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Commit | Line | Data |
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8fea2914 MT |
1 | /*- |
2 | * Copyright (c) 2007-2008, Juniper Networks, Inc. | |
3 | * All rights reserved. | |
4 | * | |
e62b5266 | 5 | * SPDX-License-Identifier: GPL-2.0 |
8fea2914 MT |
6 | */ |
7 | ||
8 | #include <common.h> | |
2b53b078 | 9 | #include <dm.h> |
7c38e90a | 10 | #include <errno.h> |
8fea2914 MT |
11 | #include <pci.h> |
12 | #include <usb.h> | |
2731b9a8 JCPV |
13 | |
14 | #include "ehci.h" | |
8fea2914 | 15 | |
2b53b078 SG |
16 | /* Information about a USB port */ |
17 | struct ehci_pci_priv { | |
18 | struct ehci_ctrl ehci; | |
19 | }; | |
20 | ||
09c5c164 SG |
21 | #ifdef CONFIG_DM_USB |
22 | ||
23 | static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, | |
24 | struct ehci_hcor **ret_hcor) | |
2b53b078 SG |
25 | { |
26 | struct ehci_hccr *hccr; | |
27 | struct ehci_hcor *hcor; | |
09c5c164 | 28 | u32 cmd; |
2b53b078 | 29 | |
09c5c164 | 30 | hccr = (struct ehci_hccr *)dm_pci_map_bar(dev, |
2b53b078 | 31 | PCI_BASE_ADDRESS_0, PCI_REGION_MEM); |
09c5c164 | 32 | hcor = (struct ehci_hcor *)((uintptr_t) hccr + |
2b53b078 SG |
33 | HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
34 | ||
35 | debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", | |
09c5c164 SG |
36 | (u32)hccr, (u32)hcor, |
37 | (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | |
2b53b078 SG |
38 | |
39 | *ret_hccr = hccr; | |
40 | *ret_hcor = hcor; | |
41 | ||
42 | /* enable busmaster */ | |
09c5c164 | 43 | dm_pci_read_config32(dev, PCI_COMMAND, &cmd); |
2b53b078 | 44 | cmd |= PCI_COMMAND_MASTER; |
09c5c164 | 45 | dm_pci_write_config32(dev, PCI_COMMAND, cmd); |
2b53b078 SG |
46 | } |
47 | ||
09c5c164 | 48 | #else |
2b53b078 | 49 | |
8fea2914 MT |
50 | #ifdef CONFIG_PCI_EHCI_DEVICE |
51 | static struct pci_device_id ehci_pci_ids[] = { | |
52 | /* Please add supported PCI EHCI controller ids here */ | |
0a5f7e1b | 53 | {0x1033, 0x00E0}, /* NEC */ |
4db2fa7f | 54 | {0x10B9, 0x5239}, /* ULI1575 PCI EHCI module ids */ |
0a5f7e1b | 55 | {0x12D8, 0x400F}, /* Pericom */ |
8fea2914 MT |
56 | {0, 0} |
57 | }; | |
58 | #endif | |
59 | ||
09c5c164 SG |
60 | static void ehci_pci_legacy_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr, |
61 | struct ehci_hcor **ret_hcor) | |
62 | { | |
63 | struct ehci_hccr *hccr; | |
64 | struct ehci_hcor *hcor; | |
65 | u32 cmd; | |
66 | ||
67 | hccr = (struct ehci_hccr *)pci_map_bar(pdev, | |
68 | PCI_BASE_ADDRESS_0, PCI_REGION_MEM); | |
69 | hcor = (struct ehci_hcor *)((uintptr_t) hccr + | |
70 | HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | |
71 | ||
72 | debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", | |
73 | (u32)hccr, (u32)hcor, | |
74 | (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | |
75 | ||
76 | *ret_hccr = hccr; | |
77 | *ret_hcor = hcor; | |
78 | ||
79 | /* enable busmaster */ | |
80 | pci_read_config_dword(pdev, PCI_COMMAND, &cmd); | |
81 | cmd |= PCI_COMMAND_MASTER; | |
82 | pci_write_config_dword(pdev, PCI_COMMAND, cmd); | |
83 | } | |
84 | ||
8fea2914 MT |
85 | /* |
86 | * Create the appropriate control structures to manage | |
87 | * a new EHCI host controller. | |
88 | */ | |
127efc4f TK |
89 | int ehci_hcd_init(int index, enum usb_init_type init, |
90 | struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) | |
8fea2914 MT |
91 | { |
92 | pci_dev_t pdev; | |
8fea2914 | 93 | |
7c38e90a | 94 | #ifdef CONFIG_PCI_EHCI_DEVICE |
8fea2914 | 95 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); |
7c38e90a | 96 | #else |
4fd46727 | 97 | pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index); |
7c38e90a VP |
98 | #endif |
99 | if (pdev < 0) { | |
8fea2914 MT |
100 | printf("EHCI host controller not found\n"); |
101 | return -1; | |
102 | } | |
09c5c164 | 103 | ehci_pci_legacy_init(pdev, ret_hccr, ret_hcor); |
8fea2914 | 104 | |
8fea2914 MT |
105 | return 0; |
106 | } | |
107 | ||
108 | /* | |
109 | * Destroy the appropriate control structures corresponding | |
110 | * the the EHCI host controller. | |
111 | */ | |
676ae068 | 112 | int ehci_hcd_stop(int index) |
8fea2914 MT |
113 | { |
114 | return 0; | |
115 | } | |
2b53b078 SG |
116 | #endif /* nCONFIG_DM_USB */ |
117 | ||
118 | #ifdef CONFIG_DM_USB | |
119 | static int ehci_pci_probe(struct udevice *dev) | |
120 | { | |
121 | struct ehci_hccr *hccr; | |
122 | struct ehci_hcor *hcor; | |
123 | ||
09c5c164 | 124 | ehci_pci_init(dev, &hccr, &hcor); |
2b53b078 SG |
125 | |
126 | return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); | |
127 | } | |
128 | ||
907eed2c SG |
129 | static const struct udevice_id ehci_pci_ids[] = { |
130 | { .compatible = "ehci-pci" }, | |
131 | { } | |
132 | }; | |
133 | ||
2b53b078 SG |
134 | U_BOOT_DRIVER(ehci_pci) = { |
135 | .name = "ehci_pci", | |
136 | .id = UCLASS_USB, | |
137 | .probe = ehci_pci_probe, | |
40527342 | 138 | .remove = ehci_deregister, |
907eed2c | 139 | .of_match = ehci_pci_ids, |
2b53b078 SG |
140 | .ops = &ehci_usb_ops, |
141 | .platdata_auto_alloc_size = sizeof(struct usb_platdata), | |
142 | .priv_auto_alloc_size = sizeof(struct ehci_pci_priv), | |
143 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
144 | }; | |
145 | ||
146 | static struct pci_device_id ehci_pci_supported[] = { | |
147 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0) }, | |
148 | {}, | |
149 | }; | |
150 | ||
151 | U_BOOT_PCI_DEVICE(ehci_pci, ehci_pci_supported); | |
152 | ||
153 | #endif /* CONFIG_DM_USB */ |