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87f938c9 | 1 | /* |
7ae18f37 | 2 | * Copyright (c) 2011 The Chromium OS Authors. |
7aaa5a60 | 3 | * Copyright (c) 2009-2015 NVIDIA Corporation |
7ae18f37 | 4 | * Copyright (c) 2013 Lucas Stach |
87f938c9 | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
87f938c9 SG |
7 | */ |
8 | ||
9 | #include <common.h> | |
c3980ad3 | 10 | #include <dm.h> |
1221ce45 | 11 | #include <linux/errno.h> |
7ae18f37 LS |
12 | #include <asm/io.h> |
13 | #include <asm-generic/gpio.h> | |
14 | #include <asm/arch/clock.h> | |
15 | #include <asm/arch-tegra/usb.h> | |
7e44d932 | 16 | #include <asm/arch-tegra/clk_rst.h> |
87f938c9 | 17 | #include <usb.h> |
7ae18f37 LS |
18 | #include <usb/ulpi.h> |
19 | #include <libfdt.h> | |
20 | #include <fdtdec.h> | |
87f938c9 SG |
21 | |
22 | #include "ehci.h" | |
87f938c9 | 23 | |
c3980ad3 SG |
24 | DECLARE_GLOBAL_DATA_PTR; |
25 | ||
7e44d932 JL |
26 | #define USB1_ADDR_MASK 0xFFFF0000 |
27 | ||
28 | #define HOSTPC1_DEVLC 0x84 | |
29 | #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) | |
30 | ||
7ae18f37 LS |
31 | #ifdef CONFIG_USB_ULPI |
32 | #ifndef CONFIG_USB_ULPI_VIEWPORT | |
33 | #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ | |
34 | define CONFIG_USB_ULPI_VIEWPORT" | |
35 | #endif | |
36 | #endif | |
37 | ||
7ae18f37 LS |
38 | /* Parameters we need for USB */ |
39 | enum { | |
40 | PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ | |
41 | PARAM_DIVM, /* PLL INPUT DIVIDER */ | |
42 | PARAM_DIVP, /* POST DIVIDER (2^N) */ | |
43 | PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ | |
44 | PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ | |
45 | PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ | |
46 | PARAM_STABLE_COUNT, /* PLL-U STABLE count */ | |
47 | PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ | |
48 | PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ | |
49 | PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ | |
50 | PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ | |
51 | ||
52 | PARAM_COUNT | |
53 | }; | |
54 | ||
55 | /* Possible port types (dual role mode) */ | |
56 | enum dr_mode { | |
57 | DR_MODE_NONE = 0, | |
58 | DR_MODE_HOST, /* supports host operation */ | |
59 | DR_MODE_DEVICE, /* supports device operation */ | |
60 | DR_MODE_OTG, /* supports both */ | |
61 | }; | |
62 | ||
27f782b6 SG |
63 | enum usb_ctlr_type { |
64 | USB_CTLR_T20, | |
65 | USB_CTLR_T30, | |
66 | USB_CTLR_T114, | |
7aaa5a60 | 67 | USB_CTLR_T210, |
27f782b6 SG |
68 | |
69 | USB_CTRL_COUNT, | |
70 | }; | |
71 | ||
7ae18f37 LS |
72 | /* Information about a USB port */ |
73 | struct fdt_usb { | |
c3980ad3 | 74 | struct ehci_ctrl ehci; |
7ae18f37 LS |
75 | struct usb_ctlr *reg; /* address of registers in physical memory */ |
76 | unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ | |
77 | unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ | |
78 | unsigned enabled:1; /* 1 to enable, 0 to disable */ | |
79 | unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ | |
27f782b6 | 80 | enum usb_ctlr_type type; |
a4539a2a | 81 | enum usb_init_type init_type; |
7ae18f37 LS |
82 | enum dr_mode dr_mode; /* dual role mode */ |
83 | enum periph_id periph_id;/* peripheral id */ | |
46927e1e SG |
84 | struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ |
85 | struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ | |
7ae18f37 LS |
86 | }; |
87 | ||
7ae18f37 LS |
88 | /* |
89 | * This table has USB timing parameters for each Oscillator frequency we | |
90 | * support. There are four sets of values: | |
91 | * | |
92 | * 1. PLLU configuration information (reference clock is osc/clk_m and | |
93 | * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). | |
94 | * | |
95 | * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz | |
96 | * ---------------------------------------------------------------------- | |
97 | * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) | |
98 | * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) | |
99 | * Filter frequency (MHz) 1 4.8 6 2 | |
100 | * CPCON 1100b 0011b 1100b 1100b | |
101 | * LFCON0 0 0 0 0 | |
102 | * | |
103 | * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: | |
104 | * | |
105 | * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz | |
106 | * --------------------------------------------------------------------------- | |
107 | * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) | |
108 | * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) | |
109 | * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) | |
110 | * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) | |
111 | * | |
112 | * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and | |
113 | * SessEnd. Each of these signals have their own debouncer and for each of | |
114 | * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or | |
115 | * BIAS_DEBOUNCE_B). | |
116 | * | |
117 | * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: | |
118 | * 0xffff -> No debouncing at all | |
119 | * <n> ms = <n> *1000 / (1/19.2MHz) / 4 | |
120 | * | |
121 | * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: | |
122 | * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 | |
123 | * | |
124 | * We need to use only DebounceA for BOOTROM. We don't need the DebounceB | |
125 | * values, so we can keep those to default. | |
126 | * | |
127 | * 4. The 20 microsecond delay after bias cell operation. | |
128 | */ | |
7e44d932 | 129 | static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { |
7ae18f37 LS |
130 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ |
131 | { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, | |
132 | { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, | |
133 | { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, | |
3e8650c0 TW |
134 | { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, |
135 | { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, | |
136 | { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } | |
7ae18f37 LS |
137 | }; |
138 | ||
7e44d932 JL |
139 | static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { |
140 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ | |
141 | { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, | |
142 | { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, | |
143 | { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, | |
3e8650c0 TW |
144 | { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, |
145 | { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, | |
146 | { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } | |
7e44d932 JL |
147 | }; |
148 | ||
149 | static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { | |
150 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ | |
151 | { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, | |
152 | { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, | |
153 | { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, | |
3e8650c0 TW |
154 | { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 }, |
155 | { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, | |
156 | { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } | |
7e44d932 JL |
157 | }; |
158 | ||
7aaa5a60 TW |
159 | /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ |
160 | static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { | |
161 | /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ | |
3e8650c0 | 162 | { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, |
7aaa5a60 TW |
163 | { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, |
164 | { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, | |
3e8650c0 TW |
165 | { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }, |
166 | { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, | |
167 | { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 } | |
7aaa5a60 TW |
168 | }; |
169 | ||
7ae18f37 LS |
170 | /* UTMIP Idle Wait Delay */ |
171 | static const u8 utmip_idle_wait_delay = 17; | |
172 | ||
173 | /* UTMIP Elastic limit */ | |
174 | static const u8 utmip_elastic_limit = 16; | |
175 | ||
176 | /* UTMIP High Speed Sync Start Delay */ | |
177 | static const u8 utmip_hs_sync_start_delay = 9; | |
87f938c9 | 178 | |
7e44d932 | 179 | struct fdt_usb_controller { |
7e44d932 JL |
180 | /* flag to determine whether controller supports hostpc register */ |
181 | u32 has_hostpc:1; | |
182 | const unsigned *pll_parameter; | |
183 | }; | |
184 | ||
27f782b6 | 185 | static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { |
7e44d932 | 186 | { |
7e44d932 JL |
187 | .has_hostpc = 0, |
188 | .pll_parameter = (const unsigned *)T20_usb_pll, | |
189 | }, | |
190 | { | |
7e44d932 JL |
191 | .has_hostpc = 1, |
192 | .pll_parameter = (const unsigned *)T30_usb_pll, | |
193 | }, | |
194 | { | |
7e44d932 JL |
195 | .has_hostpc = 1, |
196 | .pll_parameter = (const unsigned *)T114_usb_pll, | |
197 | }, | |
7aaa5a60 TW |
198 | { |
199 | .has_hostpc = 1, | |
200 | .pll_parameter = (const unsigned *)T210_usb_pll, | |
201 | }, | |
7e44d932 JL |
202 | }; |
203 | ||
8b3f7bf7 JL |
204 | /* |
205 | * A known hardware issue where Connect Status Change bit of PORTSC register | |
206 | * of USB1 controller will be set after Port Reset. | |
207 | * We have to clear it in order for later device enumeration to proceed. | |
8b3f7bf7 | 208 | */ |
deb8508c SG |
209 | static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, |
210 | uint32_t *status_reg, uint32_t *reg) | |
8b3f7bf7 | 211 | { |
56d42730 SG |
212 | struct fdt_usb *config = ctrl->priv; |
213 | struct fdt_usb_controller *controller; | |
214 | ||
215 | controller = &fdt_usb_controllers[config->type]; | |
8b3f7bf7 | 216 | mdelay(50); |
7e44d932 JL |
217 | /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ |
218 | if (controller->has_hostpc) | |
219 | *reg |= EHCI_PS_PE; | |
220 | ||
943104f0 | 221 | if (!config->has_legacy_mode) |
8b3f7bf7 JL |
222 | return; |
223 | /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ | |
224 | if (ehci_readl(status_reg) & EHCI_PS_CSC) | |
225 | *reg |= EHCI_PS_CSC; | |
226 | } | |
87f938c9 | 227 | |
deb8508c | 228 | static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) |
7e44d932 | 229 | { |
11d18a19 | 230 | struct fdt_usb *config = ctrl->priv; |
7e44d932 JL |
231 | struct usb_ctlr *usbctlr; |
232 | uint32_t tmp; | |
233 | ||
7e44d932 JL |
234 | usbctlr = config->reg; |
235 | ||
236 | tmp = ehci_readl(&usbctlr->usb_mode); | |
237 | tmp |= USBMODE_CM_HC; | |
238 | ehci_writel(&usbctlr->usb_mode, tmp); | |
239 | } | |
240 | ||
deb8508c | 241 | static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) |
7e44d932 | 242 | { |
56d42730 SG |
243 | struct fdt_usb *config = ctrl->priv; |
244 | struct fdt_usb_controller *controller; | |
7e44d932 JL |
245 | uint32_t tmp; |
246 | uint32_t *reg_ptr; | |
247 | ||
56d42730 | 248 | controller = &fdt_usb_controllers[config->type]; |
7e44d932 | 249 | if (controller->has_hostpc) { |
7338287d SG |
250 | reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + |
251 | HOSTPC1_DEVLC); | |
7e44d932 JL |
252 | tmp = ehci_readl(reg_ptr); |
253 | return HOSTPC1_PSPD(tmp); | |
254 | } else | |
255 | return PORTSC_PSPD(reg); | |
256 | } | |
257 | ||
a4539a2a SW |
258 | /* Set up VBUS for host/device mode */ |
259 | static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) | |
7ae18f37 LS |
260 | { |
261 | /* | |
a4539a2a SW |
262 | * If we are an OTG port initializing in host mode, |
263 | * check if remote host is driving VBus and bail out in this case. | |
7ae18f37 | 264 | */ |
a4539a2a SW |
265 | if (init == USB_INIT_HOST && |
266 | config->dr_mode == DR_MODE_OTG && | |
267 | (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { | |
268 | printf("tegrausb: VBUS input active; not enabling as host\n"); | |
7ae18f37 | 269 | return; |
a4539a2a | 270 | } |
7ae18f37 | 271 | |
46927e1e | 272 | if (dm_gpio_is_valid(&config->vbus_gpio)) { |
a4539a2a SW |
273 | int vbus_value; |
274 | ||
46927e1e SG |
275 | vbus_value = (init == USB_INIT_HOST); |
276 | dm_gpio_set_value(&config->vbus_gpio, vbus_value); | |
a4539a2a | 277 | |
46927e1e SG |
278 | debug("set_up_vbus: GPIO %d %d\n", |
279 | gpio_get_number(&config->vbus_gpio), vbus_value); | |
7ae18f37 LS |
280 | } |
281 | } | |
282 | ||
7e27bdda SG |
283 | static void usbf_reset_controller(struct fdt_usb *config, |
284 | struct usb_ctlr *usbctlr) | |
7ae18f37 LS |
285 | { |
286 | /* Reset the USB controller with 2us delay */ | |
287 | reset_periph(config->periph_id, 2); | |
288 | ||
289 | /* | |
290 | * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under | |
291 | * base address | |
292 | */ | |
293 | if (config->has_legacy_mode) | |
294 | setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); | |
295 | ||
296 | /* Put UTMIP1/3 in reset */ | |
297 | setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); | |
298 | ||
299 | /* Enable the UTMIP PHY */ | |
300 | if (config->utmi) | |
301 | setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); | |
302 | } | |
303 | ||
27f782b6 | 304 | static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) |
7e44d932 JL |
305 | { |
306 | const unsigned *timing; | |
307 | ||
308 | timing = controller->pll_parameter + | |
309 | clock_get_osc_freq() * PARAM_COUNT; | |
310 | ||
311 | return timing; | |
312 | } | |
313 | ||
2d34151f | 314 | /* select the PHY to use with a USB controller */ |
a4539a2a SW |
315 | static void init_phy_mux(struct fdt_usb *config, uint pts, |
316 | enum usb_init_type init) | |
2d34151f SW |
317 | { |
318 | struct usb_ctlr *usbctlr = config->reg; | |
319 | ||
320 | #if defined(CONFIG_TEGRA20) | |
321 | if (config->periph_id == PERIPH_ID_USBD) { | |
322 | clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, | |
d1fcbae1 | 323 | pts << PTS1_SHIFT); |
2d34151f SW |
324 | clrbits_le32(&usbctlr->port_sc1, STS1); |
325 | } else { | |
326 | clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, | |
d1fcbae1 | 327 | pts << PTS_SHIFT); |
2d34151f SW |
328 | clrbits_le32(&usbctlr->port_sc1, STS); |
329 | } | |
330 | #else | |
a4539a2a | 331 | /* Set to Host mode (if applicable) after Controller Reset was done */ |
2d34151f | 332 | clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, |
a4539a2a SW |
333 | (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); |
334 | /* | |
335 | * Select PHY interface after setting host mode. | |
336 | * For device mode, the ordering requirement is not an issue, since | |
337 | * only the first USB controller supports device mode, and that USB | |
338 | * controller can only talk to a UTMI PHY, so the PHY selection is | |
339 | * already made at reset time, so this write is a no-op. | |
340 | */ | |
2d34151f SW |
341 | clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, |
342 | pts << PTS_SHIFT); | |
343 | clrbits_le32(&usbctlr->hostpc1_devlc, STS); | |
344 | #endif | |
345 | } | |
346 | ||
7ae18f37 | 347 | /* set up the UTMI USB controller with the parameters provided */ |
a4539a2a SW |
348 | static int init_utmi_usb_controller(struct fdt_usb *config, |
349 | enum usb_init_type init) | |
7ae18f37 | 350 | { |
27f782b6 | 351 | struct fdt_usb_controller *controller; |
a4539a2a | 352 | u32 b_sess_valid_mask, val; |
7ae18f37 LS |
353 | int loop_count; |
354 | const unsigned *timing; | |
355 | struct usb_ctlr *usbctlr = config->reg; | |
7e44d932 JL |
356 | struct clk_rst_ctlr *clkrst; |
357 | struct usb_ctlr *usb1ctlr; | |
7ae18f37 LS |
358 | |
359 | clock_enable(config->periph_id); | |
360 | ||
361 | /* Reset the usb controller */ | |
362 | usbf_reset_controller(config, usbctlr); | |
363 | ||
364 | /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ | |
365 | clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); | |
366 | ||
367 | /* Follow the crystal clock disable by >100ns delay */ | |
368 | udelay(1); | |
369 | ||
a4539a2a SW |
370 | b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); |
371 | clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, | |
372 | (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); | |
373 | ||
7ae18f37 LS |
374 | /* |
375 | * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP | |
376 | * mux must be switched to actually use a_sess_vld threshold. | |
377 | */ | |
7e44d932 | 378 | if (config->dr_mode == DR_MODE_OTG && |
46927e1e | 379 | dm_gpio_is_valid(&config->vbus_gpio)) |
7ae18f37 LS |
380 | clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, |
381 | VBUS_SENSE_CTL_MASK, | |
382 | VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); | |
7ae18f37 | 383 | |
27f782b6 SG |
384 | controller = &fdt_usb_controllers[config->type]; |
385 | debug("controller=%p, type=%d\n", controller, config->type); | |
386 | ||
7ae18f37 LS |
387 | /* |
388 | * PLL Delay CONFIGURATION settings. The following parameters control | |
389 | * the bring up of the plls. | |
390 | */ | |
27f782b6 | 391 | timing = get_pll_timing(controller); |
7e44d932 JL |
392 | |
393 | if (!controller->has_hostpc) { | |
394 | val = readl(&usbctlr->utmip_misc_cfg1); | |
395 | clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, | |
396 | timing[PARAM_STABLE_COUNT] << | |
397 | UTMIP_PLLU_STABLE_COUNT_SHIFT); | |
398 | clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, | |
399 | timing[PARAM_ACTIVE_DELAY_COUNT] << | |
400 | UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); | |
401 | writel(val, &usbctlr->utmip_misc_cfg1); | |
402 | ||
403 | /* Set PLL enable delay count and crystal frequency count */ | |
404 | val = readl(&usbctlr->utmip_pll_cfg1); | |
405 | clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, | |
406 | timing[PARAM_ENABLE_DELAY_COUNT] << | |
407 | UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); | |
408 | clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, | |
409 | timing[PARAM_XTAL_FREQ_COUNT] << | |
410 | UTMIP_XTAL_FREQ_COUNT_SHIFT); | |
411 | writel(val, &usbctlr->utmip_pll_cfg1); | |
412 | } else { | |
413 | clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
414 | ||
415 | val = readl(&clkrst->crc_utmip_pll_cfg2); | |
416 | clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, | |
417 | timing[PARAM_STABLE_COUNT] << | |
418 | UTMIP_PLLU_STABLE_COUNT_SHIFT); | |
419 | clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, | |
420 | timing[PARAM_ACTIVE_DELAY_COUNT] << | |
421 | UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); | |
422 | writel(val, &clkrst->crc_utmip_pll_cfg2); | |
423 | ||
424 | /* Set PLL enable delay count and crystal frequency count */ | |
425 | val = readl(&clkrst->crc_utmip_pll_cfg1); | |
426 | clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, | |
427 | timing[PARAM_ENABLE_DELAY_COUNT] << | |
428 | UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); | |
429 | clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, | |
430 | timing[PARAM_XTAL_FREQ_COUNT] << | |
431 | UTMIP_XTAL_FREQ_COUNT_SHIFT); | |
432 | writel(val, &clkrst->crc_utmip_pll_cfg1); | |
433 | ||
434 | /* Disable Power Down state for PLL */ | |
435 | clrbits_le32(&clkrst->crc_utmip_pll_cfg1, | |
436 | PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | | |
437 | PLL_ACTIVE_POWERDOWN); | |
438 | ||
439 | /* Recommended PHY settings for EYE diagram */ | |
440 | val = readl(&usbctlr->utmip_xcvr_cfg0); | |
441 | clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, | |
442 | 0x4 << UTMIP_XCVR_SETUP_SHIFT); | |
443 | clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, | |
444 | 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); | |
445 | clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, | |
446 | 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); | |
447 | writel(val, &usbctlr->utmip_xcvr_cfg0); | |
448 | clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, | |
449 | UTMIP_XCVR_TERM_RANGE_ADJ_MASK, | |
450 | 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); | |
451 | ||
452 | /* Some registers can be controlled from USB1 only. */ | |
453 | if (config->periph_id != PERIPH_ID_USBD) { | |
454 | clock_enable(PERIPH_ID_USBD); | |
455 | /* Disable Reset if in Reset state */ | |
456 | reset_set_enable(PERIPH_ID_USBD, 0); | |
457 | } | |
458 | usb1ctlr = (struct usb_ctlr *) | |
96df9c7e | 459 | ((unsigned long)config->reg & USB1_ADDR_MASK); |
7e44d932 JL |
460 | val = readl(&usb1ctlr->utmip_bias_cfg0); |
461 | setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); | |
462 | clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, | |
463 | 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); | |
464 | clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, | |
465 | 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); | |
466 | writel(val, &usb1ctlr->utmip_bias_cfg0); | |
467 | ||
468 | /* Miscellaneous setting mentioned in Programming Guide */ | |
469 | clrbits_le32(&usbctlr->utmip_misc_cfg0, | |
470 | UTMIP_SUSPEND_EXIT_ON_EDGE); | |
471 | } | |
7ae18f37 LS |
472 | |
473 | /* Setting the tracking length time */ | |
474 | clrsetbits_le32(&usbctlr->utmip_bias_cfg1, | |
475 | UTMIP_BIAS_PDTRK_COUNT_MASK, | |
476 | timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); | |
477 | ||
478 | /* Program debounce time for VBUS to become valid */ | |
479 | clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, | |
480 | UTMIP_DEBOUNCE_CFG0_MASK, | |
481 | timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); | |
482 | ||
7aaa5a60 TW |
483 | if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) { |
484 | clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, | |
485 | UTMIP_DEBOUNCE_CFG0_MASK, | |
486 | (timing[PARAM_DEBOUNCE_A_TIME] >> 1) | |
487 | << UTMIP_DEBOUNCE_CFG0_SHIFT); | |
488 | clrsetbits_le32(&usbctlr->utmip_bias_cfg1, | |
489 | UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK, | |
490 | 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT); | |
491 | } | |
492 | ||
7ae18f37 LS |
493 | setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); |
494 | ||
495 | /* Disable battery charge enabling bit */ | |
496 | setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); | |
497 | ||
498 | clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); | |
499 | setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); | |
500 | ||
501 | /* | |
502 | * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT | |
503 | * Setting these fields, together with default values of the | |
504 | * other fields, results in programming the registers below as | |
505 | * follows: | |
506 | * UTMIP_HSRX_CFG0 = 0x9168c000 | |
507 | * UTMIP_HSRX_CFG1 = 0x13 | |
508 | */ | |
509 | ||
510 | /* Set PLL enable delay count and Crystal frequency count */ | |
511 | val = readl(&usbctlr->utmip_hsrx_cfg0); | |
512 | clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, | |
513 | utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); | |
514 | clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, | |
515 | utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); | |
516 | writel(val, &usbctlr->utmip_hsrx_cfg0); | |
517 | ||
518 | /* Configure the UTMIP_HS_SYNC_START_DLY */ | |
519 | clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, | |
520 | UTMIP_HS_SYNC_START_DLY_MASK, | |
521 | utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); | |
522 | ||
523 | /* Preceed the crystal clock disable by >100ns delay. */ | |
524 | udelay(1); | |
525 | ||
526 | /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ | |
527 | setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); | |
528 | ||
7e44d932 JL |
529 | if (controller->has_hostpc) { |
530 | if (config->periph_id == PERIPH_ID_USBD) | |
531 | clrbits_le32(&clkrst->crc_utmip_pll_cfg2, | |
532 | UTMIP_FORCE_PD_SAMP_A_POWERDOWN); | |
b03f4b37 SA |
533 | if (config->periph_id == PERIPH_ID_USB2) |
534 | clrbits_le32(&clkrst->crc_utmip_pll_cfg2, | |
535 | UTMIP_FORCE_PD_SAMP_B_POWERDOWN); | |
7e44d932 JL |
536 | if (config->periph_id == PERIPH_ID_USB3) |
537 | clrbits_le32(&clkrst->crc_utmip_pll_cfg2, | |
538 | UTMIP_FORCE_PD_SAMP_C_POWERDOWN); | |
539 | } | |
7ae18f37 LS |
540 | /* Finished the per-controller init. */ |
541 | ||
542 | /* De-assert UTMIP_RESET to bring out of reset. */ | |
543 | clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); | |
544 | ||
545 | /* Wait for the phy clock to become valid in 100 ms */ | |
546 | for (loop_count = 100000; loop_count != 0; loop_count--) { | |
547 | if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) | |
548 | break; | |
549 | udelay(1); | |
550 | } | |
551 | if (!loop_count) | |
7e27bdda | 552 | return -ETIMEDOUT; |
7ae18f37 LS |
553 | |
554 | /* Disable ICUSB FS/LS transceiver */ | |
555 | clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); | |
556 | ||
557 | /* Select UTMI parallel interface */ | |
a4539a2a | 558 | init_phy_mux(config, PTS_UTMI, init); |
7ae18f37 LS |
559 | |
560 | /* Deassert power down state */ | |
561 | clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | | |
562 | UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); | |
563 | clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | | |
564 | UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); | |
565 | ||
7e44d932 JL |
566 | if (controller->has_hostpc) { |
567 | /* | |
568 | * BIAS Pad Power Down is common among all 3 USB | |
569 | * controllers and can be controlled from USB1 only. | |
570 | */ | |
571 | usb1ctlr = (struct usb_ctlr *) | |
96df9c7e | 572 | ((unsigned long)config->reg & USB1_ADDR_MASK); |
7e44d932 JL |
573 | clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); |
574 | udelay(25); | |
575 | clrbits_le32(&usb1ctlr->utmip_bias_cfg1, | |
576 | UTMIP_FORCE_PDTRK_POWERDOWN); | |
577 | } | |
7ae18f37 LS |
578 | return 0; |
579 | } | |
580 | ||
581 | #ifdef CONFIG_USB_ULPI | |
582 | /* if board file does not set a ULPI reference frequency we default to 24MHz */ | |
583 | #ifndef CONFIG_ULPI_REF_CLK | |
584 | #define CONFIG_ULPI_REF_CLK 24000000 | |
585 | #endif | |
586 | ||
587 | /* set up the ULPI USB controller with the parameters provided */ | |
a4539a2a SW |
588 | static int init_ulpi_usb_controller(struct fdt_usb *config, |
589 | enum usb_init_type init) | |
7ae18f37 LS |
590 | { |
591 | u32 val; | |
592 | int loop_count; | |
593 | struct ulpi_viewport ulpi_vp; | |
594 | struct usb_ctlr *usbctlr = config->reg; | |
7e27bdda | 595 | int ret; |
7ae18f37 LS |
596 | |
597 | /* set up ULPI reference clock on pllp_out4 */ | |
598 | clock_enable(PERIPH_ID_DEV2_OUT); | |
599 | clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); | |
600 | ||
601 | /* reset ULPI phy */ | |
46927e1e SG |
602 | if (dm_gpio_is_valid(&config->phy_reset_gpio)) { |
603 | dm_gpio_set_value(&config->phy_reset_gpio, 0); | |
7ae18f37 | 604 | mdelay(5); |
46927e1e | 605 | dm_gpio_set_value(&config->phy_reset_gpio, 1); |
7ae18f37 LS |
606 | } |
607 | ||
608 | /* Reset the usb controller */ | |
609 | clock_enable(config->periph_id); | |
610 | usbf_reset_controller(config, usbctlr); | |
611 | ||
612 | /* enable pinmux bypass */ | |
613 | setbits_le32(&usbctlr->ulpi_timing_ctrl_0, | |
614 | ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); | |
615 | ||
616 | /* Select ULPI parallel interface */ | |
a4539a2a | 617 | init_phy_mux(config, PTS_ULPI, init); |
7ae18f37 LS |
618 | |
619 | /* enable ULPI transceiver */ | |
620 | setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); | |
621 | ||
622 | /* configure ULPI transceiver timings */ | |
623 | val = 0; | |
624 | writel(val, &usbctlr->ulpi_timing_ctrl_1); | |
625 | ||
626 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
627 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
628 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
629 | writel(val, &usbctlr->ulpi_timing_ctrl_1); | |
630 | udelay(10); | |
631 | ||
632 | val |= ULPI_DATA_TRIMMER_LOAD; | |
633 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
634 | val |= ULPI_DIR_TRIMMER_LOAD; | |
635 | writel(val, &usbctlr->ulpi_timing_ctrl_1); | |
636 | ||
637 | /* set up phy for host operation with external vbus supply */ | |
638 | ulpi_vp.port_num = 0; | |
639 | ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; | |
640 | ||
7e27bdda SG |
641 | ret = ulpi_init(&ulpi_vp); |
642 | if (ret) { | |
7ae18f37 | 643 | printf("Tegra ULPI viewport init failed\n"); |
7e27bdda | 644 | return ret; |
7ae18f37 LS |
645 | } |
646 | ||
647 | ulpi_set_vbus(&ulpi_vp, 1, 1); | |
648 | ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); | |
649 | ||
650 | /* enable wakeup events */ | |
651 | setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); | |
652 | ||
653 | /* Enable and wait for the phy clock to become valid in 100 ms */ | |
654 | setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); | |
655 | for (loop_count = 100000; loop_count != 0; loop_count--) { | |
656 | if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) | |
657 | break; | |
658 | udelay(1); | |
659 | } | |
660 | if (!loop_count) | |
7e27bdda | 661 | return -ETIMEDOUT; |
7ae18f37 LS |
662 | clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); |
663 | ||
664 | return 0; | |
665 | } | |
666 | #else | |
a4539a2a SW |
667 | static int init_ulpi_usb_controller(struct fdt_usb *config, |
668 | enum usb_init_type init) | |
7ae18f37 LS |
669 | { |
670 | printf("No code to set up ULPI controller, please enable" | |
671 | "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); | |
7e27bdda | 672 | return -ENOSYS; |
7ae18f37 LS |
673 | } |
674 | #endif | |
675 | ||
676 | static void config_clock(const u32 timing[]) | |
677 | { | |
7aaa5a60 TW |
678 | debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n", |
679 | __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], | |
680 | timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); | |
681 | ||
7ae18f37 LS |
682 | clock_start_pll(CLOCK_ID_USB, |
683 | timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], | |
684 | timing[PARAM_CPCON], timing[PARAM_LFCON]); | |
685 | } | |
686 | ||
4e9838c1 | 687 | static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config) |
7ae18f37 | 688 | { |
4e9838c1 SG |
689 | const void *blob = gd->fdt_blob; |
690 | int node = dev->of_offset; | |
7ae18f37 LS |
691 | const char *phy, *mode; |
692 | ||
4e9838c1 | 693 | config->reg = (struct usb_ctlr *)dev_get_addr(dev); |
7ae18f37 LS |
694 | mode = fdt_getprop(blob, node, "dr_mode", NULL); |
695 | if (mode) { | |
696 | if (0 == strcmp(mode, "host")) | |
697 | config->dr_mode = DR_MODE_HOST; | |
698 | else if (0 == strcmp(mode, "peripheral")) | |
699 | config->dr_mode = DR_MODE_DEVICE; | |
700 | else if (0 == strcmp(mode, "otg")) | |
701 | config->dr_mode = DR_MODE_OTG; | |
702 | else { | |
703 | debug("%s: Cannot decode dr_mode '%s'\n", __func__, | |
704 | mode); | |
7e27bdda | 705 | return -EINVAL; |
7ae18f37 LS |
706 | } |
707 | } else { | |
708 | config->dr_mode = DR_MODE_HOST; | |
709 | } | |
710 | ||
711 | phy = fdt_getprop(blob, node, "phy_type", NULL); | |
712 | config->utmi = phy && 0 == strcmp("utmi", phy); | |
713 | config->ulpi = phy && 0 == strcmp("ulpi", phy); | |
714 | config->enabled = fdtdec_get_is_enabled(blob, node); | |
715 | config->has_legacy_mode = fdtdec_get_bool(blob, node, | |
716 | "nvidia,has-legacy-mode"); | |
717 | config->periph_id = clock_decode_periph_id(blob, node); | |
718 | if (config->periph_id == PERIPH_ID_NONE) { | |
719 | debug("%s: Missing/invalid peripheral ID\n", __func__); | |
7e27bdda | 720 | return -EINVAL; |
7ae18f37 | 721 | } |
46927e1e SG |
722 | gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, |
723 | &config->vbus_gpio, GPIOD_IS_OUT); | |
724 | gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, | |
725 | &config->phy_reset_gpio, GPIOD_IS_OUT); | |
7ae18f37 LS |
726 | debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " |
727 | "vbus=%d, phy_reset=%d, dr_mode=%d\n", | |
728 | config->enabled, config->has_legacy_mode, config->utmi, | |
46927e1e SG |
729 | config->ulpi, config->periph_id, |
730 | gpio_get_number(&config->vbus_gpio), | |
731 | gpio_get_number(&config->phy_reset_gpio), config->dr_mode); | |
7ae18f37 LS |
732 | |
733 | return 0; | |
734 | } | |
735 | ||
ddb9a502 SG |
736 | int usb_common_init(struct fdt_usb *config, enum usb_init_type init) |
737 | { | |
738 | int ret = 0; | |
739 | ||
740 | switch (init) { | |
741 | case USB_INIT_HOST: | |
742 | switch (config->dr_mode) { | |
743 | case DR_MODE_HOST: | |
744 | case DR_MODE_OTG: | |
745 | break; | |
746 | default: | |
747 | printf("tegrausb: Invalid dr_mode %d for host mode\n", | |
748 | config->dr_mode); | |
749 | return -1; | |
750 | } | |
751 | break; | |
752 | case USB_INIT_DEVICE: | |
753 | if (config->periph_id != PERIPH_ID_USBD) { | |
754 | printf("tegrausb: Device mode only supported on first USB controller\n"); | |
755 | return -1; | |
756 | } | |
757 | if (!config->utmi) { | |
758 | printf("tegrausb: Device mode only supported with UTMI PHY\n"); | |
759 | return -1; | |
760 | } | |
761 | switch (config->dr_mode) { | |
762 | case DR_MODE_DEVICE: | |
763 | case DR_MODE_OTG: | |
764 | break; | |
765 | default: | |
766 | printf("tegrausb: Invalid dr_mode %d for device mode\n", | |
767 | config->dr_mode); | |
768 | return -1; | |
769 | } | |
770 | break; | |
771 | default: | |
772 | printf("tegrausb: Unknown USB_INIT_* %d\n", init); | |
773 | return -1; | |
774 | } | |
775 | ||
ddb9a502 SG |
776 | debug("%d, %d\n", config->utmi, config->ulpi); |
777 | if (config->utmi) | |
778 | ret = init_utmi_usb_controller(config, init); | |
779 | else if (config->ulpi) | |
780 | ret = init_ulpi_usb_controller(config, init); | |
781 | if (ret) | |
782 | return ret; | |
783 | ||
784 | set_up_vbus(config, init); | |
785 | ||
786 | config->init_type = init; | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
791 | void usb_common_uninit(struct fdt_usb *priv) | |
792 | { | |
793 | struct usb_ctlr *usbctlr; | |
794 | ||
795 | usbctlr = priv->reg; | |
796 | ||
797 | /* Stop controller */ | |
798 | writel(0, &usbctlr->usb_cmd); | |
799 | udelay(1000); | |
800 | ||
801 | /* Initiate controller reset */ | |
802 | writel(2, &usbctlr->usb_cmd); | |
803 | udelay(1000); | |
804 | } | |
805 | ||
deb8508c SG |
806 | static const struct ehci_ops tegra_ehci_ops = { |
807 | .set_usb_mode = tegra_ehci_set_usbmode, | |
808 | .get_port_speed = tegra_ehci_get_port_speed, | |
809 | .powerup_fixup = tegra_ehci_powerup_fixup, | |
810 | }; | |
811 | ||
c3980ad3 SG |
812 | static int ehci_usb_ofdata_to_platdata(struct udevice *dev) |
813 | { | |
814 | struct fdt_usb *priv = dev_get_priv(dev); | |
815 | int ret; | |
816 | ||
4e9838c1 | 817 | ret = fdt_decode_usb(dev, priv); |
c3980ad3 SG |
818 | if (ret) |
819 | return ret; | |
820 | ||
821 | priv->type = dev_get_driver_data(dev); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
826 | static int ehci_usb_probe(struct udevice *dev) | |
827 | { | |
828 | struct usb_platdata *plat = dev_get_platdata(dev); | |
829 | struct fdt_usb *priv = dev_get_priv(dev); | |
830 | struct ehci_hccr *hccr; | |
831 | struct ehci_hcor *hcor; | |
832 | static bool clk_done; | |
833 | int ret; | |
834 | ||
835 | ret = usb_common_init(priv, plat->init_type); | |
836 | if (ret) | |
837 | return ret; | |
838 | hccr = (struct ehci_hccr *)&priv->reg->cap_length; | |
839 | hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; | |
840 | if (!clk_done) { | |
841 | config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); | |
842 | clk_done = true; | |
843 | } | |
844 | ||
845 | return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, | |
846 | plat->init_type); | |
847 | } | |
848 | ||
c3980ad3 SG |
849 | static const struct udevice_id ehci_usb_ids[] = { |
850 | { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, | |
851 | { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, | |
852 | { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, | |
7aaa5a60 | 853 | { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 }, |
c3980ad3 SG |
854 | { } |
855 | }; | |
856 | ||
857 | U_BOOT_DRIVER(usb_ehci) = { | |
858 | .name = "ehci_tegra", | |
859 | .id = UCLASS_USB, | |
860 | .of_match = ehci_usb_ids, | |
861 | .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, | |
862 | .probe = ehci_usb_probe, | |
40527342 | 863 | .remove = ehci_deregister, |
c3980ad3 SG |
864 | .ops = &ehci_usb_ops, |
865 | .platdata_auto_alloc_size = sizeof(struct usb_platdata), | |
866 | .priv_auto_alloc_size = sizeof(struct fdt_usb), | |
867 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
868 | }; |