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87f938c9 | 1 | /* |
7ae18f37 | 2 | * Copyright (c) 2011 The Chromium OS Authors. |
7e44d932 | 3 | * Copyright (c) 2009-2013 NVIDIA Corporation |
7ae18f37 | 4 | * Copyright (c) 2013 Lucas Stach |
87f938c9 | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
87f938c9 SG |
7 | */ |
8 | ||
9 | #include <common.h> | |
7ae18f37 LS |
10 | #include <asm/errno.h> |
11 | #include <asm/io.h> | |
12 | #include <asm-generic/gpio.h> | |
13 | #include <asm/arch/clock.h> | |
14 | #include <asm/arch-tegra/usb.h> | |
7e44d932 | 15 | #include <asm/arch-tegra/clk_rst.h> |
87f938c9 | 16 | #include <usb.h> |
7ae18f37 LS |
17 | #include <usb/ulpi.h> |
18 | #include <libfdt.h> | |
19 | #include <fdtdec.h> | |
87f938c9 SG |
20 | |
21 | #include "ehci.h" | |
87f938c9 | 22 | |
7e44d932 JL |
23 | #define USB1_ADDR_MASK 0xFFFF0000 |
24 | ||
25 | #define HOSTPC1_DEVLC 0x84 | |
26 | #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) | |
27 | ||
7ae18f37 LS |
28 | #ifdef CONFIG_USB_ULPI |
29 | #ifndef CONFIG_USB_ULPI_VIEWPORT | |
30 | #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ | |
31 | define CONFIG_USB_ULPI_VIEWPORT" | |
32 | #endif | |
33 | #endif | |
34 | ||
35 | enum { | |
36 | USB_PORTS_MAX = 3, /* Maximum ports we allow */ | |
37 | }; | |
38 | ||
39 | /* Parameters we need for USB */ | |
40 | enum { | |
41 | PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ | |
42 | PARAM_DIVM, /* PLL INPUT DIVIDER */ | |
43 | PARAM_DIVP, /* POST DIVIDER (2^N) */ | |
44 | PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ | |
45 | PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ | |
46 | PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ | |
47 | PARAM_STABLE_COUNT, /* PLL-U STABLE count */ | |
48 | PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ | |
49 | PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ | |
50 | PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ | |
51 | PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ | |
52 | ||
53 | PARAM_COUNT | |
54 | }; | |
55 | ||
56 | /* Possible port types (dual role mode) */ | |
57 | enum dr_mode { | |
58 | DR_MODE_NONE = 0, | |
59 | DR_MODE_HOST, /* supports host operation */ | |
60 | DR_MODE_DEVICE, /* supports device operation */ | |
61 | DR_MODE_OTG, /* supports both */ | |
62 | }; | |
63 | ||
64 | /* Information about a USB port */ | |
65 | struct fdt_usb { | |
66 | struct usb_ctlr *reg; /* address of registers in physical memory */ | |
67 | unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ | |
68 | unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ | |
69 | unsigned enabled:1; /* 1 to enable, 0 to disable */ | |
70 | unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ | |
71 | unsigned initialized:1; /* has this port already been initialized? */ | |
a4539a2a | 72 | enum usb_init_type init_type; |
7ae18f37 LS |
73 | enum dr_mode dr_mode; /* dual role mode */ |
74 | enum periph_id periph_id;/* peripheral id */ | |
46927e1e SG |
75 | struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ |
76 | struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ | |
7ae18f37 LS |
77 | }; |
78 | ||
79 | static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ | |
80 | static unsigned port_count; /* Number of available ports */ | |
7e44d932 JL |
81 | /* Port that needs to clear CSC after Port Reset */ |
82 | static u32 port_addr_clear_csc; | |
7ae18f37 LS |
83 | |
84 | /* | |
85 | * This table has USB timing parameters for each Oscillator frequency we | |
86 | * support. There are four sets of values: | |
87 | * | |
88 | * 1. PLLU configuration information (reference clock is osc/clk_m and | |
89 | * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). | |
90 | * | |
91 | * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz | |
92 | * ---------------------------------------------------------------------- | |
93 | * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) | |
94 | * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) | |
95 | * Filter frequency (MHz) 1 4.8 6 2 | |
96 | * CPCON 1100b 0011b 1100b 1100b | |
97 | * LFCON0 0 0 0 0 | |
98 | * | |
99 | * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: | |
100 | * | |
101 | * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz | |
102 | * --------------------------------------------------------------------------- | |
103 | * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) | |
104 | * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) | |
105 | * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) | |
106 | * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) | |
107 | * | |
108 | * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and | |
109 | * SessEnd. Each of these signals have their own debouncer and for each of | |
110 | * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or | |
111 | * BIAS_DEBOUNCE_B). | |
112 | * | |
113 | * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: | |
114 | * 0xffff -> No debouncing at all | |
115 | * <n> ms = <n> *1000 / (1/19.2MHz) / 4 | |
116 | * | |
117 | * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: | |
118 | * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 | |
119 | * | |
120 | * We need to use only DebounceA for BOOTROM. We don't need the DebounceB | |
121 | * values, so we can keep those to default. | |
122 | * | |
123 | * 4. The 20 microsecond delay after bias cell operation. | |
124 | */ | |
7e44d932 | 125 | static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { |
7ae18f37 LS |
126 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ |
127 | { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, | |
128 | { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, | |
129 | { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, | |
130 | { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } | |
131 | }; | |
132 | ||
7e44d932 JL |
133 | static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { |
134 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ | |
135 | { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, | |
136 | { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, | |
137 | { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, | |
138 | { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } | |
139 | }; | |
140 | ||
141 | static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { | |
142 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ | |
143 | { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, | |
144 | { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, | |
145 | { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, | |
146 | { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } | |
147 | }; | |
148 | ||
7ae18f37 LS |
149 | /* UTMIP Idle Wait Delay */ |
150 | static const u8 utmip_idle_wait_delay = 17; | |
151 | ||
152 | /* UTMIP Elastic limit */ | |
153 | static const u8 utmip_elastic_limit = 16; | |
154 | ||
155 | /* UTMIP High Speed Sync Start Delay */ | |
156 | static const u8 utmip_hs_sync_start_delay = 9; | |
87f938c9 | 157 | |
7e44d932 JL |
158 | struct fdt_usb_controller { |
159 | int compat; | |
160 | /* flag to determine whether controller supports hostpc register */ | |
161 | u32 has_hostpc:1; | |
162 | const unsigned *pll_parameter; | |
163 | }; | |
164 | ||
165 | static struct fdt_usb_controller fdt_usb_controllers[] = { | |
166 | { | |
167 | .compat = COMPAT_NVIDIA_TEGRA20_USB, | |
168 | .has_hostpc = 0, | |
169 | .pll_parameter = (const unsigned *)T20_usb_pll, | |
170 | }, | |
171 | { | |
172 | .compat = COMPAT_NVIDIA_TEGRA30_USB, | |
173 | .has_hostpc = 1, | |
174 | .pll_parameter = (const unsigned *)T30_usb_pll, | |
175 | }, | |
176 | { | |
177 | .compat = COMPAT_NVIDIA_TEGRA114_USB, | |
178 | .has_hostpc = 1, | |
179 | .pll_parameter = (const unsigned *)T114_usb_pll, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct fdt_usb_controller *controller; | |
184 | ||
8b3f7bf7 JL |
185 | /* |
186 | * A known hardware issue where Connect Status Change bit of PORTSC register | |
187 | * of USB1 controller will be set after Port Reset. | |
188 | * We have to clear it in order for later device enumeration to proceed. | |
189 | * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup | |
190 | * in "ehci-hcd.c". | |
191 | */ | |
192 | void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) | |
193 | { | |
194 | mdelay(50); | |
7e44d932 JL |
195 | /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ |
196 | if (controller->has_hostpc) | |
197 | *reg |= EHCI_PS_PE; | |
198 | ||
96df9c7e | 199 | if (((unsigned long)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) |
8b3f7bf7 JL |
200 | return; |
201 | /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ | |
202 | if (ehci_readl(status_reg) & EHCI_PS_CSC) | |
203 | *reg |= EHCI_PS_CSC; | |
204 | } | |
87f938c9 | 205 | |
7e44d932 JL |
206 | /* |
207 | * This ehci_set_usbmode overrides the weak function ehci_set_usbmode | |
208 | * in "ehci-hcd.c". | |
209 | */ | |
210 | void ehci_set_usbmode(int index) | |
211 | { | |
212 | struct fdt_usb *config; | |
213 | struct usb_ctlr *usbctlr; | |
214 | uint32_t tmp; | |
215 | ||
216 | config = &port[index]; | |
217 | usbctlr = config->reg; | |
218 | ||
219 | tmp = ehci_readl(&usbctlr->usb_mode); | |
220 | tmp |= USBMODE_CM_HC; | |
221 | ehci_writel(&usbctlr->usb_mode, tmp); | |
222 | } | |
223 | ||
224 | /* | |
225 | * This ehci_get_port_speed overrides the weak function ehci_get_port_speed | |
226 | * in "ehci-hcd.c". | |
227 | */ | |
228 | int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) | |
229 | { | |
230 | uint32_t tmp; | |
231 | uint32_t *reg_ptr; | |
232 | ||
233 | if (controller->has_hostpc) { | |
234 | reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC); | |
235 | tmp = ehci_readl(reg_ptr); | |
236 | return HOSTPC1_PSPD(tmp); | |
237 | } else | |
238 | return PORTSC_PSPD(reg); | |
239 | } | |
240 | ||
a4539a2a SW |
241 | /* Set up VBUS for host/device mode */ |
242 | static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) | |
7ae18f37 LS |
243 | { |
244 | /* | |
a4539a2a SW |
245 | * If we are an OTG port initializing in host mode, |
246 | * check if remote host is driving VBus and bail out in this case. | |
7ae18f37 | 247 | */ |
a4539a2a SW |
248 | if (init == USB_INIT_HOST && |
249 | config->dr_mode == DR_MODE_OTG && | |
250 | (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { | |
251 | printf("tegrausb: VBUS input active; not enabling as host\n"); | |
7ae18f37 | 252 | return; |
a4539a2a | 253 | } |
7ae18f37 | 254 | |
46927e1e | 255 | if (dm_gpio_is_valid(&config->vbus_gpio)) { |
a4539a2a SW |
256 | int vbus_value; |
257 | ||
46927e1e SG |
258 | vbus_value = (init == USB_INIT_HOST); |
259 | dm_gpio_set_value(&config->vbus_gpio, vbus_value); | |
a4539a2a | 260 | |
46927e1e SG |
261 | debug("set_up_vbus: GPIO %d %d\n", |
262 | gpio_get_number(&config->vbus_gpio), vbus_value); | |
7ae18f37 LS |
263 | } |
264 | } | |
265 | ||
266 | void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) | |
267 | { | |
268 | /* Reset the USB controller with 2us delay */ | |
269 | reset_periph(config->periph_id, 2); | |
270 | ||
271 | /* | |
272 | * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under | |
273 | * base address | |
274 | */ | |
275 | if (config->has_legacy_mode) | |
276 | setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); | |
277 | ||
278 | /* Put UTMIP1/3 in reset */ | |
279 | setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); | |
280 | ||
281 | /* Enable the UTMIP PHY */ | |
282 | if (config->utmi) | |
283 | setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); | |
284 | } | |
285 | ||
7e44d932 JL |
286 | static const unsigned *get_pll_timing(void) |
287 | { | |
288 | const unsigned *timing; | |
289 | ||
290 | timing = controller->pll_parameter + | |
291 | clock_get_osc_freq() * PARAM_COUNT; | |
292 | ||
293 | return timing; | |
294 | } | |
295 | ||
2d34151f | 296 | /* select the PHY to use with a USB controller */ |
a4539a2a SW |
297 | static void init_phy_mux(struct fdt_usb *config, uint pts, |
298 | enum usb_init_type init) | |
2d34151f SW |
299 | { |
300 | struct usb_ctlr *usbctlr = config->reg; | |
301 | ||
302 | #if defined(CONFIG_TEGRA20) | |
303 | if (config->periph_id == PERIPH_ID_USBD) { | |
304 | clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, | |
d1fcbae1 | 305 | pts << PTS1_SHIFT); |
2d34151f SW |
306 | clrbits_le32(&usbctlr->port_sc1, STS1); |
307 | } else { | |
308 | clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, | |
d1fcbae1 | 309 | pts << PTS_SHIFT); |
2d34151f SW |
310 | clrbits_le32(&usbctlr->port_sc1, STS); |
311 | } | |
312 | #else | |
a4539a2a | 313 | /* Set to Host mode (if applicable) after Controller Reset was done */ |
2d34151f | 314 | clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, |
a4539a2a SW |
315 | (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); |
316 | /* | |
317 | * Select PHY interface after setting host mode. | |
318 | * For device mode, the ordering requirement is not an issue, since | |
319 | * only the first USB controller supports device mode, and that USB | |
320 | * controller can only talk to a UTMI PHY, so the PHY selection is | |
321 | * already made at reset time, so this write is a no-op. | |
322 | */ | |
2d34151f SW |
323 | clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, |
324 | pts << PTS_SHIFT); | |
325 | clrbits_le32(&usbctlr->hostpc1_devlc, STS); | |
326 | #endif | |
327 | } | |
328 | ||
7ae18f37 | 329 | /* set up the UTMI USB controller with the parameters provided */ |
a4539a2a SW |
330 | static int init_utmi_usb_controller(struct fdt_usb *config, |
331 | enum usb_init_type init) | |
7ae18f37 | 332 | { |
a4539a2a | 333 | u32 b_sess_valid_mask, val; |
7ae18f37 LS |
334 | int loop_count; |
335 | const unsigned *timing; | |
336 | struct usb_ctlr *usbctlr = config->reg; | |
7e44d932 JL |
337 | struct clk_rst_ctlr *clkrst; |
338 | struct usb_ctlr *usb1ctlr; | |
7ae18f37 LS |
339 | |
340 | clock_enable(config->periph_id); | |
341 | ||
342 | /* Reset the usb controller */ | |
343 | usbf_reset_controller(config, usbctlr); | |
344 | ||
345 | /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ | |
346 | clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); | |
347 | ||
348 | /* Follow the crystal clock disable by >100ns delay */ | |
349 | udelay(1); | |
350 | ||
a4539a2a SW |
351 | b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); |
352 | clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, | |
353 | (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); | |
354 | ||
7ae18f37 LS |
355 | /* |
356 | * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP | |
357 | * mux must be switched to actually use a_sess_vld threshold. | |
358 | */ | |
7e44d932 | 359 | if (config->dr_mode == DR_MODE_OTG && |
46927e1e | 360 | dm_gpio_is_valid(&config->vbus_gpio)) |
7ae18f37 LS |
361 | clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, |
362 | VBUS_SENSE_CTL_MASK, | |
363 | VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); | |
7ae18f37 LS |
364 | |
365 | /* | |
366 | * PLL Delay CONFIGURATION settings. The following parameters control | |
367 | * the bring up of the plls. | |
368 | */ | |
7e44d932 JL |
369 | timing = get_pll_timing(); |
370 | ||
371 | if (!controller->has_hostpc) { | |
372 | val = readl(&usbctlr->utmip_misc_cfg1); | |
373 | clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, | |
374 | timing[PARAM_STABLE_COUNT] << | |
375 | UTMIP_PLLU_STABLE_COUNT_SHIFT); | |
376 | clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, | |
377 | timing[PARAM_ACTIVE_DELAY_COUNT] << | |
378 | UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); | |
379 | writel(val, &usbctlr->utmip_misc_cfg1); | |
380 | ||
381 | /* Set PLL enable delay count and crystal frequency count */ | |
382 | val = readl(&usbctlr->utmip_pll_cfg1); | |
383 | clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, | |
384 | timing[PARAM_ENABLE_DELAY_COUNT] << | |
385 | UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); | |
386 | clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, | |
387 | timing[PARAM_XTAL_FREQ_COUNT] << | |
388 | UTMIP_XTAL_FREQ_COUNT_SHIFT); | |
389 | writel(val, &usbctlr->utmip_pll_cfg1); | |
390 | } else { | |
391 | clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
392 | ||
393 | val = readl(&clkrst->crc_utmip_pll_cfg2); | |
394 | clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, | |
395 | timing[PARAM_STABLE_COUNT] << | |
396 | UTMIP_PLLU_STABLE_COUNT_SHIFT); | |
397 | clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, | |
398 | timing[PARAM_ACTIVE_DELAY_COUNT] << | |
399 | UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); | |
400 | writel(val, &clkrst->crc_utmip_pll_cfg2); | |
401 | ||
402 | /* Set PLL enable delay count and crystal frequency count */ | |
403 | val = readl(&clkrst->crc_utmip_pll_cfg1); | |
404 | clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, | |
405 | timing[PARAM_ENABLE_DELAY_COUNT] << | |
406 | UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); | |
407 | clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, | |
408 | timing[PARAM_XTAL_FREQ_COUNT] << | |
409 | UTMIP_XTAL_FREQ_COUNT_SHIFT); | |
410 | writel(val, &clkrst->crc_utmip_pll_cfg1); | |
411 | ||
412 | /* Disable Power Down state for PLL */ | |
413 | clrbits_le32(&clkrst->crc_utmip_pll_cfg1, | |
414 | PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | | |
415 | PLL_ACTIVE_POWERDOWN); | |
416 | ||
417 | /* Recommended PHY settings for EYE diagram */ | |
418 | val = readl(&usbctlr->utmip_xcvr_cfg0); | |
419 | clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, | |
420 | 0x4 << UTMIP_XCVR_SETUP_SHIFT); | |
421 | clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, | |
422 | 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); | |
423 | clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, | |
424 | 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); | |
425 | writel(val, &usbctlr->utmip_xcvr_cfg0); | |
426 | clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, | |
427 | UTMIP_XCVR_TERM_RANGE_ADJ_MASK, | |
428 | 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); | |
429 | ||
430 | /* Some registers can be controlled from USB1 only. */ | |
431 | if (config->periph_id != PERIPH_ID_USBD) { | |
432 | clock_enable(PERIPH_ID_USBD); | |
433 | /* Disable Reset if in Reset state */ | |
434 | reset_set_enable(PERIPH_ID_USBD, 0); | |
435 | } | |
436 | usb1ctlr = (struct usb_ctlr *) | |
96df9c7e | 437 | ((unsigned long)config->reg & USB1_ADDR_MASK); |
7e44d932 JL |
438 | val = readl(&usb1ctlr->utmip_bias_cfg0); |
439 | setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); | |
440 | clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, | |
441 | 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); | |
442 | clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, | |
443 | 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); | |
444 | writel(val, &usb1ctlr->utmip_bias_cfg0); | |
445 | ||
446 | /* Miscellaneous setting mentioned in Programming Guide */ | |
447 | clrbits_le32(&usbctlr->utmip_misc_cfg0, | |
448 | UTMIP_SUSPEND_EXIT_ON_EDGE); | |
449 | } | |
7ae18f37 LS |
450 | |
451 | /* Setting the tracking length time */ | |
452 | clrsetbits_le32(&usbctlr->utmip_bias_cfg1, | |
453 | UTMIP_BIAS_PDTRK_COUNT_MASK, | |
454 | timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); | |
455 | ||
456 | /* Program debounce time for VBUS to become valid */ | |
457 | clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, | |
458 | UTMIP_DEBOUNCE_CFG0_MASK, | |
459 | timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); | |
460 | ||
461 | setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); | |
462 | ||
463 | /* Disable battery charge enabling bit */ | |
464 | setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); | |
465 | ||
466 | clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); | |
467 | setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); | |
468 | ||
469 | /* | |
470 | * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT | |
471 | * Setting these fields, together with default values of the | |
472 | * other fields, results in programming the registers below as | |
473 | * follows: | |
474 | * UTMIP_HSRX_CFG0 = 0x9168c000 | |
475 | * UTMIP_HSRX_CFG1 = 0x13 | |
476 | */ | |
477 | ||
478 | /* Set PLL enable delay count and Crystal frequency count */ | |
479 | val = readl(&usbctlr->utmip_hsrx_cfg0); | |
480 | clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, | |
481 | utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); | |
482 | clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, | |
483 | utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); | |
484 | writel(val, &usbctlr->utmip_hsrx_cfg0); | |
485 | ||
486 | /* Configure the UTMIP_HS_SYNC_START_DLY */ | |
487 | clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, | |
488 | UTMIP_HS_SYNC_START_DLY_MASK, | |
489 | utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); | |
490 | ||
491 | /* Preceed the crystal clock disable by >100ns delay. */ | |
492 | udelay(1); | |
493 | ||
494 | /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ | |
495 | setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); | |
496 | ||
7e44d932 JL |
497 | if (controller->has_hostpc) { |
498 | if (config->periph_id == PERIPH_ID_USBD) | |
499 | clrbits_le32(&clkrst->crc_utmip_pll_cfg2, | |
500 | UTMIP_FORCE_PD_SAMP_A_POWERDOWN); | |
b03f4b37 SA |
501 | if (config->periph_id == PERIPH_ID_USB2) |
502 | clrbits_le32(&clkrst->crc_utmip_pll_cfg2, | |
503 | UTMIP_FORCE_PD_SAMP_B_POWERDOWN); | |
7e44d932 JL |
504 | if (config->periph_id == PERIPH_ID_USB3) |
505 | clrbits_le32(&clkrst->crc_utmip_pll_cfg2, | |
506 | UTMIP_FORCE_PD_SAMP_C_POWERDOWN); | |
507 | } | |
7ae18f37 LS |
508 | /* Finished the per-controller init. */ |
509 | ||
510 | /* De-assert UTMIP_RESET to bring out of reset. */ | |
511 | clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); | |
512 | ||
513 | /* Wait for the phy clock to become valid in 100 ms */ | |
514 | for (loop_count = 100000; loop_count != 0; loop_count--) { | |
515 | if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) | |
516 | break; | |
517 | udelay(1); | |
518 | } | |
519 | if (!loop_count) | |
520 | return -1; | |
521 | ||
522 | /* Disable ICUSB FS/LS transceiver */ | |
523 | clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); | |
524 | ||
525 | /* Select UTMI parallel interface */ | |
a4539a2a | 526 | init_phy_mux(config, PTS_UTMI, init); |
7ae18f37 LS |
527 | |
528 | /* Deassert power down state */ | |
529 | clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | | |
530 | UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); | |
531 | clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | | |
532 | UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); | |
533 | ||
7e44d932 JL |
534 | if (controller->has_hostpc) { |
535 | /* | |
536 | * BIAS Pad Power Down is common among all 3 USB | |
537 | * controllers and can be controlled from USB1 only. | |
538 | */ | |
539 | usb1ctlr = (struct usb_ctlr *) | |
96df9c7e | 540 | ((unsigned long)config->reg & USB1_ADDR_MASK); |
7e44d932 JL |
541 | clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); |
542 | udelay(25); | |
543 | clrbits_le32(&usb1ctlr->utmip_bias_cfg1, | |
544 | UTMIP_FORCE_PDTRK_POWERDOWN); | |
545 | } | |
7ae18f37 LS |
546 | return 0; |
547 | } | |
548 | ||
549 | #ifdef CONFIG_USB_ULPI | |
550 | /* if board file does not set a ULPI reference frequency we default to 24MHz */ | |
551 | #ifndef CONFIG_ULPI_REF_CLK | |
552 | #define CONFIG_ULPI_REF_CLK 24000000 | |
553 | #endif | |
554 | ||
555 | /* set up the ULPI USB controller with the parameters provided */ | |
a4539a2a SW |
556 | static int init_ulpi_usb_controller(struct fdt_usb *config, |
557 | enum usb_init_type init) | |
7ae18f37 LS |
558 | { |
559 | u32 val; | |
560 | int loop_count; | |
561 | struct ulpi_viewport ulpi_vp; | |
562 | struct usb_ctlr *usbctlr = config->reg; | |
563 | ||
564 | /* set up ULPI reference clock on pllp_out4 */ | |
565 | clock_enable(PERIPH_ID_DEV2_OUT); | |
566 | clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); | |
567 | ||
568 | /* reset ULPI phy */ | |
46927e1e SG |
569 | if (dm_gpio_is_valid(&config->phy_reset_gpio)) { |
570 | dm_gpio_set_value(&config->phy_reset_gpio, 0); | |
7ae18f37 | 571 | mdelay(5); |
46927e1e | 572 | dm_gpio_set_value(&config->phy_reset_gpio, 1); |
7ae18f37 LS |
573 | } |
574 | ||
575 | /* Reset the usb controller */ | |
576 | clock_enable(config->periph_id); | |
577 | usbf_reset_controller(config, usbctlr); | |
578 | ||
579 | /* enable pinmux bypass */ | |
580 | setbits_le32(&usbctlr->ulpi_timing_ctrl_0, | |
581 | ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); | |
582 | ||
583 | /* Select ULPI parallel interface */ | |
a4539a2a | 584 | init_phy_mux(config, PTS_ULPI, init); |
7ae18f37 LS |
585 | |
586 | /* enable ULPI transceiver */ | |
587 | setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); | |
588 | ||
589 | /* configure ULPI transceiver timings */ | |
590 | val = 0; | |
591 | writel(val, &usbctlr->ulpi_timing_ctrl_1); | |
592 | ||
593 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
594 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
595 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
596 | writel(val, &usbctlr->ulpi_timing_ctrl_1); | |
597 | udelay(10); | |
598 | ||
599 | val |= ULPI_DATA_TRIMMER_LOAD; | |
600 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
601 | val |= ULPI_DIR_TRIMMER_LOAD; | |
602 | writel(val, &usbctlr->ulpi_timing_ctrl_1); | |
603 | ||
604 | /* set up phy for host operation with external vbus supply */ | |
605 | ulpi_vp.port_num = 0; | |
606 | ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; | |
607 | ||
608 | if (ulpi_init(&ulpi_vp)) { | |
609 | printf("Tegra ULPI viewport init failed\n"); | |
610 | return -1; | |
611 | } | |
612 | ||
613 | ulpi_set_vbus(&ulpi_vp, 1, 1); | |
614 | ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); | |
615 | ||
616 | /* enable wakeup events */ | |
617 | setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); | |
618 | ||
619 | /* Enable and wait for the phy clock to become valid in 100 ms */ | |
620 | setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); | |
621 | for (loop_count = 100000; loop_count != 0; loop_count--) { | |
622 | if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) | |
623 | break; | |
624 | udelay(1); | |
625 | } | |
626 | if (!loop_count) | |
627 | return -1; | |
628 | clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); | |
629 | ||
630 | return 0; | |
631 | } | |
632 | #else | |
a4539a2a SW |
633 | static int init_ulpi_usb_controller(struct fdt_usb *config, |
634 | enum usb_init_type init) | |
7ae18f37 LS |
635 | { |
636 | printf("No code to set up ULPI controller, please enable" | |
637 | "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); | |
638 | return -1; | |
639 | } | |
640 | #endif | |
641 | ||
642 | static void config_clock(const u32 timing[]) | |
643 | { | |
644 | clock_start_pll(CLOCK_ID_USB, | |
645 | timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], | |
646 | timing[PARAM_CPCON], timing[PARAM_LFCON]); | |
647 | } | |
648 | ||
7e44d932 | 649 | static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) |
7ae18f37 LS |
650 | { |
651 | const char *phy, *mode; | |
652 | ||
653 | config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); | |
654 | mode = fdt_getprop(blob, node, "dr_mode", NULL); | |
655 | if (mode) { | |
656 | if (0 == strcmp(mode, "host")) | |
657 | config->dr_mode = DR_MODE_HOST; | |
658 | else if (0 == strcmp(mode, "peripheral")) | |
659 | config->dr_mode = DR_MODE_DEVICE; | |
660 | else if (0 == strcmp(mode, "otg")) | |
661 | config->dr_mode = DR_MODE_OTG; | |
662 | else { | |
663 | debug("%s: Cannot decode dr_mode '%s'\n", __func__, | |
664 | mode); | |
665 | return -FDT_ERR_NOTFOUND; | |
666 | } | |
667 | } else { | |
668 | config->dr_mode = DR_MODE_HOST; | |
669 | } | |
670 | ||
671 | phy = fdt_getprop(blob, node, "phy_type", NULL); | |
672 | config->utmi = phy && 0 == strcmp("utmi", phy); | |
673 | config->ulpi = phy && 0 == strcmp("ulpi", phy); | |
674 | config->enabled = fdtdec_get_is_enabled(blob, node); | |
675 | config->has_legacy_mode = fdtdec_get_bool(blob, node, | |
676 | "nvidia,has-legacy-mode"); | |
7e44d932 | 677 | if (config->has_legacy_mode) |
96df9c7e | 678 | port_addr_clear_csc = (unsigned long)config->reg; |
7ae18f37 LS |
679 | config->periph_id = clock_decode_periph_id(blob, node); |
680 | if (config->periph_id == PERIPH_ID_NONE) { | |
681 | debug("%s: Missing/invalid peripheral ID\n", __func__); | |
682 | return -FDT_ERR_NOTFOUND; | |
683 | } | |
46927e1e SG |
684 | gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, |
685 | &config->vbus_gpio, GPIOD_IS_OUT); | |
686 | gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, | |
687 | &config->phy_reset_gpio, GPIOD_IS_OUT); | |
7ae18f37 LS |
688 | debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " |
689 | "vbus=%d, phy_reset=%d, dr_mode=%d\n", | |
690 | config->enabled, config->has_legacy_mode, config->utmi, | |
46927e1e SG |
691 | config->ulpi, config->periph_id, |
692 | gpio_get_number(&config->vbus_gpio), | |
693 | gpio_get_number(&config->phy_reset_gpio), config->dr_mode); | |
7ae18f37 LS |
694 | |
695 | return 0; | |
696 | } | |
697 | ||
7e44d932 JL |
698 | /* |
699 | * process_usb_nodes() - Process a list of USB nodes, adding them to our list | |
700 | * of USB ports. | |
701 | * @blob: fdt blob | |
702 | * @node_list: list of nodes to process (any <=0 are ignored) | |
703 | * @count: number of nodes to process | |
704 | * | |
705 | * Return: 0 - ok, -1 - error | |
706 | */ | |
707 | static int process_usb_nodes(const void *blob, int node_list[], int count) | |
7ae18f37 LS |
708 | { |
709 | struct fdt_usb config; | |
7e44d932 JL |
710 | int node, i; |
711 | int clk_done = 0; | |
7ae18f37 | 712 | |
7e44d932 | 713 | port_count = 0; |
7ae18f37 LS |
714 | for (i = 0; i < count; i++) { |
715 | if (port_count == USB_PORTS_MAX) { | |
716 | printf("tegrausb: Cannot register more than %d ports\n", | |
717 | USB_PORTS_MAX); | |
718 | return -1; | |
719 | } | |
720 | ||
721 | debug("USB %d: ", i); | |
722 | node = node_list[i]; | |
723 | if (!node) | |
724 | continue; | |
725 | if (fdt_decode_usb(blob, node, &config)) { | |
726 | debug("Cannot decode USB node %s\n", | |
727 | fdt_get_name(blob, node, NULL)); | |
728 | return -1; | |
729 | } | |
7e44d932 JL |
730 | if (!clk_done) { |
731 | config_clock(get_pll_timing()); | |
732 | clk_done = 1; | |
733 | } | |
7ae18f37 LS |
734 | config.initialized = 0; |
735 | ||
736 | /* add new USB port to the list of available ports */ | |
737 | port[port_count++] = config; | |
738 | } | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
16297cfb | 743 | int usb_process_devicetree(const void *blob) |
7e44d932 JL |
744 | { |
745 | int node_list[USB_PORTS_MAX]; | |
746 | int count, err = 0; | |
747 | int i; | |
748 | ||
749 | for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { | |
750 | controller = &fdt_usb_controllers[i]; | |
751 | ||
752 | count = fdtdec_find_aliases_for_id(blob, "usb", | |
753 | controller->compat, node_list, USB_PORTS_MAX); | |
754 | if (count) { | |
755 | err = process_usb_nodes(blob, node_list, count); | |
756 | if (err) | |
757 | printf("%s: Error processing USB node!\n", | |
758 | __func__); | |
759 | return err; | |
760 | } | |
761 | } | |
762 | if (i == ARRAY_SIZE(fdt_usb_controllers)) | |
763 | controller = NULL; | |
764 | ||
765 | return err; | |
766 | } | |
767 | ||
d7a55e1a LS |
768 | /** |
769 | * Start up the given port number (ports are numbered from 0 on each board). | |
770 | * This returns values for the appropriate hccr and hcor addresses to use for | |
771 | * USB EHCI operations. | |
772 | * | |
773 | * @param index port number to start | |
774 | * @param hccr returns start address of EHCI HCCR registers | |
775 | * @param hcor returns start address of EHCI HCOR registers | |
776 | * @return 0 if ok, -1 on error (generally invalid port number) | |
87f938c9 | 777 | */ |
127efc4f TK |
778 | int ehci_hcd_init(int index, enum usb_init_type init, |
779 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) | |
87f938c9 | 780 | { |
d7a55e1a LS |
781 | struct fdt_usb *config; |
782 | struct usb_ctlr *usbctlr; | |
87f938c9 | 783 | |
d7a55e1a LS |
784 | if (index >= port_count) |
785 | return -1; | |
786 | ||
787 | config = &port[index]; | |
788 | ||
a4539a2a SW |
789 | switch (init) { |
790 | case USB_INIT_HOST: | |
791 | switch (config->dr_mode) { | |
792 | case DR_MODE_HOST: | |
793 | case DR_MODE_OTG: | |
794 | break; | |
795 | default: | |
796 | printf("tegrausb: Invalid dr_mode %d for host mode\n", | |
797 | config->dr_mode); | |
798 | return -1; | |
799 | } | |
800 | break; | |
801 | case USB_INIT_DEVICE: | |
802 | if (config->periph_id != PERIPH_ID_USBD) { | |
803 | printf("tegrausb: Device mode only supported on first USB controller\n"); | |
804 | return -1; | |
805 | } | |
806 | if (!config->utmi) { | |
807 | printf("tegrausb: Device mode only supported with UTMI PHY\n"); | |
808 | return -1; | |
809 | } | |
810 | switch (config->dr_mode) { | |
811 | case DR_MODE_DEVICE: | |
812 | case DR_MODE_OTG: | |
813 | break; | |
814 | default: | |
815 | printf("tegrausb: Invalid dr_mode %d for device mode\n", | |
816 | config->dr_mode); | |
817 | return -1; | |
818 | } | |
819 | break; | |
820 | default: | |
821 | printf("tegrausb: Unknown USB_INIT_* %d\n", init); | |
822 | return -1; | |
823 | } | |
824 | ||
d7a55e1a | 825 | /* skip init, if the port is already initialized */ |
a4539a2a | 826 | if (config->initialized && config->init_type == init) |
d7a55e1a LS |
827 | goto success; |
828 | ||
a4539a2a | 829 | if (config->utmi && init_utmi_usb_controller(config, init)) { |
d7a55e1a LS |
830 | printf("tegrausb: Cannot init port %d\n", index); |
831 | return -1; | |
832 | } | |
833 | ||
a4539a2a | 834 | if (config->ulpi && init_ulpi_usb_controller(config, init)) { |
d7a55e1a | 835 | printf("tegrausb: Cannot init port %d\n", index); |
87f938c9 | 836 | return -1; |
d7a55e1a | 837 | } |
87f938c9 | 838 | |
a4539a2a | 839 | set_up_vbus(config, init); |
d7a55e1a LS |
840 | |
841 | config->initialized = 1; | |
a4539a2a | 842 | config->init_type = init; |
87f938c9 | 843 | |
d7a55e1a LS |
844 | success: |
845 | usbctlr = config->reg; | |
846 | *hccr = (struct ehci_hccr *)&usbctlr->cap_length; | |
847 | *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; | |
7e44d932 | 848 | |
87f938c9 SG |
849 | return 0; |
850 | } | |
851 | ||
852 | /* | |
d7a55e1a | 853 | * Bring down the specified USB controller |
87f938c9 | 854 | */ |
676ae068 | 855 | int ehci_hcd_stop(int index) |
87f938c9 | 856 | { |
d7a55e1a LS |
857 | struct usb_ctlr *usbctlr; |
858 | ||
859 | usbctlr = port[index].reg; | |
860 | ||
861 | /* Stop controller */ | |
862 | writel(0, &usbctlr->usb_cmd); | |
863 | udelay(1000); | |
864 | ||
865 | /* Initiate controller reset */ | |
866 | writel(2, &usbctlr->usb_cmd); | |
867 | udelay(1000); | |
868 | ||
869 | port[index].initialized = 0; | |
870 | ||
871 | return 0; | |
87f938c9 | 872 | } |