[thirdparty/u-boot.git] / drivers / usb / host / ehci.h

/* SPDX-License-Identifier: GPL-2.0 */
/*-
 * Copyright (c) 2007-2008, Juniper Networks, Inc.
 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
 * All rights reserved.
 */

#ifndef USB_EHCI_H
#define USB_EHCI_H

#include <usb.h>

/* Section 2.2.3 - N_PORTS */
#define MAX_HC_PORTS		15

/*
 * Register Space.
 */
struct ehci_hccr {
	uint32_t cr_capbase;
#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
	uint32_t cr_hcsparams;
#define HCS_PPC(p)		((p) & (1 << 4))
#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
	uint32_t cr_hccparams;
	uint8_t cr_hcsp_portrt[8];
} __attribute__ ((packed, aligned(4)));

struct ehci_hcor {
	uint32_t or_usbcmd;
#define CMD_PARK	(1 << 11)		/* enable "park" */
#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
#define CMD_LRESET	(1 << 7)		/* partial reset */
#define CMD_IAAD	(1 << 6)		/* "doorbell" interrupt */
#define CMD_ASE		(1 << 5)		/* async schedule enable */
#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
#define CMD_RESET	(1 << 1)		/* reset HC not bus */
#define CMD_RUN		(1 << 0)		/* start/stop HC */
	uint32_t or_usbsts;
#define STS_ASS		(1 << 15)
#define	STS_PSS		(1 << 14)
#define STS_HALT	(1 << 12)
	uint32_t or_usbintr;
#define INTR_UE         (1 << 0)                /* USB interrupt enable */
#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
#define INTR_PCE        (1 << 2)                /* Port change detect enable */
#define INTR_SEE        (1 << 4)                /* system error enable */
#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
	uint32_t or_frindex;
	uint32_t or_ctrldssegment;
	uint32_t or_periodiclistbase;
	uint32_t or_asynclistaddr;
	uint32_t _reserved_0_;
	uint32_t or_burstsize;
	uint32_t or_txfilltuning;
#define TXFIFO_THRESH_MASK		(0x3f << 16)
#define TXFIFO_THRESH(p)		((p & 0x3f) << 16)
	uint32_t _reserved_1_[6];
	uint32_t or_configflag;
#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
	uint32_t or_portsc[MAX_HC_PORTS];
#define PORTSC_PSPD(x)		(((x) >> 26) & 0x3)
#define PORTSC_PSPD_FS			0x0
#define PORTSC_PSPD_LS			0x1
#define PORTSC_PSPD_HS			0x2
	uint32_t or_systune;
} __attribute__ ((packed, aligned(4)));

#define USBMODE		0x68		/* USB Device mode */
#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */

/* Interface descriptor */
struct usb_linux_interface_descriptor {
	unsigned char	bLength;
	unsigned char	bDescriptorType;
	unsigned char	bInterfaceNumber;
	unsigned char	bAlternateSetting;
	unsigned char	bNumEndpoints;
	unsigned char	bInterfaceClass;
	unsigned char	bInterfaceSubClass;
	unsigned char	bInterfaceProtocol;
	unsigned char	iInterface;
} __attribute__ ((packed));

/* Configuration descriptor information.. */
struct usb_linux_config_descriptor {
	unsigned char	bLength;
	unsigned char	bDescriptorType;
	unsigned short	wTotalLength;
	unsigned char	bNumInterfaces;
	unsigned char	bConfigurationValue;
	unsigned char	iConfiguration;
	unsigned char	bmAttributes;
	unsigned char	MaxPower;
} __attribute__ ((packed));

#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
#define ehci_readl(x)		be32_to_cpu(__raw_readl(x))
#define ehci_writel(a, b)	__raw_writel(cpu_to_be32(b), a)
#else
#define ehci_readl(x)		readl(x)
#define ehci_writel(a, b)	writel(b, a)
#endif

#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
#define hc32_to_cpu(x)		be32_to_cpu((x))
#define cpu_to_hc32(x)		cpu_to_be32((x))
#else
#define hc32_to_cpu(x)		le32_to_cpu((x))
#define cpu_to_hc32(x)		cpu_to_le32((x))
#endif

#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
#define EHCI_PS_LS		(3 << 10)	/* RO line status */
#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)

#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))

/*
 * Schedule Interface Space.
 *
 * IMPORTANT: Software must ensure that no interface data structure
 * reachable by the EHCI host controller spans a 4K page boundary!
 *
 * Periodic transfers (i.e. isochronous and interrupt transfers) are
 * not supported.
 */

/* Queue Element Transfer Descriptor (qTD). */
struct qTD {
	/* this part defined by EHCI spec */
	uint32_t qt_next;			/* see EHCI 3.5.1 */
#define	QT_NEXT_TERMINATE	1
	uint32_t qt_altnext;			/* see EHCI 3.5.2 */
	uint32_t qt_token;			/* see EHCI 3.5.3 */
#define QT_TOKEN_DT(x)		(((x) & 0x1) << 31)	/* Data Toggle */
#define QT_TOKEN_GET_DT(x)		(((x) >> 31) & 0x1)
#define QT_TOKEN_TOTALBYTES(x)	(((x) & 0x7fff) << 16)	/* Total Bytes to Transfer */
#define QT_TOKEN_GET_TOTALBYTES(x)	(((x) >> 16) & 0x7fff)
#define QT_TOKEN_IOC(x)		(((x) & 0x1) << 15)	/* Interrupt On Complete */
#define QT_TOKEN_CPAGE(x)	(((x) & 0x7) << 12)	/* Current Page */
#define QT_TOKEN_CERR(x)	(((x) & 0x3) << 10)	/* Error Counter */
#define QT_TOKEN_PID(x)		(((x) & 0x3) << 8)	/* PID Code */
#define QT_TOKEN_PID_OUT		0x0
#define QT_TOKEN_PID_IN			0x1
#define QT_TOKEN_PID_SETUP		0x2
#define QT_TOKEN_STATUS(x)	(((x) & 0xff) << 0)	/* Status */
#define QT_TOKEN_GET_STATUS(x)		(((x) >> 0) & 0xff)
#define QT_TOKEN_STATUS_ACTIVE		0x80
#define QT_TOKEN_STATUS_HALTED		0x40
#define QT_TOKEN_STATUS_DATBUFERR	0x20
#define QT_TOKEN_STATUS_BABBLEDET	0x10
#define QT_TOKEN_STATUS_XACTERR		0x08
#define QT_TOKEN_STATUS_MISSEDUFRAME	0x04
#define QT_TOKEN_STATUS_SPLITXSTATE	0x02
#define QT_TOKEN_STATUS_PERR		0x01
#define QT_BUFFER_CNT		5
	uint32_t qt_buffer[QT_BUFFER_CNT];	/* see EHCI 3.5.4 */
	uint32_t qt_buffer_hi[QT_BUFFER_CNT];	/* Appendix B */
	/* pad struct for 32 byte alignment */
	uint32_t unused[3];
};

#define EHCI_PAGE_SIZE		4096

/* Queue Head (QH). */
struct QH {
	uint32_t qh_link;
#define	QH_LINK_TERMINATE	1
#define	QH_LINK_TYPE_ITD	0
#define	QH_LINK_TYPE_QH		2
#define	QH_LINK_TYPE_SITD	4
#define	QH_LINK_TYPE_FSTN	6
	uint32_t qh_endpt1;
#define QH_ENDPT1_RL(x)		(((x) & 0xf) << 28)	/* NAK Count Reload */
#define QH_ENDPT1_C(x)		(((x) & 0x1) << 27)	/* Control Endpoint Flag */
#define QH_ENDPT1_MAXPKTLEN(x)	(((x) & 0x7ff) << 16)	/* Maximum Packet Length */
#define QH_ENDPT1_H(x)		(((x) & 0x1) << 15)	/* Head of Reclamation List Flag */
#define QH_ENDPT1_DTC(x)	(((x) & 0x1) << 14)	/* Data Toggle Control */
#define QH_ENDPT1_DTC_IGNORE_QTD_TD	0x0
#define QH_ENDPT1_DTC_DT_FROM_QTD	0x1
#define QH_ENDPT1_EPS(x)	(((x) & 0x3) << 12)	/* Endpoint Speed */
#define QH_ENDPT1_EPS_FS		0x0
#define QH_ENDPT1_EPS_LS		0x1
#define QH_ENDPT1_EPS_HS		0x2
#define QH_ENDPT1_ENDPT(x)	(((x) & 0xf) << 8)	/* Endpoint Number */
#define QH_ENDPT1_I(x)		(((x) & 0x1) << 7)	/* Inactivate on Next Transaction */
#define QH_ENDPT1_DEVADDR(x)	(((x) & 0x7f) << 0)	/* Device Address */
	uint32_t qh_endpt2;
#define QH_ENDPT2_MULT(x)	(((x) & 0x3) << 30)	/* High-Bandwidth Pipe Multiplier */
#define QH_ENDPT2_PORTNUM(x)	(((x) & 0x7f) << 23)	/* Port Number */
#define QH_ENDPT2_HUBADDR(x)	(((x) & 0x7f) << 16)	/* Hub Address */
#define QH_ENDPT2_UFCMASK(x)	(((x) & 0xff) << 8)	/* Split Completion Mask */
#define QH_ENDPT2_UFSMASK(x)	(((x) & 0xff) << 0)	/* Interrupt Schedule Mask */
	uint32_t qh_curtd;
	struct qTD qh_overlay;
	/*
	 * Add dummy fill value to make the size of this struct
	 * aligned to 32 bytes
	 */
	union {
		uint32_t fill[4];
		void *buffer;
	};
};

/* Tweak flags for EHCI, used to control operation */
enum {
	/* don't use or_configflag in init */
	EHCI_TWEAK_NO_INIT_CF		= 1 << 0,
};

struct ehci_ctrl;

struct ehci_ops {
	void (*set_usb_mode)(struct ehci_ctrl *ctrl);
	int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
	void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
			      uint32_t *reg);
	uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
	int (*init_after_reset)(struct ehci_ctrl *ctrl);
};

struct ehci_ctrl {
	enum usb_init_type init;
	struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
	struct ehci_hcor *hcor;
	int rootdev;
	uint16_t portreset;
	struct QH qh_list __aligned(USB_DMA_MINALIGN);
	struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
	uint32_t *periodic_list;
	int periodic_schedules;
	int ntds;
	struct ehci_ops ops;
	void *priv;	/* client's private data */
};

/**
 * ehci_set_controller_info() - Set up private data for the controller
 *
 * This function can be called in ehci_hcd_init() to tell the EHCI layer
 * about the controller's private data pointer. Then in the above functions
 * this can be accessed given the struct ehci_ctrl pointer. Also special
 * EHCI operation methods can be provided if required
 *
 * @index:	Controller number to set
 * @priv:	Controller pointer
 * @ops:	Controller operations, or NULL to use default
 */
void ehci_set_controller_priv(int index, void *priv,
			      const struct ehci_ops *ops);

/**
 * ehci_get_controller_priv() - Get controller private data
 *
 * @index	Controller number to get
 * @return controller pointer for this index
 */
void *ehci_get_controller_priv(int index);

/* Low level init functions */
int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor);
int ehci_hcd_stop(int index);

int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
		  struct ehci_hcor *hcor, const struct ehci_ops *ops,
		  uint tweaks, enum usb_init_type init);
int ehci_deregister(struct udevice *dev);
extern struct dm_usb_ops ehci_usb_ops;

#endif /* USB_EHCI_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
aaf098cf MT	2	/*-
aaf098cf MT	3	* Copyright (c) 2007-2008, Juniper Networks, Inc.
c0d722fe	4	* Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
aaf098cf	5	* All rights reserved.
aaf098cf MT	6	*/
	7
	8	#ifndef USB_EHCI_H
	9	#define USB_EHCI_H
	10
b959655f MV	11	#include <usb.h>
b959655f MV	12
99c22556 BM	13	/* Section 2.2.3 - N_PORTS */
99c22556 BM	14	#define MAX_HC_PORTS 15
c0d722fe	15
aaf098cf MT	16	/*
	17	* Register Space.
	18	*/
	19	struct ehci_hccr {
db63299b	20	uint32_t cr_capbase;
	21	#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
	22	#define HC_VERSION(p) (((p) >> 16) & 0xffff)
aaf098cf	23	uint32_t cr_hcsparams;
c0d722fe RB	24	#define HCS_PPC(p) ((p) & (1 << 4))
c0d722fe RB	25	#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
51ab142b	26	#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
aaf098cf MT	27	uint32_t cr_hccparams;
aaf098cf MT	28	uint8_t cr_hcsp_portrt[8];
69716c19	29	} __attribute__ ((packed, aligned(4)));
aaf098cf MT	30
	31	struct ehci_hcor {
	32	uint32_t or_usbcmd;
51ab142b	33	#define CMD_PARK (1 << 11) /* enable "park" */
51ab142b	34	#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
51ab142b	35	#define CMD_LRESET (1 << 7) /* partial reset */
c02bf458 MY	36	#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
c02bf458 MY	37	#define CMD_ASE (1 << 5) /* async schedule enable */
51ab142b	38	#define CMD_PSE (1 << 4) /* periodic schedule enable */
	39	#define CMD_RESET (1 << 1) /* reset HC not bus */
	40	#define CMD_RUN (1 << 0) /* start/stop HC */
aaf098cf	41	uint32_t or_usbsts;
14eb79b7	42	#define STS_ASS (1 << 15)
8f62ca64	43	#define STS_PSS (1 << 14)
51ab142b	44	#define STS_HALT (1 << 12)
aaf098cf	45	uint32_t or_usbintr;
29c6fbe0 DD	46	#define INTR_UE (1 << 0) /* USB interrupt enable */
	47	#define INTR_UEE (1 << 1) /* USB error interrupt enable */
	48	#define INTR_PCE (1 << 2) /* Port change detect enable */
	49	#define INTR_SEE (1 << 4) /* system error enable */
	50	#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
aaf098cf MT	51	uint32_t or_frindex;
	52	uint32_t or_ctrldssegment;
	53	uint32_t or_periodiclistbase;
	54	uint32_t or_asynclistaddr;
9ab4ce22 SG	55	uint32_t _reserved_0_;
	56	uint32_t or_burstsize;
	57	uint32_t or_txfilltuning;
14eb79b7	58	#define TXFIFO_THRESH_MASK (0x3f << 16)
9ab4ce22 SG	59	#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
9ab4ce22 SG	60	uint32_t _reserved_1_[6];
aaf098cf	61	uint32_t or_configflag;
51ab142b	62	#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
99c22556	63	uint32_t or_portsc[MAX_HC_PORTS];
14eb79b7 BT	64	#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
	65	#define PORTSC_PSPD_FS 0x0
	66	#define PORTSC_PSPD_LS 0x1
	67	#define PORTSC_PSPD_HS 0x2
aaf098cf	68	uint32_t or_systune;
69716c19	69	} __attribute__ ((packed, aligned(4)));
aaf098cf	70
51ab142b	71	#define USBMODE 0x68 /* USB Device mode */
	72	#define USBMODE_SDIS (1 << 3) /* Stream disable */
	73	#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
	74	#define USBMODE_CM_HC (3 << 0) /* host controller mode */
	75	#define USBMODE_CM_IDLE (0 << 0) /* idle state */
	76
db63299b	77	/* Interface descriptor */
	78	struct usb_linux_interface_descriptor {
	79	unsigned char bLength;
	80	unsigned char bDescriptorType;
	81	unsigned char bInterfaceNumber;
	82	unsigned char bAlternateSetting;
	83	unsigned char bNumEndpoints;
	84	unsigned char bInterfaceClass;
	85	unsigned char bInterfaceSubClass;
	86	unsigned char bInterfaceProtocol;
	87	unsigned char iInterface;
	88	} __attribute__ ((packed));
	89
	90	/* Configuration descriptor information.. */
	91	struct usb_linux_config_descriptor {
	92	unsigned char bLength;
	93	unsigned char bDescriptorType;
	94	unsigned short wTotalLength;
	95	unsigned char bNumInterfaces;
	96	unsigned char bConfigurationValue;
	97	unsigned char iConfiguration;
	98	unsigned char bmAttributes;
	99	unsigned char MaxPower;
	100	} __attribute__ ((packed));
	101
	102	#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
9829ce2f AB	103	#define ehci_readl(x) be32_to_cpu(__raw_readl(x))
9829ce2f AB	104	#define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
db63299b	105	#else
9829ce2f AB	106	#define ehci_readl(x) readl(x)
9829ce2f AB	107	#define ehci_writel(a, b) writel(b, a)
db63299b	108	#endif
	109
	110	#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
	111	#define hc32_to_cpu(x) be32_to_cpu((x))
	112	#define cpu_to_hc32(x) cpu_to_be32((x))
	113	#else
	114	#define hc32_to_cpu(x) le32_to_cpu((x))
	115	#define cpu_to_hc32(x) cpu_to_le32((x))
	116	#endif
	117
c0d722fe RB	118	#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
	119	#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
	120	#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
	121	#define EHCI_PS_PO (1 << 13) /* RW port owner */
	122	#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
	123	#define EHCI_PS_LS (3 << 10) /* RO line status */
	124	#define EHCI_PS_PR (1 << 8) /* RW port reset */
	125	#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
	126	#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
	127	#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
	128	#define EHCI_PS_OCA (1 << 4) /* RO over current active */
	129	#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
	130	#define EHCI_PS_PE (1 << 2) /* RW port enable */
	131	#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
	132	#define EHCI_PS_CS (1 << 0) /* RO connect status */
aaf098cf MT	133	#define EHCI_PS_CLEAR (EHCI_PS_OCC \| EHCI_PS_PEC \| EHCI_PS_CSC)
aaf098cf MT	134
c0d722fe	135	#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
aaf098cf MT	136
	137	/*
	138	* Schedule Interface Space.
	139	*
	140	* IMPORTANT: Software must ensure that no interface data structure
	141	* reachable by the EHCI host controller spans a 4K page boundary!
	142	*
	143	* Periodic transfers (i.e. isochronous and interrupt transfers) are
	144	* not supported.
	145	*/
	146
	147	/* Queue Element Transfer Descriptor (qTD). */
	148	struct qTD {
3ed16071	149	/* this part defined by EHCI spec */
cdeb9161	150	uint32_t qt_next; /* see EHCI 3.5.1 */
aaf098cf	151	#define QT_NEXT_TERMINATE 1
cdeb9161 BT	152	uint32_t qt_altnext; /* see EHCI 3.5.2 */
cdeb9161 BT	153	uint32_t qt_token; /* see EHCI 3.5.3 */
14eb79b7 BT	154	#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
	155	#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
	156	#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
	157	#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
	158	#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
	159	#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
	160	#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
	161	#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
	162	#define QT_TOKEN_PID_OUT 0x0
	163	#define QT_TOKEN_PID_IN 0x1
	164	#define QT_TOKEN_PID_SETUP 0x2
	165	#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
	166	#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
	167	#define QT_TOKEN_STATUS_ACTIVE 0x80
	168	#define QT_TOKEN_STATUS_HALTED 0x40
	169	#define QT_TOKEN_STATUS_DATBUFERR 0x20
	170	#define QT_TOKEN_STATUS_BABBLEDET 0x10
	171	#define QT_TOKEN_STATUS_XACTERR 0x08
	172	#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
	173	#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
	174	#define QT_TOKEN_STATUS_PERR 0x01
cdeb9161 BT	175	#define QT_BUFFER_CNT 5
	176	uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
	177	uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
3ed16071 WD	178	/* pad struct for 32 byte alignment */
3ed16071 WD	179	uint32_t unused[3];
8b675fe1	180	};
aaf098cf	181
14eb79b7 BT	182	#define EHCI_PAGE_SIZE 4096
14eb79b7 BT	183
aaf098cf MT	184	/* Queue Head (QH). */
	185	struct QH {
	186	uint32_t qh_link;
	187	#define QH_LINK_TERMINATE 1
	188	#define QH_LINK_TYPE_ITD 0
	189	#define QH_LINK_TYPE_QH 2
	190	#define QH_LINK_TYPE_SITD 4
	191	#define QH_LINK_TYPE_FSTN 6
	192	uint32_t qh_endpt1;
14eb79b7 BT	193	#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
	194	#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
	195	#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
	196	#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
	197	#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
	198	#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
	199	#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
	200	#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
	201	#define QH_ENDPT1_EPS_FS 0x0
	202	#define QH_ENDPT1_EPS_LS 0x1
	203	#define QH_ENDPT1_EPS_HS 0x2
	204	#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
	205	#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
	206	#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
aaf098cf	207	uint32_t qh_endpt2;
14eb79b7 BT	208	#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
	209	#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
	210	#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
	211	#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
	212	#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
aaf098cf MT	213	uint32_t qh_curtd;
aaf098cf MT	214	struct qTD qh_overlay;
daa2dafb SR	215	/*
	216	* Add dummy fill value to make the size of this struct
	217	* aligned to 32 bytes
	218	*/
8f62ca64	219	union {
61755c79	220	uint32_t fill[4];
8f62ca64 PG	221	void *buffer;
8f62ca64 PG	222	};
aaf098cf MT	223	};
aaf098cf MT	224
7372b5bd SG	225	/* Tweak flags for EHCI, used to control operation */
	226	enum {
	227	/* don't use or_configflag in init */
	228	EHCI_TWEAK_NO_INIT_CF = 1 << 0,
	229	};
	230
deb8508c SG	231	struct ehci_ctrl;
	232
	233	struct ehci_ops {
	234	void (set_usb_mode)(struct ehci_ctrl ctrl);
	235	int (get_port_speed)(struct ehci_ctrl ctrl, uint32_t reg);
	236	void (powerup_fixup)(struct ehci_ctrl ctrl, uint32_t *status_reg,
	237	uint32_t *reg);
	238	uint32_t (get_portsc_register)(struct ehci_ctrl *ctrl, int port);
3f9f8a5b	239	int (init_after_reset)(struct ehci_ctrl ctrl);
deb8508c SG	240	};
deb8508c SG	241
b959655f	242	struct ehci_ctrl {
49b4c5c7	243	enum usb_init_type init;
b959655f MV	244	struct ehci_hccr hccr; / R/O registers, not need for volatile */
	245	struct ehci_hcor *hcor;
	246	int rootdev;
	247	uint16_t portreset;
	248	struct QH qh_list __aligned(USB_DMA_MINALIGN);
	249	struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
	250	uint32_t *periodic_list;
36b73109	251	int periodic_schedules;
b959655f	252	int ntds;
deb8508c	253	struct ehci_ops ops;
c4a3141d	254	void priv; / client's private data */
b959655f MV	255	};
b959655f MV	256
c4a3141d	257	/**
deb8508c	258	* ehci_set_controller_info() - Set up private data for the controller
c4a3141d SG	259	*
	260	* This function can be called in ehci_hcd_init() to tell the EHCI layer
	261	* about the controller's private data pointer. Then in the above functions
deb8508c SG	262	* this can be accessed given the struct ehci_ctrl pointer. Also special
deb8508c SG	263	* EHCI operation methods can be provided if required
c4a3141d SG	264	*
	265	* @index: Controller number to set
	266	* @priv: Controller pointer
deb8508c	267	* @ops: Controller operations, or NULL to use default
c4a3141d	268	*/
deb8508c SG	269	void ehci_set_controller_priv(int index, void *priv,
deb8508c SG	270	const struct ehci_ops *ops);
c4a3141d SG	271
	272	/**
	273	* ehci_get_controller_priv() - Get controller private data
	274	*
	275	* @index Controller number to get
	276	* @return controller pointer for this index
	277	*/
	278	void *ehci_get_controller_priv(int index);
	279
c0d722fe	280	/* Low level init functions */
127efc4f TK	281	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	282	struct ehci_hccr hccr, struct ehci_hcor hcor);
676ae068	283	int ehci_hcd_stop(int index);
c0d722fe	284
46b01797 SG	285	int ehci_register(struct udevice dev, struct ehci_hccr hccr,
	286	struct ehci_hcor hcor, const struct ehci_ops ops,
	287	uint tweaks, enum usb_init_type init);
	288	int ehci_deregister(struct udevice *dev);
	289	extern struct dm_usb_ops ehci_usb_ops;
	290
aaf098cf	291	#endif /* USB_EHCI_H */