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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * [ Initialisation is based on Linus' ] |
8 | * [ uhci code and gregs ohci fragments ] | |
9 | * [ (C) Copyright 1999 Linus Torvalds ] | |
10 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
11 | * |
12 | * | |
1da177e4 LT |
13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
14 | * interfaces (though some non-x86 Intel chips use it). It supports | |
15 | * smarter hardware than UHCI. A download link for the spec available | |
16 | * through the http://www.usb.org website. | |
17 | * | |
1da177e4 LT |
18 | * This file is licenced under the GPL. |
19 | */ | |
dd9048af | 20 | |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/slab.h> | |
1da177e4 LT |
29 | #include <linux/errno.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/list.h> | |
1da177e4 | 33 | #include <linux/usb.h> |
3a16f7b4 | 34 | #include <linux/usb/otg.h> |
27729aad | 35 | #include <linux/usb/hcd.h> |
dd9048af | 36 | #include <linux/dma-mapping.h> |
f4df0e33 | 37 | #include <linux/dmapool.h> |
d576bb9f | 38 | #include <linux/workqueue.h> |
684c19e0 | 39 | #include <linux/debugfs.h> |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/unaligned.h> | |
45 | #include <asm/byteorder.h> | |
46 | ||
47 | ||
1da177e4 LT |
48 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
49 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
50 | ||
51 | /*-------------------------------------------------------------------------*/ | |
52 | ||
8de98402 | 53 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
54 | |
55 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 56 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 57 | #define OHCI_INTR_INIT \ |
d413984a DB |
58 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
59 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
60 | |
61 | #ifdef __hppa__ | |
62 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
63 | #define IR_DISABLE | |
64 | #endif | |
65 | ||
66 | #ifdef CONFIG_ARCH_OMAP | |
67 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
68 | #define IR_DISABLE | |
69 | #endif | |
70 | ||
71 | /*-------------------------------------------------------------------------*/ | |
72 | ||
73 | static const char hcd_name [] = "ohci_hcd"; | |
74 | ||
d413984a DB |
75 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
76 | ||
1da177e4 | 77 | #include "ohci.h" |
ad93562b | 78 | #include "pci-quirks.h" |
1da177e4 LT |
79 | |
80 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
81 | static int ohci_init (struct ohci_hcd *ohci); | |
82 | static void ohci_stop (struct usb_hcd *hcd); | |
da6fb570 DB |
83 | |
84 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) | |
d576bb9f | 85 | static int ohci_restart (struct ohci_hcd *ohci); |
da6fb570 | 86 | #endif |
1da177e4 | 87 | |
ab1666c1 | 88 | #ifdef CONFIG_PCI |
a1f17a87 | 89 | static void sb800_prefetch(struct ohci_hcd *ohci, int on); |
ab1666c1 | 90 | #else |
a1f17a87 LY |
91 | static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) |
92 | { | |
93 | return; | |
94 | } | |
ab1666c1 LY |
95 | #endif |
96 | ||
97 | ||
1da177e4 LT |
98 | #include "ohci-hub.c" |
99 | #include "ohci-dbg.c" | |
100 | #include "ohci-mem.c" | |
101 | #include "ohci-q.c" | |
102 | ||
103 | ||
104 | /* | |
105 | * On architectures with edge-triggered interrupts we must never return | |
106 | * IRQ_NONE. | |
107 | */ | |
108 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
109 | #define IRQ_NOTMINE IRQ_HANDLED | |
110 | #else | |
111 | #define IRQ_NOTMINE IRQ_NONE | |
112 | #endif | |
113 | ||
114 | ||
115 | /* Some boards misreport power switching/overcurrent */ | |
116 | static int distrust_firmware = 1; | |
117 | module_param (distrust_firmware, bool, 0); | |
118 | MODULE_PARM_DESC (distrust_firmware, | |
119 | "true to distrust firmware power/overcurrent setup"); | |
120 | ||
121 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
122 | static int no_handshake = 0; | |
123 | module_param (no_handshake, bool, 0); | |
124 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
125 | ||
126 | /*-------------------------------------------------------------------------*/ | |
127 | ||
128 | /* | |
129 | * queue up an urb for anything except the root hub | |
130 | */ | |
131 | static int ohci_urb_enqueue ( | |
132 | struct usb_hcd *hcd, | |
1da177e4 | 133 | struct urb *urb, |
55016f10 | 134 | gfp_t mem_flags |
1da177e4 LT |
135 | ) { |
136 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
137 | struct ed *ed; | |
138 | urb_priv_t *urb_priv; | |
139 | unsigned int pipe = urb->pipe; | |
140 | int i, size = 0; | |
141 | unsigned long flags; | |
142 | int retval = 0; | |
dd9048af | 143 | |
1da177e4 | 144 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 145 | urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); |
1da177e4 | 146 | #endif |
dd9048af | 147 | |
1da177e4 | 148 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
e9df41c5 | 149 | if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) |
1da177e4 LT |
150 | return -ENOMEM; |
151 | ||
152 | /* for the private part of the URB we need the number of TDs (size) */ | |
153 | switch (ed->type) { | |
154 | case PIPE_CONTROL: | |
155 | /* td_submit_urb() doesn't yet handle these */ | |
156 | if (urb->transfer_buffer_length > 4096) | |
157 | return -EMSGSIZE; | |
158 | ||
159 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
160 | size = 2; | |
161 | /* FALLTHROUGH */ | |
162 | // case PIPE_INTERRUPT: | |
163 | // case PIPE_BULK: | |
164 | default: | |
25985edc | 165 | /* one TD for every 4096 Bytes (can be up to 8K) */ |
1da177e4 LT |
166 | size += urb->transfer_buffer_length / 4096; |
167 | /* ... and for any remaining bytes ... */ | |
168 | if ((urb->transfer_buffer_length % 4096) != 0) | |
169 | size++; | |
170 | /* ... and maybe a zero length packet to wrap it up */ | |
171 | if (size == 0) | |
172 | size++; | |
173 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
174 | && (urb->transfer_buffer_length | |
175 | % usb_maxpacket (urb->dev, pipe, | |
176 | usb_pipeout (pipe))) == 0) | |
177 | size++; | |
178 | break; | |
179 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
180 | size = urb->number_of_packets; | |
181 | break; | |
182 | } | |
183 | ||
184 | /* allocate the private part of the URB */ | |
dd00cc48 | 185 | urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
1da177e4 LT |
186 | mem_flags); |
187 | if (!urb_priv) | |
188 | return -ENOMEM; | |
1da177e4 LT |
189 | INIT_LIST_HEAD (&urb_priv->pending); |
190 | urb_priv->length = size; | |
dd9048af | 191 | urb_priv->ed = ed; |
1da177e4 LT |
192 | |
193 | /* allocate the TDs (deferring hash chain updates) */ | |
194 | for (i = 0; i < size; i++) { | |
195 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
196 | if (!urb_priv->td [i]) { | |
197 | urb_priv->length = i; | |
198 | urb_free_priv (ohci, urb_priv); | |
199 | return -ENOMEM; | |
200 | } | |
dd9048af | 201 | } |
1da177e4 LT |
202 | |
203 | spin_lock_irqsave (&ohci->lock, flags); | |
204 | ||
205 | /* don't submit to a dead HC */ | |
541c7d43 | 206 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
8de98402 BH |
207 | retval = -ENODEV; |
208 | goto fail; | |
209 | } | |
1da177e4 LT |
210 | if (!HC_IS_RUNNING(hcd->state)) { |
211 | retval = -ENODEV; | |
212 | goto fail; | |
213 | } | |
e9df41c5 AS |
214 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
215 | if (retval) | |
1da177e4 | 216 | goto fail; |
1da177e4 LT |
217 | |
218 | /* schedule the ed if needed */ | |
219 | if (ed->state == ED_IDLE) { | |
220 | retval = ed_schedule (ohci, ed); | |
e9df41c5 AS |
221 | if (retval < 0) { |
222 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
223 | goto fail; | |
224 | } | |
1da177e4 LT |
225 | if (ed->type == PIPE_ISOCHRONOUS) { |
226 | u16 frame = ohci_frame_no(ohci); | |
227 | ||
228 | /* delay a few frames before the first TD */ | |
229 | frame += max_t (u16, 8, ed->interval); | |
230 | frame &= ~(ed->interval - 1); | |
231 | frame |= ed->branch; | |
232 | urb->start_frame = frame; | |
233 | ||
234 | /* yes, only URB_ISO_ASAP is supported, and | |
235 | * urb->start_frame is never used as input. | |
236 | */ | |
237 | } | |
238 | } else if (ed->type == PIPE_ISOCHRONOUS) | |
239 | urb->start_frame = ed->last_iso + ed->interval; | |
240 | ||
241 | /* fill the TDs and link them to the ed; and | |
242 | * enable that part of the schedule, if needed | |
243 | * and update count of queued periodic urbs | |
244 | */ | |
245 | urb->hcpriv = urb_priv; | |
246 | td_submit_urb (ohci, urb); | |
247 | ||
1da177e4 LT |
248 | fail: |
249 | if (retval) | |
250 | urb_free_priv (ohci, urb_priv); | |
251 | spin_unlock_irqrestore (&ohci->lock, flags); | |
252 | return retval; | |
253 | } | |
254 | ||
255 | /* | |
55d84968 AS |
256 | * decouple the URB from the HC queues (TDs, urb_priv). |
257 | * reporting is always done | |
1da177e4 LT |
258 | * asynchronously, and we might be dealing with an urb that's |
259 | * partially transferred, or an ED with other urbs being unlinked. | |
260 | */ | |
e9df41c5 | 261 | static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
262 | { |
263 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
264 | unsigned long flags; | |
e9df41c5 | 265 | int rc; |
dd9048af | 266 | |
1da177e4 | 267 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 268 | urb_print(urb, "UNLINK", 1, status); |
dd9048af | 269 | #endif |
1da177e4 LT |
270 | |
271 | spin_lock_irqsave (&ohci->lock, flags); | |
e9df41c5 AS |
272 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
273 | if (rc) { | |
274 | ; /* Do nothing */ | |
275 | } else if (HC_IS_RUNNING(hcd->state)) { | |
1da177e4 LT |
276 | urb_priv_t *urb_priv; |
277 | ||
278 | /* Unless an IRQ completed the unlink while it was being | |
279 | * handed to us, flag it for unlink and giveback, and force | |
280 | * some upcoming INTR_SF to call finish_unlinks() | |
281 | */ | |
282 | urb_priv = urb->hcpriv; | |
283 | if (urb_priv) { | |
284 | if (urb_priv->ed->state == ED_OPER) | |
285 | start_ed_unlink (ohci, urb_priv->ed); | |
286 | } | |
287 | } else { | |
288 | /* | |
289 | * with HC dead, we won't respect hc queue pointers | |
290 | * any more ... just clean up every urb's memory. | |
291 | */ | |
292 | if (urb->hcpriv) | |
55d84968 | 293 | finish_urb(ohci, urb, status); |
1da177e4 LT |
294 | } |
295 | spin_unlock_irqrestore (&ohci->lock, flags); | |
e9df41c5 | 296 | return rc; |
1da177e4 LT |
297 | } |
298 | ||
299 | /*-------------------------------------------------------------------------*/ | |
300 | ||
301 | /* frees config/altsetting state for endpoints, | |
302 | * including ED memory, dummy TD, and bulk/intr data toggle | |
303 | */ | |
304 | ||
305 | static void | |
306 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
307 | { | |
308 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
309 | unsigned long flags; | |
310 | struct ed *ed = ep->hcpriv; | |
311 | unsigned limit = 1000; | |
312 | ||
313 | /* ASSERT: any requests/urbs are being unlinked */ | |
314 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
315 | ||
316 | if (!ed) | |
317 | return; | |
318 | ||
319 | rescan: | |
320 | spin_lock_irqsave (&ohci->lock, flags); | |
321 | ||
322 | if (!HC_IS_RUNNING (hcd->state)) { | |
323 | sanitize: | |
324 | ed->state = ED_IDLE; | |
89a0fd18 MN |
325 | if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) |
326 | ohci->eds_scheduled--; | |
7d12e780 | 327 | finish_unlinks (ohci, 0); |
1da177e4 LT |
328 | } |
329 | ||
330 | switch (ed->state) { | |
331 | case ED_UNLINK: /* wait for hw to finish? */ | |
332 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
333 | if (limit-- == 0) { | |
89a0fd18 MN |
334 | ohci_warn(ohci, "ED unlink timeout\n"); |
335 | if (quirk_zfmicro(ohci)) { | |
336 | ohci_warn(ohci, "Attempting ZF TD recovery\n"); | |
337 | ohci->ed_to_check = ed; | |
338 | ohci->zf_delay = 2; | |
339 | } | |
1da177e4 LT |
340 | goto sanitize; |
341 | } | |
342 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 343 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
344 | goto rescan; |
345 | case ED_IDLE: /* fully unlinked */ | |
346 | if (list_empty (&ed->td_list)) { | |
347 | td_free (ohci, ed->dummy); | |
348 | ed_free (ohci, ed); | |
349 | break; | |
350 | } | |
351 | /* else FALL THROUGH */ | |
352 | default: | |
353 | /* caller was supposed to have unlinked any requests; | |
354 | * that's not our job. can't recover; must leak ed. | |
355 | */ | |
356 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
357 | ed, ep->desc.bEndpointAddress, ed->state, | |
358 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
359 | td_free (ohci, ed->dummy); | |
360 | break; | |
361 | } | |
362 | ep->hcpriv = NULL; | |
363 | spin_unlock_irqrestore (&ohci->lock, flags); | |
1da177e4 LT |
364 | } |
365 | ||
366 | static int ohci_get_frame (struct usb_hcd *hcd) | |
367 | { | |
368 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
369 | ||
370 | return ohci_frame_no(ohci); | |
371 | } | |
372 | ||
373 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
374 | { | |
375 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
376 | ohci->hc_control &= OHCI_CTRL_RWC; | |
377 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
378 | } | |
379 | ||
64a21d02 | 380 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
381 | * other cases where the next software may expect clean state from the |
382 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
383 | */ | |
64a21d02 AG |
384 | static void |
385 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
386 | { |
387 | struct ohci_hcd *ohci; | |
388 | ||
64a21d02 | 389 | ohci = hcd_to_ohci (hcd); |
f4df0e33 | 390 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3df7169e AS |
391 | ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); |
392 | ||
393 | /* If the SHUTDOWN quirk is set, don't put the controller in RESET */ | |
394 | ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ? | |
395 | OHCI_CTRL_RWC | OHCI_CTRL_HCFS : | |
396 | OHCI_CTRL_RWC); | |
397 | ohci_writel(ohci, ohci->hc_control, &ohci->regs->control); | |
398 | ||
f4df0e33 DB |
399 | /* flush the writes */ |
400 | (void) ohci_readl (ohci, &ohci->regs->control); | |
f4df0e33 DB |
401 | } |
402 | ||
89a0fd18 MN |
403 | static int check_ed(struct ohci_hcd *ohci, struct ed *ed) |
404 | { | |
405 | return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 | |
406 | && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) | |
407 | == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) | |
408 | && !list_empty(&ed->td_list); | |
409 | } | |
410 | ||
411 | /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes | |
412 | * an interrupt TD but neglects to add it to the donelist. On systems with | |
413 | * this chipset, we need to periodically check the state of the queues to look | |
414 | * for such "lost" TDs. | |
415 | */ | |
416 | static void unlink_watchdog_func(unsigned long _ohci) | |
417 | { | |
da6fb570 | 418 | unsigned long flags; |
89a0fd18 MN |
419 | unsigned max; |
420 | unsigned seen_count = 0; | |
421 | unsigned i; | |
422 | struct ed **seen = NULL; | |
423 | struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; | |
424 | ||
425 | spin_lock_irqsave(&ohci->lock, flags); | |
426 | max = ohci->eds_scheduled; | |
427 | if (!max) | |
428 | goto done; | |
429 | ||
430 | if (ohci->ed_to_check) | |
431 | goto out; | |
432 | ||
433 | seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); | |
434 | if (!seen) | |
435 | goto out; | |
436 | ||
437 | for (i = 0; i < NUM_INTS; i++) { | |
438 | struct ed *ed = ohci->periodic[i]; | |
439 | ||
440 | while (ed) { | |
441 | unsigned temp; | |
442 | ||
443 | /* scan this branch of the periodic schedule tree */ | |
444 | for (temp = 0; temp < seen_count; temp++) { | |
445 | if (seen[temp] == ed) { | |
446 | /* we've checked it and what's after */ | |
447 | ed = NULL; | |
448 | break; | |
449 | } | |
450 | } | |
451 | if (!ed) | |
452 | break; | |
453 | seen[seen_count++] = ed; | |
454 | if (!check_ed(ohci, ed)) { | |
455 | ed = ed->ed_next; | |
456 | continue; | |
457 | } | |
458 | ||
459 | /* HC's TD list is empty, but HCD sees at least one | |
460 | * TD that's not been sent through the donelist. | |
461 | */ | |
462 | ohci->ed_to_check = ed; | |
463 | ohci->zf_delay = 2; | |
464 | ||
465 | /* The HC may wait until the next frame to report the | |
466 | * TD as done through the donelist and INTR_WDH. (We | |
467 | * just *assume* it's not a multi-TD interrupt URB; | |
468 | * those could defer the IRQ more than one frame, using | |
469 | * DI...) Check again after the next INTR_SF. | |
470 | */ | |
471 | ohci_writel(ohci, OHCI_INTR_SF, | |
472 | &ohci->regs->intrstatus); | |
473 | ohci_writel(ohci, OHCI_INTR_SF, | |
474 | &ohci->regs->intrenable); | |
475 | ||
476 | /* flush those writes */ | |
477 | (void) ohci_readl(ohci, &ohci->regs->control); | |
478 | ||
479 | goto out; | |
480 | } | |
481 | } | |
482 | out: | |
483 | kfree(seen); | |
484 | if (ohci->eds_scheduled) | |
9cebcdc7 | 485 | mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); |
89a0fd18 MN |
486 | done: |
487 | spin_unlock_irqrestore(&ohci->lock, flags); | |
488 | } | |
489 | ||
1da177e4 LT |
490 | /*-------------------------------------------------------------------------* |
491 | * HC functions | |
492 | *-------------------------------------------------------------------------*/ | |
493 | ||
494 | /* init memory, and kick BIOS/SMM off */ | |
495 | ||
496 | static int ohci_init (struct ohci_hcd *ohci) | |
497 | { | |
498 | int ret; | |
6a9062f3 | 499 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 500 | |
1133cd8a DB |
501 | if (distrust_firmware) |
502 | ohci->flags |= OHCI_QUIRK_HUB_POWER; | |
503 | ||
1da177e4 | 504 | disable (ohci); |
6a9062f3 | 505 | ohci->regs = hcd->regs; |
1da177e4 | 506 | |
6a9062f3 DB |
507 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
508 | * was never needed for most non-PCI systems ... remove the code? | |
509 | */ | |
510 | ||
1da177e4 LT |
511 | #ifndef IR_DISABLE |
512 | /* SMM owns the HC? not for long! */ | |
513 | if (!no_handshake && ohci_readl (ohci, | |
514 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
515 | u32 temp; | |
516 | ||
517 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
518 | ||
519 | /* this timeout is arbitrary. we make it long, so systems | |
520 | * depending on usb keyboards may be usable even if the | |
521 | * BIOS/SMM code seems pretty broken. | |
522 | */ | |
523 | temp = 500; /* arbitrary: five seconds */ | |
524 | ||
525 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
526 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
527 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
528 | msleep (10); | |
529 | if (--temp == 0) { | |
530 | ohci_err (ohci, "USB HC takeover failed!" | |
531 | " (BIOS/SMM bug)\n"); | |
532 | return -EBUSY; | |
533 | } | |
534 | } | |
535 | ohci_usb_reset (ohci); | |
536 | } | |
537 | #endif | |
538 | ||
539 | /* Disable HC interrupts */ | |
540 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
541 | |
542 | /* flush the writes, and save key bits like RWC */ | |
543 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
544 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 545 | |
fdd13b36 DB |
546 | /* Read the number of ports unless overridden */ |
547 | if (ohci->num_ports == 0) | |
548 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
549 | ||
1da177e4 LT |
550 | if (ohci->hcca) |
551 | return 0; | |
552 | ||
6a9062f3 | 553 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
554 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
555 | if (!ohci->hcca) | |
556 | return -ENOMEM; | |
557 | ||
558 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
559 | ohci_stop (hcd); |
560 | else { | |
6a9062f3 DB |
561 | create_debug_files (ohci); |
562 | } | |
1da177e4 LT |
563 | |
564 | return ret; | |
1da177e4 LT |
565 | } |
566 | ||
567 | /*-------------------------------------------------------------------------*/ | |
568 | ||
569 | /* Start an OHCI controller, set the BUS operational | |
570 | * resets USB and controller | |
dd9048af | 571 | * enable interrupts |
1da177e4 LT |
572 | */ |
573 | static int ohci_run (struct ohci_hcd *ohci) | |
574 | { | |
96f90a8b | 575 | u32 mask, val; |
1da177e4 | 576 | int first = ohci->fminterval == 0; |
6a9062f3 | 577 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
578 | |
579 | disable (ohci); | |
580 | ||
581 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
582 | if (first) { | |
583 | ||
96f90a8b HS |
584 | val = ohci_readl (ohci, &ohci->regs->fminterval); |
585 | ohci->fminterval = val & 0x3fff; | |
1da177e4 LT |
586 | if (ohci->fminterval != FI) |
587 | ohci_dbg (ohci, "fminterval delta %d\n", | |
588 | ohci->fminterval - FI); | |
589 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
590 | /* also: power/overcurrent flags in roothub.a */ | |
591 | } | |
592 | ||
6fd9086a AS |
593 | /* Reset USB nearly "by the book". RemoteWakeupConnected has |
594 | * to be checked in case boot firmware (BIOS/SMM/...) has set up | |
595 | * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). | |
596 | * If the bus glue detected wakeup capability then it should | |
bcca06ef | 597 | * already be enabled; if so we'll just enable it again. |
1da177e4 | 598 | */ |
bcca06ef AS |
599 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) |
600 | device_set_wakeup_capable(hcd->self.controller, 1); | |
1da177e4 LT |
601 | |
602 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
603 | case OHCI_USB_OPER: | |
96f90a8b | 604 | val = 0; |
1da177e4 LT |
605 | break; |
606 | case OHCI_USB_SUSPEND: | |
607 | case OHCI_USB_RESUME: | |
608 | ohci->hc_control &= OHCI_CTRL_RWC; | |
609 | ohci->hc_control |= OHCI_USB_RESUME; | |
96f90a8b | 610 | val = 10 /* msec wait */; |
1da177e4 LT |
611 | break; |
612 | // case OHCI_USB_RESET: | |
613 | default: | |
614 | ohci->hc_control &= OHCI_CTRL_RWC; | |
615 | ohci->hc_control |= OHCI_USB_RESET; | |
96f90a8b | 616 | val = 50 /* msec wait */; |
1da177e4 LT |
617 | break; |
618 | } | |
619 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
620 | // flush the writes | |
621 | (void) ohci_readl (ohci, &ohci->regs->control); | |
96f90a8b | 622 | msleep(val); |
383975d7 | 623 | |
1da177e4 LT |
624 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
625 | ||
626 | /* 2msec timelimit here means no irqs/preempt */ | |
627 | spin_lock_irq (&ohci->lock); | |
628 | ||
629 | retry: | |
630 | /* HC Reset requires max 10 us delay */ | |
631 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
96f90a8b | 632 | val = 30; /* ... allow extra time */ |
1da177e4 | 633 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
96f90a8b | 634 | if (--val == 0) { |
1da177e4 LT |
635 | spin_unlock_irq (&ohci->lock); |
636 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
637 | return -1; | |
638 | } | |
639 | udelay (1); | |
640 | } | |
641 | ||
642 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
643 | * within 2msec else HC enters RESUME | |
644 | * | |
645 | * ... but some hardware won't init fmInterval "by the book" | |
646 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
647 | * this if we write fmInterval after we're OPERATIONAL. | |
648 | * Unclear about ALi, ServerWorks, and others ... this could | |
649 | * easily be a longstanding bug in chip init on Linux. | |
650 | */ | |
651 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
652 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
653 | // flush those writes | |
654 | (void) ohci_readl (ohci, &ohci->regs->control); | |
655 | } | |
656 | ||
657 | /* Tell the controller where the control and bulk lists are | |
658 | * The lists are empty now. */ | |
659 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
660 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
661 | ||
662 | /* a reset clears this */ | |
663 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
664 | ||
665 | periodic_reinit (ohci); | |
666 | ||
667 | /* some OHCI implementations are finicky about how they init. | |
668 | * bogus values here mean not even enumeration could work. | |
669 | */ | |
670 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
671 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
672 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
673 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
674 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
675 | goto retry; | |
676 | } | |
677 | spin_unlock_irq (&ohci->lock); | |
678 | ohci_err (ohci, "init err (%08x %04x)\n", | |
679 | ohci_readl (ohci, &ohci->regs->fminterval), | |
680 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
681 | return -EOVERFLOW; | |
682 | } | |
683 | ||
d413984a | 684 | /* use rhsc irqs after khubd is fully initialized */ |
541c7d43 | 685 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
d413984a DB |
686 | hcd->uses_new_polling = 1; |
687 | ||
688 | /* start controller operations */ | |
1da177e4 | 689 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
690 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
691 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
6a9062f3 | 692 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
693 | |
694 | /* wake on ConnectStatusChange, matching external hubs */ | |
695 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
696 | ||
697 | /* Choose the interrupts we care about now, others later on demand */ | |
698 | mask = OHCI_INTR_INIT; | |
d413984a | 699 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
700 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
701 | ||
702 | /* handle root hub init quirks ... */ | |
96f90a8b HS |
703 | val = roothub_a (ohci); |
704 | val &= ~(RH_A_PSM | RH_A_OCPM); | |
1da177e4 LT |
705 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
706 | /* NSC 87560 and maybe others */ | |
96f90a8b HS |
707 | val |= RH_A_NOCP; |
708 | val &= ~(RH_A_POTPGT | RH_A_NPS); | |
709 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1133cd8a DB |
710 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || |
711 | (ohci->flags & OHCI_QUIRK_HUB_POWER)) { | |
1da177e4 LT |
712 | /* hub power always on; required for AMD-756 and some |
713 | * Mac platforms. ganged overcurrent reporting, if any. | |
714 | */ | |
96f90a8b HS |
715 | val |= RH_A_NPS; |
716 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1da177e4 LT |
717 | } |
718 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
96f90a8b | 719 | ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, |
1da177e4 LT |
720 | &ohci->regs->roothub.b); |
721 | // flush those writes | |
722 | (void) ohci_readl (ohci, &ohci->regs->control); | |
723 | ||
d413984a | 724 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
725 | spin_unlock_irq (&ohci->lock); |
726 | ||
727 | // POTPGT delay is bits 24-31, in 2 ms units. | |
96f90a8b | 728 | mdelay ((val >> 23) & 0x1fe); |
6a9062f3 | 729 | hcd->state = HC_STATE_RUNNING; |
1da177e4 | 730 | |
89a0fd18 MN |
731 | if (quirk_zfmicro(ohci)) { |
732 | /* Create timer to watch for bad queue state on ZF Micro */ | |
733 | setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, | |
734 | (unsigned long) ohci); | |
735 | ||
736 | ohci->eds_scheduled = 0; | |
737 | ohci->ed_to_check = NULL; | |
738 | } | |
739 | ||
1da177e4 LT |
740 | ohci_dump (ohci, 1); |
741 | ||
1da177e4 LT |
742 | return 0; |
743 | } | |
744 | ||
745 | /*-------------------------------------------------------------------------*/ | |
746 | ||
747 | /* an interrupt happens */ | |
748 | ||
7d12e780 | 749 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
750 | { |
751 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
752 | struct ohci_regs __iomem *regs = ohci->regs; | |
89a0fd18 | 753 | int ints; |
1da177e4 | 754 | |
565227c0 BH |
755 | /* Read interrupt status (and flush pending writes). We ignore the |
756 | * optimization of checking the LSB of hcca->done_head; it doesn't | |
757 | * work on all systems (edge triggering for OHCI can be a factor). | |
89a0fd18 | 758 | */ |
565227c0 | 759 | ints = ohci_readl(ohci, ®s->intrstatus); |
1da177e4 | 760 | |
565227c0 BH |
761 | /* Check for an all 1's result which is a typical consequence |
762 | * of dead, unclocked, or unplugged (CardBus...) devices | |
763 | */ | |
764 | if (ints == ~(u32)0) { | |
1da177e4 LT |
765 | disable (ohci); |
766 | ohci_dbg (ohci, "device removed!\n"); | |
767 | return IRQ_HANDLED; | |
565227c0 BH |
768 | } |
769 | ||
770 | /* We only care about interrupts that are enabled */ | |
771 | ints &= ohci_readl(ohci, ®s->intrenable); | |
1da177e4 LT |
772 | |
773 | /* interrupt for some other device? */ | |
565227c0 | 774 | if (ints == 0) |
1da177e4 | 775 | return IRQ_NOTMINE; |
d413984a | 776 | |
1da177e4 | 777 | if (ints & OHCI_INTR_UE) { |
1da177e4 | 778 | // e.g. due to PCI Master/Target Abort |
89a0fd18 | 779 | if (quirk_nec(ohci)) { |
d576bb9f MH |
780 | /* Workaround for a silicon bug in some NEC chips used |
781 | * in Apple's PowerBooks. Adapted from Darwin code. | |
782 | */ | |
783 | ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); | |
784 | ||
785 | ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); | |
786 | ||
787 | schedule_work (&ohci->nec_work); | |
788 | } else { | |
789 | disable (ohci); | |
790 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | |
791 | } | |
1da177e4 LT |
792 | |
793 | ohci_dump (ohci, 1); | |
794 | ohci_usb_reset (ohci); | |
795 | } | |
796 | ||
583ceada AS |
797 | if (ints & OHCI_INTR_RHSC) { |
798 | ohci_vdbg(ohci, "rhsc\n"); | |
799 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; | |
800 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
801 | ®s->intrstatus); | |
052ac01a AS |
802 | |
803 | /* NOTE: Vendors didn't always make the same implementation | |
804 | * choices for RHSC. Many followed the spec; RHSC triggers | |
805 | * on an edge, like setting and maybe clearing a port status | |
806 | * change bit. With others it's level-triggered, active | |
807 | * until khubd clears all the port status change bits. We'll | |
808 | * always disable it here and rely on polling until khubd | |
809 | * re-enables it. | |
810 | */ | |
811 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
812 | usb_hcd_poll_rh_status(hcd); |
813 | } | |
814 | ||
815 | /* For connect and disconnect events, we expect the controller | |
816 | * to turn on RHSC along with RD. But for remote wakeup events | |
817 | * this might not happen. | |
818 | */ | |
819 | else if (ints & OHCI_INTR_RD) { | |
820 | ohci_vdbg(ohci, "resume detect\n"); | |
821 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); | |
541c7d43 | 822 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
8d1a243b AS |
823 | if (ohci->autostop) { |
824 | spin_lock (&ohci->lock); | |
825 | ohci_rh_resume (ohci); | |
826 | spin_unlock (&ohci->lock); | |
827 | } else | |
f197b2c5 | 828 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
829 | } |
830 | ||
831 | if (ints & OHCI_INTR_WDH) { | |
1da177e4 | 832 | spin_lock (&ohci->lock); |
7d12e780 | 833 | dl_done_list (ohci); |
1da177e4 | 834 | spin_unlock (&ohci->lock); |
1da177e4 | 835 | } |
dd9048af | 836 | |
89a0fd18 MN |
837 | if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { |
838 | spin_lock(&ohci->lock); | |
839 | if (ohci->ed_to_check) { | |
840 | struct ed *ed = ohci->ed_to_check; | |
841 | ||
842 | if (check_ed(ohci, ed)) { | |
843 | /* HC thinks the TD list is empty; HCD knows | |
844 | * at least one TD is outstanding | |
845 | */ | |
846 | if (--ohci->zf_delay == 0) { | |
847 | struct td *td = list_entry( | |
848 | ed->td_list.next, | |
849 | struct td, td_list); | |
850 | ohci_warn(ohci, | |
851 | "Reclaiming orphan TD %p\n", | |
852 | td); | |
853 | takeback_td(ohci, td); | |
854 | ohci->ed_to_check = NULL; | |
855 | } | |
856 | } else | |
857 | ohci->ed_to_check = NULL; | |
858 | } | |
859 | spin_unlock(&ohci->lock); | |
860 | } | |
861 | ||
1da177e4 LT |
862 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
863 | ||
864 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
865 | * when there's still unlinking to be done (next frame). | |
866 | */ | |
867 | spin_lock (&ohci->lock); | |
868 | if (ohci->ed_rm_list) | |
7d12e780 | 869 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
89a0fd18 MN |
870 | if ((ints & OHCI_INTR_SF) != 0 |
871 | && !ohci->ed_rm_list | |
872 | && !ohci->ed_to_check | |
1da177e4 | 873 | && HC_IS_RUNNING(hcd->state)) |
dd9048af | 874 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 LT |
875 | spin_unlock (&ohci->lock); |
876 | ||
877 | if (HC_IS_RUNNING(hcd->state)) { | |
878 | ohci_writel (ohci, ints, ®s->intrstatus); | |
dd9048af | 879 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
880 | // flush those writes |
881 | (void) ohci_readl (ohci, &ohci->regs->control); | |
882 | } | |
883 | ||
884 | return IRQ_HANDLED; | |
885 | } | |
886 | ||
887 | /*-------------------------------------------------------------------------*/ | |
888 | ||
889 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 890 | { |
1da177e4 LT |
891 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
892 | ||
1da177e4 LT |
893 | ohci_dump (ohci, 1); |
894 | ||
569ff2de TH |
895 | if (quirk_nec(ohci)) |
896 | flush_work_sync(&ohci->nec_work); | |
1da177e4 LT |
897 | |
898 | ohci_usb_reset (ohci); | |
899 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
71795c1d PZ |
900 | free_irq(hcd->irq, hcd); |
901 | hcd->irq = -1; | |
902 | ||
89a0fd18 MN |
903 | if (quirk_zfmicro(ohci)) |
904 | del_timer(&ohci->unlink_watchdog); | |
ab1666c1 | 905 | if (quirk_amdiso(ohci)) |
ad93562b | 906 | usb_amd_dev_put(); |
89a0fd18 | 907 | |
1da177e4 LT |
908 | remove_debug_files (ohci); |
909 | ohci_mem_cleanup (ohci); | |
910 | if (ohci->hcca) { | |
dd9048af DB |
911 | dma_free_coherent (hcd->self.controller, |
912 | sizeof *ohci->hcca, | |
1da177e4 LT |
913 | ohci->hcca, ohci->hcca_dma); |
914 | ohci->hcca = NULL; | |
915 | ohci->hcca_dma = 0; | |
916 | } | |
917 | } | |
918 | ||
919 | /*-------------------------------------------------------------------------*/ | |
920 | ||
da6fb570 DB |
921 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) |
922 | ||
1da177e4 | 923 | /* must not be called from interrupt context */ |
1da177e4 LT |
924 | static int ohci_restart (struct ohci_hcd *ohci) |
925 | { | |
926 | int temp; | |
927 | int i; | |
928 | struct urb_priv *priv; | |
1da177e4 | 929 | |
1da177e4 LT |
930 | spin_lock_irq(&ohci->lock); |
931 | disable (ohci); | |
d576bb9f MH |
932 | |
933 | /* Recycle any "live" eds/tds (and urbs). */ | |
1da177e4 LT |
934 | if (!list_empty (&ohci->pending)) |
935 | ohci_dbg(ohci, "abort schedule...\n"); | |
936 | list_for_each_entry (priv, &ohci->pending, pending) { | |
937 | struct urb *urb = priv->td[0]->urb; | |
938 | struct ed *ed = priv->ed; | |
939 | ||
940 | switch (ed->state) { | |
941 | case ED_OPER: | |
942 | ed->state = ED_UNLINK; | |
943 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
944 | ed_deschedule (ohci, ed); | |
945 | ||
946 | ed->ed_next = ohci->ed_rm_list; | |
947 | ed->ed_prev = NULL; | |
948 | ohci->ed_rm_list = ed; | |
949 | /* FALLTHROUGH */ | |
950 | case ED_UNLINK: | |
951 | break; | |
952 | default: | |
953 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
954 | ed, ed->state); | |
955 | } | |
956 | ||
55d84968 AS |
957 | if (!urb->unlinked) |
958 | urb->unlinked = -ESHUTDOWN; | |
1da177e4 | 959 | } |
7d12e780 | 960 | finish_unlinks (ohci, 0); |
1da177e4 LT |
961 | spin_unlock_irq(&ohci->lock); |
962 | ||
963 | /* paranoia, in case that didn't work: */ | |
964 | ||
965 | /* empty the interrupt branches */ | |
966 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
967 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 968 | |
1da177e4 LT |
969 | /* no EDs to remove */ |
970 | ohci->ed_rm_list = NULL; | |
971 | ||
dd9048af | 972 | /* empty control and bulk lists */ |
1da177e4 LT |
973 | ohci->ed_controltail = NULL; |
974 | ohci->ed_bulktail = NULL; | |
975 | ||
976 | if ((temp = ohci_run (ohci)) < 0) { | |
977 | ohci_err (ohci, "can't restart, %d\n", temp); | |
978 | return temp; | |
1da177e4 | 979 | } |
383975d7 | 980 | ohci_dbg(ohci, "restart complete\n"); |
1da177e4 LT |
981 | return 0; |
982 | } | |
d576bb9f | 983 | |
da6fb570 DB |
984 | #endif |
985 | ||
d576bb9f MH |
986 | /*-------------------------------------------------------------------------*/ |
987 | ||
1da177e4 | 988 | MODULE_AUTHOR (DRIVER_AUTHOR); |
2b70f073 | 989 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
990 | MODULE_LICENSE ("GPL"); |
991 | ||
992 | #ifdef CONFIG_PCI | |
993 | #include "ohci-pci.c" | |
5e16fabe | 994 | #define PCI_DRIVER ohci_pci_driver |
1da177e4 LT |
995 | #endif |
996 | ||
6381fad7 | 997 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) |
1da177e4 | 998 | #include "ohci-sa1111.c" |
5e16fabe | 999 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
1000 | #endif |
1001 | ||
3ba5f38f | 1002 | #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) |
3eb0c5f4 | 1003 | #include "ohci-s3c2410.c" |
5e16fabe | 1004 | #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver |
3eb0c5f4 BD |
1005 | #endif |
1006 | ||
968b448b | 1007 | #ifdef CONFIG_USB_OHCI_HCD_OMAP1 |
1da177e4 | 1008 | #include "ohci-omap.c" |
968b448b AG |
1009 | #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver |
1010 | #endif | |
1011 | ||
1012 | #ifdef CONFIG_USB_OHCI_HCD_OMAP3 | |
1013 | #include "ohci-omap3.c" | |
1014 | #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver | |
1da177e4 LT |
1015 | #endif |
1016 | ||
e77ec189 | 1017 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
1da177e4 | 1018 | #include "ohci-pxa27x.c" |
5e16fabe | 1019 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver |
1da177e4 LT |
1020 | #endif |
1021 | ||
a5b7474a LB |
1022 | #ifdef CONFIG_ARCH_EP93XX |
1023 | #include "ohci-ep93xx.c" | |
5e16fabe | 1024 | #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver |
a5b7474a LB |
1025 | #endif |
1026 | ||
42a4f17d | 1027 | #ifdef CONFIG_MIPS_ALCHEMY |
1da177e4 | 1028 | #include "ohci-au1xxx.c" |
5e16fabe | 1029 | #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver |
1da177e4 LT |
1030 | #endif |
1031 | ||
5151d040 VW |
1032 | #ifdef CONFIG_PNX8550 |
1033 | #include "ohci-pnx8550.c" | |
5e16fabe | 1034 | #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver |
5151d040 VW |
1035 | #endif |
1036 | ||
1da177e4 LT |
1037 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC |
1038 | #include "ohci-ppc-soc.c" | |
5e16fabe | 1039 | #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver |
1da177e4 LT |
1040 | #endif |
1041 | ||
58a0cd78 | 1042 | #ifdef CONFIG_ARCH_AT91 |
39a269c0 | 1043 | #include "ohci-at91.c" |
5e16fabe | 1044 | #define PLATFORM_DRIVER ohci_hcd_at91_driver |
39a269c0 AV |
1045 | #endif |
1046 | ||
60bbfc84 VW |
1047 | #ifdef CONFIG_ARCH_PNX4008 |
1048 | #include "ohci-pnx4008.c" | |
5e16fabe | 1049 | #define PLATFORM_DRIVER usb_hcd_pnx4008_driver |
60bbfc84 VW |
1050 | #endif |
1051 | ||
efe7daf2 SS |
1052 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX |
1053 | #include "ohci-da8xx.c" | |
1054 | #define PLATFORM_DRIVER ohci_hcd_da8xx_driver | |
1055 | #endif | |
1056 | ||
60b0bf0f | 1057 | #ifdef CONFIG_USB_OHCI_SH |
828d55c5 YS |
1058 | #include "ohci-sh.c" |
1059 | #define PLATFORM_DRIVER ohci_hcd_sh_driver | |
1060 | #endif | |
1061 | ||
5e16fabe | 1062 | |
495a678f SM |
1063 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
1064 | #include "ohci-ppc-of.c" | |
1065 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
1066 | #endif | |
1067 | ||
c8c38de9 DS |
1068 | #ifdef CONFIG_PLAT_SPEAR |
1069 | #include "ohci-spear.c" | |
1070 | #define PLATFORM_DRIVER spear_ohci_hcd_driver | |
1071 | #endif | |
1072 | ||
6a6c957e GL |
1073 | #ifdef CONFIG_PPC_PS3 |
1074 | #include "ohci-ps3.c" | |
7a4eb7fd | 1075 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
6a6c957e GL |
1076 | #endif |
1077 | ||
c604e851 MB |
1078 | #ifdef CONFIG_USB_OHCI_HCD_SSB |
1079 | #include "ohci-ssb.c" | |
1080 | #define SSB_OHCI_DRIVER ssb_ohci_driver | |
1081 | #endif | |
1082 | ||
f54aab6e MD |
1083 | #ifdef CONFIG_MFD_SM501 |
1084 | #include "ohci-sm501.c" | |
3ee38d8b | 1085 | #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver |
f54aab6e MD |
1086 | #endif |
1087 | ||
78c73414 DB |
1088 | #ifdef CONFIG_MFD_TC6393XB |
1089 | #include "ohci-tmio.c" | |
1090 | #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver | |
2249071b LPC |
1091 | #endif |
1092 | ||
1093 | #ifdef CONFIG_MACH_JZ4740 | |
1094 | #include "ohci-jz4740.c" | |
1095 | #define PLATFORM_DRIVER ohci_hcd_jz4740_driver | |
78c73414 DB |
1096 | #endif |
1097 | ||
1643accd DD |
1098 | #ifdef CONFIG_USB_OCTEON_OHCI |
1099 | #include "ohci-octeon.c" | |
1100 | #define PLATFORM_DRIVER ohci_octeon_driver | |
1101 | #endif | |
1102 | ||
760efe69 ML |
1103 | #ifdef CONFIG_USB_CNS3XXX_OHCI |
1104 | #include "ohci-cns3xxx.c" | |
1105 | #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver | |
1106 | #endif | |
1107 | ||
5e16fabe SM |
1108 | #if !defined(PCI_DRIVER) && \ |
1109 | !defined(PLATFORM_DRIVER) && \ | |
968b448b AG |
1110 | !defined(OMAP1_PLATFORM_DRIVER) && \ |
1111 | !defined(OMAP3_PLATFORM_DRIVER) && \ | |
495a678f | 1112 | !defined(OF_PLATFORM_DRIVER) && \ |
6a6c957e | 1113 | !defined(SA1111_DRIVER) && \ |
c604e851 | 1114 | !defined(PS3_SYSTEM_BUS_DRIVER) && \ |
3ee38d8b | 1115 | !defined(SM501_OHCI_DRIVER) && \ |
78c73414 | 1116 | !defined(TMIO_OHCI_DRIVER) && \ |
c604e851 | 1117 | !defined(SSB_OHCI_DRIVER) |
1da177e4 LT |
1118 | #error "missing bus glue for ohci-hcd" |
1119 | #endif | |
5e16fabe SM |
1120 | |
1121 | static int __init ohci_hcd_mod_init(void) | |
1122 | { | |
1123 | int retval = 0; | |
5e16fabe SM |
1124 | |
1125 | if (usb_disabled()) | |
1126 | return -ENODEV; | |
1127 | ||
2b70f073 | 1128 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); |
5e16fabe SM |
1129 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, |
1130 | sizeof (struct ed), sizeof (struct td)); | |
9beeee65 | 1131 | set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe | 1132 | |
684c19e0 | 1133 | #ifdef DEBUG |
485f4f39 | 1134 | ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); |
684c19e0 TJ |
1135 | if (!ohci_debug_root) { |
1136 | retval = -ENOENT; | |
1137 | goto error_debug; | |
1138 | } | |
1139 | #endif | |
1140 | ||
6a6c957e | 1141 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd GL |
1142 | retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
1143 | if (retval < 0) | |
1144 | goto error_ps3; | |
6a6c957e GL |
1145 | #endif |
1146 | ||
5e16fabe SM |
1147 | #ifdef PLATFORM_DRIVER |
1148 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1149 | if (retval < 0) | |
de44743b | 1150 | goto error_platform; |
5e16fabe SM |
1151 | #endif |
1152 | ||
968b448b AG |
1153 | #ifdef OMAP1_PLATFORM_DRIVER |
1154 | retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); | |
1155 | if (retval < 0) | |
1156 | goto error_omap1_platform; | |
1157 | #endif | |
1158 | ||
1159 | #ifdef OMAP3_PLATFORM_DRIVER | |
1160 | retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); | |
1161 | if (retval < 0) | |
1162 | goto error_omap3_platform; | |
1163 | #endif | |
1164 | ||
495a678f | 1165 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1166 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
495a678f | 1167 | if (retval < 0) |
de44743b | 1168 | goto error_of_platform; |
495a678f SM |
1169 | #endif |
1170 | ||
5e16fabe SM |
1171 | #ifdef SA1111_DRIVER |
1172 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
1173 | if (retval < 0) | |
de44743b | 1174 | goto error_sa1111; |
5e16fabe SM |
1175 | #endif |
1176 | ||
1177 | #ifdef PCI_DRIVER | |
1178 | retval = pci_register_driver(&PCI_DRIVER); | |
1179 | if (retval < 0) | |
de44743b | 1180 | goto error_pci; |
5e16fabe SM |
1181 | #endif |
1182 | ||
c604e851 MB |
1183 | #ifdef SSB_OHCI_DRIVER |
1184 | retval = ssb_driver_register(&SSB_OHCI_DRIVER); | |
1185 | if (retval) | |
1186 | goto error_ssb; | |
1187 | #endif | |
1188 | ||
3ee38d8b BD |
1189 | #ifdef SM501_OHCI_DRIVER |
1190 | retval = platform_driver_register(&SM501_OHCI_DRIVER); | |
1191 | if (retval < 0) | |
1192 | goto error_sm501; | |
1193 | #endif | |
1194 | ||
78c73414 DB |
1195 | #ifdef TMIO_OHCI_DRIVER |
1196 | retval = platform_driver_register(&TMIO_OHCI_DRIVER); | |
1197 | if (retval < 0) | |
1198 | goto error_tmio; | |
1199 | #endif | |
1200 | ||
5e16fabe SM |
1201 | return retval; |
1202 | ||
1203 | /* Error path */ | |
78c73414 DB |
1204 | #ifdef TMIO_OHCI_DRIVER |
1205 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1206 | error_tmio: | |
1207 | #endif | |
3ee38d8b | 1208 | #ifdef SM501_OHCI_DRIVER |
78c73414 | 1209 | platform_driver_unregister(&SM501_OHCI_DRIVER); |
3ee38d8b BD |
1210 | error_sm501: |
1211 | #endif | |
c604e851 | 1212 | #ifdef SSB_OHCI_DRIVER |
78c73414 | 1213 | ssb_driver_unregister(&SSB_OHCI_DRIVER); |
c604e851 MB |
1214 | error_ssb: |
1215 | #endif | |
de44743b | 1216 | #ifdef PCI_DRIVER |
c604e851 | 1217 | pci_unregister_driver(&PCI_DRIVER); |
de44743b BH |
1218 | error_pci: |
1219 | #endif | |
1220 | #ifdef SA1111_DRIVER | |
1221 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1222 | error_sa1111: | |
5e16fabe | 1223 | #endif |
495a678f | 1224 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1225 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
de44743b | 1226 | error_of_platform: |
495a678f | 1227 | #endif |
de44743b BH |
1228 | #ifdef PLATFORM_DRIVER |
1229 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1230 | error_platform: | |
6a6c957e | 1231 | #endif |
968b448b AG |
1232 | #ifdef OMAP1_PLATFORM_DRIVER |
1233 | platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); | |
1234 | error_omap1_platform: | |
1235 | #endif | |
1236 | #ifdef OMAP3_PLATFORM_DRIVER | |
1237 | platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); | |
1238 | error_omap3_platform: | |
1239 | #endif | |
6a6c957e | 1240 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1241 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1242 | error_ps3: |
5e16fabe | 1243 | #endif |
684c19e0 TJ |
1244 | #ifdef DEBUG |
1245 | debugfs_remove(ohci_debug_root); | |
1246 | ohci_debug_root = NULL; | |
1247 | error_debug: | |
1248 | #endif | |
1249 | ||
9beeee65 | 1250 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1251 | return retval; |
1252 | } | |
1253 | module_init(ohci_hcd_mod_init); | |
1254 | ||
1255 | static void __exit ohci_hcd_mod_exit(void) | |
1256 | { | |
78c73414 DB |
1257 | #ifdef TMIO_OHCI_DRIVER |
1258 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1259 | #endif | |
3ee38d8b BD |
1260 | #ifdef SM501_OHCI_DRIVER |
1261 | platform_driver_unregister(&SM501_OHCI_DRIVER); | |
1262 | #endif | |
c604e851 MB |
1263 | #ifdef SSB_OHCI_DRIVER |
1264 | ssb_driver_unregister(&SSB_OHCI_DRIVER); | |
1265 | #endif | |
5e16fabe SM |
1266 | #ifdef PCI_DRIVER |
1267 | pci_unregister_driver(&PCI_DRIVER); | |
1268 | #endif | |
1269 | #ifdef SA1111_DRIVER | |
1270 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1271 | #endif | |
495a678f | 1272 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1273 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
495a678f | 1274 | #endif |
5e16fabe SM |
1275 | #ifdef PLATFORM_DRIVER |
1276 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1277 | #endif | |
ffb6748f KM |
1278 | #ifdef OMAP3_PLATFORM_DRIVER |
1279 | platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); | |
1280 | #endif | |
6a6c957e | 1281 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1282 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1283 | #endif |
684c19e0 TJ |
1284 | #ifdef DEBUG |
1285 | debugfs_remove(ohci_debug_root); | |
1286 | #endif | |
9beeee65 | 1287 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1288 | } |
1289 | module_exit(ohci_hcd_mod_exit); | |
1290 |