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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
f9c589e1 | 69 | #include <linux/dma-mapping.h> |
7f84eef0 | 70 | #include "xhci.h" |
3a7fa5be | 71 | #include "xhci-trace.h" |
0cbd4b34 | 72 | #include "xhci-mtk.h" |
7f84eef0 SS |
73 | |
74 | /* | |
75 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
76 | * address of the TRB. | |
77 | */ | |
23e3be11 | 78 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
79 | union xhci_trb *trb) |
80 | { | |
6071d836 | 81 | unsigned long segment_offset; |
7f84eef0 | 82 | |
6071d836 | 83 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 84 | return 0; |
6071d836 SS |
85 | /* offset in TRBs */ |
86 | segment_offset = trb - seg->trbs; | |
7895086a | 87 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 88 | return 0; |
6071d836 | 89 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
90 | } |
91 | ||
0ce57499 MN |
92 | static bool trb_is_noop(union xhci_trb *trb) |
93 | { | |
94 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
95 | } | |
96 | ||
2d98ef40 MN |
97 | static bool trb_is_link(union xhci_trb *trb) |
98 | { | |
99 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
100 | } | |
101 | ||
bd5e67f5 MN |
102 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
103 | { | |
104 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
105 | } | |
106 | ||
107 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
108 | struct xhci_segment *seg, union xhci_trb *trb) | |
109 | { | |
110 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
111 | } | |
112 | ||
d0c77d84 MN |
113 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
114 | { | |
115 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
116 | } | |
117 | ||
2a72126d MN |
118 | static bool last_td_in_urb(struct xhci_td *td) |
119 | { | |
120 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
121 | ||
9ef7fbbb | 122 | return urb_priv->num_tds_done == urb_priv->num_tds; |
2a72126d MN |
123 | } |
124 | ||
125 | static void inc_td_cnt(struct urb *urb) | |
126 | { | |
127 | struct urb_priv *urb_priv = urb->hcpriv; | |
128 | ||
9ef7fbbb | 129 | urb_priv->num_tds_done++; |
2a72126d MN |
130 | } |
131 | ||
ae1e3f07 MN |
132 | static void trb_to_noop(union xhci_trb *trb, u32 noop_type) |
133 | { | |
134 | if (trb_is_link(trb)) { | |
135 | /* unchain chained link TRBs */ | |
136 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
137 | } else { | |
138 | trb->generic.field[0] = 0; | |
139 | trb->generic.field[1] = 0; | |
140 | trb->generic.field[2] = 0; | |
141 | /* Preserve only the cycle bit of this TRB */ | |
142 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); | |
143 | trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); | |
144 | } | |
145 | } | |
146 | ||
ae636747 SS |
147 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
148 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
149 | * effect the ring dequeue or enqueue pointers. | |
150 | */ | |
151 | static void next_trb(struct xhci_hcd *xhci, | |
152 | struct xhci_ring *ring, | |
153 | struct xhci_segment **seg, | |
154 | union xhci_trb **trb) | |
155 | { | |
2d98ef40 | 156 | if (trb_is_link(*trb)) { |
ae636747 SS |
157 | *seg = (*seg)->next; |
158 | *trb = ((*seg)->trbs); | |
159 | } else { | |
a1669b2c | 160 | (*trb)++; |
ae636747 SS |
161 | } |
162 | } | |
163 | ||
7f84eef0 SS |
164 | /* |
165 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
166 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
167 | */ | |
3b72fca0 | 168 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 169 | { |
bd5e67f5 MN |
170 | /* event ring doesn't have link trbs, check for last trb */ |
171 | if (ring->type == TYPE_EVENT) { | |
172 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 173 | ring->dequeue++; |
bd5e67f5 | 174 | return; |
7f84eef0 | 175 | } |
bd5e67f5 MN |
176 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
177 | ring->cycle_state ^= 1; | |
178 | ring->deq_seg = ring->deq_seg->next; | |
179 | ring->dequeue = ring->deq_seg->trbs; | |
180 | return; | |
181 | } | |
182 | ||
183 | /* All other rings have link trbs */ | |
184 | if (!trb_is_link(ring->dequeue)) { | |
185 | ring->dequeue++; | |
186 | ring->num_trbs_free++; | |
187 | } | |
188 | while (trb_is_link(ring->dequeue)) { | |
189 | ring->deq_seg = ring->deq_seg->next; | |
190 | ring->dequeue = ring->deq_seg->trbs; | |
191 | } | |
b2d6edbb LB |
192 | |
193 | trace_xhci_inc_deq(ring); | |
194 | ||
bd5e67f5 | 195 | return; |
7f84eef0 SS |
196 | } |
197 | ||
198 | /* | |
199 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
200 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
201 | * | |
202 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
203 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
204 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
205 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
206 | * | |
207 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
208 | * set, but other sections talk about dealing with the chain bit set. This was |
209 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
210 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
211 | * |
212 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
213 | * prepare_transfer()? | |
7f84eef0 | 214 | */ |
6cc30d85 | 215 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 216 | bool more_trbs_coming) |
7f84eef0 SS |
217 | { |
218 | u32 chain; | |
219 | union xhci_trb *next; | |
220 | ||
28ccd296 | 221 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 222 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 223 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 224 | ring->num_trbs_free--; |
7f84eef0 SS |
225 | next = ++(ring->enqueue); |
226 | ||
2251198b | 227 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 228 | while (trb_is_link(next)) { |
6cc30d85 | 229 | |
2251198b MN |
230 | /* |
231 | * If the caller doesn't plan on enqueueing more TDs before | |
232 | * ringing the doorbell, then we don't want to give the link TRB | |
233 | * to the hardware just yet. We'll give the link TRB back in | |
234 | * prepare_ring() just before we enqueue the TD at the top of | |
235 | * the ring. | |
236 | */ | |
237 | if (!chain && !more_trbs_coming) | |
238 | break; | |
3b72fca0 | 239 | |
2251198b MN |
240 | /* If we're not dealing with 0.95 hardware or isoc rings on |
241 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
242 | * (which may mean the chain bit is cleared). | |
243 | */ | |
244 | if (!(ring->type == TYPE_ISOC && | |
245 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
246 | !xhci_link_trb_quirk(xhci)) { | |
247 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
248 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 249 | } |
2251198b MN |
250 | /* Give this link TRB to the hardware */ |
251 | wmb(); | |
252 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
253 | ||
254 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 255 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
256 | ring->cycle_state ^= 1; |
257 | ||
7f84eef0 SS |
258 | ring->enq_seg = ring->enq_seg->next; |
259 | ring->enqueue = ring->enq_seg->trbs; | |
260 | next = ring->enqueue; | |
261 | } | |
b2d6edbb LB |
262 | |
263 | trace_xhci_inc_enq(ring); | |
7f84eef0 SS |
264 | } |
265 | ||
266 | /* | |
085deb16 AX |
267 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
268 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 269 | */ |
b008df60 | 270 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
271 | unsigned int num_trbs) |
272 | { | |
085deb16 | 273 | int num_trbs_in_deq_seg; |
b008df60 | 274 | |
085deb16 AX |
275 | if (ring->num_trbs_free < num_trbs) |
276 | return 0; | |
277 | ||
278 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
279 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
280 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
281 | return 0; | |
282 | } | |
283 | ||
284 | return 1; | |
7f84eef0 SS |
285 | } |
286 | ||
7f84eef0 | 287 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 288 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 289 | { |
c181bc5b EF |
290 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
291 | return; | |
292 | ||
7f84eef0 | 293 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 294 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 295 | /* Flush PCI posted writes */ |
b0ba9720 | 296 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
297 | } |
298 | ||
cb4d5ce5 OH |
299 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
300 | { | |
301 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
302 | } | |
303 | ||
1c111b6c OH |
304 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
305 | { | |
306 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, | |
307 | cmd_list); | |
308 | } | |
309 | ||
310 | /* | |
311 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
312 | * If there are other commands waiting then restart the ring and kick the timer. | |
313 | * This must be called with command ring stopped and xhci->lock held. | |
314 | */ | |
315 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
316 | struct xhci_command *cur_cmd) | |
317 | { | |
318 | struct xhci_command *i_cmd; | |
1c111b6c OH |
319 | |
320 | /* Turn all aborted commands in list to no-ops, then restart */ | |
321 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { | |
322 | ||
0b7c105a | 323 | if (i_cmd->status != COMP_COMMAND_ABORTED) |
1c111b6c OH |
324 | continue; |
325 | ||
604d02a2 | 326 | i_cmd->status = COMP_COMMAND_RING_STOPPED; |
1c111b6c OH |
327 | |
328 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
329 | i_cmd->command_trb); | |
5278204c MN |
330 | |
331 | trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); | |
1c111b6c OH |
332 | |
333 | /* | |
334 | * caller waiting for completion is called when command | |
335 | * completion event is received for these no-op commands | |
336 | */ | |
337 | } | |
338 | ||
339 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
340 | ||
341 | /* ring command ring doorbell to restart the command ring */ | |
342 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
343 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
344 | xhci->current_cmd = cur_cmd; | |
345 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); | |
346 | xhci_ring_cmd_db(xhci); | |
347 | } | |
348 | } | |
349 | ||
350 | /* Must be called with xhci->lock held, releases and aquires lock back */ | |
351 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) | |
b92cc66c EF |
352 | { |
353 | u64 temp_64; | |
354 | int ret; | |
355 | ||
356 | xhci_dbg(xhci, "Abort command ring\n"); | |
357 | ||
1c111b6c | 358 | reinit_completion(&xhci->cmd_ring_stop_completion); |
3425aa03 | 359 | |
1c111b6c | 360 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
477632df SS |
361 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
362 | &xhci->op_regs->cmd_ring); | |
b92cc66c | 363 | |
d9f11ba9 MN |
364 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the |
365 | * completion of the Command Abort operation. If CRR is not negated in 5 | |
366 | * seconds then driver handles it as if host died (-ENODEV). | |
367 | * In the future we should distinguish between -ENODEV and -ETIMEDOUT | |
368 | * and try to recover a -ETIMEDOUT with a host controller reset. | |
b92cc66c | 369 | */ |
dc0b177c | 370 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
371 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
372 | if (ret < 0) { | |
d9f11ba9 | 373 | xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); |
1cc6d861 | 374 | xhci_halt(xhci); |
d9f11ba9 MN |
375 | xhci_hc_died(xhci); |
376 | return ret; | |
1c111b6c OH |
377 | } |
378 | /* | |
379 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
380 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
381 | * but the completion event in never sent. Wait 2 secs (arbitrary | |
382 | * number) to handle those cases after negation of CMD_RING_RUNNING. | |
383 | */ | |
384 | spin_unlock_irqrestore(&xhci->lock, flags); | |
385 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, | |
386 | msecs_to_jiffies(2000)); | |
387 | spin_lock_irqsave(&xhci->lock, flags); | |
388 | if (!ret) { | |
389 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); | |
390 | xhci_cleanup_command_queue(xhci); | |
391 | } else { | |
392 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); | |
b92cc66c | 393 | } |
b92cc66c EF |
394 | return 0; |
395 | } | |
396 | ||
be88fe4f | 397 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 398 | unsigned int slot_id, |
e9df17eb SS |
399 | unsigned int ep_index, |
400 | unsigned int stream_id) | |
ae636747 | 401 | { |
28ccd296 | 402 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
403 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
404 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 405 | |
ae636747 | 406 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 407 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
408 | * We don't want to restart any stream rings if there's a set dequeue |
409 | * pointer command pending because the device can choose to start any | |
410 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 411 | */ |
9983a5fc | 412 | if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || |
50d64676 MW |
413 | (ep_state & EP_HALTED)) |
414 | return; | |
204b7793 | 415 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
416 | /* The CPU has better things to do at this point than wait for a |
417 | * write-posting flush. It'll get there soon enough. | |
418 | */ | |
ae636747 SS |
419 | } |
420 | ||
e9df17eb SS |
421 | /* Ring the doorbell for any rings with pending URBs */ |
422 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
423 | unsigned int slot_id, | |
424 | unsigned int ep_index) | |
425 | { | |
426 | unsigned int stream_id; | |
427 | struct xhci_virt_ep *ep; | |
428 | ||
429 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
430 | ||
431 | /* A ring has pending URBs if its TD list is not empty */ | |
432 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 433 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 434 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
435 | return; |
436 | } | |
437 | ||
438 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
439 | stream_id++) { | |
440 | struct xhci_stream_info *stream_info = ep->stream_info; | |
441 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
442 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
443 | stream_id); | |
e9df17eb SS |
444 | } |
445 | } | |
446 | ||
75b040ec AI |
447 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
448 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
449 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
450 | */ | |
451 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
452 | unsigned int slot_id, unsigned int ep_index, |
453 | unsigned int stream_id) | |
454 | { | |
455 | struct xhci_virt_ep *ep; | |
456 | ||
457 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
458 | /* Common case: no streams */ | |
459 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
460 | return ep->ring; | |
461 | ||
462 | if (stream_id == 0) { | |
463 | xhci_warn(xhci, | |
464 | "WARN: Slot ID %u, ep index %u has streams, " | |
465 | "but URB has no stream ID.\n", | |
466 | slot_id, ep_index); | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | if (stream_id < ep->stream_info->num_streams) | |
471 | return ep->stream_info->stream_rings[stream_id]; | |
472 | ||
473 | xhci_warn(xhci, | |
474 | "WARN: Slot ID %u, ep index %u has " | |
475 | "stream IDs 1 to %u allocated, " | |
476 | "but stream ID %u is requested.\n", | |
477 | slot_id, ep_index, | |
478 | ep->stream_info->num_streams - 1, | |
479 | stream_id); | |
480 | return NULL; | |
481 | } | |
482 | ||
ae636747 SS |
483 | /* |
484 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
485 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
486 | * dequeue pointer, and new consumer cycle state in state. | |
487 | * Update our internal representation of the ring's dequeue pointer. | |
488 | * | |
489 | * We do this in three jumps: | |
490 | * - First we update our new ring state to be the same as when the xHC stopped. | |
491 | * - Then we traverse the ring to find the segment that contains | |
492 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
493 | * any link TRBs with the toggle cycle bit set. | |
494 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
495 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
496 | * |
497 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
498 | * with correct __le32 accesses they should work fine. Only users of this are | |
499 | * in here. | |
ae636747 | 500 | */ |
c92bcfa7 | 501 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 502 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
503 | unsigned int stream_id, struct xhci_td *cur_td, |
504 | struct xhci_dequeue_state *state) | |
ae636747 SS |
505 | { |
506 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 507 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 508 | struct xhci_ring *ep_ring; |
365038d8 MN |
509 | struct xhci_segment *new_seg; |
510 | union xhci_trb *new_deq; | |
c92bcfa7 | 511 | dma_addr_t addr; |
1f81b6d2 | 512 | u64 hw_dequeue; |
365038d8 MN |
513 | bool cycle_found = false; |
514 | bool td_last_trb_found = false; | |
ae636747 | 515 | |
e9df17eb SS |
516 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
517 | ep_index, stream_id); | |
518 | if (!ep_ring) { | |
519 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
520 | "for invalid stream ID %u.\n", | |
521 | stream_id); | |
522 | return; | |
523 | } | |
68e41c5d | 524 | |
ae636747 | 525 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
526 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
527 | "Finding endpoint context"); | |
c4bedb77 HG |
528 | /* 4.6.9 the css flag is written to the stream context for streams */ |
529 | if (ep->ep_state & EP_HAS_STREAMS) { | |
530 | struct xhci_stream_ctx *ctx = | |
531 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 532 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
533 | } else { |
534 | struct xhci_ep_ctx *ep_ctx | |
535 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 536 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 537 | } |
ae636747 | 538 | |
365038d8 MN |
539 | new_seg = ep_ring->deq_seg; |
540 | new_deq = ep_ring->dequeue; | |
541 | state->new_cycle_state = hw_dequeue & 0x1; | |
542 | ||
1f81b6d2 | 543 | /* |
365038d8 MN |
544 | * We want to find the pointer, segment and cycle state of the new trb |
545 | * (the one after current TD's last_trb). We know the cycle state at | |
546 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
547 | * found. | |
1f81b6d2 | 548 | */ |
365038d8 MN |
549 | do { |
550 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
551 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
552 | cycle_found = true; | |
553 | if (td_last_trb_found) | |
554 | break; | |
555 | } | |
556 | if (new_deq == cur_td->last_trb) | |
557 | td_last_trb_found = true; | |
1f81b6d2 | 558 | |
3495e451 MN |
559 | if (cycle_found && trb_is_link(new_deq) && |
560 | link_trb_toggles_cycle(new_deq)) | |
365038d8 MN |
561 | state->new_cycle_state ^= 0x1; |
562 | ||
563 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
564 | ||
565 | /* Search wrapped around, bail out */ | |
566 | if (new_deq == ep->ring->dequeue) { | |
567 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
568 | state->new_deq_seg = NULL; | |
569 | state->new_deq_ptr = NULL; | |
570 | return; | |
571 | } | |
572 | ||
573 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 574 | |
365038d8 MN |
575 | state->new_deq_seg = new_seg; |
576 | state->new_deq_ptr = new_deq; | |
ae636747 | 577 | |
1f81b6d2 | 578 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
579 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
580 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 581 | |
aa50b290 XR |
582 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
583 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
584 | state->new_deq_seg); |
585 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
586 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
587 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 588 | (unsigned long long) addr); |
ae636747 SS |
589 | } |
590 | ||
522989a2 SS |
591 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
592 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
593 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
594 | */ | |
23e3be11 | 595 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 596 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 597 | { |
0d58a1a0 MN |
598 | struct xhci_segment *seg = td->start_seg; |
599 | union xhci_trb *trb = td->first_trb; | |
600 | ||
601 | while (1) { | |
ae1e3f07 MN |
602 | trb_to_noop(trb, TRB_TR_NOOP); |
603 | ||
0d58a1a0 MN |
604 | /* flip cycle if asked to */ |
605 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
606 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
607 | ||
608 | if (trb == td->last_trb) | |
ae636747 | 609 | break; |
0d58a1a0 MN |
610 | |
611 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
612 | } |
613 | } | |
614 | ||
575688e1 | 615 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
616 | struct xhci_virt_ep *ep) |
617 | { | |
9983a5fc | 618 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
f9926596 MN |
619 | /* Can't del_timer_sync in interrupt */ |
620 | del_timer(&ep->stop_cmd_timer); | |
6f5165cf SS |
621 | } |
622 | ||
2a72126d MN |
623 | /* |
624 | * Must be called with xhci->lock held in interrupt context, | |
625 | * releases and re-acquires xhci->lock | |
626 | */ | |
6f5165cf | 627 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 628 | struct xhci_td *cur_td, int status) |
6f5165cf | 629 | { |
2a72126d MN |
630 | struct urb *urb = cur_td->urb; |
631 | struct urb_priv *urb_priv = urb->hcpriv; | |
632 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
633 | ||
634 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
635 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
636 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
637 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
638 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 639 | } |
8e51adcc | 640 | } |
446b3141 | 641 | xhci_urb_free_priv(urb_priv); |
2a72126d | 642 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
446b3141 | 643 | spin_unlock(&xhci->lock); |
5abdc2e6 | 644 | trace_xhci_urb_giveback(urb); |
7bc5d5af | 645 | usb_hcd_giveback_urb(hcd, urb, status); |
446b3141 MN |
646 | spin_lock(&xhci->lock); |
647 | } | |
648 | ||
2d6d5769 WY |
649 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
650 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
651 | { |
652 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
653 | struct xhci_segment *seg = td->bounce_seg; | |
654 | struct urb *urb = td->urb; | |
655 | ||
f45e2a02 | 656 | if (!ring || !seg || !urb) |
f9c589e1 MN |
657 | return; |
658 | ||
659 | if (usb_urb_dir_out(urb)) { | |
660 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
661 | DMA_TO_DEVICE); | |
662 | return; | |
663 | } | |
664 | ||
665 | /* for in tranfers we need to copy the data from bounce to sg */ | |
666 | sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, | |
667 | seg->bounce_len, seg->bounce_offs); | |
668 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
669 | DMA_FROM_DEVICE); | |
670 | seg->bounce_len = 0; | |
671 | seg->bounce_offs = 0; | |
672 | } | |
673 | ||
ae636747 SS |
674 | /* |
675 | * When we get a command completion for a Stop Endpoint Command, we need to | |
676 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
677 | * | |
678 | * 1. If the HW was in the middle of processing the TD that needs to be | |
679 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
680 | * in the TD with a Set Dequeue Pointer Command. | |
681 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
682 | * bit cleared) so that the HW will skip over them. | |
683 | */ | |
b8200c94 | 684 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 685 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 686 | { |
ae636747 SS |
687 | unsigned int ep_index; |
688 | struct xhci_ring *ep_ring; | |
63a0d9ab | 689 | struct xhci_virt_ep *ep; |
326b4810 | 690 | struct xhci_td *cur_td = NULL; |
ae636747 | 691 | struct xhci_td *last_unlinked_td; |
19a7d0d6 FB |
692 | struct xhci_ep_ctx *ep_ctx; |
693 | struct xhci_virt_device *vdev; | |
ae636747 | 694 | |
c92bcfa7 | 695 | struct xhci_dequeue_state deq_state; |
ae636747 | 696 | |
bc752bde | 697 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 698 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
699 | xhci_warn(xhci, "Stop endpoint command " |
700 | "completion for disabled slot %u\n", | |
701 | slot_id); | |
702 | return; | |
703 | } | |
704 | ||
ae636747 | 705 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 706 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
707 | |
708 | vdev = xhci->devs[slot_id]; | |
709 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
710 | trace_xhci_handle_cmd_stop_ep(ep_ctx); | |
711 | ||
63a0d9ab | 712 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
04861f83 FB |
713 | last_unlinked_td = list_last_entry(&ep->cancelled_td_list, |
714 | struct xhci_td, cancelled_td_list); | |
ae636747 | 715 | |
678539cf | 716 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 717 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
e9df17eb | 718 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 719 | return; |
678539cf | 720 | } |
ae636747 SS |
721 | |
722 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
723 | * We have the xHCI lock, so nothing can modify this list until we drop | |
724 | * it. We're also in the event handler, so we can't get re-interrupted | |
725 | * if another Stop Endpoint command completes | |
726 | */ | |
04861f83 | 727 | list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { |
aa50b290 XR |
728 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
729 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
730 | (unsigned long long)xhci_trb_virt_to_dma( |
731 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
732 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
733 | if (!ep_ring) { | |
734 | /* This shouldn't happen unless a driver is mucking | |
735 | * with the stream ID after submission. This will | |
736 | * leave the TD on the hardware ring, and the hardware | |
737 | * will try to execute it, and may access a buffer | |
738 | * that has already been freed. In the best case, the | |
739 | * hardware will execute it, and the event handler will | |
740 | * ignore the completion event for that TD, since it was | |
741 | * removed from the td_list for that endpoint. In | |
742 | * short, don't muck with the stream ID after | |
743 | * submission. | |
744 | */ | |
745 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
746 | "has invalid stream ID %u.\n", | |
747 | cur_td->urb, | |
748 | cur_td->urb->stream_id); | |
749 | goto remove_finished_td; | |
750 | } | |
ae636747 SS |
751 | /* |
752 | * If we stopped on the TD we need to cancel, then we have to | |
753 | * move the xHC endpoint ring dequeue pointer past this TD. | |
754 | */ | |
63a0d9ab | 755 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
756 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
757 | cur_td->urb->stream_id, | |
758 | cur_td, &deq_state); | |
ae636747 | 759 | else |
522989a2 | 760 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 761 | remove_finished_td: |
ae636747 SS |
762 | /* |
763 | * The event handler won't see a completion for this TD anymore, | |
764 | * so remove it from the endpoint ring's TD list. Keep it in | |
765 | * the cancelled TD list for URB completion later. | |
766 | */ | |
585df1d9 | 767 | list_del_init(&cur_td->td_list); |
ae636747 | 768 | } |
04861f83 | 769 | |
6f5165cf | 770 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
771 | |
772 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
773 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 HG |
774 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
775 | ep->stopped_td->urb->stream_id, &deq_state); | |
ac9d8fe7 | 776 | xhci_ring_cmd_db(xhci); |
ae636747 | 777 | } else { |
e9df17eb SS |
778 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
779 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 780 | } |
526867c3 | 781 | |
ae636747 SS |
782 | /* |
783 | * Drop the lock and complete the URBs in the cancelled TD list. | |
784 | * New TDs to be cancelled might be added to the end of the list before | |
785 | * we can complete all the URBs for the TDs we already unlinked. | |
786 | * So stop when we've completed the URB for the last TD we unlinked. | |
787 | */ | |
788 | do { | |
04861f83 | 789 | cur_td = list_first_entry(&ep->cancelled_td_list, |
ae636747 | 790 | struct xhci_td, cancelled_td_list); |
585df1d9 | 791 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
792 | |
793 | /* Clean up the cancelled URB */ | |
ae636747 SS |
794 | /* Doesn't matter what we pass for status, since the core will |
795 | * just overwrite it (because the URB has been unlinked). | |
796 | */ | |
f76a28a6 | 797 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
a60f2f2f | 798 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); |
2a72126d MN |
799 | inc_td_cnt(cur_td->urb); |
800 | if (last_td_in_urb(cur_td)) | |
801 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); | |
ae636747 | 802 | |
6f5165cf SS |
803 | /* Stop processing the cancelled list if the watchdog timer is |
804 | * running. | |
805 | */ | |
806 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
807 | return; | |
ae636747 SS |
808 | } while (cur_td != last_unlinked_td); |
809 | ||
810 | /* Return to the event handler with xhci->lock re-acquired */ | |
811 | } | |
812 | ||
50e8725e SS |
813 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
814 | { | |
815 | struct xhci_td *cur_td; | |
a54cfae3 | 816 | struct xhci_td *tmp; |
50e8725e | 817 | |
a54cfae3 | 818 | list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { |
50e8725e | 819 | list_del_init(&cur_td->td_list); |
a54cfae3 | 820 | |
50e8725e SS |
821 | if (!list_empty(&cur_td->cancelled_td_list)) |
822 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 | 823 | |
a60f2f2f | 824 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
2a72126d MN |
825 | |
826 | inc_td_cnt(cur_td->urb); | |
827 | if (last_td_in_urb(cur_td)) | |
828 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
829 | } |
830 | } | |
831 | ||
832 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
833 | int slot_id, int ep_index) | |
834 | { | |
835 | struct xhci_td *cur_td; | |
a54cfae3 | 836 | struct xhci_td *tmp; |
50e8725e SS |
837 | struct xhci_virt_ep *ep; |
838 | struct xhci_ring *ring; | |
839 | ||
840 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
841 | if ((ep->ep_state & EP_HAS_STREAMS) || |
842 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
843 | int stream_id; | |
844 | ||
845 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
846 | stream_id++) { | |
847 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
848 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
849 | slot_id, ep_index, stream_id + 1); | |
850 | xhci_kill_ring_urbs(xhci, | |
851 | ep->stream_info->stream_rings[stream_id]); | |
852 | } | |
853 | } else { | |
854 | ring = ep->ring; | |
855 | if (!ring) | |
856 | return; | |
857 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
858 | "Killing URBs for slot ID %u, ep index %u", | |
859 | slot_id, ep_index); | |
860 | xhci_kill_ring_urbs(xhci, ring); | |
861 | } | |
2a72126d | 862 | |
a54cfae3 FB |
863 | list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, |
864 | cancelled_td_list) { | |
865 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d | 866 | inc_td_cnt(cur_td->urb); |
a54cfae3 | 867 | |
2a72126d MN |
868 | if (last_td_in_urb(cur_td)) |
869 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
870 | } |
871 | } | |
872 | ||
d9f11ba9 MN |
873 | /* |
874 | * host controller died, register read returns 0xffffffff | |
875 | * Complete pending commands, mark them ABORTED. | |
876 | * URBs need to be given back as usb core might be waiting with device locks | |
877 | * held for the URBs to finish during device disconnect, blocking host remove. | |
878 | * | |
879 | * Call with xhci->lock held. | |
880 | * lock is relased and re-acquired while giving back urb. | |
881 | */ | |
882 | void xhci_hc_died(struct xhci_hcd *xhci) | |
883 | { | |
884 | int i, j; | |
885 | ||
886 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
887 | return; | |
888 | ||
889 | xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); | |
890 | xhci->xhc_state |= XHCI_STATE_DYING; | |
891 | ||
892 | xhci_cleanup_command_queue(xhci); | |
893 | ||
894 | /* return any pending urbs, remove may be waiting for them */ | |
895 | for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
896 | if (!xhci->devs[i]) | |
897 | continue; | |
898 | for (j = 0; j < 31; j++) | |
899 | xhci_kill_endpoint_urbs(xhci, i, j); | |
900 | } | |
901 | ||
902 | /* inform usb core hc died if PCI remove isn't already handling it */ | |
903 | if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) | |
904 | usb_hc_died(xhci_to_hcd(xhci)); | |
905 | } | |
906 | ||
6f5165cf SS |
907 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
908 | * In this case, we assume the host controller is broken or dying or dead. The | |
909 | * host may still be completing some other events, so we have to be careful to | |
910 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
911 | * through xhci->state. | |
912 | * | |
913 | * The timer may also fire if the host takes a very long time to respond to the | |
914 | * command, and the stop endpoint command completion handler cannot delete the | |
915 | * timer before the timer function is called. Another endpoint cancellation may | |
916 | * sneak in before the timer function can grab the lock, and that may queue | |
917 | * another stop endpoint command and add the timer back. So we cannot use a | |
918 | * simple flag to say whether there is a pending stop endpoint command for a | |
919 | * particular endpoint. | |
920 | * | |
f9926596 MN |
921 | * Instead we use a combination of that flag and checking if a new timer is |
922 | * pending. | |
6f5165cf SS |
923 | */ |
924 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
925 | { | |
926 | struct xhci_hcd *xhci; | |
927 | struct xhci_virt_ep *ep; | |
f43d6231 | 928 | unsigned long flags; |
6f5165cf SS |
929 | |
930 | ep = (struct xhci_virt_ep *) arg; | |
931 | xhci = ep->xhci; | |
932 | ||
f43d6231 | 933 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf | 934 | |
f9926596 MN |
935 | /* bail out if cmd completed but raced with stop ep watchdog timer.*/ |
936 | if (!(ep->ep_state & EP_STOP_CMD_PENDING) || | |
937 | timer_pending(&ep->stop_cmd_timer)) { | |
f43d6231 | 938 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9926596 | 939 | xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); |
6f5165cf SS |
940 | return; |
941 | } | |
942 | ||
943 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
f9926596 MN |
944 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
945 | ||
d9f11ba9 | 946 | xhci_halt(xhci); |
6f5165cf | 947 | |
d9f11ba9 MN |
948 | /* |
949 | * handle a stop endpoint cmd timeout as if host died (-ENODEV). | |
950 | * In the future we could distinguish between -ENODEV and -ETIMEDOUT | |
951 | * and try to recover a -ETIMEDOUT with a host controller reset | |
952 | */ | |
953 | xhci_hc_died(xhci); | |
6f5165cf | 954 | |
f43d6231 | 955 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
956 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
957 | "xHCI host controller is dead."); | |
6f5165cf SS |
958 | } |
959 | ||
b008df60 AX |
960 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, |
961 | struct xhci_virt_device *dev, | |
962 | struct xhci_ring *ep_ring, | |
963 | unsigned int ep_index) | |
964 | { | |
965 | union xhci_trb *dequeue_temp; | |
966 | int num_trbs_free_temp; | |
967 | bool revert = false; | |
968 | ||
969 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
970 | dequeue_temp = ep_ring->dequeue; | |
971 | ||
0d9f78a9 SS |
972 | /* If we get two back-to-back stalls, and the first stalled transfer |
973 | * ends just before a link TRB, the dequeue pointer will be left on | |
974 | * the link TRB by the code in the while loop. So we have to update | |
975 | * the dequeue pointer one segment further, or we'll jump off | |
976 | * the segment into la-la-land. | |
977 | */ | |
2d98ef40 | 978 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
979 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
980 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
981 | } | |
982 | ||
b008df60 AX |
983 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
984 | /* We have more usable TRBs */ | |
985 | ep_ring->num_trbs_free++; | |
986 | ep_ring->dequeue++; | |
2d98ef40 | 987 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
988 | if (ep_ring->dequeue == |
989 | dev->eps[ep_index].queued_deq_ptr) | |
990 | break; | |
991 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
992 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
993 | } | |
994 | if (ep_ring->dequeue == dequeue_temp) { | |
995 | revert = true; | |
996 | break; | |
997 | } | |
998 | } | |
999 | ||
1000 | if (revert) { | |
1001 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1002 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1003 | } | |
1004 | } | |
1005 | ||
ae636747 SS |
1006 | /* |
1007 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1008 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1009 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1010 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1011 | * cancellations pending. | |
1012 | */ | |
b8200c94 | 1013 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1014 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1015 | { |
ae636747 | 1016 | unsigned int ep_index; |
e9df17eb | 1017 | unsigned int stream_id; |
ae636747 SS |
1018 | struct xhci_ring *ep_ring; |
1019 | struct xhci_virt_device *dev; | |
9aad95e2 | 1020 | struct xhci_virt_ep *ep; |
d115b048 JY |
1021 | struct xhci_ep_ctx *ep_ctx; |
1022 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 1023 | |
28ccd296 ME |
1024 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1025 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 1026 | dev = xhci->devs[slot_id]; |
9aad95e2 | 1027 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
1028 | |
1029 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
1030 | if (!ep_ring) { | |
e587b8b2 | 1031 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1032 | stream_id); |
1033 | /* XXX: Harmless??? */ | |
0d4976ec | 1034 | goto cleanup; |
e9df17eb SS |
1035 | } |
1036 | ||
d115b048 JY |
1037 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
1038 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
19a7d0d6 FB |
1039 | trace_xhci_handle_cmd_set_deq(slot_ctx); |
1040 | trace_xhci_handle_cmd_set_deq_ep(ep_ctx); | |
ae636747 | 1041 | |
c69a0597 | 1042 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1043 | unsigned int ep_state; |
1044 | unsigned int slot_state; | |
1045 | ||
c69a0597 | 1046 | switch (cmd_comp_code) { |
0b7c105a | 1047 | case COMP_TRB_ERROR: |
e587b8b2 | 1048 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 | 1049 | break; |
0b7c105a | 1050 | case COMP_CONTEXT_STATE_ERROR: |
e587b8b2 | 1051 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1052 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1053 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1054 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1055 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1056 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1057 | slot_state, ep_state); |
1058 | break; | |
0b7c105a | 1059 | case COMP_SLOT_NOT_ENABLED_ERROR: |
e587b8b2 ON |
1060 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1061 | slot_id); | |
ae636747 SS |
1062 | break; |
1063 | default: | |
e587b8b2 ON |
1064 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1065 | cmd_comp_code); | |
ae636747 SS |
1066 | break; |
1067 | } | |
1068 | /* OK what do we do now? The endpoint state is hosed, and we | |
1069 | * should never get to this point if the synchronization between | |
1070 | * queueing, and endpoint state are correct. This might happen | |
1071 | * if the device gets disconnected after we've finished | |
1072 | * cancelling URBs, which might not be an error... | |
1073 | */ | |
1074 | } else { | |
9aad95e2 HG |
1075 | u64 deq; |
1076 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1077 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1078 | struct xhci_stream_ctx *ctx = | |
1079 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1080 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1081 | } else { | |
1082 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1083 | } | |
aa50b290 | 1084 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1085 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1086 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1087 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1088 | /* Update the ring's dequeue segment and dequeue pointer |
1089 | * to reflect the new position. | |
1090 | */ | |
b008df60 AX |
1091 | update_ring_for_set_deq_completion(xhci, dev, |
1092 | ep_ring, ep_index); | |
bf161e85 | 1093 | } else { |
e587b8b2 | 1094 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1095 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1096 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1097 | } |
ae636747 SS |
1098 | } |
1099 | ||
0d4976ec | 1100 | cleanup: |
63a0d9ab | 1101 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1102 | dev->eps[ep_index].queued_deq_seg = NULL; |
1103 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1104 | /* Restart any rings with pending URBs */ |
1105 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1106 | } |
1107 | ||
b8200c94 | 1108 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1109 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1110 | { |
19a7d0d6 FB |
1111 | struct xhci_virt_device *vdev; |
1112 | struct xhci_ep_ctx *ep_ctx; | |
a1587d97 SS |
1113 | unsigned int ep_index; |
1114 | ||
28ccd296 | 1115 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
1116 | vdev = xhci->devs[slot_id]; |
1117 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
1118 | trace_xhci_handle_cmd_reset_ep(ep_ctx); | |
1119 | ||
a1587d97 SS |
1120 | /* This command will only fail if the endpoint wasn't halted, |
1121 | * but we don't care. | |
1122 | */ | |
a0254324 | 1123 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1124 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1125 | |
ac9d8fe7 SS |
1126 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1127 | * command complete before the endpoint can be used. Queue that here | |
1128 | * because the HW can't handle two commands being queued in a row. | |
1129 | */ | |
1130 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 | 1131 | struct xhci_command *command; |
74e0b564 | 1132 | |
ddba5cd0 | 1133 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
74e0b564 | 1134 | if (!command) |
a0ee619f | 1135 | return; |
74e0b564 | 1136 | |
4bdfe4c3 XR |
1137 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1138 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1139 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1140 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1141 | false); | |
ac9d8fe7 SS |
1142 | xhci_ring_cmd_db(xhci); |
1143 | } else { | |
c3492dbf | 1144 | /* Clear our internal halted state */ |
63a0d9ab | 1145 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1146 | } |
a1587d97 | 1147 | } |
ae636747 | 1148 | |
b244b431 | 1149 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1150 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1151 | { |
1152 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1153 | command->slot_id = slot_id; |
b244b431 | 1154 | else |
c2d3d49b | 1155 | command->slot_id = 0; |
b244b431 XR |
1156 | } |
1157 | ||
6c02dd14 XR |
1158 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1159 | { | |
1160 | struct xhci_virt_device *virt_dev; | |
19a7d0d6 | 1161 | struct xhci_slot_ctx *slot_ctx; |
6c02dd14 XR |
1162 | |
1163 | virt_dev = xhci->devs[slot_id]; | |
1164 | if (!virt_dev) | |
1165 | return; | |
19a7d0d6 FB |
1166 | |
1167 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
1168 | trace_xhci_handle_cmd_disable_slot(slot_ctx); | |
1169 | ||
6c02dd14 XR |
1170 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
1171 | /* Delete default control endpoint resources */ | |
1172 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1173 | xhci_free_virt_device(xhci, slot_id); | |
1174 | } | |
1175 | ||
6ed46d33 XR |
1176 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1177 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1178 | { | |
1179 | struct xhci_virt_device *virt_dev; | |
1180 | struct xhci_input_control_ctx *ctrl_ctx; | |
19a7d0d6 | 1181 | struct xhci_ep_ctx *ep_ctx; |
6ed46d33 XR |
1182 | unsigned int ep_index; |
1183 | unsigned int ep_state; | |
1184 | u32 add_flags, drop_flags; | |
1185 | ||
6ed46d33 XR |
1186 | /* |
1187 | * Configure endpoint commands can come from the USB core | |
1188 | * configuration or alt setting changes, or because the HW | |
1189 | * needed an extra configure endpoint command after a reset | |
1190 | * endpoint command or streams were being configured. | |
1191 | * If the command was for a halted endpoint, the xHCI driver | |
1192 | * is not waiting on the configure endpoint command. | |
1193 | */ | |
9ea1833e | 1194 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1195 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1196 | if (!ctrl_ctx) { |
1197 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1198 | return; | |
1199 | } | |
1200 | ||
1201 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1202 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1203 | /* Input ctx add_flags are the endpoint index plus one */ | |
1204 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1205 | ||
19a7d0d6 FB |
1206 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); |
1207 | trace_xhci_handle_cmd_config_ep(ep_ctx); | |
1208 | ||
6ed46d33 XR |
1209 | /* A usb_set_interface() call directly after clearing a halted |
1210 | * condition may race on this quirky hardware. Not worth | |
1211 | * worrying about, since this is prototype hardware. Not sure | |
1212 | * if this will work for streams, but streams support was | |
1213 | * untested on this prototype. | |
1214 | */ | |
1215 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1216 | ep_index != (unsigned int) -1 && | |
1217 | add_flags - SLOT_FLAG == drop_flags) { | |
1218 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1219 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1220 | return; |
6ed46d33 XR |
1221 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1222 | "Completed config ep cmd - " | |
1223 | "last ep index = %d, state = %d", | |
1224 | ep_index, ep_state); | |
1225 | /* Clear internal halted state and restart ring(s) */ | |
1226 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1227 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1228 | return; | |
1229 | } | |
6ed46d33 XR |
1230 | return; |
1231 | } | |
1232 | ||
19a7d0d6 FB |
1233 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) |
1234 | { | |
1235 | struct xhci_virt_device *vdev; | |
1236 | struct xhci_slot_ctx *slot_ctx; | |
1237 | ||
1238 | vdev = xhci->devs[slot_id]; | |
1239 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1240 | trace_xhci_handle_cmd_addr_dev(slot_ctx); | |
1241 | } | |
1242 | ||
f681321b XR |
1243 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1244 | struct xhci_event_cmd *event) | |
1245 | { | |
19a7d0d6 FB |
1246 | struct xhci_virt_device *vdev; |
1247 | struct xhci_slot_ctx *slot_ctx; | |
1248 | ||
1249 | vdev = xhci->devs[slot_id]; | |
1250 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1251 | trace_xhci_handle_cmd_reset_dev(slot_ctx); | |
1252 | ||
f681321b | 1253 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1254 | if (!xhci->devs[slot_id]) |
f681321b XR |
1255 | xhci_warn(xhci, "Reset device command completion " |
1256 | "for disabled slot %u\n", slot_id); | |
1257 | } | |
1258 | ||
2c070821 XR |
1259 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1260 | struct xhci_event_cmd *event) | |
1261 | { | |
1262 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1263 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1264 | return; |
1265 | } | |
1266 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1267 | "NEC firmware version %2x.%02x", | |
1268 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1269 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1270 | } | |
1271 | ||
9ea1833e | 1272 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1273 | { |
1274 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1275 | |
1276 | if (cmd->completion) { | |
1277 | cmd->status = status; | |
1278 | complete(cmd->completion); | |
1279 | } else { | |
c9aa1a2d | 1280 | kfree(cmd); |
9ea1833e | 1281 | } |
c9aa1a2d MN |
1282 | } |
1283 | ||
1284 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1285 | { | |
1286 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1287 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
0b7c105a | 1288 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); |
c9aa1a2d MN |
1289 | } |
1290 | ||
cb4d5ce5 | 1291 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1292 | { |
1293 | struct xhci_hcd *xhci; | |
c311e391 MN |
1294 | unsigned long flags; |
1295 | u64 hw_ring_state; | |
cb4d5ce5 OH |
1296 | |
1297 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1298 | |
c311e391 | 1299 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1300 | |
a5a1b951 MN |
1301 | /* |
1302 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1303 | * raced with command completion. Command is handled so just return. | |
1304 | */ | |
cb4d5ce5 | 1305 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1306 | spin_unlock_irqrestore(&xhci->lock, flags); |
1307 | return; | |
c311e391 | 1308 | } |
2b985467 | 1309 | /* mark this command to be cancelled */ |
0b7c105a | 1310 | xhci->current_cmd->status = COMP_COMMAND_ABORTED; |
2b985467 | 1311 | |
c311e391 MN |
1312 | /* Make sure command ring is running before aborting it */ |
1313 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
d9f11ba9 MN |
1314 | if (hw_ring_state == ~(u64)0) { |
1315 | xhci_hc_died(xhci); | |
1316 | goto time_out_completed; | |
1317 | } | |
1318 | ||
c311e391 MN |
1319 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && |
1320 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1c111b6c OH |
1321 | /* Prevent new doorbell, and start command abort */ |
1322 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
c311e391 | 1323 | xhci_dbg(xhci, "Command timeout\n"); |
d9f11ba9 | 1324 | xhci_abort_cmd_ring(xhci, flags); |
4dea7077 | 1325 | goto time_out_completed; |
c311e391 | 1326 | } |
3425aa03 | 1327 | |
1c111b6c OH |
1328 | /* host removed. Bail out */ |
1329 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1330 | xhci_dbg(xhci, "host removed, ring start fail?\n"); | |
3425aa03 | 1331 | xhci_cleanup_command_queue(xhci); |
4dea7077 LB |
1332 | |
1333 | goto time_out_completed; | |
3425aa03 MN |
1334 | } |
1335 | ||
c311e391 MN |
1336 | /* command timeout on stopped ring, ring can't be aborted */ |
1337 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1338 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1339 | |
1340 | time_out_completed: | |
c311e391 MN |
1341 | spin_unlock_irqrestore(&xhci->lock, flags); |
1342 | return; | |
1343 | } | |
1344 | ||
7f84eef0 SS |
1345 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1346 | struct xhci_event_cmd *event) | |
1347 | { | |
28ccd296 | 1348 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1349 | u64 cmd_dma; |
1350 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1351 | u32 cmd_comp_code; |
9124b121 | 1352 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1353 | struct xhci_command *cmd; |
b54fc46d | 1354 | u32 cmd_type; |
7f84eef0 | 1355 | |
28ccd296 | 1356 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1357 | cmd_trb = xhci->cmd_ring->dequeue; |
a37c3f76 FB |
1358 | |
1359 | trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); | |
1360 | ||
23e3be11 | 1361 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1362 | cmd_trb); |
f4c8f03c LB |
1363 | /* |
1364 | * Check whether the completion event is for our internal kept | |
1365 | * command. | |
1366 | */ | |
1367 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1368 | xhci_warn(xhci, | |
1369 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1370 | return; |
1371 | } | |
b63f4053 | 1372 | |
04861f83 | 1373 | cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); |
c9aa1a2d | 1374 | |
cb4d5ce5 | 1375 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1376 | |
e7a79a1d | 1377 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1378 | |
1379 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
604d02a2 | 1380 | if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { |
1c111b6c | 1381 | complete_all(&xhci->cmd_ring_stop_completion); |
c311e391 MN |
1382 | return; |
1383 | } | |
33be1265 MN |
1384 | |
1385 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1386 | xhci_err(xhci, | |
1387 | "Command completion event does not match command\n"); | |
1388 | return; | |
1389 | } | |
1390 | ||
c311e391 MN |
1391 | /* |
1392 | * Host aborted the command ring, check if the current command was | |
1393 | * supposed to be aborted, otherwise continue normally. | |
1394 | * The command ring is stopped now, but the xHC will issue a Command | |
1395 | * Ring Stopped event which will cause us to restart it. | |
1396 | */ | |
0b7c105a | 1397 | if (cmd_comp_code == COMP_COMMAND_ABORTED) { |
c311e391 | 1398 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
0b7c105a | 1399 | if (cmd->status == COMP_COMMAND_ABORTED) { |
2a7cfdf3 BW |
1400 | if (xhci->current_cmd == cmd) |
1401 | xhci->current_cmd = NULL; | |
c311e391 | 1402 | goto event_handled; |
2a7cfdf3 | 1403 | } |
b63f4053 EF |
1404 | } |
1405 | ||
b54fc46d XR |
1406 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1407 | switch (cmd_type) { | |
1408 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1409 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1410 | break; |
b54fc46d | 1411 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1412 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1413 | break; |
b54fc46d | 1414 | case TRB_CONFIG_EP: |
9ea1833e MN |
1415 | if (!cmd->completion) |
1416 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1417 | cmd_comp_code); | |
f94e0186 | 1418 | break; |
b54fc46d | 1419 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1420 | break; |
b54fc46d | 1421 | case TRB_ADDR_DEV: |
19a7d0d6 | 1422 | xhci_handle_cmd_addr_dev(xhci, slot_id); |
3ffbba95 | 1423 | break; |
b54fc46d | 1424 | case TRB_STOP_RING: |
b8200c94 XR |
1425 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1426 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1427 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1428 | break; |
b54fc46d | 1429 | case TRB_SET_DEQ: |
b8200c94 XR |
1430 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1431 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1432 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1433 | break; |
b54fc46d | 1434 | case TRB_CMD_NOOP: |
c311e391 | 1435 | /* Is this an aborted command turned to NO-OP? */ |
604d02a2 MN |
1436 | if (cmd->status == COMP_COMMAND_RING_STOPPED) |
1437 | cmd_comp_code = COMP_COMMAND_RING_STOPPED; | |
7f84eef0 | 1438 | break; |
b54fc46d | 1439 | case TRB_RESET_EP: |
b8200c94 XR |
1440 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1441 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1442 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1443 | break; |
b54fc46d | 1444 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1445 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1446 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1447 | */ | |
1448 | slot_id = TRB_TO_SLOT_ID( | |
1449 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1450 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1451 | break; |
b54fc46d | 1452 | case TRB_NEC_GET_FW: |
2c070821 | 1453 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1454 | break; |
7f84eef0 SS |
1455 | default: |
1456 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1457 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1458 | break; |
1459 | } | |
c9aa1a2d | 1460 | |
c311e391 | 1461 | /* restart timer if this wasn't the last command */ |
daa47f21 | 1462 | if (!list_is_singular(&xhci->cmd_list)) { |
04861f83 FB |
1463 | xhci->current_cmd = list_first_entry(&cmd->cmd_list, |
1464 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1465 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1466 | } else if (xhci->current_cmd == cmd) { |
1467 | xhci->current_cmd = NULL; | |
c311e391 MN |
1468 | } |
1469 | ||
1470 | event_handled: | |
9ea1833e | 1471 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1472 | |
3b72fca0 | 1473 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1474 | } |
1475 | ||
0238634d SS |
1476 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1477 | union xhci_trb *event) | |
1478 | { | |
1479 | u32 trb_type; | |
1480 | ||
28ccd296 | 1481 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1482 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1483 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1484 | handle_cmd_completion(xhci, &event->event_cmd); | |
1485 | } | |
1486 | ||
f6ff0ac8 SS |
1487 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1488 | * port registers -- USB 3.0 and USB 2.0). | |
1489 | * | |
1490 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1491 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1492 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1493 | */ |
1494 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1495 | struct xhci_hcd *xhci, u32 port_id) | |
1496 | { | |
1497 | unsigned int i; | |
1498 | unsigned int num_similar_speed_ports = 0; | |
1499 | ||
1500 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1501 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1502 | * speed ports, up to 1 port before this port. | |
1503 | */ | |
1504 | for (i = 0; i < (port_id - 1); i++) { | |
1505 | u8 port_speed = xhci->port_array[i]; | |
1506 | ||
1507 | /* | |
1508 | * Skip ports that don't have known speeds, or have duplicate | |
1509 | * Extended Capabilities port speed entries. | |
1510 | */ | |
22e04870 | 1511 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1512 | continue; |
1513 | ||
1514 | /* | |
1515 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1516 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1517 | * matches the device speed, it's a similar speed port. | |
1518 | */ | |
b50107bb | 1519 | if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) |
f6ff0ac8 SS |
1520 | num_similar_speed_ports++; |
1521 | } | |
1522 | return num_similar_speed_ports; | |
1523 | } | |
1524 | ||
623bef9e SS |
1525 | static void handle_device_notification(struct xhci_hcd *xhci, |
1526 | union xhci_trb *event) | |
1527 | { | |
1528 | u32 slot_id; | |
4ee823b8 | 1529 | struct usb_device *udev; |
623bef9e | 1530 | |
7e76ad43 | 1531 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1532 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1533 | xhci_warn(xhci, "Device Notification event for " |
1534 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1535 | return; |
1536 | } | |
1537 | ||
1538 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1539 | slot_id); | |
1540 | udev = xhci->devs[slot_id]->udev; | |
1541 | if (udev && udev->parent) | |
1542 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1543 | } |
1544 | ||
0f2a7930 SS |
1545 | static void handle_port_status(struct xhci_hcd *xhci, |
1546 | union xhci_trb *event) | |
1547 | { | |
f6ff0ac8 | 1548 | struct usb_hcd *hcd; |
0f2a7930 | 1549 | u32 port_id; |
56192531 | 1550 | u32 temp, temp1; |
518e848e | 1551 | int max_ports; |
56192531 | 1552 | int slot_id; |
5308a91b | 1553 | unsigned int faked_port_index; |
f6ff0ac8 | 1554 | u8 major_revision; |
20b67cf5 | 1555 | struct xhci_bus_state *bus_state; |
28ccd296 | 1556 | __le32 __iomem **port_array; |
386139d7 | 1557 | bool bogus_port_status = false; |
0f2a7930 SS |
1558 | |
1559 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1560 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1561 | xhci_warn(xhci, | |
1562 | "WARN: xHC returned failed port status event\n"); | |
1563 | ||
28ccd296 | 1564 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1565 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1566 | ||
518e848e SS |
1567 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1568 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1569 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1570 | inc_deq(xhci, xhci->event_ring); |
1571 | return; | |
56192531 AX |
1572 | } |
1573 | ||
f6ff0ac8 SS |
1574 | /* Figure out which usb_hcd this port is attached to: |
1575 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1576 | */ | |
1577 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1578 | |
1579 | /* Find the right roothub. */ | |
1580 | hcd = xhci_to_hcd(xhci); | |
b50107bb | 1581 | if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) |
09ce0c0c PC |
1582 | hcd = xhci->shared_hcd; |
1583 | ||
f6ff0ac8 SS |
1584 | if (major_revision == 0) { |
1585 | xhci_warn(xhci, "Event for port %u not in " | |
1586 | "Extended Capabilities, ignoring.\n", | |
1587 | port_id); | |
386139d7 | 1588 | bogus_port_status = true; |
f6ff0ac8 | 1589 | goto cleanup; |
5308a91b | 1590 | } |
22e04870 | 1591 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1592 | xhci_warn(xhci, "Event for port %u duplicated in" |
1593 | "Extended Capabilities, ignoring.\n", | |
1594 | port_id); | |
386139d7 | 1595 | bogus_port_status = true; |
f6ff0ac8 SS |
1596 | goto cleanup; |
1597 | } | |
1598 | ||
1599 | /* | |
1600 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1601 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1602 | * resume event, but we first need to translate the hardware port ID | |
1603 | * into the index into the ports on the correct split roothub, and the | |
1604 | * correct bus_state structure. | |
1605 | */ | |
f6ff0ac8 | 1606 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
b50107bb | 1607 | if (hcd->speed >= HCD_USB3) |
f6ff0ac8 SS |
1608 | port_array = xhci->usb3_ports; |
1609 | else | |
1610 | port_array = xhci->usb2_ports; | |
1611 | /* Find the faked port hub number */ | |
1612 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1613 | port_id); | |
5308a91b | 1614 | |
b0ba9720 | 1615 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1616 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1617 | xhci_dbg(xhci, "resume root hub\n"); |
1618 | usb_hcd_resume_root_hub(hcd); | |
1619 | } | |
1620 | ||
b50107bb | 1621 | if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
fac4271d ZJC |
1622 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); |
1623 | ||
56192531 AX |
1624 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
1625 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1626 | ||
b0ba9720 | 1627 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1628 | if (!(temp1 & CMD_RUN)) { |
1629 | xhci_warn(xhci, "xHC is not running.\n"); | |
1630 | goto cleanup; | |
1631 | } | |
1632 | ||
2338b9e4 | 1633 | if (DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1634 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1635 | /* Set a flag to say the port signaled remote wakeup, |
1636 | * so we can tell the difference between the end of | |
1637 | * device and host initiated resume. | |
1638 | */ | |
1639 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1640 | xhci_test_and_clear_bit(xhci, port_array, |
1641 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1642 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1643 | XDEV_U0); | |
d93814cf SS |
1644 | /* Need to wait until the next link state change |
1645 | * indicates the device is actually in U0. | |
1646 | */ | |
1647 | bogus_port_status = true; | |
1648 | goto cleanup; | |
f69115fd MN |
1649 | } else if (!test_bit(faked_port_index, |
1650 | &bus_state->resuming_ports)) { | |
56192531 | 1651 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
f6ff0ac8 | 1652 | bus_state->resume_done[faked_port_index] = jiffies + |
b9e45188 | 1653 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
f370b996 | 1654 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1655 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1656 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1657 | /* Do the rest in GetPortStatus */ |
1658 | } | |
1659 | } | |
d93814cf SS |
1660 | |
1661 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
2338b9e4 | 1662 | DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1663 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
4ee823b8 SS |
1664 | /* We've just brought the device into U0 through either the |
1665 | * Resume state after a device remote wakeup, or through the | |
1666 | * U3Exit state after a host-initiated resume. If it's a device | |
1667 | * initiated remote wake, don't pass up the link state change, | |
1668 | * so the roothub behavior is consistent with external | |
1669 | * USB 3.0 hub behavior. | |
1670 | */ | |
d93814cf SS |
1671 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1672 | faked_port_index + 1); | |
1673 | if (slot_id && xhci->devs[slot_id]) | |
1674 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1675 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1676 | bus_state->port_remote_wakeup &= |
1677 | ~(1 << faked_port_index); | |
1678 | xhci_test_and_clear_bit(xhci, port_array, | |
1679 | faked_port_index, PORT_PLC); | |
1680 | usb_wakeup_notification(hcd->self.root_hub, | |
1681 | faked_port_index + 1); | |
1682 | bogus_port_status = true; | |
1683 | goto cleanup; | |
1684 | } | |
d93814cf | 1685 | } |
56192531 | 1686 | |
8b3d4570 SS |
1687 | /* |
1688 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1689 | * RExit to a disconnect state). If so, let the the driver know it's | |
1690 | * out of the RExit state. | |
1691 | */ | |
2338b9e4 | 1692 | if (!DEV_SUPERSPEED_ANY(temp) && |
8b3d4570 SS |
1693 | test_and_clear_bit(faked_port_index, |
1694 | &bus_state->rexit_ports)) { | |
1695 | complete(&bus_state->rexit_done[faked_port_index]); | |
1696 | bogus_port_status = true; | |
1697 | goto cleanup; | |
1698 | } | |
1699 | ||
b50107bb | 1700 | if (hcd->speed < HCD_USB3) |
6fd45621 AX |
1701 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
1702 | PORT_PLC); | |
1703 | ||
56192531 | 1704 | cleanup: |
0f2a7930 | 1705 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1706 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1707 | |
386139d7 SS |
1708 | /* Don't make the USB core poll the roothub if we got a bad port status |
1709 | * change event. Besides, at that point we can't tell which roothub | |
1710 | * (USB 2.0 or USB 3.0) to kick. | |
1711 | */ | |
1712 | if (bogus_port_status) | |
1713 | return; | |
1714 | ||
c52804a4 SS |
1715 | /* |
1716 | * xHCI port-status-change events occur when the "or" of all the | |
1717 | * status-change bits in the portsc register changes from 0 to 1. | |
1718 | * New status changes won't cause an event if any other change | |
1719 | * bits are still set. When an event occurs, switch over to | |
1720 | * polling to avoid losing status changes. | |
1721 | */ | |
1722 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1723 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1724 | spin_unlock(&xhci->lock); |
1725 | /* Pass this up to the core */ | |
f6ff0ac8 | 1726 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1727 | spin_lock(&xhci->lock); |
1728 | } | |
1729 | ||
d0e96f5a SS |
1730 | /* |
1731 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1732 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1733 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1734 | * returns 0. | |
1735 | */ | |
cffb9be8 HG |
1736 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1737 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1738 | union xhci_trb *start_trb, |
1739 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1740 | dma_addr_t suspect_dma, |
1741 | bool debug) | |
d0e96f5a SS |
1742 | { |
1743 | dma_addr_t start_dma; | |
1744 | dma_addr_t end_seg_dma; | |
1745 | dma_addr_t end_trb_dma; | |
1746 | struct xhci_segment *cur_seg; | |
1747 | ||
23e3be11 | 1748 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1749 | cur_seg = start_seg; |
1750 | ||
1751 | do { | |
2fa88daa | 1752 | if (start_dma == 0) |
326b4810 | 1753 | return NULL; |
ae636747 | 1754 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1755 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1756 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1757 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1758 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1759 | |
cffb9be8 HG |
1760 | if (debug) |
1761 | xhci_warn(xhci, | |
1762 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1763 | (unsigned long long)suspect_dma, | |
1764 | (unsigned long long)start_dma, | |
1765 | (unsigned long long)end_trb_dma, | |
1766 | (unsigned long long)cur_seg->dma, | |
1767 | (unsigned long long)end_seg_dma); | |
1768 | ||
d0e96f5a SS |
1769 | if (end_trb_dma > 0) { |
1770 | /* The end TRB is in this segment, so suspect should be here */ | |
1771 | if (start_dma <= end_trb_dma) { | |
1772 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1773 | return cur_seg; | |
1774 | } else { | |
1775 | /* Case for one segment with | |
1776 | * a TD wrapped around to the top | |
1777 | */ | |
1778 | if ((suspect_dma >= start_dma && | |
1779 | suspect_dma <= end_seg_dma) || | |
1780 | (suspect_dma >= cur_seg->dma && | |
1781 | suspect_dma <= end_trb_dma)) | |
1782 | return cur_seg; | |
1783 | } | |
326b4810 | 1784 | return NULL; |
d0e96f5a SS |
1785 | } else { |
1786 | /* Might still be somewhere in this segment */ | |
1787 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1788 | return cur_seg; | |
1789 | } | |
1790 | cur_seg = cur_seg->next; | |
23e3be11 | 1791 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1792 | } while (cur_seg != start_seg); |
d0e96f5a | 1793 | |
326b4810 | 1794 | return NULL; |
d0e96f5a SS |
1795 | } |
1796 | ||
bcef3fd5 SS |
1797 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1798 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1799 | unsigned int stream_id, |
f97c08ae | 1800 | struct xhci_td *td, union xhci_trb *ep_trb) |
bcef3fd5 SS |
1801 | { |
1802 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1803 | struct xhci_command *command; |
1804 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1805 | if (!command) | |
1806 | return; | |
1807 | ||
d0167ad2 | 1808 | ep->ep_state |= EP_HALTED; |
e9df17eb | 1809 | ep->stopped_stream = stream_id; |
1624ae1c | 1810 | |
ddba5cd0 | 1811 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
d97b4f8d | 1812 | xhci_cleanup_stalled_ring(xhci, ep_index, td); |
1624ae1c | 1813 | |
5e5cf6fc | 1814 | ep->stopped_stream = 0; |
1624ae1c | 1815 | |
bcef3fd5 SS |
1816 | xhci_ring_cmd_db(xhci); |
1817 | } | |
1818 | ||
1819 | /* Check if an error has halted the endpoint ring. The class driver will | |
1820 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1821 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1822 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1823 | * Ring Dequeue Pointer command manually. | |
1824 | */ | |
1825 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1826 | struct xhci_ep_ctx *ep_ctx, | |
1827 | unsigned int trb_comp_code) | |
1828 | { | |
1829 | /* TRB completion codes that may require a manual halt cleanup */ | |
0b7c105a FB |
1830 | if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || |
1831 | trb_comp_code == COMP_BABBLE_DETECTED_ERROR || | |
1832 | trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) | |
d4fc8bf5 | 1833 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
1834 | * is not halted. The 0.96 spec says it is. Some HW |
1835 | * claims to be 0.95 compliant, but it halts the control | |
1836 | * endpoint anyway. Check if a babble halted the | |
1837 | * endpoint. | |
1838 | */ | |
5071e6b2 | 1839 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
1840 | return 1; |
1841 | ||
1842 | return 0; | |
1843 | } | |
1844 | ||
b45b5069 SS |
1845 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1846 | { | |
1847 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1848 | /* Vendor defined "informational" completion code, | |
1849 | * treat as not-an-error. | |
1850 | */ | |
1851 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1852 | trb_comp_code); | |
1853 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1854 | return 1; | |
1855 | } | |
1856 | return 0; | |
1857 | } | |
1858 | ||
55fa4396 FB |
1859 | static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, |
1860 | struct xhci_ring *ep_ring, int *status) | |
1861 | { | |
1862 | struct urb_priv *urb_priv; | |
1863 | struct urb *urb = NULL; | |
1864 | ||
1865 | /* Clean up the endpoint's TD list */ | |
1866 | urb = td->urb; | |
1867 | urb_priv = urb->hcpriv; | |
1868 | ||
1869 | /* if a bounce buffer was used to align this td then unmap it */ | |
a60f2f2f | 1870 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); |
55fa4396 FB |
1871 | |
1872 | /* Do one last check of the actual transfer length. | |
1873 | * If the host controller said we transferred more data than the buffer | |
1874 | * length, urb->actual_length will be a very big number (since it's | |
1875 | * unsigned). Play it safe and say we didn't transfer anything. | |
1876 | */ | |
1877 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1878 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", | |
1879 | urb->transfer_buffer_length, urb->actual_length); | |
1880 | urb->actual_length = 0; | |
1881 | *status = 0; | |
1882 | } | |
1883 | list_del_init(&td->td_list); | |
1884 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1885 | if (!list_empty(&td->cancelled_td_list)) | |
1886 | list_del_init(&td->cancelled_td_list); | |
1887 | ||
1888 | inc_td_cnt(urb); | |
1889 | /* Giveback the urb when all the tds are completed */ | |
1890 | if (last_td_in_urb(td)) { | |
1891 | if ((urb->actual_length != urb->transfer_buffer_length && | |
1892 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
1893 | (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
1894 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", | |
1895 | urb, urb->actual_length, | |
1896 | urb->transfer_buffer_length, *status); | |
1897 | ||
1898 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
1899 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
1900 | *status = 0; | |
1901 | xhci_giveback_urb_in_irq(xhci, td, *status); | |
1902 | } | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
4422da61 | 1907 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
f97c08ae | 1908 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
4422da61 AX |
1909 | struct xhci_virt_ep *ep, int *status, bool skip) |
1910 | { | |
1911 | struct xhci_virt_device *xdev; | |
4422da61 | 1912 | struct xhci_ep_ctx *ep_ctx; |
be0f50c2 | 1913 | struct xhci_ring *ep_ring; |
be0f50c2 | 1914 | unsigned int slot_id; |
4422da61 | 1915 | u32 trb_comp_code; |
be0f50c2 | 1916 | int ep_index; |
4422da61 | 1917 | |
28ccd296 | 1918 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1919 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1920 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1921 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1922 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1923 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1924 | |
1925 | if (skip) | |
1926 | goto td_cleanup; | |
1927 | ||
0b7c105a FB |
1928 | if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
1929 | trb_comp_code == COMP_STOPPED || | |
1930 | trb_comp_code == COMP_STOPPED_SHORT_PACKET) { | |
4422da61 AX |
1931 | /* The Endpoint Stop Command completion will take care of any |
1932 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1933 | * the ring dequeue pointer or take this TD off any lists yet. | |
1934 | */ | |
4422da61 | 1935 | return 0; |
69defe04 | 1936 | } |
0b7c105a | 1937 | if (trb_comp_code == COMP_STALL_ERROR || |
69defe04 MN |
1938 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, |
1939 | trb_comp_code)) { | |
1940 | /* Issue a reset endpoint command to clear the host side | |
1941 | * halt, followed by a set dequeue command to move the | |
1942 | * dequeue pointer past the TD. | |
1943 | * The class driver clears the device side halt later. | |
1944 | */ | |
1945 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
f97c08ae | 1946 | ep_ring->stream_id, td, ep_trb); |
4422da61 | 1947 | } else { |
69defe04 MN |
1948 | /* Update ring dequeue pointer */ |
1949 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1950 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1951 | inc_deq(xhci, ep_ring); |
1952 | } | |
4422da61 AX |
1953 | |
1954 | td_cleanup: | |
55fa4396 | 1955 | return xhci_td_cleanup(xhci, td, ep_ring, status); |
4422da61 AX |
1956 | } |
1957 | ||
30a65b45 MN |
1958 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
1959 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1960 | union xhci_trb *stop_trb) | |
1961 | { | |
1962 | u32 sum; | |
1963 | union xhci_trb *trb = ring->dequeue; | |
1964 | struct xhci_segment *seg = ring->deq_seg; | |
1965 | ||
1966 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
1967 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
1968 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
1969 | } | |
1970 | return sum; | |
1971 | } | |
1972 | ||
8af56be1 AX |
1973 | /* |
1974 | * Process control tds, update urb status and actual_length. | |
1975 | */ | |
1976 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 1977 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
8af56be1 AX |
1978 | struct xhci_virt_ep *ep, int *status) |
1979 | { | |
1980 | struct xhci_virt_device *xdev; | |
1981 | struct xhci_ring *ep_ring; | |
1982 | unsigned int slot_id; | |
1983 | int ep_index; | |
1984 | struct xhci_ep_ctx *ep_ctx; | |
1985 | u32 trb_comp_code; | |
0b6c324c | 1986 | u32 remaining, requested; |
29fc1aa4 | 1987 | u32 trb_type; |
8af56be1 | 1988 | |
29fc1aa4 | 1989 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); |
28ccd296 | 1990 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1991 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1992 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1993 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1994 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1995 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
1996 | requested = td->urb->transfer_buffer_length; |
1997 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
1998 | ||
8af56be1 AX |
1999 | switch (trb_comp_code) { |
2000 | case COMP_SUCCESS: | |
29fc1aa4 | 2001 | if (trb_type != TRB_STATUS) { |
0b6c324c | 2002 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
29fc1aa4 | 2003 | (trb_type == TRB_DATA) ? "data" : "setup"); |
8af56be1 | 2004 | *status = -ESHUTDOWN; |
0b6c324c | 2005 | break; |
8af56be1 | 2006 | } |
0b6c324c | 2007 | *status = 0; |
8af56be1 | 2008 | break; |
0b7c105a | 2009 | case COMP_SHORT_PACKET: |
0b6c324c | 2010 | *status = 0; |
8af56be1 | 2011 | break; |
0b7c105a | 2012 | case COMP_STOPPED_SHORT_PACKET: |
29fc1aa4 | 2013 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2014 | td->urb->actual_length = remaining; |
40a3b775 | 2015 | else |
0b6c324c MN |
2016 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
2017 | goto finish_td; | |
0b7c105a | 2018 | case COMP_STOPPED: |
29fc1aa4 FB |
2019 | switch (trb_type) { |
2020 | case TRB_SETUP: | |
2021 | td->urb->actual_length = 0; | |
2022 | goto finish_td; | |
2023 | case TRB_DATA: | |
2024 | case TRB_NORMAL: | |
0b6c324c | 2025 | td->urb->actual_length = requested - remaining; |
29fc1aa4 | 2026 | goto finish_td; |
0ab2881a MN |
2027 | case TRB_STATUS: |
2028 | td->urb->actual_length = requested; | |
2029 | goto finish_td; | |
29fc1aa4 FB |
2030 | default: |
2031 | xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", | |
2032 | trb_type); | |
2033 | goto finish_td; | |
2034 | } | |
0b7c105a | 2035 | case COMP_STOPPED_LENGTH_INVALID: |
0b6c324c | 2036 | goto finish_td; |
8af56be1 AX |
2037 | default: |
2038 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2039 | ep_ctx, trb_comp_code)) |
8af56be1 | 2040 | break; |
0b6c324c MN |
2041 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
2042 | trb_comp_code, ep_index); | |
8af56be1 | 2043 | /* else fall through */ |
0b7c105a | 2044 | case COMP_STALL_ERROR: |
8af56be1 | 2045 | /* Did we transfer part of the data (middle) phase? */ |
29fc1aa4 | 2046 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2047 | td->urb->actual_length = requested - remaining; |
22ae47e6 | 2048 | else if (!td->urb_length_set) |
8af56be1 | 2049 | td->urb->actual_length = 0; |
0b6c324c | 2050 | goto finish_td; |
8af56be1 | 2051 | } |
0b6c324c MN |
2052 | |
2053 | /* stopped at setup stage, no data transferred */ | |
29fc1aa4 | 2054 | if (trb_type == TRB_SETUP) |
0b6c324c MN |
2055 | goto finish_td; |
2056 | ||
8af56be1 | 2057 | /* |
0b6c324c MN |
2058 | * if on data stage then update the actual_length of the URB and flag it |
2059 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2060 | */ |
29fc1aa4 FB |
2061 | if (trb_type == TRB_DATA || |
2062 | trb_type == TRB_NORMAL) { | |
0b6c324c MN |
2063 | td->urb_length_set = true; |
2064 | td->urb->actual_length = requested - remaining; | |
2065 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2066 | return 0; | |
8af56be1 AX |
2067 | } |
2068 | ||
0b6c324c MN |
2069 | /* at status stage */ |
2070 | if (!td->urb_length_set) | |
2071 | td->urb->actual_length = requested; | |
2072 | ||
2073 | finish_td: | |
f97c08ae | 2074 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
8af56be1 AX |
2075 | } |
2076 | ||
04e51901 AX |
2077 | /* |
2078 | * Process isochronous tds, update urb packet status and actual_length. | |
2079 | */ | |
2080 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2081 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
04e51901 AX |
2082 | struct xhci_virt_ep *ep, int *status) |
2083 | { | |
2084 | struct xhci_ring *ep_ring; | |
2085 | struct urb_priv *urb_priv; | |
2086 | int idx; | |
926008c9 | 2087 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2088 | u32 trb_comp_code; |
36da3a1d MN |
2089 | bool sum_trbs_for_length = false; |
2090 | u32 remaining, requested, ep_trb_len; | |
2091 | int short_framestatus; | |
04e51901 | 2092 | |
28ccd296 ME |
2093 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2094 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 | 2095 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2096 | idx = urb_priv->num_tds_done; |
926008c9 | 2097 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2098 | requested = frame->length; |
2099 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2100 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2101 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2102 | -EREMOTEIO : 0; | |
04e51901 | 2103 | |
926008c9 DT |
2104 | /* handle completion code */ |
2105 | switch (trb_comp_code) { | |
2106 | case COMP_SUCCESS: | |
36da3a1d MN |
2107 | if (remaining) { |
2108 | frame->status = short_framestatus; | |
2109 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2110 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2111 | break; |
2112 | } | |
36da3a1d MN |
2113 | frame->status = 0; |
2114 | break; | |
0b7c105a | 2115 | case COMP_SHORT_PACKET: |
36da3a1d MN |
2116 | frame->status = short_framestatus; |
2117 | sum_trbs_for_length = true; | |
926008c9 | 2118 | break; |
0b7c105a | 2119 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
926008c9 | 2120 | frame->status = -ECOMM; |
926008c9 | 2121 | break; |
0b7c105a FB |
2122 | case COMP_ISOCH_BUFFER_OVERRUN: |
2123 | case COMP_BABBLE_DETECTED_ERROR: | |
926008c9 | 2124 | frame->status = -EOVERFLOW; |
926008c9 | 2125 | break; |
0b7c105a FB |
2126 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
2127 | case COMP_STALL_ERROR: | |
d104d015 | 2128 | frame->status = -EPROTO; |
d104d015 | 2129 | break; |
0b7c105a | 2130 | case COMP_USB_TRANSACTION_ERROR: |
926008c9 | 2131 | frame->status = -EPROTO; |
f97c08ae | 2132 | if (ep_trb != td->last_trb) |
d104d015 | 2133 | return 0; |
926008c9 | 2134 | break; |
0b7c105a | 2135 | case COMP_STOPPED: |
36da3a1d MN |
2136 | sum_trbs_for_length = true; |
2137 | break; | |
0b7c105a | 2138 | case COMP_STOPPED_SHORT_PACKET: |
36da3a1d MN |
2139 | /* field normally containing residue now contains tranferred */ |
2140 | frame->status = short_framestatus; | |
2141 | requested = remaining; | |
2142 | break; | |
0b7c105a | 2143 | case COMP_STOPPED_LENGTH_INVALID: |
36da3a1d MN |
2144 | requested = 0; |
2145 | remaining = 0; | |
926008c9 DT |
2146 | break; |
2147 | default: | |
36da3a1d | 2148 | sum_trbs_for_length = true; |
926008c9 DT |
2149 | frame->status = -1; |
2150 | break; | |
04e51901 AX |
2151 | } |
2152 | ||
36da3a1d MN |
2153 | if (sum_trbs_for_length) |
2154 | frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + | |
2155 | ep_trb_len - remaining; | |
2156 | else | |
2157 | frame->actual_length = requested; | |
04e51901 | 2158 | |
36da3a1d | 2159 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2160 | |
f97c08ae | 2161 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
04e51901 AX |
2162 | } |
2163 | ||
926008c9 DT |
2164 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2165 | struct xhci_transfer_event *event, | |
2166 | struct xhci_virt_ep *ep, int *status) | |
2167 | { | |
2168 | struct xhci_ring *ep_ring; | |
2169 | struct urb_priv *urb_priv; | |
2170 | struct usb_iso_packet_descriptor *frame; | |
2171 | int idx; | |
2172 | ||
f6975314 | 2173 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 | 2174 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2175 | idx = urb_priv->num_tds_done; |
926008c9 DT |
2176 | frame = &td->urb->iso_frame_desc[idx]; |
2177 | ||
b3df3f9c | 2178 | /* The transfer is partly done. */ |
926008c9 DT |
2179 | frame->status = -EXDEV; |
2180 | ||
2181 | /* calc actual length */ | |
2182 | frame->actual_length = 0; | |
2183 | ||
2184 | /* Update ring dequeue pointer */ | |
2185 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2186 | inc_deq(xhci, ep_ring); |
2187 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2188 | |
2189 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2190 | } | |
2191 | ||
22405ed2 AX |
2192 | /* |
2193 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2194 | */ | |
2195 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2196 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
22405ed2 AX |
2197 | struct xhci_virt_ep *ep, int *status) |
2198 | { | |
2199 | struct xhci_ring *ep_ring; | |
22405ed2 | 2200 | u32 trb_comp_code; |
f97c08ae | 2201 | u32 remaining, requested, ep_trb_len; |
22405ed2 | 2202 | |
28ccd296 ME |
2203 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2204 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
30a65b45 | 2205 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2206 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2207 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2208 | |
2209 | switch (trb_comp_code) { | |
2210 | case COMP_SUCCESS: | |
30a65b45 | 2211 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2212 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2213 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2214 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2215 | td->urb->ep->desc.bEndpointAddress, | |
2216 | requested, remaining); | |
22405ed2 | 2217 | } |
52ab8685 | 2218 | *status = 0; |
22405ed2 | 2219 | break; |
0b7c105a | 2220 | case COMP_SHORT_PACKET: |
30a65b45 MN |
2221 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2222 | td->urb->ep->desc.bEndpointAddress, | |
2223 | requested, remaining); | |
52ab8685 | 2224 | *status = 0; |
22405ed2 | 2225 | break; |
0b7c105a | 2226 | case COMP_STOPPED_SHORT_PACKET: |
30a65b45 MN |
2227 | td->urb->actual_length = remaining; |
2228 | goto finish_td; | |
0b7c105a | 2229 | case COMP_STOPPED_LENGTH_INVALID: |
30a65b45 | 2230 | /* stopped on ep trb with invalid length, exclude it */ |
f97c08ae | 2231 | ep_trb_len = 0; |
30a65b45 MN |
2232 | remaining = 0; |
2233 | break; | |
22405ed2 | 2234 | default: |
30a65b45 | 2235 | /* do nothing */ |
22405ed2 AX |
2236 | break; |
2237 | } | |
40a3b775 | 2238 | |
f97c08ae | 2239 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2240 | td->urb->actual_length = requested - remaining; |
2241 | else | |
2242 | td->urb->actual_length = | |
f97c08ae MN |
2243 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2244 | ep_trb_len - remaining; | |
30a65b45 MN |
2245 | finish_td: |
2246 | if (remaining > requested) { | |
2247 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2248 | remaining); | |
22405ed2 | 2249 | td->urb->actual_length = 0; |
22405ed2 | 2250 | } |
f97c08ae | 2251 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
22405ed2 AX |
2252 | } |
2253 | ||
d0e96f5a SS |
2254 | /* |
2255 | * If this function returns an error condition, it means it got a Transfer | |
2256 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2257 | * At this point, the host controller is probably hosed and should be reset. | |
2258 | */ | |
2259 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2260 | struct xhci_transfer_event *event) | |
2261 | { | |
2262 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2263 | struct xhci_virt_ep *ep; |
d0e96f5a | 2264 | struct xhci_ring *ep_ring; |
82d1009f | 2265 | unsigned int slot_id; |
d0e96f5a | 2266 | int ep_index; |
326b4810 | 2267 | struct xhci_td *td = NULL; |
f97c08ae MN |
2268 | dma_addr_t ep_trb_dma; |
2269 | struct xhci_segment *ep_seg; | |
2270 | union xhci_trb *ep_trb; | |
d0e96f5a | 2271 | int status = -EINPROGRESS; |
d115b048 | 2272 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2273 | struct list_head *tmp; |
66d1eebc | 2274 | u32 trb_comp_code; |
c2d7b49f | 2275 | int td_num = 0; |
3b4739b8 | 2276 | bool handling_skipped_tds = false; |
d0e96f5a | 2277 | |
28ccd296 | 2278 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2279 | xdev = xhci->devs[slot_id]; |
d0e96f5a | 2280 | if (!xdev) { |
b7f769ae ZX |
2281 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", |
2282 | slot_id); | |
9258c0b2 | 2283 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2284 | (unsigned long long) xhci_trb_virt_to_dma( |
2285 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2286 | xhci->event_ring->dequeue), |
2287 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2288 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2289 | le32_to_cpu(event->transfer_len), | |
2290 | le32_to_cpu(event->flags)); | |
d0e96f5a SS |
2291 | return -ENODEV; |
2292 | } | |
2293 | ||
2294 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2295 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2296 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2297 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2298 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
5071e6b2 | 2299 | if (!ep_ring || GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
b7f769ae ZX |
2300 | xhci_err(xhci, |
2301 | "ERROR Transfer event for disabled endpoint slot %u ep %u or incorrect stream ring\n", | |
2302 | slot_id, ep_index); | |
9258c0b2 | 2303 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2304 | (unsigned long long) xhci_trb_virt_to_dma( |
2305 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2306 | xhci->event_ring->dequeue), |
2307 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2308 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2309 | le32_to_cpu(event->transfer_len), | |
2310 | le32_to_cpu(event->flags)); | |
d0e96f5a SS |
2311 | return -ENODEV; |
2312 | } | |
2313 | ||
c2d7b49f AX |
2314 | /* Count current td numbers if ep->skip is set */ |
2315 | if (ep->skip) { | |
2316 | list_for_each(tmp, &ep_ring->td_list) | |
2317 | td_num++; | |
2318 | } | |
2319 | ||
f97c08ae | 2320 | ep_trb_dma = le64_to_cpu(event->buffer); |
28ccd296 | 2321 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
986a92d4 | 2322 | /* Look for common error cases */ |
66d1eebc | 2323 | switch (trb_comp_code) { |
b10de142 SS |
2324 | /* Skip codes that require special handling depending on |
2325 | * transfer type | |
2326 | */ | |
2327 | case COMP_SUCCESS: | |
1c11a172 | 2328 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2329 | break; |
2330 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
0b7c105a | 2331 | trb_comp_code = COMP_SHORT_PACKET; |
1530bbc6 | 2332 | else |
8202ce2e | 2333 | xhci_warn_ratelimited(xhci, |
b7f769ae ZX |
2334 | "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", |
2335 | slot_id, ep_index); | |
0b7c105a | 2336 | case COMP_SHORT_PACKET: |
b10de142 | 2337 | break; |
0b7c105a | 2338 | case COMP_STOPPED: |
b7f769ae ZX |
2339 | xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", |
2340 | slot_id, ep_index); | |
ae636747 | 2341 | break; |
0b7c105a | 2342 | case COMP_STOPPED_LENGTH_INVALID: |
b7f769ae ZX |
2343 | xhci_dbg(xhci, |
2344 | "Stopped on No-op or Link TRB for slot %u ep %u\n", | |
2345 | slot_id, ep_index); | |
ae636747 | 2346 | break; |
0b7c105a | 2347 | case COMP_STOPPED_SHORT_PACKET: |
b7f769ae ZX |
2348 | xhci_dbg(xhci, |
2349 | "Stopped with short packet transfer detected for slot %u ep %u\n", | |
2350 | slot_id, ep_index); | |
40a3b775 | 2351 | break; |
0b7c105a | 2352 | case COMP_STALL_ERROR: |
b7f769ae ZX |
2353 | xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, |
2354 | ep_index); | |
63a0d9ab | 2355 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2356 | status = -EPIPE; |
2357 | break; | |
0b7c105a | 2358 | case COMP_TRB_ERROR: |
b7f769ae ZX |
2359 | xhci_warn(xhci, |
2360 | "WARN: TRB error for slot %u ep %u on endpoint\n", | |
2361 | slot_id, ep_index); | |
b10de142 SS |
2362 | status = -EILSEQ; |
2363 | break; | |
0b7c105a FB |
2364 | case COMP_SPLIT_TRANSACTION_ERROR: |
2365 | case COMP_USB_TRANSACTION_ERROR: | |
b7f769ae ZX |
2366 | xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", |
2367 | slot_id, ep_index); | |
b10de142 SS |
2368 | status = -EPROTO; |
2369 | break; | |
0b7c105a | 2370 | case COMP_BABBLE_DETECTED_ERROR: |
b7f769ae ZX |
2371 | xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", |
2372 | slot_id, ep_index); | |
4a73143c SS |
2373 | status = -EOVERFLOW; |
2374 | break; | |
0b7c105a | 2375 | case COMP_DATA_BUFFER_ERROR: |
b7f769ae ZX |
2376 | xhci_warn(xhci, |
2377 | "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", | |
2378 | slot_id, ep_index); | |
b10de142 SS |
2379 | status = -ENOSR; |
2380 | break; | |
0b7c105a | 2381 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
b7f769ae ZX |
2382 | xhci_warn(xhci, |
2383 | "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", | |
2384 | slot_id, ep_index); | |
986a92d4 | 2385 | break; |
0b7c105a | 2386 | case COMP_ISOCH_BUFFER_OVERRUN: |
b7f769ae ZX |
2387 | xhci_warn(xhci, |
2388 | "WARN: buffer overrun event for slot %u ep %u on endpoint", | |
2389 | slot_id, ep_index); | |
986a92d4 | 2390 | break; |
0b7c105a | 2391 | case COMP_RING_UNDERRUN: |
986a92d4 AX |
2392 | /* |
2393 | * When the Isoch ring is empty, the xHC will generate | |
2394 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2395 | * Underrun Event for OUT Isoch endpoint. | |
2396 | */ | |
2397 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2398 | if (!list_empty(&ep_ring->td_list)) | |
2399 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2400 | "still with TDs queued?\n", | |
28ccd296 ME |
2401 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2402 | ep_index); | |
986a92d4 | 2403 | goto cleanup; |
0b7c105a | 2404 | case COMP_RING_OVERRUN: |
986a92d4 AX |
2405 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
2406 | if (!list_empty(&ep_ring->td_list)) | |
2407 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2408 | "still with TDs queued?\n", | |
28ccd296 ME |
2409 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2410 | ep_index); | |
986a92d4 | 2411 | goto cleanup; |
0b7c105a | 2412 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
b7f769ae ZX |
2413 | xhci_warn(xhci, |
2414 | "WARN: detect an incompatible device for slot %u ep %u", | |
2415 | slot_id, ep_index); | |
f6ba6fe2 AH |
2416 | status = -EPROTO; |
2417 | break; | |
0b7c105a | 2418 | case COMP_MISSED_SERVICE_ERROR: |
d18240db AX |
2419 | /* |
2420 | * When encounter missed service error, one or more isoc tds | |
2421 | * may be missed by xHC. | |
2422 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2423 | * short transfer when process the ep_ring next time. | |
2424 | */ | |
2425 | ep->skip = true; | |
b7f769ae ZX |
2426 | xhci_dbg(xhci, |
2427 | "Miss service interval error for slot %u ep %u, set skip flag\n", | |
2428 | slot_id, ep_index); | |
d18240db | 2429 | goto cleanup; |
0b7c105a | 2430 | case COMP_NO_PING_RESPONSE_ERROR: |
3b4739b8 | 2431 | ep->skip = true; |
b7f769ae ZX |
2432 | xhci_dbg(xhci, |
2433 | "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", | |
2434 | slot_id, ep_index); | |
3b4739b8 | 2435 | goto cleanup; |
b10de142 | 2436 | default: |
b45b5069 | 2437 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2438 | status = 0; |
2439 | break; | |
2440 | } | |
b7f769ae ZX |
2441 | xhci_warn(xhci, |
2442 | "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", | |
2443 | trb_comp_code, slot_id, ep_index); | |
986a92d4 AX |
2444 | goto cleanup; |
2445 | } | |
2446 | ||
d18240db AX |
2447 | do { |
2448 | /* This TRB should be in the TD at the head of this ring's | |
2449 | * TD list. | |
2450 | */ | |
2451 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2452 | /* |
2453 | * A stopped endpoint may generate an extra completion | |
2454 | * event if the device was suspended. Don't print | |
2455 | * warnings. | |
2456 | */ | |
0b7c105a FB |
2457 | if (!(trb_comp_code == COMP_STOPPED || |
2458 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
a83d6755 SS |
2459 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
2460 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2461 | ep_index); | |
a83d6755 | 2462 | } |
d18240db AX |
2463 | if (ep->skip) { |
2464 | ep->skip = false; | |
b7f769ae ZX |
2465 | xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", |
2466 | slot_id, ep_index); | |
d18240db | 2467 | } |
d18240db AX |
2468 | goto cleanup; |
2469 | } | |
986a92d4 | 2470 | |
c2d7b49f AX |
2471 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2472 | if (ep->skip && td_num == 0) { | |
2473 | ep->skip = false; | |
b7f769ae ZX |
2474 | xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", |
2475 | slot_id, ep_index); | |
c2d7b49f AX |
2476 | goto cleanup; |
2477 | } | |
2478 | ||
04861f83 FB |
2479 | td = list_first_entry(&ep_ring->td_list, struct xhci_td, |
2480 | td_list); | |
c2d7b49f AX |
2481 | if (ep->skip) |
2482 | td_num--; | |
926008c9 | 2483 | |
d18240db | 2484 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2485 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2486 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2487 | |
2488 | /* | |
2489 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2490 | * is not in the current TD pointed by ep_ring->dequeue because | |
2491 | * that the hardware dequeue pointer still at the previous TRB | |
2492 | * of the current TD. The previous TRB maybe a Link TD or the | |
2493 | * last TRB of the previous TD. The command completion handle | |
2494 | * will take care the rest. | |
2495 | */ | |
0b7c105a FB |
2496 | if (!ep_seg && (trb_comp_code == COMP_STOPPED || |
2497 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
e1cf486d AH |
2498 | goto cleanup; |
2499 | } | |
2500 | ||
f97c08ae | 2501 | if (!ep_seg) { |
926008c9 DT |
2502 | if (!ep->skip || |
2503 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2504 | /* Some host controllers give a spurious |
2505 | * successful event after a short transfer. | |
2506 | * Ignore it. | |
2507 | */ | |
ddba5cd0 | 2508 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2509 | ep_ring->last_td_was_short) { |
2510 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2511 | goto cleanup; |
2512 | } | |
926008c9 DT |
2513 | /* HC is busted, give up! */ |
2514 | xhci_err(xhci, | |
2515 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2516 | "part of current TD ep_index %d " |
2517 | "comp_code %u\n", ep_index, | |
2518 | trb_comp_code); | |
2519 | trb_in_td(xhci, ep_ring->deq_seg, | |
2520 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2521 | ep_trb_dma, true); |
926008c9 DT |
2522 | return -ESHUTDOWN; |
2523 | } | |
2524 | ||
0c03d89d | 2525 | skip_isoc_td(xhci, td, event, ep, &status); |
926008c9 DT |
2526 | goto cleanup; |
2527 | } | |
0b7c105a | 2528 | if (trb_comp_code == COMP_SHORT_PACKET) |
ad808333 SS |
2529 | ep_ring->last_td_was_short = true; |
2530 | else | |
2531 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2532 | |
2533 | if (ep->skip) { | |
b7f769ae ZX |
2534 | xhci_dbg(xhci, |
2535 | "Found td. Clear skip flag for slot %u ep %u.\n", | |
2536 | slot_id, ep_index); | |
d18240db AX |
2537 | ep->skip = false; |
2538 | } | |
678539cf | 2539 | |
f97c08ae MN |
2540 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2541 | sizeof(*ep_trb)]; | |
a37c3f76 FB |
2542 | |
2543 | trace_xhci_handle_transfer(ep_ring, | |
2544 | (struct xhci_generic_trb *) ep_trb); | |
2545 | ||
926008c9 DT |
2546 | /* |
2547 | * No-op TRB should not trigger interrupts. | |
f97c08ae | 2548 | * If ep_trb is a no-op TRB, it means the |
926008c9 DT |
2549 | * corresponding TD has been cancelled. Just ignore |
2550 | * the TD. | |
2551 | */ | |
f97c08ae | 2552 | if (trb_is_noop(ep_trb)) { |
b7f769ae ZX |
2553 | xhci_dbg(xhci, |
2554 | "ep_trb is a no-op TRB. Skip it for slot %u ep %u\n", | |
2555 | slot_id, ep_index); | |
926008c9 | 2556 | goto cleanup; |
d18240db | 2557 | } |
4422da61 | 2558 | |
0c03d89d | 2559 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2560 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
0c03d89d | 2561 | process_ctrl_td(xhci, td, ep_trb, event, ep, &status); |
04e51901 | 2562 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
0c03d89d | 2563 | process_isoc_td(xhci, td, ep_trb, event, ep, &status); |
d18240db | 2564 | else |
0c03d89d MN |
2565 | process_bulk_intr_td(xhci, td, ep_trb, event, ep, |
2566 | &status); | |
d18240db | 2567 | cleanup: |
3b4739b8 | 2568 | handling_skipped_tds = ep->skip && |
0b7c105a FB |
2569 | trb_comp_code != COMP_MISSED_SERVICE_ERROR && |
2570 | trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; | |
3b4739b8 | 2571 | |
d18240db | 2572 | /* |
3b4739b8 MN |
2573 | * Do not update event ring dequeue pointer if we're in a loop |
2574 | * processing missed tds. | |
d18240db | 2575 | */ |
3b4739b8 | 2576 | if (!handling_skipped_tds) |
3b72fca0 | 2577 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2578 | |
d18240db AX |
2579 | /* |
2580 | * If ep->skip is set, it means there are missed tds on the | |
2581 | * endpoint ring need to take care of. | |
2582 | * Process them as short transfer until reach the td pointed by | |
2583 | * the event. | |
2584 | */ | |
3b4739b8 | 2585 | } while (handling_skipped_tds); |
d18240db | 2586 | |
d0e96f5a SS |
2587 | return 0; |
2588 | } | |
2589 | ||
0f2a7930 SS |
2590 | /* |
2591 | * This function handles all OS-owned events on the event ring. It may drop | |
2592 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2593 | * Returns >0 for "possibly more events to process" (caller should call again), |
2594 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2595 | */ |
9dee9a21 | 2596 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2597 | { |
2598 | union xhci_trb *event; | |
0f2a7930 | 2599 | int update_ptrs = 1; |
d0e96f5a | 2600 | int ret; |
7f84eef0 | 2601 | |
f4c8f03c | 2602 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2603 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2604 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2605 | return -ENOMEM; | |
7f84eef0 SS |
2606 | } |
2607 | ||
2608 | event = xhci->event_ring->dequeue; | |
2609 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2610 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2611 | xhci->event_ring->cycle_state) |
9dee9a21 | 2612 | return 0; |
7f84eef0 | 2613 | |
a37c3f76 FB |
2614 | trace_xhci_handle_event(xhci->event_ring, &event->generic); |
2615 | ||
92a3da41 ME |
2616 | /* |
2617 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2618 | * speculative reads of the event's flags/data below. | |
2619 | */ | |
2620 | rmb(); | |
0f2a7930 | 2621 | /* FIXME: Handle more event types. */ |
f4c8f03c | 2622 | switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { |
7f84eef0 SS |
2623 | case TRB_TYPE(TRB_COMPLETION): |
2624 | handle_cmd_completion(xhci, &event->event_cmd); | |
2625 | break; | |
0f2a7930 SS |
2626 | case TRB_TYPE(TRB_PORT_STATUS): |
2627 | handle_port_status(xhci, event); | |
2628 | update_ptrs = 0; | |
2629 | break; | |
d0e96f5a SS |
2630 | case TRB_TYPE(TRB_TRANSFER): |
2631 | ret = handle_tx_event(xhci, &event->trans_event); | |
f4c8f03c | 2632 | if (ret >= 0) |
d0e96f5a SS |
2633 | update_ptrs = 0; |
2634 | break; | |
623bef9e SS |
2635 | case TRB_TYPE(TRB_DEV_NOTE): |
2636 | handle_device_notification(xhci, event); | |
2637 | break; | |
7f84eef0 | 2638 | default: |
28ccd296 ME |
2639 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2640 | TRB_TYPE(48)) | |
0238634d SS |
2641 | handle_vendor_event(xhci, event); |
2642 | else | |
f4c8f03c LB |
2643 | xhci_warn(xhci, "ERROR unknown event type %d\n", |
2644 | TRB_FIELD_TO_TYPE( | |
2645 | le32_to_cpu(event->event_cmd.flags))); | |
7f84eef0 | 2646 | } |
6f5165cf SS |
2647 | /* Any of the above functions may drop and re-acquire the lock, so check |
2648 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2649 | */ | |
2650 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2651 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2652 | "event handler.\n"); | |
9dee9a21 | 2653 | return 0; |
6f5165cf | 2654 | } |
7f84eef0 | 2655 | |
c06d68b8 SS |
2656 | if (update_ptrs) |
2657 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2658 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2659 | |
9dee9a21 ME |
2660 | /* Are there more items on the event ring? Caller will call us again to |
2661 | * check. | |
2662 | */ | |
2663 | return 1; | |
7f84eef0 | 2664 | } |
9032cd52 SS |
2665 | |
2666 | /* | |
2667 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2668 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2669 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2670 | */ | |
2671 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2672 | { | |
2673 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c06d68b8 | 2674 | union xhci_trb *event_ring_deq; |
76a35293 | 2675 | irqreturn_t ret = IRQ_NONE; |
63aea0db | 2676 | unsigned long flags; |
c06d68b8 | 2677 | dma_addr_t deq; |
76a35293 FB |
2678 | u64 temp_64; |
2679 | u32 status; | |
9032cd52 | 2680 | |
63aea0db | 2681 | spin_lock_irqsave(&xhci->lock, flags); |
9032cd52 | 2682 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2683 | status = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
2684 | if (status == ~(u32)0) { |
2685 | xhci_hc_died(xhci); | |
76a35293 FB |
2686 | ret = IRQ_HANDLED; |
2687 | goto out; | |
9032cd52 | 2688 | } |
76a35293 FB |
2689 | |
2690 | if (!(status & STS_EINT)) | |
2691 | goto out; | |
2692 | ||
27e0dd4d | 2693 | if (status & STS_FATAL) { |
9032cd52 SS |
2694 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2695 | xhci_halt(xhci); | |
76a35293 FB |
2696 | ret = IRQ_HANDLED; |
2697 | goto out; | |
9032cd52 SS |
2698 | } |
2699 | ||
bda53145 SS |
2700 | /* |
2701 | * Clear the op reg interrupt status first, | |
2702 | * so we can receive interrupts from other MSI-X interrupters. | |
2703 | * Write 1 to clear the interrupt status. | |
2704 | */ | |
27e0dd4d | 2705 | status |= STS_EINT; |
204b7793 | 2706 | writel(status, &xhci->op_regs->status); |
bda53145 | 2707 | |
6a29beef | 2708 | if (!hcd->msi_enabled) { |
c21599a3 | 2709 | u32 irq_pending; |
b0ba9720 | 2710 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2711 | irq_pending |= IMAN_IP; |
204b7793 | 2712 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2713 | } |
bda53145 | 2714 | |
27a41a83 GKB |
2715 | if (xhci->xhc_state & XHCI_STATE_DYING || |
2716 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
2717 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2718 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2719 | /* Clear the event handler busy flag (RW1C); |
2720 | * the event ring should be empty. | |
bda53145 | 2721 | */ |
f7b2e403 | 2722 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2723 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2724 | &xhci->ir_set->erst_dequeue); | |
76a35293 FB |
2725 | ret = IRQ_HANDLED; |
2726 | goto out; | |
c06d68b8 SS |
2727 | } |
2728 | ||
2729 | event_ring_deq = xhci->event_ring->dequeue; | |
2730 | /* FIXME this should be a delayed service routine | |
2731 | * that clears the EHB. | |
2732 | */ | |
9dee9a21 | 2733 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2734 | |
f7b2e403 | 2735 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2736 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2737 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2738 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2739 | xhci->event_ring->dequeue); | |
2740 | if (deq == 0) | |
2741 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2742 | "ring dequeue ptr.\n"); | |
2743 | /* Update HC event ring dequeue pointer */ | |
2744 | temp_64 &= ERST_PTR_MASK; | |
2745 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2746 | } | |
2747 | ||
2748 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2749 | temp_64 |= ERST_EHB; | |
477632df | 2750 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
76a35293 | 2751 | ret = IRQ_HANDLED; |
c06d68b8 | 2752 | |
76a35293 | 2753 | out: |
63aea0db | 2754 | spin_unlock_irqrestore(&xhci->lock, flags); |
9032cd52 | 2755 | |
76a35293 | 2756 | return ret; |
9032cd52 SS |
2757 | } |
2758 | ||
851ec164 | 2759 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2760 | { |
968b822c | 2761 | return xhci_irq(hcd); |
9032cd52 | 2762 | } |
7f84eef0 | 2763 | |
d0e96f5a SS |
2764 | /**** Endpoint Ring Operations ****/ |
2765 | ||
7f84eef0 SS |
2766 | /* |
2767 | * Generic function for queueing a TRB on a ring. | |
2768 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2769 | * |
2770 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2771 | * prepare_transfer()? | |
7f84eef0 SS |
2772 | */ |
2773 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2774 | bool more_trbs_coming, |
7f84eef0 SS |
2775 | u32 field1, u32 field2, u32 field3, u32 field4) |
2776 | { | |
2777 | struct xhci_generic_trb *trb; | |
2778 | ||
2779 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2780 | trb->field[0] = cpu_to_le32(field1); |
2781 | trb->field[1] = cpu_to_le32(field2); | |
2782 | trb->field[2] = cpu_to_le32(field3); | |
2783 | trb->field[3] = cpu_to_le32(field4); | |
a37c3f76 FB |
2784 | |
2785 | trace_xhci_queue_trb(ring, trb); | |
2786 | ||
3b72fca0 | 2787 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2788 | } |
2789 | ||
d0e96f5a SS |
2790 | /* |
2791 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2792 | * FIXME allocate segments if the ring is full. | |
2793 | */ | |
2794 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2795 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2796 | { |
8dfec614 AX |
2797 | unsigned int num_trbs_needed; |
2798 | ||
d0e96f5a | 2799 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2800 | switch (ep_state) { |
2801 | case EP_STATE_DISABLED: | |
2802 | /* | |
2803 | * USB core changed config/interfaces without notifying us, | |
2804 | * or hardware is reporting the wrong state. | |
2805 | */ | |
2806 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2807 | return -ENOENT; | |
d0e96f5a | 2808 | case EP_STATE_ERROR: |
c92bcfa7 | 2809 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2810 | /* FIXME event handling code for error needs to clear it */ |
2811 | /* XXX not sure if this should be -ENOENT or not */ | |
2812 | return -EINVAL; | |
c92bcfa7 SS |
2813 | case EP_STATE_HALTED: |
2814 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2815 | case EP_STATE_STOPPED: |
2816 | case EP_STATE_RUNNING: | |
2817 | break; | |
2818 | default: | |
2819 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2820 | /* | |
2821 | * FIXME issue Configure Endpoint command to try to get the HC | |
2822 | * back into a known state. | |
2823 | */ | |
2824 | return -EINVAL; | |
2825 | } | |
8dfec614 AX |
2826 | |
2827 | while (1) { | |
3d4b81ed SS |
2828 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2829 | break; | |
8dfec614 AX |
2830 | |
2831 | if (ep_ring == xhci->cmd_ring) { | |
2832 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2833 | return -ENOMEM; | |
2834 | } | |
2835 | ||
68ffb011 XR |
2836 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2837 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2838 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2839 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2840 | mem_flags)) { | |
2841 | xhci_err(xhci, "Ring expansion failed\n"); | |
2842 | return -ENOMEM; | |
2843 | } | |
261fa12b | 2844 | } |
6c12db90 | 2845 | |
d0c77d84 MN |
2846 | while (trb_is_link(ep_ring->enqueue)) { |
2847 | /* If we're not dealing with 0.95 hardware or isoc rings | |
2848 | * on AMD 0.96 host, clear the chain bit. | |
2849 | */ | |
2850 | if (!xhci_link_trb_quirk(xhci) && | |
2851 | !(ep_ring->type == TYPE_ISOC && | |
2852 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
2853 | ep_ring->enqueue->link.control &= | |
2854 | cpu_to_le32(~TRB_CHAIN); | |
2855 | else | |
2856 | ep_ring->enqueue->link.control |= | |
2857 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 2858 | |
d0c77d84 MN |
2859 | wmb(); |
2860 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 2861 | |
d0c77d84 MN |
2862 | /* Toggle the cycle bit after the last ring segment. */ |
2863 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
2864 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 2865 | |
d0c77d84 MN |
2866 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
2867 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
6c12db90 | 2868 | } |
d0e96f5a SS |
2869 | return 0; |
2870 | } | |
2871 | ||
23e3be11 | 2872 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2873 | struct xhci_virt_device *xdev, |
2874 | unsigned int ep_index, | |
e9df17eb | 2875 | unsigned int stream_id, |
d0e96f5a SS |
2876 | unsigned int num_trbs, |
2877 | struct urb *urb, | |
8e51adcc | 2878 | unsigned int td_index, |
d0e96f5a SS |
2879 | gfp_t mem_flags) |
2880 | { | |
2881 | int ret; | |
8e51adcc AX |
2882 | struct urb_priv *urb_priv; |
2883 | struct xhci_td *td; | |
e9df17eb | 2884 | struct xhci_ring *ep_ring; |
d115b048 | 2885 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2886 | |
2887 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2888 | if (!ep_ring) { | |
2889 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2890 | stream_id); | |
2891 | return -EINVAL; | |
2892 | } | |
2893 | ||
5071e6b2 | 2894 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 2895 | num_trbs, mem_flags); |
d0e96f5a SS |
2896 | if (ret) |
2897 | return ret; | |
d0e96f5a | 2898 | |
8e51adcc | 2899 | urb_priv = urb->hcpriv; |
7e64b037 | 2900 | td = &urb_priv->td[td_index]; |
8e51adcc AX |
2901 | |
2902 | INIT_LIST_HEAD(&td->td_list); | |
2903 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2904 | ||
2905 | if (td_index == 0) { | |
214f76f7 | 2906 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2907 | if (unlikely(ret)) |
8e51adcc | 2908 | return ret; |
d0e96f5a SS |
2909 | } |
2910 | ||
8e51adcc | 2911 | td->urb = urb; |
d0e96f5a | 2912 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2913 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2914 | td->start_seg = ep_ring->enq_seg; | |
2915 | td->first_trb = ep_ring->enqueue; | |
2916 | ||
d0e96f5a SS |
2917 | return 0; |
2918 | } | |
2919 | ||
d2510342 AI |
2920 | static unsigned int count_trbs(u64 addr, u64 len) |
2921 | { | |
2922 | unsigned int num_trbs; | |
2923 | ||
2924 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
2925 | TRB_MAX_BUFF_SIZE); | |
2926 | if (num_trbs == 0) | |
2927 | num_trbs++; | |
2928 | ||
2929 | return num_trbs; | |
2930 | } | |
2931 | ||
2932 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
2933 | { | |
2934 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
2935 | } | |
2936 | ||
2937 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 2938 | { |
8a96c052 | 2939 | struct scatterlist *sg; |
d2510342 | 2940 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 2941 | |
d2510342 | 2942 | full_len = urb->transfer_buffer_length; |
8a96c052 | 2943 | |
d2510342 AI |
2944 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
2945 | len = sg_dma_len(sg); | |
2946 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
2947 | len = min_t(unsigned int, len, full_len); | |
2948 | full_len -= len; | |
2949 | if (full_len == 0) | |
8a96c052 SS |
2950 | break; |
2951 | } | |
d2510342 | 2952 | |
8a96c052 SS |
2953 | return num_trbs; |
2954 | } | |
2955 | ||
d2510342 AI |
2956 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
2957 | { | |
2958 | u64 addr, len; | |
2959 | ||
2960 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
2961 | len = urb->iso_frame_desc[i].length; | |
2962 | ||
2963 | return count_trbs(addr, len); | |
2964 | } | |
2965 | ||
2966 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 2967 | { |
d2510342 | 2968 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 2969 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2970 | "queued %#x (%d), asked for %#x (%d)\n", |
2971 | __func__, | |
2972 | urb->ep->desc.bEndpointAddress, | |
2973 | running_total, running_total, | |
2974 | urb->transfer_buffer_length, | |
2975 | urb->transfer_buffer_length); | |
2976 | } | |
2977 | ||
23e3be11 | 2978 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2979 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2980 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2981 | { |
8a96c052 SS |
2982 | /* |
2983 | * Pass all the TRBs to the hardware at once and make sure this write | |
2984 | * isn't reordered. | |
2985 | */ | |
2986 | wmb(); | |
50f7b52a | 2987 | if (start_cycle) |
28ccd296 | 2988 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 2989 | else |
28ccd296 | 2990 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 2991 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2992 | } |
2993 | ||
78140156 AI |
2994 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
2995 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 2996 | { |
624defa1 SS |
2997 | int xhci_interval; |
2998 | int ep_interval; | |
2999 | ||
28ccd296 | 3000 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3001 | ep_interval = urb->interval; |
78140156 | 3002 | |
624defa1 SS |
3003 | /* Convert to microframes */ |
3004 | if (urb->dev->speed == USB_SPEED_LOW || | |
3005 | urb->dev->speed == USB_SPEED_FULL) | |
3006 | ep_interval *= 8; | |
78140156 | 3007 | |
624defa1 SS |
3008 | /* FIXME change this to a warning and a suggestion to use the new API |
3009 | * to set the polling interval (once the API is added). | |
3010 | */ | |
3011 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3012 | dev_dbg_ratelimited(&urb->dev->dev, |
3013 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3014 | ep_interval, ep_interval == 1 ? "" : "s", | |
3015 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3016 | urb->interval = xhci_interval; |
3017 | /* Convert back to frames for LS/FS devices */ | |
3018 | if (urb->dev->speed == USB_SPEED_LOW || | |
3019 | urb->dev->speed == USB_SPEED_FULL) | |
3020 | urb->interval /= 8; | |
3021 | } | |
78140156 AI |
3022 | } |
3023 | ||
3024 | /* | |
3025 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3026 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3027 | * (comprised of sg list entries) can take several service intervals to | |
3028 | * transmit. | |
3029 | */ | |
3030 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3031 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3032 | { | |
3033 | struct xhci_ep_ctx *ep_ctx; | |
3034 | ||
3035 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3036 | check_interval(xhci, urb, ep_ctx); | |
3037 | ||
3fc8206d | 3038 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3039 | } |
3040 | ||
4da6e6f2 | 3041 | /* |
4525c0a1 SS |
3042 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3043 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3044 | * |
3045 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3046 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3047 | * |
3048 | * Packets transferred up to and including this TRB = packets_transferred = | |
3049 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3050 | * | |
3051 | * TD size = total_packet_count - packets_transferred | |
3052 | * | |
c840d6ce MN |
3053 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3054 | * including this TRB, right shifted by 10 | |
3055 | * | |
3056 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3057 | * This is taken care of in the TRB_TD_SIZE() macro | |
3058 | * | |
4525c0a1 | 3059 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3060 | */ |
c840d6ce MN |
3061 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3062 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3063 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3064 | { |
c840d6ce MN |
3065 | u32 maxp, total_packet_count; |
3066 | ||
0cbd4b34 CY |
3067 | /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ |
3068 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) | |
c840d6ce MN |
3069 | return ((td_total_len - transferred) >> 10); |
3070 | ||
48df4a6f | 3071 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3072 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3073 | trb_buff_len == td_total_len) |
48df4a6f SS |
3074 | return 0; |
3075 | ||
0cbd4b34 CY |
3076 | /* for MTK xHCI, TD size doesn't include this TRB */ |
3077 | if (xhci->quirks & XHCI_MTK_HOST) | |
3078 | trb_buff_len = 0; | |
3079 | ||
734d3ddd | 3080 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3081 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3082 | ||
c840d6ce MN |
3083 | /* Queueing functions don't count the current TRB into transferred */ |
3084 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3085 | } |
3086 | ||
f9c589e1 | 3087 | |
474ed23a | 3088 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3089 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3090 | { |
f9c589e1 | 3091 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3092 | unsigned int unalign; |
3093 | unsigned int max_pkt; | |
f9c589e1 | 3094 | u32 new_buff_len; |
474ed23a | 3095 | |
734d3ddd | 3096 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3097 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3098 | ||
3099 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3100 | if (unalign == 0) | |
3101 | return 0; | |
3102 | ||
f9c589e1 MN |
3103 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3104 | unalign, *trb_buff_len); | |
3105 | ||
474ed23a MN |
3106 | /* is the last nornal TRB alignable by splitting it */ |
3107 | if (*trb_buff_len > unalign) { | |
3108 | *trb_buff_len -= unalign; | |
f9c589e1 | 3109 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3110 | return 0; |
3111 | } | |
f9c589e1 MN |
3112 | |
3113 | /* | |
3114 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3115 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3116 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3117 | */ | |
3118 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3119 | ||
3120 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3121 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3122 | ||
3123 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3124 | if (usb_urb_dir_out(urb)) { | |
3125 | sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, | |
3126 | seg->bounce_buf, new_buff_len, enqd_len); | |
3127 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3128 | max_pkt, DMA_TO_DEVICE); | |
3129 | } else { | |
3130 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3131 | max_pkt, DMA_FROM_DEVICE); | |
3132 | } | |
3133 | ||
3134 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3135 | /* try without aligning. Some host controllers survive */ | |
3136 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3137 | return 0; | |
3138 | } | |
3139 | *trb_buff_len = new_buff_len; | |
3140 | seg->bounce_len = new_buff_len; | |
3141 | seg->bounce_offs = enqd_len; | |
3142 | ||
3143 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3144 | ||
474ed23a MN |
3145 | return 1; |
3146 | } | |
3147 | ||
d2510342 AI |
3148 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3149 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3150 | struct urb *urb, int slot_id, unsigned int ep_index) |
3151 | { | |
5a5a0b1a | 3152 | struct xhci_ring *ring; |
8e51adcc | 3153 | struct urb_priv *urb_priv; |
8a96c052 | 3154 | struct xhci_td *td; |
d2510342 AI |
3155 | struct xhci_generic_trb *start_trb; |
3156 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3157 | bool more_trbs_coming = true; |
3158 | bool need_zero_pkt = false; | |
86065c27 MN |
3159 | bool first_trb = true; |
3160 | unsigned int num_trbs; | |
d2510342 | 3161 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3162 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3163 | int sent_len, ret; |
d2510342 | 3164 | u32 field, length_field, remainder; |
f9c589e1 | 3165 | u64 addr, send_addr; |
8a96c052 | 3166 | |
5a5a0b1a MN |
3167 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3168 | if (!ring) | |
e9df17eb SS |
3169 | return -EINVAL; |
3170 | ||
86065c27 | 3171 | full_len = urb->transfer_buffer_length; |
d2510342 AI |
3172 | /* If we have scatter/gather list, we use it. */ |
3173 | if (urb->num_sgs) { | |
3174 | num_sgs = urb->num_mapped_sgs; | |
3175 | sg = urb->sg; | |
86065c27 MN |
3176 | addr = (u64) sg_dma_address(sg); |
3177 | block_len = sg_dma_len(sg); | |
d2510342 | 3178 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3179 | } else { |
d2510342 | 3180 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3181 | addr = (u64) urb->transfer_dma; |
3182 | block_len = full_len; | |
3183 | } | |
4758dcd1 | 3184 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3185 | ep_index, urb->stream_id, |
3b72fca0 | 3186 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3187 | if (unlikely(ret < 0)) |
4758dcd1 | 3188 | return ret; |
8e51adcc AX |
3189 | |
3190 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3191 | |
3192 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
9ef7fbbb | 3193 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) |
5a83f04a | 3194 | need_zero_pkt = true; |
4758dcd1 | 3195 | |
7e64b037 | 3196 | td = &urb_priv->td[0]; |
8e51adcc | 3197 | |
8a96c052 SS |
3198 | /* |
3199 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3200 | * until we've finished creating all the other TRBs. The ring's cycle | |
3201 | * state may change as we enqueue the other TRBs, so save it too. | |
3202 | */ | |
5a5a0b1a MN |
3203 | start_trb = &ring->enqueue->generic; |
3204 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3205 | send_addr = addr; |
8a96c052 | 3206 | |
d2510342 | 3207 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3208 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3209 | enqd_len += trb_buff_len) { | |
d2510342 | 3210 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3211 | |
86065c27 MN |
3212 | /* TRB buffer should not cross 64KB boundaries */ |
3213 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3214 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3215 | |
86065c27 MN |
3216 | if (enqd_len + trb_buff_len > full_len) |
3217 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3218 | |
3219 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3220 | if (first_trb) { |
3221 | first_trb = false; | |
50f7b52a | 3222 | if (start_cycle == 0) |
d2510342 | 3223 | field |= TRB_CYCLE; |
50f7b52a | 3224 | } else |
5a5a0b1a | 3225 | field |= ring->cycle_state; |
b10de142 SS |
3226 | |
3227 | /* Chain all the TRBs together; clear the chain bit in the last | |
3228 | * TRB to indicate it's the last TRB in the chain. | |
3229 | */ | |
86065c27 | 3230 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3231 | field |= TRB_CHAIN; |
2d98ef40 | 3232 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3233 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3234 | &trb_buff_len, |
3235 | ring->enq_seg)) { | |
3236 | send_addr = ring->enq_seg->bounce_dma; | |
3237 | /* assuming TD won't span 2 segs */ | |
3238 | td->bounce_seg = ring->enq_seg; | |
3239 | } | |
474ed23a | 3240 | } |
f9c589e1 MN |
3241 | } |
3242 | if (enqd_len + trb_buff_len >= full_len) { | |
3243 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3244 | field |= TRB_IOC; |
124c3937 | 3245 | more_trbs_coming = false; |
5a83f04a | 3246 | td->last_trb = ring->enqueue; |
b10de142 | 3247 | } |
af8b9e63 SS |
3248 | |
3249 | /* Only set interrupt on short packet for IN endpoints */ | |
3250 | if (usb_urb_dir_in(urb)) | |
3251 | field |= TRB_ISP; | |
3252 | ||
4da6e6f2 | 3253 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3254 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3255 | full_len, urb, more_trbs_coming); | |
3256 | ||
f9dc68fe | 3257 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3258 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3259 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3260 | |
124c3937 | 3261 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3262 | lower_32_bits(send_addr), |
3263 | upper_32_bits(send_addr), | |
f9dc68fe | 3264 | length_field, |
d2510342 | 3265 | field); |
b10de142 | 3266 | |
b10de142 | 3267 | addr += trb_buff_len; |
f9c589e1 | 3268 | sent_len = trb_buff_len; |
d2510342 | 3269 | |
f9c589e1 | 3270 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3271 | /* New sg entry */ |
3272 | --num_sgs; | |
f9c589e1 | 3273 | sent_len -= block_len; |
86065c27 | 3274 | if (num_sgs != 0) { |
d2510342 | 3275 | sg = sg_next(sg); |
86065c27 MN |
3276 | block_len = sg_dma_len(sg); |
3277 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3278 | addr += sent_len; |
d2510342 AI |
3279 | } |
3280 | } | |
f9c589e1 MN |
3281 | block_len -= sent_len; |
3282 | send_addr = addr; | |
d2510342 | 3283 | } |
b10de142 | 3284 | |
5a83f04a MN |
3285 | if (need_zero_pkt) { |
3286 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3287 | ep_index, urb->stream_id, | |
3288 | 1, urb, 1, mem_flags); | |
7e64b037 | 3289 | urb_priv->td[1].last_trb = ring->enqueue; |
5a83f04a MN |
3290 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
3291 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
3292 | } | |
3293 | ||
86065c27 | 3294 | check_trb_math(urb, enqd_len); |
e9df17eb | 3295 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3296 | start_cycle, start_trb); |
b10de142 SS |
3297 | return 0; |
3298 | } | |
3299 | ||
d0e96f5a | 3300 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3301 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3302 | struct urb *urb, int slot_id, unsigned int ep_index) |
3303 | { | |
3304 | struct xhci_ring *ep_ring; | |
3305 | int num_trbs; | |
3306 | int ret; | |
3307 | struct usb_ctrlrequest *setup; | |
3308 | struct xhci_generic_trb *start_trb; | |
3309 | int start_cycle; | |
fb79a6da | 3310 | u32 field; |
8e51adcc | 3311 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3312 | struct xhci_td *td; |
3313 | ||
e9df17eb SS |
3314 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3315 | if (!ep_ring) | |
3316 | return -EINVAL; | |
d0e96f5a SS |
3317 | |
3318 | /* | |
3319 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3320 | * DMA address. | |
3321 | */ | |
3322 | if (!urb->setup_packet) | |
3323 | return -EINVAL; | |
3324 | ||
d0e96f5a SS |
3325 | /* 1 TRB for setup, 1 for status */ |
3326 | num_trbs = 2; | |
3327 | /* | |
3328 | * Don't need to check if we need additional event data and normal TRBs, | |
3329 | * since data in control transfers will never get bigger than 16MB | |
3330 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3331 | */ | |
3332 | if (urb->transfer_buffer_length > 0) | |
3333 | num_trbs++; | |
e9df17eb SS |
3334 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3335 | ep_index, urb->stream_id, | |
3b72fca0 | 3336 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3337 | if (ret < 0) |
3338 | return ret; | |
3339 | ||
8e51adcc | 3340 | urb_priv = urb->hcpriv; |
7e64b037 | 3341 | td = &urb_priv->td[0]; |
8e51adcc | 3342 | |
d0e96f5a SS |
3343 | /* |
3344 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3345 | * until we've finished creating all the other TRBs. The ring's cycle | |
3346 | * state may change as we enqueue the other TRBs, so save it too. | |
3347 | */ | |
3348 | start_trb = &ep_ring->enqueue->generic; | |
3349 | start_cycle = ep_ring->cycle_state; | |
3350 | ||
3351 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3352 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3353 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3354 | field = 0; |
3355 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3356 | if (start_cycle == 0) | |
3357 | field |= 0x1; | |
b83cdc8f | 3358 | |
dca77945 | 3359 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3360 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3361 | if (urb->transfer_buffer_length > 0) { |
3362 | if (setup->bRequestType & USB_DIR_IN) | |
3363 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3364 | else | |
3365 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3366 | } | |
3367 | } | |
3368 | ||
3b72fca0 | 3369 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3370 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3371 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3372 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3373 | /* Immediate data in pointer */ | |
3374 | field); | |
d0e96f5a SS |
3375 | |
3376 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3377 | /* Only set interrupt on short packet for IN endpoints */ |
3378 | if (usb_urb_dir_in(urb)) | |
3379 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3380 | else | |
3381 | field = TRB_TYPE(TRB_DATA); | |
3382 | ||
d0e96f5a | 3383 | if (urb->transfer_buffer_length > 0) { |
fb79a6da LB |
3384 | u32 length_field, remainder; |
3385 | ||
3386 | remainder = xhci_td_remainder(xhci, 0, | |
3387 | urb->transfer_buffer_length, | |
3388 | urb->transfer_buffer_length, | |
3389 | urb, 1); | |
3390 | length_field = TRB_LEN(urb->transfer_buffer_length) | | |
3391 | TRB_TD_SIZE(remainder) | | |
3392 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
3393 | if (setup->bRequestType & USB_DIR_IN) |
3394 | field |= TRB_DIR_IN; | |
3b72fca0 | 3395 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3396 | lower_32_bits(urb->transfer_dma), |
3397 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3398 | length_field, |
af8b9e63 | 3399 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3400 | } |
3401 | ||
3402 | /* Save the DMA address of the last TRB in the TD */ | |
3403 | td->last_trb = ep_ring->enqueue; | |
3404 | ||
3405 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3406 | /* If the device sent data, the status stage is an OUT transfer */ | |
3407 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3408 | field = 0; | |
3409 | else | |
3410 | field = TRB_DIR_IN; | |
3b72fca0 | 3411 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3412 | 0, |
3413 | 0, | |
3414 | TRB_INTR_TARGET(0), | |
3415 | /* Event on completion */ | |
3416 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3417 | ||
e9df17eb | 3418 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3419 | start_cycle, start_trb); |
d0e96f5a SS |
3420 | return 0; |
3421 | } | |
3422 | ||
5cd43e33 SS |
3423 | /* |
3424 | * The transfer burst count field of the isochronous TRB defines the number of | |
3425 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3426 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3427 | * This field is zero based, meaning a value of zero in the field means one | |
3428 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3429 | * zero. Only xHCI 1.0 host controllers support this field. | |
3430 | */ | |
3431 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3432 | struct urb *urb, unsigned int total_packet_count) |
3433 | { | |
3434 | unsigned int max_burst; | |
3435 | ||
09c352ed | 3436 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3437 | return 0; |
3438 | ||
3439 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3440 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3441 | } |
3442 | ||
b61d378f SS |
3443 | /* |
3444 | * Returns the number of packets in the last "burst" of packets. This field is | |
3445 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3446 | * the last burst packet count is equal to the total number of packets in the | |
3447 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3448 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3449 | * contain 1 to (bMaxBurst + 1) packets. | |
3450 | */ | |
3451 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3452 | struct urb *urb, unsigned int total_packet_count) |
3453 | { | |
3454 | unsigned int max_burst; | |
3455 | unsigned int residue; | |
3456 | ||
3457 | if (xhci->hci_version < 0x100) | |
3458 | return 0; | |
3459 | ||
09c352ed | 3460 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3461 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3462 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3463 | residue = total_packet_count % (max_burst + 1); | |
3464 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3465 | * number of packets, but the TLBPC field is zero-based. | |
3466 | */ | |
3467 | if (residue == 0) | |
3468 | return max_burst; | |
3469 | return residue - 1; | |
b61d378f | 3470 | } |
09c352ed MN |
3471 | if (total_packet_count == 0) |
3472 | return 0; | |
3473 | return total_packet_count - 1; | |
b61d378f SS |
3474 | } |
3475 | ||
79b8094f LB |
3476 | /* |
3477 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3478 | * target frame that the Interval associated with this Isochronous | |
3479 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3480 | * | |
3481 | * Returns actual frame id on success, negative value on error. | |
3482 | */ | |
3483 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3484 | struct urb *urb, int index) | |
3485 | { | |
3486 | int start_frame, ist, ret = 0; | |
3487 | int start_frame_id, end_frame_id, current_frame_id; | |
3488 | ||
3489 | if (urb->dev->speed == USB_SPEED_LOW || | |
3490 | urb->dev->speed == USB_SPEED_FULL) | |
3491 | start_frame = urb->start_frame + index * urb->interval; | |
3492 | else | |
3493 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3494 | ||
3495 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3496 | * | |
3497 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3498 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3499 | * be executed. | |
3500 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3501 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3502 | */ | |
3503 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3504 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3505 | ist <<= 3; | |
3506 | ||
3507 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3508 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3509 | * where: | |
3510 | * | |
3511 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3512 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3513 | * | |
3514 | * Both the End Frame ID and Start Frame ID values are calculated | |
3515 | * in microframes. When software determines the valid Frame ID value; | |
3516 | * The End Frame ID value should be rounded down to the nearest Frame | |
3517 | * boundary, and the Start Frame ID value should be rounded up to the | |
3518 | * nearest Frame boundary. | |
3519 | */ | |
3520 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3521 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3522 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3523 | ||
3524 | start_frame &= 0x7ff; | |
3525 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3526 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3527 | ||
3528 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3529 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3530 | start_frame_id, end_frame_id, start_frame); | |
3531 | ||
3532 | if (start_frame_id < end_frame_id) { | |
3533 | if (start_frame > end_frame_id || | |
3534 | start_frame < start_frame_id) | |
3535 | ret = -EINVAL; | |
3536 | } else if (start_frame_id > end_frame_id) { | |
3537 | if ((start_frame > end_frame_id && | |
3538 | start_frame < start_frame_id)) | |
3539 | ret = -EINVAL; | |
3540 | } else { | |
3541 | ret = -EINVAL; | |
3542 | } | |
3543 | ||
3544 | if (index == 0) { | |
3545 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3546 | start_frame = start_frame_id + 1; | |
3547 | if (urb->dev->speed == USB_SPEED_LOW || | |
3548 | urb->dev->speed == USB_SPEED_FULL) | |
3549 | urb->start_frame = start_frame; | |
3550 | else | |
3551 | urb->start_frame = start_frame << 3; | |
3552 | ret = 0; | |
3553 | } | |
3554 | } | |
3555 | ||
3556 | if (ret) { | |
3557 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
3558 | start_frame, current_frame_id, index, | |
3559 | start_frame_id, end_frame_id); | |
3560 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
3561 | return ret; | |
3562 | } | |
3563 | ||
3564 | return start_frame; | |
3565 | } | |
3566 | ||
04e51901 AX |
3567 | /* This is for isoc transfer */ |
3568 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3569 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3570 | { | |
3571 | struct xhci_ring *ep_ring; | |
3572 | struct urb_priv *urb_priv; | |
3573 | struct xhci_td *td; | |
3574 | int num_tds, trbs_per_td; | |
3575 | struct xhci_generic_trb *start_trb; | |
3576 | bool first_trb; | |
3577 | int start_cycle; | |
3578 | u32 field, length_field; | |
3579 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3580 | u64 start_addr, addr; | |
3581 | int i, j; | |
47cbf692 | 3582 | bool more_trbs_coming; |
79b8094f | 3583 | struct xhci_virt_ep *xep; |
09c352ed | 3584 | int frame_id; |
04e51901 | 3585 | |
79b8094f | 3586 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3587 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
3588 | ||
3589 | num_tds = urb->number_of_packets; | |
3590 | if (num_tds < 1) { | |
3591 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3592 | return -EINVAL; | |
3593 | } | |
04e51901 AX |
3594 | start_addr = (u64) urb->transfer_dma; |
3595 | start_trb = &ep_ring->enqueue->generic; | |
3596 | start_cycle = ep_ring->cycle_state; | |
3597 | ||
522989a2 | 3598 | urb_priv = urb->hcpriv; |
09c352ed | 3599 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 3600 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
3601 | unsigned int total_pkt_count, max_pkt; |
3602 | unsigned int burst_count, last_burst_pkt_count; | |
3603 | u32 sia_frame_id; | |
04e51901 | 3604 | |
4da6e6f2 | 3605 | first_trb = true; |
04e51901 AX |
3606 | running_total = 0; |
3607 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3608 | td_len = urb->iso_frame_desc[i].length; | |
3609 | td_remain_len = td_len; | |
734d3ddd | 3610 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
3611 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
3612 | ||
48df4a6f | 3613 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
3614 | if (total_pkt_count == 0) |
3615 | total_pkt_count++; | |
3616 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
3617 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
3618 | urb, total_pkt_count); | |
04e51901 | 3619 | |
d2510342 | 3620 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3621 | |
3622 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3623 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3624 | if (ret < 0) { |
3625 | if (i == 0) | |
3626 | return ret; | |
3627 | goto cleanup; | |
3628 | } | |
7e64b037 | 3629 | td = &urb_priv->td[i]; |
09c352ed MN |
3630 | |
3631 | /* use SIA as default, if frame id is used overwrite it */ | |
3632 | sia_frame_id = TRB_SIA; | |
3633 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
3634 | HCC_CFC(xhci->hcc_params)) { | |
3635 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
3636 | if (frame_id >= 0) | |
3637 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
3638 | } | |
3639 | /* | |
3640 | * Set isoc specific data for the first TRB in a TD. | |
3641 | * Prevent HW from getting the TRBs by keeping the cycle state | |
3642 | * inverted in the first TDs isoc TRB. | |
3643 | */ | |
2f6d3b65 | 3644 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
3645 | TRB_TLBPC(last_burst_pkt_count) | |
3646 | sia_frame_id | | |
3647 | (i ? ep_ring->cycle_state : !start_cycle); | |
3648 | ||
2f6d3b65 MN |
3649 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
3650 | if (!xep->use_extended_tbc) | |
3651 | field |= TRB_TBC(burst_count); | |
3652 | ||
09c352ed | 3653 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
3654 | for (j = 0; j < trbs_per_td; j++) { |
3655 | u32 remainder = 0; | |
09c352ed MN |
3656 | |
3657 | /* only first TRB is isoc, overwrite otherwise */ | |
3658 | if (!first_trb) | |
3659 | field = TRB_TYPE(TRB_NORMAL) | | |
3660 | ep_ring->cycle_state; | |
04e51901 | 3661 | |
af8b9e63 SS |
3662 | /* Only set interrupt on short packet for IN EPs */ |
3663 | if (usb_urb_dir_in(urb)) | |
3664 | field |= TRB_ISP; | |
3665 | ||
09c352ed | 3666 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 3667 | if (j < trbs_per_td - 1) { |
47cbf692 | 3668 | more_trbs_coming = true; |
09c352ed | 3669 | field |= TRB_CHAIN; |
04e51901 | 3670 | } else { |
09c352ed | 3671 | more_trbs_coming = false; |
04e51901 AX |
3672 | td->last_trb = ep_ring->enqueue; |
3673 | field |= TRB_IOC; | |
09c352ed MN |
3674 | /* set BEI, except for the last TD */ |
3675 | if (xhci->hci_version >= 0x100 && | |
3676 | !(xhci->quirks & XHCI_AVOID_BEI) && | |
3677 | i < num_tds - 1) | |
3678 | field |= TRB_BEI; | |
04e51901 | 3679 | } |
04e51901 | 3680 | /* Calculate TRB length */ |
d2510342 | 3681 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
3682 | if (trb_buff_len > td_remain_len) |
3683 | trb_buff_len = td_remain_len; | |
3684 | ||
4da6e6f2 | 3685 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
3686 | remainder = xhci_td_remainder(xhci, running_total, |
3687 | trb_buff_len, td_len, | |
124c3937 | 3688 | urb, more_trbs_coming); |
c840d6ce | 3689 | |
04e51901 | 3690 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 3691 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3692 | |
2f6d3b65 MN |
3693 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
3694 | if (first_trb && xep->use_extended_tbc) | |
3695 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
3696 | else | |
3697 | length_field |= TRB_TD_SIZE(remainder); | |
3698 | first_trb = false; | |
3699 | ||
3b72fca0 | 3700 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3701 | lower_32_bits(addr), |
3702 | upper_32_bits(addr), | |
3703 | length_field, | |
af8b9e63 | 3704 | field); |
04e51901 AX |
3705 | running_total += trb_buff_len; |
3706 | ||
3707 | addr += trb_buff_len; | |
3708 | td_remain_len -= trb_buff_len; | |
3709 | } | |
3710 | ||
3711 | /* Check TD length */ | |
3712 | if (running_total != td_len) { | |
3713 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3714 | ret = -EINVAL; |
3715 | goto cleanup; | |
04e51901 AX |
3716 | } |
3717 | } | |
3718 | ||
79b8094f LB |
3719 | /* store the next frame id */ |
3720 | if (HCC_CFC(xhci->hcc_params)) | |
3721 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
3722 | ||
c41136b0 AX |
3723 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3724 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3725 | usb_amd_quirk_pll_disable(); | |
3726 | } | |
3727 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3728 | ||
e1eab2e0 AX |
3729 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3730 | start_cycle, start_trb); | |
04e51901 | 3731 | return 0; |
522989a2 SS |
3732 | cleanup: |
3733 | /* Clean up a partially enqueued isoc transfer. */ | |
3734 | ||
3735 | for (i--; i >= 0; i--) | |
7e64b037 | 3736 | list_del_init(&urb_priv->td[i].td_list); |
522989a2 SS |
3737 | |
3738 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3739 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3740 | * won't accidentally start executing bogus TDs when we partially | |
3741 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3742 | */ | |
7e64b037 | 3743 | urb_priv->td[0].last_trb = ep_ring->enqueue; |
522989a2 | 3744 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
7e64b037 | 3745 | td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); |
522989a2 SS |
3746 | |
3747 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
7e64b037 MN |
3748 | ep_ring->enqueue = urb_priv->td[0].first_trb; |
3749 | ep_ring->enq_seg = urb_priv->td[0].start_seg; | |
522989a2 | 3750 | ep_ring->cycle_state = start_cycle; |
b008df60 | 3751 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3752 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3753 | return ret; | |
04e51901 AX |
3754 | } |
3755 | ||
3756 | /* | |
3757 | * Check transfer ring to guarantee there is enough room for the urb. | |
3758 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
3759 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
3760 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
3761 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
3762 | */ |
3763 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3764 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3765 | { | |
3766 | struct xhci_virt_device *xdev; | |
3767 | struct xhci_ring *ep_ring; | |
3768 | struct xhci_ep_ctx *ep_ctx; | |
3769 | int start_frame; | |
04e51901 AX |
3770 | int num_tds, num_trbs, i; |
3771 | int ret; | |
79b8094f LB |
3772 | struct xhci_virt_ep *xep; |
3773 | int ist; | |
04e51901 AX |
3774 | |
3775 | xdev = xhci->devs[slot_id]; | |
79b8094f | 3776 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3777 | ep_ring = xdev->eps[ep_index].ring; |
3778 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3779 | ||
3780 | num_trbs = 0; | |
3781 | num_tds = urb->number_of_packets; | |
3782 | for (i = 0; i < num_tds; i++) | |
d2510342 | 3783 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3784 | |
3785 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3786 | * Do not insert any td of the urb to the ring if the check failed. | |
3787 | */ | |
5071e6b2 | 3788 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3789 | num_trbs, mem_flags); |
04e51901 AX |
3790 | if (ret) |
3791 | return ret; | |
3792 | ||
79b8094f LB |
3793 | /* |
3794 | * Check interval value. This should be done before we start to | |
3795 | * calculate the start frame value. | |
3796 | */ | |
78140156 | 3797 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
3798 | |
3799 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 3800 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 3801 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
3802 | urb->start_frame = xep->next_frame_id; |
3803 | goto skip_start_over; | |
3804 | } | |
79b8094f LB |
3805 | } |
3806 | ||
3807 | start_frame = readl(&xhci->run_regs->microframe_index); | |
3808 | start_frame &= 0x3fff; | |
3809 | /* | |
3810 | * Round up to the next frame and consider the time before trb really | |
3811 | * gets scheduled by hardare. | |
3812 | */ | |
3813 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3814 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3815 | ist <<= 3; | |
3816 | start_frame += ist + XHCI_CFC_DELAY; | |
3817 | start_frame = roundup(start_frame, 8); | |
3818 | ||
3819 | /* | |
3820 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
3821 | * is greate than 8 microframes. | |
3822 | */ | |
3823 | if (urb->dev->speed == USB_SPEED_LOW || | |
3824 | urb->dev->speed == USB_SPEED_FULL) { | |
3825 | start_frame = roundup(start_frame, urb->interval << 3); | |
3826 | urb->start_frame = start_frame >> 3; | |
3827 | } else { | |
3828 | start_frame = roundup(start_frame, urb->interval); | |
3829 | urb->start_frame = start_frame; | |
3830 | } | |
3831 | ||
3832 | skip_start_over: | |
b008df60 AX |
3833 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3834 | ||
3fc8206d | 3835 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3836 | } |
3837 | ||
d0e96f5a SS |
3838 | /**** Command Ring Operations ****/ |
3839 | ||
913a8a34 SS |
3840 | /* Generic function for queueing a command TRB on the command ring. |
3841 | * Check to make sure there's room on the command ring for one command TRB. | |
3842 | * Also check that there's room reserved for commands that must not fail. | |
3843 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3844 | * then only check for the number of reserved spots. | |
3845 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3846 | * because the command event handler may want to resubmit a failed command. | |
3847 | */ | |
ddba5cd0 MN |
3848 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3849 | u32 field1, u32 field2, | |
3850 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3851 | { |
913a8a34 | 3852 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3853 | int ret; |
ad6b1d91 | 3854 | |
98d74f9c MN |
3855 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
3856 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 3857 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 3858 | return -ESHUTDOWN; |
ad6b1d91 | 3859 | } |
d1dc908a | 3860 | |
913a8a34 SS |
3861 | if (!command_must_succeed) |
3862 | reserved_trbs++; | |
3863 | ||
d1dc908a | 3864 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3865 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3866 | if (ret < 0) { |
3867 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3868 | if (command_must_succeed) |
3869 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3870 | "unfailable commands failed.\n"); | |
d1dc908a | 3871 | return ret; |
7f84eef0 | 3872 | } |
c9aa1a2d MN |
3873 | |
3874 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
ddba5cd0 | 3875 | |
c311e391 | 3876 | /* if there are no other commands queued we start the timeout timer */ |
daa47f21 | 3877 | if (list_empty(&xhci->cmd_list)) { |
c311e391 | 3878 | xhci->current_cmd = cmd; |
cb4d5ce5 | 3879 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
3880 | } |
3881 | ||
daa47f21 LB |
3882 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
3883 | ||
3b72fca0 AX |
3884 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3885 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3886 | return 0; |
3887 | } | |
3888 | ||
3ffbba95 | 3889 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3890 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3891 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3892 | { |
ddba5cd0 | 3893 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3894 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3895 | } |
3896 | ||
3897 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3898 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3899 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3900 | { |
ddba5cd0 | 3901 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3902 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3903 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3904 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3905 | } |
3906 | ||
ddba5cd0 | 3907 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3908 | u32 field1, u32 field2, u32 field3, u32 field4) |
3909 | { | |
ddba5cd0 | 3910 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3911 | } |
3912 | ||
2a8f82c4 | 3913 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3914 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3915 | u32 slot_id) | |
2a8f82c4 | 3916 | { |
ddba5cd0 | 3917 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3918 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3919 | false); |
3ffbba95 | 3920 | } |
f94e0186 SS |
3921 | |
3922 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3923 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3924 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3925 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3926 | { |
ddba5cd0 | 3927 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3928 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3929 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3930 | command_must_succeed); | |
f94e0186 | 3931 | } |
ae636747 | 3932 | |
f2217e8e | 3933 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3934 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3935 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3936 | { |
ddba5cd0 | 3937 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3938 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3939 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3940 | command_must_succeed); |
f2217e8e SS |
3941 | } |
3942 | ||
be88fe4f AX |
3943 | /* |
3944 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3945 | * activity on an endpoint that is about to be suspended. | |
3946 | */ | |
ddba5cd0 MN |
3947 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3948 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3949 | { |
3950 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3951 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3952 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3953 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3954 | |
ddba5cd0 | 3955 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 3956 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3957 | } |
3958 | ||
d3a43e66 HG |
3959 | /* Set Transfer Ring Dequeue Pointer command */ |
3960 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
3961 | unsigned int slot_id, unsigned int ep_index, | |
3962 | unsigned int stream_id, | |
3963 | struct xhci_dequeue_state *deq_state) | |
ae636747 SS |
3964 | { |
3965 | dma_addr_t addr; | |
3966 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3967 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3968 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 3969 | u32 trb_sct = 0; |
ae636747 | 3970 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3971 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
3972 | struct xhci_command *cmd; |
3973 | int ret; | |
ae636747 | 3974 | |
d3a43e66 HG |
3975 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
3976 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
3977 | deq_state->new_deq_seg, | |
3978 | (unsigned long long)deq_state->new_deq_seg->dma, | |
3979 | deq_state->new_deq_ptr, | |
3980 | (unsigned long long)xhci_trb_virt_to_dma( | |
3981 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
3982 | deq_state->new_cycle_state); | |
3983 | ||
3984 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
3985 | deq_state->new_deq_ptr); | |
c92bcfa7 | 3986 | if (addr == 0) { |
ae636747 | 3987 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 3988 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
3989 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
3990 | return; | |
c92bcfa7 | 3991 | } |
bf161e85 SS |
3992 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
3993 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
3994 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
3995 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 3996 | return; |
bf161e85 | 3997 | } |
1e3452e3 HG |
3998 | |
3999 | /* This function gets called from contexts where it cannot sleep */ | |
4000 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
74e0b564 | 4001 | if (!cmd) |
d3a43e66 | 4002 | return; |
1e3452e3 | 4003 | |
d3a43e66 HG |
4004 | ep->queued_deq_seg = deq_state->new_deq_seg; |
4005 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
95241dbd HG |
4006 | if (stream_id) |
4007 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
1e3452e3 | 4008 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
4009 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
4010 | upper_32_bits(addr), trb_stream_id, | |
4011 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
4012 | if (ret < 0) { |
4013 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 4014 | return; |
1e3452e3 HG |
4015 | } |
4016 | ||
d3a43e66 HG |
4017 | /* Stop the TD queueing code from ringing the doorbell until |
4018 | * this command completes. The HC won't set the dequeue pointer | |
4019 | * if the ring is running, and ringing the doorbell starts the | |
4020 | * ring running. | |
4021 | */ | |
4022 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 4023 | } |
a1587d97 | 4024 | |
ddba5cd0 MN |
4025 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4026 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
4027 | { |
4028 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4029 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4030 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4031 | ||
ddba5cd0 MN |
4032 | return queue_command(xhci, cmd, 0, 0, 0, |
4033 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4034 | } |