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Commit | Line | Data |
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a1428969 TA |
1 | /* |
2 | * Mentor USB OTG Core host controller driver. | |
3 | * | |
4 | * Copyright (c) 2008 Texas Instruments | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
a1428969 TA |
7 | * |
8 | * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
c60795f4 | 12 | #include <usb.h> |
a1428969 TA |
13 | #include "musb_hcd.h" |
14 | ||
15 | /* MSC control transfers */ | |
16 | #define USB_MSC_BBB_RESET 0xFF | |
17 | #define USB_MSC_BBB_GET_MAX_LUN 0xFE | |
18 | ||
19 | /* Endpoint configuration information */ | |
0228348e | 20 | static const struct musb_epinfo epinfo[3] = { |
a1428969 TA |
21 | {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ |
22 | {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ | |
23 | {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ | |
24 | }; | |
25 | ||
321790f6 BW |
26 | /* --- Virtual Root Hub ---------------------------------------------------- */ |
27 | #ifdef MUSB_NO_MULTIPOINT | |
28 | static int rh_devnum; | |
29 | static u32 port_status; | |
30 | ||
eb838e7d | 31 | #include <usbroothubdes.h> |
321790f6 | 32 | |
321790f6 BW |
33 | #endif |
34 | ||
a1428969 TA |
35 | /* |
36 | * This function writes the data toggle value. | |
37 | */ | |
38 | static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) | |
39 | { | |
40 | u16 toggle = usb_gettoggle(dev, ep, dir_out); | |
41 | u16 csr; | |
42 | ||
43 | if (dir_out) { | |
4ee691f6 BW |
44 | csr = readw(&musbr->txcsr); |
45 | if (!toggle) { | |
46 | if (csr & MUSB_TXCSR_MODE) | |
47 | csr = MUSB_TXCSR_CLRDATATOG; | |
48 | else | |
49 | csr = 0; | |
50 | writew(csr, &musbr->txcsr); | |
51 | } else { | |
a1428969 TA |
52 | csr |= MUSB_TXCSR_H_WR_DATATOGGLE; |
53 | writew(csr, &musbr->txcsr); | |
54 | csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); | |
55 | writew(csr, &musbr->txcsr); | |
56 | } | |
57 | } else { | |
4ee691f6 BW |
58 | if (!toggle) { |
59 | csr = readw(&musbr->txcsr); | |
60 | if (csr & MUSB_TXCSR_MODE) | |
61 | csr = MUSB_RXCSR_CLRDATATOG; | |
62 | else | |
63 | csr = 0; | |
64 | writew(csr, &musbr->rxcsr); | |
65 | } else { | |
a1428969 TA |
66 | csr = readw(&musbr->rxcsr); |
67 | csr |= MUSB_RXCSR_H_WR_DATATOGGLE; | |
68 | writew(csr, &musbr->rxcsr); | |
69 | csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); | |
70 | writew(csr, &musbr->rxcsr); | |
71 | } | |
72 | } | |
73 | } | |
74 | ||
75 | /* | |
eae4b2b6 VC |
76 | * This function checks if RxStall has occurred on the endpoint. If a RxStall |
77 | * has occurred, the RxStall is cleared and 1 is returned. If RxStall has | |
78 | * not occurred, 0 is returned. | |
a1428969 TA |
79 | */ |
80 | static u8 check_stall(u8 ep, u8 dir_out) | |
81 | { | |
82 | u16 csr; | |
83 | ||
84 | /* For endpoint 0 */ | |
85 | if (!ep) { | |
86 | csr = readw(&musbr->txcsr); | |
87 | if (csr & MUSB_CSR0_H_RXSTALL) { | |
88 | csr &= ~MUSB_CSR0_H_RXSTALL; | |
89 | writew(csr, &musbr->txcsr); | |
90 | return 1; | |
91 | } | |
92 | } else { /* For non-ep0 */ | |
93 | if (dir_out) { /* is it tx ep */ | |
94 | csr = readw(&musbr->txcsr); | |
95 | if (csr & MUSB_TXCSR_H_RXSTALL) { | |
96 | csr &= ~MUSB_TXCSR_H_RXSTALL; | |
97 | writew(csr, &musbr->txcsr); | |
98 | return 1; | |
99 | } | |
100 | } else { /* is it rx ep */ | |
101 | csr = readw(&musbr->rxcsr); | |
102 | if (csr & MUSB_RXCSR_H_RXSTALL) { | |
103 | csr &= ~MUSB_RXCSR_H_RXSTALL; | |
104 | writew(csr, &musbr->rxcsr); | |
105 | return 1; | |
106 | } | |
107 | } | |
108 | } | |
109 | return 0; | |
110 | } | |
111 | ||
112 | /* | |
113 | * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout | |
114 | * error and -2 for stall. | |
115 | */ | |
116 | static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) | |
117 | { | |
118 | u16 csr; | |
119 | int result = 1; | |
95de1e2f | 120 | int timeout = CONFIG_USB_MUSB_TIMEOUT; |
a1428969 TA |
121 | |
122 | while (result > 0) { | |
123 | csr = readw(&musbr->txcsr); | |
124 | if (csr & MUSB_CSR0_H_ERROR) { | |
125 | csr &= ~MUSB_CSR0_H_ERROR; | |
126 | writew(csr, &musbr->txcsr); | |
127 | dev->status = USB_ST_CRC_ERR; | |
128 | result = -1; | |
129 | break; | |
130 | } | |
131 | ||
132 | switch (bit_mask) { | |
133 | case MUSB_CSR0_TXPKTRDY: | |
134 | if (!(csr & MUSB_CSR0_TXPKTRDY)) { | |
135 | if (check_stall(MUSB_CONTROL_EP, 0)) { | |
136 | dev->status = USB_ST_STALLED; | |
137 | result = -2; | |
138 | } else | |
139 | result = 0; | |
140 | } | |
141 | break; | |
142 | ||
143 | case MUSB_CSR0_RXPKTRDY: | |
144 | if (check_stall(MUSB_CONTROL_EP, 0)) { | |
145 | dev->status = USB_ST_STALLED; | |
146 | result = -2; | |
147 | } else | |
148 | if (csr & MUSB_CSR0_RXPKTRDY) | |
149 | result = 0; | |
150 | break; | |
151 | ||
152 | case MUSB_CSR0_H_REQPKT: | |
153 | if (!(csr & MUSB_CSR0_H_REQPKT)) { | |
154 | if (check_stall(MUSB_CONTROL_EP, 0)) { | |
155 | dev->status = USB_ST_STALLED; | |
156 | result = -2; | |
157 | } else | |
158 | result = 0; | |
159 | } | |
160 | break; | |
161 | } | |
c3a012ce BW |
162 | |
163 | /* Check the timeout */ | |
164 | if (--timeout) | |
165 | udelay(1); | |
166 | else { | |
167 | dev->status = USB_ST_CRC_ERR; | |
168 | result = -1; | |
169 | break; | |
170 | } | |
a1428969 | 171 | } |
c3a012ce | 172 | |
a1428969 TA |
173 | return result; |
174 | } | |
175 | ||
176 | /* | |
177 | * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. | |
178 | */ | |
ddd025bb | 179 | static int wait_until_txep_ready(struct usb_device *dev, u8 ep) |
a1428969 TA |
180 | { |
181 | u16 csr; | |
95de1e2f | 182 | int timeout = CONFIG_USB_MUSB_TIMEOUT; |
a1428969 TA |
183 | |
184 | do { | |
185 | if (check_stall(ep, 1)) { | |
186 | dev->status = USB_ST_STALLED; | |
187 | return 0; | |
188 | } | |
189 | ||
190 | csr = readw(&musbr->txcsr); | |
191 | if (csr & MUSB_TXCSR_H_ERROR) { | |
192 | dev->status = USB_ST_CRC_ERR; | |
193 | return 0; | |
194 | } | |
c3a012ce BW |
195 | |
196 | /* Check the timeout */ | |
197 | if (--timeout) | |
198 | udelay(1); | |
199 | else { | |
200 | dev->status = USB_ST_CRC_ERR; | |
201 | return -1; | |
202 | } | |
203 | ||
a1428969 TA |
204 | } while (csr & MUSB_TXCSR_TXPKTRDY); |
205 | return 1; | |
206 | } | |
207 | ||
208 | /* | |
209 | * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. | |
210 | */ | |
ddd025bb | 211 | static int wait_until_rxep_ready(struct usb_device *dev, u8 ep) |
a1428969 TA |
212 | { |
213 | u16 csr; | |
95de1e2f | 214 | int timeout = CONFIG_USB_MUSB_TIMEOUT; |
a1428969 TA |
215 | |
216 | do { | |
217 | if (check_stall(ep, 0)) { | |
218 | dev->status = USB_ST_STALLED; | |
219 | return 0; | |
220 | } | |
221 | ||
222 | csr = readw(&musbr->rxcsr); | |
223 | if (csr & MUSB_RXCSR_H_ERROR) { | |
224 | dev->status = USB_ST_CRC_ERR; | |
225 | return 0; | |
226 | } | |
c3a012ce BW |
227 | |
228 | /* Check the timeout */ | |
229 | if (--timeout) | |
230 | udelay(1); | |
231 | else { | |
232 | dev->status = USB_ST_CRC_ERR; | |
233 | return -1; | |
234 | } | |
235 | ||
a1428969 TA |
236 | } while (!(csr & MUSB_RXCSR_RXPKTRDY)); |
237 | return 1; | |
238 | } | |
239 | ||
240 | /* | |
241 | * This function performs the setup phase of the control transfer | |
242 | */ | |
243 | static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) | |
244 | { | |
245 | int result; | |
246 | u16 csr; | |
247 | ||
248 | /* write the control request to ep0 fifo */ | |
249 | write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); | |
250 | ||
251 | /* enable transfer of setup packet */ | |
252 | csr = readw(&musbr->txcsr); | |
253 | csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); | |
254 | writew(csr, &musbr->txcsr); | |
255 | ||
256 | /* wait until the setup packet is transmitted */ | |
257 | result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); | |
258 | dev->act_len = 0; | |
259 | return result; | |
260 | } | |
261 | ||
262 | /* | |
263 | * This function handles the control transfer in data phase | |
264 | */ | |
265 | static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) | |
266 | { | |
267 | u16 csr; | |
268 | u32 rxlen = 0; | |
269 | u32 nextlen = 0; | |
270 | u8 maxpktsize = (1 << dev->maxpacketsize) * 8; | |
271 | u8 *rxbuff = (u8 *)buffer; | |
272 | u8 rxedlength; | |
273 | int result; | |
274 | ||
275 | while (rxlen < len) { | |
276 | /* Determine the next read length */ | |
277 | nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); | |
278 | ||
279 | /* Set the ReqPkt bit */ | |
280 | csr = readw(&musbr->txcsr); | |
281 | writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); | |
282 | result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); | |
283 | if (result < 0) | |
284 | return result; | |
285 | ||
286 | /* Actual number of bytes received by usb */ | |
287 | rxedlength = readb(&musbr->rxcount); | |
288 | ||
289 | /* Read the data from the RxFIFO */ | |
290 | read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); | |
291 | ||
292 | /* Clear the RxPktRdy Bit */ | |
293 | csr = readw(&musbr->txcsr); | |
294 | csr &= ~MUSB_CSR0_RXPKTRDY; | |
295 | writew(csr, &musbr->txcsr); | |
296 | ||
297 | /* short packet? */ | |
298 | if (rxedlength != nextlen) { | |
299 | dev->act_len += rxedlength; | |
300 | break; | |
301 | } | |
302 | rxlen += nextlen; | |
303 | dev->act_len = rxlen; | |
304 | } | |
305 | return 0; | |
306 | } | |
307 | ||
308 | /* | |
309 | * This function handles the control transfer out data phase | |
310 | */ | |
311 | static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) | |
312 | { | |
313 | u16 csr; | |
314 | u32 txlen = 0; | |
315 | u32 nextlen = 0; | |
316 | u8 maxpktsize = (1 << dev->maxpacketsize) * 8; | |
317 | u8 *txbuff = (u8 *)buffer; | |
318 | int result = 0; | |
319 | ||
320 | while (txlen < len) { | |
321 | /* Determine the next write length */ | |
322 | nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); | |
323 | ||
324 | /* Load the data to send in FIFO */ | |
325 | write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); | |
326 | ||
327 | /* Set TXPKTRDY bit */ | |
328 | csr = readw(&musbr->txcsr); | |
99b4eaa6 AM |
329 | |
330 | csr |= MUSB_CSR0_TXPKTRDY; | |
331 | #if !defined(CONFIG_SOC_DM365) | |
332 | csr |= MUSB_CSR0_H_DIS_PING; | |
333 | #endif | |
334 | writew(csr, &musbr->txcsr); | |
a1428969 TA |
335 | result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); |
336 | if (result < 0) | |
337 | break; | |
338 | ||
339 | txlen += nextlen; | |
340 | dev->act_len = txlen; | |
341 | } | |
342 | return result; | |
343 | } | |
344 | ||
345 | /* | |
346 | * This function handles the control transfer out status phase | |
347 | */ | |
348 | static int ctrlreq_out_status_phase(struct usb_device *dev) | |
349 | { | |
350 | u16 csr; | |
351 | int result; | |
352 | ||
353 | /* Set the StatusPkt bit */ | |
354 | csr = readw(&musbr->txcsr); | |
99b4eaa6 AM |
355 | csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); |
356 | #if !defined(CONFIG_SOC_DM365) | |
357 | csr |= MUSB_CSR0_H_DIS_PING; | |
358 | #endif | |
a1428969 TA |
359 | writew(csr, &musbr->txcsr); |
360 | ||
361 | /* Wait until TXPKTRDY bit is cleared */ | |
362 | result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); | |
363 | return result; | |
364 | } | |
365 | ||
366 | /* | |
367 | * This function handles the control transfer in status phase | |
368 | */ | |
369 | static int ctrlreq_in_status_phase(struct usb_device *dev) | |
370 | { | |
371 | u16 csr; | |
372 | int result; | |
373 | ||
374 | /* Set the StatusPkt bit and ReqPkt bit */ | |
99b4eaa6 AM |
375 | csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; |
376 | #if !defined(CONFIG_SOC_DM365) | |
377 | csr |= MUSB_CSR0_H_DIS_PING; | |
378 | #endif | |
a1428969 TA |
379 | writew(csr, &musbr->txcsr); |
380 | result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); | |
381 | ||
382 | /* clear StatusPkt bit and RxPktRdy bit */ | |
383 | csr = readw(&musbr->txcsr); | |
384 | csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); | |
385 | writew(csr, &musbr->txcsr); | |
386 | return result; | |
387 | } | |
388 | ||
389 | /* | |
390 | * determines the speed of the device (High/Full/Slow) | |
391 | */ | |
392 | static u8 get_dev_speed(struct usb_device *dev) | |
393 | { | |
c60795f4 IY |
394 | return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : |
395 | ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : | |
a1428969 TA |
396 | MUSB_TYPE_SPEED_FULL); |
397 | } | |
398 | ||
399 | /* | |
400 | * configure the hub address and the port address. | |
401 | */ | |
402 | static void config_hub_port(struct usb_device *dev, u8 ep) | |
403 | { | |
404 | u8 chid; | |
405 | u8 hub; | |
406 | ||
407 | /* Find out the nearest parent which is high speed */ | |
408 | while (dev->parent->parent != NULL) | |
409 | if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) | |
410 | dev = dev->parent; | |
411 | else | |
412 | break; | |
413 | ||
414 | /* determine the port address at that hub */ | |
415 | hub = dev->parent->devnum; | |
416 | for (chid = 0; chid < USB_MAXCHILDREN; chid++) | |
417 | if (dev->parent->children[chid] == dev) | |
418 | break; | |
419 | ||
8868fd44 | 420 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
421 | /* configure the hub address and the port address */ |
422 | writeb(hub, &musbr->tar[ep].txhubaddr); | |
423 | writeb((chid + 1), &musbr->tar[ep].txhubport); | |
424 | writeb(hub, &musbr->tar[ep].rxhubaddr); | |
425 | writeb((chid + 1), &musbr->tar[ep].rxhubport); | |
8868fd44 | 426 | #endif |
a1428969 TA |
427 | } |
428 | ||
321790f6 BW |
429 | #ifdef MUSB_NO_MULTIPOINT |
430 | ||
431 | static void musb_port_reset(int do_reset) | |
432 | { | |
433 | u8 power = readb(&musbr->power); | |
434 | ||
435 | if (do_reset) { | |
436 | power &= 0xf0; | |
437 | writeb(power | MUSB_POWER_RESET, &musbr->power); | |
438 | port_status |= USB_PORT_STAT_RESET; | |
439 | port_status &= ~USB_PORT_STAT_ENABLE; | |
440 | udelay(30000); | |
441 | } else { | |
442 | writeb(power & ~MUSB_POWER_RESET, &musbr->power); | |
443 | ||
444 | power = readb(&musbr->power); | |
445 | if (power & MUSB_POWER_HSMODE) | |
446 | port_status |= USB_PORT_STAT_HIGH_SPEED; | |
447 | ||
448 | port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16)); | |
449 | port_status |= USB_PORT_STAT_ENABLE | |
450 | | (USB_PORT_STAT_C_RESET << 16) | |
451 | | (USB_PORT_STAT_C_ENABLE << 16); | |
452 | } | |
453 | } | |
454 | ||
455 | /* | |
456 | * root hub control | |
457 | */ | |
458 | static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe, | |
459 | void *buffer, int transfer_len, | |
460 | struct devrequest *cmd) | |
461 | { | |
462 | int leni = transfer_len; | |
463 | int len = 0; | |
464 | int stat = 0; | |
465 | u32 datab[4]; | |
0228348e | 466 | const u8 *data_buf = (u8 *) datab; |
321790f6 BW |
467 | u16 bmRType_bReq; |
468 | u16 wValue; | |
469 | u16 wIndex; | |
470 | u16 wLength; | |
471 | u16 int_usb; | |
472 | ||
473 | if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { | |
474 | debug("Root-Hub submit IRQ: NOT implemented\n"); | |
475 | return 0; | |
476 | } | |
477 | ||
478 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
479 | wValue = swap_16(cmd->value); | |
480 | wIndex = swap_16(cmd->index); | |
481 | wLength = swap_16(cmd->length); | |
482 | ||
483 | debug("--- HUB ----------------------------------------\n"); | |
484 | debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n", | |
485 | bmRType_bReq, wValue, wIndex, wLength); | |
486 | debug("------------------------------------------------\n"); | |
487 | ||
488 | switch (bmRType_bReq) { | |
489 | case RH_GET_STATUS: | |
490 | debug("RH_GET_STATUS\n"); | |
491 | ||
492 | *(__u16 *) data_buf = swap_16(1); | |
493 | len = 2; | |
494 | break; | |
495 | ||
496 | case RH_GET_STATUS | RH_INTERFACE: | |
497 | debug("RH_GET_STATUS | RH_INTERFACE\n"); | |
498 | ||
499 | *(__u16 *) data_buf = swap_16(0); | |
500 | len = 2; | |
501 | break; | |
502 | ||
503 | case RH_GET_STATUS | RH_ENDPOINT: | |
504 | debug("RH_GET_STATUS | RH_ENDPOINT\n"); | |
505 | ||
506 | *(__u16 *) data_buf = swap_16(0); | |
507 | len = 2; | |
508 | break; | |
509 | ||
510 | case RH_GET_STATUS | RH_CLASS: | |
511 | debug("RH_GET_STATUS | RH_CLASS\n"); | |
512 | ||
513 | *(__u32 *) data_buf = swap_32(0); | |
514 | len = 4; | |
515 | break; | |
516 | ||
517 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: | |
518 | debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n"); | |
519 | ||
520 | int_usb = readw(&musbr->intrusb); | |
521 | if (int_usb & MUSB_INTR_CONNECT) { | |
522 | port_status |= USB_PORT_STAT_CONNECTION | |
523 | | (USB_PORT_STAT_C_CONNECTION << 16); | |
524 | port_status |= USB_PORT_STAT_HIGH_SPEED | |
525 | | USB_PORT_STAT_ENABLE; | |
526 | } | |
527 | ||
528 | if (port_status & USB_PORT_STAT_RESET) | |
529 | musb_port_reset(0); | |
530 | ||
531 | *(__u32 *) data_buf = swap_32(port_status); | |
532 | len = 4; | |
533 | break; | |
534 | ||
535 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
536 | debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n"); | |
537 | ||
538 | switch (wValue) { | |
539 | case RH_ENDPOINT_STALL: | |
540 | debug("C_HUB_ENDPOINT_STALL\n"); | |
541 | len = 0; | |
542 | break; | |
543 | } | |
544 | port_status &= ~(1 << wValue); | |
545 | break; | |
546 | ||
547 | case RH_CLEAR_FEATURE | RH_CLASS: | |
548 | debug("RH_CLEAR_FEATURE | RH_CLASS\n"); | |
549 | ||
550 | switch (wValue) { | |
551 | case RH_C_HUB_LOCAL_POWER: | |
552 | debug("C_HUB_LOCAL_POWER\n"); | |
553 | len = 0; | |
554 | break; | |
555 | ||
556 | case RH_C_HUB_OVER_CURRENT: | |
557 | debug("C_HUB_OVER_CURRENT\n"); | |
558 | len = 0; | |
559 | break; | |
560 | } | |
561 | port_status &= ~(1 << wValue); | |
562 | break; | |
563 | ||
564 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
565 | debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n"); | |
566 | ||
567 | switch (wValue) { | |
568 | case RH_PORT_ENABLE: | |
569 | len = 0; | |
570 | break; | |
571 | ||
572 | case RH_PORT_SUSPEND: | |
573 | len = 0; | |
574 | break; | |
575 | ||
576 | case RH_PORT_POWER: | |
577 | len = 0; | |
578 | break; | |
579 | ||
580 | case RH_C_PORT_CONNECTION: | |
581 | len = 0; | |
582 | break; | |
583 | ||
584 | case RH_C_PORT_ENABLE: | |
585 | len = 0; | |
586 | break; | |
587 | ||
588 | case RH_C_PORT_SUSPEND: | |
589 | len = 0; | |
590 | break; | |
591 | ||
592 | case RH_C_PORT_OVER_CURRENT: | |
593 | len = 0; | |
594 | break; | |
595 | ||
596 | case RH_C_PORT_RESET: | |
597 | len = 0; | |
598 | break; | |
599 | ||
600 | default: | |
601 | debug("invalid wValue\n"); | |
602 | stat = USB_ST_STALLED; | |
603 | } | |
604 | ||
605 | port_status &= ~(1 << wValue); | |
606 | break; | |
607 | ||
608 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
609 | debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n"); | |
610 | ||
611 | switch (wValue) { | |
612 | case RH_PORT_SUSPEND: | |
613 | len = 0; | |
614 | break; | |
615 | ||
616 | case RH_PORT_RESET: | |
617 | musb_port_reset(1); | |
618 | len = 0; | |
619 | break; | |
620 | ||
621 | case RH_PORT_POWER: | |
622 | len = 0; | |
623 | break; | |
624 | ||
625 | case RH_PORT_ENABLE: | |
626 | len = 0; | |
627 | break; | |
628 | ||
629 | default: | |
630 | debug("invalid wValue\n"); | |
631 | stat = USB_ST_STALLED; | |
632 | } | |
633 | ||
634 | port_status |= 1 << wValue; | |
635 | break; | |
636 | ||
637 | case RH_SET_ADDRESS: | |
638 | debug("RH_SET_ADDRESS\n"); | |
639 | ||
640 | rh_devnum = wValue; | |
641 | len = 0; | |
642 | break; | |
643 | ||
644 | case RH_GET_DESCRIPTOR: | |
645 | debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength); | |
646 | ||
647 | switch (wValue) { | |
648 | case (USB_DT_DEVICE << 8): /* device descriptor */ | |
649 | len = min_t(unsigned int, | |
650 | leni, min_t(unsigned int, | |
651 | sizeof(root_hub_dev_des), | |
652 | wLength)); | |
653 | data_buf = root_hub_dev_des; | |
654 | break; | |
655 | ||
656 | case (USB_DT_CONFIG << 8): /* configuration descriptor */ | |
657 | len = min_t(unsigned int, | |
658 | leni, min_t(unsigned int, | |
659 | sizeof(root_hub_config_des), | |
660 | wLength)); | |
661 | data_buf = root_hub_config_des; | |
662 | break; | |
663 | ||
664 | case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */ | |
665 | len = min_t(unsigned int, | |
666 | leni, min_t(unsigned int, | |
667 | sizeof(root_hub_str_index0), | |
668 | wLength)); | |
669 | data_buf = root_hub_str_index0; | |
670 | break; | |
671 | ||
672 | case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */ | |
673 | len = min_t(unsigned int, | |
674 | leni, min_t(unsigned int, | |
675 | sizeof(root_hub_str_index1), | |
676 | wLength)); | |
677 | data_buf = root_hub_str_index1; | |
678 | break; | |
679 | ||
680 | default: | |
681 | debug("invalid wValue\n"); | |
682 | stat = USB_ST_STALLED; | |
683 | } | |
684 | ||
685 | break; | |
686 | ||
0228348e MF |
687 | case RH_GET_DESCRIPTOR | RH_CLASS: { |
688 | u8 *_data_buf = (u8 *) datab; | |
321790f6 BW |
689 | debug("RH_GET_DESCRIPTOR | RH_CLASS\n"); |
690 | ||
0228348e MF |
691 | _data_buf[0] = 0x09; /* min length; */ |
692 | _data_buf[1] = 0x29; | |
693 | _data_buf[2] = 0x1; /* 1 port */ | |
694 | _data_buf[3] = 0x01; /* per-port power switching */ | |
695 | _data_buf[3] |= 0x10; /* no overcurrent reporting */ | |
321790f6 BW |
696 | |
697 | /* Corresponds to data_buf[4-7] */ | |
0228348e MF |
698 | _data_buf[4] = 0; |
699 | _data_buf[5] = 5; | |
700 | _data_buf[6] = 0; | |
701 | _data_buf[7] = 0x02; | |
702 | _data_buf[8] = 0xff; | |
321790f6 BW |
703 | |
704 | len = min_t(unsigned int, leni, | |
705 | min_t(unsigned int, data_buf[0], wLength)); | |
706 | break; | |
0228348e | 707 | } |
321790f6 BW |
708 | |
709 | case RH_GET_CONFIGURATION: | |
710 | debug("RH_GET_CONFIGURATION\n"); | |
711 | ||
712 | *(__u8 *) data_buf = 0x01; | |
713 | len = 1; | |
714 | break; | |
715 | ||
716 | case RH_SET_CONFIGURATION: | |
717 | debug("RH_SET_CONFIGURATION\n"); | |
718 | ||
719 | len = 0; | |
720 | break; | |
721 | ||
722 | default: | |
723 | debug("*** *** *** unsupported root hub command *** *** ***\n"); | |
724 | stat = USB_ST_STALLED; | |
725 | } | |
726 | ||
727 | len = min_t(int, len, leni); | |
728 | if (buffer != data_buf) | |
729 | memcpy(buffer, data_buf, len); | |
730 | ||
731 | dev->act_len = len; | |
732 | dev->status = stat; | |
b9743081 | 733 | debug("dev act_len %d, status %lu\n", dev->act_len, dev->status); |
321790f6 BW |
734 | |
735 | return stat; | |
736 | } | |
737 | ||
738 | static void musb_rh_init(void) | |
739 | { | |
740 | rh_devnum = 0; | |
741 | port_status = 0; | |
742 | } | |
743 | ||
744 | #else | |
745 | ||
746 | static void musb_rh_init(void) {} | |
747 | ||
748 | #endif | |
749 | ||
a1428969 TA |
750 | /* |
751 | * do a control transfer | |
752 | */ | |
753 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
754 | int len, struct devrequest *setup) | |
755 | { | |
756 | int devnum = usb_pipedevice(pipe); | |
a1428969 TA |
757 | u8 devspeed; |
758 | ||
321790f6 BW |
759 | #ifdef MUSB_NO_MULTIPOINT |
760 | /* Control message is for the HUB? */ | |
b17ce92a CC |
761 | if (devnum == rh_devnum) { |
762 | int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup); | |
763 | if (stat) | |
764 | return stat; | |
765 | } | |
321790f6 BW |
766 | #endif |
767 | ||
a1428969 TA |
768 | /* select control endpoint */ |
769 | writeb(MUSB_CONTROL_EP, &musbr->index); | |
94191960 | 770 | readw(&musbr->txcsr); |
a1428969 | 771 | |
8868fd44 | 772 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
773 | /* target addr and (for multipoint) hub addr/port */ |
774 | writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); | |
775 | writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); | |
8868fd44 | 776 | #endif |
a1428969 TA |
777 | |
778 | /* configure the hub address and the port number as required */ | |
779 | devspeed = get_dev_speed(dev); | |
780 | if ((musb_ishighspeed()) && (dev->parent != NULL) && | |
781 | (devspeed != MUSB_TYPE_SPEED_HIGH)) { | |
782 | config_hub_port(dev, MUSB_CONTROL_EP); | |
783 | writeb(devspeed << 6, &musbr->txtype); | |
784 | } else { | |
785 | writeb(musb_cfg.musb_speed << 6, &musbr->txtype); | |
8868fd44 | 786 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
787 | writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); |
788 | writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); | |
789 | writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); | |
790 | writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); | |
8868fd44 | 791 | #endif |
a1428969 TA |
792 | } |
793 | ||
794 | /* Control transfer setup phase */ | |
795 | if (ctrlreq_setup_phase(dev, setup) < 0) | |
796 | return 0; | |
797 | ||
798 | switch (setup->request) { | |
799 | case USB_REQ_GET_DESCRIPTOR: | |
800 | case USB_REQ_GET_CONFIGURATION: | |
801 | case USB_REQ_GET_INTERFACE: | |
802 | case USB_REQ_GET_STATUS: | |
803 | case USB_MSC_BBB_GET_MAX_LUN: | |
804 | /* control transfer in-data-phase */ | |
805 | if (ctrlreq_in_data_phase(dev, len, buffer) < 0) | |
806 | return 0; | |
807 | /* control transfer out-status-phase */ | |
808 | if (ctrlreq_out_status_phase(dev) < 0) | |
809 | return 0; | |
810 | break; | |
811 | ||
812 | case USB_REQ_SET_ADDRESS: | |
813 | case USB_REQ_SET_CONFIGURATION: | |
814 | case USB_REQ_SET_FEATURE: | |
815 | case USB_REQ_SET_INTERFACE: | |
816 | case USB_REQ_CLEAR_FEATURE: | |
817 | case USB_MSC_BBB_RESET: | |
818 | /* control transfer in status phase */ | |
819 | if (ctrlreq_in_status_phase(dev) < 0) | |
820 | return 0; | |
821 | break; | |
822 | ||
823 | case USB_REQ_SET_DESCRIPTOR: | |
824 | /* control transfer out data phase */ | |
825 | if (ctrlreq_out_data_phase(dev, len, buffer) < 0) | |
826 | return 0; | |
827 | /* control transfer in status phase */ | |
828 | if (ctrlreq_in_status_phase(dev) < 0) | |
829 | return 0; | |
830 | break; | |
831 | ||
832 | default: | |
833 | /* unhandled control transfer */ | |
834 | return -1; | |
835 | } | |
836 | ||
837 | dev->status = 0; | |
838 | dev->act_len = len; | |
93ceb479 BW |
839 | |
840 | #ifdef MUSB_NO_MULTIPOINT | |
841 | /* Set device address to USB_FADDR register */ | |
842 | if (setup->request == USB_REQ_SET_ADDRESS) | |
843 | writeb(dev->devnum, &musbr->faddr); | |
844 | #endif | |
845 | ||
a1428969 TA |
846 | return len; |
847 | } | |
848 | ||
849 | /* | |
850 | * do a bulk transfer | |
851 | */ | |
852 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, | |
853 | void *buffer, int len) | |
854 | { | |
855 | int dir_out = usb_pipeout(pipe); | |
856 | int ep = usb_pipeendpoint(pipe); | |
8868fd44 | 857 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 | 858 | int devnum = usb_pipedevice(pipe); |
8868fd44 | 859 | #endif |
a1428969 TA |
860 | u8 type; |
861 | u16 csr; | |
862 | u32 txlen = 0; | |
863 | u32 nextlen = 0; | |
864 | u8 devspeed; | |
865 | ||
866 | /* select bulk endpoint */ | |
867 | writeb(MUSB_BULK_EP, &musbr->index); | |
868 | ||
8868fd44 | 869 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
870 | /* write the address of the device */ |
871 | if (dir_out) | |
872 | writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); | |
873 | else | |
874 | writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); | |
8868fd44 | 875 | #endif |
a1428969 TA |
876 | |
877 | /* configure the hub address and the port number as required */ | |
878 | devspeed = get_dev_speed(dev); | |
879 | if ((musb_ishighspeed()) && (dev->parent != NULL) && | |
880 | (devspeed != MUSB_TYPE_SPEED_HIGH)) { | |
881 | /* | |
882 | * MUSB is in high speed and the destination device is full | |
883 | * speed device. So configure the hub address and port | |
884 | * address registers. | |
885 | */ | |
886 | config_hub_port(dev, MUSB_BULK_EP); | |
887 | } else { | |
8868fd44 | 888 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
889 | if (dir_out) { |
890 | writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); | |
891 | writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); | |
892 | } else { | |
893 | writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); | |
894 | writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); | |
895 | } | |
8868fd44 | 896 | #endif |
a1428969 TA |
897 | devspeed = musb_cfg.musb_speed; |
898 | } | |
899 | ||
900 | /* Write the saved toggle bit value */ | |
901 | write_toggle(dev, ep, dir_out); | |
902 | ||
903 | if (dir_out) { /* bulk-out transfer */ | |
904 | /* Program the TxType register */ | |
905 | type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | | |
906 | (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | | |
907 | (ep & MUSB_TYPE_REMOTE_END); | |
908 | writeb(type, &musbr->txtype); | |
909 | ||
910 | /* Write maximum packet size to the TxMaxp register */ | |
911 | writew(dev->epmaxpacketout[ep], &musbr->txmaxp); | |
912 | while (txlen < len) { | |
913 | nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? | |
914 | (len-txlen) : dev->epmaxpacketout[ep]; | |
915 | ||
916 | /* Write the data to the FIFO */ | |
917 | write_fifo(MUSB_BULK_EP, nextlen, | |
918 | (void *)(((u8 *)buffer) + txlen)); | |
919 | ||
920 | /* Set the TxPktRdy bit */ | |
921 | csr = readw(&musbr->txcsr); | |
922 | writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); | |
923 | ||
924 | /* Wait until the TxPktRdy bit is cleared */ | |
ddd025bb | 925 | if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) { |
a1428969 TA |
926 | readw(&musbr->txcsr); |
927 | usb_settoggle(dev, ep, dir_out, | |
928 | (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); | |
929 | dev->act_len = txlen; | |
930 | return 0; | |
931 | } | |
932 | txlen += nextlen; | |
933 | } | |
934 | ||
935 | /* Keep a copy of the data toggle bit */ | |
936 | csr = readw(&musbr->txcsr); | |
937 | usb_settoggle(dev, ep, dir_out, | |
938 | (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); | |
939 | } else { /* bulk-in transfer */ | |
940 | /* Write the saved toggle bit value */ | |
941 | write_toggle(dev, ep, dir_out); | |
942 | ||
943 | /* Program the RxType register */ | |
944 | type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | | |
945 | (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | | |
946 | (ep & MUSB_TYPE_REMOTE_END); | |
947 | writeb(type, &musbr->rxtype); | |
948 | ||
949 | /* Write the maximum packet size to the RxMaxp register */ | |
950 | writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); | |
951 | while (txlen < len) { | |
952 | nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? | |
953 | (len-txlen) : dev->epmaxpacketin[ep]; | |
954 | ||
955 | /* Set the ReqPkt bit */ | |
bc72a919 BW |
956 | csr = readw(&musbr->rxcsr); |
957 | writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); | |
a1428969 TA |
958 | |
959 | /* Wait until the RxPktRdy bit is set */ | |
ddd025bb | 960 | if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) { |
a1428969 TA |
961 | csr = readw(&musbr->rxcsr); |
962 | usb_settoggle(dev, ep, dir_out, | |
963 | (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); | |
964 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
965 | writew(csr, &musbr->rxcsr); | |
966 | dev->act_len = txlen; | |
967 | return 0; | |
968 | } | |
969 | ||
970 | /* Read the data from the FIFO */ | |
971 | read_fifo(MUSB_BULK_EP, nextlen, | |
972 | (void *)(((u8 *)buffer) + txlen)); | |
973 | ||
974 | /* Clear the RxPktRdy bit */ | |
975 | csr = readw(&musbr->rxcsr); | |
976 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
977 | writew(csr, &musbr->rxcsr); | |
978 | txlen += nextlen; | |
979 | } | |
980 | ||
981 | /* Keep a copy of the data toggle bit */ | |
982 | csr = readw(&musbr->rxcsr); | |
983 | usb_settoggle(dev, ep, dir_out, | |
984 | (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); | |
985 | } | |
986 | ||
987 | /* bulk transfer is complete */ | |
988 | dev->status = 0; | |
989 | dev->act_len = len; | |
990 | return 0; | |
991 | } | |
992 | ||
993 | /* | |
994 | * This function initializes the usb controller module. | |
995 | */ | |
06d513ec | 996 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
a1428969 TA |
997 | { |
998 | u8 power; | |
999 | u32 timeout; | |
1000 | ||
321790f6 BW |
1001 | musb_rh_init(); |
1002 | ||
a1428969 TA |
1003 | if (musb_platform_init() == -1) |
1004 | return -1; | |
1005 | ||
1006 | /* Configure all the endpoint FIFO's and start usb controller */ | |
1007 | musbr = musb_cfg.regs; | |
e31dc61e | 1008 | musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo)); |
a1428969 TA |
1009 | musb_start(); |
1010 | ||
1011 | /* | |
1012 | * Wait until musb is enabled in host mode with a timeout. There | |
1013 | * should be a usb device connected. | |
1014 | */ | |
1015 | timeout = musb_cfg.timeout; | |
8c865018 | 1016 | while (--timeout) |
a1428969 TA |
1017 | if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) |
1018 | break; | |
1019 | ||
1020 | /* if musb core is not in host mode, then return */ | |
1021 | if (!timeout) | |
1022 | return -1; | |
1023 | ||
1024 | /* start usb bus reset */ | |
1025 | power = readb(&musbr->power); | |
1026 | writeb(power | MUSB_POWER_RESET, &musbr->power); | |
1027 | ||
1028 | /* After initiating a usb reset, wait for about 20ms to 30ms */ | |
1029 | udelay(30000); | |
1030 | ||
1031 | /* stop usb bus reset */ | |
1032 | power = readb(&musbr->power); | |
1033 | power &= ~MUSB_POWER_RESET; | |
1034 | writeb(power, &musbr->power); | |
1035 | ||
1036 | /* Determine if the connected device is a high/full/low speed device */ | |
1037 | musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? | |
1038 | MUSB_TYPE_SPEED_HIGH : | |
1039 | ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? | |
1040 | MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | /* | |
1045 | * This function stops the operation of the davinci usb module. | |
1046 | */ | |
c7e3b2b5 | 1047 | int usb_lowlevel_stop(int index) |
a1428969 TA |
1048 | { |
1049 | /* Reset the USB module */ | |
1050 | musb_platform_deinit(); | |
1051 | writeb(0, &musbr->devctl); | |
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * This function supports usb interrupt transfers. Currently, usb interrupt | |
1057 | * transfers are not supported. | |
1058 | */ | |
1059 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, | |
1060 | void *buffer, int len, int interval) | |
1061 | { | |
1062 | int dir_out = usb_pipeout(pipe); | |
1063 | int ep = usb_pipeendpoint(pipe); | |
8868fd44 | 1064 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 | 1065 | int devnum = usb_pipedevice(pipe); |
8868fd44 | 1066 | #endif |
a1428969 TA |
1067 | u8 type; |
1068 | u16 csr; | |
1069 | u32 txlen = 0; | |
1070 | u32 nextlen = 0; | |
1071 | u8 devspeed; | |
1072 | ||
1073 | /* select interrupt endpoint */ | |
1074 | writeb(MUSB_INTR_EP, &musbr->index); | |
1075 | ||
8868fd44 | 1076 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
1077 | /* write the address of the device */ |
1078 | if (dir_out) | |
1079 | writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); | |
1080 | else | |
1081 | writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); | |
8868fd44 | 1082 | #endif |
a1428969 TA |
1083 | |
1084 | /* configure the hub address and the port number as required */ | |
1085 | devspeed = get_dev_speed(dev); | |
1086 | if ((musb_ishighspeed()) && (dev->parent != NULL) && | |
1087 | (devspeed != MUSB_TYPE_SPEED_HIGH)) { | |
1088 | /* | |
1089 | * MUSB is in high speed and the destination device is full | |
1090 | * speed device. So configure the hub address and port | |
1091 | * address registers. | |
1092 | */ | |
1093 | config_hub_port(dev, MUSB_INTR_EP); | |
1094 | } else { | |
8868fd44 | 1095 | #ifndef MUSB_NO_MULTIPOINT |
a1428969 TA |
1096 | if (dir_out) { |
1097 | writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); | |
1098 | writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); | |
1099 | } else { | |
1100 | writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); | |
1101 | writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); | |
1102 | } | |
8868fd44 | 1103 | #endif |
a1428969 TA |
1104 | devspeed = musb_cfg.musb_speed; |
1105 | } | |
1106 | ||
1107 | /* Write the saved toggle bit value */ | |
1108 | write_toggle(dev, ep, dir_out); | |
1109 | ||
1110 | if (!dir_out) { /* intrrupt-in transfer */ | |
1111 | /* Write the saved toggle bit value */ | |
1112 | write_toggle(dev, ep, dir_out); | |
1113 | writeb(interval, &musbr->rxinterval); | |
1114 | ||
1115 | /* Program the RxType register */ | |
1116 | type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | | |
1117 | (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) | | |
1118 | (ep & MUSB_TYPE_REMOTE_END); | |
1119 | writeb(type, &musbr->rxtype); | |
1120 | ||
1121 | /* Write the maximum packet size to the RxMaxp register */ | |
1122 | writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); | |
1123 | ||
1124 | while (txlen < len) { | |
1125 | nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? | |
1126 | (len-txlen) : dev->epmaxpacketin[ep]; | |
1127 | ||
1128 | /* Set the ReqPkt bit */ | |
bc72a919 BW |
1129 | csr = readw(&musbr->rxcsr); |
1130 | writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); | |
a1428969 TA |
1131 | |
1132 | /* Wait until the RxPktRdy bit is set */ | |
ddd025bb | 1133 | if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) { |
a1428969 TA |
1134 | csr = readw(&musbr->rxcsr); |
1135 | usb_settoggle(dev, ep, dir_out, | |
1136 | (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); | |
1137 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
1138 | writew(csr, &musbr->rxcsr); | |
1139 | dev->act_len = txlen; | |
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | /* Read the data from the FIFO */ | |
1144 | read_fifo(MUSB_INTR_EP, nextlen, | |
1145 | (void *)(((u8 *)buffer) + txlen)); | |
1146 | ||
1147 | /* Clear the RxPktRdy bit */ | |
1148 | csr = readw(&musbr->rxcsr); | |
1149 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
1150 | writew(csr, &musbr->rxcsr); | |
1151 | txlen += nextlen; | |
1152 | } | |
1153 | ||
1154 | /* Keep a copy of the data toggle bit */ | |
1155 | csr = readw(&musbr->rxcsr); | |
1156 | usb_settoggle(dev, ep, dir_out, | |
1157 | (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); | |
1158 | } | |
1159 | ||
1160 | /* interrupt transfer is complete */ | |
1161 | dev->irq_status = 0; | |
1162 | dev->irq_act_len = len; | |
1163 | dev->irq_handle(dev); | |
1164 | dev->status = 0; | |
1165 | dev->act_len = len; | |
1166 | return 0; | |
1167 | } |