[people/ms/u-boot.git] / drivers / usb / musb-new / musb_dma.h

/*
 * MUSB OTG driver DMA controller abstraction
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2006 by Texas Instruments
 * Copyright (C) 2006-2007 Nokia Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef __MUSB_DMA_H__
#define __MUSB_DMA_H__

struct musb_hw_ep;

/*
 * DMA Controller Abstraction
 *
 * DMA Controllers are abstracted to allow use of a variety of different
 * implementations of DMA, as allowed by the Inventra USB cores.  On the
 * host side, usbcore sets up the DMA mappings and flushes caches; on the
 * peripheral side, the gadget controller driver does.  Responsibilities
 * of a DMA controller driver include:
 *
 *  - Handling the details of moving multiple USB packets
 *    in cooperation with the Inventra USB core, including especially
 *    the correct RX side treatment of short packets and buffer-full
 *    states (both of which terminate transfers).
 *
 *  - Knowing the correlation between dma channels and the
 *    Inventra core's local endpoint resources and data direction.
 *
 *  - Maintaining a list of allocated/available channels.
 *
 *  - Updating channel status on interrupts,
 *    whether shared with the Inventra core or separate.
 */

#define	DMA_ADDR_INVALID	(~(dma_addr_t)0)

#ifndef CONFIG_USB_MUSB_PIO_ONLY
#define	is_dma_capable()	(1)
#else
#define	is_dma_capable()	(0)
#endif

#ifdef CONFIG_USB_TI_CPPI_DMA
#define	is_cppi_enabled()	1
#else
#define	is_cppi_enabled()	0
#endif

#ifdef CONFIG_USB_TUSB_OMAP_DMA
#define tusb_dma_omap()			1
#else
#define tusb_dma_omap()			0
#endif

/*
 * DMA channel status ... updated by the dma controller driver whenever that
 * status changes, and protected by the overall controller spinlock.
 */
enum dma_channel_status {
	/* unallocated */
	MUSB_DMA_STATUS_UNKNOWN,
	/* allocated ... but not busy, no errors */
	MUSB_DMA_STATUS_FREE,
	/* busy ... transactions are active */
	MUSB_DMA_STATUS_BUSY,
	/* transaction(s) aborted due to ... dma or memory bus error */
	MUSB_DMA_STATUS_BUS_ABORT,
	/* transaction(s) aborted due to ... core error or USB fault */
	MUSB_DMA_STATUS_CORE_ABORT
};

struct dma_controller;

/**
 * struct dma_channel - A DMA channel.
 * @private_data: channel-private data
 * @max_len: the maximum number of bytes the channel can move in one
 *	transaction (typically representing many USB maximum-sized packets)
 * @actual_len: how many bytes have been transferred
 * @status: current channel status (updated e.g. on interrupt)
 * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
 *
 * channels are associated with an endpoint for the duration of at least
 * one usb transfer.
 */
struct dma_channel {
	void			*private_data;
	/* FIXME not void* private_data, but a dma_controller * */
	size_t			max_len;
	size_t			actual_len;
	enum dma_channel_status	status;
	bool			desired_mode;
};

/*
 * dma_channel_status - return status of dma channel
 * @c: the channel
 *
 * Returns the software's view of the channel status.  If that status is BUSY
 * then it's possible that the hardware has completed (or aborted) a transfer,
 * so the driver needs to update that status.
 */
static inline enum dma_channel_status
dma_channel_status(struct dma_channel *c)
{
	return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
}

/**
 * struct dma_controller - A DMA Controller.
 * @start: call this to start a DMA controller;
 *	return 0 on success, else negative errno
 * @stop: call this to stop a DMA controller
 *	return 0 on success, else negative errno
 * @channel_alloc: call this to allocate a DMA channel
 * @channel_release: call this to release a DMA channel
 * @channel_abort: call this to abort a pending DMA transaction,
 *	returning it to FREE (but allocated) state
 *
 * Controllers manage dma channels.
 */
struct dma_controller {
	int			(*start)(struct dma_controller *);
	int			(*stop)(struct dma_controller *);
	struct dma_channel	*(*channel_alloc)(struct dma_controller *,
					struct musb_hw_ep *, u8 is_tx);
	void			(*channel_release)(struct dma_channel *);
	int			(*channel_program)(struct dma_channel *channel,
							u16 maxpacket, u8 mode,
							dma_addr_t dma_addr,
							u32 length);
	int			(*channel_abort)(struct dma_channel *);
	int			(*is_compatible)(struct dma_channel *channel,
							u16 maxpacket,
							void *buf, u32 length);
};

/* called after channel_program(), may indicate a fault */
extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);


extern struct dma_controller *__init
dma_controller_create(struct musb *, void __iomem *);

extern void dma_controller_destroy(struct dma_controller *);

#endif	/* __MUSB_DMA_H__ */
Commit	Line	Data
eb81955b IY	1	/*
	2	* MUSB OTG driver DMA controller abstraction
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2006 by Texas Instruments
	6	* Copyright (C) 2006-2007 Nokia Corporation
	7	*
5b8031cc	8	* SPDX-License-Identifier: GPL-2.0
eb81955b IY	9	*/
	10
	11	#ifndef __MUSB_DMA_H__
	12	#define __MUSB_DMA_H__
	13
	14	struct musb_hw_ep;
	15
	16	/*
	17	* DMA Controller Abstraction
	18	*
	19	* DMA Controllers are abstracted to allow use of a variety of different
	20	* implementations of DMA, as allowed by the Inventra USB cores. On the
	21	* host side, usbcore sets up the DMA mappings and flushes caches; on the
	22	* peripheral side, the gadget controller driver does. Responsibilities
	23	* of a DMA controller driver include:
	24	*
	25	* - Handling the details of moving multiple USB packets
	26	* in cooperation with the Inventra USB core, including especially
	27	* the correct RX side treatment of short packets and buffer-full
	28	* states (both of which terminate transfers).
	29	*
	30	* - Knowing the correlation between dma channels and the
	31	* Inventra core's local endpoint resources and data direction.
	32	*
	33	* - Maintaining a list of allocated/available channels.
	34	*
	35	* - Updating channel status on interrupts,
	36	* whether shared with the Inventra core or separate.
	37	*/
	38
	39	#define DMA_ADDR_INVALID (~(dma_addr_t)0)
	40
95de1e2f	41	#ifndef CONFIG_USB_MUSB_PIO_ONLY
eb81955b IY	42	#define is_dma_capable() (1)
	43	#else
	44	#define is_dma_capable() (0)
	45	#endif
	46
	47	#ifdef CONFIG_USB_TI_CPPI_DMA
	48	#define is_cppi_enabled() 1
	49	#else
	50	#define is_cppi_enabled() 0
	51	#endif
	52
	53	#ifdef CONFIG_USB_TUSB_OMAP_DMA
	54	#define tusb_dma_omap() 1
	55	#else
	56	#define tusb_dma_omap() 0
	57	#endif
	58
eb81955b IY	59	/*
	60	* DMA channel status ... updated by the dma controller driver whenever that
	61	* status changes, and protected by the overall controller spinlock.
	62	*/
	63	enum dma_channel_status {
	64	/* unallocated */
	65	MUSB_DMA_STATUS_UNKNOWN,
	66	/* allocated ... but not busy, no errors */
	67	MUSB_DMA_STATUS_FREE,
	68	/* busy ... transactions are active */
	69	MUSB_DMA_STATUS_BUSY,
	70	/* transaction(s) aborted due to ... dma or memory bus error */
	71	MUSB_DMA_STATUS_BUS_ABORT,
	72	/* transaction(s) aborted due to ... core error or USB fault */
	73	MUSB_DMA_STATUS_CORE_ABORT
	74	};
	75
	76	struct dma_controller;
	77
	78	/**
	79	* struct dma_channel - A DMA channel.
	80	* @private_data: channel-private data
	81	* @max_len: the maximum number of bytes the channel can move in one
	82	* transaction (typically representing many USB maximum-sized packets)
	83	* @actual_len: how many bytes have been transferred
	84	* @status: current channel status (updated e.g. on interrupt)
	85	* @desired_mode: true if mode 1 is desired; false if mode 0 is desired
	86	*
	87	* channels are associated with an endpoint for the duration of at least
	88	* one usb transfer.
	89	*/
	90	struct dma_channel {
	91	void *private_data;
	92	/* FIXME not void* private_data, but a dma_controller * */
	93	size_t max_len;
	94	size_t actual_len;
	95	enum dma_channel_status status;
	96	bool desired_mode;
	97	};
	98
	99	/*
	100	* dma_channel_status - return status of dma channel
	101	* @c: the channel
	102	*
	103	* Returns the software's view of the channel status. If that status is BUSY
	104	* then it's possible that the hardware has completed (or aborted) a transfer,
	105	* so the driver needs to update that status.
	106	*/
	107	static inline enum dma_channel_status
	108	dma_channel_status(struct dma_channel *c)
	109	{
	110	return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
	111	}
	112
	113	/**
	114	* struct dma_controller - A DMA Controller.
	115	* @start: call this to start a DMA controller;
	116	* return 0 on success, else negative errno
	117	* @stop: call this to stop a DMA controller
	118	* return 0 on success, else negative errno
	119	* @channel_alloc: call this to allocate a DMA channel
	120	* @channel_release: call this to release a DMA channel
	121	* @channel_abort: call this to abort a pending DMA transaction,
	122	* returning it to FREE (but allocated) state
123	*
124	* Controllers manage dma channels.
125	*/
126	struct dma_controller {
127	int (start)(struct dma_controller );
128	int (stop)(struct dma_controller );
129	struct dma_channel (channel_alloc)(struct dma_controller *,
130	struct musb_hw_ep *, u8 is_tx);
131	void (channel_release)(struct dma_channel );
132	int (channel_program)(struct dma_channel channel,
133	u16 maxpacket, u8 mode,
134	dma_addr_t dma_addr,
135	u32 length);
136	int (channel_abort)(struct dma_channel );
137	int (is_compatible)(struct dma_channel channel,
138	u16 maxpacket,
139	void *buf, u32 length);
140	};
141
142	/* called after channel_program(), may indicate a fault */
143	extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
144
145
146	extern struct dma_controller *__init
147	dma_controller_create(struct musb , void __iomem );
148
149	extern void dma_controller_destroy(struct dma_controller *);
150
151	#endif /* __MUSB_DMA_H__ */