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3e326ece MK |
1 | /* |
2 | * URB OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> | |
6 | * | |
7 | * usb-ohci.h | |
8 | */ | |
9 | ||
10 | /* functions for doing board specific setup/cleanup */ | |
24e37645 | 11 | #ifdef CFG_USB_BOARD_INIT |
3e326ece MK |
12 | extern int usb_board_init(void); |
13 | extern int usb_board_stop(void); | |
ddf83a2f | 14 | extern int usb_cpu_init_fail(void); |
24e37645 MK |
15 | #endif |
16 | ||
17 | #ifdef CFG_USB_CPU_INIT | |
18 | extern int usb_cpu_init(void); | |
19 | extern int usb_cpu_stop(void); | |
ddf83a2f | 20 | extern int usb_cpu_init_fail(void); |
24e37645 MK |
21 | #endif |
22 | ||
3e326ece MK |
23 | |
24 | static int cc_to_error[16] = { | |
25 | ||
26 | /* mapping of the OHCI CC status to error codes */ | |
27 | /* No Error */ 0, | |
28 | /* CRC Error */ USB_ST_CRC_ERR, | |
29 | /* Bit Stuff */ USB_ST_BIT_ERR, | |
30 | /* Data Togg */ USB_ST_CRC_ERR, | |
31 | /* Stall */ USB_ST_STALLED, | |
32 | /* DevNotResp */ -1, | |
33 | /* PIDCheck */ USB_ST_BIT_ERR, | |
34 | /* UnExpPID */ USB_ST_BIT_ERR, | |
35 | /* DataOver */ USB_ST_BUF_ERR, | |
36 | /* DataUnder */ USB_ST_BUF_ERR, | |
37 | /* reservd */ -1, | |
38 | /* reservd */ -1, | |
39 | /* BufferOver */ USB_ST_BUF_ERR, | |
40 | /* BuffUnder */ USB_ST_BUF_ERR, | |
41 | /* Not Access */ -1, | |
42 | /* Not Access */ -1 | |
43 | }; | |
44 | ||
45 | /* ED States */ | |
46 | ||
47 | #define ED_NEW 0x00 | |
48 | #define ED_UNLINK 0x01 | |
49 | #define ED_OPER 0x02 | |
50 | #define ED_DEL 0x04 | |
51 | #define ED_URB_DEL 0x08 | |
52 | ||
53 | /* usb_ohci_ed */ | |
54 | struct ed { | |
55 | __u32 hwINFO; | |
56 | __u32 hwTailP; | |
57 | __u32 hwHeadP; | |
58 | __u32 hwNextED; | |
59 | ||
60 | struct ed *ed_prev; | |
61 | __u8 int_period; | |
62 | __u8 int_branch; | |
63 | __u8 int_load; | |
64 | __u8 int_interval; | |
65 | __u8 state; | |
66 | __u8 type; | |
67 | __u16 last_iso; | |
68 | struct ed *ed_rm_list; | |
69 | ||
70 | struct usb_device *usb_dev; | |
71 | __u32 unused[3]; | |
72 | } __attribute((aligned(16))); | |
73 | typedef struct ed ed_t; | |
74 | ||
75 | ||
76 | /* TD info field */ | |
77 | #define TD_CC 0xf0000000 | |
78 | #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) | |
79 | #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) | |
80 | #define TD_EC 0x0C000000 | |
81 | #define TD_T 0x03000000 | |
82 | #define TD_T_DATA0 0x02000000 | |
83 | #define TD_T_DATA1 0x03000000 | |
84 | #define TD_T_TOGGLE 0x00000000 | |
85 | #define TD_R 0x00040000 | |
86 | #define TD_DI 0x00E00000 | |
87 | #define TD_DI_SET(X) (((X) & 0x07)<< 21) | |
88 | #define TD_DP 0x00180000 | |
89 | #define TD_DP_SETUP 0x00000000 | |
90 | #define TD_DP_IN 0x00100000 | |
91 | #define TD_DP_OUT 0x00080000 | |
92 | ||
93 | #define TD_ISO 0x00010000 | |
94 | #define TD_DEL 0x00020000 | |
95 | ||
96 | /* CC Codes */ | |
97 | #define TD_CC_NOERROR 0x00 | |
98 | #define TD_CC_CRC 0x01 | |
99 | #define TD_CC_BITSTUFFING 0x02 | |
100 | #define TD_CC_DATATOGGLEM 0x03 | |
101 | #define TD_CC_STALL 0x04 | |
102 | #define TD_DEVNOTRESP 0x05 | |
103 | #define TD_PIDCHECKFAIL 0x06 | |
104 | #define TD_UNEXPECTEDPID 0x07 | |
105 | #define TD_DATAOVERRUN 0x08 | |
106 | #define TD_DATAUNDERRUN 0x09 | |
107 | #define TD_BUFFEROVERRUN 0x0C | |
108 | #define TD_BUFFERUNDERRUN 0x0D | |
109 | #define TD_NOTACCESSED 0x0F | |
110 | ||
111 | ||
112 | #define MAXPSW 1 | |
113 | ||
114 | struct td { | |
115 | __u32 hwINFO; | |
116 | __u32 hwCBP; /* Current Buffer Pointer */ | |
117 | __u32 hwNextTD; /* Next TD Pointer */ | |
118 | __u32 hwBE; /* Memory Buffer End Pointer */ | |
119 | ||
120 | __u16 hwPSW[MAXPSW]; | |
121 | __u8 unused; | |
122 | __u8 index; | |
123 | struct ed *ed; | |
124 | struct td *next_dl_td; | |
125 | struct usb_device *usb_dev; | |
126 | int transfer_len; | |
127 | __u32 data; | |
128 | ||
129 | __u32 unused2[2]; | |
130 | } __attribute((aligned(32))); | |
131 | typedef struct td td_t; | |
132 | ||
133 | #define OHCI_ED_SKIP (1 << 14) | |
134 | ||
135 | /* | |
136 | * The HCCA (Host Controller Communications Area) is a 256 byte | |
137 | * structure defined in the OHCI spec. that the host controller is | |
138 | * told the base address of. It must be 256-byte aligned. | |
139 | */ | |
140 | ||
141 | #define NUM_INTS 32 /* part of the OHCI standard */ | |
142 | struct ohci_hcca { | |
143 | __u32 int_table[NUM_INTS]; /* Interrupt ED table */ | |
144 | __u16 frame_no; /* current frame number */ | |
145 | __u16 pad1; /* set to 0 on each frame_no change */ | |
146 | __u32 done_head; /* info returned for an interrupt */ | |
147 | u8 reserved_for_hc[116]; | |
148 | } __attribute((aligned(256))); | |
149 | ||
150 | ||
151 | /* | |
152 | * Maximum number of root hub ports. | |
153 | */ | |
154 | #define MAX_ROOT_PORTS 3 /* maximum OHCI root hub ports */ | |
155 | ||
156 | /* | |
157 | * This is the structure of the OHCI controller's memory mapped I/O | |
158 | * region. This is Memory Mapped I/O. You must use the readl() and | |
159 | * writel() macros defined in asm/io.h to access these!! | |
160 | */ | |
161 | struct ohci_regs { | |
162 | /* control and status registers */ | |
163 | __u32 revision; | |
164 | __u32 control; | |
165 | __u32 cmdstatus; | |
166 | __u32 intrstatus; | |
167 | __u32 intrenable; | |
168 | __u32 intrdisable; | |
169 | /* memory pointers */ | |
170 | __u32 hcca; | |
171 | __u32 ed_periodcurrent; | |
172 | __u32 ed_controlhead; | |
173 | __u32 ed_controlcurrent; | |
174 | __u32 ed_bulkhead; | |
175 | __u32 ed_bulkcurrent; | |
176 | __u32 donehead; | |
177 | /* frame counters */ | |
178 | __u32 fminterval; | |
179 | __u32 fmremaining; | |
180 | __u32 fmnumber; | |
181 | __u32 periodicstart; | |
182 | __u32 lsthresh; | |
183 | /* Root hub ports */ | |
184 | struct ohci_roothub_regs { | |
185 | __u32 a; | |
186 | __u32 b; | |
187 | __u32 status; | |
188 | __u32 portstatus[MAX_ROOT_PORTS]; | |
189 | } roothub; | |
190 | } __attribute((aligned(32))); | |
191 | ||
192 | ||
193 | /* OHCI CONTROL AND STATUS REGISTER MASKS */ | |
194 | ||
195 | /* | |
196 | * HcControl (control) register masks | |
197 | */ | |
198 | #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ | |
199 | #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ | |
200 | #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ | |
201 | #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ | |
202 | #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ | |
203 | #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ | |
204 | #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ | |
205 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ | |
206 | #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ | |
207 | ||
208 | /* pre-shifted values for HCFS */ | |
209 | # define OHCI_USB_RESET (0 << 6) | |
210 | # define OHCI_USB_RESUME (1 << 6) | |
211 | # define OHCI_USB_OPER (2 << 6) | |
212 | # define OHCI_USB_SUSPEND (3 << 6) | |
213 | ||
214 | /* | |
215 | * HcCommandStatus (cmdstatus) register masks | |
216 | */ | |
217 | #define OHCI_HCR (1 << 0) /* host controller reset */ | |
218 | #define OHCI_CLF (1 << 1) /* control list filled */ | |
219 | #define OHCI_BLF (1 << 2) /* bulk list filled */ | |
220 | #define OHCI_OCR (1 << 3) /* ownership change request */ | |
221 | #define OHCI_SOC (3 << 16) /* scheduling overrun count */ | |
222 | ||
223 | /* | |
224 | * masks used with interrupt registers: | |
225 | * HcInterruptStatus (intrstatus) | |
226 | * HcInterruptEnable (intrenable) | |
227 | * HcInterruptDisable (intrdisable) | |
228 | */ | |
229 | #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ | |
230 | #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ | |
231 | #define OHCI_INTR_SF (1 << 2) /* start frame */ | |
232 | #define OHCI_INTR_RD (1 << 3) /* resume detect */ | |
233 | #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ | |
234 | #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ | |
235 | #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ | |
236 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ | |
237 | #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ | |
238 | ||
239 | ||
240 | /* Virtual Root HUB */ | |
241 | struct virt_root_hub { | |
242 | int devnum; /* Address of Root Hub endpoint */ | |
243 | void *dev; /* was urb */ | |
244 | void *int_addr; | |
245 | int send; | |
246 | int interval; | |
247 | }; | |
248 | ||
249 | /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ | |
250 | ||
251 | /* destination of request */ | |
252 | #define RH_INTERFACE 0x01 | |
253 | #define RH_ENDPOINT 0x02 | |
254 | #define RH_OTHER 0x03 | |
255 | ||
256 | #define RH_CLASS 0x20 | |
257 | #define RH_VENDOR 0x40 | |
258 | ||
259 | /* Requests: bRequest << 8 | bmRequestType */ | |
260 | #define RH_GET_STATUS 0x0080 | |
261 | #define RH_CLEAR_FEATURE 0x0100 | |
262 | #define RH_SET_FEATURE 0x0300 | |
263 | #define RH_SET_ADDRESS 0x0500 | |
264 | #define RH_GET_DESCRIPTOR 0x0680 | |
265 | #define RH_SET_DESCRIPTOR 0x0700 | |
266 | #define RH_GET_CONFIGURATION 0x0880 | |
267 | #define RH_SET_CONFIGURATION 0x0900 | |
268 | #define RH_GET_STATE 0x0280 | |
269 | #define RH_GET_INTERFACE 0x0A80 | |
270 | #define RH_SET_INTERFACE 0x0B00 | |
271 | #define RH_SYNC_FRAME 0x0C80 | |
272 | /* Our Vendor Specific Request */ | |
273 | #define RH_SET_EP 0x2000 | |
274 | ||
275 | ||
276 | /* Hub port features */ | |
277 | #define RH_PORT_CONNECTION 0x00 | |
278 | #define RH_PORT_ENABLE 0x01 | |
279 | #define RH_PORT_SUSPEND 0x02 | |
280 | #define RH_PORT_OVER_CURRENT 0x03 | |
281 | #define RH_PORT_RESET 0x04 | |
282 | #define RH_PORT_POWER 0x08 | |
283 | #define RH_PORT_LOW_SPEED 0x09 | |
284 | ||
285 | #define RH_C_PORT_CONNECTION 0x10 | |
286 | #define RH_C_PORT_ENABLE 0x11 | |
287 | #define RH_C_PORT_SUSPEND 0x12 | |
288 | #define RH_C_PORT_OVER_CURRENT 0x13 | |
289 | #define RH_C_PORT_RESET 0x14 | |
290 | ||
291 | /* Hub features */ | |
292 | #define RH_C_HUB_LOCAL_POWER 0x00 | |
293 | #define RH_C_HUB_OVER_CURRENT 0x01 | |
294 | ||
295 | #define RH_DEVICE_REMOTE_WAKEUP 0x00 | |
296 | #define RH_ENDPOINT_STALL 0x01 | |
297 | ||
298 | #define RH_ACK 0x01 | |
299 | #define RH_REQ_ERR -1 | |
300 | #define RH_NACK 0x00 | |
301 | ||
302 | ||
303 | /* OHCI ROOT HUB REGISTER MASKS */ | |
304 | ||
305 | /* roothub.portstatus [i] bits */ | |
306 | #define RH_PS_CCS 0x00000001 /* current connect status */ | |
307 | #define RH_PS_PES 0x00000002 /* port enable status*/ | |
308 | #define RH_PS_PSS 0x00000004 /* port suspend status */ | |
309 | #define RH_PS_POCI 0x00000008 /* port over current indicator */ | |
310 | #define RH_PS_PRS 0x00000010 /* port reset status */ | |
311 | #define RH_PS_PPS 0x00000100 /* port power status */ | |
312 | #define RH_PS_LSDA 0x00000200 /* low speed device attached */ | |
313 | #define RH_PS_CSC 0x00010000 /* connect status change */ | |
314 | #define RH_PS_PESC 0x00020000 /* port enable status change */ | |
315 | #define RH_PS_PSSC 0x00040000 /* port suspend status change */ | |
316 | #define RH_PS_OCIC 0x00080000 /* over current indicator change */ | |
317 | #define RH_PS_PRSC 0x00100000 /* port reset status change */ | |
318 | ||
319 | /* roothub.status bits */ | |
320 | #define RH_HS_LPS 0x00000001 /* local power status */ | |
321 | #define RH_HS_OCI 0x00000002 /* over current indicator */ | |
322 | #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ | |
323 | #define RH_HS_LPSC 0x00010000 /* local power status change */ | |
324 | #define RH_HS_OCIC 0x00020000 /* over current indicator change */ | |
325 | #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ | |
326 | ||
327 | /* roothub.b masks */ | |
328 | #define RH_B_DR 0x0000ffff /* device removable flags */ | |
329 | #define RH_B_PPCM 0xffff0000 /* port power control mask */ | |
330 | ||
331 | /* roothub.a masks */ | |
332 | #define RH_A_NDP (0xff << 0) /* number of downstream ports */ | |
333 | #define RH_A_PSM (1 << 8) /* power switching mode */ | |
334 | #define RH_A_NPS (1 << 9) /* no power switching */ | |
335 | #define RH_A_DT (1 << 10) /* device type (mbz) */ | |
336 | #define RH_A_OCPM (1 << 11) /* over current protection mode */ | |
337 | #define RH_A_NOCP (1 << 12) /* no over current protection */ | |
338 | #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ | |
339 | ||
340 | /* urb */ | |
341 | #define N_URB_TD 48 | |
342 | typedef struct | |
343 | { | |
344 | ed_t *ed; | |
345 | __u16 length; /* number of tds associated with this request */ | |
346 | __u16 td_cnt; /* number of tds already serviced */ | |
347 | int state; | |
348 | unsigned long pipe; | |
349 | int actual_length; | |
350 | td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ | |
351 | } urb_priv_t; | |
352 | #define URB_DEL 1 | |
353 | ||
354 | /* | |
355 | * This is the full ohci controller description | |
356 | * | |
357 | * Note how the "proper" USB information is just | |
358 | * a subset of what the full implementation needs. (Linus) | |
359 | */ | |
360 | ||
361 | ||
362 | typedef struct ohci { | |
363 | struct ohci_hcca *hcca; /* hcca */ | |
364 | /*dma_addr_t hcca_dma;*/ | |
365 | ||
366 | int irq; | |
367 | int disabled; /* e.g. got a UE, we're hung */ | |
368 | int sleeping; | |
369 | unsigned long flags; /* for HC bugs */ | |
370 | ||
371 | struct ohci_regs *regs; /* OHCI controller's memory */ | |
372 | ||
373 | ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ | |
374 | ed_t *ed_bulktail; /* last endpoint of bulk list */ | |
375 | ed_t *ed_controltail; /* last endpoint of control list */ | |
376 | int intrstatus; | |
377 | __u32 hc_control; /* copy of the hc control reg */ | |
378 | struct usb_device *dev[32]; | |
379 | struct virt_root_hub rh; | |
380 | ||
381 | const char *slot_name; | |
382 | } ohci_t; | |
383 | ||
384 | #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ | |
385 | ||
386 | struct ohci_device { | |
387 | ed_t ed[NUM_EDS]; | |
388 | int ed_cnt; | |
389 | }; | |
390 | ||
391 | /* hcd */ | |
392 | /* endpoint */ | |
393 | static int ep_link(ohci_t * ohci, ed_t * ed); | |
394 | static int ep_unlink(ohci_t * ohci, ed_t * ed); | |
395 | static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); | |
396 | ||
397 | /*-------------------------------------------------------------------------*/ | |
398 | ||
399 | /* we need more TDs than EDs */ | |
400 | #define NUM_TD 64 | |
401 | ||
402 | /* +1 so we can align the storage */ | |
403 | td_t gtd[NUM_TD+1]; | |
404 | /* pointers to aligned storage */ | |
405 | td_t *ptd; | |
406 | ||
407 | /* TDs ... */ | |
408 | static inline struct td * | |
409 | td_alloc (struct usb_device *usb_dev) | |
410 | { | |
411 | int i; | |
412 | struct td *td; | |
413 | ||
414 | td = NULL; | |
415 | for (i = 0; i < NUM_TD; i++) | |
416 | { | |
417 | if (ptd[i].usb_dev == NULL) | |
418 | { | |
419 | td = &ptd[i]; | |
420 | td->usb_dev = usb_dev; | |
421 | break; | |
422 | } | |
423 | } | |
424 | ||
425 | return td; | |
426 | } | |
427 | ||
428 | static inline void | |
429 | ed_free (struct ed *ed) | |
430 | { | |
431 | ed->usb_dev = NULL; | |
432 | } |