]>
Commit | Line | Data |
---|---|---|
39cf4804 SP |
1 | /* |
2 | * Driver for AT91/AT32 LCD Controller | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <asm/io.h> | |
39cf4804 SP |
27 | #include <asm/arch/gpio.h> |
28 | #include <asm/arch/clk.h> | |
29 | #include <lcd.h> | |
30 | #include <atmel_lcdc.h> | |
31 | ||
32 | int lcd_line_length; | |
39cf4804 SP |
33 | |
34 | void *lcd_base; /* Start of framebuffer memory */ | |
35 | void *lcd_console_address; /* Start of console buffer */ | |
36 | ||
37 | short console_col; | |
38 | short console_row; | |
39 | ||
40 | /* configurable parameters */ | |
41 | #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 | |
42 | #define ATMEL_LCDC_DMA_BURST_LEN 8 | |
6bbced67 MJ |
43 | #ifndef ATMEL_LCDC_GUARD_TIME |
44 | #define ATMEL_LCDC_GUARD_TIME 1 | |
45 | #endif | |
39cf4804 SP |
46 | |
47 | #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9) | |
48 | #define ATMEL_LCDC_FIFO_SIZE 2048 | |
49 | #else | |
50 | #define ATMEL_LCDC_FIFO_SIZE 512 | |
51 | #endif | |
52 | ||
53 | #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) | |
54 | #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) | |
55 | ||
56 | void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) | |
57 | { | |
58 | #if defined(CONFIG_ATMEL_LCD_BGR555) | |
59 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), | |
60 | (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7)); | |
61 | #else | |
62 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), | |
63 | (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8)); | |
64 | #endif | |
65 | } | |
66 | ||
67 | void lcd_ctrl_init(void *lcdbase) | |
68 | { | |
69 | unsigned long value; | |
70 | ||
71 | /* Turn off the LCD controller and the DMA controller */ | |
72 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, | |
6bbced67 | 73 | ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET); |
39cf4804 SP |
74 | |
75 | /* Wait for the LCDC core to become idle */ | |
76 | while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) | |
77 | udelay(10); | |
78 | ||
79 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0); | |
80 | ||
81 | /* Reset LCDC DMA */ | |
82 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); | |
83 | ||
84 | /* ...set frame size and burst length = 8 words (?) */ | |
85 | value = (panel_info.vl_col * panel_info.vl_row * | |
86 | NBITS(panel_info.vl_bpix)) / 32; | |
87 | value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); | |
88 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value); | |
89 | ||
90 | /* Set pixel clock */ | |
91 | value = get_lcdc_clk_rate(0) / panel_info.vl_clk; | |
92 | if (get_lcdc_clk_rate(0) % panel_info.vl_clk) | |
93 | value++; | |
94 | value = (value / 2) - 1; | |
95 | ||
96 | if (!value) { | |
97 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); | |
98 | } else | |
99 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, | |
100 | value << ATMEL_LCDC_CLKVAL_OFFSET); | |
101 | ||
102 | /* Initialize control register 2 */ | |
f2302d44 SR |
103 | #ifdef CONFIG_AVR32 |
104 | value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; | |
105 | #else | |
39cf4804 | 106 | value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; |
f2302d44 | 107 | #endif |
39cf4804 SP |
108 | if (panel_info.vl_tft) |
109 | value |= ATMEL_LCDC_DISTYPE_TFT; | |
110 | ||
70dbc54c | 111 | value |= panel_info.vl_sync; |
39cf4804 SP |
112 | value |= (panel_info.vl_bpix << 5); |
113 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); | |
114 | ||
115 | /* Vertical timing */ | |
116 | value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; | |
117 | value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET; | |
118 | value |= panel_info.vl_lower_margin; | |
119 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value); | |
120 | ||
121 | /* Horizontal timing */ | |
122 | value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; | |
123 | value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; | |
124 | value |= (panel_info.vl_left_margin - 1); | |
125 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value); | |
126 | ||
127 | /* Display size */ | |
128 | value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET; | |
129 | value |= panel_info.vl_row - 1; | |
130 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value); | |
131 | ||
132 | /* FIFO Threshold: Use formula from data sheet */ | |
133 | value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); | |
134 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value); | |
135 | ||
136 | /* Toggle LCD_MODE every frame */ | |
137 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0); | |
138 | ||
139 | /* Disable all interrupts */ | |
140 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL); | |
141 | ||
142 | /* Set contrast */ | |
143 | value = ATMEL_LCDC_PS_DIV8 | | |
39cf4804 | 144 | ATMEL_LCDC_ENA_PWMENABLE; |
cdfcedbf AS |
145 | if (!panel_info.vl_cont_pol_low) |
146 | value |= ATMEL_LCDC_POL_POSITIVE; | |
39cf4804 SP |
147 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value); |
148 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); | |
149 | ||
150 | /* Set framebuffer DMA base address and pixel offset */ | |
151 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase); | |
152 | ||
153 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); | |
154 | lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, | |
6bbced67 | 155 | (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); |
39cf4804 SP |
156 | } |
157 | ||
158 | ulong calc_fbsize(void) | |
159 | { | |
160 | return ((panel_info.vl_col * panel_info.vl_row * | |
161 | NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; | |
162 | } |