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Merge tag 'video-for-2019.07-rc1' of git://git.denx.de/u-boot-video
[thirdparty/u-boot.git] / drivers / video / da8xx-fb.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
13402868
SB		 2/*
3 * Porting to u-boot:
4 *
5 * (C) Copyright 2011
6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 *
8 * Copyright (C) 2008-2009 MontaVista Software Inc.
9 * Copyright (C) 2008-2009 Texas Instruments Inc
10 *
11 * Based on the LCD driver for TI Avalanche processors written by
12 * Ajay Singh and Shalom Hai.
13402868
SB		 13 */
14
15#include <common.h>
963be689 16#include <memalign.h>
13402868
SB		 17#include <video_fb.h>
18#include <linux/list.h>
19#include <linux/fb.h>
20
1221ce45 21#include <linux/errno.h>
13402868
SB		 22#include <asm/io.h>
23#include <asm/arch/hardware.h>
24
25#include "videomodes.h"
0017f9ee 26#include "da8xx-fb.h"
13402868 27
765f2f08
HS		 28#if !defined(DA8XX_LCD_CNTL_BASE)
29#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
30#endif
31
13402868
SB		 32#define DRIVER_NAME "da8xx_lcdc"
33
765f2f08
HS		 34#define LCD_VERSION_1 1
35#define LCD_VERSION_2 2
36
13402868
SB		 37/* LCD Status Register */
38#define LCD_END_OF_FRAME1 (1 << 9)
39#define LCD_END_OF_FRAME0 (1 << 8)
40#define LCD_PL_LOAD_DONE (1 << 6)
41#define LCD_FIFO_UNDERFLOW (1 << 5)
42#define LCD_SYNC_LOST (1 << 2)
43
44/* LCD DMA Control Register */
45#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
46#define LCD_DMA_BURST_1 0x0
47#define LCD_DMA_BURST_2 0x1
48#define LCD_DMA_BURST_4 0x2
49#define LCD_DMA_BURST_8 0x3
50#define LCD_DMA_BURST_16 0x4
765f2f08
HS		 51#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
52#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
53#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
13402868
SB		 54#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
55
765f2f08
HS		 56#define LCD_V2_TFT_24BPP_MODE (1 << 25)
57#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
58
13402868
SB		 59/* LCD Control Register */
60#define LCD_CLK_DIVISOR(x) ((x) << 8)
61#define LCD_RASTER_MODE 0x01
62
63/* LCD Raster Control Register */
64#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
65#define PALETTE_AND_DATA 0x00
66#define PALETTE_ONLY 0x01
67#define DATA_ONLY 0x02
68
69#define LCD_MONO_8BIT_MODE (1 << 9)
70#define LCD_RASTER_ORDER (1 << 8)
71#define LCD_TFT_MODE (1 << 7)
765f2f08
HS		 72#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
73#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
74#define LCD_V1_PL_INT_ENA (1 << 4)
75#define LCD_V2_PL_INT_ENA (1 << 6)
13402868
SB		 76#define LCD_MONOCHROME_MODE (1 << 1)
77#define LCD_RASTER_ENABLE (1 << 0)
78#define LCD_TFT_ALT_ENABLE (1 << 23)
79#define LCD_STN_565_ENABLE (1 << 24)
765f2f08
HS		 80#define LCD_V2_DMA_CLK_EN (1 << 2)
81#define LCD_V2_LIDD_CLK_EN (1 << 1)
82#define LCD_V2_CORE_CLK_EN (1 << 0)
83#define LCD_V2_LPP_B10 26
84#define LCD_V2_TFT_24BPP_MODE (1 << 25)
85#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
13402868
SB		 86
87/* LCD Raster Timing 2 Register */
88#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
89#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
90#define LCD_SYNC_CTRL (1 << 25)
91#define LCD_SYNC_EDGE (1 << 24)
92#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
93#define LCD_INVERT_LINE_CLOCK (1 << 21)
94#define LCD_INVERT_FRAME_CLOCK (1 << 20)
95
765f2f08
HS		 96/* Clock registers available only on Version 2 */
97#define LCD_CLK_MAIN_RESET (1 << 3)
13402868
SB		 98/* LCD Block */
99struct da8xx_lcd_regs {
100 u32 revid;
101 u32 ctrl;
102 u32 stat;
103 u32 lidd_ctrl;
104 u32 lidd_cs0_conf;
105 u32 lidd_cs0_addr;
106 u32 lidd_cs0_data;
107 u32 lidd_cs1_conf;
108 u32 lidd_cs1_addr;
109 u32 lidd_cs1_data;
110 u32 raster_ctrl;
111 u32 raster_timing_0;
112 u32 raster_timing_1;
113 u32 raster_timing_2;
114 u32 raster_subpanel;
115 u32 reserved;
116 u32 dma_ctrl;
117 u32 dma_frm_buf_base_addr_0;
118 u32 dma_frm_buf_ceiling_addr_0;
119 u32 dma_frm_buf_base_addr_1;
120 u32 dma_frm_buf_ceiling_addr_1;
765f2f08
HS		 121 u32 resv1;
122 u32 raw_stat;
123 u32 masked_stat;
124 u32 int_ena_set;
125 u32 int_ena_clr;
126 u32 end_of_int_ind;
127 /* Clock registers available only on Version 2 */
128 u32 clk_ena;
129 u32 clk_reset;
13402868
SB		 130};
131
132#define LCD_NUM_BUFFERS 1
133
134#define WSI_TIMEOUT 50
135#define PALETTE_SIZE 256
136#define LEFT_MARGIN 64
137#define RIGHT_MARGIN 64
138#define UPPER_MARGIN 32
139#define LOWER_MARGIN 32
765f2f08
HS		 140#define WAIT_FOR_FRAME_DONE true
141#define NO_WAIT_FOR_FRAME_DONE false
13402868
SB		 142
143#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
13402868
SB		 144
145static struct da8xx_lcd_regs *da8xx_fb_reg_base;
146
147DECLARE_GLOBAL_DATA_PTR;
148
149/* graphics setup */
150static GraphicDevice gpanel;
151static const struct da8xx_panel *lcd_panel;
152static struct fb_info *da8xx_fb_info;
153static int bits_x_pixel;
765f2f08
HS		 154static unsigned int lcd_revision;
155const struct lcd_ctrl_config *da8xx_lcd_cfg;
13402868
SB		 156
157static inline unsigned int lcdc_read(u32 *addr)
158{
159 return (unsigned int)readl(addr);
160}
161
162static inline void lcdc_write(unsigned int val, u32 *addr)
163{
164 writel(val, addr);
165}
166
167struct da8xx_fb_par {
168 u32 p_palette_base;
169 unsigned char *v_palette_base;
170 dma_addr_t vram_phys;
171 unsigned long vram_size;
172 void *vram_virt;
173 unsigned int dma_start;
174 unsigned int dma_end;
175 struct clk *lcdc_clk;
176 int irq;
177 unsigned short pseudo_palette[16];
178 unsigned int palette_sz;
179 unsigned int pxl_clk;
180 int blank;
181 int vsync_flag;
182 int vsync_timeout;
183};
184
185
186/* Variable Screen Information */
187static struct fb_var_screeninfo da8xx_fb_var = {
188 .xoffset = 0,
189 .yoffset = 0,
190 .transp = {0, 0, 0},
191 .nonstd = 0,
192 .activate = 0,
193 .height = -1,
194 .width = -1,
195 .pixclock = 46666, /* 46us - AUO display */
196 .accel_flags = 0,
197 .left_margin = LEFT_MARGIN,
198 .right_margin = RIGHT_MARGIN,
199 .upper_margin = UPPER_MARGIN,
200 .lower_margin = LOWER_MARGIN,
201 .sync = 0,
202 .vmode = FB_VMODE_NONINTERLACED
203};
204
205static struct fb_fix_screeninfo da8xx_fb_fix = {
206 .id = "DA8xx FB Drv",
207 .type = FB_TYPE_PACKED_PIXELS,
208 .type_aux = 0,
209 .visual = FB_VISUAL_PSEUDOCOLOR,
210 .xpanstep = 0,
211 .ypanstep = 1,
212 .ywrapstep = 0,
213 .accel = FB_ACCEL_NONE
214};
215
13402868
SB		 216/* Enable the Raster Engine of the LCD Controller */
217static inline void lcd_enable_raster(void)
218{
219 u32 reg;
220
765f2f08
HS		 221 /* Put LCDC in reset for several cycles */
222 if (lcd_revision == LCD_VERSION_2)
223 lcdc_write(LCD_CLK_MAIN_RESET,
224 &da8xx_fb_reg_base->clk_reset);
225
226 udelay(1000);
227 /* Bring LCDC out of reset */
228 if (lcd_revision == LCD_VERSION_2)
229 lcdc_write(0,
230 &da8xx_fb_reg_base->clk_reset);
231
232 udelay(1000);
233
13402868
SB		 234 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
235 if (!(reg & LCD_RASTER_ENABLE))
236 lcdc_write(reg | LCD_RASTER_ENABLE,
237 &da8xx_fb_reg_base->raster_ctrl);
238}
239
240/* Disable the Raster Engine of the LCD Controller */
765f2f08 241static inline void lcd_disable_raster(bool wait_for_frame_done)
13402868
SB		 242{
243 u32 reg;
765f2f08
HS		 244 u32 loop_cnt = 0;
245 u32 stat;
246 u32 i = 0;
247
248 if (wait_for_frame_done)
249 loop_cnt = 5000;
13402868
SB		 250
251 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
252 if (reg & LCD_RASTER_ENABLE)
253 lcdc_write(reg & ~LCD_RASTER_ENABLE,
254 &da8xx_fb_reg_base->raster_ctrl);
765f2f08
HS		 255
256 /* Wait for the current frame to complete */
257 do {
258 if (lcd_revision == LCD_VERSION_1)
259 stat = lcdc_read(&da8xx_fb_reg_base->stat);
260 else
261 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
262
263 mdelay(1);
264 } while (!(stat & 0x01) && (i++ < loop_cnt));
265
266 if (lcd_revision == LCD_VERSION_1)
267 lcdc_write(stat, &da8xx_fb_reg_base->stat);
268 else
269 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
270
271 if ((loop_cnt != 0) && (i >= loop_cnt)) {
272 printf("LCD Controller timed out\n");
273 return;
274 }
13402868
SB		 275}
276
277static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
278{
279 u32 start;
280 u32 end;
281 u32 reg_ras;
282 u32 reg_dma;
765f2f08 283 u32 reg_int;
13402868
SB		 284
285 /* init reg to clear PLM (loading mode) fields */
286 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
287 reg_ras &= ~(3 << 20);
288
289 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
290
291 if (load_mode == LOAD_DATA) {
292 start = par->dma_start;
293 end = par->dma_end;
294
295 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
765f2f08
HS		 296 if (lcd_revision == LCD_VERSION_1) {
297 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
298 } else {
299 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
300 LCD_V2_END_OF_FRAME0_INT_ENA |
301 LCD_V2_END_OF_FRAME1_INT_ENA |
302 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
303 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
304 }
13402868
SB		 305
306#if (LCD_NUM_BUFFERS == 2)
307 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
308 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
309 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
310 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
311 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
312#else
313 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
314 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
315 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
316 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
317 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
318#endif
319
320 } else if (load_mode == LOAD_PALETTE) {
321 start = par->p_palette_base;
322 end = start + par->palette_sz - 1;
323
324 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
765f2f08
HS		 325 if (lcd_revision == LCD_VERSION_1) {
326 reg_ras |= LCD_V1_PL_INT_ENA;
327 } else {
328 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
329 LCD_V2_PL_INT_ENA;
330 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
331 }
13402868
SB		 332
333 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
334 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
335 }
336
337 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
338 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
339
340 /*
341 * The Raster enable bit must be set after all other control fields are
342 * set.
343 */
344 lcd_enable_raster();
345}
346
347/* Configure the Burst Size of DMA */
348static int lcd_cfg_dma(int burst_size)
349{
350 u32 reg;
351
352 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
353 switch (burst_size) {
354 case 1:
355 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
356 break;
357 case 2:
358 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
359 break;
360 case 4:
361 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
362 break;
363 case 8:
364 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
365 break;
366 case 16:
367 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
368 break;
369 default:
370 return -EINVAL;
371 }
372 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
373
374 return 0;
375}
376
377static void lcd_cfg_ac_bias(int period, int transitions_per_int)
378{
379 u32 reg;
380
535cce0f 381 /* Set the AC Bias Period and Number of Transitions per Interrupt */
13402868
SB		 382 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
383 reg |= LCD_AC_BIAS_FREQUENCY(period) |
384 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
385 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
386}
387
388static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
389 int front_porch)
390{
391 u32 reg;
392
393 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
394 reg |= ((back_porch & 0xff) << 24)
395 | ((front_porch & 0xff) << 16)
396 | ((pulse_width & 0x3f) << 10);
397 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
398}
399
400static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
401 int front_porch)
402{
403 u32 reg;
404
405 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
406 reg |= ((back_porch & 0xff) << 24)
407 | ((front_porch & 0xff) << 16)
408 | ((pulse_width & 0x3f) << 10);
409 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
410}
411
412static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
413{
414 u32 reg;
765f2f08 415 u32 reg_int;
13402868
SB		 416
417 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
418 LCD_MONO_8BIT_MODE |
419 LCD_MONOCHROME_MODE);
420
421 switch (cfg->p_disp_panel->panel_shade) {
422 case MONOCHROME:
423 reg |= LCD_MONOCHROME_MODE;
424 if (cfg->mono_8bit_mode)
425 reg |= LCD_MONO_8BIT_MODE;
426 break;
427 case COLOR_ACTIVE:
428 reg |= LCD_TFT_MODE;
429 if (cfg->tft_alt_mode)
430 reg |= LCD_TFT_ALT_ENABLE;
431 break;
432
433 case COLOR_PASSIVE:
434 if (cfg->stn_565_mode)
435 reg |= LCD_STN_565_ENABLE;
436 break;
437
438 default:
439 return -EINVAL;
440 }
441
442 /* enable additional interrupts here */
765f2f08
HS		 443 if (lcd_revision == LCD_VERSION_1) {
444 reg |= LCD_V1_UNDERFLOW_INT_ENA;
445 } else {
446 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
447 LCD_V2_UNDERFLOW_INT_ENA;
448 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
449 }
13402868
SB		 450
451 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
452
453 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
454
455 if (cfg->sync_ctrl)
456 reg |= LCD_SYNC_CTRL;
457 else
458 reg &= ~LCD_SYNC_CTRL;
459
460 if (cfg->sync_edge)
461 reg |= LCD_SYNC_EDGE;
462 else
463 reg &= ~LCD_SYNC_EDGE;
464
465 if (cfg->invert_line_clock)
466 reg |= LCD_INVERT_LINE_CLOCK;
467 else
468 reg &= ~LCD_INVERT_LINE_CLOCK;
469
470 if (cfg->invert_frm_clock)
471 reg |= LCD_INVERT_FRAME_CLOCK;
472 else
473 reg &= ~LCD_INVERT_FRAME_CLOCK;
474
475 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
476
477 return 0;
478}
479
480static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
481 u32 bpp, u32 raster_order)
482{
483 u32 reg;
484
485 /* Set the Panel Width */
486 /* Pixels per line = (PPL + 1)*16 */
765f2f08
HS		 487 if (lcd_revision == LCD_VERSION_1) {
488 /*
535cce0f 489 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
765f2f08
HS		 490 * pixels
491 */
492 width &= 0x3f0;
493 } else {
494 /*
495 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
496 * pixels.
497 */
498 width &= 0x7f0;
499 }
13402868
SB		 500 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
501 reg &= 0xfffffc00;
765f2f08
HS		 502 if (lcd_revision == LCD_VERSION_1) {
503 reg |= ((width >> 4) - 1) << 4;
504 } else {
505 width = (width >> 4) - 1;
506 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
507 }
13402868
SB		 508 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
509
510 /* Set the Panel Height */
765f2f08 511 /* Set bits 9:0 of Lines Per Pixel */
13402868
SB		 512 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
513 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
514 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
515
765f2f08
HS		 516 /* Set bit 10 of Lines Per Pixel */
517 if (lcd_revision == LCD_VERSION_2) {
518 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
519 reg |= ((height - 1) & 0x400) << 16;
520 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
521 }
522
13402868
SB		 523 /* Set the Raster Order of the Frame Buffer */
524 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
525 if (raster_order)
526 reg |= LCD_RASTER_ORDER;
765f2f08
HS		 527
528 if (bpp == 24)
529 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
530 else if (bpp == 32)
531 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
532 | LCD_V2_TFT_24BPP_UNPACK);
533
13402868
SB		 534 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
535
536 switch (bpp) {
537 case 1:
538 case 2:
539 case 4:
540 case 16:
765f2f08
HS		 541 case 24:
542 case 32:
13402868
SB		 543 par->palette_sz = 16 * 2;
544 break;
545
546 case 8:
547 par->palette_sz = 256 * 2;
548 break;
549
550 default:
551 return -EINVAL;
552 }
553
554 return 0;
555}
556
557static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
558 unsigned blue, unsigned transp,
559 struct fb_info *info)
560{
561 struct da8xx_fb_par *par = info->par;
562 unsigned short *palette = (unsigned short *) par->v_palette_base;
563 u_short pal;
564 int update_hw = 0;
565
566 if (regno > 255)
567 return 1;
568
569 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
570 return 1;
571
572 if (info->var.bits_per_pixel == 8) {
573 red >>= 4;
574 green >>= 8;
575 blue >>= 12;
576
577 pal = (red & 0x0f00);
578 pal |= (green & 0x00f0);
579 pal |= (blue & 0x000f);
580
581 if (palette[regno] != pal) {
582 update_hw = 1;
583 palette[regno] = pal;
584 }
585 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
586 red >>= (16 - info->var.red.length);
587 red <<= info->var.red.offset;
588
589 green >>= (16 - info->var.green.length);
590 green <<= info->var.green.offset;
591
592 blue >>= (16 - info->var.blue.length);
593 blue <<= info->var.blue.offset;
594
595 par->pseudo_palette[regno] = red | green | blue;
596
765f2f08
HS		 597 if (palette[0] != 0x4000) {
598 update_hw = 1;
599 palette[0] = 0x4000;
600 }
601 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
602 ((info->var.bits_per_pixel == 24) && regno < 24)) {
603 red >>= (24 - info->var.red.length);
604 red <<= info->var.red.offset;
605
606 green >>= (24 - info->var.green.length);
607 green <<= info->var.green.offset;
608
609 blue >>= (24 - info->var.blue.length);
610 blue <<= info->var.blue.offset;
611
612 par->pseudo_palette[regno] = red | green | blue;
613
13402868
SB		 614 if (palette[0] != 0x4000) {
615 update_hw = 1;
616 palette[0] = 0x4000;
617 }
618 }
619
620 /* Update the palette in the h/w as needed. */
621 if (update_hw)
622 lcd_blit(LOAD_PALETTE, par);
623
624 return 0;
625}
626
627static void lcd_reset(struct da8xx_fb_par *par)
628{
629 /* Disable the Raster if previously Enabled */
765f2f08 630 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
13402868
SB		 631
632 /* DMA has to be disabled */
633 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
634 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
765f2f08
HS		 635
636 if (lcd_revision == LCD_VERSION_2) {
637 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
638 /* Write 1 to reset */
639 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
640 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
641 }
13402868
SB		 642}
643
644static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
645{
646 unsigned int lcd_clk, div;
647
648 /* Get clock from sysclk2 */
649 lcd_clk = clk_get(2);
650
651 div = lcd_clk / par->pxl_clk;
765f2f08
HS		 652 debug("LCD Clock: %d Divider: %d PixClk: %d\n",
653 lcd_clk, div, par->pxl_clk);
13402868
SB		 654
655 /* Configure the LCD clock divisor. */
656 lcdc_write(LCD_CLK_DIVISOR(div) |
657 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
765f2f08
HS		 658
659 if (lcd_revision == LCD_VERSION_2)
660 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
661 LCD_V2_CORE_CLK_EN,
662 &da8xx_fb_reg_base->clk_ena);
13402868
SB		 663}
664
665static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
666 const struct da8xx_panel *panel)
667{
668 u32 bpp;
669 int ret = 0;
670
671 lcd_reset(par);
672
673 /* Calculate the divider */
674 lcd_calc_clk_divider(par);
675
676 if (panel->invert_pxl_clk)
677 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
678 LCD_INVERT_PIXEL_CLOCK),
679 &da8xx_fb_reg_base->raster_timing_2);
680 else
681 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
682 ~LCD_INVERT_PIXEL_CLOCK),
683 &da8xx_fb_reg_base->raster_timing_2);
684
685 /* Configure the DMA burst size. */
686 ret = lcd_cfg_dma(cfg->dma_burst_sz);
687 if (ret < 0)
688 return ret;
689
690 /* Configure the AC bias properties. */
691 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
692
693 /* Configure the vertical and horizontal sync properties. */
694 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
695 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
696
535cce0f 697 /* Configure for display */
13402868
SB		 698 ret = lcd_cfg_display(cfg);
699 if (ret < 0)
700 return ret;
701
765f2f08
HS		 702 if ((QVGA != cfg->p_disp_panel->panel_type) &&
703 (WVGA != cfg->p_disp_panel->panel_type))
13402868
SB		 704 return -EINVAL;
705
706 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
707 cfg->bpp >= cfg->p_disp_panel->min_bpp)
708 bpp = cfg->bpp;
709 else
710 bpp = cfg->p_disp_panel->max_bpp;
711 if (bpp == 12)
712 bpp = 16;
713 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
714 (unsigned int)panel->height, bpp,
715 cfg->raster_order);
716 if (ret < 0)
717 return ret;
718
719 /* Configure FDD */
720 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
721 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
722
723 return 0;
724}
725
726static void lcdc_dma_start(void)
727{
728 struct da8xx_fb_par *par = da8xx_fb_info->par;
729 lcdc_write(par->dma_start,
730 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
731 lcdc_write(par->dma_end,
732 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
733 lcdc_write(0,
734 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
735 lcdc_write(0,
736 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
737}
738
765f2f08 739static u32 lcdc_irq_handler_rev01(void)
13402868
SB		 740{
741 struct da8xx_fb_par *par = da8xx_fb_info->par;
742 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
743 u32 reg_ras;
744
745 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
746 debug("LCD_SYNC_LOST\n");
765f2f08 747 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
13402868
SB		 748 lcdc_write(stat, &da8xx_fb_reg_base->stat);
749 lcd_enable_raster();
750 return LCD_SYNC_LOST;
751 } else if (stat & LCD_PL_LOAD_DONE) {
752 debug("LCD_PL_LOAD_DONE\n");
753 /*
754 * Must disable raster before changing state of any control bit.
755 * And also must be disabled before clearing the PL loading
756 * interrupt via the following write to the status register. If
757 * this is done after then one gets multiple PL done interrupts.
758 */
765f2f08 759 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
13402868
SB		 760
761 lcdc_write(stat, &da8xx_fb_reg_base->stat);
762
535cce0f 763 /* Disable PL completion interrupt */
13402868 764 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
765f2f08 765 reg_ras &= ~LCD_V1_PL_INT_ENA;
13402868
SB		 766 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
767
768 /* Setup and start data loading mode */
769 lcd_blit(LOAD_DATA, par);
770 return LCD_PL_LOAD_DONE;
771 } else {
772 lcdc_write(stat, &da8xx_fb_reg_base->stat);
773
774 if (stat & LCD_END_OF_FRAME0)
775 debug("LCD_END_OF_FRAME0\n");
776
777 lcdc_write(par->dma_start,
778 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
779 lcdc_write(par->dma_end,
780 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
781 par->vsync_flag = 1;
782 return LCD_END_OF_FRAME0;
783 }
784 return stat;
785}
786
765f2f08
HS		 787static u32 lcdc_irq_handler_rev02(void)
788{
789 struct da8xx_fb_par *par = da8xx_fb_info->par;
790 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
791 u32 reg_int;
792
793 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
794 debug("LCD_SYNC_LOST\n");
795 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
796 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
797 lcd_enable_raster();
798 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
799 return LCD_SYNC_LOST;
800 } else if (stat & LCD_PL_LOAD_DONE) {
801 debug("LCD_PL_LOAD_DONE\n");
802 /*
803 * Must disable raster before changing state of any control bit.
804 * And also must be disabled before clearing the PL loading
805 * interrupt via the following write to the status register. If
806 * this is done after then one gets multiple PL done interrupts.
807 */
808 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
809
810 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
811
535cce0f 812 /* Disable PL completion interrupt */
765f2f08
HS		 813 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
814 (LCD_V2_PL_INT_ENA);
815 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
816
817 /* Setup and start data loading mode */
818 lcd_blit(LOAD_DATA, par);
819 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
820 return LCD_PL_LOAD_DONE;
821 } else {
822 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
823
824 if (stat & LCD_END_OF_FRAME0)
825 debug("LCD_END_OF_FRAME0\n");
826
827 lcdc_write(par->dma_start,
828 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
829 lcdc_write(par->dma_end,
830 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
831 par->vsync_flag = 1;
832 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
833 return LCD_END_OF_FRAME0;
834 }
835 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
836 return stat;
837}
838
839static u32 lcdc_irq_handler(void)
840{
841 if (lcd_revision == LCD_VERSION_1)
842 return lcdc_irq_handler_rev01();
843 else
844 return lcdc_irq_handler_rev02();
845}
846
13402868
SB		 847static u32 wait_for_event(u32 event)
848{
849 u32 timeout = 50000;
850 u32 ret;
851
852 do {
853 ret = lcdc_irq_handler();
854 udelay(1000);
c16b342d
HS		 855 --timeout;
856 } while (!(ret & event) && timeout);
13402868 857
c16b342d 858 if (!(ret & event)) {
13402868
SB		 859 printf("%s: event %d not hit\n", __func__, event);
860 return -1;
861 }
862
863 return 0;
864
865}
866
867void *video_hw_init(void)
868{
869 struct da8xx_fb_par *par;
13402868 870 u32 size;
765f2f08 871 u32 rev;
13402868
SB		 872 char *p;
873
874 if (!lcd_panel) {
875 printf("Display not initialized\n");
876 return NULL;
877 }
878 gpanel.winSizeX = lcd_panel->width;
879 gpanel.winSizeY = lcd_panel->height;
880 gpanel.plnSizeX = lcd_panel->width;
881 gpanel.plnSizeY = lcd_panel->height;
882
883 switch (bits_x_pixel) {
765f2f08
HS		 884 case 32:
885 gpanel.gdfBytesPP = 4;
886 gpanel.gdfIndex = GDF_32BIT_X888RGB;
887 break;
13402868
SB		 888 case 24:
889 gpanel.gdfBytesPP = 4;
890 gpanel.gdfIndex = GDF_32BIT_X888RGB;
891 break;
892 case 16:
893 gpanel.gdfBytesPP = 2;
894 gpanel.gdfIndex = GDF_16BIT_565RGB;
895 break;
896 default:
897 gpanel.gdfBytesPP = 1;
898 gpanel.gdfIndex = GDF__8BIT_INDEX;
899 break;
900 }
901
765f2f08
HS		 902 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
903
904 /* Determine LCD IP Version */
905 rev = lcdc_read(&da8xx_fb_reg_base->revid);
906 switch (rev) {
907 case 0x4C100102:
908 lcd_revision = LCD_VERSION_1;
909 break;
910 case 0x4F200800:
911 case 0x4F201000:
912 lcd_revision = LCD_VERSION_2;
913 break;
914 default:
915 printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
916 rev);
917 lcd_revision = LCD_VERSION_1;
918 break;
919 }
13402868 920
765f2f08
HS		 921 debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
922 gpanel.winSizeX,
923 gpanel.winSizeY,
924 da8xx_lcd_cfg->bpp);
13402868
SB		 925
926 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
963be689 927 da8xx_fb_info = malloc_cache_aligned(size);
13402868
SB		 928 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
929
930 if (!da8xx_fb_info) {
931 printf("Memory allocation failed for fb_info\n");
932 return NULL;
933 }
934 memset(da8xx_fb_info, 0, size);
935 p = (char *)da8xx_fb_info;
936 da8xx_fb_info->par = p + sizeof(struct fb_info);
937 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
938
939 par = da8xx_fb_info->par;
940 par->pxl_clk = lcd_panel->pxl_clk;
941
765f2f08 942 if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
13402868 943 printf("lcd_init failed\n");
13402868
SB		 944 goto err_release_fb;
945 }
946
947 /* allocate frame buffer */
765f2f08
HS		 948 par->vram_size = lcd_panel->width * lcd_panel->height *
949 da8xx_lcd_cfg->bpp;
13402868
SB		 950 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
951
963be689 952 par->vram_virt = malloc_cache_aligned(par->vram_size);
13402868
SB		 953
954 par->vram_phys = (dma_addr_t) par->vram_virt;
955 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
956 (unsigned int)par->vram_size,
957 (unsigned int)par->vram_virt);
958 if (!par->vram_virt) {
959 printf("GLCD: malloc for frame buffer failed\n");
13402868
SB		 960 goto err_release_fb;
961 }
4e023626 962 gd->fb_base = (int)par->vram_virt;
13402868
SB		 963
964 gpanel.frameAdrs = (unsigned int)par->vram_virt;
965 da8xx_fb_info->screen_base = (char *) par->vram_virt;
966 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
967 da8xx_fb_fix.smem_len = par->vram_size;
765f2f08 968 da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
13402868
SB		 969
970 par->dma_start = par->vram_phys;
971 par->dma_end = par->dma_start + lcd_panel->height *
972 da8xx_fb_fix.line_length - 1;
973
974 /* allocate palette buffer */
963be689 975 par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
13402868
SB		 976 if (!par->v_palette_base) {
977 printf("GLCD: malloc for palette buffer failed\n");
978 goto err_release_fb_mem;
979 }
980 memset(par->v_palette_base, 0, PALETTE_SIZE);
981 par->p_palette_base = (unsigned int)par->v_palette_base;
982
983 /* Initialize par */
765f2f08 984 da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
13402868
SB		 985
986 da8xx_fb_var.xres = lcd_panel->width;
987 da8xx_fb_var.xres_virtual = lcd_panel->width;
988
989 da8xx_fb_var.yres = lcd_panel->height;
990 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
991
992 da8xx_fb_var.grayscale =
765f2f08
HS		 993 da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
994 da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
13402868
SB		 995
996 da8xx_fb_var.hsync_len = lcd_panel->hsw;
997 da8xx_fb_var.vsync_len = lcd_panel->vsw;
998
999 /* Initialize fbinfo */
1000 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1001 da8xx_fb_info->fix = da8xx_fb_fix;
1002 da8xx_fb_info->var = da8xx_fb_var;
1003 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1004 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1005 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1006
1007 /* Clear interrupt */
1008 memset((void *)par->vram_virt, 0, par->vram_size);
765f2f08
HS		 1009 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1010 if (lcd_revision == LCD_VERSION_1)
1011 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1012 else
1013 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
13402868
SB		 1014 debug("Palette at 0x%x size %d\n", par->p_palette_base,
1015 par->palette_sz);
1016 lcdc_dma_start();
1017
1018 /* Load a default palette */
1019 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1020
1021 /* Check that the palette is loaded */
1022 wait_for_event(LCD_PL_LOAD_DONE);
1023
1024 /* Wait until DMA is working */
1025 wait_for_event(LCD_END_OF_FRAME0);
1026
1027 return (void *)&gpanel;
1028
1029err_release_fb_mem:
1030 free(par->vram_virt);
1031
1032err_release_fb:
1033 free(da8xx_fb_info);
1034
1035 return NULL;
1036}
1037
765f2f08
HS		 1038void da8xx_video_init(const struct da8xx_panel *panel,
1039 const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
13402868
SB		 1040{
1041 lcd_panel = panel;
765f2f08 1042 da8xx_lcd_cfg = lcd_cfg;
13402868
SB		 1043 bits_x_pixel = bits_pixel;
1044}
"Das U-Boot" Source Tree