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d2a6982f DL |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics | |
3 | * | |
4 | * Author: Donghwa Lee <dh09.lee@samsung.com> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
d2a6982f DL |
7 | */ |
8 | ||
9 | #include <config.h> | |
10 | #include <common.h> | |
11 | #include <malloc.h> | |
0c06db59 | 12 | #include <linux/compat.h> |
d2a6982f DL |
13 | #include <linux/err.h> |
14 | #include <asm/arch/clk.h> | |
15 | #include <asm/arch/cpu.h> | |
16 | #include <asm/arch/dp_info.h> | |
17 | #include <asm/arch/dp.h> | |
9947d13e AK |
18 | #include <fdtdec.h> |
19 | #include <libfdt.h> | |
d2a6982f DL |
20 | |
21 | #include "exynos_dp_lowlevel.h" | |
22 | ||
9947d13e AK |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
d2a6982f DL |
25 | static struct exynos_dp_platform_data *dp_pd; |
26 | ||
c18222be AK |
27 | void __exynos_set_dp_phy(unsigned int onoff) |
28 | { | |
29 | } | |
30 | void exynos_set_dp_phy(unsigned int onoff) | |
31 | __attribute__((weak, alias("__exynos_set_dp_phy"))); | |
32 | ||
d2a6982f DL |
33 | static void exynos_dp_disp_info(struct edp_disp_info *disp_info) |
34 | { | |
35 | disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + | |
36 | disp_info->h_back_porch + disp_info->h_front_porch; | |
37 | disp_info->v_total = disp_info->v_res + disp_info->v_sync_width + | |
38 | disp_info->v_back_porch + disp_info->v_front_porch; | |
39 | ||
40 | return; | |
41 | } | |
42 | ||
43 | static int exynos_dp_init_dp(void) | |
44 | { | |
45 | int ret; | |
46 | exynos_dp_reset(); | |
47 | ||
48 | /* SW defined function Normal operation */ | |
49 | exynos_dp_enable_sw_func(DP_ENABLE); | |
50 | ||
51 | ret = exynos_dp_init_analog_func(); | |
52 | if (ret != EXYNOS_DP_SUCCESS) | |
53 | return ret; | |
54 | ||
55 | exynos_dp_init_hpd(); | |
56 | exynos_dp_init_aux(); | |
57 | ||
58 | return ret; | |
59 | } | |
60 | ||
61 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) | |
62 | { | |
63 | int i; | |
64 | unsigned char sum = 0; | |
65 | ||
66 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) | |
67 | sum = sum + edid_data[i]; | |
68 | ||
69 | return sum; | |
70 | } | |
71 | ||
72 | static unsigned int exynos_dp_read_edid(void) | |
73 | { | |
74 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; | |
75 | unsigned int extend_block = 0; | |
76 | unsigned char sum; | |
77 | unsigned char test_vector; | |
78 | int retval; | |
79 | ||
80 | /* | |
81 | * EDID device address is 0x50. | |
82 | * However, if necessary, you must have set upper address | |
83 | * into E-EDID in I2C device, 0x30. | |
84 | */ | |
85 | ||
86 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ | |
87 | exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, | |
88 | &extend_block); | |
89 | ||
90 | if (extend_block > 0) { | |
91 | printf("DP EDID data includes a single extension!\n"); | |
92 | ||
93 | /* Read EDID data */ | |
94 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, | |
95 | EDID_HEADER_PATTERN, | |
96 | EDID_BLOCK_LENGTH, | |
97 | &edid[EDID_HEADER_PATTERN]); | |
98 | if (retval != 0) { | |
99 | printf("DP EDID Read failed!\n"); | |
100 | return -1; | |
101 | } | |
102 | sum = exynos_dp_calc_edid_check_sum(edid); | |
103 | if (sum != 0) { | |
104 | printf("DP EDID bad checksum!\n"); | |
105 | return -1; | |
106 | } | |
107 | ||
108 | /* Read additional EDID data */ | |
109 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, | |
110 | EDID_BLOCK_LENGTH, | |
111 | EDID_BLOCK_LENGTH, | |
112 | &edid[EDID_BLOCK_LENGTH]); | |
113 | if (retval != 0) { | |
114 | printf("DP EDID Read failed!\n"); | |
115 | return -1; | |
116 | } | |
117 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); | |
118 | if (sum != 0) { | |
119 | printf("DP EDID bad checksum!\n"); | |
120 | return -1; | |
121 | } | |
122 | ||
123 | exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, | |
124 | &test_vector); | |
125 | if (test_vector & DPCD_TEST_EDID_READ) { | |
126 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, | |
127 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); | |
128 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, | |
129 | DPCD_TEST_EDID_CHECKSUM_WRITE); | |
130 | } | |
131 | } else { | |
132 | debug("DP EDID data does not include any extensions.\n"); | |
133 | ||
134 | /* Read EDID data */ | |
135 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, | |
136 | EDID_HEADER_PATTERN, | |
137 | EDID_BLOCK_LENGTH, | |
138 | &edid[EDID_HEADER_PATTERN]); | |
139 | ||
140 | if (retval != 0) { | |
141 | printf("DP EDID Read failed!\n"); | |
142 | return -1; | |
143 | } | |
144 | sum = exynos_dp_calc_edid_check_sum(edid); | |
145 | if (sum != 0) { | |
146 | printf("DP EDID bad checksum!\n"); | |
147 | return -1; | |
148 | } | |
149 | ||
150 | exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, | |
151 | &test_vector); | |
152 | if (test_vector & DPCD_TEST_EDID_READ) { | |
153 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, | |
154 | edid[EDID_CHECKSUM]); | |
155 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, | |
156 | DPCD_TEST_EDID_CHECKSUM_WRITE); | |
157 | } | |
158 | } | |
159 | ||
160 | debug("DP EDID Read success!\n"); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info) | |
166 | { | |
167 | unsigned char buf[12]; | |
168 | unsigned int ret; | |
169 | unsigned char temp; | |
170 | unsigned char retry_cnt; | |
171 | unsigned char dpcd_rev[16]; | |
172 | unsigned char lane_bw[16]; | |
173 | unsigned char lane_cnt[16]; | |
174 | ||
175 | memset(dpcd_rev, 0, 16); | |
176 | memset(lane_bw, 0, 16); | |
177 | memset(lane_cnt, 0, 16); | |
178 | memset(buf, 0, 12); | |
179 | ||
180 | retry_cnt = 5; | |
181 | while (retry_cnt) { | |
182 | /* Read DPCD 0x0000-0x000b */ | |
183 | ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12, | |
184 | buf); | |
185 | if (ret != EXYNOS_DP_SUCCESS) { | |
186 | if (retry_cnt == 0) { | |
187 | printf("DP read_byte_from_dpcd() failed\n"); | |
188 | return ret; | |
189 | } | |
190 | retry_cnt--; | |
191 | } else | |
192 | break; | |
193 | } | |
194 | ||
195 | /* */ | |
196 | temp = buf[DPCD_DPCD_REV]; | |
197 | if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) | |
198 | edp_info->dpcd_rev = temp; | |
199 | else { | |
200 | printf("DP Wrong DPCD Rev : %x\n", temp); | |
201 | return -ENODEV; | |
202 | } | |
203 | ||
204 | temp = buf[DPCD_MAX_LINK_RATE]; | |
205 | if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) | |
206 | edp_info->lane_bw = temp; | |
207 | else { | |
208 | printf("DP Wrong MAX LINK RATE : %x\n", temp); | |
209 | return -EINVAL; | |
210 | } | |
211 | ||
212 | /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */ | |
213 | if (edp_info->dpcd_rev == DP_DPCD_REV_11) { | |
214 | temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; | |
215 | if (buf[DPCD_MAX_LANE_COUNT] & 0x80) | |
216 | edp_info->dpcd_efc = 1; | |
217 | else | |
218 | edp_info->dpcd_efc = 0; | |
219 | } else { | |
220 | temp = buf[DPCD_MAX_LANE_COUNT]; | |
221 | edp_info->dpcd_efc = 0; | |
222 | } | |
223 | ||
224 | if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || | |
225 | temp == DP_LANE_CNT_4) { | |
226 | edp_info->lane_cnt = temp; | |
227 | } else { | |
228 | printf("DP Wrong MAX LANE COUNT : %x\n", temp); | |
229 | return -EINVAL; | |
230 | } | |
231 | ||
232 | ret = exynos_dp_read_edid(); | |
233 | if (ret != EXYNOS_DP_SUCCESS) { | |
234 | printf("DP exynos_dp_read_edid() failed\n"); | |
235 | return -EINVAL; | |
236 | } | |
237 | ||
238 | return ret; | |
239 | } | |
240 | ||
241 | static void exynos_dp_init_training(void) | |
242 | { | |
243 | /* | |
244 | * MACRO_RST must be applied after the PLL_LOCK to avoid | |
245 | * the DP inter pair skew issue for at least 10 us | |
246 | */ | |
247 | exynos_dp_reset_macro(); | |
248 | ||
249 | /* All DP analog module power up */ | |
250 | exynos_dp_set_analog_power_down(POWER_ALL, 0); | |
251 | } | |
252 | ||
253 | static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info) | |
254 | { | |
255 | unsigned char buf[5]; | |
256 | unsigned int ret = 0; | |
257 | ||
258 | debug("DP: %s was called\n", __func__); | |
259 | ||
260 | edp_info->lt_info.lt_status = DP_LT_CR; | |
261 | edp_info->lt_info.ep_loop = 0; | |
262 | edp_info->lt_info.cr_loop[0] = 0; | |
263 | edp_info->lt_info.cr_loop[1] = 0; | |
264 | edp_info->lt_info.cr_loop[2] = 0; | |
265 | edp_info->lt_info.cr_loop[3] = 0; | |
266 | ||
267 | /* Set sink to D0 (Sink Not Ready) mode. */ | |
268 | ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE, | |
269 | DPCD_SET_POWER_STATE_D0); | |
270 | if (ret != EXYNOS_DP_SUCCESS) { | |
271 | printf("DP write_dpcd_byte failed\n"); | |
272 | return ret; | |
273 | } | |
274 | ||
275 | /* Set link rate and count as you want to establish*/ | |
276 | exynos_dp_set_link_bandwidth(edp_info->lane_bw); | |
277 | exynos_dp_set_lane_count(edp_info->lane_cnt); | |
278 | ||
279 | /* Setup RX configuration */ | |
280 | buf[0] = edp_info->lane_bw; | |
281 | buf[1] = edp_info->lane_cnt; | |
282 | ||
283 | ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2, | |
284 | buf); | |
285 | if (ret != EXYNOS_DP_SUCCESS) { | |
286 | printf("DP write_dpcd_byte failed\n"); | |
287 | return ret; | |
288 | } | |
289 | ||
290 | exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0, | |
291 | edp_info->lane_cnt); | |
292 | ||
293 | /* Set training pattern 1 */ | |
294 | exynos_dp_set_training_pattern(TRAINING_PTN1); | |
295 | ||
296 | /* Set RX training pattern */ | |
297 | buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; | |
298 | ||
299 | buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | | |
300 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; | |
301 | buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | | |
302 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; | |
303 | buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | | |
304 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; | |
305 | buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | | |
306 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; | |
307 | ||
308 | ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET, | |
309 | 5, buf); | |
310 | if (ret != EXYNOS_DP_SUCCESS) { | |
311 | printf("DP write_dpcd_byte failed\n"); | |
312 | return ret; | |
313 | } | |
314 | ||
315 | return ret; | |
316 | } | |
317 | ||
318 | static unsigned int exynos_dp_training_pattern_dis(void) | |
319 | { | |
320 | unsigned int ret = EXYNOS_DP_SUCCESS; | |
321 | ||
322 | exynos_dp_set_training_pattern(DP_NONE); | |
323 | ||
324 | ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, | |
325 | DPCD_TRAINING_PATTERN_DISABLED); | |
326 | if (ret != EXYNOS_DP_SUCCESS) { | |
327 | printf("DP requst_link_traninig_req failed\n"); | |
328 | return -EAGAIN; | |
329 | } | |
330 | ||
331 | return ret; | |
332 | } | |
333 | ||
334 | static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) | |
335 | { | |
336 | unsigned char data; | |
337 | unsigned int ret = EXYNOS_DP_SUCCESS; | |
338 | ||
339 | ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET, | |
340 | &data); | |
341 | if (ret != EXYNOS_DP_SUCCESS) { | |
342 | printf("DP read_from_dpcd failed\n"); | |
343 | return -EAGAIN; | |
344 | } | |
345 | ||
346 | if (enable) | |
347 | data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data); | |
348 | else | |
349 | data = DPCD_LN_COUNT_SET(data); | |
350 | ||
351 | ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, | |
352 | data); | |
353 | if (ret != EXYNOS_DP_SUCCESS) { | |
354 | printf("DP write_to_dpcd failed\n"); | |
355 | return -EAGAIN; | |
356 | ||
357 | } | |
358 | ||
359 | return ret; | |
360 | } | |
361 | ||
362 | static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode) | |
363 | { | |
364 | unsigned int ret = EXYNOS_DP_SUCCESS; | |
365 | ||
366 | ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode); | |
367 | if (ret != EXYNOS_DP_SUCCESS) { | |
368 | printf("DP rx_enhance_mode failed\n"); | |
369 | return -EAGAIN; | |
370 | } | |
371 | ||
372 | exynos_dp_enable_enhanced_mode(enhance_mode); | |
373 | ||
374 | return ret; | |
375 | } | |
376 | ||
377 | static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info, | |
378 | unsigned char *status) | |
379 | { | |
380 | unsigned int ret, i; | |
381 | unsigned char buf[2]; | |
382 | unsigned char lane_stat[DP_LANE_CNT_4] = {0,}; | |
383 | unsigned char shift_val[DP_LANE_CNT_4] = {0,}; | |
384 | ||
385 | shift_val[0] = 0; | |
386 | shift_val[1] = 4; | |
387 | shift_val[2] = 0; | |
388 | shift_val[3] = 4; | |
389 | ||
390 | ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf); | |
391 | if (ret != EXYNOS_DP_SUCCESS) { | |
392 | printf("DP read lane status failed\n"); | |
393 | return ret; | |
394 | } | |
395 | ||
396 | for (i = 0; i < edp_info->lane_cnt; i++) { | |
397 | lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; | |
398 | if (lane_stat[0] != lane_stat[i]) { | |
399 | printf("Wrong lane status\n"); | |
400 | return -EINVAL; | |
401 | } | |
402 | } | |
403 | ||
404 | *status = lane_stat[0]; | |
405 | ||
406 | return ret; | |
407 | } | |
408 | ||
409 | static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num, | |
410 | unsigned char *sw, unsigned char *em) | |
411 | { | |
412 | unsigned int ret = EXYNOS_DP_SUCCESS; | |
413 | unsigned char buf; | |
414 | unsigned int dpcd_addr; | |
415 | unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; | |
416 | ||
417 | /*lane_num value is used as arry index, so this range 0 ~ 3 */ | |
418 | dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); | |
419 | ||
420 | ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf); | |
421 | if (ret != EXYNOS_DP_SUCCESS) { | |
422 | printf("DP read adjust request failed\n"); | |
423 | return -EAGAIN; | |
424 | } | |
425 | ||
426 | *sw = ((buf >> shift_val[lane_num]) & 0x03); | |
427 | *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; | |
428 | ||
429 | return ret; | |
430 | } | |
431 | ||
432 | static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info) | |
433 | { | |
434 | int ret; | |
435 | ||
436 | ret = exynos_dp_training_pattern_dis(); | |
437 | if (ret != EXYNOS_DP_SUCCESS) { | |
438 | printf("DP training_patter_disable() failed\n"); | |
439 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
440 | } | |
441 | ||
442 | ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); | |
443 | if (ret != EXYNOS_DP_SUCCESS) { | |
444 | printf("DP set_enhanced_mode() failed\n"); | |
445 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
446 | } | |
447 | ||
448 | return ret; | |
449 | } | |
450 | ||
451 | static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info) | |
452 | { | |
453 | int ret; | |
454 | ||
455 | if (edp_info->lane_bw == DP_LANE_BW_2_70) { | |
456 | edp_info->lane_bw = DP_LANE_BW_1_62; | |
457 | printf("DP Change lane bw to 1.62Gbps\n"); | |
458 | edp_info->lt_info.lt_status = DP_LT_START; | |
459 | ret = EXYNOS_DP_SUCCESS; | |
460 | } else { | |
461 | ret = exynos_dp_training_pattern_dis(); | |
462 | if (ret != EXYNOS_DP_SUCCESS) | |
463 | printf("DP training_patter_disable() failed\n"); | |
464 | ||
465 | ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); | |
466 | if (ret != EXYNOS_DP_SUCCESS) | |
467 | printf("DP set_enhanced_mode() failed\n"); | |
468 | ||
469 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
470 | } | |
471 | ||
472 | return ret; | |
473 | } | |
474 | ||
475 | static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info | |
476 | *edp_info) | |
477 | { | |
478 | unsigned int ret = EXYNOS_DP_SUCCESS; | |
479 | unsigned char lane_stat; | |
480 | unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; | |
481 | unsigned int i; | |
482 | unsigned char adj_req_sw; | |
483 | unsigned char adj_req_em; | |
484 | unsigned char buf[5]; | |
485 | ||
486 | debug("DP: %s was called\n", __func__); | |
487 | mdelay(1); | |
488 | ||
489 | ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); | |
490 | if (ret != EXYNOS_DP_SUCCESS) { | |
491 | printf("DP read lane status failed\n"); | |
492 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
493 | return ret; | |
494 | } | |
495 | ||
496 | if (lane_stat & DP_LANE_STAT_CR_DONE) { | |
497 | debug("DP clock Recovery training succeed\n"); | |
498 | exynos_dp_set_training_pattern(TRAINING_PTN2); | |
499 | ||
500 | for (i = 0; i < edp_info->lane_cnt; i++) { | |
501 | ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw, | |
502 | &adj_req_em); | |
503 | if (ret != EXYNOS_DP_SUCCESS) { | |
504 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
505 | return ret; | |
506 | } | |
507 | ||
508 | lt_ctl_val[i] = 0; | |
509 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; | |
510 | ||
511 | if ((adj_req_sw == VOLTAGE_LEVEL_3) | |
512 | || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { | |
513 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | | |
514 | MAX_PRE_EMPHASIS_REACH_3; | |
515 | } | |
516 | exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); | |
517 | } | |
518 | ||
519 | buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; | |
520 | buf[1] = lt_ctl_val[0]; | |
521 | buf[2] = lt_ctl_val[1]; | |
522 | buf[3] = lt_ctl_val[2]; | |
523 | buf[4] = lt_ctl_val[3]; | |
524 | ||
525 | ret = exynos_dp_write_bytes_to_dpcd( | |
526 | DPCD_TRAINING_PATTERN_SET, 5, buf); | |
527 | if (ret != EXYNOS_DP_SUCCESS) { | |
528 | printf("DP write traning pattern1 failed\n"); | |
529 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
530 | return ret; | |
531 | } else | |
532 | edp_info->lt_info.lt_status = DP_LT_ET; | |
533 | } else { | |
534 | for (i = 0; i < edp_info->lane_cnt; i++) { | |
535 | lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i); | |
536 | ret = exynos_dp_read_dpcd_adj_req(i, | |
537 | &adj_req_sw, &adj_req_em); | |
538 | if (ret != EXYNOS_DP_SUCCESS) { | |
539 | printf("DP read adj req failed\n"); | |
540 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
541 | return ret; | |
542 | } | |
543 | ||
544 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || | |
545 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) | |
546 | ret = exynos_dp_reduce_link_rate(edp_info); | |
547 | ||
548 | if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == | |
549 | adj_req_sw) && | |
550 | (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == | |
551 | adj_req_em)) { | |
552 | edp_info->lt_info.cr_loop[i]++; | |
553 | if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP) | |
554 | ret = exynos_dp_reduce_link_rate( | |
555 | edp_info); | |
556 | } | |
557 | ||
558 | lt_ctl_val[i] = 0; | |
559 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; | |
560 | ||
561 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || | |
562 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { | |
563 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | | |
564 | MAX_PRE_EMPHASIS_REACH_3; | |
565 | } | |
566 | exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); | |
567 | } | |
568 | ||
569 | ret = exynos_dp_write_bytes_to_dpcd( | |
570 | DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); | |
571 | if (ret != EXYNOS_DP_SUCCESS) { | |
572 | printf("DP write traning pattern2 failed\n"); | |
573 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
574 | return ret; | |
575 | } | |
576 | } | |
577 | ||
578 | return ret; | |
579 | } | |
580 | ||
581 | static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info | |
582 | *edp_info) | |
583 | { | |
584 | unsigned int ret = EXYNOS_DP_SUCCESS; | |
585 | unsigned char lane_stat, adj_req_sw, adj_req_em, i; | |
586 | unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; | |
587 | unsigned char interlane_aligned = 0; | |
588 | unsigned char f_bw; | |
589 | unsigned char f_lane_cnt; | |
590 | unsigned char sink_stat; | |
591 | ||
592 | mdelay(1); | |
593 | ||
594 | ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); | |
595 | if (ret != EXYNOS_DP_SUCCESS) { | |
596 | printf("DP read lane status failed\n"); | |
597 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
598 | return ret; | |
599 | } | |
600 | ||
601 | debug("DP lane stat : %x\n", lane_stat); | |
602 | ||
603 | if (lane_stat & DP_LANE_STAT_CR_DONE) { | |
604 | ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED, | |
605 | &sink_stat); | |
606 | if (ret != EXYNOS_DP_SUCCESS) { | |
607 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
608 | ||
609 | return ret; | |
610 | } | |
611 | ||
612 | interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); | |
613 | ||
614 | for (i = 0; i < edp_info->lane_cnt; i++) { | |
615 | ret = exynos_dp_read_dpcd_adj_req(i, | |
616 | &adj_req_sw, &adj_req_em); | |
617 | if (ret != EXYNOS_DP_SUCCESS) { | |
618 | printf("DP read adj req 1 failed\n"); | |
619 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
620 | ||
621 | return ret; | |
622 | } | |
623 | ||
624 | lt_ctl_val[i] = 0; | |
625 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; | |
626 | ||
627 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || | |
628 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { | |
629 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3; | |
630 | lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3; | |
631 | } | |
632 | } | |
633 | ||
634 | if (((lane_stat&DP_LANE_STAT_CE_DONE) && | |
635 | (lane_stat&DP_LANE_STAT_SYM_LOCK)) | |
636 | && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { | |
637 | debug("DP Equalizer training succeed\n"); | |
638 | ||
639 | f_bw = exynos_dp_get_link_bandwidth(); | |
640 | f_lane_cnt = exynos_dp_get_lane_count(); | |
641 | ||
642 | debug("DP final BandWidth : %x\n", f_bw); | |
643 | debug("DP final Lane Count : %x\n", f_lane_cnt); | |
644 | ||
645 | edp_info->lt_info.lt_status = DP_LT_FINISHED; | |
646 | ||
647 | exynos_dp_equalizer_err_link(edp_info); | |
648 | ||
649 | } else { | |
650 | edp_info->lt_info.ep_loop++; | |
651 | ||
652 | if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) { | |
653 | if (edp_info->lane_bw == DP_LANE_BW_2_70) { | |
654 | ret = exynos_dp_reduce_link_rate( | |
655 | edp_info); | |
656 | } else { | |
657 | edp_info->lt_info.lt_status = | |
658 | DP_LT_FAIL; | |
659 | exynos_dp_equalizer_err_link(edp_info); | |
660 | } | |
661 | } else { | |
662 | for (i = 0; i < edp_info->lane_cnt; i++) | |
663 | exynos_dp_set_lanex_pre_emphasis( | |
664 | lt_ctl_val[i], i); | |
665 | ||
666 | ret = exynos_dp_write_bytes_to_dpcd( | |
667 | DPCD_TRAINING_LANE0_SET, | |
668 | 4, lt_ctl_val); | |
669 | if (ret != EXYNOS_DP_SUCCESS) { | |
670 | printf("DP set lt pattern failed\n"); | |
671 | edp_info->lt_info.lt_status = | |
672 | DP_LT_FAIL; | |
673 | exynos_dp_equalizer_err_link(edp_info); | |
674 | } | |
675 | } | |
676 | } | |
677 | } else if (edp_info->lane_bw == DP_LANE_BW_2_70) { | |
678 | ret = exynos_dp_reduce_link_rate(edp_info); | |
679 | } else { | |
680 | edp_info->lt_info.lt_status = DP_LT_FAIL; | |
681 | exynos_dp_equalizer_err_link(edp_info); | |
682 | } | |
683 | ||
684 | return ret; | |
685 | } | |
686 | ||
687 | static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info) | |
688 | { | |
689 | unsigned int ret = 0; | |
690 | int training_finished; | |
691 | ||
692 | /* Turn off unnecessary lane */ | |
693 | if (edp_info->lane_cnt == 1) | |
694 | exynos_dp_set_analog_power_down(CH1_BLOCK, 1); | |
695 | ||
696 | training_finished = 0; | |
697 | ||
698 | edp_info->lt_info.lt_status = DP_LT_START; | |
699 | ||
700 | /* Process here */ | |
701 | while (!training_finished) { | |
702 | switch (edp_info->lt_info.lt_status) { | |
703 | case DP_LT_START: | |
704 | ret = exynos_dp_link_start(edp_info); | |
705 | if (ret != EXYNOS_DP_SUCCESS) { | |
706 | printf("DP LT:link start failed\n"); | |
707 | return ret; | |
708 | } | |
709 | break; | |
710 | case DP_LT_CR: | |
711 | ret = exynos_dp_process_clock_recovery(edp_info); | |
712 | if (ret != EXYNOS_DP_SUCCESS) { | |
713 | printf("DP LT:clock recovery failed\n"); | |
714 | return ret; | |
715 | } | |
716 | break; | |
717 | case DP_LT_ET: | |
718 | ret = exynos_dp_process_equalizer_training(edp_info); | |
719 | if (ret != EXYNOS_DP_SUCCESS) { | |
720 | printf("DP LT:equalizer training failed\n"); | |
721 | return ret; | |
722 | } | |
723 | break; | |
724 | case DP_LT_FINISHED: | |
725 | training_finished = 1; | |
726 | break; | |
727 | case DP_LT_FAIL: | |
728 | return -1; | |
729 | } | |
730 | } | |
731 | ||
732 | return ret; | |
733 | } | |
734 | ||
735 | static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info) | |
736 | { | |
737 | unsigned int ret; | |
738 | ||
739 | exynos_dp_init_training(); | |
740 | ||
741 | ret = exynos_dp_sw_link_training(edp_info); | |
742 | if (ret != EXYNOS_DP_SUCCESS) | |
743 | printf("DP dp_sw_link_traning() failed\n"); | |
744 | ||
745 | return ret; | |
746 | } | |
747 | ||
748 | static void exynos_dp_enable_scramble(unsigned int enable) | |
749 | { | |
750 | unsigned char data; | |
751 | ||
752 | if (enable) { | |
753 | exynos_dp_enable_scrambling(DP_ENABLE); | |
754 | ||
755 | exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, | |
756 | &data); | |
757 | exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, | |
758 | (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); | |
759 | } else { | |
760 | exynos_dp_enable_scrambling(DP_DISABLE); | |
761 | exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, | |
762 | &data); | |
763 | exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, | |
764 | (u8)(data | DPCD_SCRAMBLING_DISABLED)); | |
765 | } | |
766 | } | |
767 | ||
768 | static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info) | |
769 | { | |
770 | unsigned int ret = 0; | |
771 | unsigned int retry_cnt; | |
772 | ||
773 | mdelay(1); | |
774 | ||
775 | if (edp_info->video_info.master_mode) { | |
776 | printf("DP does not support master mode\n"); | |
777 | return -ENODEV; | |
778 | } else { | |
779 | /* debug slave */ | |
780 | exynos_dp_config_video_slave_mode(&edp_info->video_info); | |
781 | } | |
782 | ||
783 | exynos_dp_set_video_color_format(&edp_info->video_info); | |
784 | ||
785 | if (edp_info->video_info.bist_mode) { | |
786 | if (exynos_dp_config_video_bist(edp_info) != 0) | |
787 | return -1; | |
788 | } | |
789 | ||
790 | ret = exynos_dp_get_pll_lock_status(); | |
791 | if (ret != PLL_LOCKED) { | |
792 | printf("DP PLL is not locked yet\n"); | |
793 | return -EIO; | |
794 | } | |
795 | ||
796 | if (edp_info->video_info.master_mode == 0) { | |
797 | retry_cnt = 10; | |
798 | while (retry_cnt) { | |
799 | ret = exynos_dp_is_slave_video_stream_clock_on(); | |
800 | if (ret != EXYNOS_DP_SUCCESS) { | |
801 | if (retry_cnt == 0) { | |
802 | printf("DP stream_clock_on failed\n"); | |
803 | return ret; | |
804 | } | |
805 | retry_cnt--; | |
806 | mdelay(1); | |
807 | } else | |
808 | break; | |
809 | } | |
810 | } | |
811 | ||
812 | /* Set to use the register calculated M/N video */ | |
813 | exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0); | |
814 | ||
815 | /* For video bist, Video timing must be generated by register */ | |
816 | exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE); | |
817 | ||
818 | /* Enable video bist */ | |
819 | if (edp_info->video_info.bist_pattern != COLOR_RAMP && | |
820 | edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES && | |
821 | edp_info->video_info.bist_pattern != COLOR_SQUARE) | |
822 | exynos_dp_enable_video_bist(edp_info->video_info.bist_mode); | |
823 | else | |
824 | exynos_dp_enable_video_bist(DP_DISABLE); | |
825 | ||
826 | /* Disable video mute */ | |
827 | exynos_dp_enable_video_mute(DP_DISABLE); | |
828 | ||
829 | /* Configure video Master or Slave mode */ | |
830 | exynos_dp_enable_video_master(edp_info->video_info.master_mode); | |
831 | ||
832 | /* Enable video */ | |
833 | exynos_dp_start_video(); | |
834 | ||
835 | if (edp_info->video_info.master_mode == 0) { | |
836 | retry_cnt = 100; | |
837 | while (retry_cnt) { | |
838 | ret = exynos_dp_is_video_stream_on(); | |
839 | if (ret != EXYNOS_DP_SUCCESS) { | |
840 | if (retry_cnt == 0) { | |
841 | printf("DP Timeout of video stream\n"); | |
842 | return ret; | |
843 | } | |
844 | retry_cnt--; | |
845 | mdelay(5); | |
846 | } else | |
847 | break; | |
848 | } | |
849 | } | |
850 | ||
851 | return ret; | |
852 | } | |
853 | ||
9947d13e AK |
854 | #ifdef CONFIG_OF_CONTROL |
855 | int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info) | |
856 | { | |
857 | unsigned int node = fdtdec_next_compatible(blob, 0, | |
858 | COMPAT_SAMSUNG_EXYNOS5_DP); | |
859 | if (node <= 0) { | |
860 | debug("exynos_dp: Can't get device node for dp\n"); | |
861 | return -ENODEV; | |
862 | } | |
863 | ||
864 | edp_info->disp_info.h_res = fdtdec_get_int(blob, node, | |
865 | "samsung,h-res", 0); | |
866 | edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node, | |
867 | "samsung,h-sync-width", 0); | |
868 | edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node, | |
869 | "samsung,h-back-porch", 0); | |
870 | edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node, | |
871 | "samsung,h-front-porch", 0); | |
872 | edp_info->disp_info.v_res = fdtdec_get_int(blob, node, | |
873 | "samsung,v-res", 0); | |
874 | edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node, | |
875 | "samsung,v-sync-width", 0); | |
876 | edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node, | |
877 | "samsung,v-back-porch", 0); | |
878 | edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node, | |
879 | "samsung,v-front-porch", 0); | |
880 | edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node, | |
881 | "samsung,v-sync-rate", 0); | |
882 | ||
883 | edp_info->lt_info.lt_status = fdtdec_get_int(blob, node, | |
884 | "samsung,lt-status", 0); | |
885 | ||
886 | edp_info->video_info.master_mode = fdtdec_get_int(blob, node, | |
887 | "samsung,master-mode", 0); | |
888 | edp_info->video_info.bist_mode = fdtdec_get_int(blob, node, | |
889 | "samsung,bist-mode", 0); | |
890 | edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node, | |
891 | "samsung,bist-pattern", 0); | |
892 | edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node, | |
893 | "samsung,h-sync-polarity", 0); | |
894 | edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node, | |
895 | "samsung,v-sync-polarity", 0); | |
896 | edp_info->video_info.interlaced = fdtdec_get_int(blob, node, | |
897 | "samsung,interlaced", 0); | |
898 | edp_info->video_info.color_space = fdtdec_get_int(blob, node, | |
899 | "samsung,color-space", 0); | |
900 | edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node, | |
901 | "samsung,dynamic-range", 0); | |
902 | edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, | |
903 | "samsung,ycbcr-coeff", 0); | |
904 | edp_info->video_info.color_depth = fdtdec_get_int(blob, node, | |
905 | "samsung,color-depth", 0); | |
906 | return 0; | |
907 | } | |
908 | #endif | |
909 | ||
d2a6982f DL |
910 | unsigned int exynos_init_dp(void) |
911 | { | |
912 | unsigned int ret; | |
913 | struct edp_device_info *edp_info; | |
d2a6982f DL |
914 | |
915 | edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL); | |
916 | if (!edp_info) { | |
917 | debug("failed to allocate edp device object.\n"); | |
918 | return -EFAULT; | |
919 | } | |
920 | ||
9947d13e AK |
921 | #ifdef CONFIG_OF_CONTROL |
922 | if (exynos_dp_parse_dt(gd->fdt_blob, edp_info)) | |
923 | debug("unable to parse DP DT node\n"); | |
924 | #else | |
d2a6982f DL |
925 | edp_info = dp_pd->edp_dev_info; |
926 | if (edp_info == NULL) { | |
927 | debug("failed to get edp_info data.\n"); | |
928 | return -EFAULT; | |
929 | } | |
9947d13e | 930 | #endif |
d2a6982f | 931 | |
beded3d1 AK |
932 | exynos_dp_set_base_addr(); |
933 | ||
d2a6982f DL |
934 | exynos_dp_disp_info(&edp_info->disp_info); |
935 | ||
c18222be | 936 | exynos_set_dp_phy(1); |
d2a6982f DL |
937 | |
938 | ret = exynos_dp_init_dp(); | |
939 | if (ret != EXYNOS_DP_SUCCESS) { | |
940 | printf("DP exynos_dp_init_dp() failed\n"); | |
941 | return ret; | |
942 | } | |
943 | ||
944 | ret = exynos_dp_handle_edid(edp_info); | |
945 | if (ret != EXYNOS_DP_SUCCESS) { | |
946 | printf("EDP handle_edid fail\n"); | |
947 | return ret; | |
948 | } | |
949 | ||
950 | ret = exynos_dp_set_link_train(edp_info); | |
951 | if (ret != EXYNOS_DP_SUCCESS) { | |
952 | printf("DP link training fail\n"); | |
953 | return ret; | |
954 | } | |
955 | ||
956 | exynos_dp_enable_scramble(DP_ENABLE); | |
957 | exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE); | |
958 | exynos_dp_enable_enhanced_mode(DP_ENABLE); | |
959 | ||
960 | exynos_dp_set_link_bandwidth(edp_info->lane_bw); | |
961 | exynos_dp_set_lane_count(edp_info->lane_cnt); | |
962 | ||
963 | exynos_dp_init_video(); | |
964 | ret = exynos_dp_config_video(edp_info); | |
965 | if (ret != EXYNOS_DP_SUCCESS) { | |
966 | printf("Exynos DP init failed\n"); | |
967 | return ret; | |
968 | } | |
969 | ||
970 | printf("Exynos DP init done\n"); | |
971 | ||
972 | return ret; | |
973 | } | |
974 | ||
975 | void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd) | |
976 | { | |
977 | if (pd == NULL) { | |
978 | debug("pd is NULL\n"); | |
979 | return; | |
980 | } | |
981 | ||
982 | dp_pd = pd; | |
983 | } |