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imx: spl: implement spl_boot_device for i.MX8M
[people/ms/u-boot.git] / drivers / video / ivybridge_igd.c
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2c943804
SG		 1/*
2 * Copyright (C) 2016 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <bios_emul.h>
9#include <dm.h>
10#include <errno.h>
11#include <fdtdec.h>
12#include <pci_rom.h>
13#include <vbe.h>
14#include <asm/intel_regs.h>
15#include <asm/io.h>
16#include <asm/mtrr.h>
17#include <asm/pci.h>
18#include <asm/arch/pch.h>
19#include <asm/arch/sandybridge.h>
20
05af050e
SG		 21DECLARE_GLOBAL_DATA_PTR;
22
2c943804
SG		 23struct gt_powermeter {
24 u16 reg;
25 u32 value;
26};
27
28/* These are magic values - unfortunately the meaning is unknown */
29static const struct gt_powermeter snb_pm_gt1[] = {
30 { 0xa200, 0xcc000000 },
31 { 0xa204, 0x07000040 },
32 { 0xa208, 0x0000fe00 },
33 { 0xa20c, 0x00000000 },
34 { 0xa210, 0x17000000 },
35 { 0xa214, 0x00000021 },
36 { 0xa218, 0x0817fe19 },
37 { 0xa21c, 0x00000000 },
38 { 0xa220, 0x00000000 },
39 { 0xa224, 0xcc000000 },
40 { 0xa228, 0x07000040 },
41 { 0xa22c, 0x0000fe00 },
42 { 0xa230, 0x00000000 },
43 { 0xa234, 0x17000000 },
44 { 0xa238, 0x00000021 },
45 { 0xa23c, 0x0817fe19 },
46 { 0xa240, 0x00000000 },
47 { 0xa244, 0x00000000 },
48 { 0xa248, 0x8000421e },
49 { 0 }
50};
51
52static const struct gt_powermeter snb_pm_gt2[] = {
53 { 0xa200, 0x330000a6 },
54 { 0xa204, 0x402d0031 },
55 { 0xa208, 0x00165f83 },
56 { 0xa20c, 0xf1000000 },
57 { 0xa210, 0x00000000 },
58 { 0xa214, 0x00160016 },
59 { 0xa218, 0x002a002b },
60 { 0xa21c, 0x00000000 },
61 { 0xa220, 0x00000000 },
62 { 0xa224, 0x330000a6 },
63 { 0xa228, 0x402d0031 },
64 { 0xa22c, 0x00165f83 },
65 { 0xa230, 0xf1000000 },
66 { 0xa234, 0x00000000 },
67 { 0xa238, 0x00160016 },
68 { 0xa23c, 0x002a002b },
69 { 0xa240, 0x00000000 },
70 { 0xa244, 0x00000000 },
71 { 0xa248, 0x8000421e },
72 { 0 }
73};
74
75static const struct gt_powermeter ivb_pm_gt1[] = {
76 { 0xa800, 0x00000000 },
77 { 0xa804, 0x00021c00 },
78 { 0xa808, 0x00000403 },
79 { 0xa80c, 0x02001700 },
80 { 0xa810, 0x05000200 },
81 { 0xa814, 0x00000000 },
82 { 0xa818, 0x00690500 },
83 { 0xa81c, 0x0000007f },
84 { 0xa820, 0x01002501 },
85 { 0xa824, 0x00000300 },
86 { 0xa828, 0x01000331 },
87 { 0xa82c, 0x0000000c },
88 { 0xa830, 0x00010016 },
89 { 0xa834, 0x01100101 },
90 { 0xa838, 0x00010103 },
91 { 0xa83c, 0x00041300 },
92 { 0xa840, 0x00000b30 },
93 { 0xa844, 0x00000000 },
94 { 0xa848, 0x7f000000 },
95 { 0xa84c, 0x05000008 },
96 { 0xa850, 0x00000001 },
97 { 0xa854, 0x00000004 },
98 { 0xa858, 0x00000007 },
99 { 0xa85c, 0x00000000 },
100 { 0xa860, 0x00010000 },
101 { 0xa248, 0x0000221e },
102 { 0xa900, 0x00000000 },
103 { 0xa904, 0x00001c00 },
104 { 0xa908, 0x00000000 },
105 { 0xa90c, 0x06000000 },
106 { 0xa910, 0x09000200 },
107 { 0xa914, 0x00000000 },
108 { 0xa918, 0x00590000 },
109 { 0xa91c, 0x00000000 },
110 { 0xa920, 0x04002501 },
111 { 0xa924, 0x00000100 },
112 { 0xa928, 0x03000410 },
113 { 0xa92c, 0x00000000 },
114 { 0xa930, 0x00020000 },
115 { 0xa934, 0x02070106 },
116 { 0xa938, 0x00010100 },
117 { 0xa93c, 0x00401c00 },
118 { 0xa940, 0x00000000 },
119 { 0xa944, 0x00000000 },
120 { 0xa948, 0x10000e00 },
121 { 0xa94c, 0x02000004 },
122 { 0xa950, 0x00000001 },
123 { 0xa954, 0x00000004 },
124 { 0xa960, 0x00060000 },
125 { 0xaa3c, 0x00001c00 },
126 { 0xaa54, 0x00000004 },
127 { 0xaa60, 0x00060000 },
128 { 0 }
129};
130
131static const struct gt_powermeter ivb_pm_gt2[] = {
132 { 0xa800, 0x10000000 },
133 { 0xa804, 0x00033800 },
134 { 0xa808, 0x00000902 },
135 { 0xa80c, 0x0c002f00 },
136 { 0xa810, 0x12000400 },
137 { 0xa814, 0x00000000 },
138 { 0xa818, 0x00d20800 },
139 { 0xa81c, 0x00000002 },
140 { 0xa820, 0x03004b02 },
141 { 0xa824, 0x00000600 },
142 { 0xa828, 0x07000773 },
143 { 0xa82c, 0x00000000 },
144 { 0xa830, 0x00010032 },
145 { 0xa834, 0x1520040d },
146 { 0xa838, 0x00020105 },
147 { 0xa83c, 0x00083700 },
148 { 0xa840, 0x0000151d },
149 { 0xa844, 0x00000000 },
150 { 0xa848, 0x20001b00 },
151 { 0xa84c, 0x0a000010 },
152 { 0xa850, 0x00000000 },
153 { 0xa854, 0x00000008 },
154 { 0xa858, 0x00000008 },
155 { 0xa85c, 0x00000000 },
156 { 0xa860, 0x00020000 },
157 { 0xa248, 0x0000221e },
158 { 0xa900, 0x00000000 },
159 { 0xa904, 0x00003500 },
160 { 0xa908, 0x00000000 },
161 { 0xa90c, 0x0c000000 },
162 { 0xa910, 0x12000500 },
163 { 0xa914, 0x00000000 },
164 { 0xa918, 0x00b20000 },
165 { 0xa91c, 0x00000000 },
166 { 0xa920, 0x08004b02 },
167 { 0xa924, 0x00000200 },
168 { 0xa928, 0x07000820 },
169 { 0xa92c, 0x00000000 },
170 { 0xa930, 0x00030000 },
171 { 0xa934, 0x050f020d },
172 { 0xa938, 0x00020300 },
173 { 0xa93c, 0x00903900 },
174 { 0xa940, 0x00000000 },
175 { 0xa944, 0x00000000 },
176 { 0xa948, 0x20001b00 },
177 { 0xa94c, 0x0a000010 },
178 { 0xa950, 0x00000000 },
179 { 0xa954, 0x00000008 },
180 { 0xa960, 0x00110000 },
181 { 0xaa3c, 0x00003900 },
182 { 0xaa54, 0x00000008 },
183 { 0xaa60, 0x00110000 },
184 { 0 }
185};
186
187static const struct gt_powermeter ivb_pm_gt2_17w[] = {
188 { 0xa800, 0x20000000 },
189 { 0xa804, 0x000e3800 },
190 { 0xa808, 0x00000806 },
191 { 0xa80c, 0x0c002f00 },
192 { 0xa810, 0x0c000800 },
193 { 0xa814, 0x00000000 },
194 { 0xa818, 0x00d20d00 },
195 { 0xa81c, 0x000000ff },
196 { 0xa820, 0x03004b02 },
197 { 0xa824, 0x00000600 },
198 { 0xa828, 0x07000773 },
199 { 0xa82c, 0x00000000 },
200 { 0xa830, 0x00020032 },
201 { 0xa834, 0x1520040d },
202 { 0xa838, 0x00020105 },
203 { 0xa83c, 0x00083700 },
204 { 0xa840, 0x000016ff },
205 { 0xa844, 0x00000000 },
206 { 0xa848, 0xff000000 },
207 { 0xa84c, 0x0a000010 },
208 { 0xa850, 0x00000002 },
209 { 0xa854, 0x00000008 },
210 { 0xa858, 0x0000000f },
211 { 0xa85c, 0x00000000 },
212 { 0xa860, 0x00020000 },
213 { 0xa248, 0x0000221e },
214 { 0xa900, 0x00000000 },
215 { 0xa904, 0x00003800 },
216 { 0xa908, 0x00000000 },
217 { 0xa90c, 0x0c000000 },
218 { 0xa910, 0x12000800 },
219 { 0xa914, 0x00000000 },
220 { 0xa918, 0x00b20000 },
221 { 0xa91c, 0x00000000 },
222 { 0xa920, 0x08004b02 },
223 { 0xa924, 0x00000300 },
224 { 0xa928, 0x01000820 },
225 { 0xa92c, 0x00000000 },
226 { 0xa930, 0x00030000 },
227 { 0xa934, 0x15150406 },
228 { 0xa938, 0x00020300 },
229 { 0xa93c, 0x00903900 },
230 { 0xa940, 0x00000000 },
231 { 0xa944, 0x00000000 },
232 { 0xa948, 0x20001b00 },
233 { 0xa94c, 0x0a000010 },
234 { 0xa950, 0x00000000 },
235 { 0xa954, 0x00000008 },
236 { 0xa960, 0x00110000 },
237 { 0xaa3c, 0x00003900 },
238 { 0xaa54, 0x00000008 },
239 { 0xaa60, 0x00110000 },
240 { 0 }
241};
242
243static const struct gt_powermeter ivb_pm_gt2_35w[] = {
244 { 0xa800, 0x00000000 },
245 { 0xa804, 0x00030400 },
246 { 0xa808, 0x00000806 },
247 { 0xa80c, 0x0c002f00 },
248 { 0xa810, 0x0c000300 },
249 { 0xa814, 0x00000000 },
250 { 0xa818, 0x00d20d00 },
251 { 0xa81c, 0x000000ff },
252 { 0xa820, 0x03004b02 },
253 { 0xa824, 0x00000600 },
254 { 0xa828, 0x07000773 },
255 { 0xa82c, 0x00000000 },
256 { 0xa830, 0x00020032 },
257 { 0xa834, 0x1520040d },
258 { 0xa838, 0x00020105 },
259 { 0xa83c, 0x00083700 },
260 { 0xa840, 0x000016ff },
261 { 0xa844, 0x00000000 },
262 { 0xa848, 0xff000000 },
263 { 0xa84c, 0x0a000010 },
264 { 0xa850, 0x00000001 },
265 { 0xa854, 0x00000008 },
266 { 0xa858, 0x00000008 },
267 { 0xa85c, 0x00000000 },
268 { 0xa860, 0x00020000 },
269 { 0xa248, 0x0000221e },
270 { 0xa900, 0x00000000 },
271 { 0xa904, 0x00003800 },
272 { 0xa908, 0x00000000 },
273 { 0xa90c, 0x0c000000 },
274 { 0xa910, 0x12000800 },
275 { 0xa914, 0x00000000 },
276 { 0xa918, 0x00b20000 },
277 { 0xa91c, 0x00000000 },
278 { 0xa920, 0x08004b02 },
279 { 0xa924, 0x00000300 },
280 { 0xa928, 0x01000820 },
281 { 0xa92c, 0x00000000 },
282 { 0xa930, 0x00030000 },
283 { 0xa934, 0x15150406 },
284 { 0xa938, 0x00020300 },
285 { 0xa93c, 0x00903900 },
286 { 0xa940, 0x00000000 },
287 { 0xa944, 0x00000000 },
288 { 0xa948, 0x20001b00 },
289 { 0xa94c, 0x0a000010 },
290 { 0xa950, 0x00000000 },
291 { 0xa954, 0x00000008 },
292 { 0xa960, 0x00110000 },
293 { 0xaa3c, 0x00003900 },
294 { 0xaa54, 0x00000008 },
295 { 0xaa60, 0x00110000 },
296 { 0 }
297};
298
299static inline u32 gtt_read(void *bar, u32 reg)
300{
301 return readl(bar + reg);
302}
303
304static inline void gtt_write(void *bar, u32 reg, u32 data)
305{
306 writel(data, bar + reg);
307}
308
309static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
310{
311 for (; pm && pm->reg; pm++)
312 gtt_write(bar, pm->reg, pm->value);
313}
314
315#define GTT_RETRY 1000
316static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
317{
318 unsigned try = GTT_RETRY;
319 u32 data;
320
321 while (try--) {
322 data = gtt_read(bar, reg);
323 if ((data & mask) == value)
324 return 1;
325 udelay(10);
326 }
327
328 printf("GT init timeout\n");
329 return 0;
330}
331
332static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
333{
334 u32 reg32;
335
336 debug("GT Power Management Init, silicon = %#x\n", rev);
337
338 if (rev < IVB_STEP_C0) {
339 /* 1: Enable force wake */
340 gtt_write(gtt_bar, 0xa18c, 0x00000001);
341 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
342 } else {
343 gtt_write(gtt_bar, 0xa180, 1 << 5);
344 gtt_write(gtt_bar, 0xa188, 0xffff0001);
345 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
346 }
347
348 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
349 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
350 reg32 = gtt_read(gtt_bar, 0x42004);
351 reg32 |= (1 << 14) | (1 << 15);
352 gtt_write(gtt_bar, 0x42004, reg32);
353 }
354
355 if (rev >= IVB_STEP_A0) {
356 /* Display Reset Acknowledge Settings */
357 reg32 = gtt_read(gtt_bar, 0x45010);
358 reg32 |= (1 << 1) | (1 << 0);
359 gtt_write(gtt_bar, 0x45010, reg32);
360 }
361
362 /* 2: Get GT SKU from GTT+0x911c[13] */
363 reg32 = gtt_read(gtt_bar, 0x911c);
364 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
365 if (reg32 & (1 << 13)) {
366 debug("SNB GT1 Power Meter Weights\n");
367 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
368 } else {
369 debug("SNB GT2 Power Meter Weights\n");
370 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
371 }
372 } else {
373 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
374
375 if (reg32 & (1 << 13)) {
376 /* GT1 SKU */
377 debug("IVB GT1 Power Meter Weights\n");
378 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
379 } else {
380 /* GT2 SKU */
381 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
382 tdp /= (1 << unit);
383
384 if (tdp <= 17) {
385 /* <=17W ULV */
386 debug("IVB GT2 17W Power Meter Weights\n");
387 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
388 } else if ((tdp >= 25) && (tdp <= 35)) {
389 /* 25W-35W */
390 debug("IVB GT2 25W-35W Power Meter Weights\n");
391 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
392 } else {
393 /* All others */
394 debug("IVB GT2 35W Power Meter Weights\n");
395 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
396 }
397 }
398 }
399
400 /* 3: Gear ratio map */
401 gtt_write(gtt_bar, 0xa004, 0x00000010);
402
403 /* 4: GFXPAUSE */
404 gtt_write(gtt_bar, 0xa000, 0x00070020);
405
406 /* 5: Dynamic EU trip control */
407 gtt_write(gtt_bar, 0xa080, 0x00000004);
408
409 /* 6: ECO bits */
410 reg32 = gtt_read(gtt_bar, 0xa180);
411 reg32 |= (1 << 26) | (1 << 31);
412 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
413 if (rev >= SNB_STEP_D1)
414 reg32 |= (1 << 20);
415 gtt_write(gtt_bar, 0xa180, reg32);
416
417 /* 6a: for SnB step D2+ only */
418 if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
419 (rev >= SNB_STEP_D2)) {
420 reg32 = gtt_read(gtt_bar, 0x9400);
421 reg32 |= (1 << 7);
422 gtt_write(gtt_bar, 0x9400, reg32);
423
424 reg32 = gtt_read(gtt_bar, 0x941c);
425 reg32 &= 0xf;
426 reg32 |= (1 << 1);
427 gtt_write(gtt_bar, 0x941c, reg32);
428 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
429 }
430
431 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
432 reg32 = gtt_read(gtt_bar, 0x907c);
433 reg32 |= (1 << 16);
434 gtt_write(gtt_bar, 0x907c, reg32);
435
436 /* 6b: Clocking reset controls */
437 gtt_write(gtt_bar, 0x9424, 0x00000001);
438 } else {
439 /* 6b: Clocking reset controls */
440 gtt_write(gtt_bar, 0x9424, 0x00000000);
441 }
442
443 /* 7 */
444 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
445 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
446 /* Mailbox Cmd for RC6 VID */
447 gtt_write(gtt_bar, 0x138124, 0x80000004);
448 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
449 gtt_write(gtt_bar, 0x138124, 0x8000000a);
450 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
451 }
452
453 /* 8 */
454 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
455 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
456 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
457 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
458 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
459 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
460
461 /* 9 */
462 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
463 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
464 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
465
466 /* 10 */
467 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
468 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
469 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
470 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
471 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
472
473 /* 11 */
474 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
475 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
476 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
477 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
478 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
479 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
480 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
481
482 /* 11a: Enable Render Standby (RC6) */
483 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
484 /*
485 * IvyBridge should also support DeepRenderStandby.
486 *
487 * Unfortunately it does not work reliably on all SKUs so
488 * disable it here and it can be enabled by the kernel.
489 */
490 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
491 } else {
492 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
493 }
494
495 /* 12: Normal Frequency Request */
496 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
497 reg32 = readl(MCHBAR_REG(0x5998));
498 reg32 >>= 16;
499 reg32 &= 0xef;
500 reg32 <<= 25;
501 gtt_write(gtt_bar, 0xa008, reg32);
502
503 /* 13: RP Control */
504 gtt_write(gtt_bar, 0xa024, 0x00000592);
505
506 /* 14: Enable PM Interrupts */
507 gtt_write(gtt_bar, 0x4402c, 0x03000076);
508
509 /* Clear 0x6c024 [8:6] */
510 reg32 = gtt_read(gtt_bar, 0x6c024);
511 reg32 &= ~0x000001c0;
512 gtt_write(gtt_bar, 0x6c024, reg32);
513
514 return 0;
515}
516
517static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
518{
519 const void *blob = gd->fdt_blob;
e160f7d4 520 int node = dev_of_offset(dev);
2c943804
SG		 521 u32 reg32, cycle_delay;
522
523 debug("GT Power Management Init (post VBIOS)\n");
524
525 /* 15: Deassert Force Wake */
526 if (rev < IVB_STEP_C0) {
527 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
528 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
529 } else {
530 gtt_write(gtt_bar, 0xa188, 0x1fffe);
531 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
532 gtt_write(gtt_bar, 0xa188,
533 gtt_read(gtt_bar, 0xa188) | 1);
534 }
535 }
536
537 /* 16: SW RC Control */
538 gtt_write(gtt_bar, 0xa094, 0x00060000);
539
540 /* Setup Digital Port Hotplug */
541 reg32 = gtt_read(gtt_bar, 0xc4030);
542 if (!reg32) {
543 u32 dp_hotplug[3];
544
545 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
546 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
547 return -EINVAL;
548
549 reg32 = (dp_hotplug[0] & 0x7) << 2;
550 reg32 |= (dp_hotplug[0] & 0x7) << 10;
551 reg32 |= (dp_hotplug[0] & 0x7) << 18;
552 gtt_write(gtt_bar, 0xc4030, reg32);
553 }
554
555 /* Setup Panel Power On Delays */
556 reg32 = gtt_read(gtt_bar, 0xc7208);
557 if (!reg32) {
558 reg32 = (unsigned)fdtdec_get_int(blob, node,
559 "panel-port-select", 0) << 30;
560 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
561 << 16;
562 reg32 |= fdtdec_get_int(blob, node,
563 "panel-power-backlight-on-delay", 0);
564 gtt_write(gtt_bar, 0xc7208, reg32);
565 }
566
567 /* Setup Panel Power Off Delays */
568 reg32 = gtt_read(gtt_bar, 0xc720c);
569 if (!reg32) {
570 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
571 << 16;
572 reg32 |= fdtdec_get_int(blob, node,
573 "panel-power-backlight-off-delay", 0);
574 gtt_write(gtt_bar, 0xc720c, reg32);
575 }
576
577 /* Setup Panel Power Cycle Delay */
578 cycle_delay = fdtdec_get_int(blob, node,
579 "intel,panel-power-cycle-delay", 0);
580 if (cycle_delay) {
581 reg32 = gtt_read(gtt_bar, 0xc7210);
582 reg32 &= ~0xff;
583 reg32 |= cycle_delay;
584 gtt_write(gtt_bar, 0xc7210, reg32);
585 }
586
587 /* Enable Backlight if needed */
588 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
589 if (reg32) {
590 gtt_write(gtt_bar, 0x48250, (1 << 31));
591 gtt_write(gtt_bar, 0x48254, reg32);
592 }
593 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
594 if (reg32) {
595 gtt_write(gtt_bar, 0xc8250, (1 << 31));
596 gtt_write(gtt_bar, 0xc8254, reg32);
597 }
598
599 return 0;
600}
601
602/*
603 * Some vga option roms are used for several chipsets but they only have one
604 * PCI ID in their header. If we encounter such an option rom, we need to do
605 * the mapping ourselves.
606 */
607
608uint32_t board_map_oprom_vendev(uint32_t vendev)
609{
610 switch (vendev) {
611 case 0x80860102: /* GT1 Desktop */
612 case 0x8086010a: /* GT1 Server */
613 case 0x80860112: /* GT2 Desktop */
614 case 0x80860116: /* GT2 Mobile */
615 case 0x80860122: /* GT2 Desktop >=1.3GHz */
616 case 0x80860126: /* GT2 Mobile >=1.3GHz */
617 case 0x80860156: /* IVB */
618 case 0x80860166: /* IVB */
619 return 0x80860106; /* GT1 Mobile */
620 }
621
622 return vendev;
623}
624
625static int int15_handler(void)
626{
627 int res = 0;
628
629 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
630
631 switch (M.x86.R_AX) {
632 case 0x5f34:
633 /*
634 * Set Panel Fitting Hook:
635 * bit 2 = Graphics Stretching
636 * bit 1 = Text Stretching
637 * bit 0 = Centering (do not set with bit1 or bit2)
638 * 0 = video bios default
639 */
640 M.x86.R_AX = 0x005f;
641 M.x86.R_CL = 0x00; /* Use video bios default */
642 res = 1;
643 break;
644 case 0x5f35:
645 /*
646 * Boot Display Device Hook:
647 * bit 0 = CRT
648 * bit 1 = TV (eDP)
649 * bit 2 = EFP
650 * bit 3 = LFP
651 * bit 4 = CRT2
652 * bit 5 = TV2 (eDP)
653 * bit 6 = EFP2
654 * bit 7 = LFP2
655 */
656 M.x86.R_AX = 0x005f;
657 M.x86.R_CX = 0x0000; /* Use video bios default */
658 res = 1;
659 break;
660 case 0x5f51:
661 /*
662 * Hook to select active LFP configuration:
663 * 00h = No LVDS, VBIOS does not enable LVDS
664 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
665 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
666 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
667 */
668 M.x86.R_AX = 0x005f;
669 M.x86.R_CX = 0x0003; /* eDP */
670 res = 1;
671 break;
672 case 0x5f70:
673 switch (M.x86.R_CH) {
674 case 0:
675 /* Get Mux */
676 M.x86.R_AX = 0x005f;
677 M.x86.R_CX = 0x0000;
678 res = 1;
679 break;
680 case 1:
681 /* Set Mux */
682 M.x86.R_AX = 0x005f;
683 M.x86.R_CX = 0x0000;
684 res = 1;
685 break;
686 case 2:
687 /* Get SG/Non-SG mode */
688 M.x86.R_AX = 0x005f;
689 M.x86.R_CX = 0x0000;
690 res = 1;
691 break;
692 default:
693 /* Interrupt was not handled */
694 debug("Unknown INT15 5f70 function: 0x%02x\n",
695 M.x86.R_CH);
696 break;
697 }
698 break;
699 case 0x5fac:
700 res = 1;
701 break;
702 default:
703 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
704 break;
705 }
706 return res;
707}
708
709static void sandybridge_setup_graphics(struct udevice *dev,
710 struct udevice *video_dev)
711{
712 u32 reg32;
713 u16 reg16;
714 u8 reg8;
715
716 dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
717 switch (reg16) {
718 case 0x0102: /* GT1 Desktop */
719 case 0x0106: /* GT1 Mobile */
720 case 0x010a: /* GT1 Server */
721 case 0x0112: /* GT2 Desktop */
722 case 0x0116: /* GT2 Mobile */
723 case 0x0122: /* GT2 Desktop >=1.3GHz */
724 case 0x0126: /* GT2 Mobile >=1.3GHz */
725 case 0x0156: /* IvyBridge */
726 case 0x0166: /* IvyBridge */
727 break;
728 default:
729 debug("Graphics not supported by this CPU/chipset\n");
730 return;
731 }
732
733 debug("Initialising Graphics\n");
734
735 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
736 dm_pci_read_config16(dev, GGC, &reg16);
737 reg16 &= ~0x00f8;
738 reg16 |= 1 << 3;
739 /* Program GTT memory by setting GGC[9:8] = 2MB */
740 reg16 &= ~0x0300;
741 reg16 |= 2 << 8;
742 /* Enable VGA decode */
743 reg16 &= ~0x0002;
744 dm_pci_write_config16(dev, GGC, reg16);
745
746 /* Enable 256MB aperture */
747 dm_pci_read_config8(video_dev, MSAC, &reg8);
748 reg8 &= ~0x06;
749 reg8 |= 0x02;
750 dm_pci_write_config8(video_dev, MSAC, reg8);
751
752 /* Erratum workarounds */
753 reg32 = readl(MCHBAR_REG(0x5f00));
754 reg32 |= (1 << 9) | (1 << 10);
755 writel(reg32, MCHBAR_REG(0x5f00));
756
757 /* Enable SA Clock Gating */
758 reg32 = readl(MCHBAR_REG(0x5f00));
759 writel(reg32 | 1, MCHBAR_REG(0x5f00));
760
761 /* GPU RC6 workaround for sighting 366252 */
762 reg32 = readl(MCHBAR_REG(0x5d14));
763 reg32 |= (1 << 31);
764 writel(reg32, MCHBAR_REG(0x5d14));
765
766 /* VLW */
767 reg32 = readl(MCHBAR_REG(0x6120));
768 reg32 &= ~(1 << 0);
769 writel(reg32, MCHBAR_REG(0x6120));
770
771 reg32 = readl(MCHBAR_REG(0x5418));
772 reg32 |= (1 << 4) | (1 << 5);
773 writel(reg32, MCHBAR_REG(0x5418));
774}
775
776static int gma_func0_init(struct udevice *dev)
777{
778 struct udevice *nbridge;
779 void *gtt_bar;
780 ulong base;
781 u32 reg32;
782 int ret;
783 int rev;
784
785 /* Enable PCH Display Port */
786 writew(0x0010, RCB_REG(DISPBDF));
787 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
788
789 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
790 if (ret)
791 return ret;
792 rev = bridge_silicon_revision(nbridge);
793 sandybridge_setup_graphics(nbridge, dev);
794
795 /* IGD needs to be Bus Master */
796 dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
797 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
798 dm_pci_write_config32(dev, PCI_COMMAND, reg32);
799
800 /* Use write-combining for the graphics memory, 256MB */
801 base = dm_pci_read_bar32(dev, 2);
802 mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
803 mtrr_commit(true);
804
c7ccb2c0 805 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
2c943804
SG		 806 debug("GT bar %p\n", gtt_bar);
807 ret = gma_pm_init_pre_vbios(gtt_bar, rev);
808 if (ret)
809 return ret;
810
811 return rev;
812}
813
814static int bd82x6x_video_probe(struct udevice *dev)
815{
816 void *gtt_bar;
817 int ret, rev;
818
819 rev = gma_func0_init(dev);
820 if (rev < 0)
821 return rev;
822 ret = vbe_setup_video(dev, int15_handler);
823 if (ret)
824 return ret;
825
826 /* Post VBIOS init */
c7ccb2c0 827 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
2c943804
SG		 828 ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
829 if (ret)
830 return ret;
831
832 return 0;
833}
834
835static const struct udevice_id bd82x6x_video_ids[] = {
836 { .compatible = "intel,gma" },
837 { }
838};
839
840U_BOOT_DRIVER(bd82x6x_video) = {
841 .name = "bd82x6x_video",
842 .id = UCLASS_VIDEO,
843 .of_match = bd82x6x_video_ids,
844 .probe = bd82x6x_video_probe,
845};
"Das U-Boot" Source Tree