[people/ms/u-boot.git] / drivers / video / mb862xx.c

/*
 * (C) Copyright 2007
 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
 * PCI and video mode code was derived from smiLynxEM driver.
 */

#include <common.h>

#include <asm/io.h>
#include <pci.h>
#include <video_fb.h>
#include "videomodes.h"
#include <mb862xx.h>

#if defined(CONFIG_POST)
#include <post.h>
#endif

/*
 * Graphic Device
 */
GraphicDevice mb862xx;

/*
 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
 */
#define VIDEO_MEM_SIZE	0x01FC0000

#if defined(CONFIG_PCI)
#if defined(CONFIG_VIDEO_CORALP)

static struct pci_device_id supported[] = {
	{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
	{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
	{ }
};

/* Internal clock frequency divider table, index is mode number */
unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
#endif
#endif

#if defined(CONFIG_VIDEO_CORALP)
#define	rd_io		in32r
#define	wr_io		out32r
#else
#define	rd_io(addr)	in_be32((volatile unsigned *)(addr))
#define	wr_io(addr, val)	out_be32((volatile unsigned *)(addr), (val))
#endif

#define HOST_RD_REG(off)	rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
#define HOST_WR_REG(off, val)	wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
				      (val))
#define DISP_RD_REG(off)	rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
#define DISP_WR_REG(off, val)	wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
				      (val))
#define DE_RD_REG(off)		rd_io((dev->dprBase + (off)))
#define DE_WR_REG(off, val)	wr_io((dev->dprBase + (off)), (val))

#if defined(CONFIG_VIDEO_CORALP)
#define DE_WR_FIFO(val)		wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
#else
#define DE_WR_FIFO(val)		wr_io((dev->dprBase + (GC_FIFO)), (val))
#endif

#define L0PAL_WR_REG(idx, val)	wr_io((dev->frameAdrs + \
				       (GC_DISP_BASE | GC_L0PAL0) + \
				       ((idx) << 2)), (val))

#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
static void gdc_sw_reset (void)
{
	GraphicDevice *dev = &mb862xx;

	HOST_WR_REG (GC_SRST, 0x1);
	udelay (500);
	video_hw_init ();
}


static void de_wait (void)
{
	GraphicDevice *dev = &mb862xx;
	int lc = 0x10000;

	/*
	 * Sync with software writes to framebuffer,
	 * try to reset if engine locked
	 */
	while (DE_RD_REG (GC_CTR) & 0x00000131)
		if (lc-- < 0) {
			gdc_sw_reset ();
			puts ("gdc reset done after drawing engine lock.\n");
			break;
		}
}

static void de_wait_slots (int slots)
{
	GraphicDevice *dev = &mb862xx;
	int lc = 0x10000;

	/* Wait for free fifo slots */
	while (DE_RD_REG (GC_IFCNT) < slots)
		if (lc-- < 0) {
			gdc_sw_reset ();
			puts ("gdc reset done after drawing engine lock.\n");
			break;
		}
}
#endif

#if !defined(CONFIG_VIDEO_CORALP)
static void board_disp_init (void)
{
	GraphicDevice *dev = &mb862xx;
	const gdc_regs *regs = board_get_regs ();

	while (regs->index) {
		DISP_WR_REG (regs->index, regs->value);
		regs++;
	}
}
#endif

/*
 * Init drawing engine if accel enabled.
 * Also clears visible framebuffer.
 */
static void de_init (void)
{
	GraphicDevice *dev = &mb862xx;
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
	int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;

	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;

	/* Setup mode and fbbase, xres, fg, bg */
	de_wait_slots (2);
	DE_WR_FIFO (0xf1010108);
	DE_WR_FIFO (cf | 0x0300);
	DE_WR_REG (GC_FBR, 0x0);
	DE_WR_REG (GC_XRES, dev->winSizeX);
	DE_WR_REG (GC_FC, 0x0);
	DE_WR_REG (GC_BC, 0x0);
	/* Reset clipping */
	DE_WR_REG (GC_CXMIN, 0x0);
	DE_WR_REG (GC_CXMAX, dev->winSizeX);
	DE_WR_REG (GC_CYMIN, 0x0);
	DE_WR_REG (GC_CYMAX, dev->winSizeY);

	/* Clear framebuffer using drawing engine */
	de_wait_slots (3);
	DE_WR_FIFO (0x09410000);
	DE_WR_FIFO (0x00000000);
	DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
	/* sync with SW access to framebuffer */
	de_wait ();
#else
	unsigned int i, *p;

	i = dev->winSizeX * dev->winSizeY;
	p = (unsigned int *)dev->frameAdrs;
	while (i--)
		*p++ = 0;
#endif
}

#if defined(CONFIG_VIDEO_CORALP)
/* use CCF and MMR parameters for Coral-P Eval. Board as default */
#ifndef CONFIG_SYS_MB862xx_CCF
#define CONFIG_SYS_MB862xx_CCF	0x00090000
#endif
#ifndef CONFIG_SYS_MB862xx_MMR
#define CONFIG_SYS_MB862xx_MMR	0x11d7fa13
#endif

unsigned int pci_video_init (void)
{
	GraphicDevice *dev = &mb862xx;
	pci_dev_t devbusfn;
	u16 device;

	if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
		puts("controller not present\n");
		return 0;
	}

	/* PCI setup */
	pci_write_config_dword (devbusfn, PCI_COMMAND,
				(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
	dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);

	if (dev->frameAdrs == 0) {
		puts ("PCI config: failed to get base address\n");
		return 0;
	}

	dev->pciBase = dev->frameAdrs;

	puts("Coral-");

	pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
	switch (device) {
	case PCI_DEVICE_ID_CORAL_P:
		puts("P\n");
		break;
	case PCI_DEVICE_ID_CORAL_PA:
		puts("PA\n");
		break;
	default:
		puts("Unknown\n");
		return 0;
	}

	/* Setup clocks and memory mode for Coral-P(A) */
	HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
	udelay (200);
	HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
	udelay (100);
	return dev->frameAdrs;
}

unsigned int card_init (void)
{
	GraphicDevice *dev = &mb862xx;
	unsigned int cf, videomode, div = 0;
	unsigned long t1, hsync, vsync;
	char *penv;
	int tmp, i, bpp;
	struct ctfb_res_modes *res_mode;
	struct ctfb_res_modes var_mode;

	memset (dev, 0, sizeof (GraphicDevice));

	if (!pci_video_init ())
		return 0;

	tmp = 0;
	videomode = 0x310;
	/* get video mode via environment */
	penv = env_get("videomode");
	if (penv) {
		/* decide if it is a string */
		if (penv[0] <= '9') {
			videomode = (int) simple_strtoul (penv, NULL, 16);
			tmp = 1;
		}
	} else {
		tmp = 1;
	}

	if (tmp) {
		/* parameter are vesa modes, search params */
		for (i = 0; i < VESA_MODES_COUNT; i++) {
			if (vesa_modes[i].vesanr == videomode)
				break;
		}
		if (i == VESA_MODES_COUNT) {
			printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
				videomode);
			i = 0;
		}
		res_mode = (struct ctfb_res_modes *)
			   &res_mode_init[vesa_modes[i].resindex];
		if (vesa_modes[i].resindex > 2) {
			puts ("\tUnsupported resolution, using default\n");
			bpp = vesa_modes[1].bits_per_pixel;
			div = fr_div[1];
		}
		bpp = vesa_modes[i].bits_per_pixel;
		div = fr_div[vesa_modes[i].resindex];
	} else {
		res_mode = (struct ctfb_res_modes *) &var_mode;
		bpp = video_get_params (res_mode, penv);
	}

	/* calculate hsync and vsync freq (info only) */
	t1 = (res_mode->left_margin + res_mode->xres +
	      res_mode->right_margin + res_mode->hsync_len) / 8;
	t1 *= 8;
	t1 *= res_mode->pixclock;
	t1 /= 1000;
	hsync = 1000000000L / t1;
	t1 *= (res_mode->upper_margin + res_mode->yres +
	       res_mode->lower_margin + res_mode->vsync_len);
	t1 /= 1000;
	vsync = 1000000000L / t1;

	/* fill in Graphic device struct */
	sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
		 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
	printf ("\t%s\n", dev->modeIdent);
	dev->winSizeX = res_mode->xres;
	dev->winSizeY = res_mode->yres;
	dev->memSize = VIDEO_MEM_SIZE;

	switch (bpp) {
	case 8:
		dev->gdfIndex = GDF__8BIT_INDEX;
		dev->gdfBytesPP = 1;
		break;
	case 15:
	case 16:
		dev->gdfIndex = GDF_15BIT_555RGB;
		dev->gdfBytesPP = 2;
		break;
	default:
		printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
			bpp);
		puts ("\tfallback to 15bpp\n");
		dev->gdfIndex = GDF_15BIT_555RGB;
		dev->gdfBytesPP = 2;
	}

	/* Setup dot clock (internal pll, division rate) */
	DISP_WR_REG (GC_DCM1, div);
	/* L0 init */
	cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
	DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
			     (dev->winSizeY - 1) | cf);
	DISP_WR_REG (GC_L0OA0, 0x0);
	DISP_WR_REG (GC_L0DA0, 0x0);
	DISP_WR_REG (GC_L0DY_L0DX, 0x0);
	DISP_WR_REG (GC_L0EM, 0x0);
	DISP_WR_REG (GC_L0WY_L0WX, 0x0);
	DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);

	/* Display timing init */
	DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
				res_mode->left_margin +
				res_mode->right_margin +
				res_mode->hsync_len - 1) << 16);
	DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
				   (dev->winSizeX - 1));
	DISP_WR_REG (GC_VSW_HSW_HSP_A,  (res_mode->vsync_len - 1) << 24 |
					(res_mode->hsync_len - 1) << 16 |
					(dev->winSizeX +
					 res_mode->right_margin - 1));
	DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
				res_mode->upper_margin +
				res_mode->vsync_len - 1) << 16);
	DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
				   (dev->winSizeY +
				    res_mode->lower_margin - 1));
	DISP_WR_REG (GC_WY_WX, 0x0);
	DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
	/* Display enable, L0 layer */
	DISP_WR_REG (GC_DCM1, 0x80010000 | div);

	return dev->frameAdrs;
}
#endif


#if !defined(CONFIG_VIDEO_CORALP)
int mb862xx_probe(unsigned int addr)
{
	GraphicDevice *dev = &mb862xx;
	unsigned int reg;

	dev->frameAdrs = addr;
	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;

	/* Try to access GDC ID/Revision registers */
	reg = HOST_RD_REG (GC_CID);
	reg = HOST_RD_REG (GC_CID);
	if (reg == 0x303) {
		reg = DE_RD_REG(GC_REV);
		reg = DE_RD_REG(GC_REV);
		if ((reg & ~0xff) == 0x20050100)
			return MB862XX_TYPE_LIME;
	}

	return 0;
}
#endif

void *video_hw_init (void)
{
	GraphicDevice *dev = &mb862xx;

	puts ("Video: Fujitsu ");

	memset (dev, 0, sizeof (GraphicDevice));

#if defined(CONFIG_VIDEO_CORALP)
	if (card_init () == 0)
		return NULL;
#else
	/*
	 * Preliminary init of the onboard graphic controller,
	 * retrieve base address
	 */
	if ((dev->frameAdrs = board_video_init ()) == 0) {
		puts ("Controller not found!\n");
		return NULL;
	} else {
		puts ("Lime\n");

		/* Set Change of Clock Frequency Register */
		HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
		/* Delay required */
		udelay(300);
		/* Set Memory I/F Mode Register) */
		HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
	}
#endif

	de_init ();

#if !defined(CONFIG_VIDEO_CORALP)
	board_disp_init ();
#endif

#if (defined(CONFIG_LWMON5) || \
     defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
	/* Lamp on */
	board_backlight_switch (1);
#endif

	return dev;
}

/*
 * Set a RGB color in the LUT
 */
void video_set_lut (unsigned int index, unsigned char r,
		    unsigned char g, unsigned char b)
{
	GraphicDevice *dev = &mb862xx;

	L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
}

#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
/*
 * Drawing engine Fill and BitBlt screen region
 */
void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
			unsigned int dst_y, unsigned int dim_x,
			unsigned int dim_y, unsigned int color)
{
	GraphicDevice *dev = &mb862xx;

	de_wait_slots (3);
	DE_WR_REG (GC_FC, color);
	DE_WR_FIFO (0x09410000);
	DE_WR_FIFO ((dst_y << 16) | dst_x);
	DE_WR_FIFO ((dim_y << 16) | dim_x);
	de_wait ();
}

void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
		      unsigned int src_y, unsigned int dst_x,
		      unsigned int dst_y, unsigned int width,
		      unsigned int height)
{
	GraphicDevice *dev = &mb862xx;
	unsigned int ctrl = 0x0d000000L;

	if (src_x >= dst_x && src_y >= dst_y)
		ctrl |= 0x00440000L;
	else if (src_x >= dst_x && src_y <= dst_y)
		ctrl |= 0x00460000L;
	else if (src_x <= dst_x && src_y >= dst_y)
		ctrl |= 0x00450000L;
	else
		ctrl |= 0x00470000L;

	de_wait_slots (4);
	DE_WR_FIFO (ctrl);
	DE_WR_FIFO ((src_y << 16) | src_x);
	DE_WR_FIFO ((dst_y << 16) | dst_x);
	DE_WR_FIFO ((height << 16) | width);
	de_wait (); /* sync */
}
#endif
Commit	Line	Data
bed53753 AG	1	/*
	2	* (C) Copyright 2007
	3	* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
bed53753 AG	6	*/
	7
	8	/*
	9	* mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
	10	* PCI and video mode code was derived from smiLynxEM driver.
	11	*/
	12
	13	#include <common.h>
	14
bed53753 AG	15	#include <asm/io.h>
	16	#include <pci.h>
	17	#include <video_fb.h>
	18	#include "videomodes.h"
	19	#include <mb862xx.h>
	20
0d48926c YT	21	#if defined(CONFIG_POST)
	22	#include <post.h>
	23	#endif
e8652867	24
bed53753 AG	25	/*
	26	* Graphic Device
	27	*/
	28	GraphicDevice mb862xx;
	29
	30	/*
	31	* 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
	32	*/
	33	#define VIDEO_MEM_SIZE 0x01FC0000
	34
	35	#if defined(CONFIG_PCI)
	36	#if defined(CONFIG_VIDEO_CORALP)
	37
	38	static struct pci_device_id supported[] = {
	39	{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
	40	{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
	41	{ }
	42	};
	43
	44	/* Internal clock frequency divider table, index is mode number */
	45	unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
	46	#endif
	47	#endif
	48
	49	#if defined(CONFIG_VIDEO_CORALP)
	50	#define rd_io in32r
	51	#define wr_io out32r
	52	#else
e8652867 AG	53	#define rd_io(addr) in_be32((volatile unsigned *)(addr))
e8652867 AG	54	#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
bed53753 AG	55	#endif
bed53753 AG	56
cce99b2a AG	57	#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
cce99b2a AG	58	#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
e8652867	59	(val))
cce99b2a AG	60	#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
cce99b2a AG	61	#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
e8652867 AG	62	(val))
	63	#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
	64	#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
bed53753 AG	65
bed53753 AG	66	#if defined(CONFIG_VIDEO_CORALP)
cce99b2a	67	#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
bed53753	68	#else
cce99b2a	69	#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
bed53753 AG	70	#endif
bed53753 AG	71
cce99b2a AG	72	#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
cce99b2a AG	73	(GC_DISP_BASE \| GC_L0PAL0) + \
e8652867	74	((idx) << 2)), (val))
bed53753	75
5d16ca87	76	#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
e8652867	77	static void gdc_sw_reset (void)
bed53753	78	{
e8652867 AG	79	GraphicDevice *dev = &mb862xx;
e8652867 AG	80
cce99b2a	81	HOST_WR_REG (GC_SRST, 0x1);
bed53753 AG	82	udelay (500);
	83	video_hw_init ();
	84	}
	85
	86
e8652867	87	static void de_wait (void)
bed53753	88	{
e8652867	89	GraphicDevice *dev = &mb862xx;
bed53753 AG	90	int lc = 0x10000;
bed53753 AG	91
e8652867 AG	92	/*
	93	* Sync with software writes to framebuffer,
	94	* try to reset if engine locked
	95	*/
cce99b2a	96	while (DE_RD_REG (GC_CTR) & 0x00000131)
bed53753 AG	97	if (lc-- < 0) {
bed53753 AG	98	gdc_sw_reset ();
9d173e02	99	puts ("gdc reset done after drawing engine lock.\n");
bed53753 AG	100	break;
	101	}
	102	}
	103
e8652867	104	static void de_wait_slots (int slots)
bed53753	105	{
e8652867	106	GraphicDevice *dev = &mb862xx;
bed53753 AG	107	int lc = 0x10000;
	108
	109	/* Wait for free fifo slots */
cce99b2a	110	while (DE_RD_REG (GC_IFCNT) < slots)
bed53753 AG	111	if (lc-- < 0) {
bed53753 AG	112	gdc_sw_reset ();
9d173e02	113	puts ("gdc reset done after drawing engine lock.\n");
bed53753 AG	114	break;
	115	}
	116	}
5d16ca87	117	#endif
bed53753 AG	118
bed53753 AG	119	#if !defined(CONFIG_VIDEO_CORALP)
e8652867	120	static void board_disp_init (void)
bed53753	121	{
e8652867	122	GraphicDevice *dev = &mb862xx;
bed53753 AG	123	const gdc_regs *regs = board_get_regs ();
	124
	125	while (regs->index) {
	126	DISP_WR_REG (regs->index, regs->value);
	127	regs++;
	128	}
	129	}
	130	#endif
	131
	132	/*
5d16ca87 AG	133	* Init drawing engine if accel enabled.
5d16ca87 AG	134	* Also clears visible framebuffer.
bed53753 AG	135	*/
	136	static void de_init (void)
	137	{
e8652867	138	GraphicDevice *dev = &mb862xx;
5d16ca87	139	#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
e8652867	140	int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
bed53753	141
cce99b2a	142	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
bed53753 AG	143
	144	/* Setup mode and fbbase, xres, fg, bg */
	145	de_wait_slots (2);
	146	DE_WR_FIFO (0xf1010108);
	147	DE_WR_FIFO (cf \| 0x0300);
cce99b2a AG	148	DE_WR_REG (GC_FBR, 0x0);
	149	DE_WR_REG (GC_XRES, dev->winSizeX);
	150	DE_WR_REG (GC_FC, 0x0);
	151	DE_WR_REG (GC_BC, 0x0);
bed53753	152	/* Reset clipping */
cce99b2a AG	153	DE_WR_REG (GC_CXMIN, 0x0);
	154	DE_WR_REG (GC_CXMAX, dev->winSizeX);
	155	DE_WR_REG (GC_CYMIN, 0x0);
	156	DE_WR_REG (GC_CYMAX, dev->winSizeY);
bed53753 AG	157
	158	/* Clear framebuffer using drawing engine */
	159	de_wait_slots (3);
	160	DE_WR_FIFO (0x09410000);
	161	DE_WR_FIFO (0x00000000);
e8652867	162	DE_WR_FIFO (dev->winSizeY << 16 \| dev->winSizeX);
322716a1 AG	163	/* sync with SW access to framebuffer */
322716a1 AG	164	de_wait ();
5d16ca87 AG	165	#else
	166	unsigned int i, *p;
	167
	168	i = dev->winSizeX * dev->winSizeY;
	169	p = (unsigned int *)dev->frameAdrs;
	170	while (i--)
	171	*p++ = 0;
	172	#endif
bed53753 AG	173	}
	174
	175	#if defined(CONFIG_VIDEO_CORALP)
d7ffd27a AG	176	/* use CCF and MMR parameters for Coral-P Eval. Board as default */
	177	#ifndef CONFIG_SYS_MB862xx_CCF
	178	#define CONFIG_SYS_MB862xx_CCF 0x00090000
	179	#endif
	180	#ifndef CONFIG_SYS_MB862xx_MMR
	181	#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
	182	#endif
	183
e8652867	184	unsigned int pci_video_init (void)
bed53753	185	{
e8652867	186	GraphicDevice *dev = &mb862xx;
bed53753	187	pci_dev_t devbusfn;
d7ffd27a	188	u16 device;
bed53753	189
e8652867	190	if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
01b0f500	191	puts("controller not present\n");
bed53753 AG	192	return 0;
	193	}
	194
	195	/* PCI setup */
e8652867 AG	196	pci_write_config_dword (devbusfn, PCI_COMMAND,
	197	(PCI_COMMAND_MEMORY \| PCI_COMMAND_IO));
	198	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
	199	dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
bed53753	200
e8652867	201	if (dev->frameAdrs == 0) {
9d173e02	202	puts ("PCI config: failed to get base address\n");
bed53753 AG	203	return 0;
	204	}
	205
e8652867	206	dev->pciBase = dev->frameAdrs;
bed53753	207
d7ffd27a AG	208	puts("Coral-");
	209
	210	pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
	211	switch (device) {
	212	case PCI_DEVICE_ID_CORAL_P:
	213	puts("P\n");
	214	break;
	215	case PCI_DEVICE_ID_CORAL_PA:
	216	puts("PA\n");
	217	break;
	218	default:
	219	puts("Unknown\n");
	220	return 0;
	221	}
	222
	223	/* Setup clocks and memory mode for Coral-P(A) */
	224	HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
bed53753	225	udelay (200);
d7ffd27a	226	HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
bed53753	227	udelay (100);
e8652867	228	return dev->frameAdrs;
bed53753 AG	229	}
	230
	231	unsigned int card_init (void)
	232	{
e8652867	233	GraphicDevice *dev = &mb862xx;
bed53753 AG	234	unsigned int cf, videomode, div = 0;
	235	unsigned long t1, hsync, vsync;
	236	char *penv;
	237	int tmp, i, bpp;
	238	struct ctfb_res_modes *res_mode;
	239	struct ctfb_res_modes var_mode;
	240
e8652867	241	memset (dev, 0, sizeof (GraphicDevice));
bed53753	242
e8652867	243	if (!pci_video_init ())
bed53753	244	return 0;
bed53753	245
bed53753 AG	246	tmp = 0;
	247	videomode = 0x310;
	248	/* get video mode via environment */
00caae6d SG	249	penv = env_get("videomode");
00caae6d SG	250	if (penv) {
e8652867	251	/* decide if it is a string */
bed53753 AG	252	if (penv[0] <= '9') {
	253	videomode = (int) simple_strtoul (penv, NULL, 16);
	254	tmp = 1;
	255	}
	256	} else {
	257	tmp = 1;
	258	}
e8652867	259
bed53753	260	if (tmp) {
e8652867	261	/* parameter are vesa modes, search params */
bed53753 AG	262	for (i = 0; i < VESA_MODES_COUNT; i++) {
	263	if (vesa_modes[i].vesanr == videomode)
	264	break;
	265	}
	266	if (i == VESA_MODES_COUNT) {
e8652867 AG	267	printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
e8652867 AG	268	videomode);
bed53753 AG	269	i = 0;
bed53753 AG	270	}
e8652867 AG	271	res_mode = (struct ctfb_res_modes *)
e8652867 AG	272	&res_mode_init[vesa_modes[i].resindex];
bed53753	273	if (vesa_modes[i].resindex > 2) {
9d173e02	274	puts ("\tUnsupported resolution, using default\n");
bed53753 AG	275	bpp = vesa_modes[1].bits_per_pixel;
	276	div = fr_div[1];
	277	}
	278	bpp = vesa_modes[i].bits_per_pixel;
	279	div = fr_div[vesa_modes[i].resindex];
	280	} else {
bed53753 AG	281	res_mode = (struct ctfb_res_modes *) &var_mode;
	282	bpp = video_get_params (res_mode, penv);
	283	}
	284
	285	/* calculate hsync and vsync freq (info only) */
	286	t1 = (res_mode->left_margin + res_mode->xres +
	287	res_mode->right_margin + res_mode->hsync_len) / 8;
	288	t1 *= 8;
	289	t1 *= res_mode->pixclock;
	290	t1 /= 1000;
	291	hsync = 1000000000L / t1;
	292	t1 *= (res_mode->upper_margin + res_mode->yres +
	293	res_mode->lower_margin + res_mode->vsync_len);
	294	t1 /= 1000;
	295	vsync = 1000000000L / t1;
	296
	297	/* fill in Graphic device struct */
e8652867	298	sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
bed53753	299	res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
e8652867 AG	300	printf ("\t%s\n", dev->modeIdent);
	301	dev->winSizeX = res_mode->xres;
	302	dev->winSizeY = res_mode->yres;
	303	dev->memSize = VIDEO_MEM_SIZE;
bed53753 AG	304
	305	switch (bpp) {
	306	case 8:
e8652867 AG	307	dev->gdfIndex = GDF__8BIT_INDEX;
e8652867 AG	308	dev->gdfBytesPP = 1;
bed53753 AG	309	break;
	310	case 15:
	311	case 16:
e8652867 AG	312	dev->gdfIndex = GDF_15BIT_555RGB;
e8652867 AG	313	dev->gdfBytesPP = 2;
bed53753 AG	314	break;
bed53753 AG	315	default:
e8652867 AG	316	printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
e8652867 AG	317	bpp);
9d173e02	318	puts ("\tfallback to 15bpp\n");
e8652867 AG	319	dev->gdfIndex = GDF_15BIT_555RGB;
e8652867 AG	320	dev->gdfBytesPP = 2;
bed53753 AG	321	}
	322
	323	/* Setup dot clock (internal pll, division rate) */
cce99b2a	324	DISP_WR_REG (GC_DCM1, div);
bed53753	325	/* L0 init */
e8652867	326	cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
cce99b2a	327	DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 \|
e8652867	328	(dev->winSizeY - 1) \| cf);
cce99b2a AG	329	DISP_WR_REG (GC_L0OA0, 0x0);
	330	DISP_WR_REG (GC_L0DA0, 0x0);
	331	DISP_WR_REG (GC_L0DY_L0DX, 0x0);
	332	DISP_WR_REG (GC_L0EM, 0x0);
	333	DISP_WR_REG (GC_L0WY_L0WX, 0x0);
	334	DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 \| dev->winSizeX);
bed53753 AG	335
bed53753 AG	336	/* Display timing init */
cce99b2a AG	337	DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
	338	res_mode->left_margin +
	339	res_mode->right_margin +
	340	res_mode->hsync_len - 1) << 16);
	341	DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 \|
	342	(dev->winSizeX - 1));
	343	DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 \|
	344	(res_mode->hsync_len - 1) << 16 \|
	345	(dev->winSizeX +
	346	res_mode->right_margin - 1));
	347	DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
	348	res_mode->upper_margin +
	349	res_mode->vsync_len - 1) << 16);
	350	DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 \|
	351	(dev->winSizeY +
	352	res_mode->lower_margin - 1));
	353	DISP_WR_REG (GC_WY_WX, 0x0);
	354	DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 \| dev->winSizeX);
bed53753	355	/* Display enable, L0 layer */
cce99b2a	356	DISP_WR_REG (GC_DCM1, 0x80010000 \| div);
bed53753	357
e8652867	358	return dev->frameAdrs;
bed53753 AG	359	}
	360	#endif
	361
c28d3bbe WG	362
	363	#if !defined(CONFIG_VIDEO_CORALP)
	364	int mb862xx_probe(unsigned int addr)
	365	{
	366	GraphicDevice *dev = &mb862xx;
	367	unsigned int reg;
	368
	369	dev->frameAdrs = addr;
	370	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
	371
	372	/* Try to access GDC ID/Revision registers */
	373	reg = HOST_RD_REG (GC_CID);
	374	reg = HOST_RD_REG (GC_CID);
	375	if (reg == 0x303) {
	376	reg = DE_RD_REG(GC_REV);
	377	reg = DE_RD_REG(GC_REV);
	378	if ((reg & ~0xff) == 0x20050100)
	379	return MB862XX_TYPE_LIME;
	380	}
	381
	382	return 0;
	383	}
	384	#endif
	385
bed53753 AG	386	void *video_hw_init (void)
bed53753 AG	387	{
e8652867	388	GraphicDevice *dev = &mb862xx;
bed53753	389
9d173e02	390	puts ("Video: Fujitsu ");
bed53753	391
e8652867	392	memset (dev, 0, sizeof (GraphicDevice));
bed53753 AG	393
bed53753 AG	394	#if defined(CONFIG_VIDEO_CORALP)
e8652867 AG	395	if (card_init () == 0)
e8652867 AG	396	return NULL;
bed53753	397	#else
e8652867 AG	398	/*
	399	* Preliminary init of the onboard graphic controller,
	400	* retrieve base address
	401	*/
	402	if ((dev->frameAdrs = board_video_init ()) == 0) {
9d173e02	403	puts ("Controller not found!\n");
e8652867	404	return NULL;
c28d3bbe	405	} else {
9d173e02	406	puts ("Lime\n");
c28d3bbe WG	407
	408	/* Set Change of Clock Frequency Register */
	409	HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
	410	/* Delay required */
	411	udelay(300);
	412	/* Set Memory I/F Mode Register) */
	413	HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
	414	}
bed53753 AG	415	#endif
	416
	417	de_init ();
	418
	419	#if !defined(CONFIG_VIDEO_CORALP)
e8652867	420	board_disp_init ();
bed53753 AG	421	#endif
bed53753 AG	422
04386f65 SR	423	#if (defined(CONFIG_LWMON5) \|\| \
04386f65 SR	424	defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
bed53753 AG	425	/* Lamp on */
	426	board_backlight_switch (1);
	427	#endif
	428
e8652867	429	return dev;
bed53753 AG	430	}
	431
	432	/*
	433	* Set a RGB color in the LUT
	434	*/
e8652867 AG	435	void video_set_lut (unsigned int index, unsigned char r,
e8652867 AG	436	unsigned char g, unsigned char b)
bed53753	437	{
e8652867	438	GraphicDevice *dev = &mb862xx;
bed53753 AG	439
	440	L0PAL_WR_REG (index, (r << 16) \| (g << 8) \| (b));
	441	}
	442
5d16ca87	443	#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
bed53753 AG	444	/*
	445	* Drawing engine Fill and BitBlt screen region
	446	*/
e8652867 AG	447	void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
	448	unsigned int dst_y, unsigned int dim_x,
	449	unsigned int dim_y, unsigned int color)
bed53753	450	{
e8652867	451	GraphicDevice *dev = &mb862xx;
bed53753 AG	452
bed53753 AG	453	de_wait_slots (3);
cce99b2a	454	DE_WR_REG (GC_FC, color);
bed53753 AG	455	DE_WR_FIFO (0x09410000);
	456	DE_WR_FIFO ((dst_y << 16) \| dst_x);
	457	DE_WR_FIFO ((dim_y << 16) \| dim_x);
	458	de_wait ();
	459	}
	460
e8652867 AG	461	void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
	462	unsigned int src_y, unsigned int dst_x,
	463	unsigned int dst_y, unsigned int width,
bed53753 AG	464	unsigned int height)
bed53753 AG	465	{
e8652867	466	GraphicDevice *dev = &mb862xx;
bed53753 AG	467	unsigned int ctrl = 0x0d000000L;
	468
	469	if (src_x >= dst_x && src_y >= dst_y)
	470	ctrl \|= 0x00440000L;
	471	else if (src_x >= dst_x && src_y <= dst_y)
	472	ctrl \|= 0x00460000L;
	473	else if (src_x <= dst_x && src_y >= dst_y)
	474	ctrl \|= 0x00450000L;
	475	else
	476	ctrl \|= 0x00470000L;
	477
	478	de_wait_slots (4);
	479	DE_WR_FIFO (ctrl);
	480	DE_WR_FIFO ((src_y << 16) \| src_x);
	481	DE_WR_FIFO ((dst_y << 16) \| dst_x);
	482	DE_WR_FIFO ((height << 16) \| width);
	483	de_wait (); /* sync */
	484	}
5d16ca87	485	#endif