[thirdparty/u-boot.git] / drivers / video / mpc8xx_lcd.c

/*
 * (C) Copyright 2001-2002
 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************/
/* ** HEADER FILES							*/
/************************************************************************/

/* #define DEBUG */

#include <config.h>
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <version.h>
#include <stdarg.h>
#include <lcdvideo.h>
#include <linux/types.h>
#include <stdio_dev.h>
#if defined(CONFIG_POST)
#include <post.h>
#endif
#include <lcd.h>

#ifdef CONFIG_LCD

/************************************************************************/
/* ** CONFIG STUFF -- should be moved to board config file		*/
/************************************************************************/
#ifndef CONFIG_LCD_INFO
#define CONFIG_LCD_INFO		/* Display Logo, (C) and system info	*/
#endif

#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
#undef CONFIG_LCD_LOGO
#undef CONFIG_LCD_INFO
#endif

/*----------------------------------------------------------------------*/
#ifdef CONFIG_KYOCERA_KCS057QV1AJ
/*
 *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
 */
#define LCD_BPP	LCD_COLOR4

vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SP19X001_Z1A
/*
 *  Hitachi SP19X001-. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_HITACHI_SP19X001_Z1A */
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
#ifdef CONFIG_NEC_NL6448AC33
/*
 *  NEC NL6448AC33-18. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448AC33 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_NEC_NL6448BC20
/*
 *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC20 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_NEC_NL6448BC33_54
/*
 *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC33_54 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_LQ104V7DS01
/*
 *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
    3, 0, 0, 1, 1, 25, 1, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ104V7DS01 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_16x9
/*
 * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
 * not sure what it is.......
 */
vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 15, 4, 0, 3
};
#endif /* CONFIG_SHARP_16x9 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_LQ057Q3DC02
/*
 * Sharp LQ057Q3DC02 display. Active, color, single scan.
 */
#undef LCD_DF
#define LCD_DF 12

vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 15, 4, 0, 3
		/* wbl, vpw, lcdac, wbf */
};
#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ057Q3DC02 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_LQ64D341
/*
 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 128, 16, 0, 32
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ64D341 */

#ifdef CONFIG_SHARP_LQ065T9DR51U
/*
 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
 */
vidinfo_t panel_info = {
    400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 248, 4, 0, 35
		/* wbl, vpw, lcdac, wbf */
};
#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ065T9DR51U */

#ifdef CONFIG_SHARP_LQ084V1DG21
/*
 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
    3, 0, 0, 1, 1, 160, 3, 0, 48
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ084V1DG21 */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_HLD1045
/*
 * HLD1045 display, 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 160, 3, 0, 48
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_HLD1045 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_PRIMEVIEW_V16C6448AC
/*
 * Prime View V16C6448AC
 */
vidinfo_t panel_info = {
    640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 35
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_PRIMEVIEW_V16C6448AC */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_OPTREX_BW
/*
 * Optrex   CBL50840-2 NF-FW 99 22 M5
 * or
 * Hitachi  LMG6912RPFC-00T
 * or
 * Hitachi  SP14Q002
 *
 * 320x240. Black & white.
 */
#define OPTREX_BPP	0	/* 0 - monochrome,     1 bpp */
				/* 1 -  4 grey levels, 2 bpp */
				/* 2 - 16 grey levels, 4 bpp */
vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
    OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
};
#endif /* CONFIG_OPTREX_BW */

/*-----------------------------------------------------------------*/
#ifdef CONFIG_EDT32F10
/*
 * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
 */
#define LCD_BPP		LCD_MONOCHROME
#define LCD_DF		10

vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
    LCD_BPP,  0, 0, 0, 0, 33, 0, 0, 0
};
#endif

/************************************************************************/
/* ----------------- chipset specific functions ----------------------- */
/************************************************************************/

/*
 * Calculate fb size for VIDEOLFB_ATAG.
 */
ulong calc_fbsize (void)
{
	ulong size;
	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;

	size = line_length * panel_info.vl_row;

	return size;
}

void lcd_ctrl_init (void *lcdbase)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile lcd823_t *lcdp = &immr->im_lcd;

	uint lccrtmp;
	uint lchcr_hpc_tmp;

	/* Initialize the LCD control register according to the LCD
	 * parameters defined.  We do everything here but enable
	 * the controller.
	 */

#ifdef CONFIG_RPXLITE
	/* This is special for RPXlite_DW Software Development Platform **[Sam]** */
	panel_info.vl_dp = CONFIG_SYS_LOW;
#endif

	lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
		   (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));

	lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)	|
		   LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)	|
		   LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)	|
		   LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)	|
		   LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)	|
		   LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)	|
		   LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)	|
		   LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)	|
		   LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)	|
		   LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);

#if 0
	lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
	lccrtmp |= LCCR_EIEN;
#endif

	lcdp->lcd_lccr = lccrtmp;
	lcdp->lcd_lcsr = 0xFF;		/* Clear pending interrupts */

	/* Initialize LCD controller bus priorities.
	 */
#ifdef CONFIG_RBC823
	immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1;	/* RAID = 01, LAID = 00 */
#else
	immr->im_siu_conf.sc_sdcr &= ~0x0f;	/* RAID = LAID = 0 */

	/* set SHFT/CLOCK division factor 4
	 * This needs to be set based upon display type and processor
	 * speed.  The TFT displays run about 20 to 30 MHz.
	 * I was running 64 MHz processor speed.
	 * The value for this divider must be chosen so the result is
	 * an integer of the processor speed (i.e., divide by 3 with
	 * 64 MHz would be bad).
	 */
	immr->im_clkrst.car_sccr &= ~0x1F;
	immr->im_clkrst.car_sccr |= LCD_DF;	/* was 8 */

#endif /* CONFIG_RBC823 */

#if defined(CONFIG_RBC823)
	/* Enable LCD on port D.
	 */
	immr->im_ioport.iop_pddat &= 0x0300;
	immr->im_ioport.iop_pdpar |= 0x1CFF;
	immr->im_ioport.iop_pddir |= 0x1CFF;

	/* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
	 */
	immr->im_cpm.cp_pbdat &= ~0x00005001;
	immr->im_cpm.cp_pbpar &= ~0x00005001;
	immr->im_cpm.cp_pbdir |=  0x00005001;
#elif !defined(CONFIG_EDT32F10)
	/* Enable LCD on port D.
	 */
	immr->im_ioport.iop_pdpar |= 0x1FFF;
	immr->im_ioport.iop_pddir |= 0x1FFF;

	/* Enable LCD_A/B/C on port B.
	 */
	immr->im_cpm.cp_pbpar |= 0x00005001;
	immr->im_cpm.cp_pbdir |= 0x00005001;
#else
	/* Enable LCD on port D.
	 */
	immr->im_ioport.iop_pdpar |= 0x1DFF;
	immr->im_ioport.iop_pdpar &= ~0x0200;
	immr->im_ioport.iop_pddir |= 0x1FFF;
	immr->im_ioport.iop_pddat |= 0x0200;
#endif

	/* Load the physical address of the linear frame buffer
	 * into the LCD controller.
	 * BIG NOTE:  This has to be modified to load A and B depending
	 * upon the split mode of the LCD.
	 */
	lcdp->lcd_lcfaa = (ulong)lcdbase;
	lcdp->lcd_lcfba = (ulong)lcdbase;

	/* MORE HACKS...This must be updated according to 823 manual
	 * for different panels.
	 * Udi Finkelstein - done - see below:
	 * Note: You better not try unsupported combinations such as
	 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
	 */
	lchcr_hpc_tmp =
		(panel_info.vl_col *
		 (panel_info.vl_tft ? 8 :
			(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
			 /* use << to mult by: single scan = 1, dual scan = 2 */
			  panel_info.vl_splt) *
			 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */

	lcdp->lcd_lchcr = LCHCR_BO |
			  LCDBIT (LCHCR_AT_BIT, 4) |
			  LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
			  panel_info.vl_wbl;

	lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
			  LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
			  LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
			  panel_info.vl_wbf;

}

/*----------------------------------------------------------------------*/

#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = &(immr->im_cpm);
	unsigned short colreg, *cmap_ptr;

	cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];

	colreg = ((red   & 0x0F) << 8) |
		 ((green & 0x0F) << 4) |
		  (blue  & 0x0F) ;
#ifdef	CONFIG_SYS_INVERT_COLORS
	colreg ^= 0x0FFF;
#endif
	*cmap_ptr = colreg;

	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
		regno, &(cp->lcd_cmap[regno * 2]),
		red, green, blue,
		cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
}
#endif	/* LCD_COLOR8 */

/*----------------------------------------------------------------------*/

#if LCD_BPP == LCD_MONOCHROME
static
void lcd_initcolregs (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = &(immr->im_cpm);
	ushort regno;

	for (regno = 0; regno < 16; regno++) {
		cp->lcd_cmap[regno * 2] = 0;
		cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
	}
}
#endif

/*----------------------------------------------------------------------*/

void lcd_enable (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile lcd823_t *lcdp = &immr->im_lcd;

	/* Enable the LCD panel */
#ifndef CONFIG_RBC823
	immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));		/* LAM = 1 */
#endif
	lcdp->lcd_lccr |= LCCR_PON;

#ifdef CONFIG_V37
	/* Turn on display backlight */
	immr->im_cpm.cp_pbpar |= 0x00008000;
	immr->im_cpm.cp_pbdir |= 0x00008000;
#elif defined(CONFIG_RBC823)
	/* Turn on display backlight */
	immr->im_cpm.cp_pbdat |= 0x00004000;
#endif

#if defined(CONFIG_LWMON)
    {	uchar c = pic_read (0x60);
#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
	/* Enable LCD later in sysmon test, only if temperature is OK */
#else
	c |= 0x07;	/* Power on CCFL, Enable CCFL, Chip Enable LCD */
#endif
	pic_write (0x60, c);
    }
#endif /* CONFIG_LWMON */

#if defined(CONFIG_R360MPI)
    {
	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
	unsigned long bgi, ctr;
	char *p;

	if ((p = getenv("lcdbgi")) != NULL) {
		bgi = simple_strtoul (p, 0, 10) & 0xFFF;
	} else {
		bgi = 0xFFF;
	}

	if ((p = getenv("lcdctr")) != NULL) {
		ctr = simple_strtoul (p, 0, 10) & 0xFFF;
	} else {
		ctr=0x7FF;
	}

	r360_i2c_lcd_write(0x10, 0x01);
	r360_i2c_lcd_write(0x20, 0x01);
	r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
	r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
    }
#endif /* CONFIG_R360MPI */
#ifdef CONFIG_RBC823
	udelay(200000); /* wait 200ms */
	/* Turn VEE_ON first */
	immr->im_cpm.cp_pbdat |= 0x00000001;
	udelay(200000); /* wait 200ms */
	/* Now turn on LCD_ON */
	immr->im_cpm.cp_pbdat |= 0x00001000;
#endif
#ifdef CONFIG_RRVISION
	debug ("PC4->Output(1): enable LVDS\n");
	debug ("PC5->Output(0): disable PAL clock\n");
	immr->im_ioport.iop_pddir |=  0x1000;
	immr->im_ioport.iop_pcpar &= ~(0x0C00);
	immr->im_ioport.iop_pcdir |=   0x0C00 ;
	immr->im_ioport.iop_pcdat |=   0x0800 ;
	immr->im_ioport.iop_pcdat &= ~(0x0400);
	debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
	       immr->im_ioport.iop_pdpar,
	       immr->im_ioport.iop_pddir,
	       immr->im_ioport.iop_pddat);
	debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
	       immr->im_ioport.iop_pcpar,
	       immr->im_ioport.iop_pcdir,
	       immr->im_ioport.iop_pcdat);
#endif
}

/*----------------------------------------------------------------------*/

#if defined (CONFIG_RBC823)
void lcd_disable (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile lcd823_t *lcdp = &immr->im_lcd;

#if defined(CONFIG_LWMON)
    {	uchar c = pic_read (0x60);
	c &= ~0x07;	/* Power off CCFL, Disable CCFL, Chip Disable LCD */
	pic_write (0x60, c);
    }
#elif defined(CONFIG_R360MPI)
    {
	extern void r360_i2c_lcd_write (uchar data0, uchar data1);

	r360_i2c_lcd_write(0x10, 0x00);
	r360_i2c_lcd_write(0x20, 0x00);
	r360_i2c_lcd_write(0x30, 0x00);
	r360_i2c_lcd_write(0x40, 0x00);
    }
#endif /* CONFIG_LWMON */
	/* Disable the LCD panel */
	lcdp->lcd_lccr &= ~LCCR_PON;
#ifdef CONFIG_RBC823
	/* Turn off display backlight, VEE and LCD_ON */
	immr->im_cpm.cp_pbdat &= ~0x00005001;
#else
	immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25));	/* LAM = 0 */
#endif /* CONFIG_RBC823 */
}
#endif	/* NOT_USED_SO_FAR || CONFIG_RBC823 */


/************************************************************************/

#endif /* CONFIG_LCD */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* (C) Copyright 2001-2002
	3	* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5b1d7137 WD	6	*/
	7
	8	/************************************************************************/
	9	/* ** HEADER FILES */
	10	/************************************************************************/
	11
8564acf9 WD	12	/* #define DEBUG */
8564acf9 WD	13
5b1d7137 WD	14	#include <config.h>
5b1d7137 WD	15	#include <common.h>
c3f4d17e	16	#include <command.h>
7aa78614	17	#include <watchdog.h>
5b1d7137 WD	18	#include <version.h>
	19	#include <stdarg.h>
	20	#include <lcdvideo.h>
	21	#include <linux/types.h>
52cb4d4f	22	#include <stdio_dev.h>
4532cb69 WD	23	#if defined(CONFIG_POST)
	24	#include <post.h>
	25	#endif
682011ff	26	#include <lcd.h>
5b1d7137 WD	27
	28	#ifdef CONFIG_LCD
	29
	30	/************************************************************************/
	31	/* ** CONFIG STUFF -- should be moved to board config file */
	32	/************************************************************************/
88804d19 WD	33	#ifndef CONFIG_LCD_INFO
	34	#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
	35	#endif
608c9146	36
d791b1dc	37	#if defined(CONFIG_V37) \|\| defined(CONFIG_EDT32F10)
608c9146	38	#undef CONFIG_LCD_LOGO
88804d19	39	#undef CONFIG_LCD_INFO
608c9146 WD	40	#endif
608c9146 WD	41
5b1d7137 WD	42	/----------------------------------------------------------------------/
	43	#ifdef CONFIG_KYOCERA_KCS057QV1AJ
	44	/*
	45	* Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
	46	*/
	47	#define LCD_BPP LCD_COLOR4
	48
8655b6f8	49	vidinfo_t panel_info = {
6d0f6bcf	50	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
5b1d7137 WD	51	LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
	52	/* wbl, vpw, lcdac, wbf */
	53	};
	54	#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
	55	/----------------------------------------------------------------------/
	56
682011ff WD	57	/----------------------------------------------------------------------/
	58	#ifdef CONFIG_HITACHI_SP19X001_Z1A
	59	/*
	60	* Hitachi SP19X001-. Active, color, single scan.
	61	*/
8655b6f8	62	vidinfo_t panel_info = {
6d0f6bcf	63	640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
682011ff WD	64	LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
	65	/* wbl, vpw, lcdac, wbf */
	66	};
	67	#endif /* CONFIG_HITACHI_SP19X001_Z1A */
	68	/----------------------------------------------------------------------/
	69
5b1d7137	70	/----------------------------------------------------------------------/
fd3103bb	71	#ifdef CONFIG_NEC_NL6448AC33
5b1d7137	72	/*
fd3103bb	73	* NEC NL6448AC33-18. Active, color, single scan.
5b1d7137	74	*/
8655b6f8	75	vidinfo_t panel_info = {
6d0f6bcf	76	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	77	3, 0, 0, 1, 1, 144, 2, 0, 33
	78	/* wbl, vpw, lcdac, wbf */
	79	};
fd3103bb	80	#endif /* CONFIG_NEC_NL6448AC33 */
5b1d7137 WD	81	/----------------------------------------------------------------------/
5b1d7137 WD	82
fd3103bb	83	#ifdef CONFIG_NEC_NL6448BC20
5b1d7137	84	/*
fd3103bb	85	* NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
5b1d7137	86	*/
8655b6f8	87	vidinfo_t panel_info = {
6d0f6bcf	88	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	89	3, 0, 0, 1, 1, 144, 2, 0, 33
	90	/* wbl, vpw, lcdac, wbf */
	91	};
fd3103bb WD	92	#endif /* CONFIG_NEC_NL6448BC20 */
	93	/----------------------------------------------------------------------/
	94
	95	#ifdef CONFIG_NEC_NL6448BC33_54
	96	/*
	97	* NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
	98	*/
8655b6f8	99	vidinfo_t panel_info = {
6d0f6bcf	100	640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
fd3103bb WD	101	3, 0, 0, 1, 1, 144, 2, 0, 33
	102	/* wbl, vpw, lcdac, wbf */
	103	};
	104	#endif /* CONFIG_NEC_NL6448BC33_54 */
5b1d7137 WD	105	/----------------------------------------------------------------------/
	106
	107	#ifdef CONFIG_SHARP_LQ104V7DS01
	108	/*
	109	* SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
	110	*/
8655b6f8	111	vidinfo_t panel_info = {
6d0f6bcf	112	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
5b1d7137 WD	113	3, 0, 0, 1, 1, 25, 1, 0, 33
	114	/* wbl, vpw, lcdac, wbf */
	115	};
	116	#endif /* CONFIG_SHARP_LQ104V7DS01 */
	117	/----------------------------------------------------------------------/
	118
	119	#ifdef CONFIG_SHARP_16x9
	120	/*
	121	* Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
	122	* not sure what it is.......
	123	*/
8655b6f8	124	vidinfo_t panel_info = {
6d0f6bcf	125	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
5b1d7137 WD	126	3, 0, 0, 1, 1, 15, 4, 0, 3
	127	};
	128	#endif /* CONFIG_SHARP_16x9 */
	129	/----------------------------------------------------------------------/
	130
	131	#ifdef CONFIG_SHARP_LQ057Q3DC02
	132	/*
	133	* Sharp LQ057Q3DC02 display. Active, color, single scan.
	134	*/
8655b6f8	135	#undef LCD_DF
4a6fd34b WD	136	#define LCD_DF 12
4a6fd34b WD	137
8655b6f8	138	vidinfo_t panel_info = {
6d0f6bcf	139	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	140	3, 0, 0, 1, 1, 15, 4, 0, 3
	141	/* wbl, vpw, lcdac, wbf */
	142	};
88804d19	143	#define CONFIG_LCD_INFO_BELOW_LOGO
5b1d7137 WD	144	#endif /* CONFIG_SHARP_LQ057Q3DC02 */
	145	/----------------------------------------------------------------------/
	146
	147	#ifdef CONFIG_SHARP_LQ64D341
	148	/*
	149	* Sharp LQ64D341 display, 640x480. Active, color, single scan.
	150	*/
8655b6f8	151	vidinfo_t panel_info = {
6d0f6bcf	152	640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	153	3, 0, 0, 1, 1, 128, 16, 0, 32
	154	/* wbl, vpw, lcdac, wbf */
	155	};
	156	#endif /* CONFIG_SHARP_LQ64D341 */
608c9146	157
29127b6a	158	#ifdef CONFIG_SHARP_LQ065T9DR51U
	159	/*
	160	* Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
	161	*/
8655b6f8	162	vidinfo_t panel_info = {
6d0f6bcf	163	400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
29127b6a	164	3, 0, 0, 1, 1, 248, 4, 0, 35
	165	/* wbl, vpw, lcdac, wbf */
	166	};
88804d19	167	#define CONFIG_LCD_INFO_BELOW_LOGO
29127b6a	168	#endif /* CONFIG_SHARP_LQ065T9DR51U */
29127b6a	169
608c9146 WD	170	#ifdef CONFIG_SHARP_LQ084V1DG21
	171	/*
	172	* Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
	173	*/
8655b6f8	174	vidinfo_t panel_info = {
6d0f6bcf	175	640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
608c9146 WD	176	3, 0, 0, 1, 1, 160, 3, 0, 48
	177	/* wbl, vpw, lcdac, wbf */
	178	};
	179	#endif /* CONFIG_SHARP_LQ084V1DG21 */
	180
5b1d7137 WD	181	/----------------------------------------------------------------------/
	182
	183	#ifdef CONFIG_HLD1045
	184	/*
	185	* HLD1045 display, 640x480. Active, color, single scan.
	186	*/
8655b6f8	187	vidinfo_t panel_info = {
6d0f6bcf	188	640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	189	3, 0, 0, 1, 1, 160, 3, 0, 48
	190	/* wbl, vpw, lcdac, wbf */
	191	};
	192	#endif /* CONFIG_HLD1045 */
	193	/----------------------------------------------------------------------/
	194
	195	#ifdef CONFIG_PRIMEVIEW_V16C6448AC
	196	/*
	197	* Prime View V16C6448AC
	198	*/
8655b6f8	199	vidinfo_t panel_info = {
6d0f6bcf	200	640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	201	3, 0, 0, 1, 1, 144, 2, 0, 35
	202	/* wbl, vpw, lcdac, wbf */
	203	};
	204	#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
	205
	206	/----------------------------------------------------------------------/
	207
	208	#ifdef CONFIG_OPTREX_BW
	209	/*
	210	* Optrex CBL50840-2 NF-FW 99 22 M5
	211	* or
	212	* Hitachi LMG6912RPFC-00T
	213	* or
	214	* Hitachi SP14Q002
	215	*
	216	* 320x240. Black & white.
	217	*/
	218	#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
	219	/* 1 - 4 grey levels, 2 bpp */
	220	/* 2 - 16 grey levels, 4 bpp */
8655b6f8	221	vidinfo_t panel_info = {
6d0f6bcf	222	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
5b1d7137 WD	223	OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
	224	};
	225	#endif /* CONFIG_OPTREX_BW */
	226
	227	/-----------------------------------------------------------------/
	228	#ifdef CONFIG_EDT32F10
	229	/*
	230	* Emerging Display Technologies 320x240. Passive, monochrome, single scan.
	231	*/
	232	#define LCD_BPP LCD_MONOCHROME
4a6fd34b	233	#define LCD_DF 10
5b1d7137	234
8655b6f8	235	vidinfo_t panel_info = {
6d0f6bcf	236	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
4a6fd34b	237	LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
5b1d7137 WD	238	};
5b1d7137 WD	239	#endif
5b1d7137 WD	240
5b1d7137 WD	241	/************************************************************************/
8655b6f8	242	/* ----------------- chipset specific functions ----------------------- */
5b1d7137 WD	243	/************************************************************************/
	244
	245	/*
8655b6f8	246	* Calculate fb size for VIDEOLFB_ATAG.
5b1d7137	247	*/
8655b6f8	248	ulong calc_fbsize (void)
5b1d7137 WD	249	{
	250	ulong size;
	251	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
	252
5b1d7137 WD	253	size = line_length * panel_info.vl_row;
5b1d7137 WD	254
8655b6f8	255	return size;
5b1d7137 WD	256	}
5b1d7137 WD	257
8655b6f8	258	void lcd_ctrl_init (void *lcdbase)
5b1d7137	259	{
6d0f6bcf	260	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	261	volatile lcd823_t *lcdp = &immr->im_lcd;
	262
	263	uint lccrtmp;
682011ff	264	uint lchcr_hpc_tmp;
5b1d7137 WD	265
	266	/* Initialize the LCD control register according to the LCD
	267	* parameters defined. We do everything here but enable
	268	* the controller.
	269	*/
	270
e63c8ee3 WD	271	#ifdef CONFIG_RPXLITE
e63c8ee3 WD	272	/* This is special for RPXlite_DW Software Development Platform [Sam] */
6d0f6bcf	273	panel_info.vl_dp = CONFIG_SYS_LOW;
e63c8ee3 WD	274	#endif
e63c8ee3 WD	275
5b1d7137 WD	276	lccrtmp = LCDBIT (LCCR_BNUM_BIT,
	277	(((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
	278
	279	lccrtmp \|= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) \|
	280	LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) \|
	281	LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) \|
	282	LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) \|
	283	LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) \|
	284	LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) \|
	285	LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) \|
	286	LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) \|
	287	LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) \|
	288	LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
	289
	290	#if 0
	291	lccrtmp \|= ((SIU_LEVEL5 / 2) << 12);
	292	lccrtmp \|= LCCR_EIEN;
	293	#endif
	294
	295	lcdp->lcd_lccr = lccrtmp;
	296	lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
	297
	298	/* Initialize LCD controller bus priorities.
	299	*/
682011ff WD	300	#ifdef CONFIG_RBC823
	301	immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) \| 1; /* RAID = 01, LAID = 00 */
	302	#else
5b1d7137 WD	303	immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
	304
	305	/* set SHFT/CLOCK division factor 4
	306	* This needs to be set based upon display type and processor
	307	* speed. The TFT displays run about 20 to 30 MHz.
	308	* I was running 64 MHz processor speed.
	309	* The value for this divider must be chosen so the result is
	310	* an integer of the processor speed (i.e., divide by 3 with
	311	* 64 MHz would be bad).
	312	*/
	313	immr->im_clkrst.car_sccr &= ~0x1F;
	314	immr->im_clkrst.car_sccr \|= LCD_DF; /* was 8 */
	315
682011ff WD	316	#endif /* CONFIG_RBC823 */
	317
	318	#if defined(CONFIG_RBC823)
	319	/* Enable LCD on port D.
	320	*/
	321	immr->im_ioport.iop_pddat &= 0x0300;
	322	immr->im_ioport.iop_pdpar \|= 0x1CFF;
	323	immr->im_ioport.iop_pddir \|= 0x1CFF;
	324
	325	/* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
	326	*/
	327	immr->im_cpm.cp_pbdat &= ~0x00005001;
	328	immr->im_cpm.cp_pbpar &= ~0x00005001;
	329	immr->im_cpm.cp_pbdir \|= 0x00005001;
	330	#elif !defined(CONFIG_EDT32F10)
5b1d7137 WD	331	/* Enable LCD on port D.
	332	*/
	333	immr->im_ioport.iop_pdpar \|= 0x1FFF;
	334	immr->im_ioport.iop_pddir \|= 0x1FFF;
	335
	336	/* Enable LCD_A/B/C on port B.
	337	*/
	338	immr->im_cpm.cp_pbpar \|= 0x00005001;
	339	immr->im_cpm.cp_pbdir \|= 0x00005001;
	340	#else
	341	/* Enable LCD on port D.
	342	*/
	343	immr->im_ioport.iop_pdpar \|= 0x1DFF;
	344	immr->im_ioport.iop_pdpar &= ~0x0200;
	345	immr->im_ioport.iop_pddir \|= 0x1FFF;
	346	immr->im_ioport.iop_pddat \|= 0x0200;
	347	#endif
	348
	349	/* Load the physical address of the linear frame buffer
	350	* into the LCD controller.
	351	* BIG NOTE: This has to be modified to load A and B depending
	352	* upon the split mode of the LCD.
	353	*/
00a0ca59 JH	354	lcdp->lcd_lcfaa = (ulong)lcdbase;
00a0ca59 JH	355	lcdp->lcd_lcfba = (ulong)lcdbase;
5b1d7137 WD	356
	357	/* MORE HACKS...This must be updated according to 823 manual
	358	* for different panels.
682011ff WD	359	* Udi Finkelstein - done - see below:
	360	* Note: You better not try unsupported combinations such as
	361	* 4-bit wide passive dual scan LCD at 4/8 Bit color.
5b1d7137	362	*/
682011ff	363	lchcr_hpc_tmp =
8bde7f77	364	(panel_info.vl_col *
682011ff WD	365	(panel_info.vl_tft ? 8 :
	366	(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
	367	/* use << to mult by: single scan = 1, dual scan = 2 */
	368	panel_info.vl_splt) *
	369	(panel_info.vl_bpix \| 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
	370
5b1d7137 WD	371	lcdp->lcd_lchcr = LCHCR_BO \|
5b1d7137 WD	372	LCDBIT (LCHCR_AT_BIT, 4) \|
682011ff	373	LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) \|
5b1d7137	374	panel_info.vl_wbl;
5b1d7137 WD	375
	376	lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) \|
	377	LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) \|
	378	LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) \|
	379	panel_info.vl_wbf;
	380
	381	}
	382
	383	/----------------------------------------------------------------------/
	384
5b1d7137	385	#if LCD_BPP == LCD_COLOR8
8655b6f8	386	void
5b1d7137 WD	387	lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
5b1d7137 WD	388	{
6d0f6bcf	389	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	390	volatile cpm8xx_t *cp = &(immr->im_cpm);
	391	unsigned short colreg, *cmap_ptr;
	392
	393	cmap_ptr = (unsigned short )&cp->lcd_cmap[regno 2];
	394
	395	colreg = ((red & 0x0F) << 8) \|
	396	((green & 0x0F) << 4) \|
	397	(blue & 0x0F) ;
6d0f6bcf	398	#ifdef CONFIG_SYS_INVERT_COLORS
5b1d7137 WD	399	colreg ^= 0x0FFF;
	400	#endif
	401	*cmap_ptr = colreg;
	402
	403	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
	404	regno, &(cp->lcd_cmap[regno * 2]),
	405	red, green, blue,
8bde7f77	406	cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
5b1d7137 WD	407	}
	408	#endif /* LCD_COLOR8 */
	409
	410	/----------------------------------------------------------------------/
	411
	412	#if LCD_BPP == LCD_MONOCHROME
	413	static
	414	void lcd_initcolregs (void)
	415	{
6d0f6bcf	416	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	417	volatile cpm8xx_t *cp = &(immr->im_cpm);
	418	ushort regno;
	419
	420	for (regno = 0; regno < 16; regno++) {
	421	cp->lcd_cmap[regno * 2] = 0;
	422	cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
	423	}
	424	}
	425	#endif
	426
	427	/----------------------------------------------------------------------/
	428
8655b6f8	429	void lcd_enable (void)
5b1d7137	430	{
6d0f6bcf	431	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	432	volatile lcd823_t *lcdp = &immr->im_lcd;
	433
	434	/* Enable the LCD panel */
682011ff	435	#ifndef CONFIG_RBC823
5b1d7137	436	immr->im_siu_conf.sc_sdcr \|= (1 << (31 - 25)); /* LAM = 1 */
682011ff	437	#endif
5b1d7137	438	lcdp->lcd_lccr \|= LCCR_PON;
608c9146 WD	439
	440	#ifdef CONFIG_V37
	441	/* Turn on display backlight */
	442	immr->im_cpm.cp_pbpar \|= 0x00008000;
	443	immr->im_cpm.cp_pbdir \|= 0x00008000;
682011ff WD	444	#elif defined(CONFIG_RBC823)
	445	/* Turn on display backlight */
	446	immr->im_cpm.cp_pbdat \|= 0x00004000;
608c9146 WD	447	#endif
608c9146 WD	448
5b1d7137 WD	449	#if defined(CONFIG_LWMON)
5b1d7137 WD	450	{ uchar c = pic_read (0x60);
6d0f6bcf	451	#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
7d7ce412	452	/* Enable LCD later in sysmon test, only if temperature is OK */
4532cb69	453	#else
8bde7f77	454	c \|= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
4532cb69	455	#endif
5b1d7137 WD	456	pic_write (0x60, c);
5b1d7137 WD	457	}
4a6fd34b WD	458	#endif /* CONFIG_LWMON */
	459
	460	#if defined(CONFIG_R360MPI)
5b1d7137	461	{
4a6fd34b	462	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
cb4dbb7b WD	463	unsigned long bgi, ctr;
	464	char *p;
	465
	466	if ((p = getenv("lcdbgi")) != NULL) {
	467	bgi = simple_strtoul (p, 0, 10) & 0xFFF;
	468	} else {
	469	bgi = 0xFFF;
	470	}
	471
	472	if ((p = getenv("lcdctr")) != NULL) {
	473	ctr = simple_strtoul (p, 0, 10) & 0xFFF;
	474	} else {
	475	ctr=0x7FF;
	476	}
5b1d7137	477
4a6fd34b WD	478	r360_i2c_lcd_write(0x10, 0x01);
4a6fd34b WD	479	r360_i2c_lcd_write(0x20, 0x01);
cb4dbb7b WD	480	r360_i2c_lcd_write(0x30 \| ((bgi>>8) & 0xF), bgi & 0xFF);
cb4dbb7b WD	481	r360_i2c_lcd_write(0x40 \| ((ctr>>8) & 0xF), ctr & 0xFF);
5b1d7137	482	}
4a6fd34b	483	#endif /* CONFIG_R360MPI */
682011ff WD	484	#ifdef CONFIG_RBC823
	485	udelay(200000); /* wait 200ms */
	486	/* Turn VEE_ON first */
	487	immr->im_cpm.cp_pbdat \|= 0x00000001;
	488	udelay(200000); /* wait 200ms */
	489	/* Now turn on LCD_ON */
	490	immr->im_cpm.cp_pbdat \|= 0x00001000;
	491	#endif
8564acf9 WD	492	#ifdef CONFIG_RRVISION
	493	debug ("PC4->Output(1): enable LVDS\n");
	494	debug ("PC5->Output(0): disable PAL clock\n");
	495	immr->im_ioport.iop_pddir \|= 0x1000;
	496	immr->im_ioport.iop_pcpar &= ~(0x0C00);
	497	immr->im_ioport.iop_pcdir \|= 0x0C00 ;
	498	immr->im_ioport.iop_pcdat \|= 0x0800 ;
	499	immr->im_ioport.iop_pcdat &= ~(0x0400);
	500	debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
	501	immr->im_ioport.iop_pdpar,
	502	immr->im_ioport.iop_pddir,
	503	immr->im_ioport.iop_pddat);
	504	debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
	505	immr->im_ioport.iop_pcpar,
	506	immr->im_ioport.iop_pcdir,
	507	immr->im_ioport.iop_pcdat);
	508	#endif
5b1d7137 WD	509	}
	510
	511	/----------------------------------------------------------------------/
	512
682011ff WD	513	#if defined (CONFIG_RBC823)
682011ff WD	514	void lcd_disable (void)
5b1d7137	515	{
6d0f6bcf	516	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	517	volatile lcd823_t *lcdp = &immr->im_lcd;
	518
	519	#if defined(CONFIG_LWMON)
	520	{ uchar c = pic_read (0x60);
8bde7f77	521	c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
5b1d7137 WD	522	pic_write (0x60, c);
	523	}
	524	#elif defined(CONFIG_R360MPI)
	525	{
4a6fd34b	526	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
5b1d7137	527
4a6fd34b WD	528	r360_i2c_lcd_write(0x10, 0x00);
	529	r360_i2c_lcd_write(0x20, 0x00);
	530	r360_i2c_lcd_write(0x30, 0x00);
	531	r360_i2c_lcd_write(0x40, 0x00);
5b1d7137 WD	532	}
	533	#endif /* CONFIG_LWMON */
	534	/* Disable the LCD panel */
	535	lcdp->lcd_lccr &= ~LCCR_PON;
682011ff WD	536	#ifdef CONFIG_RBC823
	537	/* Turn off display backlight, VEE and LCD_ON */
	538	immr->im_cpm.cp_pbdat &= ~0x00005001;
	539	#else
5b1d7137	540	immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
682011ff	541	#endif /* CONFIG_RBC823 */
5b1d7137	542	}
682011ff	543	#endif /* NOT_USED_SO_FAR \|\| CONFIG_RBC823 */
5b1d7137 WD	544
5b1d7137 WD	545
5b1d7137 WD	546	/************************************************************************/
	547
	548	#endif /* CONFIG_LCD */