[thirdparty/u-boot.git] / drivers / video / s6e8ax0.c

/*
 * Copyright (C) 2012 Samsung Electronics
 *
 * Author: Donghwa Lee <dh09.lee@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <common.h>
#include <asm/arch/mipi_dsim.h>

#include "exynos_mipi_dsi_lowlevel.h"
#include "exynos_mipi_dsi_common.h"

static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	int reverse = dsim_dev->dsim_lcd_dev->reverse_panel;
	static const unsigned char data_to_send[] = {
		0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c,
		0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20,
		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
		0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3,
		0xff, 0xff, 0xc8
	};

	static const unsigned char data_to_send_reverse[] = {
		0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c,
		0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20,
		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
		0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1,
		0xf6, 0xf6, 0xc1
	};

	if (reverse) {
		ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send_reverse,
			ARRAY_SIZE(data_to_send_reverse));
	} else {
		ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
	}
}

static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xf2, 0x80, 0x03, 0x0d
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	/* 7500K 2.2 Set : 30cd */
	static const unsigned char data_to_send[] = {
		0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad,
		0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1,
		0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74,
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3);
}

static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xf6, 0x00, 0x02, 0x00
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0,
		0x00
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40);
}

static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xb1, 0x04, 0x00
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
			(unsigned int)data_to_send,
			ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;

	ops->cmd_write(dsim_dev,
		MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
}

static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;

	ops->cmd_write(dsim_dev,
		MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
}

static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xf0, 0x5a, 0x5a
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
{
	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	static const unsigned char data_to_send[] = {
		0xf1, 0x5a, 0x5a
	};

	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
}

static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
{
	/*
	 * in case of setting gamma and panel condition at first,
	 * it shuold be setting like below.
	 * set_gamma() -> set_panel_condition()
	 */

	s6e8ax0_apply_level1_key(dsim_dev);
	s6e8ax0_apply_mtp_key(dsim_dev);

	s6e8ax0_sleep_out(dsim_dev);
	mdelay(5);
	s6e8ax0_panel_cond(dsim_dev);
	s6e8ax0_display_cond(dsim_dev);
	s6e8ax0_gamma_cond(dsim_dev);
	s6e8ax0_gamma_update(dsim_dev);

	s6e8ax0_etc_source_control(dsim_dev);
	s6e8ax0_elvss_set(dsim_dev);
	s6e8ax0_etc_pentile_control(dsim_dev);
	s6e8ax0_etc_mipi_control1(dsim_dev);
	s6e8ax0_etc_mipi_control2(dsim_dev);
	s6e8ax0_etc_power_control(dsim_dev);
	s6e8ax0_etc_mipi_control3(dsim_dev);
	s6e8ax0_etc_mipi_control4(dsim_dev);
}

static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev)
{
	s6e8ax0_panel_init(dsim_dev);

	return 0;
}

static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev)
{
	s6e8ax0_display_on(dsim_dev);
}

static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = {
	.name = "s6e8ax0",
	.id = -1,

	.mipi_panel_init = s6e8ax0_panel_set,
	.mipi_display_on = s6e8ax0_display_enable,
};

void s6e8ax0_init(void)
{
	exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver);
}
Commit	Line	Data
bba09e9f DL	1	/*
	2	* Copyright (C) 2012 Samsung Electronics
	3	*
	4	* Author: Donghwa Lee <dh09.lee@samsung.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
bba09e9f DL	7	*/
	8
	9	#include <common.h>
	10	#include <asm/arch/mipi_dsim.h>
	11
	12	#include "exynos_mipi_dsi_lowlevel.h"
	13	#include "exynos_mipi_dsi_common.h"
	14
	15	static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
	16	{
	17	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
3d024086	18	int reverse = dsim_dev->dsim_lcd_dev->reverse_panel;
b1d8654b	19	static const unsigned char data_to_send[] = {
bba09e9f DL	20	0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c,
	21	0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20,
	22	0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
	23	0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3,
	24	0xff, 0xff, 0xc8
	25	};
	26
b1d8654b	27	static const unsigned char data_to_send_reverse[] = {
3d024086 DL	28	0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c,
	29	0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20,
	30	0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
	31	0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1,
	32	0xf6, 0xf6, 0xc1
	33	};
	34
	35	if (reverse) {
	36	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	37	(unsigned int)data_to_send_reverse,
	38	ARRAY_SIZE(data_to_send_reverse));
	39	} else {
	40	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
bba09e9f	41	(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
3d024086	42	}
bba09e9f DL	43	}
	44
	45	static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
	46	{
	47	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	48	static const unsigned char data_to_send[] = {
bba09e9f DL	49	0xf2, 0x80, 0x03, 0x0d
	50	};
	51
	52	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	53	(unsigned int)data_to_send,
	54	ARRAY_SIZE(data_to_send));
	55	}
	56
	57	static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
	58	{
	59	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
8ecb4c64	60	/* 7500K 2.2 Set : 30cd */
b1d8654b	61	static const unsigned char data_to_send[] = {
8ecb4c64 DL	62	0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad,
	63	0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1,
	64	0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74,
bba09e9f DL	65	};
	66
	67	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	68	(unsigned int)data_to_send,
	69	ARRAY_SIZE(data_to_send));
	70	}
	71
	72	static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
	73	{
	74	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	75
	76	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3);
	77	}
	78
	79	static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
	80	{
	81	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	82	static const unsigned char data_to_send[] = {
bba09e9f DL	83	0xf6, 0x00, 0x02, 0x00
	84	};
	85
	86	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	87	(unsigned int)data_to_send,
	88	ARRAY_SIZE(data_to_send));
	89	}
	90
	91	static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
	92	{
	93	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	94	static const unsigned char data_to_send[] = {
bba09e9f DL	95	0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0,
	96	0x00
	97	};
	98
	99	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	100	(unsigned int)data_to_send,
	101	ARRAY_SIZE(data_to_send));
	102	}
	103
	104	static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
	105	{
	106	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	107	static const unsigned char data_to_send[] = {
bba09e9f DL	108	0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d
	109	};
	110
	111	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	112	(unsigned int)data_to_send,
	113	ARRAY_SIZE(data_to_send));
	114	}
	115
	116	static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
	117	{
	118	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	119	static const unsigned char data_to_send[] = {
bba09e9f DL	120	0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03
	121	};
	122
	123	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	124	(unsigned int)data_to_send,
	125	ARRAY_SIZE(data_to_send));
	126	}
	127
	128	static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
	129	{
	130	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	131	static const unsigned char data_to_send[] = {
bba09e9f DL	132	0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02
	133	};
	134
	135	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	136	(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
	137	}
	138
	139	static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
	140	{
	141	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	142
	143	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40);
	144	}
	145
	146	static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
	147	{
	148	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	149	static const unsigned char data_to_send[] = {
bba09e9f DL	150	0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00
	151	};
	152
	153	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	154	(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
	155	}
	156
	157	static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
	158	{
	159	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	160	static const unsigned char data_to_send[] = {
bba09e9f DL	161	0xb1, 0x04, 0x00
	162	};
	163
	164	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	165	(unsigned int)data_to_send,
	166	ARRAY_SIZE(data_to_send));
	167	}
	168
	169	static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
	170	{
	171	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	172
	173	ops->cmd_write(dsim_dev,
	174	MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
	175	}
	176
	177	static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
	178	{
	179	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
	180
	181	ops->cmd_write(dsim_dev,
	182	MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
	183	}
	184
	185	static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
	186	{
	187	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	188	static const unsigned char data_to_send[] = {
bba09e9f DL	189	0xf0, 0x5a, 0x5a
	190	};
	191
	192	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	193	(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
	194	}
	195
	196	static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
	197	{
	198	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
b1d8654b	199	static const unsigned char data_to_send[] = {
bba09e9f DL	200	0xf1, 0x5a, 0x5a
	201	};
	202
	203	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
	204	(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
	205	}
	206
	207	static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
	208	{
	209	/*
	210	* in case of setting gamma and panel condition at first,
	211	* it shuold be setting like below.
	212	* set_gamma() -> set_panel_condition()
	213	*/
	214
	215	s6e8ax0_apply_level1_key(dsim_dev);
	216	s6e8ax0_apply_mtp_key(dsim_dev);
	217
	218	s6e8ax0_sleep_out(dsim_dev);
	219	mdelay(5);
	220	s6e8ax0_panel_cond(dsim_dev);
	221	s6e8ax0_display_cond(dsim_dev);
	222	s6e8ax0_gamma_cond(dsim_dev);
	223	s6e8ax0_gamma_update(dsim_dev);
	224
	225	s6e8ax0_etc_source_control(dsim_dev);
	226	s6e8ax0_elvss_set(dsim_dev);
	227	s6e8ax0_etc_pentile_control(dsim_dev);
	228	s6e8ax0_etc_mipi_control1(dsim_dev);
	229	s6e8ax0_etc_mipi_control2(dsim_dev);
	230	s6e8ax0_etc_power_control(dsim_dev);
	231	s6e8ax0_etc_mipi_control3(dsim_dev);
	232	s6e8ax0_etc_mipi_control4(dsim_dev);
	233	}
	234
	235	static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev)
	236	{
	237	s6e8ax0_panel_init(dsim_dev);
	238
	239	return 0;
	240	}
	241
	242	static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev)
	243	{
	244	s6e8ax0_display_on(dsim_dev);
	245	}
	246
	247	static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = {
	248	.name = "s6e8ax0",
	249	.id = -1,
	250
	251	.mipi_panel_init = s6e8ax0_panel_set,
	252	.mipi_display_on = s6e8ax0_display_enable,
	253	};
	254
	255	void s6e8ax0_init(void)
	256	{
	257	exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver);
	258	}