]> git.ipfire.org Git - thirdparty/u-boot.git/blame - drivers/video/stm32/stm32_ltdc.c
projects / thirdparty / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'efi-2025-07-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
[thirdparty/u-boot.git] / drivers / video / stm32 / stm32_ltdc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
72719d2f 2/*
c4c33e9d 3 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
72719d2f
PC		 6 */
7
8d2257e5
PD		 8#define LOG_CATEGORY UCLASS_VIDEO
9
72719d2f 10#include <clk.h>
aeaf3306 11#include <display.h>
72719d2f 12#include <dm.h>
f7ae49fc 13#include <log.h>
72719d2f 14#include <panel.h>
c0fb2fc0 15#include <reset.h>
72719d2f 16#include <video.h>
aeaf3306 17#include <video_bridge.h>
72719d2f 18#include <asm/io.h>
72719d2f 19#include <dm/device-internal.h>
336d4615 20#include <dm/device_compat.h>
cd93d625 21#include <linux/bitops.h>
1e94b46f 22#include <linux/printk.h>
72719d2f 23
72719d2f
PC		 24struct stm32_ltdc_priv {
25 void __iomem *regs;
72719d2f
PC		 26 enum video_log2_bpp l2bpp;
27 u32 bg_col_argb;
13dc7562
YF		 28 const u32 *layer_regs;
29 const u32 *pix_fmt_hw;
72719d2f
PC		 30 u32 crop_x, crop_y, crop_w, crop_h;
31 u32 alpha;
13dc7562
YF		 32 u32 hw_version;
33};
34
35/* Layer register offsets */
36static const u32 layer_regs_a0[] = {
37 0x80, /* L1 configuration 0 */
38 0x00, /* not available */
39 0x00, /* not available */
40 0x84, /* L1 control register */
41 0x88, /* L1 window horizontal position configuration */
42 0x8c, /* L1 window vertical position configuration */
43 0x90, /* L1 color keying configuration */
44 0x94, /* L1 pixel format configuration */
45 0x98, /* L1 constant alpha configuration */
46 0x9c, /* L1 default color configuration */
47 0xa0, /* L1 blending factors configuration */
48 0x00, /* not available */
49 0x00, /* not available */
50 0xac, /* L1 color frame buffer address */
51 0xb0, /* L1 color frame buffer length */
52 0xb4, /* L1 color frame buffer line number */
53 0x00, /* not available */
54 0x00, /* not available */
55 0x00, /* not available */
56 0x00, /* not available */
57 0xc4, /* L1 CLUT write */
58 0x00, /* not available */
59 0x00, /* not available */
60 0x00, /* not available */
61 0x00, /* not available */
62 0x00, /* not available */
63 0x00, /* not available */
64 0x00, /* not available */
65 0x00, /* not available */
66 0x00, /* not available */
67 0x00 /* not available */
68};
69
70static const u32 layer_regs_a1[] = {
71 0x80, /* L1 configuration 0 */
72 0x84, /* L1 configuration 1 */
73 0x00, /* L1 reload control */
74 0x88, /* L1 control register */
75 0x8c, /* L1 window horizontal position configuration */
76 0x90, /* L1 window vertical position configuration */
77 0x94, /* L1 color keying configuration */
78 0x98, /* L1 pixel format configuration */
79 0x9c, /* L1 constant alpha configuration */
80 0xa0, /* L1 default color configuration */
81 0xa4, /* L1 blending factors configuration */
82 0xa8, /* L1 burst length configuration */
83 0x00, /* not available */
84 0xac, /* L1 color frame buffer address */
85 0xb0, /* L1 color frame buffer length */
86 0xb4, /* L1 color frame buffer line number */
87 0xb8, /* L1 auxiliary frame buffer address 0 */
88 0xbc, /* L1 auxiliary frame buffer address 1 */
89 0xc0, /* L1 auxiliary frame buffer length */
90 0xc4, /* L1 auxiliary frame buffer line number */
91 0xc8, /* L1 CLUT write */
92 0x00, /* not available */
93 0x00, /* not available */
94 0x00, /* not available */
95 0x00, /* not available */
96 0x00, /* not available */
97 0x00, /* not available */
98 0x00, /* not available */
99 0x00, /* not available */
100 0x00, /* not available */
101 0x00 /* not available */
102};
103
104static const u32 layer_regs_a2[] = {
105 0x100, /* L1 configuration 0 */
106 0x104, /* L1 configuration 1 */
107 0x108, /* L1 reload control */
108 0x10c, /* L1 control register */
109 0x110, /* L1 window horizontal position configuration */
110 0x114, /* L1 window vertical position configuration */
111 0x118, /* L1 color keying configuration */
112 0x11c, /* L1 pixel format configuration */
113 0x120, /* L1 constant alpha configuration */
114 0x124, /* L1 default color configuration */
115 0x128, /* L1 blending factors configuration */
116 0x12c, /* L1 burst length configuration */
117 0x130, /* L1 planar configuration */
118 0x134, /* L1 color frame buffer address */
119 0x138, /* L1 color frame buffer length */
120 0x13c, /* L1 color frame buffer line number */
121 0x140, /* L1 auxiliary frame buffer address 0 */
122 0x144, /* L1 auxiliary frame buffer address 1 */
123 0x148, /* L1 auxiliary frame buffer length */
124 0x14c, /* L1 auxiliary frame buffer line number */
125 0x150, /* L1 CLUT write */
126 0x154, /* not available */
127 0x158, /* not available */
128 0x15c, /* not available */
129 0x160, /* not available */
130 0x164, /* not available */
131 0x168, /* not available */
132 0x16c, /* L1 Conversion YCbCr RGB 0 */
133 0x170, /* L1 Conversion YCbCr RGB 1 */
134 0x174, /* L1 Flexible Pixel Format 0 */
135 0x178 /* L1 Flexible Pixel Format 1 */
72719d2f
PC		 136};
137
138/* LTDC main registers */
139#define LTDC_IDR 0x00 /* IDentification */
140#define LTDC_LCR 0x04 /* Layer Count */
141#define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
142#define LTDC_BPCR 0x0C /* Back Porch Configuration */
143#define LTDC_AWCR 0x10 /* Active Width Configuration */
144#define LTDC_TWCR 0x14 /* Total Width Configuration */
145#define LTDC_GCR 0x18 /* Global Control */
146#define LTDC_GC1R 0x1C /* Global Configuration 1 */
147#define LTDC_GC2R 0x20 /* Global Configuration 2 */
148#define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
149#define LTDC_GACR 0x28 /* GAmma Correction */
150#define LTDC_BCCR 0x2C /* Background Color Configuration */
151#define LTDC_IER 0x34 /* Interrupt Enable */
152#define LTDC_ISR 0x38 /* Interrupt Status */
153#define LTDC_ICR 0x3C /* Interrupt Clear */
154#define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
155#define LTDC_CPSR 0x44 /* Current Position Status */
156#define LTDC_CDSR 0x48 /* Current Display Status */
157
13dc7562
YF		 158/* Layer register offsets */
159#define LTDC_L1C0R (priv->layer_regs[0]) /* L1 configuration 0 */
160#define LTDC_L1C1R (priv->layer_regs[1]) /* L1 configuration 1 */
161#define LTDC_L1RCR (priv->layer_regs[2]) /* L1 reload control */
162#define LTDC_L1CR (priv->layer_regs[3]) /* L1 control register */
163#define LTDC_L1WHPCR (priv->layer_regs[4]) /* L1 window horizontal position configuration */
164#define LTDC_L1WVPCR (priv->layer_regs[5]) /* L1 window vertical position configuration */
165#define LTDC_L1CKCR (priv->layer_regs[6]) /* L1 color keying configuration */
166#define LTDC_L1PFCR (priv->layer_regs[7]) /* L1 pixel format configuration */
167#define LTDC_L1CACR (priv->layer_regs[8]) /* L1 constant alpha configuration */
168#define LTDC_L1DCCR (priv->layer_regs[9]) /* L1 default color configuration */
169#define LTDC_L1BFCR (priv->layer_regs[10]) /* L1 blending factors configuration */
170#define LTDC_L1BLCR (priv->layer_regs[11]) /* L1 burst length configuration */
171#define LTDC_L1PCR (priv->layer_regs[12]) /* L1 planar configuration */
172#define LTDC_L1CFBAR (priv->layer_regs[13]) /* L1 color frame buffer address */
173#define LTDC_L1CFBLR (priv->layer_regs[14]) /* L1 color frame buffer length */
174#define LTDC_L1CFBLNR (priv->layer_regs[15]) /* L1 color frame buffer line number */
175#define LTDC_L1AFBA0R (priv->layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
176#define LTDC_L1AFBA1R (priv->layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
177#define LTDC_L1AFBLR (priv->layer_regs[18]) /* L1 auxiliary frame buffer length */
178#define LTDC_L1AFBLNR (priv->layer_regs[19]) /* L1 auxiliary frame buffer line number */
179#define LTDC_L1CLUTWR (priv->layer_regs[20]) /* L1 CLUT write */
180#define LTDC_L1CYR0R (priv->layer_regs[27]) /* L1 Conversion YCbCr RGB 0 */
181#define LTDC_L1CYR1R (priv->layer_regs[28]) /* L1 Conversion YCbCr RGB 1 */
182#define LTDC_L1FPF0R (priv->layer_regs[29]) /* L1 Flexible Pixel Format 0 */
183#define LTDC_L1FPF1R (priv->layer_regs[30]) /* L1 Flexible Pixel Format 1 */
72719d2f
PC		 184
185/* Bit definitions */
186#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
187#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
188
189#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
190#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
191
192#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
193#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
194
195#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
196#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
197
198#define GCR_LTDCEN BIT(0) /* LTDC ENable */
199#define GCR_DEN BIT(16) /* Dither ENable */
200#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
201#define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
202#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
203#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
204
205#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
206#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
207#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
208#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
209#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
210#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
211#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
212#define GC1R_BCP BIT(22) /* Background Colour Programmable */
213#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
214#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
215#define GC1R_TP BIT(25) /* Timing Programmable */
216#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
217#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
218#define GC1R_DWP BIT(28) /* Dither Width Programmable */
219#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
220#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
221
222#define GC2R_EDCA BIT(0) /* External Display Control Ability */
223#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
224#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
225#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
226#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
227#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
228
229#define SRCR_IMR BIT(0) /* IMmediate Reload */
230#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
231
232#define LXCR_LEN BIT(0) /* Layer ENable */
233#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
234#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
235
236#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
237#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
238
239#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
240#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
241
242#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
243
244#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
245
246#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
247#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
248
249#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
250#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
251
252#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
253
254#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
e6194ce6 255#define BF1_CA 0x400 /* Constant Alpha */
72719d2f 256#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
e6194ce6 257#define BF2_1CA 0x005 /* 1 - Constant Alpha */
72719d2f 258
13dc7562
YF		 259#define NB_PF 8 /* Max nb of HW pixel format */
260
261#define HWVER_10200 0x010200
262#define HWVER_10300 0x010300
263#define HWVER_20101 0x020101
264#define HWVER_40100 0x040100
265
72719d2f 266enum stm32_ltdc_pix_fmt {
13dc7562
YF		 267 PF_ARGB8888 = 0, /* ARGB [32 bits] */
268 PF_ABGR8888, /* ABGR [32 bits] */
269 PF_BGRA8888, /* BGRA [32 bits] */
270 PF_RGBA8888, /* RGBA [32 bits] */
271 PF_RGB888, /* RGB [24 bits] */
272 PF_BGR565, /* RGB [16 bits] */
273 PF_RGB565, /* RGB [16 bits] */
274 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
275 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
276 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
277 PF_AL88, /* Alpha:8 bits + indexed 8 bits [16 bits] */
278 PF_L8, /* Indexed 8 bits [8 bits] */
279 PF_NONE
280};
281
282static const enum stm32_ltdc_pix_fmt pix_fmt_a0[NB_PF] = {
283 PF_ARGB8888, /* 0x00 */
284 PF_RGB888, /* 0x01 */
285 PF_RGB565, /* 0x02 */
286 PF_ARGB1555, /* 0x03 */
287 PF_ARGB4444, /* 0x04 */
288 PF_L8, /* 0x05 */
289 PF_AL44, /* 0x06 */
290 PF_AL88 /* 0x07 */
291};
292
293static const enum stm32_ltdc_pix_fmt pix_fmt_a1[NB_PF] = {
294 PF_ARGB8888, /* 0x00 */
295 PF_RGB888, /* 0x01 */
296 PF_RGB565, /* 0x02 */
297 PF_RGBA8888, /* 0x03 */
298 PF_AL44, /* 0x04 */
299 PF_L8, /* 0x05 */
300 PF_ARGB1555, /* 0x06 */
301 PF_ARGB4444 /* 0x07 */
302};
303
304static const enum stm32_ltdc_pix_fmt pix_fmt_a2[NB_PF] = {
305 PF_ARGB8888, /* 0x00 */
306 PF_ABGR8888, /* 0x01 */
307 PF_RGBA8888, /* 0x02 */
308 PF_BGRA8888, /* 0x03 */
309 PF_RGB565, /* 0x04 */
310 PF_BGR565, /* 0x05 */
311 PF_RGB888, /* 0x06 */
312 PF_NONE /* 0x07 (flexible pixel format) */
72719d2f
PC		 313};
314
315/* TODO add more color format support */
316static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
317{
318 enum stm32_ltdc_pix_fmt pf;
319
320 switch (l2bpp) {
321 case VIDEO_BPP16:
322 pf = PF_RGB565;
323 break;
324
e6194ce6 325 case VIDEO_BPP32:
326 pf = PF_ARGB8888;
327 break;
328
329 case VIDEO_BPP8:
330 pf = PF_L8;
331 break;
332
72719d2f
PC		 333 case VIDEO_BPP1:
334 case VIDEO_BPP2:
335 case VIDEO_BPP4:
72719d2f 336 default:
8d2257e5
PD		 337 log_warning("warning %dbpp not supported yet, %dbpp instead\n",
338 VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
72719d2f
PC		 339 pf = PF_RGB565;
340 break;
341 }
342
8d2257e5 343 log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
72719d2f
PC		 344
345 return (u32)pf;
346}
347
e6194ce6 348static bool has_alpha(u32 fmt)
349{
350 switch (fmt) {
351 case PF_ARGB8888:
352 case PF_ARGB1555:
353 case PF_ARGB4444:
354 case PF_AL44:
355 case PF_AL88:
356 return true;
357 case PF_RGB888:
358 case PF_RGB565:
359 case PF_L8:
360 default:
361 return false;
362 }
363}
364
72719d2f
PC		 365static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
366{
367 /* Reload configuration immediately & enable LTDC */
368 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
369 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
370}
371
aeaf3306
YF		 372static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
373 struct display_timing *timings)
72719d2f
PC		 374{
375 void __iomem *regs = priv->regs;
72719d2f
PC		 376 u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
377 u32 total_w, total_h;
378 u32 val;
379
380 /* Convert video timings to ltdc timings */
aeaf3306
YF		 381 hsync = timings->hsync_len.typ - 1;
382 vsync = timings->vsync_len.typ - 1;
383 acc_hbp = hsync + timings->hback_porch.typ;
384 acc_vbp = vsync + timings->vback_porch.typ;
385 acc_act_w = acc_hbp + timings->hactive.typ;
386 acc_act_h = acc_vbp + timings->vactive.typ;
387 total_w = acc_act_w + timings->hfront_porch.typ;
388 total_h = acc_act_h + timings->vfront_porch.typ;
72719d2f
PC		 389
390 /* Synchronization sizes */
391 val = (hsync << 16) | vsync;
392 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
393
394 /* Accumulated back porch */
395 val = (acc_hbp << 16) | acc_vbp;
396 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
397
398 /* Accumulated active width */
399 val = (acc_act_w << 16) | acc_act_h;
400 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
401
402 /* Total width & height */
403 val = (total_w << 16) | total_h;
404 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
405
75fa711a 406 setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
407
72719d2f
PC		 408 /* Signal polarities */
409 val = 0;
8d2257e5 410 log_debug("timing->flags 0x%08x\n", timings->flags);
aeaf3306 411 if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
72719d2f 412 val |= GCR_HSPOL;
aeaf3306 413 if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
72719d2f 414 val |= GCR_VSPOL;
ef4ce6df 415 if (timings->flags & DISPLAY_FLAGS_DE_LOW)
72719d2f 416 val |= GCR_DEPOL;
aeaf3306 417 if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
72719d2f
PC		 418 val |= GCR_PCPOL;
419 clrsetbits_le32(regs + LTDC_GCR,
420 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
421
422 /* Overall background color */
423 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
424}
425
426static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
427{
428 void __iomem *regs = priv->regs;
429 u32 x0, x1, y0, y1;
430 u32 pitch_in_bytes;
431 u32 line_length;
432 u32 bus_width;
433 u32 val, tmp, bpp;
e6194ce6 434 u32 format;
72719d2f
PC		 435
436 x0 = priv->crop_x;
437 x1 = priv->crop_x + priv->crop_w - 1;
438 y0 = priv->crop_y;
439 y1 = priv->crop_y + priv->crop_h - 1;
440
441 /* Horizontal start and stop position */
442 tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
443 val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
444 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
445 val);
446
447 /* Vertical start & stop position */
448 tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
449 val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
450 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
451 val);
452
453 /* Layer background color */
454 writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
455
456 /* Color frame buffer pitch in bytes & line length */
457 bpp = VNBITS(priv->l2bpp);
458 pitch_in_bytes = priv->crop_w * (bpp >> 3);
459 bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
460 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
461 val = (pitch_in_bytes << 16) | line_length;
462 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
463
464 /* Pixel format */
e6194ce6 465 format = stm32_ltdc_get_pixel_format(priv->l2bpp);
13dc7562
YF		 466 for (val = 0; val < NB_PF; val++)
467 if (priv->pix_fmt_hw[val] == format)
468 break;
469
470 if (val >= NB_PF) {
471 log_err("invalid pixel format\n");
472 return;
473 }
474
475 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
72719d2f
PC		 476
477 /* Constant alpha value */
478 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
479
e6194ce6 480 /* Specifies the blending factors : with or without pixel alpha */
481 /* Manage hw-specific capabilities */
482 val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
483
72719d2f 484 /* Blending factors */
e6194ce6 485 clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
72719d2f
PC		 486
487 /* Frame buffer line number */
488 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
489
490 /* Frame buffer address */
491 writel(fb_addr, regs + LTDC_L1CFBAR);
492
493 /* Enable layer 1 */
494 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
495}
496
47256b04
DB		 497#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY)
498static int stm32_ltdc_alloc_fb(struct udevice *dev)
499{
500 u32 sdram_size = gd->ram_size;
501 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
502 phys_addr_t cpu;
503 dma_addr_t bus;
504 u64 dma_size;
505 int ret;
506
507 ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size);
508 if (ret) {
509 dev_err(dev, "failed to get dma address\n");
510 return ret;
511 }
512
513 uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align);
514 return 0;
515}
516#else
517static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
518{
519 /* Delegate framebuffer allocation to video-uclass */
520 return 0;
521}
522#endif
523
72719d2f
PC		 524static int stm32_ltdc_probe(struct udevice *dev)
525{
8a8d24bd 526 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
72719d2f
PC		 527 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
528 struct stm32_ltdc_priv *priv = dev_get_priv(dev);
aeaf3306
YF		 529 struct udevice *bridge = NULL;
530 struct udevice *panel = NULL;
531 struct display_timing timings;
2a0e8784 532 struct clk pclk;
c0fb2fc0 533 struct reset_ctl rst;
310ef930 534 ulong rate;
aeaf3306 535 int ret;
72719d2f 536
a12a73b6
JJ		 537 priv->regs = dev_read_addr_ptr(dev);
538 if (!priv->regs) {
aeaf3306 539 dev_err(dev, "ltdc dt register address error\n");
72719d2f
PC		 540 return -EINVAL;
541 }
542
2a0e8784 543 ret = clk_get_by_index(dev, 0, &pclk);
72719d2f 544 if (ret) {
aeaf3306 545 dev_err(dev, "peripheral clock get error %d\n", ret);
2a0e8784 546 return ret;
547 }
548
549 ret = clk_enable(&pclk);
550 if (ret) {
aeaf3306 551 dev_err(dev, "peripheral clock enable error %d\n", ret);
72719d2f
PC		 552 return ret;
553 }
554
13dc7562
YF		 555 priv->hw_version = readl(priv->regs + LTDC_IDR);
556 debug("%s: LTDC hardware 0x%x\n", __func__, priv->hw_version);
557
558 switch (priv->hw_version) {
559 case HWVER_10200:
560 case HWVER_10300:
561 priv->layer_regs = layer_regs_a0;
562 priv->pix_fmt_hw = pix_fmt_a0;
563 break;
564 case HWVER_20101:
565 priv->layer_regs = layer_regs_a1;
566 priv->pix_fmt_hw = pix_fmt_a1;
567 break;
568 case HWVER_40100:
569 priv->layer_regs = layer_regs_a2;
570 priv->pix_fmt_hw = pix_fmt_a2;
571 break;
572 default:
573 return -ENODEV;
574 }
575
aeaf3306 576 ret = uclass_first_device_err(UCLASS_PANEL, &panel);
c0fb2fc0 577 if (ret) {
aeaf3306
YF		 578 if (ret != -ENODEV)
579 dev_err(dev, "panel device error %d\n", ret);
580 return ret;
c0fb2fc0 581 }
582
aeaf3306 583 ret = panel_get_display_timing(panel, &timings);
2a0e8784 584 if (ret) {
28c6ba86 585 ret = ofnode_decode_display_timing(dev_ofnode(panel),
aeaf3306
YF		 586 0, &timings);
587 if (ret) {
588 dev_err(dev, "decode display timing error %d\n", ret);
589 return ret;
590 }
2a0e8784 591 }
592
310ef930
GF		 593 rate = clk_set_rate(&pclk, timings.pixelclock.typ);
594 if (IS_ERR_VALUE(rate))
595 dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
596 timings.pixelclock.typ, rate);
aeaf3306 597
8d2257e5 598 dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
310ef930 599 timings.pixelclock.typ, rate);
aeaf3306
YF		 600
601 ret = reset_get_by_index(dev, 0, &rst);
72719d2f 602 if (ret) {
aeaf3306 603 dev_err(dev, "missing ltdc hardware reset\n");
72719d2f
PC		 604 return ret;
605 }
606
aeaf3306
YF		 607 /* Reset */
608 reset_deassert(&rst);
72719d2f 609
aeaf3306
YF		 610 if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
611 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
612 if (ret)
8d2257e5
PD		 613 dev_dbg(dev,
614 "No video bridge, or no backlight on bridge\n");
aeaf3306
YF		 615
616 if (bridge) {
617 ret = video_bridge_attach(bridge);
618 if (ret) {
8d2257e5 619 dev_err(bridge, "fail to attach bridge\n");
aeaf3306
YF		 620 return ret;
621 }
622 }
72719d2f
PC		 623 }
624
72719d2f
PC		 625 /* TODO Below parameters are hard-coded for the moment... */
626 priv->l2bpp = VIDEO_BPP16;
627 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
628 priv->crop_x = 0;
629 priv->crop_y = 0;
aeaf3306
YF		 630 priv->crop_w = timings.hactive.typ;
631 priv->crop_h = timings.vactive.typ;
72719d2f
PC		 632 priv->alpha = 0xFF;
633
47256b04
DB		 634 ret = stm32_ltdc_alloc_fb(dev);
635 if (ret)
636 return ret;
637
8d2257e5
PD		 638 dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
639 timings.hactive.typ, timings.vactive.typ,
640 VNBITS(priv->l2bpp), uc_plat->base);
641 dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
642 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
643 priv->bg_col_argb, priv->alpha);
72719d2f
PC		 644
645 /* Configure & start LTDC */
aeaf3306 646 stm32_ltdc_set_mode(priv, &timings);
72719d2f
PC		 647 stm32_ltdc_set_layer1(priv, uc_plat->base);
648 stm32_ltdc_enable(priv);
649
aeaf3306
YF		 650 uc_priv->xsize = timings.hactive.typ;
651 uc_priv->ysize = timings.vactive.typ;
72719d2f
PC		 652 uc_priv->bpix = priv->l2bpp;
653
aeaf3306
YF		 654 if (!bridge) {
655 ret = panel_enable_backlight(panel);
656 if (ret) {
657 dev_err(dev, "panel %s enable backlight error %d\n",
658 panel->name, ret);
659 return ret;
660 }
661 } else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
662 ret = video_bridge_set_backlight(bridge, 80);
663 if (ret) {
664 dev_err(dev, "fail to set backlight\n");
665 return ret;
666 }
667 }
668
72719d2f
PC		 669 video_set_flush_dcache(dev, true);
670
671 return 0;
672}
673
674static int stm32_ltdc_bind(struct udevice *dev)
675{
8a8d24bd 676 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
72719d2f
PC		 677
678 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
679 CONFIG_VIDEO_STM32_MAX_YRES *
680 (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
6cdeb323
PD		 681 /* align framebuffer on kernel MMU_SECTION_SIZE = max 2MB for LPAE */
682 uc_plat->align = SZ_2M;
683 dev_dbg(dev, "frame buffer max size %d bytes align %x\n",
684 uc_plat->size, uc_plat->align);
72719d2f
PC		 685
686 return 0;
687}
688
689static const struct udevice_id stm32_ltdc_ids[] = {
690 { .compatible = "st,stm32-ltdc" },
691 { }
692};
693
694U_BOOT_DRIVER(stm32_ltdc) = {
c4c33e9d 695 .name = "stm32_display",
696 .id = UCLASS_VIDEO,
697 .of_match = stm32_ltdc_ids,
698 .probe = stm32_ltdc_probe,
699 .bind = stm32_ltdc_bind,
41575d8e 700 .priv_auto = sizeof(struct stm32_ltdc_priv),
72719d2f 701};
"Das U-Boot" Source Tree