[thirdparty/u-boot.git] / drivers / watchdog / ast_wdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017 Google, Inc
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <wdt.h>
#include <asm/io.h>
#include <asm/arch/wdt.h>

#define WDT_AST2500	2500
#define WDT_AST2400	2400

struct ast_wdt_priv {
	struct ast_wdt *regs;
};

static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
	struct ast_wdt_priv *priv = dev_get_priv(dev);
	ulong driver_data = dev_get_driver_data(dev);
	u32 reset_mode = ast_reset_mode_from_flags(flags);

	clrsetbits_le32(&priv->regs->ctrl,
			WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
			reset_mode << WDT_CTRL_RESET_MODE_SHIFT);

	if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
		writel(ast_reset_mask_from_flags(flags),
		       &priv->regs->reset_mask);

	writel((u32) timeout, &priv->regs->counter_reload_val);
	writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
	/*
	 * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
	 * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
	 * read-only
	 */
	setbits_le32(&priv->regs->ctrl,
		     WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);

	return 0;
}

static int ast_wdt_stop(struct udevice *dev)
{
	struct ast_wdt_priv *priv = dev_get_priv(dev);

	clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);

	return 0;
}

static int ast_wdt_reset(struct udevice *dev)
{
	struct ast_wdt_priv *priv = dev_get_priv(dev);

	writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);

	return 0;
}

static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
{
	struct ast_wdt_priv *priv = dev_get_priv(dev);
	int ret;

	ret = ast_wdt_start(dev, 1, flags);
	if (ret)
		return ret;

	while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
		;

	return ast_wdt_stop(dev);
}

static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
{
	struct ast_wdt_priv *priv = dev_get_priv(dev);

	priv->regs = devfdt_get_addr_ptr(dev);
	if (IS_ERR(priv->regs))
		return PTR_ERR(priv->regs);

	return 0;
}

static const struct wdt_ops ast_wdt_ops = {
	.start = ast_wdt_start,
	.reset = ast_wdt_reset,
	.stop = ast_wdt_stop,
	.expire_now = ast_wdt_expire_now,
};

static const struct udevice_id ast_wdt_ids[] = {
	{ .compatible = "aspeed,wdt", .data = WDT_AST2500 },
	{ .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
	{ .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
	{}
};

static int ast_wdt_probe(struct udevice *dev)
{
	debug("%s() wdt%u\n", __func__, dev->seq);
	ast_wdt_stop(dev);

	return 0;
}

U_BOOT_DRIVER(ast_wdt) = {
	.name = "ast_wdt",
	.id = UCLASS_WDT,
	.of_match = ast_wdt_ids,
	.probe = ast_wdt_probe,
	.priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
	.ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
	.ops = &ast_wdt_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1eb0a464	2	/*
1eb0a464	3	* Copyright 2017 Google, Inc
1eb0a464	4	*/
	5
	6	#include <common.h>
	7	#include <dm.h>
	8	#include <errno.h>
	9	#include <wdt.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/wdt.h>
	12
	13	#define WDT_AST2500 2500
	14	#define WDT_AST2400 2400
	15
1eb0a464	16	struct ast_wdt_priv {
	17	struct ast_wdt *regs;
	18	};
	19
	20	static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
	21	{
	22	struct ast_wdt_priv *priv = dev_get_priv(dev);
	23	ulong driver_data = dev_get_driver_data(dev);
	24	u32 reset_mode = ast_reset_mode_from_flags(flags);
	25
	26	clrsetbits_le32(&priv->regs->ctrl,
	27	WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
	28	reset_mode << WDT_CTRL_RESET_MODE_SHIFT);
	29
	30	if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
	31	writel(ast_reset_mask_from_flags(flags),
	32	&priv->regs->reset_mask);
	33
	34	writel((u32) timeout, &priv->regs->counter_reload_val);
	35	writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
	36	/*
	37	* Setting CLK1MHZ bit is just for compatibility with ast2400 part.
	38	* On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
	39	* read-only
	40	*/
	41	setbits_le32(&priv->regs->ctrl,
	42	WDT_CTRL_EN \| WDT_CTRL_RESET \| WDT_CTRL_CLK1MHZ);
	43
	44	return 0;
	45	}
	46
	47	static int ast_wdt_stop(struct udevice *dev)
	48	{
	49	struct ast_wdt_priv *priv = dev_get_priv(dev);
	50
	51	clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
	52
	53	return 0;
	54	}
	55
	56	static int ast_wdt_reset(struct udevice *dev)
	57	{
	58	struct ast_wdt_priv *priv = dev_get_priv(dev);
	59
	60	writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
	61
	62	return 0;
	63	}
	64
	65	static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
	66	{
	67	struct ast_wdt_priv *priv = dev_get_priv(dev);
	68	int ret;
	69
	70	ret = ast_wdt_start(dev, 1, flags);
	71	if (ret)
	72	return ret;
	73
	74	while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
	75	;
	76
	77	return ast_wdt_stop(dev);
	78	}
	79
80	static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
81	{
82	struct ast_wdt_priv *priv = dev_get_priv(dev);
83
a821c4af	84	priv->regs = devfdt_get_addr_ptr(dev);
1eb0a464	85	if (IS_ERR(priv->regs))
	86	return PTR_ERR(priv->regs);
	87
	88	return 0;
	89	}
	90
	91	static const struct wdt_ops ast_wdt_ops = {
	92	.start = ast_wdt_start,
	93	.reset = ast_wdt_reset,
	94	.stop = ast_wdt_stop,
	95	.expire_now = ast_wdt_expire_now,
	96	};
	97
	98	static const struct udevice_id ast_wdt_ids[] = {
	99	{ .compatible = "aspeed,wdt", .data = WDT_AST2500 },
	100	{ .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
	101	{ .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
	102	{}
	103	};
	104
	105	static int ast_wdt_probe(struct udevice *dev)
	106	{
	107	debug("%s() wdt%u\n", __func__, dev->seq);
	108	ast_wdt_stop(dev);
	109
	110	return 0;
	111	}
	112
	113	U_BOOT_DRIVER(ast_wdt) = {
	114	.name = "ast_wdt",
	115	.id = UCLASS_WDT,
	116	.of_match = ast_wdt_ids,
	117	.probe = ast_wdt_probe,
	118	.priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
	119	.ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
	120	.ops = &ast_wdt_ops,
	121	.flags = DM_FLAG_PRE_RELOC,
	122	};