]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/watchdog/f71808e_wdt.c
projects / thirdparty / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156
[thirdparty/linux.git] / drivers / watchdog / f71808e_wdt.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
96cb4eb0
GS		 2/***************************************************************************
3 * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
4 * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> *
5 * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> *
6 * *
96cb4eb0
GS		 7 ***************************************************************************/
8
27c766aa
JP		 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
96cb4eb0
GS		 11#include <linux/err.h>
12#include <linux/fs.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/miscdevice.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/notifier.h>
20#include <linux/reboot.h>
21#include <linux/uaccess.h>
22#include <linux/watchdog.h>
23
24#define DRVNAME "f71808e_wdt"
25
26#define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
27#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
85c130a8 28#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
96cb4eb0
GS		 29
30#define SIO_REG_LDSEL 0x07 /* Logical device select */
31#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
32#define SIO_REG_DEVREV 0x22 /* Device revision */
33#define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
7977ff6e 34#define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
14b24a88 35#define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
f9a9f096
LB		 36#define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */
37#define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */
38#define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */
14b24a88 39#define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */
96cb4eb0
GS		 40#define SIO_REG_ENABLE 0x30 /* Logical device enable */
41#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
42
43#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
f9a9f096
LB		 44#define SIO_F71808_ID 0x0901 /* Chipset ID */
45#define SIO_F71858_ID 0x0507 /* Chipset ID */
96cb4eb0 46#define SIO_F71862_ID 0x0601 /* Chipset ID */
166fbcf8 47#define SIO_F71868_ID 0x1106 /* Chipset ID */
df278dac 48#define SIO_F71869_ID 0x0814 /* Chipset ID */
3017020d 49#define SIO_F71869A_ID 0x1007 /* Chipset ID */
96cb4eb0
GS		 50#define SIO_F71882_ID 0x0541 /* Chipset ID */
51#define SIO_F71889_ID 0x0723 /* Chipset ID */
ea0c03e8 52#define SIO_F81865_ID 0x0704 /* Chipset ID */
14b24a88 53#define SIO_F81866_ID 0x1010 /* Chipset ID */
96cb4eb0 54
96cb4eb0
GS		 55#define F71808FG_REG_WDO_CONF 0xf0
56#define F71808FG_REG_WDT_CONF 0xf5
57#define F71808FG_REG_WD_TIME 0xf6
58
59#define F71808FG_FLAG_WDOUT_EN 7
60
b97cb21a 61#define F71808FG_FLAG_WDTMOUT_STS 6
96cb4eb0
GS		 62#define F71808FG_FLAG_WD_EN 5
63#define F71808FG_FLAG_WD_PULSE 4
64#define F71808FG_FLAG_WD_UNIT 3
65
ea0c03e8
KP		 66#define F81865_REG_WDO_CONF 0xfa
67#define F81865_FLAG_WDOUT_EN 0
68
96cb4eb0
GS		 69/* Default values */
70#define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */
71#define WATCHDOG_MAX_TIMEOUT (60 * 255)
72#define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for
73 watchdog signal */
7977ff6e
LB		 74#define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output
75 pin number 63 */
96cb4eb0
GS		 76
77static unsigned short force_id;
78module_param(force_id, ushort, 0);
79MODULE_PARM_DESC(force_id, "Override the detected device ID");
80
81static const int max_timeout = WATCHDOG_MAX_TIMEOUT;
f9a9f096 82static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */
96cb4eb0
GS		 83module_param(timeout, int, 0);
84MODULE_PARM_DESC(timeout,
85 "Watchdog timeout in seconds. 1<= timeout <="
86 __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default="
87 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
88
89static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH;
90module_param(pulse_width, uint, 0);
91MODULE_PARM_DESC(pulse_width,
166fbcf8 92 "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
96cb4eb0
GS		 93 " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")");
94
7977ff6e
LB		 95static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN;
96module_param(f71862fg_pin, uint, 0);
97MODULE_PARM_DESC(f71862fg_pin,
98 "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
99 " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")");
100
90ab5ee9 101static bool nowayout = WATCHDOG_NOWAYOUT;
96cb4eb0
GS		 102module_param(nowayout, bool, 0444);
103MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
104
105static unsigned int start_withtimeout;
106module_param(start_withtimeout, uint, 0);
107MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
108 " given initial timeout. Zero (default) disables this feature.");
109
166fbcf8
MS		 110enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
111 f81865, f81866};
96cb4eb0
GS		 112
113static const char *f71808e_names[] = {
114 "f71808fg",
115 "f71858fg",
116 "f71862fg",
166fbcf8 117 "f71868",
df278dac 118 "f71869",
96cb4eb0
GS		 119 "f71882fg",
120 "f71889fg",
ea0c03e8 121 "f81865",
14b24a88 122 "f81866",
96cb4eb0
GS		 123};
124
125/* Super-I/O Function prototypes */
126static inline int superio_inb(int base, int reg);
127static inline int superio_inw(int base, int reg);
128static inline void superio_outb(int base, int reg, u8 val);
129static inline void superio_set_bit(int base, int reg, int bit);
130static inline void superio_clear_bit(int base, int reg, int bit);
131static inline int superio_enter(int base);
132static inline void superio_select(int base, int ld);
133static inline void superio_exit(int base);
134
135struct watchdog_data {
136 unsigned short sioaddr;
137 enum chips type;
138 unsigned long opened;
139 struct mutex lock;
140 char expect_close;
141 struct watchdog_info ident;
142
143 unsigned short timeout;
144 u8 timer_val; /* content for the wd_time register */
145 char minutes_mode;
146 u8 pulse_val; /* pulse width flag */
147 char pulse_mode; /* enable pulse output mode? */
148 char caused_reboot; /* last reboot was by the watchdog */
149};
150
151static struct watchdog_data watchdog = {
152 .lock = __MUTEX_INITIALIZER(watchdog.lock),
153};
154
155/* Super I/O functions */
156static inline int superio_inb(int base, int reg)
157{
158 outb(reg, base);
159 return inb(base + 1);
160}
161
162static int superio_inw(int base, int reg)
163{
164 int val;
165 val = superio_inb(base, reg) << 8;
166 val |= superio_inb(base, reg + 1);
167 return val;
168}
169
170static inline void superio_outb(int base, int reg, u8 val)
171{
172 outb(reg, base);
173 outb(val, base + 1);
174}
175
176static inline void superio_set_bit(int base, int reg, int bit)
177{
178 unsigned long val = superio_inb(base, reg);
179 __set_bit(bit, &val);
180 superio_outb(base, reg, val);
181}
182
183static inline void superio_clear_bit(int base, int reg, int bit)
184{
185 unsigned long val = superio_inb(base, reg);
186 __clear_bit(bit, &val);
187 superio_outb(base, reg, val);
188}
189
190static inline int superio_enter(int base)
191{
192 /* Don't step on other drivers' I/O space by accident */
193 if (!request_muxed_region(base, 2, DRVNAME)) {
27c766aa 194 pr_err("I/O address 0x%04x already in use\n", (int)base);
96cb4eb0
GS		 195 return -EBUSY;
196 }
197
3017020d 198 /* according to the datasheet the key must be sent twice! */
96cb4eb0
GS		 199 outb(SIO_UNLOCK_KEY, base);
200 outb(SIO_UNLOCK_KEY, base);
201
202 return 0;
203}
204
205static inline void superio_select(int base, int ld)
206{
207 outb(SIO_REG_LDSEL, base);
208 outb(ld, base + 1);
209}
210
211static inline void superio_exit(int base)
212{
213 outb(SIO_LOCK_KEY, base);
214 release_region(base, 2);
215}
216
217static int watchdog_set_timeout(int timeout)
218{
219 if (timeout <= 0
220 || timeout > max_timeout) {
27c766aa 221 pr_err("watchdog timeout out of range\n");
96cb4eb0
GS		 222 return -EINVAL;
223 }
224
225 mutex_lock(&watchdog.lock);
226
227 watchdog.timeout = timeout;
228 if (timeout > 0xff) {
229 watchdog.timer_val = DIV_ROUND_UP(timeout, 60);
230 watchdog.minutes_mode = true;
231 } else {
232 watchdog.timer_val = timeout;
233 watchdog.minutes_mode = false;
234 }
235
236 mutex_unlock(&watchdog.lock);
237
238 return 0;
239}
240
241static int watchdog_set_pulse_width(unsigned int pw)
242{
243 int err = 0;
166fbcf8
MS		 244 unsigned int t1 = 25, t2 = 125, t3 = 5000;
245
246 if (watchdog.type == f71868) {
247 t1 = 30;
248 t2 = 150;
249 t3 = 6000;
250 }
96cb4eb0
GS		 251
252 mutex_lock(&watchdog.lock);
253
166fbcf8 254 if (pw <= 1) {
96cb4eb0 255 watchdog.pulse_val = 0;
166fbcf8 256 } else if (pw <= t1) {
96cb4eb0 257 watchdog.pulse_val = 1;
166fbcf8 258 } else if (pw <= t2) {
96cb4eb0 259 watchdog.pulse_val = 2;
166fbcf8 260 } else if (pw <= t3) {
96cb4eb0
GS		 261 watchdog.pulse_val = 3;
262 } else {
27c766aa 263 pr_err("pulse width out of range\n");
96cb4eb0
GS		 264 err = -EINVAL;
265 goto exit_unlock;
266 }
267
268 watchdog.pulse_mode = pw;
269
270exit_unlock:
271 mutex_unlock(&watchdog.lock);
272 return err;
273}
274
275static int watchdog_keepalive(void)
276{
277 int err = 0;
278
279 mutex_lock(&watchdog.lock);
280 err = superio_enter(watchdog.sioaddr);
281 if (err)
282 goto exit_unlock;
283 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
284
285 if (watchdog.minutes_mode)
286 /* select minutes for timer units */
287 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
288 F71808FG_FLAG_WD_UNIT);
289 else
290 /* select seconds for timer units */
291 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
292 F71808FG_FLAG_WD_UNIT);
293
294 /* Set timer value */
295 superio_outb(watchdog.sioaddr, F71808FG_REG_WD_TIME,
296 watchdog.timer_val);
297
298 superio_exit(watchdog.sioaddr);
299
300exit_unlock:
301 mutex_unlock(&watchdog.lock);
302 return err;
303}
304
7977ff6e
LB		 305static int f71862fg_pin_configure(unsigned short ioaddr)
306{
307 /* When ioaddr is non-zero the calling function has to take care of
308 mutex handling and superio preparation! */
309
310 if (f71862fg_pin == 63) {
311 if (ioaddr) {
312 /* SPI must be disabled first to use this pin! */
313 superio_clear_bit(ioaddr, SIO_REG_ROM_ADDR_SEL, 6);
314 superio_set_bit(ioaddr, SIO_REG_MFUNCT3, 4);
315 }
316 } else if (f71862fg_pin == 56) {
317 if (ioaddr)
318 superio_set_bit(ioaddr, SIO_REG_MFUNCT1, 1);
319 } else {
27c766aa 320 pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin);
7977ff6e
LB		 321 return -EINVAL;
322 }
323 return 0;
324}
325
96cb4eb0
GS		 326static int watchdog_start(void)
327{
a3f764d2 328 int err;
e347afa5 329 u8 tmp;
a3f764d2 330
96cb4eb0 331 /* Make sure we don't die as soon as the watchdog is enabled below */
a3f764d2 332 err = watchdog_keepalive();
96cb4eb0
GS		 333 if (err)
334 return err;
335
336 mutex_lock(&watchdog.lock);
337 err = superio_enter(watchdog.sioaddr);
338 if (err)
339 goto exit_unlock;
340 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
341
342 /* Watchdog pin configuration */
343 switch (watchdog.type) {
344 case f71808fg:
345 /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
f9a9f096
LB		 346 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT2, 3);
347 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 3);
96cb4eb0
GS		 348 break;
349
7977ff6e
LB		 350 case f71862fg:
351 err = f71862fg_pin_configure(watchdog.sioaddr);
352 if (err)
353 goto exit_superio;
354 break;
355
166fbcf8 356 case f71868:
df278dac
MA		 357 case f71869:
358 /* GPIO14 --> WDTRST# */
359 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4);
360 break;
361
96cb4eb0
GS		 362 case f71882fg:
363 /* Set pin 56 to WDTRST# */
f9a9f096 364 superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1);
96cb4eb0
GS		 365 break;
366
dee00abb
GS		 367 case f71889fg:
368 /* set pin 40 to WDTRST# */
f9a9f096
LB		 369 superio_outb(watchdog.sioaddr, SIO_REG_MFUNCT3,
370 superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf);
dee00abb
GS		 371 break;
372
ea0c03e8
KP		 373 case f81865:
374 /* Set pin 70 to WDTRST# */
375 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5);
376 break;
377
14b24a88 378 case f81866:
14b24a88
JZHPH		 379 /*
380 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
381 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
382 * BIT5: 0 -> WDTRST#
383 * 1 -> GPIO15
384 */
e347afa5
JZHPH		 385 tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL);
386 tmp &= ~(BIT(3) | BIT(0));
387 tmp |= BIT(2);
388 superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
389
390 superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);
14b24a88
JZHPH		 391 break;
392
96cb4eb0
GS		 393 default:
394 /*
395 * 'default' label to shut up the compiler and catch
396 * programmer errors
397 */
398 err = -ENODEV;
399 goto exit_superio;
400 }
401
402 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
403 superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0);
ea0c03e8 404
14b24a88 405 if (watchdog.type == f81865 || watchdog.type == f81866)
ea0c03e8
KP		 406 superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF,
407 F81865_FLAG_WDOUT_EN);
408 else
409 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
410 F71808FG_FLAG_WDOUT_EN);
96cb4eb0
GS		 411
412 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
413 F71808FG_FLAG_WD_EN);
414
415 if (watchdog.pulse_mode) {
416 /* Select "pulse" output mode with given duration */
417 u8 wdt_conf = superio_inb(watchdog.sioaddr,
418 F71808FG_REG_WDT_CONF);
419
420 /* Set WD_PSWIDTH bits (1:0) */
421 wdt_conf = (wdt_conf & 0xfc) | (watchdog.pulse_val & 0x03);
422 /* Set WD_PULSE to "pulse" mode */
423 wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
424
425 superio_outb(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
426 wdt_conf);
427 } else {
428 /* Select "level" output mode */
429 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
430 F71808FG_FLAG_WD_PULSE);
431 }
432
433exit_superio:
434 superio_exit(watchdog.sioaddr);
435exit_unlock:
436 mutex_unlock(&watchdog.lock);
437
438 return err;
439}
440
441static int watchdog_stop(void)
442{
443 int err = 0;
444
445 mutex_lock(&watchdog.lock);
446 err = superio_enter(watchdog.sioaddr);
447 if (err)
448 goto exit_unlock;
449 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
450
451 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
452 F71808FG_FLAG_WD_EN);
453
454 superio_exit(watchdog.sioaddr);
455
456exit_unlock:
457 mutex_unlock(&watchdog.lock);
458
459 return err;
460}
461
462static int watchdog_get_status(void)
463{
464 int status = 0;
465
466 mutex_lock(&watchdog.lock);
467 status = (watchdog.caused_reboot) ? WDIOF_CARDRESET : 0;
468 mutex_unlock(&watchdog.lock);
469
470 return status;
471}
472
473static bool watchdog_is_running(void)
474{
475 /*
476 * if we fail to determine the watchdog's status assume it to be
477 * running to be on the safe side
478 */
479 bool is_running = true;
480
481 mutex_lock(&watchdog.lock);
482 if (superio_enter(watchdog.sioaddr))
483 goto exit_unlock;
484 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
485
486 is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
487 && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
977f6f68 488 & BIT(F71808FG_FLAG_WD_EN));
96cb4eb0
GS		 489
490 superio_exit(watchdog.sioaddr);
491
492exit_unlock:
493 mutex_unlock(&watchdog.lock);
494 return is_running;
495}
496
497/* /dev/watchdog api */
498
499static int watchdog_open(struct inode *inode, struct file *file)
500{
501 int err;
502
503 /* If the watchdog is alive we don't need to start it again */
504 if (test_and_set_bit(0, &watchdog.opened))
505 return -EBUSY;
506
507 err = watchdog_start();
508 if (err) {
509 clear_bit(0, &watchdog.opened);
510 return err;
511 }
512
513 if (nowayout)
514 __module_get(THIS_MODULE);
515
516 watchdog.expect_close = 0;
c5bf68fe 517 return stream_open(inode, file);
96cb4eb0
GS		 518}
519
520static int watchdog_release(struct inode *inode, struct file *file)
521{
522 clear_bit(0, &watchdog.opened);
523
524 if (!watchdog.expect_close) {
525 watchdog_keepalive();
27c766aa 526 pr_crit("Unexpected close, not stopping watchdog!\n");
96cb4eb0
GS		 527 } else if (!nowayout) {
528 watchdog_stop();
529 }
530 return 0;
531}
532
533/*
534 * watchdog_write:
535 * @file: file handle to the watchdog
536 * @buf: buffer to write
537 * @count: count of bytes
538 * @ppos: pointer to the position to write. No seeks allowed
539 *
540 * A write to a watchdog device is defined as a keepalive signal. Any
541 * write of data will do, as we we don't define content meaning.
542 */
543
544static ssize_t watchdog_write(struct file *file, const char __user *buf,
545 size_t count, loff_t *ppos)
546{
547 if (count) {
548 if (!nowayout) {
549 size_t i;
550
551 /* In case it was set long ago */
552 bool expect_close = false;
553
554 for (i = 0; i != count; i++) {
555 char c;
556 if (get_user(c, buf + i))
557 return -EFAULT;
7bd3e7b7
IP		 558 if (c == 'V')
559 expect_close = true;
96cb4eb0
GS		 560 }
561
562 /* Properly order writes across fork()ed processes */
563 mutex_lock(&watchdog.lock);
564 watchdog.expect_close = expect_close;
565 mutex_unlock(&watchdog.lock);
566 }
567
568 /* someone wrote to us, we should restart timer */
569 watchdog_keepalive();
570 }
571 return count;
572}
573
574/*
575 * watchdog_ioctl:
576 * @inode: inode of the device
577 * @file: file handle to the device
578 * @cmd: watchdog command
579 * @arg: argument pointer
580 *
581 * The watchdog API defines a common set of functions for all watchdogs
582 * according to their available features.
583 */
584static long watchdog_ioctl(struct file *file, unsigned int cmd,
585 unsigned long arg)
586{
587 int status;
588 int new_options;
589 int new_timeout;
590 union {
591 struct watchdog_info __user *ident;
592 int __user *i;
593 } uarg;
594
595 uarg.i = (int __user *)arg;
596
597 switch (cmd) {
598 case WDIOC_GETSUPPORT:
599 return copy_to_user(uarg.ident, &watchdog.ident,
600 sizeof(watchdog.ident)) ? -EFAULT : 0;
601
602 case WDIOC_GETSTATUS:
603 status = watchdog_get_status();
604 if (status < 0)
605 return status;
606 return put_user(status, uarg.i);
607
608 case WDIOC_GETBOOTSTATUS:
609 return put_user(0, uarg.i);
610
611 case WDIOC_SETOPTIONS:
612 if (get_user(new_options, uarg.i))
613 return -EFAULT;
614
615 if (new_options & WDIOS_DISABLECARD)
616 watchdog_stop();
617
618 if (new_options & WDIOS_ENABLECARD)
619 return watchdog_start();
fd846b57 620 /* fall through */
96cb4eb0
GS		 621
622 case WDIOC_KEEPALIVE:
623 watchdog_keepalive();
624 return 0;
625
626 case WDIOC_SETTIMEOUT:
627 if (get_user(new_timeout, uarg.i))
628 return -EFAULT;
629
630 if (watchdog_set_timeout(new_timeout))
631 return -EINVAL;
632
633 watchdog_keepalive();
fd846b57 634 /* fall through */
96cb4eb0
GS		 635
636 case WDIOC_GETTIMEOUT:
637 return put_user(watchdog.timeout, uarg.i);
638
639 default:
640 return -ENOTTY;
641
642 }
643}
644
645static int watchdog_notify_sys(struct notifier_block *this, unsigned long code,
646 void *unused)
647{
648 if (code == SYS_DOWN || code == SYS_HALT)
649 watchdog_stop();
650 return NOTIFY_DONE;
651}
652
653static const struct file_operations watchdog_fops = {
654 .owner = THIS_MODULE,
655 .llseek = no_llseek,
656 .open = watchdog_open,
657 .release = watchdog_release,
658 .write = watchdog_write,
659 .unlocked_ioctl = watchdog_ioctl,
660};
661
662static struct miscdevice watchdog_miscdev = {
663 .minor = WATCHDOG_MINOR,
664 .name = "watchdog",
665 .fops = &watchdog_fops,
666};
667
668static struct notifier_block watchdog_notifier = {
669 .notifier_call = watchdog_notify_sys,
670};
671
672static int __init watchdog_init(int sioaddr)
673{
674 int wdt_conf, err = 0;
675
676 /* No need to lock watchdog.lock here because no entry points
677 * into the module have been registered yet.
678 */
679 watchdog.sioaddr = sioaddr;
680 watchdog.ident.options = WDIOC_SETTIMEOUT
681 | WDIOF_MAGICCLOSE
682 | WDIOF_KEEPALIVEPING;
683
684 snprintf(watchdog.ident.identity,
685 sizeof(watchdog.ident.identity), "%s watchdog",
686 f71808e_names[watchdog.type]);
687
688 err = superio_enter(sioaddr);
689 if (err)
690 return err;
691 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
692
693 wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
b97cb21a 694 watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS);
96cb4eb0
GS		 695
696 superio_exit(sioaddr);
697
698 err = watchdog_set_timeout(timeout);
699 if (err)
700 return err;
701 err = watchdog_set_pulse_width(pulse_width);
702 if (err)
703 return err;
704
705 err = register_reboot_notifier(&watchdog_notifier);
706 if (err)
707 return err;
708
709 err = misc_register(&watchdog_miscdev);
710 if (err) {
27c766aa
JP		 711 pr_err("cannot register miscdev on minor=%d\n",
712 watchdog_miscdev.minor);
96cb4eb0
GS		 713 goto exit_reboot;
714 }
715
716 if (start_withtimeout) {
717 if (start_withtimeout <= 0
718 || start_withtimeout > max_timeout) {
27c766aa 719 pr_err("starting timeout out of range\n");
96cb4eb0
GS		 720 err = -EINVAL;
721 goto exit_miscdev;
722 }
723
724 err = watchdog_start();
725 if (err) {
27c766aa 726 pr_err("cannot start watchdog timer\n");
96cb4eb0
GS		 727 goto exit_miscdev;
728 }
729
730 mutex_lock(&watchdog.lock);
731 err = superio_enter(sioaddr);
732 if (err)
733 goto exit_unlock;
734 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
735
736 if (start_withtimeout > 0xff) {
737 /* select minutes for timer units */
738 superio_set_bit(sioaddr, F71808FG_REG_WDT_CONF,
739 F71808FG_FLAG_WD_UNIT);
740 superio_outb(sioaddr, F71808FG_REG_WD_TIME,
741 DIV_ROUND_UP(start_withtimeout, 60));
742 } else {
743 /* select seconds for timer units */
744 superio_clear_bit(sioaddr, F71808FG_REG_WDT_CONF,
745 F71808FG_FLAG_WD_UNIT);
746 superio_outb(sioaddr, F71808FG_REG_WD_TIME,
747 start_withtimeout);
748 }
749
750 superio_exit(sioaddr);
751 mutex_unlock(&watchdog.lock);
752
753 if (nowayout)
754 __module_get(THIS_MODULE);
755
27c766aa 756 pr_info("watchdog started with initial timeout of %u sec\n",
96cb4eb0
GS		 757 start_withtimeout);
758 }
759
760 return 0;
761
762exit_unlock:
763 mutex_unlock(&watchdog.lock);
764exit_miscdev:
765 misc_deregister(&watchdog_miscdev);
766exit_reboot:
767 unregister_reboot_notifier(&watchdog_notifier);
768
769 return err;
770}
771
772static int __init f71808e_find(int sioaddr)
773{
774 u16 devid;
775 int err = superio_enter(sioaddr);
776 if (err)
777 return err;
778
779 devid = superio_inw(sioaddr, SIO_REG_MANID);
780 if (devid != SIO_FINTEK_ID) {
27c766aa 781 pr_debug("Not a Fintek device\n");
96cb4eb0
GS		 782 err = -ENODEV;
783 goto exit;
784 }
785
786 devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
787 switch (devid) {
788 case SIO_F71808_ID:
789 watchdog.type = f71808fg;
790 break;
7977ff6e
LB		 791 case SIO_F71862_ID:
792 watchdog.type = f71862fg;
793 err = f71862fg_pin_configure(0); /* validate module parameter */
794 break;
166fbcf8
MS		 795 case SIO_F71868_ID:
796 watchdog.type = f71868;
797 break;
df278dac 798 case SIO_F71869_ID:
3017020d 799 case SIO_F71869A_ID:
df278dac
MA		 800 watchdog.type = f71869;
801 break;
96cb4eb0
GS		 802 case SIO_F71882_ID:
803 watchdog.type = f71882fg;
804 break;
96cb4eb0 805 case SIO_F71889_ID:
dee00abb
GS		 806 watchdog.type = f71889fg;
807 break;
96cb4eb0
GS		 808 case SIO_F71858_ID:
809 /* Confirmed (by datasheet) not to have a watchdog. */
810 err = -ENODEV;
811 goto exit;
ea0c03e8
KP		 812 case SIO_F81865_ID:
813 watchdog.type = f81865;
14b24a88
JZHPH		 814 break;
815 case SIO_F81866_ID:
816 watchdog.type = f81866;
ea0c03e8 817 break;
96cb4eb0 818 default:
27c766aa
JP		 819 pr_info("Unrecognized Fintek device: %04x\n",
820 (unsigned int)devid);
96cb4eb0
GS		 821 err = -ENODEV;
822 goto exit;
823 }
824
27c766aa 825 pr_info("Found %s watchdog chip, revision %d\n",
96cb4eb0
GS		 826 f71808e_names[watchdog.type],
827 (int)superio_inb(sioaddr, SIO_REG_DEVREV));
828exit:
829 superio_exit(sioaddr);
830 return err;
831}
832
833static int __init f71808e_init(void)
834{
835 static const unsigned short addrs[] = { 0x2e, 0x4e };
836 int err = -ENODEV;
837 int i;
838
839 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
840 err = f71808e_find(addrs[i]);
841 if (err == 0)
842 break;
843 }
844 if (i == ARRAY_SIZE(addrs))
845 return err;
846
847 return watchdog_init(addrs[i]);
848}
849
850static void __exit f71808e_exit(void)
851{
852 if (watchdog_is_running()) {
27c766aa 853 pr_warn("Watchdog timer still running, stopping it\n");
96cb4eb0
GS		 854 watchdog_stop();
855 }
856 misc_deregister(&watchdog_miscdev);
857 unregister_reboot_notifier(&watchdog_notifier);
858}
859
860MODULE_DESCRIPTION("F71808E Watchdog Driver");
861MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>");
862MODULE_LICENSE("GPL");
863
864module_init(f71808e_init);
865module_exit(f71808e_exit);
A mirror of Linus' kernel repository