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Commit | Line | Data |
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abbab703 TK |
1 | /* |
2 | * watchdog.c - driver for i.mx on-chip watchdog | |
3 | * | |
4 | * Licensed under the GPL-2 or later. | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
9 | #include <watchdog.h> | |
10 | #include <asm/arch/imx-regs.h> | |
11 | ||
12 | struct watchdog_regs { | |
13 | u16 wcr; /* Control */ | |
14 | u16 wsr; /* Service */ | |
15 | u16 wrsr; /* Reset Status */ | |
16 | }; | |
17 | ||
18 | #define WCR_WDZST 0x01 | |
19 | #define WCR_WDBG 0x02 | |
20 | #define WCR_WDE 0x04 /* WDOG enable */ | |
21 | #define WCR_WDT 0x08 | |
723ec69a | 22 | #define WCR_SRS 0x10 |
abbab703 TK |
23 | #define WCR_WDW 0x80 |
24 | #define SET_WCR_WT(x) (x << 8) | |
25 | ||
26 | #ifdef CONFIG_IMX_WATCHDOG | |
27 | void hw_watchdog_reset(void) | |
28 | { | |
29 | struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; | |
30 | ||
31 | writew(0x5555, &wdog->wsr); | |
32 | writew(0xaaaa, &wdog->wsr); | |
33 | } | |
34 | ||
35 | void hw_watchdog_init(void) | |
36 | { | |
37 | struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; | |
38 | u16 timeout; | |
39 | ||
40 | /* | |
41 | * The timer watchdog can be set between | |
42 | * 0.5 and 128 Seconds. If not defined | |
43 | * in configuration file, sets 128 Seconds | |
44 | */ | |
45 | #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS | |
46 | #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 | |
47 | #endif | |
48 | timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; | |
723ec69a | 49 | writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | |
abbab703 TK |
50 | WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); |
51 | hw_watchdog_reset(); | |
52 | } | |
53 | #endif | |
54 | ||
55 | void reset_cpu(ulong addr) | |
56 | { | |
57 | struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; | |
58 | ||
59 | writew(WCR_WDE, &wdog->wcr); | |
60 | writew(0x5555, &wdog->wsr); | |
61 | writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ | |
62 | while (1) { | |
63 | /* | |
64 | * spin for .5 seconds before reset | |
65 | */ | |
66 | } | |
67 | } |