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fabbfb9e 1/*
0d7b1014 2 * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
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3 *
4 * Authors: Dave Updegraff <dave@cray.org>
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5 * Kumar Gala <galak@kernel.crashing.org>
6 * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
7 * ..and from sc520_wdt
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8 * Copyright (c) 2008 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
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10 *
11 * Note: it appears that you can only actually ENABLE or DISABLE the thing
12 * once after POR. Once enabled, you cannot disable, and vice versa.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
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20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
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22#include <linux/fs.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
500c919e 25#include <linux/timer.h>
fabbfb9e 26#include <linux/miscdevice.h>
5af50730 27#include <linux/of_address.h>
ef8ab12e 28#include <linux/of_platform.h>
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29#include <linux/module.h>
30#include <linux/watchdog.h>
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31#include <linux/io.h>
32#include <linux/uaccess.h>
ef8ab12e 33#include <sysdev/fsl_soc.h>
fabbfb9e 34
59ca1b0d 35struct mpc8xxx_wdt {
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36 __be32 res0;
37 __be32 swcrr; /* System watchdog control register */
38#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
39#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
40#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
41#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
42 __be32 swcnr; /* System watchdog count register */
43 u8 res1[2];
44 __be16 swsrr; /* System watchdog service register */
45 u8 res2[0xF0];
46};
47
59ca1b0d 48struct mpc8xxx_wdt_type {
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49 int prescaler;
50 bool hw_enabled;
51};
52
59ca1b0d 53static struct mpc8xxx_wdt __iomem *wd_base;
593fc178 54static int mpc8xxx_wdt_init_late(void);
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55
56static u16 timeout = 0xffff;
57module_param(timeout, ushort, 0);
f26ef3dc 58MODULE_PARM_DESC(timeout,
76550d32 59 "Watchdog timeout in ticks. (0<timeout<65536, default=65535)");
fabbfb9e 60
90ab5ee9 61static bool reset = 1;
fabbfb9e 62module_param(reset, bool, 0);
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63MODULE_PARM_DESC(reset,
64 "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
fabbfb9e 65
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66static bool nowayout = WATCHDOG_NOWAYOUT;
67module_param(nowayout, bool, 0);
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68MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
69 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
70
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71/*
72 * We always prescale, but if someone really doesn't want to they can set this
73 * to 0
74 */
75static int prescale = 1;
fabbfb9e 76
c7dfd0cc 77static DEFINE_SPINLOCK(wdt_spinlock);
fabbfb9e 78
59ca1b0d 79static void mpc8xxx_wdt_keepalive(void)
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80{
81 /* Ping the WDT */
82 spin_lock(&wdt_spinlock);
83 out_be16(&wd_base->swsrr, 0x556c);
84 out_be16(&wd_base->swsrr, 0xaa39);
85 spin_unlock(&wdt_spinlock);
86}
87
d5cfaf0a 88static struct watchdog_device mpc8xxx_wdt_dev;
59ca1b0d 89static void mpc8xxx_wdt_timer_ping(unsigned long arg);
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90static DEFINE_TIMER(wdt_timer, mpc8xxx_wdt_timer_ping, 0,
91 (unsigned long)&mpc8xxx_wdt_dev);
500c919e 92
59ca1b0d 93static void mpc8xxx_wdt_timer_ping(unsigned long arg)
500c919e 94{
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95 struct watchdog_device *w = (struct watchdog_device *)arg;
96
59ca1b0d 97 mpc8xxx_wdt_keepalive();
500c919e 98 /* We're pinging it twice faster than needed, just to be sure. */
d5cfaf0a 99 mod_timer(&wdt_timer, jiffies + HZ * w->timeout / 2);
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100}
101
d5cfaf0a 102static int mpc8xxx_wdt_start(struct watchdog_device *w)
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103{
104 u32 tmp = SWCRR_SWEN;
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105
106 /* Good, fire up the show */
107 if (prescale)
108 tmp |= SWCRR_SWPR;
109 if (reset)
110 tmp |= SWCRR_SWRI;
111
112 tmp |= timeout << 16;
113
114 out_be32(&wd_base->swcrr, tmp);
115
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116 del_timer_sync(&wdt_timer);
117
d5cfaf0a 118 return 0;
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119}
120
d5cfaf0a 121static int mpc8xxx_wdt_ping(struct watchdog_device *w)
fabbfb9e 122{
d5cfaf0a 123 mpc8xxx_wdt_keepalive();
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124 return 0;
125}
126
d5cfaf0a 127static int mpc8xxx_wdt_stop(struct watchdog_device *w)
fabbfb9e 128{
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129 mod_timer(&wdt_timer, jiffies);
130 return 0;
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131}
132
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133static struct watchdog_info mpc8xxx_wdt_info = {
134 .options = WDIOF_KEEPALIVEPING,
135 .firmware_version = 1,
136 .identity = "MPC8xxx",
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137};
138
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139static struct watchdog_ops mpc8xxx_wdt_ops = {
140 .owner = THIS_MODULE,
141 .start = mpc8xxx_wdt_start,
142 .ping = mpc8xxx_wdt_ping,
143 .stop = mpc8xxx_wdt_stop,
144};
145
146static struct watchdog_device mpc8xxx_wdt_dev = {
147 .info = &mpc8xxx_wdt_info,
148 .ops = &mpc8xxx_wdt_ops,
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149};
150
b1608d69 151static const struct of_device_id mpc8xxx_wdt_match[];
2d991a16 152static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
fabbfb9e 153{
fabbfb9e 154 int ret;
b1608d69 155 const struct of_device_id *match;
de2b606c 156 struct device_node *np = ofdev->dev.of_node;
639397e4 157 const struct mpc8xxx_wdt_type *wdt_type;
ef8ab12e 158 u32 freq = fsl_get_sys_freq();
500c919e 159 bool enabled;
d5cfaf0a 160 unsigned int timeout_sec;
fabbfb9e 161
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162 match = of_match_device(mpc8xxx_wdt_match, &ofdev->dev);
163 if (!match)
1c48a5c9 164 return -EINVAL;
b1608d69 165 wdt_type = match->data;
1c48a5c9 166
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167 if (!freq || freq == -1)
168 return -EINVAL;
fabbfb9e 169
500c919e 170 wd_base = of_iomap(np, 0);
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171 if (!wd_base)
172 return -ENOMEM;
fabbfb9e 173
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174 enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN;
175 if (!enabled && wdt_type->hw_enabled) {
27c766aa 176 pr_info("could not be enabled in software\n");
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177 ret = -ENOSYS;
178 goto err_unmap;
179 }
180
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181 /* Calculate the timeout in seconds */
182 if (prescale)
500c919e 183 timeout_sec = (timeout * wdt_type->prescaler) / freq;
fabbfb9e 184 else
ef8ab12e 185 timeout_sec = timeout / freq;
fabbfb9e 186
d5cfaf0a 187 mpc8xxx_wdt_dev.timeout = timeout_sec;
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188#ifdef MODULE
189 ret = mpc8xxx_wdt_init_late();
190 if (ret)
191 goto err_unmap;
192#endif
193
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194 pr_info("WDT driver for MPC8xxx initialized. mode:%s timeout=%d (%d seconds)\n",
195 reset ? "reset" : "interrupt", timeout, timeout_sec);
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196
197 /*
198 * If the watchdog was previously enabled or we're running on
59ca1b0d 199 * MPC8xxx, we should ping the wdt from the kernel until the
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200 * userspace handles it.
201 */
202 if (enabled)
d5cfaf0a 203 mod_timer(&wdt_timer, jiffies);
fabbfb9e 204 return 0;
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205err_unmap:
206 iounmap(wd_base);
0d7b1014 207 wd_base = NULL;
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208 return ret;
209}
210
4b12b896 211static int mpc8xxx_wdt_remove(struct platform_device *ofdev)
fabbfb9e 212{
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213 pr_crit("Watchdog removed, expect the %s soon!\n",
214 reset ? "reset" : "machine check exception");
500c919e 215 del_timer_sync(&wdt_timer);
d5cfaf0a 216 watchdog_unregister_device(&mpc8xxx_wdt_dev);
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217 iounmap(wd_base);
218
219 return 0;
220}
221
59ca1b0d 222static const struct of_device_id mpc8xxx_wdt_match[] = {
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223 {
224 .compatible = "mpc83xx_wdt",
59ca1b0d 225 .data = &(struct mpc8xxx_wdt_type) {
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226 .prescaler = 0x10000,
227 },
228 },
229 {
230 .compatible = "fsl,mpc8610-wdt",
59ca1b0d 231 .data = &(struct mpc8xxx_wdt_type) {
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232 .prescaler = 0x10000,
233 .hw_enabled = true,
234 },
ef8ab12e 235 },
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236 {
237 .compatible = "fsl,mpc823-wdt",
238 .data = &(struct mpc8xxx_wdt_type) {
239 .prescaler = 0x800,
240 },
241 },
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242 {},
243};
59ca1b0d 244MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
ef8ab12e 245
1c48a5c9 246static struct platform_driver mpc8xxx_wdt_driver = {
59ca1b0d 247 .probe = mpc8xxx_wdt_probe,
82268714 248 .remove = mpc8xxx_wdt_remove,
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249 .driver = {
250 .name = "mpc8xxx_wdt",
251 .owner = THIS_MODULE,
252 .of_match_table = mpc8xxx_wdt_match,
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253 },
254};
255
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256/*
257 * We do wdt initialization in two steps: arch_initcall probes the wdt
258 * very early to start pinging the watchdog (misc devices are not yet
259 * available), and later module_init() just registers the misc device.
260 */
593fc178 261static int mpc8xxx_wdt_init_late(void)
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262{
263 int ret;
264
265 if (!wd_base)
266 return -ENODEV;
267
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268 watchdog_set_nowayout(&mpc8xxx_wdt_dev, nowayout);
269
270 ret = watchdog_register_device(&mpc8xxx_wdt_dev);
0d7b1014 271 if (ret) {
d5cfaf0a 272 pr_err("cannot register watchdog device (err=%d)\n", ret);
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273 return ret;
274 }
275 return 0;
276}
593fc178 277#ifndef MODULE
0d7b1014 278module_init(mpc8xxx_wdt_init_late);
593fc178 279#endif
0d7b1014 280
59ca1b0d 281static int __init mpc8xxx_wdt_init(void)
fabbfb9e 282{
1c48a5c9 283 return platform_driver_register(&mpc8xxx_wdt_driver);
fabbfb9e 284}
0d7b1014 285arch_initcall(mpc8xxx_wdt_init);
fabbfb9e 286
59ca1b0d 287static void __exit mpc8xxx_wdt_exit(void)
fabbfb9e 288{
1c48a5c9 289 platform_driver_unregister(&mpc8xxx_wdt_driver);
fabbfb9e 290}
59ca1b0d 291module_exit(mpc8xxx_wdt_exit);
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292
293MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
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294MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
295 "uProcessors");
fabbfb9e 296MODULE_LICENSE("GPL");