]> git.ipfire.org Git - people/ms/linux.git/blame - drivers/watchdog/mpc8xxx_wdt.c
watchdog: mpc8xxx: simplify registration
[people/ms/linux.git] / drivers / watchdog / mpc8xxx_wdt.c
CommitLineData
fabbfb9e 1/*
0d7b1014 2 * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
fabbfb9e
KG
3 *
4 * Authors: Dave Updegraff <dave@cray.org>
5f3b2756
WVS
5 * Kumar Gala <galak@kernel.crashing.org>
6 * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
7 * ..and from sc520_wdt
500c919e
AV
8 * Copyright (c) 2008 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
fabbfb9e
KG
10 *
11 * Note: it appears that you can only actually ENABLE or DISABLE the thing
12 * once after POR. Once enabled, you cannot disable, and vice versa.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
27c766aa
JP
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
fabbfb9e
KG
22#include <linux/fs.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
500c919e 25#include <linux/timer.h>
fabbfb9e 26#include <linux/miscdevice.h>
5af50730 27#include <linux/of_address.h>
ef8ab12e 28#include <linux/of_platform.h>
fabbfb9e
KG
29#include <linux/module.h>
30#include <linux/watchdog.h>
f26ef3dc
AC
31#include <linux/io.h>
32#include <linux/uaccess.h>
ef8ab12e 33#include <sysdev/fsl_soc.h>
fabbfb9e 34
59ca1b0d 35struct mpc8xxx_wdt {
fabbfb9e
KG
36 __be32 res0;
37 __be32 swcrr; /* System watchdog control register */
38#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
39#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
40#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
41#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
42 __be32 swcnr; /* System watchdog count register */
43 u8 res1[2];
44 __be16 swsrr; /* System watchdog service register */
45 u8 res2[0xF0];
46};
47
59ca1b0d 48struct mpc8xxx_wdt_type {
500c919e
AV
49 int prescaler;
50 bool hw_enabled;
51};
52
59ca1b0d 53static struct mpc8xxx_wdt __iomem *wd_base;
fabbfb9e
KG
54
55static u16 timeout = 0xffff;
56module_param(timeout, ushort, 0);
f26ef3dc 57MODULE_PARM_DESC(timeout,
76550d32 58 "Watchdog timeout in ticks. (0<timeout<65536, default=65535)");
fabbfb9e 59
90ab5ee9 60static bool reset = 1;
fabbfb9e 61module_param(reset, bool, 0);
f26ef3dc
AC
62MODULE_PARM_DESC(reset,
63 "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
fabbfb9e 64
86a1e189
WVS
65static bool nowayout = WATCHDOG_NOWAYOUT;
66module_param(nowayout, bool, 0);
500c919e
AV
67MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
68 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
69
c7dfd0cc 70static DEFINE_SPINLOCK(wdt_spinlock);
fabbfb9e 71
59ca1b0d 72static void mpc8xxx_wdt_keepalive(void)
fabbfb9e
KG
73{
74 /* Ping the WDT */
75 spin_lock(&wdt_spinlock);
76 out_be16(&wd_base->swsrr, 0x556c);
77 out_be16(&wd_base->swsrr, 0xaa39);
78 spin_unlock(&wdt_spinlock);
79}
80
d5cfaf0a 81static struct watchdog_device mpc8xxx_wdt_dev;
59ca1b0d 82static void mpc8xxx_wdt_timer_ping(unsigned long arg);
d5cfaf0a
CL
83static DEFINE_TIMER(wdt_timer, mpc8xxx_wdt_timer_ping, 0,
84 (unsigned long)&mpc8xxx_wdt_dev);
500c919e 85
59ca1b0d 86static void mpc8xxx_wdt_timer_ping(unsigned long arg)
500c919e 87{
d5cfaf0a
CL
88 struct watchdog_device *w = (struct watchdog_device *)arg;
89
59ca1b0d 90 mpc8xxx_wdt_keepalive();
500c919e 91 /* We're pinging it twice faster than needed, just to be sure. */
d5cfaf0a 92 mod_timer(&wdt_timer, jiffies + HZ * w->timeout / 2);
500c919e
AV
93}
94
d5cfaf0a 95static int mpc8xxx_wdt_start(struct watchdog_device *w)
fabbfb9e 96{
a57e06f7 97 u32 tmp = SWCRR_SWEN | SWCRR_SWPR;
fabbfb9e
KG
98
99 /* Good, fire up the show */
fabbfb9e
KG
100 if (reset)
101 tmp |= SWCRR_SWRI;
102
103 tmp |= timeout << 16;
104
105 out_be32(&wd_base->swcrr, tmp);
106
500c919e
AV
107 del_timer_sync(&wdt_timer);
108
d5cfaf0a 109 return 0;
fabbfb9e
KG
110}
111
d5cfaf0a 112static int mpc8xxx_wdt_ping(struct watchdog_device *w)
fabbfb9e 113{
d5cfaf0a 114 mpc8xxx_wdt_keepalive();
fabbfb9e
KG
115 return 0;
116}
117
d5cfaf0a 118static int mpc8xxx_wdt_stop(struct watchdog_device *w)
fabbfb9e 119{
d5cfaf0a
CL
120 mod_timer(&wdt_timer, jiffies);
121 return 0;
fabbfb9e
KG
122}
123
d5cfaf0a
CL
124static struct watchdog_info mpc8xxx_wdt_info = {
125 .options = WDIOF_KEEPALIVEPING,
126 .firmware_version = 1,
127 .identity = "MPC8xxx",
fabbfb9e
KG
128};
129
d5cfaf0a
CL
130static struct watchdog_ops mpc8xxx_wdt_ops = {
131 .owner = THIS_MODULE,
132 .start = mpc8xxx_wdt_start,
133 .ping = mpc8xxx_wdt_ping,
134 .stop = mpc8xxx_wdt_stop,
135};
136
137static struct watchdog_device mpc8xxx_wdt_dev = {
138 .info = &mpc8xxx_wdt_info,
139 .ops = &mpc8xxx_wdt_ops,
fabbfb9e
KG
140};
141
b1608d69 142static const struct of_device_id mpc8xxx_wdt_match[];
2d991a16 143static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
fabbfb9e 144{
fabbfb9e 145 int ret;
b1608d69 146 const struct of_device_id *match;
de2b606c 147 struct device_node *np = ofdev->dev.of_node;
639397e4 148 const struct mpc8xxx_wdt_type *wdt_type;
ef8ab12e 149 u32 freq = fsl_get_sys_freq();
500c919e 150 bool enabled;
d5cfaf0a 151 unsigned int timeout_sec;
fabbfb9e 152
b1608d69
GL
153 match = of_match_device(mpc8xxx_wdt_match, &ofdev->dev);
154 if (!match)
1c48a5c9 155 return -EINVAL;
b1608d69 156 wdt_type = match->data;
1c48a5c9 157
ef8ab12e
AV
158 if (!freq || freq == -1)
159 return -EINVAL;
fabbfb9e 160
500c919e 161 wd_base = of_iomap(np, 0);
ef8ab12e
AV
162 if (!wd_base)
163 return -ENOMEM;
fabbfb9e 164
500c919e
AV
165 enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN;
166 if (!enabled && wdt_type->hw_enabled) {
27c766aa 167 pr_info("could not be enabled in software\n");
500c919e
AV
168 ret = -ENOSYS;
169 goto err_unmap;
170 }
171
fabbfb9e 172 /* Calculate the timeout in seconds */
a57e06f7 173 timeout_sec = (timeout * wdt_type->prescaler) / freq;
fabbfb9e 174
d5cfaf0a 175 mpc8xxx_wdt_dev.timeout = timeout_sec;
50ffb53e
UKK
176
177 watchdog_set_nowayout(&mpc8xxx_wdt_dev, nowayout);
178
179 ret = watchdog_register_device(&mpc8xxx_wdt_dev);
180 if (ret) {
181 pr_err("cannot register watchdog device (err=%d)\n", ret);
593fc178 182 goto err_unmap;
50ffb53e 183 }
593fc178 184
27c766aa
JP
185 pr_info("WDT driver for MPC8xxx initialized. mode:%s timeout=%d (%d seconds)\n",
186 reset ? "reset" : "interrupt", timeout, timeout_sec);
500c919e
AV
187
188 /*
189 * If the watchdog was previously enabled or we're running on
59ca1b0d 190 * MPC8xxx, we should ping the wdt from the kernel until the
500c919e
AV
191 * userspace handles it.
192 */
193 if (enabled)
d5cfaf0a 194 mod_timer(&wdt_timer, jiffies);
fabbfb9e 195 return 0;
fabbfb9e
KG
196err_unmap:
197 iounmap(wd_base);
fabbfb9e
KG
198 return ret;
199}
200
4b12b896 201static int mpc8xxx_wdt_remove(struct platform_device *ofdev)
fabbfb9e 202{
d5cfaf0a
CL
203 pr_crit("Watchdog removed, expect the %s soon!\n",
204 reset ? "reset" : "machine check exception");
500c919e 205 del_timer_sync(&wdt_timer);
d5cfaf0a 206 watchdog_unregister_device(&mpc8xxx_wdt_dev);
fabbfb9e
KG
207 iounmap(wd_base);
208
209 return 0;
210}
211
59ca1b0d 212static const struct of_device_id mpc8xxx_wdt_match[] = {
ef8ab12e
AV
213 {
214 .compatible = "mpc83xx_wdt",
59ca1b0d 215 .data = &(struct mpc8xxx_wdt_type) {
500c919e
AV
216 .prescaler = 0x10000,
217 },
218 },
219 {
220 .compatible = "fsl,mpc8610-wdt",
59ca1b0d 221 .data = &(struct mpc8xxx_wdt_type) {
500c919e
AV
222 .prescaler = 0x10000,
223 .hw_enabled = true,
224 },
ef8ab12e 225 },
0d7b1014
AV
226 {
227 .compatible = "fsl,mpc823-wdt",
228 .data = &(struct mpc8xxx_wdt_type) {
229 .prescaler = 0x800,
4af897fa 230 .hw_enabled = true,
0d7b1014
AV
231 },
232 },
ef8ab12e
AV
233 {},
234};
59ca1b0d 235MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
ef8ab12e 236
1c48a5c9 237static struct platform_driver mpc8xxx_wdt_driver = {
59ca1b0d 238 .probe = mpc8xxx_wdt_probe,
82268714 239 .remove = mpc8xxx_wdt_remove,
4018294b
GL
240 .driver = {
241 .name = "mpc8xxx_wdt",
4018294b 242 .of_match_table = mpc8xxx_wdt_match,
fabbfb9e
KG
243 },
244};
245
59ca1b0d 246static int __init mpc8xxx_wdt_init(void)
fabbfb9e 247{
1c48a5c9 248 return platform_driver_register(&mpc8xxx_wdt_driver);
fabbfb9e 249}
0d7b1014 250arch_initcall(mpc8xxx_wdt_init);
fabbfb9e 251
59ca1b0d 252static void __exit mpc8xxx_wdt_exit(void)
fabbfb9e 253{
1c48a5c9 254 platform_driver_unregister(&mpc8xxx_wdt_driver);
fabbfb9e 255}
59ca1b0d 256module_exit(mpc8xxx_wdt_exit);
fabbfb9e
KG
257
258MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
0d7b1014
AV
259MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
260 "uProcessors");
fabbfb9e 261MODULE_LICENSE("GPL");