[people/arne_f/kernel.git] / drivers / watchdog / octeon-wdt-main.c

/*
 * Octeon Watchdog driver
 *
 * Copyright (C) 2007-2017 Cavium, Inc.
 *
 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
 *
 * Some parts derived from wdt.c
 *
 *	(c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
 *						All Rights Reserved.
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
 *	warranty for any of this software. This material is provided
 *	"AS-IS" and at no charge.
 *
 *	(c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 *
 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
 * For most systems this is less than 10 seconds, so to allow for
 * software to request longer watchdog heartbeats, we maintain software
 * counters to count multiples of the base rate.  If the system locks
 * up in such a manner that we can not run the software counters, the
 * only result is a watchdog reset sooner than was requested.  But
 * that is OK, because in this case userspace would likely not be able
 * to do anything anyhow.
 *
 * The hardware watchdog interval we call the period.  The OCTEON
 * watchdog goes through several stages, after the first period an
 * irq is asserted, then if it is not reset, after the next period NMI
 * is asserted, then after an additional period a chip wide soft reset.
 * So for the software counters, we reset watchdog after each period
 * and decrement the counter.  But for the last two periods we need to
 * let the watchdog progress to the NMI stage so we disable the irq
 * and let it proceed.  Once in the NMI, we print the register state
 * to the serial port and then wait for the reset.
 *
 * A watchdog is maintained for each CPU in the system, that way if
 * one CPU suffers a lockup, we also get a register dump and reset.
 * The userspace ping resets the watchdog on all CPUs.
 *
 * Before userspace opens the watchdog device, we still run the
 * watchdogs to catch any lockups that may be kernel related.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/interrupt.h>
#include <linux/watchdog.h>
#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/cpu.h>
#include <linux/irq.h>

#include <asm/mipsregs.h>
#include <asm/uasm.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-boot-vector.h>
#include <asm/octeon/cvmx-ciu2-defs.h>
#include <asm/octeon/cvmx-rst-defs.h>

/* Watchdog interrupt major block number (8 MSBs of intsn) */
#define WD_BLOCK_NUMBER		0x01

static int divisor;

/* The count needed to achieve timeout_sec. */
static unsigned int timeout_cnt;

/* The maximum period supported. */
static unsigned int max_timeout_sec;

/* The current period.  */
static unsigned int timeout_sec;

/* Set to non-zero when userspace countdown mode active */
static bool do_countdown;
static unsigned int countdown_reset;
static unsigned int per_cpu_countdown[NR_CPUS];

static cpumask_t irq_enabled_cpus;

#define WD_TIMO 60			/* Default heartbeat = 60 seconds */

#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)

static int heartbeat = WD_TIMO;
module_param(heartbeat, int, 0444);
MODULE_PARM_DESC(heartbeat,
	"Watchdog heartbeat in seconds. (0 < heartbeat, default="
				__MODULE_STRING(WD_TIMO) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0444);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static int disable;
module_param(disable, int, 0444);
MODULE_PARM_DESC(disable,
	"Disable the watchdog entirely (default=0)");

static struct cvmx_boot_vector_element *octeon_wdt_bootvector;

void octeon_wdt_nmi_stage2(void);

static int cpu2core(int cpu)
{
#ifdef CONFIG_SMP
	return cpu_logical_map(cpu) & 0x3f;
#else
	return cvmx_get_core_num();
#endif
}

/**
 * Poke the watchdog when an interrupt is received
 *
 * @cpl:
 * @dev_id:
 *
 * Returns
 */
static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
{
	int cpu = raw_smp_processor_id();
	unsigned int core = cpu2core(cpu);
	int node = cpu_to_node(cpu);

	if (do_countdown) {
		if (per_cpu_countdown[cpu] > 0) {
			/* We're alive, poke the watchdog */
			cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
			per_cpu_countdown[cpu]--;
		} else {
			/* Bad news, you are about to reboot. */
			disable_irq_nosync(cpl);
			cpumask_clear_cpu(cpu, &irq_enabled_cpus);
		}
	} else {
		/* Not open, just ping away... */
		cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
	}
	return IRQ_HANDLED;
}

/* From setup.c */
extern int prom_putchar(char c);

/**
 * Write a string to the uart
 *
 * @str:        String to write
 */
static void octeon_wdt_write_string(const char *str)
{
	/* Just loop writing one byte at a time */
	while (*str)
		prom_putchar(*str++);
}

/**
 * Write a hex number out of the uart
 *
 * @value:      Number to display
 * @digits:     Number of digits to print (1 to 16)
 */
static void octeon_wdt_write_hex(u64 value, int digits)
{
	int d;
	int v;

	for (d = 0; d < digits; d++) {
		v = (value >> ((digits - d - 1) * 4)) & 0xf;
		if (v >= 10)
			prom_putchar('a' + v - 10);
		else
			prom_putchar('0' + v);
	}
}

static const char reg_name[][3] = {
	"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};

/**
 * NMI stage 3 handler. NMIs are handled in the following manner:
 * 1) The first NMI handler enables CVMSEG and transfers from
 * the bootbus region into normal memory. It is careful to not
 * destroy any registers.
 * 2) The second stage handler uses CVMSEG to save the registers
 * and create a stack for C code. It then calls the third level
 * handler with one argument, a pointer to the register values.
 * 3) The third, and final, level handler is the following C
 * function that prints out some useful infomration.
 *
 * @reg:    Pointer to register state before the NMI
 */
void octeon_wdt_nmi_stage3(u64 reg[32])
{
	u64 i;

	unsigned int coreid = cvmx_get_core_num();
	/*
	 * Save status and cause early to get them before any changes
	 * might happen.
	 */
	u64 cp0_cause = read_c0_cause();
	u64 cp0_status = read_c0_status();
	u64 cp0_error_epc = read_c0_errorepc();
	u64 cp0_epc = read_c0_epc();

	/* Delay so output from all cores output is not jumbled together. */
	udelay(85000 * coreid);

	octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
	octeon_wdt_write_hex(coreid, 2);
	octeon_wdt_write_string(" ***\r\n");
	for (i = 0; i < 32; i++) {
		octeon_wdt_write_string("\t");
		octeon_wdt_write_string(reg_name[i]);
		octeon_wdt_write_string("\t0x");
		octeon_wdt_write_hex(reg[i], 16);
		if (i & 1)
			octeon_wdt_write_string("\r\n");
	}
	octeon_wdt_write_string("\terr_epc\t0x");
	octeon_wdt_write_hex(cp0_error_epc, 16);

	octeon_wdt_write_string("\tepc\t0x");
	octeon_wdt_write_hex(cp0_epc, 16);
	octeon_wdt_write_string("\r\n");

	octeon_wdt_write_string("\tstatus\t0x");
	octeon_wdt_write_hex(cp0_status, 16);
	octeon_wdt_write_string("\tcause\t0x");
	octeon_wdt_write_hex(cp0_cause, 16);
	octeon_wdt_write_string("\r\n");

	/* The CIU register is different for each Octeon model. */
	if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
		octeon_wdt_write_string("\tsrc_wd\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
		octeon_wdt_write_string("\ten_wd\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
		octeon_wdt_write_string("\r\n");
		octeon_wdt_write_string("\tsrc_rml\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
		octeon_wdt_write_string("\ten_rml\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
		octeon_wdt_write_string("\r\n");
		octeon_wdt_write_string("\tsum\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
		octeon_wdt_write_string("\r\n");
	} else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
		octeon_wdt_write_string("\tsum0\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
		octeon_wdt_write_string("\ten0\t0x");
		octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
		octeon_wdt_write_string("\r\n");
	}

	octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");

	/*
	 * G-30204: We must trigger a soft reset before watchdog
	 * does an incomplete job of doing it.
	 */
	if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
		u64 scr;
		unsigned int node = cvmx_get_node_num();
		unsigned int lcore = cvmx_get_local_core_num();
		union cvmx_ciu_wdogx ciu_wdog;

		/*
		 * Wait for other cores to print out information, but
		 * not too long.  Do the soft reset before watchdog
		 * can trigger it.
		 */
		do {
			ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
		} while (ciu_wdog.s.cnt > 0x10000);

		scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
		scr |= 1 << 11; /* Indicate watchdog in bit 11 */
		cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
		cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
	}
}

static int octeon_wdt_cpu_to_irq(int cpu)
{
	unsigned int coreid;
	int node;
	int irq;

	coreid = cpu2core(cpu);
	node = cpu_to_node(cpu);

	if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
		struct irq_domain *domain;
		int hwirq;

		domain = octeon_irq_get_block_domain(node,
						     WD_BLOCK_NUMBER);
		hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
		irq = irq_find_mapping(domain, hwirq);
	} else {
		irq = OCTEON_IRQ_WDOG0 + coreid;
	}
	return irq;
}

static int octeon_wdt_cpu_pre_down(unsigned int cpu)
{
	unsigned int core;
	int node;
	union cvmx_ciu_wdogx ciu_wdog;

	core = cpu2core(cpu);

	node = cpu_to_node(cpu);

	/* Poke the watchdog to clear out its state */
	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);

	/* Disable the hardware. */
	ciu_wdog.u64 = 0;
	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);

	free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
	return 0;
}

static int octeon_wdt_cpu_online(unsigned int cpu)
{
	unsigned int core;
	unsigned int irq;
	union cvmx_ciu_wdogx ciu_wdog;
	int node;
	struct irq_domain *domain;
	int hwirq;

	core = cpu2core(cpu);
	node = cpu_to_node(cpu);

	octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;

	/* Disable it before doing anything with the interrupts. */
	ciu_wdog.u64 = 0;
	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);

	per_cpu_countdown[cpu] = countdown_reset;

	if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
		/* Must get the domain for the watchdog block */
		domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);

		/* Get a irq for the wd intsn (hardware interrupt) */
		hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
		irq = irq_create_mapping(domain, hwirq);
		irqd_set_trigger_type(irq_get_irq_data(irq),
				      IRQ_TYPE_EDGE_RISING);
	} else
		irq = OCTEON_IRQ_WDOG0 + core;

	if (request_irq(irq, octeon_wdt_poke_irq,
			IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
		panic("octeon_wdt: Couldn't obtain irq %d", irq);

	/* Must set the irq affinity here */
	if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
		cpumask_t mask;

		cpumask_clear(&mask);
		cpumask_set_cpu(cpu, &mask);
		irq_set_affinity(irq, &mask);
	}

	cpumask_set_cpu(cpu, &irq_enabled_cpus);

	/* Poke the watchdog to clear out its state */
	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);

	/* Finally enable the watchdog now that all handlers are installed */
	ciu_wdog.u64 = 0;
	ciu_wdog.s.len = timeout_cnt;
	ciu_wdog.s.mode = 3;	/* 3 = Interrupt + NMI + Soft-Reset */
	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);

	return 0;
}

static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
{
	int cpu;
	int coreid;
	int node;

	if (disable)
		return 0;

	for_each_online_cpu(cpu) {
		coreid = cpu2core(cpu);
		node = cpu_to_node(cpu);
		cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
		per_cpu_countdown[cpu] = countdown_reset;
		if ((countdown_reset || !do_countdown) &&
		    !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
			/* We have to enable the irq */
			enable_irq(octeon_wdt_cpu_to_irq(cpu));
			cpumask_set_cpu(cpu, &irq_enabled_cpus);
		}
	}
	return 0;
}

static void octeon_wdt_calc_parameters(int t)
{
	unsigned int periods;

	timeout_sec = max_timeout_sec;


	/*
	 * Find the largest interrupt period, that can evenly divide
	 * the requested heartbeat time.
	 */
	while ((t % timeout_sec) != 0)
		timeout_sec--;

	periods = t / timeout_sec;

	/*
	 * The last two periods are after the irq is disabled, and
	 * then to the nmi, so we subtract them off.
	 */

	countdown_reset = periods > 2 ? periods - 2 : 0;
	heartbeat = t;
	timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
}

static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
				  unsigned int t)
{
	int cpu;
	int coreid;
	union cvmx_ciu_wdogx ciu_wdog;
	int node;

	if (t <= 0)
		return -1;

	octeon_wdt_calc_parameters(t);

	if (disable)
		return 0;

	for_each_online_cpu(cpu) {
		coreid = cpu2core(cpu);
		node = cpu_to_node(cpu);
		cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
		ciu_wdog.u64 = 0;
		ciu_wdog.s.len = timeout_cnt;
		ciu_wdog.s.mode = 3;	/* 3 = Interrupt + NMI + Soft-Reset */
		cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
		cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
	}
	octeon_wdt_ping(wdog); /* Get the irqs back on. */
	return 0;
}

static int octeon_wdt_start(struct watchdog_device *wdog)
{
	octeon_wdt_ping(wdog);
	do_countdown = 1;
	return 0;
}

static int octeon_wdt_stop(struct watchdog_device *wdog)
{
	do_countdown = 0;
	octeon_wdt_ping(wdog);
	return 0;
}

static const struct watchdog_info octeon_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "OCTEON",
};

static const struct watchdog_ops octeon_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= octeon_wdt_start,
	.stop		= octeon_wdt_stop,
	.ping		= octeon_wdt_ping,
	.set_timeout	= octeon_wdt_set_timeout,
};

static struct watchdog_device octeon_wdt = {
	.info	= &octeon_wdt_info,
	.ops	= &octeon_wdt_ops,
};

static enum cpuhp_state octeon_wdt_online;
/**
 * Module/ driver initialization.
 *
 * Returns Zero on success
 */
static int __init octeon_wdt_init(void)
{
	int ret;

	octeon_wdt_bootvector = cvmx_boot_vector_get();
	if (!octeon_wdt_bootvector) {
		pr_err("Error: Cannot allocate boot vector.\n");
		return -ENOMEM;
	}

	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
		divisor = 0x200;
	else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
		divisor = 0x400;
	else
		divisor = 0x100;

	/*
	 * Watchdog time expiration length = The 16 bits of LEN
	 * represent the most significant bits of a 24 bit decrementer
	 * that decrements every divisor cycle.
	 *
	 * Try for a timeout of 5 sec, if that fails a smaller number
	 * of even seconds,
	 */
	max_timeout_sec = 6;
	do {
		max_timeout_sec--;
		timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
	} while (timeout_cnt > 65535);

	BUG_ON(timeout_cnt == 0);

	octeon_wdt_calc_parameters(heartbeat);

	pr_info("Initial granularity %d Sec\n", timeout_sec);

	octeon_wdt.timeout	= timeout_sec;
	octeon_wdt.max_timeout	= UINT_MAX;

	watchdog_set_nowayout(&octeon_wdt, nowayout);

	ret = watchdog_register_device(&octeon_wdt);
	if (ret) {
		pr_err("watchdog_register_device() failed: %d\n", ret);
		return ret;
	}

	if (disable) {
		pr_notice("disabled\n");
		return 0;
	}

	cpumask_clear(&irq_enabled_cpus);

	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
				octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
	if (ret < 0)
		goto err;
	octeon_wdt_online = ret;
	return 0;
err:
	cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
	watchdog_unregister_device(&octeon_wdt);
	return ret;
}

/**
 * Module / driver shutdown
 */
static void __exit octeon_wdt_cleanup(void)
{
	watchdog_unregister_device(&octeon_wdt);

	if (disable)
		return;

	cpuhp_remove_state(octeon_wdt_online);

	/*
	 * Disable the boot-bus memory, the code it points to is soon
	 * to go missing.
	 */
	cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
}

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
module_init(octeon_wdt_init);
module_exit(octeon_wdt_cleanup);
Commit	Line	Data
4c076fb4 DD	1	/*
	2	* Octeon Watchdog driver
	3	*
381cec02	4	* Copyright (C) 2007-2017 Cavium, Inc.
4c076fb4	5	*
3d588c93 AK	6	* Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
3d588c93 AK	7	*
4c076fb4 DD	8	* Some parts derived from wdt.c
	9	*
	10	* (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
	11	* All Rights Reserved.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License
	15	* as published by the Free Software Foundation; either version
	16	* 2 of the License, or (at your option) any later version.
	17	*
	18	* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
	19	* warranty for any of this software. This material is provided
	20	* "AS-IS" and at no charge.
	21	*
	22	* (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
	23	*
	24	* This file is subject to the terms and conditions of the GNU General Public
	25	* License. See the file "COPYING" in the main directory of this archive
	26	* for more details.
	27	*
	28	*
	29	* The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
	30	* For most systems this is less than 10 seconds, so to allow for
	31	* software to request longer watchdog heartbeats, we maintain software
	32	* counters to count multiples of the base rate. If the system locks
	33	* up in such a manner that we can not run the software counters, the
	34	* only result is a watchdog reset sooner than was requested. But
	35	* that is OK, because in this case userspace would likely not be able
	36	* to do anything anyhow.
	37	*
	38	* The hardware watchdog interval we call the period. The OCTEON
	39	* watchdog goes through several stages, after the first period an
	40	* irq is asserted, then if it is not reset, after the next period NMI
	41	* is asserted, then after an additional period a chip wide soft reset.
	42	* So for the software counters, we reset watchdog after each period
	43	* and decrement the counter. But for the last two periods we need to
	44	* let the watchdog progress to the NMI stage so we disable the irq
	45	* and let it proceed. Once in the NMI, we print the register state
	46	* to the serial port and then wait for the reset.
	47	*
	48	* A watchdog is maintained for each CPU in the system, that way if
	49	* one CPU suffers a lockup, we also get a register dump and reset.
	50	* The userspace ping resets the watchdog on all CPUs.
	51	*
	52	* Before userspace opens the watchdog device, we still run the
	53	* watchdogs to catch any lockups that may be kernel related.
	54	*
	55	*/
	56
27c766aa JP	57	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	58
4c076fb4 DD	59	#include <linux/interrupt.h>
	60	#include <linux/watchdog.h>
	61	#include <linux/cpumask.h>
4c076fb4	62	#include <linux/module.h>
4c076fb4 DD	63	#include <linux/delay.h>
4c076fb4 DD	64	#include <linux/cpu.h>
ca4d3e67	65	#include <linux/irq.h>
4c076fb4 DD	66
	67	#include <asm/mipsregs.h>
	68	#include <asm/uasm.h>
	69
	70	#include <asm/octeon/octeon.h>
49d148b4	71	#include <asm/octeon/cvmx-boot-vector.h>
0cd4e7a9	72	#include <asm/octeon/cvmx-ciu2-defs.h>
1d1821b2 CM	73	#include <asm/octeon/cvmx-rst-defs.h>
	74
	75	/* Watchdog interrupt major block number (8 MSBs of intsn) */
	76	#define WD_BLOCK_NUMBER 0x01
0cd4e7a9 DD	77
0cd4e7a9 DD	78	static int divisor;
4c076fb4 DD	79
	80	/* The count needed to achieve timeout_sec. */
	81	static unsigned int timeout_cnt;
	82
	83	/* The maximum period supported. */
	84	static unsigned int max_timeout_sec;
	85
	86	/* The current period. */
	87	static unsigned int timeout_sec;
	88
	89	/* Set to non-zero when userspace countdown mode active */
381cec02	90	static bool do_countdown;
4c076fb4 DD	91	static unsigned int countdown_reset;
	92	static unsigned int per_cpu_countdown[NR_CPUS];
	93
	94	static cpumask_t irq_enabled_cpus;
	95
	96	#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
	97
1d1821b2 CM	98	#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
1d1821b2 CM	99
4c076fb4	100	static int heartbeat = WD_TIMO;
381cec02	101	module_param(heartbeat, int, 0444);
4c076fb4 DD	102	MODULE_PARM_DESC(heartbeat,
	103	"Watchdog heartbeat in seconds. (0 < heartbeat, default="
	104	__MODULE_STRING(WD_TIMO) ")");
	105
86a1e189	106	static bool nowayout = WATCHDOG_NOWAYOUT;
381cec02	107	module_param(nowayout, bool, 0444);
4c076fb4 DD	108	MODULE_PARM_DESC(nowayout,
	109	"Watchdog cannot be stopped once started (default="
	110	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	111
381cec02 SH	112	static int disable;
	113	module_param(disable, int, 0444);
	114	MODULE_PARM_DESC(disable,
	115	"Disable the watchdog entirely (default=0)");
	116
49d148b4	117	static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
4c076fb4 DD	118
	119	void octeon_wdt_nmi_stage2(void);
	120
4c076fb4 DD	121	static int cpu2core(int cpu)
	122	{
	123	#ifdef CONFIG_SMP
1d1821b2	124	return cpu_logical_map(cpu) & 0x3f;
4c076fb4 DD	125	#else
	126	return cvmx_get_core_num();
	127	#endif
	128	}
	129
4c076fb4 DD	130	/**
	131	* Poke the watchdog when an interrupt is received
	132	*
	133	* @cpl:
	134	* @dev_id:
	135	*
	136	* Returns
	137	*/
	138	static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
	139	{
1d1821b2 CM	140	int cpu = raw_smp_processor_id();
	141	unsigned int core = cpu2core(cpu);
	142	int node = cpu_to_node(cpu);
4c076fb4	143
381cec02	144	if (do_countdown) {
4c076fb4 DD	145	if (per_cpu_countdown[cpu] > 0) {
4c076fb4 DD	146	/* We're alive, poke the watchdog */
1d1821b2	147	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
4c076fb4 DD	148	per_cpu_countdown[cpu]--;
	149	} else {
	150	/* Bad news, you are about to reboot. */
	151	disable_irq_nosync(cpl);
	152	cpumask_clear_cpu(cpu, &irq_enabled_cpus);
	153	}
	154	} else {
	155	/* Not open, just ping away... */
1d1821b2	156	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
4c076fb4 DD	157	}
	158	return IRQ_HANDLED;
	159	}
	160
	161	/* From setup.c */
	162	extern int prom_putchar(char c);
	163
	164	/**
	165	* Write a string to the uart
	166	*
	167	* @str: String to write
	168	*/
	169	static void octeon_wdt_write_string(const char *str)
	170	{
	171	/* Just loop writing one byte at a time */
	172	while (*str)
	173	prom_putchar(*str++);
	174	}
	175
	176	/**
	177	* Write a hex number out of the uart
	178	*
	179	* @value: Number to display
	180	* @digits: Number of digits to print (1 to 16)
	181	*/
	182	static void octeon_wdt_write_hex(u64 value, int digits)
	183	{
	184	int d;
	185	int v;
8692cf0a	186
4c076fb4 DD	187	for (d = 0; d < digits; d++) {
	188	v = (value >> ((digits - d - 1) * 4)) & 0xf;
	189	if (v >= 10)
	190	prom_putchar('a' + v - 10);
	191	else
	192	prom_putchar('0' + v);
	193	}
	194	}
	195
3a30c07e	196	static const char reg_name[][3] = {
4c076fb4 DD	197	"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
	198	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
	199	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
	200	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
	201	};
	202
	203	/**
	204	* NMI stage 3 handler. NMIs are handled in the following manner:
	205	* 1) The first NMI handler enables CVMSEG and transfers from
	206	* the bootbus region into normal memory. It is careful to not
	207	* destroy any registers.
	208	* 2) The second stage handler uses CVMSEG to save the registers
	209	* and create a stack for C code. It then calls the third level
	210	* handler with one argument, a pointer to the register values.
	211	* 3) The third, and final, level handler is the following C
	212	* function that prints out some useful infomration.
	213	*
	214	* @reg: Pointer to register state before the NMI
	215	*/
	216	void octeon_wdt_nmi_stage3(u64 reg[32])
	217	{
	218	u64 i;
	219
	220	unsigned int coreid = cvmx_get_core_num();
	221	/*
	222	* Save status and cause early to get them before any changes
	223	* might happen.
	224	*/
	225	u64 cp0_cause = read_c0_cause();
	226	u64 cp0_status = read_c0_status();
	227	u64 cp0_error_epc = read_c0_errorepc();
	228	u64 cp0_epc = read_c0_epc();
	229
	230	/* Delay so output from all cores output is not jumbled together. */
0cd4e7a9	231	udelay(85000 * coreid);
4c076fb4 DD	232
4c076fb4 DD	233	octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
0cd4e7a9	234	octeon_wdt_write_hex(coreid, 2);
4c076fb4 DD	235	octeon_wdt_write_string(" ***\r\n");
	236	for (i = 0; i < 32; i++) {
	237	octeon_wdt_write_string("\t");
	238	octeon_wdt_write_string(reg_name[i]);
	239	octeon_wdt_write_string("\t0x");
	240	octeon_wdt_write_hex(reg[i], 16);
	241	if (i & 1)
	242	octeon_wdt_write_string("\r\n");
	243	}
	244	octeon_wdt_write_string("\terr_epc\t0x");
	245	octeon_wdt_write_hex(cp0_error_epc, 16);
	246
	247	octeon_wdt_write_string("\tepc\t0x");
	248	octeon_wdt_write_hex(cp0_epc, 16);
	249	octeon_wdt_write_string("\r\n");
	250
	251	octeon_wdt_write_string("\tstatus\t0x");
	252	octeon_wdt_write_hex(cp0_status, 16);
	253	octeon_wdt_write_string("\tcause\t0x");
	254	octeon_wdt_write_hex(cp0_cause, 16);
	255	octeon_wdt_write_string("\r\n");
	256
0cd4e7a9 DD	257	/* The CIU register is different for each Octeon model. */
	258	if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
	259	octeon_wdt_write_string("\tsrc_wd\t0x");
	260	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
	261	octeon_wdt_write_string("\ten_wd\t0x");
	262	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
	263	octeon_wdt_write_string("\r\n");
	264	octeon_wdt_write_string("\tsrc_rml\t0x");
	265	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
	266	octeon_wdt_write_string("\ten_rml\t0x");
	267	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
	268	octeon_wdt_write_string("\r\n");
	269	octeon_wdt_write_string("\tsum\t0x");
	270	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
	271	octeon_wdt_write_string("\r\n");
	272	} else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
	273	octeon_wdt_write_string("\tsum0\t0x");
	274	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
	275	octeon_wdt_write_string("\ten0\t0x");
	276	octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
	277	octeon_wdt_write_string("\r\n");
	278	}
4c076fb4 DD	279
4c076fb4 DD	280	octeon_wdt_write_string("* Chip soft reset soon *\r\n");
1d1821b2 CM	281
	282	/*
	283	* G-30204: We must trigger a soft reset before watchdog
	284	* does an incomplete job of doing it.
	285	*/
	286	if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
	287	u64 scr;
	288	unsigned int node = cvmx_get_node_num();
	289	unsigned int lcore = cvmx_get_local_core_num();
	290	union cvmx_ciu_wdogx ciu_wdog;
	291
	292	/*
	293	* Wait for other cores to print out information, but
	294	* not too long. Do the soft reset before watchdog
	295	* can trigger it.
	296	*/
	297	do {
	298	ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
	299	} while (ciu_wdog.s.cnt > 0x10000);
	300
	301	scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
	302	scr \|= 1 << 11; /* Indicate watchdog in bit 11 */
	303	cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
	304	cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
	305	}
	306	}
	307
	308	static int octeon_wdt_cpu_to_irq(int cpu)
	309	{
	310	unsigned int coreid;
	311	int node;
	312	int irq;
	313
	314	coreid = cpu2core(cpu);
	315	node = cpu_to_node(cpu);
	316
	317	if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
	318	struct irq_domain *domain;
	319	int hwirq;
	320
	321	domain = octeon_irq_get_block_domain(node,
	322	WD_BLOCK_NUMBER);
	323	hwirq = WD_BLOCK_NUMBER << 12 \| 0x200 \| coreid;
	324	irq = irq_find_mapping(domain, hwirq);
	325	} else {
	326	irq = OCTEON_IRQ_WDOG0 + coreid;
	327	}
	328	return irq;
4c076fb4 DD	329	}
4c076fb4 DD	330
948b9c60	331	static int octeon_wdt_cpu_pre_down(unsigned int cpu)
4c076fb4 DD	332	{
4c076fb4 DD	333	unsigned int core;
1d1821b2	334	int node;
4c076fb4 DD	335	union cvmx_ciu_wdogx ciu_wdog;
	336
	337	core = cpu2core(cpu);
	338
1d1821b2	339	node = cpu_to_node(cpu);
4c076fb4 DD	340
4c076fb4 DD	341	/* Poke the watchdog to clear out its state */
1d1821b2	342	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
4c076fb4 DD	343
	344	/* Disable the hardware. */
	345	ciu_wdog.u64 = 0;
1d1821b2	346	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
4c076fb4	347
1d1821b2	348	free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
948b9c60	349	return 0;
4c076fb4 DD	350	}
4c076fb4 DD	351
948b9c60	352	static int octeon_wdt_cpu_online(unsigned int cpu)
4c076fb4 DD	353	{
	354	unsigned int core;
	355	unsigned int irq;
	356	union cvmx_ciu_wdogx ciu_wdog;
1d1821b2 CM	357	int node;
	358	struct irq_domain *domain;
	359	int hwirq;
4c076fb4 DD	360
4c076fb4 DD	361	core = cpu2core(cpu);
1d1821b2	362	node = cpu_to_node(cpu);
4c076fb4	363
49d148b4 SH	364	octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
49d148b4 SH	365
4c076fb4 DD	366	/* Disable it before doing anything with the interrupts. */
4c076fb4 DD	367	ciu_wdog.u64 = 0;
1d1821b2	368	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
4c076fb4 DD	369
	370	per_cpu_countdown[cpu] = countdown_reset;
	371
1d1821b2 CM	372	if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
	373	/* Must get the domain for the watchdog block */
	374	domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
	375
	376	/* Get a irq for the wd intsn (hardware interrupt) */
	377	hwirq = WD_BLOCK_NUMBER << 12 \| 0x200 \| core;
	378	irq = irq_create_mapping(domain, hwirq);
	379	irqd_set_trigger_type(irq_get_irq_data(irq),
	380	IRQ_TYPE_EDGE_RISING);
	381	} else
	382	irq = OCTEON_IRQ_WDOG0 + core;
4c076fb4 DD	383
4c076fb4 DD	384	if (request_irq(irq, octeon_wdt_poke_irq,
47bfd058	385	IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
4c076fb4 DD	386	panic("octeon_wdt: Couldn't obtain irq %d", irq);
4c076fb4 DD	387
1d1821b2 CM	388	/* Must set the irq affinity here */
	389	if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
	390	cpumask_t mask;
	391
	392	cpumask_clear(&mask);
	393	cpumask_set_cpu(cpu, &mask);
	394	irq_set_affinity(irq, &mask);
	395	}
	396
4c076fb4 DD	397	cpumask_set_cpu(cpu, &irq_enabled_cpus);
	398
	399	/* Poke the watchdog to clear out its state */
1d1821b2	400	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
4c076fb4 DD	401
	402	/* Finally enable the watchdog now that all handlers are installed */
	403	ciu_wdog.u64 = 0;
	404	ciu_wdog.s.len = timeout_cnt;
	405	ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
1d1821b2	406	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
4c076fb4	407
948b9c60	408	return 0;
4c076fb4 DD	409	}
4c076fb4 DD	410
3d588c93	411	static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
4c076fb4 DD	412	{
	413	int cpu;
	414	int coreid;
1d1821b2	415	int node;
4c076fb4	416
381cec02 SH	417	if (disable)
	418	return 0;
	419
4c076fb4 DD	420	for_each_online_cpu(cpu) {
4c076fb4 DD	421	coreid = cpu2core(cpu);
1d1821b2 CM	422	node = cpu_to_node(cpu);
1d1821b2 CM	423	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
4c076fb4	424	per_cpu_countdown[cpu] = countdown_reset;
381cec02	425	if ((countdown_reset \|\| !do_countdown) &&
4c076fb4 DD	426	!cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
4c076fb4 DD	427	/* We have to enable the irq */
1d1821b2	428	enable_irq(octeon_wdt_cpu_to_irq(cpu));
4c076fb4 DD	429	cpumask_set_cpu(cpu, &irq_enabled_cpus);
	430	}
	431	}
3d588c93	432	return 0;
4c076fb4 DD	433	}
	434
	435	static void octeon_wdt_calc_parameters(int t)
	436	{
	437	unsigned int periods;
	438
	439	timeout_sec = max_timeout_sec;
	440
	441
	442	/*
	443	* Find the largest interrupt period, that can evenly divide
	444	* the requested heartbeat time.
	445	*/
	446	while ((t % timeout_sec) != 0)
	447	timeout_sec--;
	448
	449	periods = t / timeout_sec;
	450
	451	/*
	452	* The last two periods are after the irq is disabled, and
	453	* then to the nmi, so we subtract them off.
	454	*/
	455
	456	countdown_reset = periods > 2 ? periods - 2 : 0;
	457	heartbeat = t;
0cd4e7a9	458	timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
4c076fb4 DD	459	}
4c076fb4 DD	460
3d588c93 AK	461	static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
3d588c93 AK	462	unsigned int t)
4c076fb4 DD	463	{
	464	int cpu;
	465	int coreid;
	466	union cvmx_ciu_wdogx ciu_wdog;
1d1821b2	467	int node;
4c076fb4 DD	468
	469	if (t <= 0)
	470	return -1;
	471
	472	octeon_wdt_calc_parameters(t);
	473
381cec02 SH	474	if (disable)
	475	return 0;
	476
4c076fb4 DD	477	for_each_online_cpu(cpu) {
4c076fb4 DD	478	coreid = cpu2core(cpu);
1d1821b2 CM	479	node = cpu_to_node(cpu);
1d1821b2 CM	480	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
4c076fb4 DD	481	ciu_wdog.u64 = 0;
	482	ciu_wdog.s.len = timeout_cnt;
	483	ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
1d1821b2 CM	484	cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
1d1821b2 CM	485	cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
4c076fb4	486	}
3d588c93	487	octeon_wdt_ping(wdog); /* Get the irqs back on. */
4c076fb4 DD	488	return 0;
	489	}
	490
3d588c93	491	static int octeon_wdt_start(struct watchdog_device *wdog)
4c076fb4	492	{
3d588c93	493	octeon_wdt_ping(wdog);
381cec02	494	do_countdown = 1;
3d588c93	495	return 0;
4c076fb4 DD	496	}
4c076fb4 DD	497
3d588c93	498	static int octeon_wdt_stop(struct watchdog_device *wdog)
4c076fb4	499	{
381cec02	500	do_countdown = 0;
3d588c93	501	octeon_wdt_ping(wdog);
4c076fb4 DD	502	return 0;
	503	}
	504
3d588c93 AK	505	static const struct watchdog_info octeon_wdt_info = {
	506	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
	507	.identity = "OCTEON",
4c076fb4 DD	508	};
4c076fb4 DD	509
3d588c93 AK	510	static const struct watchdog_ops octeon_wdt_ops = {
	511	.owner = THIS_MODULE,
	512	.start = octeon_wdt_start,
	513	.stop = octeon_wdt_stop,
	514	.ping = octeon_wdt_ping,
	515	.set_timeout = octeon_wdt_set_timeout,
4c076fb4 DD	516	};
4c076fb4 DD	517
3d588c93 AK	518	static struct watchdog_device octeon_wdt = {
	519	.info = &octeon_wdt_info,
	520	.ops = &octeon_wdt_ops,
	521	};
4c076fb4	522
948b9c60	523	static enum cpuhp_state octeon_wdt_online;
4c076fb4 DD	524	/**
	525	* Module/ driver initialization.
	526	*
	527	* Returns Zero on success
	528	*/
	529	static int __init octeon_wdt_init(void)
	530	{
4c076fb4	531	int ret;
4c076fb4	532
49d148b4 SH	533	octeon_wdt_bootvector = cvmx_boot_vector_get();
	534	if (!octeon_wdt_bootvector) {
	535	pr_err("Error: Cannot allocate boot vector.\n");
	536	return -ENOMEM;
	537	}
	538
0cd4e7a9 DD	539	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
0cd4e7a9 DD	540	divisor = 0x200;
1d1821b2 CM	541	else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1d1821b2 CM	542	divisor = 0x400;
0cd4e7a9 DD	543	else
	544	divisor = 0x100;
	545
4c076fb4 DD	546	/*
	547	* Watchdog time expiration length = The 16 bits of LEN
	548	* represent the most significant bits of a 24 bit decrementer
0cd4e7a9	549	* that decrements every divisor cycle.
4c076fb4 DD	550	*
	551	* Try for a timeout of 5 sec, if that fails a smaller number
	552	* of even seconds,
	553	*/
	554	max_timeout_sec = 6;
	555	do {
	556	max_timeout_sec--;
0cd4e7a9	557	timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
4c076fb4 DD	558	} while (timeout_cnt > 65535);
	559
	560	BUG_ON(timeout_cnt == 0);
	561
	562	octeon_wdt_calc_parameters(heartbeat);
	563
27c766aa	564	pr_info("Initial granularity %d Sec\n", timeout_sec);
4c076fb4	565
3d588c93 AK	566	octeon_wdt.timeout = timeout_sec;
	567	octeon_wdt.max_timeout = UINT_MAX;
	568
	569	watchdog_set_nowayout(&octeon_wdt, nowayout);
	570
	571	ret = watchdog_register_device(&octeon_wdt);
4c076fb4	572	if (ret) {
3d588c93 AK	573	pr_err("watchdog_register_device() failed: %d\n", ret);
3d588c93 AK	574	return ret;
4c076fb4 DD	575	}
4c076fb4 DD	576
381cec02 SH	577	if (disable) {
	578	pr_notice("disabled\n");
	579	return 0;
	580	}
	581
4c076fb4 DD	582	cpumask_clear(&irq_enabled_cpus);
4c076fb4 DD	583
948b9c60 SAS	584	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
	585	octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
	586	if (ret < 0)
	587	goto err;
	588	octeon_wdt_online = ret;
3d588c93	589	return 0;
948b9c60 SAS	590	err:
	591	cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
	592	watchdog_unregister_device(&octeon_wdt);
	593	return ret;
4c076fb4 DD	594	}
	595
	596	/**
	597	* Module / driver shutdown
	598	*/
	599	static void __exit octeon_wdt_cleanup(void)
	600	{
3d588c93	601	watchdog_unregister_device(&octeon_wdt);
381cec02 SH	602
	603	if (disable)
	604	return;
	605
948b9c60	606	cpuhp_remove_state(octeon_wdt_online);
99c3bf36	607
4c076fb4 DD	608	/*
	609	* Disable the boot-bus memory, the code it points to is soon
	610	* to go missing.
	611	*/
	612	cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
	613	}
	614
	615	MODULE_LICENSE("GPL");
381cec02 SH	616	MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
381cec02 SH	617	MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
4c076fb4 DD	618	module_init(octeon_wdt_init);
4c076fb4 DD	619	module_exit(octeon_wdt_cleanup);