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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
67b915a5 | 20 | #include "config.h" |
d5a8f07c | 21 | #ifdef _WIN32 |
4fddf62a | 22 | #define WIN32_LEAN_AND_MEAN |
d5a8f07c FB |
23 | #include <windows.h> |
24 | #else | |
a98d49b1 | 25 | #include <sys/types.h> |
d5a8f07c FB |
26 | #include <sys/mman.h> |
27 | #endif | |
54936004 FB |
28 | #include <stdlib.h> |
29 | #include <stdio.h> | |
30 | #include <stdarg.h> | |
31 | #include <string.h> | |
32 | #include <errno.h> | |
33 | #include <unistd.h> | |
34 | #include <inttypes.h> | |
35 | ||
6180a181 FB |
36 | #include "cpu.h" |
37 | #include "exec-all.h" | |
ca10f867 | 38 | #include "qemu-common.h" |
53a5960a PB |
39 | #if defined(CONFIG_USER_ONLY) |
40 | #include <qemu.h> | |
41 | #endif | |
54936004 | 42 | |
fd6ce8f6 | 43 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 44 | //#define DEBUG_FLUSH |
9fa3e853 | 45 | //#define DEBUG_TLB |
67d3b957 | 46 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
47 | |
48 | /* make various TB consistency checks */ | |
5fafdf24 TS |
49 | //#define DEBUG_TB_CHECK |
50 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 51 | |
1196be37 | 52 | //#define DEBUG_IOPORT |
db7b5426 | 53 | //#define DEBUG_SUBPAGE |
1196be37 | 54 | |
99773bd4 PB |
55 | #if !defined(CONFIG_USER_ONLY) |
56 | /* TB consistency checks only implemented for usermode emulation. */ | |
57 | #undef DEBUG_TB_CHECK | |
58 | #endif | |
59 | ||
fd6ce8f6 | 60 | /* threshold to flush the translated code buffer */ |
d07bde88 | 61 | #define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - code_gen_max_block_size()) |
fd6ce8f6 | 62 | |
9fa3e853 FB |
63 | #define SMC_BITMAP_USE_THRESHOLD 10 |
64 | ||
65 | #define MMAP_AREA_START 0x00000000 | |
66 | #define MMAP_AREA_END 0xa8000000 | |
fd6ce8f6 | 67 | |
108c49b8 FB |
68 | #if defined(TARGET_SPARC64) |
69 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 | |
5dcb6b91 BS |
70 | #elif defined(TARGET_SPARC) |
71 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
bedb69ea JM |
72 | #elif defined(TARGET_ALPHA) |
73 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
74 | #define TARGET_VIRT_ADDR_SPACE_BITS 42 | |
108c49b8 FB |
75 | #elif defined(TARGET_PPC64) |
76 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
00f82b8a AJ |
77 | #elif defined(TARGET_X86_64) && !defined(USE_KQEMU) |
78 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
79 | #elif defined(TARGET_I386) && !defined(USE_KQEMU) | |
80 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
108c49b8 FB |
81 | #else |
82 | /* Note: for compatibility with kqemu, we use 32 bits for x86_64 */ | |
83 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
84 | #endif | |
85 | ||
fd6ce8f6 | 86 | TranslationBlock tbs[CODE_GEN_MAX_BLOCKS]; |
9fa3e853 | 87 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
fd6ce8f6 | 88 | int nb_tbs; |
eb51d102 FB |
89 | /* any access to the tbs or the page table must use this lock */ |
90 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; | |
fd6ce8f6 | 91 | |
7cb69cae | 92 | uint8_t code_gen_prologue[1024] __attribute__((aligned (32))); |
b8076a74 | 93 | uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32))); |
fd6ce8f6 FB |
94 | uint8_t *code_gen_ptr; |
95 | ||
00f82b8a | 96 | ram_addr_t phys_ram_size; |
9fa3e853 FB |
97 | int phys_ram_fd; |
98 | uint8_t *phys_ram_base; | |
1ccde1cb | 99 | uint8_t *phys_ram_dirty; |
e9a1ab19 | 100 | static ram_addr_t phys_ram_alloc_offset = 0; |
9fa3e853 | 101 | |
6a00d601 FB |
102 | CPUState *first_cpu; |
103 | /* current CPU in the current thread. It is only valid inside | |
104 | cpu_exec() */ | |
5fafdf24 | 105 | CPUState *cpu_single_env; |
6a00d601 | 106 | |
54936004 | 107 | typedef struct PageDesc { |
92e873b9 | 108 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 109 | TranslationBlock *first_tb; |
9fa3e853 FB |
110 | /* in order to optimize self modifying code, we count the number |
111 | of lookups we do to a given page to use a bitmap */ | |
112 | unsigned int code_write_count; | |
113 | uint8_t *code_bitmap; | |
114 | #if defined(CONFIG_USER_ONLY) | |
115 | unsigned long flags; | |
116 | #endif | |
54936004 FB |
117 | } PageDesc; |
118 | ||
92e873b9 FB |
119 | typedef struct PhysPageDesc { |
120 | /* offset in host memory of the page + io_index in the low 12 bits */ | |
00f82b8a | 121 | ram_addr_t phys_offset; |
92e873b9 FB |
122 | } PhysPageDesc; |
123 | ||
54936004 | 124 | #define L2_BITS 10 |
bedb69ea JM |
125 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS) |
126 | /* XXX: this is a temporary hack for alpha target. | |
127 | * In the future, this is to be replaced by a multi-level table | |
128 | * to actually be able to handle the complete 64 bits address space. | |
129 | */ | |
130 | #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS) | |
131 | #else | |
03875444 | 132 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
bedb69ea | 133 | #endif |
54936004 FB |
134 | |
135 | #define L1_SIZE (1 << L1_BITS) | |
136 | #define L2_SIZE (1 << L2_BITS) | |
137 | ||
33417e70 | 138 | static void io_mem_init(void); |
fd6ce8f6 | 139 | |
83fb7adf FB |
140 | unsigned long qemu_real_host_page_size; |
141 | unsigned long qemu_host_page_bits; | |
142 | unsigned long qemu_host_page_size; | |
143 | unsigned long qemu_host_page_mask; | |
54936004 | 144 | |
92e873b9 | 145 | /* XXX: for system emulation, it could just be an array */ |
54936004 | 146 | static PageDesc *l1_map[L1_SIZE]; |
0a962c02 | 147 | PhysPageDesc **l1_phys_map; |
54936004 | 148 | |
33417e70 | 149 | /* io memory support */ |
33417e70 FB |
150 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
151 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 152 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
33417e70 | 153 | static int io_mem_nb; |
6658ffb8 PB |
154 | #if defined(CONFIG_SOFTMMU) |
155 | static int io_mem_watch; | |
156 | #endif | |
33417e70 | 157 | |
34865134 FB |
158 | /* log support */ |
159 | char *logfilename = "/tmp/qemu.log"; | |
160 | FILE *logfile; | |
161 | int loglevel; | |
e735b91c | 162 | static int log_append = 0; |
34865134 | 163 | |
e3db7226 FB |
164 | /* statistics */ |
165 | static int tlb_flush_count; | |
166 | static int tb_flush_count; | |
167 | static int tb_phys_invalidate_count; | |
168 | ||
db7b5426 BS |
169 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
170 | typedef struct subpage_t { | |
171 | target_phys_addr_t base; | |
3ee89922 BS |
172 | CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4]; |
173 | CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4]; | |
174 | void *opaque[TARGET_PAGE_SIZE][2][4]; | |
db7b5426 BS |
175 | } subpage_t; |
176 | ||
7cb69cae FB |
177 | #ifdef _WIN32 |
178 | static void map_exec(void *addr, long size) | |
179 | { | |
180 | DWORD old_protect; | |
181 | VirtualProtect(addr, size, | |
182 | PAGE_EXECUTE_READWRITE, &old_protect); | |
183 | ||
184 | } | |
185 | #else | |
186 | static void map_exec(void *addr, long size) | |
187 | { | |
188 | unsigned long start, end; | |
189 | ||
190 | start = (unsigned long)addr; | |
191 | start &= ~(qemu_real_host_page_size - 1); | |
192 | ||
193 | end = (unsigned long)addr + size; | |
194 | end += qemu_real_host_page_size - 1; | |
195 | end &= ~(qemu_real_host_page_size - 1); | |
196 | ||
197 | mprotect((void *)start, end - start, | |
198 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
199 | } | |
200 | #endif | |
201 | ||
b346ff46 | 202 | static void page_init(void) |
54936004 | 203 | { |
83fb7adf | 204 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 205 | TARGET_PAGE_SIZE */ |
67b915a5 | 206 | #ifdef _WIN32 |
d5a8f07c FB |
207 | { |
208 | SYSTEM_INFO system_info; | |
209 | DWORD old_protect; | |
3b46e624 | 210 | |
d5a8f07c FB |
211 | GetSystemInfo(&system_info); |
212 | qemu_real_host_page_size = system_info.dwPageSize; | |
d5a8f07c | 213 | } |
67b915a5 | 214 | #else |
83fb7adf | 215 | qemu_real_host_page_size = getpagesize(); |
67b915a5 | 216 | #endif |
7cb69cae FB |
217 | map_exec(code_gen_buffer, sizeof(code_gen_buffer)); |
218 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); | |
d5a8f07c | 219 | |
83fb7adf FB |
220 | if (qemu_host_page_size == 0) |
221 | qemu_host_page_size = qemu_real_host_page_size; | |
222 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
223 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
224 | qemu_host_page_bits = 0; | |
225 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
226 | qemu_host_page_bits++; | |
227 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
108c49b8 FB |
228 | l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *)); |
229 | memset(l1_phys_map, 0, L1_SIZE * sizeof(void *)); | |
50a9569b AZ |
230 | |
231 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) | |
232 | { | |
233 | long long startaddr, endaddr; | |
234 | FILE *f; | |
235 | int n; | |
236 | ||
237 | f = fopen("/proc/self/maps", "r"); | |
238 | if (f) { | |
239 | do { | |
240 | n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr); | |
241 | if (n == 2) { | |
e0b8d65a BS |
242 | startaddr = MIN(startaddr, |
243 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
244 | endaddr = MIN(endaddr, | |
245 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
50a9569b AZ |
246 | page_set_flags(TARGET_PAGE_ALIGN(startaddr), |
247 | TARGET_PAGE_ALIGN(endaddr), | |
248 | PAGE_RESERVED); | |
249 | } | |
250 | } while (!feof(f)); | |
251 | fclose(f); | |
252 | } | |
253 | } | |
254 | #endif | |
54936004 FB |
255 | } |
256 | ||
00f82b8a | 257 | static inline PageDesc *page_find_alloc(target_ulong index) |
54936004 | 258 | { |
54936004 FB |
259 | PageDesc **lp, *p; |
260 | ||
54936004 FB |
261 | lp = &l1_map[index >> L2_BITS]; |
262 | p = *lp; | |
263 | if (!p) { | |
264 | /* allocate if not found */ | |
59817ccb | 265 | p = qemu_malloc(sizeof(PageDesc) * L2_SIZE); |
fd6ce8f6 | 266 | memset(p, 0, sizeof(PageDesc) * L2_SIZE); |
54936004 FB |
267 | *lp = p; |
268 | } | |
269 | return p + (index & (L2_SIZE - 1)); | |
270 | } | |
271 | ||
00f82b8a | 272 | static inline PageDesc *page_find(target_ulong index) |
54936004 | 273 | { |
54936004 FB |
274 | PageDesc *p; |
275 | ||
54936004 FB |
276 | p = l1_map[index >> L2_BITS]; |
277 | if (!p) | |
278 | return 0; | |
fd6ce8f6 FB |
279 | return p + (index & (L2_SIZE - 1)); |
280 | } | |
281 | ||
108c49b8 | 282 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 283 | { |
108c49b8 | 284 | void **lp, **p; |
e3f4e2a4 | 285 | PhysPageDesc *pd; |
92e873b9 | 286 | |
108c49b8 FB |
287 | p = (void **)l1_phys_map; |
288 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 | |
289 | ||
290 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) | |
291 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS | |
292 | #endif | |
293 | lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1)); | |
92e873b9 FB |
294 | p = *lp; |
295 | if (!p) { | |
296 | /* allocate if not found */ | |
108c49b8 FB |
297 | if (!alloc) |
298 | return NULL; | |
299 | p = qemu_vmalloc(sizeof(void *) * L1_SIZE); | |
300 | memset(p, 0, sizeof(void *) * L1_SIZE); | |
301 | *lp = p; | |
302 | } | |
303 | #endif | |
304 | lp = p + ((index >> L2_BITS) & (L1_SIZE - 1)); | |
e3f4e2a4 PB |
305 | pd = *lp; |
306 | if (!pd) { | |
307 | int i; | |
108c49b8 FB |
308 | /* allocate if not found */ |
309 | if (!alloc) | |
310 | return NULL; | |
e3f4e2a4 PB |
311 | pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE); |
312 | *lp = pd; | |
313 | for (i = 0; i < L2_SIZE; i++) | |
314 | pd[i].phys_offset = IO_MEM_UNASSIGNED; | |
92e873b9 | 315 | } |
e3f4e2a4 | 316 | return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); |
92e873b9 FB |
317 | } |
318 | ||
108c49b8 | 319 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 320 | { |
108c49b8 | 321 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
322 | } |
323 | ||
9fa3e853 | 324 | #if !defined(CONFIG_USER_ONLY) |
6a00d601 | 325 | static void tlb_protect_code(ram_addr_t ram_addr); |
5fafdf24 | 326 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 327 | target_ulong vaddr); |
9fa3e853 | 328 | #endif |
fd6ce8f6 | 329 | |
6a00d601 | 330 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 331 | { |
6a00d601 FB |
332 | CPUState **penv; |
333 | int cpu_index; | |
334 | ||
fd6ce8f6 | 335 | if (!code_gen_ptr) { |
57fec1fe | 336 | cpu_gen_init(); |
fd6ce8f6 | 337 | code_gen_ptr = code_gen_buffer; |
b346ff46 | 338 | page_init(); |
33417e70 | 339 | io_mem_init(); |
fd6ce8f6 | 340 | } |
6a00d601 FB |
341 | env->next_cpu = NULL; |
342 | penv = &first_cpu; | |
343 | cpu_index = 0; | |
344 | while (*penv != NULL) { | |
345 | penv = (CPUState **)&(*penv)->next_cpu; | |
346 | cpu_index++; | |
347 | } | |
348 | env->cpu_index = cpu_index; | |
6658ffb8 | 349 | env->nb_watchpoints = 0; |
6a00d601 | 350 | *penv = env; |
fd6ce8f6 FB |
351 | } |
352 | ||
9fa3e853 FB |
353 | static inline void invalidate_page_bitmap(PageDesc *p) |
354 | { | |
355 | if (p->code_bitmap) { | |
59817ccb | 356 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
357 | p->code_bitmap = NULL; |
358 | } | |
359 | p->code_write_count = 0; | |
360 | } | |
361 | ||
fd6ce8f6 FB |
362 | /* set to NULL all the 'first_tb' fields in all PageDescs */ |
363 | static void page_flush_tb(void) | |
364 | { | |
365 | int i, j; | |
366 | PageDesc *p; | |
367 | ||
368 | for(i = 0; i < L1_SIZE; i++) { | |
369 | p = l1_map[i]; | |
370 | if (p) { | |
9fa3e853 FB |
371 | for(j = 0; j < L2_SIZE; j++) { |
372 | p->first_tb = NULL; | |
373 | invalidate_page_bitmap(p); | |
374 | p++; | |
375 | } | |
fd6ce8f6 FB |
376 | } |
377 | } | |
378 | } | |
379 | ||
380 | /* flush all the translation blocks */ | |
d4e8164f | 381 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 382 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 383 | { |
6a00d601 | 384 | CPUState *env; |
0124311e | 385 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
386 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
387 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
388 | nb_tbs, nb_tbs > 0 ? | |
389 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 390 | #endif |
a208e54a PB |
391 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > CODE_GEN_BUFFER_SIZE) |
392 | cpu_abort(env1, "Internal error: code buffer overflow\n"); | |
393 | ||
fd6ce8f6 | 394 | nb_tbs = 0; |
3b46e624 | 395 | |
6a00d601 FB |
396 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
397 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
398 | } | |
9fa3e853 | 399 | |
8a8a608f | 400 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 401 | page_flush_tb(); |
9fa3e853 | 402 | |
fd6ce8f6 | 403 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
404 | /* XXX: flush processor icache at this point if cache flush is |
405 | expensive */ | |
e3db7226 | 406 | tb_flush_count++; |
fd6ce8f6 FB |
407 | } |
408 | ||
409 | #ifdef DEBUG_TB_CHECK | |
410 | ||
bc98a7ef | 411 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
412 | { |
413 | TranslationBlock *tb; | |
414 | int i; | |
415 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
416 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
417 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
418 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
419 | address >= tb->pc + tb->size)) { | |
420 | printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n", | |
99773bd4 | 421 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
422 | } |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | /* verify that all the pages have correct rights for code */ | |
428 | static void tb_page_check(void) | |
429 | { | |
430 | TranslationBlock *tb; | |
431 | int i, flags1, flags2; | |
3b46e624 | 432 | |
99773bd4 PB |
433 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
434 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
435 | flags1 = page_get_flags(tb->pc); |
436 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
437 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
438 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 439 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
440 | } |
441 | } | |
442 | } | |
443 | } | |
444 | ||
d4e8164f FB |
445 | void tb_jmp_check(TranslationBlock *tb) |
446 | { | |
447 | TranslationBlock *tb1; | |
448 | unsigned int n1; | |
449 | ||
450 | /* suppress any remaining jumps to this TB */ | |
451 | tb1 = tb->jmp_first; | |
452 | for(;;) { | |
453 | n1 = (long)tb1 & 3; | |
454 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
455 | if (n1 == 2) | |
456 | break; | |
457 | tb1 = tb1->jmp_next[n1]; | |
458 | } | |
459 | /* check end of list */ | |
460 | if (tb1 != tb) { | |
461 | printf("ERROR: jmp_list from 0x%08lx\n", (long)tb); | |
462 | } | |
463 | } | |
464 | ||
fd6ce8f6 FB |
465 | #endif |
466 | ||
467 | /* invalidate one TB */ | |
468 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
469 | int next_offset) | |
470 | { | |
471 | TranslationBlock *tb1; | |
472 | for(;;) { | |
473 | tb1 = *ptb; | |
474 | if (tb1 == tb) { | |
475 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
476 | break; | |
477 | } | |
478 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
479 | } | |
480 | } | |
481 | ||
9fa3e853 FB |
482 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
483 | { | |
484 | TranslationBlock *tb1; | |
485 | unsigned int n1; | |
486 | ||
487 | for(;;) { | |
488 | tb1 = *ptb; | |
489 | n1 = (long)tb1 & 3; | |
490 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
491 | if (tb1 == tb) { | |
492 | *ptb = tb1->page_next[n1]; | |
493 | break; | |
494 | } | |
495 | ptb = &tb1->page_next[n1]; | |
496 | } | |
497 | } | |
498 | ||
d4e8164f FB |
499 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
500 | { | |
501 | TranslationBlock *tb1, **ptb; | |
502 | unsigned int n1; | |
503 | ||
504 | ptb = &tb->jmp_next[n]; | |
505 | tb1 = *ptb; | |
506 | if (tb1) { | |
507 | /* find tb(n) in circular list */ | |
508 | for(;;) { | |
509 | tb1 = *ptb; | |
510 | n1 = (long)tb1 & 3; | |
511 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
512 | if (n1 == n && tb1 == tb) | |
513 | break; | |
514 | if (n1 == 2) { | |
515 | ptb = &tb1->jmp_first; | |
516 | } else { | |
517 | ptb = &tb1->jmp_next[n1]; | |
518 | } | |
519 | } | |
520 | /* now we can suppress tb(n) from the list */ | |
521 | *ptb = tb->jmp_next[n]; | |
522 | ||
523 | tb->jmp_next[n] = NULL; | |
524 | } | |
525 | } | |
526 | ||
527 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
528 | another TB */ | |
529 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
530 | { | |
531 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
532 | } | |
533 | ||
00f82b8a | 534 | static inline void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
fd6ce8f6 | 535 | { |
6a00d601 | 536 | CPUState *env; |
8a40a180 | 537 | PageDesc *p; |
d4e8164f | 538 | unsigned int h, n1; |
00f82b8a | 539 | target_phys_addr_t phys_pc; |
8a40a180 | 540 | TranslationBlock *tb1, *tb2; |
3b46e624 | 541 | |
8a40a180 FB |
542 | /* remove the TB from the hash list */ |
543 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
544 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 545 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
546 | offsetof(TranslationBlock, phys_hash_next)); |
547 | ||
548 | /* remove the TB from the page list */ | |
549 | if (tb->page_addr[0] != page_addr) { | |
550 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
551 | tb_page_remove(&p->first_tb, tb); | |
552 | invalidate_page_bitmap(p); | |
553 | } | |
554 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
555 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
556 | tb_page_remove(&p->first_tb, tb); | |
557 | invalidate_page_bitmap(p); | |
558 | } | |
559 | ||
36bdbe54 | 560 | tb_invalidated_flag = 1; |
59817ccb | 561 | |
fd6ce8f6 | 562 | /* remove the TB from the hash list */ |
8a40a180 | 563 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
564 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
565 | if (env->tb_jmp_cache[h] == tb) | |
566 | env->tb_jmp_cache[h] = NULL; | |
567 | } | |
d4e8164f FB |
568 | |
569 | /* suppress this TB from the two jump lists */ | |
570 | tb_jmp_remove(tb, 0); | |
571 | tb_jmp_remove(tb, 1); | |
572 | ||
573 | /* suppress any remaining jumps to this TB */ | |
574 | tb1 = tb->jmp_first; | |
575 | for(;;) { | |
576 | n1 = (long)tb1 & 3; | |
577 | if (n1 == 2) | |
578 | break; | |
579 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
580 | tb2 = tb1->jmp_next[n1]; | |
581 | tb_reset_jump(tb1, n1); | |
582 | tb1->jmp_next[n1] = NULL; | |
583 | tb1 = tb2; | |
584 | } | |
585 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 586 | |
e3db7226 | 587 | tb_phys_invalidate_count++; |
9fa3e853 FB |
588 | } |
589 | ||
590 | static inline void set_bits(uint8_t *tab, int start, int len) | |
591 | { | |
592 | int end, mask, end1; | |
593 | ||
594 | end = start + len; | |
595 | tab += start >> 3; | |
596 | mask = 0xff << (start & 7); | |
597 | if ((start & ~7) == (end & ~7)) { | |
598 | if (start < end) { | |
599 | mask &= ~(0xff << (end & 7)); | |
600 | *tab |= mask; | |
601 | } | |
602 | } else { | |
603 | *tab++ |= mask; | |
604 | start = (start + 8) & ~7; | |
605 | end1 = end & ~7; | |
606 | while (start < end1) { | |
607 | *tab++ = 0xff; | |
608 | start += 8; | |
609 | } | |
610 | if (start < end) { | |
611 | mask = ~(0xff << (end & 7)); | |
612 | *tab |= mask; | |
613 | } | |
614 | } | |
615 | } | |
616 | ||
617 | static void build_page_bitmap(PageDesc *p) | |
618 | { | |
619 | int n, tb_start, tb_end; | |
620 | TranslationBlock *tb; | |
3b46e624 | 621 | |
59817ccb | 622 | p->code_bitmap = qemu_malloc(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
623 | if (!p->code_bitmap) |
624 | return; | |
625 | memset(p->code_bitmap, 0, TARGET_PAGE_SIZE / 8); | |
626 | ||
627 | tb = p->first_tb; | |
628 | while (tb != NULL) { | |
629 | n = (long)tb & 3; | |
630 | tb = (TranslationBlock *)((long)tb & ~3); | |
631 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
632 | if (n == 0) { | |
633 | /* NOTE: tb_end may be after the end of the page, but | |
634 | it is not a problem */ | |
635 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
636 | tb_end = tb_start + tb->size; | |
637 | if (tb_end > TARGET_PAGE_SIZE) | |
638 | tb_end = TARGET_PAGE_SIZE; | |
639 | } else { | |
640 | tb_start = 0; | |
641 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
642 | } | |
643 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
644 | tb = tb->page_next[n]; | |
645 | } | |
646 | } | |
647 | ||
d720b93d FB |
648 | #ifdef TARGET_HAS_PRECISE_SMC |
649 | ||
5fafdf24 | 650 | static void tb_gen_code(CPUState *env, |
d720b93d FB |
651 | target_ulong pc, target_ulong cs_base, int flags, |
652 | int cflags) | |
653 | { | |
654 | TranslationBlock *tb; | |
655 | uint8_t *tc_ptr; | |
656 | target_ulong phys_pc, phys_page2, virt_page2; | |
657 | int code_gen_size; | |
658 | ||
c27004ec FB |
659 | phys_pc = get_phys_addr_code(env, pc); |
660 | tb = tb_alloc(pc); | |
d720b93d FB |
661 | if (!tb) { |
662 | /* flush must be done */ | |
663 | tb_flush(env); | |
664 | /* cannot fail at this point */ | |
c27004ec | 665 | tb = tb_alloc(pc); |
d720b93d FB |
666 | } |
667 | tc_ptr = code_gen_ptr; | |
668 | tb->tc_ptr = tc_ptr; | |
669 | tb->cs_base = cs_base; | |
670 | tb->flags = flags; | |
671 | tb->cflags = cflags; | |
d07bde88 | 672 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 673 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 674 | |
d720b93d | 675 | /* check next page if needed */ |
c27004ec | 676 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 677 | phys_page2 = -1; |
c27004ec | 678 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
d720b93d FB |
679 | phys_page2 = get_phys_addr_code(env, virt_page2); |
680 | } | |
681 | tb_link_phys(tb, phys_pc, phys_page2); | |
682 | } | |
683 | #endif | |
3b46e624 | 684 | |
9fa3e853 FB |
685 | /* invalidate all TBs which intersect with the target physical page |
686 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
687 | the same physical page. 'is_cpu_write_access' should be true if called |
688 | from a real cpu write access: the virtual CPU will exit the current | |
689 | TB if code is modified inside this TB. */ | |
00f82b8a | 690 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
d720b93d FB |
691 | int is_cpu_write_access) |
692 | { | |
693 | int n, current_tb_modified, current_tb_not_found, current_flags; | |
d720b93d | 694 | CPUState *env = cpu_single_env; |
9fa3e853 | 695 | PageDesc *p; |
ea1c1802 | 696 | TranslationBlock *tb, *tb_next, *current_tb, *saved_tb; |
9fa3e853 | 697 | target_ulong tb_start, tb_end; |
d720b93d | 698 | target_ulong current_pc, current_cs_base; |
9fa3e853 FB |
699 | |
700 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 701 | if (!p) |
9fa3e853 | 702 | return; |
5fafdf24 | 703 | if (!p->code_bitmap && |
d720b93d FB |
704 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
705 | is_cpu_write_access) { | |
9fa3e853 FB |
706 | /* build code bitmap */ |
707 | build_page_bitmap(p); | |
708 | } | |
709 | ||
710 | /* we remove all the TBs in the range [start, end[ */ | |
711 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
d720b93d FB |
712 | current_tb_not_found = is_cpu_write_access; |
713 | current_tb_modified = 0; | |
714 | current_tb = NULL; /* avoid warning */ | |
715 | current_pc = 0; /* avoid warning */ | |
716 | current_cs_base = 0; /* avoid warning */ | |
717 | current_flags = 0; /* avoid warning */ | |
9fa3e853 FB |
718 | tb = p->first_tb; |
719 | while (tb != NULL) { | |
720 | n = (long)tb & 3; | |
721 | tb = (TranslationBlock *)((long)tb & ~3); | |
722 | tb_next = tb->page_next[n]; | |
723 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
724 | if (n == 0) { | |
725 | /* NOTE: tb_end may be after the end of the page, but | |
726 | it is not a problem */ | |
727 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
728 | tb_end = tb_start + tb->size; | |
729 | } else { | |
730 | tb_start = tb->page_addr[1]; | |
731 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
732 | } | |
733 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
734 | #ifdef TARGET_HAS_PRECISE_SMC |
735 | if (current_tb_not_found) { | |
736 | current_tb_not_found = 0; | |
737 | current_tb = NULL; | |
738 | if (env->mem_write_pc) { | |
739 | /* now we have a real cpu fault */ | |
740 | current_tb = tb_find_pc(env->mem_write_pc); | |
741 | } | |
742 | } | |
743 | if (current_tb == tb && | |
744 | !(current_tb->cflags & CF_SINGLE_INSN)) { | |
745 | /* If we are modifying the current TB, we must stop | |
746 | its execution. We could be more precise by checking | |
747 | that the modification is after the current PC, but it | |
748 | would require a specialized function to partially | |
749 | restore the CPU state */ | |
3b46e624 | 750 | |
d720b93d | 751 | current_tb_modified = 1; |
5fafdf24 | 752 | cpu_restore_state(current_tb, env, |
d720b93d FB |
753 | env->mem_write_pc, NULL); |
754 | #if defined(TARGET_I386) | |
755 | current_flags = env->hflags; | |
756 | current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); | |
757 | current_cs_base = (target_ulong)env->segs[R_CS].base; | |
758 | current_pc = current_cs_base + env->eip; | |
759 | #else | |
760 | #error unsupported CPU | |
761 | #endif | |
762 | } | |
763 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
764 | /* we need to do that to handle the case where a signal |
765 | occurs while doing tb_phys_invalidate() */ | |
766 | saved_tb = NULL; | |
767 | if (env) { | |
768 | saved_tb = env->current_tb; | |
769 | env->current_tb = NULL; | |
770 | } | |
9fa3e853 | 771 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
772 | if (env) { |
773 | env->current_tb = saved_tb; | |
774 | if (env->interrupt_request && env->current_tb) | |
775 | cpu_interrupt(env, env->interrupt_request); | |
776 | } | |
9fa3e853 FB |
777 | } |
778 | tb = tb_next; | |
779 | } | |
780 | #if !defined(CONFIG_USER_ONLY) | |
781 | /* if no code remaining, no need to continue to use slow writes */ | |
782 | if (!p->first_tb) { | |
783 | invalidate_page_bitmap(p); | |
d720b93d FB |
784 | if (is_cpu_write_access) { |
785 | tlb_unprotect_code_phys(env, start, env->mem_write_vaddr); | |
786 | } | |
787 | } | |
788 | #endif | |
789 | #ifdef TARGET_HAS_PRECISE_SMC | |
790 | if (current_tb_modified) { | |
791 | /* we generate a block containing just the instruction | |
792 | modifying the memory. It will ensure that it cannot modify | |
793 | itself */ | |
ea1c1802 | 794 | env->current_tb = NULL; |
5fafdf24 | 795 | tb_gen_code(env, current_pc, current_cs_base, current_flags, |
d720b93d FB |
796 | CF_SINGLE_INSN); |
797 | cpu_resume_from_signal(env, NULL); | |
9fa3e853 | 798 | } |
fd6ce8f6 | 799 | #endif |
9fa3e853 | 800 | } |
fd6ce8f6 | 801 | |
9fa3e853 | 802 | /* len must be <= 8 and start must be a multiple of len */ |
00f82b8a | 803 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
9fa3e853 FB |
804 | { |
805 | PageDesc *p; | |
806 | int offset, b; | |
59817ccb | 807 | #if 0 |
a4193c8a FB |
808 | if (1) { |
809 | if (loglevel) { | |
5fafdf24 TS |
810 | fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
811 | cpu_single_env->mem_write_vaddr, len, | |
812 | cpu_single_env->eip, | |
a4193c8a FB |
813 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
814 | } | |
59817ccb FB |
815 | } |
816 | #endif | |
9fa3e853 | 817 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 818 | if (!p) |
9fa3e853 FB |
819 | return; |
820 | if (p->code_bitmap) { | |
821 | offset = start & ~TARGET_PAGE_MASK; | |
822 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
823 | if (b & ((1 << len) - 1)) | |
824 | goto do_invalidate; | |
825 | } else { | |
826 | do_invalidate: | |
d720b93d | 827 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
828 | } |
829 | } | |
830 | ||
9fa3e853 | 831 | #if !defined(CONFIG_SOFTMMU) |
00f82b8a | 832 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
d720b93d | 833 | unsigned long pc, void *puc) |
9fa3e853 | 834 | { |
d720b93d FB |
835 | int n, current_flags, current_tb_modified; |
836 | target_ulong current_pc, current_cs_base; | |
9fa3e853 | 837 | PageDesc *p; |
d720b93d FB |
838 | TranslationBlock *tb, *current_tb; |
839 | #ifdef TARGET_HAS_PRECISE_SMC | |
840 | CPUState *env = cpu_single_env; | |
841 | #endif | |
9fa3e853 FB |
842 | |
843 | addr &= TARGET_PAGE_MASK; | |
844 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 845 | if (!p) |
9fa3e853 FB |
846 | return; |
847 | tb = p->first_tb; | |
d720b93d FB |
848 | current_tb_modified = 0; |
849 | current_tb = NULL; | |
850 | current_pc = 0; /* avoid warning */ | |
851 | current_cs_base = 0; /* avoid warning */ | |
852 | current_flags = 0; /* avoid warning */ | |
853 | #ifdef TARGET_HAS_PRECISE_SMC | |
854 | if (tb && pc != 0) { | |
855 | current_tb = tb_find_pc(pc); | |
856 | } | |
857 | #endif | |
9fa3e853 FB |
858 | while (tb != NULL) { |
859 | n = (long)tb & 3; | |
860 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
861 | #ifdef TARGET_HAS_PRECISE_SMC |
862 | if (current_tb == tb && | |
863 | !(current_tb->cflags & CF_SINGLE_INSN)) { | |
864 | /* If we are modifying the current TB, we must stop | |
865 | its execution. We could be more precise by checking | |
866 | that the modification is after the current PC, but it | |
867 | would require a specialized function to partially | |
868 | restore the CPU state */ | |
3b46e624 | 869 | |
d720b93d FB |
870 | current_tb_modified = 1; |
871 | cpu_restore_state(current_tb, env, pc, puc); | |
872 | #if defined(TARGET_I386) | |
873 | current_flags = env->hflags; | |
874 | current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); | |
875 | current_cs_base = (target_ulong)env->segs[R_CS].base; | |
876 | current_pc = current_cs_base + env->eip; | |
877 | #else | |
878 | #error unsupported CPU | |
879 | #endif | |
880 | } | |
881 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
882 | tb_phys_invalidate(tb, addr); |
883 | tb = tb->page_next[n]; | |
884 | } | |
fd6ce8f6 | 885 | p->first_tb = NULL; |
d720b93d FB |
886 | #ifdef TARGET_HAS_PRECISE_SMC |
887 | if (current_tb_modified) { | |
888 | /* we generate a block containing just the instruction | |
889 | modifying the memory. It will ensure that it cannot modify | |
890 | itself */ | |
ea1c1802 | 891 | env->current_tb = NULL; |
5fafdf24 | 892 | tb_gen_code(env, current_pc, current_cs_base, current_flags, |
d720b93d FB |
893 | CF_SINGLE_INSN); |
894 | cpu_resume_from_signal(env, puc); | |
895 | } | |
896 | #endif | |
fd6ce8f6 | 897 | } |
9fa3e853 | 898 | #endif |
fd6ce8f6 FB |
899 | |
900 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 901 | static inline void tb_alloc_page(TranslationBlock *tb, |
53a5960a | 902 | unsigned int n, target_ulong page_addr) |
fd6ce8f6 FB |
903 | { |
904 | PageDesc *p; | |
9fa3e853 FB |
905 | TranslationBlock *last_first_tb; |
906 | ||
907 | tb->page_addr[n] = page_addr; | |
3a7d929e | 908 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
909 | tb->page_next[n] = p->first_tb; |
910 | last_first_tb = p->first_tb; | |
911 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
912 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 913 | |
107db443 | 914 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 915 | |
9fa3e853 | 916 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 917 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
918 | target_ulong addr; |
919 | PageDesc *p2; | |
9fa3e853 FB |
920 | int prot; |
921 | ||
fd6ce8f6 FB |
922 | /* force the host page as non writable (writes will have a |
923 | page fault + mprotect overhead) */ | |
53a5960a | 924 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 925 | prot = 0; |
53a5960a PB |
926 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
927 | addr += TARGET_PAGE_SIZE) { | |
928 | ||
929 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
930 | if (!p2) | |
931 | continue; | |
932 | prot |= p2->flags; | |
933 | p2->flags &= ~PAGE_WRITE; | |
934 | page_get_flags(addr); | |
935 | } | |
5fafdf24 | 936 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
937 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
938 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 939 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 940 | page_addr); |
fd6ce8f6 | 941 | #endif |
fd6ce8f6 | 942 | } |
9fa3e853 FB |
943 | #else |
944 | /* if some code is already present, then the pages are already | |
945 | protected. So we handle the case where only the first TB is | |
946 | allocated in a physical page */ | |
947 | if (!last_first_tb) { | |
6a00d601 | 948 | tlb_protect_code(page_addr); |
9fa3e853 FB |
949 | } |
950 | #endif | |
d720b93d FB |
951 | |
952 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
953 | } |
954 | ||
955 | /* Allocate a new translation block. Flush the translation buffer if | |
956 | too many translation blocks or too much generated code. */ | |
c27004ec | 957 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
958 | { |
959 | TranslationBlock *tb; | |
fd6ce8f6 | 960 | |
5fafdf24 | 961 | if (nb_tbs >= CODE_GEN_MAX_BLOCKS || |
fd6ce8f6 | 962 | (code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE) |
d4e8164f | 963 | return NULL; |
fd6ce8f6 FB |
964 | tb = &tbs[nb_tbs++]; |
965 | tb->pc = pc; | |
b448f2f3 | 966 | tb->cflags = 0; |
d4e8164f FB |
967 | return tb; |
968 | } | |
969 | ||
9fa3e853 FB |
970 | /* add a new TB and link it to the physical page tables. phys_page2 is |
971 | (-1) to indicate that only one page contains the TB. */ | |
5fafdf24 | 972 | void tb_link_phys(TranslationBlock *tb, |
9fa3e853 | 973 | target_ulong phys_pc, target_ulong phys_page2) |
d4e8164f | 974 | { |
9fa3e853 FB |
975 | unsigned int h; |
976 | TranslationBlock **ptb; | |
977 | ||
978 | /* add in the physical hash table */ | |
979 | h = tb_phys_hash_func(phys_pc); | |
980 | ptb = &tb_phys_hash[h]; | |
981 | tb->phys_hash_next = *ptb; | |
982 | *ptb = tb; | |
fd6ce8f6 FB |
983 | |
984 | /* add in the page list */ | |
9fa3e853 FB |
985 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
986 | if (phys_page2 != -1) | |
987 | tb_alloc_page(tb, 1, phys_page2); | |
988 | else | |
989 | tb->page_addr[1] = -1; | |
9fa3e853 | 990 | |
d4e8164f FB |
991 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
992 | tb->jmp_next[0] = NULL; | |
993 | tb->jmp_next[1] = NULL; | |
994 | ||
995 | /* init original jump addresses */ | |
996 | if (tb->tb_next_offset[0] != 0xffff) | |
997 | tb_reset_jump(tb, 0); | |
998 | if (tb->tb_next_offset[1] != 0xffff) | |
999 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1000 | |
1001 | #ifdef DEBUG_TB_CHECK | |
1002 | tb_page_check(); | |
1003 | #endif | |
fd6ce8f6 FB |
1004 | } |
1005 | ||
9fa3e853 FB |
1006 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1007 | tb[1].tc_ptr. Return NULL if not found */ | |
1008 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1009 | { |
9fa3e853 FB |
1010 | int m_min, m_max, m; |
1011 | unsigned long v; | |
1012 | TranslationBlock *tb; | |
a513fe19 FB |
1013 | |
1014 | if (nb_tbs <= 0) | |
1015 | return NULL; | |
1016 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1017 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1018 | return NULL; | |
1019 | /* binary search (cf Knuth) */ | |
1020 | m_min = 0; | |
1021 | m_max = nb_tbs - 1; | |
1022 | while (m_min <= m_max) { | |
1023 | m = (m_min + m_max) >> 1; | |
1024 | tb = &tbs[m]; | |
1025 | v = (unsigned long)tb->tc_ptr; | |
1026 | if (v == tc_ptr) | |
1027 | return tb; | |
1028 | else if (tc_ptr < v) { | |
1029 | m_max = m - 1; | |
1030 | } else { | |
1031 | m_min = m + 1; | |
1032 | } | |
5fafdf24 | 1033 | } |
a513fe19 FB |
1034 | return &tbs[m_max]; |
1035 | } | |
7501267e | 1036 | |
ea041c0e FB |
1037 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1038 | ||
1039 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1040 | { | |
1041 | TranslationBlock *tb1, *tb_next, **ptb; | |
1042 | unsigned int n1; | |
1043 | ||
1044 | tb1 = tb->jmp_next[n]; | |
1045 | if (tb1 != NULL) { | |
1046 | /* find head of list */ | |
1047 | for(;;) { | |
1048 | n1 = (long)tb1 & 3; | |
1049 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1050 | if (n1 == 2) | |
1051 | break; | |
1052 | tb1 = tb1->jmp_next[n1]; | |
1053 | } | |
1054 | /* we are now sure now that tb jumps to tb1 */ | |
1055 | tb_next = tb1; | |
1056 | ||
1057 | /* remove tb from the jmp_first list */ | |
1058 | ptb = &tb_next->jmp_first; | |
1059 | for(;;) { | |
1060 | tb1 = *ptb; | |
1061 | n1 = (long)tb1 & 3; | |
1062 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1063 | if (n1 == n && tb1 == tb) | |
1064 | break; | |
1065 | ptb = &tb1->jmp_next[n1]; | |
1066 | } | |
1067 | *ptb = tb->jmp_next[n]; | |
1068 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1069 | |
ea041c0e FB |
1070 | /* suppress the jump to next tb in generated code */ |
1071 | tb_reset_jump(tb, n); | |
1072 | ||
0124311e | 1073 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1074 | tb_reset_jump_recursive(tb_next); |
1075 | } | |
1076 | } | |
1077 | ||
1078 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1079 | { | |
1080 | tb_reset_jump_recursive2(tb, 0); | |
1081 | tb_reset_jump_recursive2(tb, 1); | |
1082 | } | |
1083 | ||
1fddef4b | 1084 | #if defined(TARGET_HAS_ICE) |
d720b93d FB |
1085 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1086 | { | |
9b3c35e0 JM |
1087 | target_phys_addr_t addr; |
1088 | target_ulong pd; | |
c2f07f81 PB |
1089 | ram_addr_t ram_addr; |
1090 | PhysPageDesc *p; | |
d720b93d | 1091 | |
c2f07f81 PB |
1092 | addr = cpu_get_phys_page_debug(env, pc); |
1093 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1094 | if (!p) { | |
1095 | pd = IO_MEM_UNASSIGNED; | |
1096 | } else { | |
1097 | pd = p->phys_offset; | |
1098 | } | |
1099 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1100 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1101 | } |
c27004ec | 1102 | #endif |
d720b93d | 1103 | |
6658ffb8 PB |
1104 | /* Add a watchpoint. */ |
1105 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr) | |
1106 | { | |
1107 | int i; | |
1108 | ||
1109 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1110 | if (addr == env->watchpoint[i].vaddr) | |
1111 | return 0; | |
1112 | } | |
1113 | if (env->nb_watchpoints >= MAX_WATCHPOINTS) | |
1114 | return -1; | |
1115 | ||
1116 | i = env->nb_watchpoints++; | |
1117 | env->watchpoint[i].vaddr = addr; | |
1118 | tlb_flush_page(env, addr); | |
1119 | /* FIXME: This flush is needed because of the hack to make memory ops | |
1120 | terminate the TB. It can be removed once the proper IO trap and | |
1121 | re-execute bits are in. */ | |
1122 | tb_flush(env); | |
1123 | return i; | |
1124 | } | |
1125 | ||
1126 | /* Remove a watchpoint. */ | |
1127 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr) | |
1128 | { | |
1129 | int i; | |
1130 | ||
1131 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1132 | if (addr == env->watchpoint[i].vaddr) { | |
1133 | env->nb_watchpoints--; | |
1134 | env->watchpoint[i] = env->watchpoint[env->nb_watchpoints]; | |
1135 | tlb_flush_page(env, addr); | |
1136 | return 0; | |
1137 | } | |
1138 | } | |
1139 | return -1; | |
1140 | } | |
1141 | ||
c33a346e FB |
1142 | /* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a |
1143 | breakpoint is reached */ | |
2e12669a | 1144 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc) |
4c3a88a2 | 1145 | { |
1fddef4b | 1146 | #if defined(TARGET_HAS_ICE) |
4c3a88a2 | 1147 | int i; |
3b46e624 | 1148 | |
4c3a88a2 FB |
1149 | for(i = 0; i < env->nb_breakpoints; i++) { |
1150 | if (env->breakpoints[i] == pc) | |
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | if (env->nb_breakpoints >= MAX_BREAKPOINTS) | |
1155 | return -1; | |
1156 | env->breakpoints[env->nb_breakpoints++] = pc; | |
3b46e624 | 1157 | |
d720b93d | 1158 | breakpoint_invalidate(env, pc); |
4c3a88a2 FB |
1159 | return 0; |
1160 | #else | |
1161 | return -1; | |
1162 | #endif | |
1163 | } | |
1164 | ||
1165 | /* remove a breakpoint */ | |
2e12669a | 1166 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc) |
4c3a88a2 | 1167 | { |
1fddef4b | 1168 | #if defined(TARGET_HAS_ICE) |
4c3a88a2 FB |
1169 | int i; |
1170 | for(i = 0; i < env->nb_breakpoints; i++) { | |
1171 | if (env->breakpoints[i] == pc) | |
1172 | goto found; | |
1173 | } | |
1174 | return -1; | |
1175 | found: | |
4c3a88a2 | 1176 | env->nb_breakpoints--; |
1fddef4b FB |
1177 | if (i < env->nb_breakpoints) |
1178 | env->breakpoints[i] = env->breakpoints[env->nb_breakpoints]; | |
d720b93d FB |
1179 | |
1180 | breakpoint_invalidate(env, pc); | |
4c3a88a2 FB |
1181 | return 0; |
1182 | #else | |
1183 | return -1; | |
1184 | #endif | |
1185 | } | |
1186 | ||
c33a346e FB |
1187 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1188 | CPU loop after each instruction */ | |
1189 | void cpu_single_step(CPUState *env, int enabled) | |
1190 | { | |
1fddef4b | 1191 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1192 | if (env->singlestep_enabled != enabled) { |
1193 | env->singlestep_enabled = enabled; | |
1194 | /* must flush all the translated code to avoid inconsistancies */ | |
9fa3e853 | 1195 | /* XXX: only flush what is necessary */ |
0124311e | 1196 | tb_flush(env); |
c33a346e FB |
1197 | } |
1198 | #endif | |
1199 | } | |
1200 | ||
34865134 FB |
1201 | /* enable or disable low levels log */ |
1202 | void cpu_set_log(int log_flags) | |
1203 | { | |
1204 | loglevel = log_flags; | |
1205 | if (loglevel && !logfile) { | |
11fcfab4 | 1206 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1207 | if (!logfile) { |
1208 | perror(logfilename); | |
1209 | _exit(1); | |
1210 | } | |
9fa3e853 FB |
1211 | #if !defined(CONFIG_SOFTMMU) |
1212 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1213 | { | |
1214 | static uint8_t logfile_buf[4096]; | |
1215 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); | |
1216 | } | |
1217 | #else | |
34865134 | 1218 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1219 | #endif |
e735b91c PB |
1220 | log_append = 1; |
1221 | } | |
1222 | if (!loglevel && logfile) { | |
1223 | fclose(logfile); | |
1224 | logfile = NULL; | |
34865134 FB |
1225 | } |
1226 | } | |
1227 | ||
1228 | void cpu_set_log_filename(const char *filename) | |
1229 | { | |
1230 | logfilename = strdup(filename); | |
e735b91c PB |
1231 | if (logfile) { |
1232 | fclose(logfile); | |
1233 | logfile = NULL; | |
1234 | } | |
1235 | cpu_set_log(loglevel); | |
34865134 | 1236 | } |
c33a346e | 1237 | |
0124311e | 1238 | /* mask must never be zero, except for A20 change call */ |
68a79315 | 1239 | void cpu_interrupt(CPUState *env, int mask) |
ea041c0e FB |
1240 | { |
1241 | TranslationBlock *tb; | |
15a51156 | 1242 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1243 | |
68a79315 | 1244 | env->interrupt_request |= mask; |
ea041c0e FB |
1245 | /* if the cpu is currently executing code, we must unlink it and |
1246 | all the potentially executing TB */ | |
1247 | tb = env->current_tb; | |
ee8b7021 FB |
1248 | if (tb && !testandset(&interrupt_lock)) { |
1249 | env->current_tb = NULL; | |
ea041c0e | 1250 | tb_reset_jump_recursive(tb); |
15a51156 | 1251 | resetlock(&interrupt_lock); |
ea041c0e FB |
1252 | } |
1253 | } | |
1254 | ||
b54ad049 FB |
1255 | void cpu_reset_interrupt(CPUState *env, int mask) |
1256 | { | |
1257 | env->interrupt_request &= ~mask; | |
1258 | } | |
1259 | ||
f193c797 | 1260 | CPULogItem cpu_log_items[] = { |
5fafdf24 | 1261 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1262 | "show generated host assembly code for each compiled TB" }, |
1263 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1264 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1265 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1266 | "show micro ops for each compiled TB" }, |
f193c797 | 1267 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1268 | "show micro ops " |
1269 | #ifdef TARGET_I386 | |
1270 | "before eflags optimization and " | |
f193c797 | 1271 | #endif |
e01a1157 | 1272 | "after liveness analysis" }, |
f193c797 FB |
1273 | { CPU_LOG_INT, "int", |
1274 | "show interrupts/exceptions in short format" }, | |
1275 | { CPU_LOG_EXEC, "exec", | |
1276 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1277 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1278 | "show CPU state before block translation" }, |
f193c797 FB |
1279 | #ifdef TARGET_I386 |
1280 | { CPU_LOG_PCALL, "pcall", | |
1281 | "show protected mode far calls/returns/exceptions" }, | |
1282 | #endif | |
8e3a9fd2 | 1283 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1284 | { CPU_LOG_IOPORT, "ioport", |
1285 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1286 | #endif |
f193c797 FB |
1287 | { 0, NULL, NULL }, |
1288 | }; | |
1289 | ||
1290 | static int cmp1(const char *s1, int n, const char *s2) | |
1291 | { | |
1292 | if (strlen(s2) != n) | |
1293 | return 0; | |
1294 | return memcmp(s1, s2, n) == 0; | |
1295 | } | |
3b46e624 | 1296 | |
f193c797 FB |
1297 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1298 | int cpu_str_to_log_mask(const char *str) | |
1299 | { | |
1300 | CPULogItem *item; | |
1301 | int mask; | |
1302 | const char *p, *p1; | |
1303 | ||
1304 | p = str; | |
1305 | mask = 0; | |
1306 | for(;;) { | |
1307 | p1 = strchr(p, ','); | |
1308 | if (!p1) | |
1309 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1310 | if(cmp1(p,p1-p,"all")) { |
1311 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1312 | mask |= item->mask; | |
1313 | } | |
1314 | } else { | |
f193c797 FB |
1315 | for(item = cpu_log_items; item->mask != 0; item++) { |
1316 | if (cmp1(p, p1 - p, item->name)) | |
1317 | goto found; | |
1318 | } | |
1319 | return 0; | |
8e3a9fd2 | 1320 | } |
f193c797 FB |
1321 | found: |
1322 | mask |= item->mask; | |
1323 | if (*p1 != ',') | |
1324 | break; | |
1325 | p = p1 + 1; | |
1326 | } | |
1327 | return mask; | |
1328 | } | |
ea041c0e | 1329 | |
7501267e FB |
1330 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1331 | { | |
1332 | va_list ap; | |
493ae1f0 | 1333 | va_list ap2; |
7501267e FB |
1334 | |
1335 | va_start(ap, fmt); | |
493ae1f0 | 1336 | va_copy(ap2, ap); |
7501267e FB |
1337 | fprintf(stderr, "qemu: fatal: "); |
1338 | vfprintf(stderr, fmt, ap); | |
1339 | fprintf(stderr, "\n"); | |
1340 | #ifdef TARGET_I386 | |
7fe48483 FB |
1341 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1342 | #else | |
1343 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1344 | #endif |
924edcae | 1345 | if (logfile) { |
f9373291 | 1346 | fprintf(logfile, "qemu: fatal: "); |
493ae1f0 | 1347 | vfprintf(logfile, fmt, ap2); |
f9373291 JM |
1348 | fprintf(logfile, "\n"); |
1349 | #ifdef TARGET_I386 | |
1350 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); | |
1351 | #else | |
1352 | cpu_dump_state(env, logfile, fprintf, 0); | |
1353 | #endif | |
924edcae AZ |
1354 | fflush(logfile); |
1355 | fclose(logfile); | |
1356 | } | |
493ae1f0 | 1357 | va_end(ap2); |
f9373291 | 1358 | va_end(ap); |
7501267e FB |
1359 | abort(); |
1360 | } | |
1361 | ||
c5be9f08 TS |
1362 | CPUState *cpu_copy(CPUState *env) |
1363 | { | |
01ba9816 | 1364 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1365 | /* preserve chaining and index */ |
1366 | CPUState *next_cpu = new_env->next_cpu; | |
1367 | int cpu_index = new_env->cpu_index; | |
1368 | memcpy(new_env, env, sizeof(CPUState)); | |
1369 | new_env->next_cpu = next_cpu; | |
1370 | new_env->cpu_index = cpu_index; | |
1371 | return new_env; | |
1372 | } | |
1373 | ||
0124311e FB |
1374 | #if !defined(CONFIG_USER_ONLY) |
1375 | ||
5c751e99 EI |
1376 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1377 | { | |
1378 | unsigned int i; | |
1379 | ||
1380 | /* Discard jump cache entries for any tb which might potentially | |
1381 | overlap the flushed page. */ | |
1382 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1383 | memset (&env->tb_jmp_cache[i], 0, | |
1384 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1385 | ||
1386 | i = tb_jmp_cache_hash_page(addr); | |
1387 | memset (&env->tb_jmp_cache[i], 0, | |
1388 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1389 | } | |
1390 | ||
ee8b7021 FB |
1391 | /* NOTE: if flush_global is true, also flush global entries (not |
1392 | implemented yet) */ | |
1393 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1394 | { |
33417e70 | 1395 | int i; |
0124311e | 1396 | |
9fa3e853 FB |
1397 | #if defined(DEBUG_TLB) |
1398 | printf("tlb_flush:\n"); | |
1399 | #endif | |
0124311e FB |
1400 | /* must reset current TB so that interrupts cannot modify the |
1401 | links while we are modifying them */ | |
1402 | env->current_tb = NULL; | |
1403 | ||
33417e70 | 1404 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
84b7b8e7 FB |
1405 | env->tlb_table[0][i].addr_read = -1; |
1406 | env->tlb_table[0][i].addr_write = -1; | |
1407 | env->tlb_table[0][i].addr_code = -1; | |
1408 | env->tlb_table[1][i].addr_read = -1; | |
1409 | env->tlb_table[1][i].addr_write = -1; | |
1410 | env->tlb_table[1][i].addr_code = -1; | |
6fa4cea9 JM |
1411 | #if (NB_MMU_MODES >= 3) |
1412 | env->tlb_table[2][i].addr_read = -1; | |
1413 | env->tlb_table[2][i].addr_write = -1; | |
1414 | env->tlb_table[2][i].addr_code = -1; | |
1415 | #if (NB_MMU_MODES == 4) | |
1416 | env->tlb_table[3][i].addr_read = -1; | |
1417 | env->tlb_table[3][i].addr_write = -1; | |
1418 | env->tlb_table[3][i].addr_code = -1; | |
1419 | #endif | |
1420 | #endif | |
33417e70 | 1421 | } |
9fa3e853 | 1422 | |
8a40a180 | 1423 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 FB |
1424 | |
1425 | #if !defined(CONFIG_SOFTMMU) | |
1426 | munmap((void *)MMAP_AREA_START, MMAP_AREA_END - MMAP_AREA_START); | |
0a962c02 FB |
1427 | #endif |
1428 | #ifdef USE_KQEMU | |
1429 | if (env->kqemu_enabled) { | |
1430 | kqemu_flush(env, flush_global); | |
1431 | } | |
9fa3e853 | 1432 | #endif |
e3db7226 | 1433 | tlb_flush_count++; |
33417e70 FB |
1434 | } |
1435 | ||
274da6b2 | 1436 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1437 | { |
5fafdf24 | 1438 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1439 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1440 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1441 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1442 | addr == (tlb_entry->addr_code & |
84b7b8e7 FB |
1443 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
1444 | tlb_entry->addr_read = -1; | |
1445 | tlb_entry->addr_write = -1; | |
1446 | tlb_entry->addr_code = -1; | |
1447 | } | |
61382a50 FB |
1448 | } |
1449 | ||
2e12669a | 1450 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1451 | { |
8a40a180 | 1452 | int i; |
0124311e | 1453 | |
9fa3e853 | 1454 | #if defined(DEBUG_TLB) |
108c49b8 | 1455 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1456 | #endif |
0124311e FB |
1457 | /* must reset current TB so that interrupts cannot modify the |
1458 | links while we are modifying them */ | |
1459 | env->current_tb = NULL; | |
61382a50 FB |
1460 | |
1461 | addr &= TARGET_PAGE_MASK; | |
1462 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
84b7b8e7 FB |
1463 | tlb_flush_entry(&env->tlb_table[0][i], addr); |
1464 | tlb_flush_entry(&env->tlb_table[1][i], addr); | |
6fa4cea9 JM |
1465 | #if (NB_MMU_MODES >= 3) |
1466 | tlb_flush_entry(&env->tlb_table[2][i], addr); | |
1467 | #if (NB_MMU_MODES == 4) | |
1468 | tlb_flush_entry(&env->tlb_table[3][i], addr); | |
1469 | #endif | |
1470 | #endif | |
0124311e | 1471 | |
5c751e99 | 1472 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 | 1473 | |
0124311e | 1474 | #if !defined(CONFIG_SOFTMMU) |
9fa3e853 | 1475 | if (addr < MMAP_AREA_END) |
0124311e | 1476 | munmap((void *)addr, TARGET_PAGE_SIZE); |
61382a50 | 1477 | #endif |
0a962c02 FB |
1478 | #ifdef USE_KQEMU |
1479 | if (env->kqemu_enabled) { | |
1480 | kqemu_flush_page(env, addr); | |
1481 | } | |
1482 | #endif | |
9fa3e853 FB |
1483 | } |
1484 | ||
9fa3e853 FB |
1485 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1486 | can be detected */ | |
6a00d601 | 1487 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1488 | { |
5fafdf24 | 1489 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1490 | ram_addr + TARGET_PAGE_SIZE, |
1491 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1492 | } |
1493 | ||
9fa3e853 | 1494 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 1495 | tested for self modifying code */ |
5fafdf24 | 1496 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 1497 | target_ulong vaddr) |
9fa3e853 | 1498 | { |
3a7d929e | 1499 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
1ccde1cb FB |
1500 | } |
1501 | ||
5fafdf24 | 1502 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
1503 | unsigned long start, unsigned long length) |
1504 | { | |
1505 | unsigned long addr; | |
84b7b8e7 FB |
1506 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
1507 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1508 | if ((addr - start) < length) { |
84b7b8e7 | 1509 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_NOTDIRTY; |
1ccde1cb FB |
1510 | } |
1511 | } | |
1512 | } | |
1513 | ||
3a7d929e | 1514 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 1515 | int dirty_flags) |
1ccde1cb FB |
1516 | { |
1517 | CPUState *env; | |
4f2ac237 | 1518 | unsigned long length, start1; |
0a962c02 FB |
1519 | int i, mask, len; |
1520 | uint8_t *p; | |
1ccde1cb FB |
1521 | |
1522 | start &= TARGET_PAGE_MASK; | |
1523 | end = TARGET_PAGE_ALIGN(end); | |
1524 | ||
1525 | length = end - start; | |
1526 | if (length == 0) | |
1527 | return; | |
0a962c02 | 1528 | len = length >> TARGET_PAGE_BITS; |
3a7d929e | 1529 | #ifdef USE_KQEMU |
6a00d601 FB |
1530 | /* XXX: should not depend on cpu context */ |
1531 | env = first_cpu; | |
3a7d929e | 1532 | if (env->kqemu_enabled) { |
f23db169 FB |
1533 | ram_addr_t addr; |
1534 | addr = start; | |
1535 | for(i = 0; i < len; i++) { | |
1536 | kqemu_set_notdirty(env, addr); | |
1537 | addr += TARGET_PAGE_SIZE; | |
1538 | } | |
3a7d929e FB |
1539 | } |
1540 | #endif | |
f23db169 FB |
1541 | mask = ~dirty_flags; |
1542 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); | |
1543 | for(i = 0; i < len; i++) | |
1544 | p[i] &= mask; | |
1545 | ||
1ccde1cb FB |
1546 | /* we modify the TLB cache so that the dirty bit will be set again |
1547 | when accessing the range */ | |
59817ccb | 1548 | start1 = start + (unsigned long)phys_ram_base; |
6a00d601 FB |
1549 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
1550 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
84b7b8e7 | 1551 | tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length); |
6a00d601 | 1552 | for(i = 0; i < CPU_TLB_SIZE; i++) |
84b7b8e7 | 1553 | tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length); |
6fa4cea9 JM |
1554 | #if (NB_MMU_MODES >= 3) |
1555 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1556 | tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); | |
1557 | #if (NB_MMU_MODES == 4) | |
1558 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1559 | tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); | |
1560 | #endif | |
1561 | #endif | |
6a00d601 | 1562 | } |
59817ccb FB |
1563 | |
1564 | #if !defined(CONFIG_SOFTMMU) | |
1565 | /* XXX: this is expensive */ | |
1566 | { | |
1567 | VirtPageDesc *p; | |
1568 | int j; | |
1569 | target_ulong addr; | |
1570 | ||
1571 | for(i = 0; i < L1_SIZE; i++) { | |
1572 | p = l1_virt_map[i]; | |
1573 | if (p) { | |
1574 | addr = i << (TARGET_PAGE_BITS + L2_BITS); | |
1575 | for(j = 0; j < L2_SIZE; j++) { | |
1576 | if (p->valid_tag == virt_valid_tag && | |
1577 | p->phys_addr >= start && p->phys_addr < end && | |
1578 | (p->prot & PROT_WRITE)) { | |
1579 | if (addr < MMAP_AREA_END) { | |
5fafdf24 | 1580 | mprotect((void *)addr, TARGET_PAGE_SIZE, |
59817ccb FB |
1581 | p->prot & ~PROT_WRITE); |
1582 | } | |
1583 | } | |
1584 | addr += TARGET_PAGE_SIZE; | |
1585 | p++; | |
1586 | } | |
1587 | } | |
1588 | } | |
1589 | } | |
1590 | #endif | |
1ccde1cb FB |
1591 | } |
1592 | ||
3a7d929e FB |
1593 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
1594 | { | |
1595 | ram_addr_t ram_addr; | |
1596 | ||
84b7b8e7 | 1597 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5fafdf24 | 1598 | ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + |
3a7d929e FB |
1599 | tlb_entry->addend - (unsigned long)phys_ram_base; |
1600 | if (!cpu_physical_memory_is_dirty(ram_addr)) { | |
84b7b8e7 | 1601 | tlb_entry->addr_write |= IO_MEM_NOTDIRTY; |
3a7d929e FB |
1602 | } |
1603 | } | |
1604 | } | |
1605 | ||
1606 | /* update the TLB according to the current state of the dirty bits */ | |
1607 | void cpu_tlb_update_dirty(CPUState *env) | |
1608 | { | |
1609 | int i; | |
1610 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
84b7b8e7 | 1611 | tlb_update_dirty(&env->tlb_table[0][i]); |
3a7d929e | 1612 | for(i = 0; i < CPU_TLB_SIZE; i++) |
84b7b8e7 | 1613 | tlb_update_dirty(&env->tlb_table[1][i]); |
6fa4cea9 JM |
1614 | #if (NB_MMU_MODES >= 3) |
1615 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1616 | tlb_update_dirty(&env->tlb_table[2][i]); | |
1617 | #if (NB_MMU_MODES == 4) | |
1618 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1619 | tlb_update_dirty(&env->tlb_table[3][i]); | |
1620 | #endif | |
1621 | #endif | |
3a7d929e FB |
1622 | } |
1623 | ||
5fafdf24 | 1624 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, |
108c49b8 | 1625 | unsigned long start) |
1ccde1cb FB |
1626 | { |
1627 | unsigned long addr; | |
84b7b8e7 FB |
1628 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_NOTDIRTY) { |
1629 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1630 | if (addr == start) { |
84b7b8e7 | 1631 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_RAM; |
1ccde1cb FB |
1632 | } |
1633 | } | |
1634 | } | |
1635 | ||
1636 | /* update the TLB corresponding to virtual page vaddr and phys addr | |
1637 | addr so that it is no longer dirty */ | |
6a00d601 FB |
1638 | static inline void tlb_set_dirty(CPUState *env, |
1639 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb | 1640 | { |
1ccde1cb FB |
1641 | int i; |
1642 | ||
1ccde1cb FB |
1643 | addr &= TARGET_PAGE_MASK; |
1644 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
84b7b8e7 FB |
1645 | tlb_set_dirty1(&env->tlb_table[0][i], addr); |
1646 | tlb_set_dirty1(&env->tlb_table[1][i], addr); | |
6fa4cea9 JM |
1647 | #if (NB_MMU_MODES >= 3) |
1648 | tlb_set_dirty1(&env->tlb_table[2][i], addr); | |
1649 | #if (NB_MMU_MODES == 4) | |
1650 | tlb_set_dirty1(&env->tlb_table[3][i], addr); | |
1651 | #endif | |
1652 | #endif | |
9fa3e853 FB |
1653 | } |
1654 | ||
59817ccb FB |
1655 | /* add a new TLB entry. At most one entry for a given virtual address |
1656 | is permitted. Return 0 if OK or 2 if the page could not be mapped | |
1657 | (can only happen in non SOFTMMU mode for I/O pages or pages | |
1658 | conflicting with the host address space). */ | |
5fafdf24 TS |
1659 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
1660 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 1661 | int mmu_idx, int is_softmmu) |
9fa3e853 | 1662 | { |
92e873b9 | 1663 | PhysPageDesc *p; |
4f2ac237 | 1664 | unsigned long pd; |
9fa3e853 | 1665 | unsigned int index; |
4f2ac237 | 1666 | target_ulong address; |
108c49b8 | 1667 | target_phys_addr_t addend; |
9fa3e853 | 1668 | int ret; |
84b7b8e7 | 1669 | CPUTLBEntry *te; |
6658ffb8 | 1670 | int i; |
9fa3e853 | 1671 | |
92e873b9 | 1672 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1673 | if (!p) { |
1674 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
1675 | } else { |
1676 | pd = p->phys_offset; | |
9fa3e853 FB |
1677 | } |
1678 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
1679 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
1680 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
1681 | #endif |
1682 | ||
1683 | ret = 0; | |
1684 | #if !defined(CONFIG_SOFTMMU) | |
5fafdf24 | 1685 | if (is_softmmu) |
9fa3e853 FB |
1686 | #endif |
1687 | { | |
2a4188a3 | 1688 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
9fa3e853 FB |
1689 | /* IO memory case */ |
1690 | address = vaddr | pd; | |
1691 | addend = paddr; | |
1692 | } else { | |
1693 | /* standard memory */ | |
1694 | address = vaddr; | |
1695 | addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK); | |
1696 | } | |
6658ffb8 PB |
1697 | |
1698 | /* Make accesses to pages with watchpoints go via the | |
1699 | watchpoint trap routines. */ | |
1700 | for (i = 0; i < env->nb_watchpoints; i++) { | |
1701 | if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) { | |
1702 | if (address & ~TARGET_PAGE_MASK) { | |
d79acba4 | 1703 | env->watchpoint[i].addend = 0; |
6658ffb8 PB |
1704 | address = vaddr | io_mem_watch; |
1705 | } else { | |
d79acba4 AZ |
1706 | env->watchpoint[i].addend = pd - paddr + |
1707 | (unsigned long) phys_ram_base; | |
6658ffb8 PB |
1708 | /* TODO: Figure out how to make read watchpoints coexist |
1709 | with code. */ | |
1710 | pd = (pd & TARGET_PAGE_MASK) | io_mem_watch | IO_MEM_ROMD; | |
1711 | } | |
1712 | } | |
1713 | } | |
d79acba4 | 1714 | |
90f18422 | 1715 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
9fa3e853 | 1716 | addend -= vaddr; |
6ebbf390 | 1717 | te = &env->tlb_table[mmu_idx][index]; |
84b7b8e7 | 1718 | te->addend = addend; |
67b915a5 | 1719 | if (prot & PAGE_READ) { |
84b7b8e7 FB |
1720 | te->addr_read = address; |
1721 | } else { | |
1722 | te->addr_read = -1; | |
1723 | } | |
5c751e99 EI |
1724 | |
1725 | if (te->addr_code != -1) { | |
1726 | tlb_flush_jmp_cache(env, te->addr_code); | |
1727 | } | |
84b7b8e7 FB |
1728 | if (prot & PAGE_EXEC) { |
1729 | te->addr_code = address; | |
9fa3e853 | 1730 | } else { |
84b7b8e7 | 1731 | te->addr_code = -1; |
9fa3e853 | 1732 | } |
67b915a5 | 1733 | if (prot & PAGE_WRITE) { |
5fafdf24 | 1734 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || |
856074ec FB |
1735 | (pd & IO_MEM_ROMD)) { |
1736 | /* write access calls the I/O callback */ | |
5fafdf24 | 1737 | te->addr_write = vaddr | |
856074ec | 1738 | (pd & ~(TARGET_PAGE_MASK | IO_MEM_ROMD)); |
5fafdf24 | 1739 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && |
1ccde1cb | 1740 | !cpu_physical_memory_is_dirty(pd)) { |
84b7b8e7 | 1741 | te->addr_write = vaddr | IO_MEM_NOTDIRTY; |
9fa3e853 | 1742 | } else { |
84b7b8e7 | 1743 | te->addr_write = address; |
9fa3e853 FB |
1744 | } |
1745 | } else { | |
84b7b8e7 | 1746 | te->addr_write = -1; |
9fa3e853 FB |
1747 | } |
1748 | } | |
1749 | #if !defined(CONFIG_SOFTMMU) | |
1750 | else { | |
1751 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM) { | |
1752 | /* IO access: no mapping is done as it will be handled by the | |
1753 | soft MMU */ | |
1754 | if (!(env->hflags & HF_SOFTMMU_MASK)) | |
1755 | ret = 2; | |
1756 | } else { | |
1757 | void *map_addr; | |
59817ccb FB |
1758 | |
1759 | if (vaddr >= MMAP_AREA_END) { | |
1760 | ret = 2; | |
1761 | } else { | |
1762 | if (prot & PROT_WRITE) { | |
5fafdf24 | 1763 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || |
d720b93d | 1764 | #if defined(TARGET_HAS_SMC) || 1 |
59817ccb | 1765 | first_tb || |
d720b93d | 1766 | #endif |
5fafdf24 | 1767 | ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && |
59817ccb FB |
1768 | !cpu_physical_memory_is_dirty(pd))) { |
1769 | /* ROM: we do as if code was inside */ | |
1770 | /* if code is present, we only map as read only and save the | |
1771 | original mapping */ | |
1772 | VirtPageDesc *vp; | |
3b46e624 | 1773 | |
90f18422 | 1774 | vp = virt_page_find_alloc(vaddr >> TARGET_PAGE_BITS, 1); |
59817ccb FB |
1775 | vp->phys_addr = pd; |
1776 | vp->prot = prot; | |
1777 | vp->valid_tag = virt_valid_tag; | |
1778 | prot &= ~PAGE_WRITE; | |
1779 | } | |
1780 | } | |
5fafdf24 | 1781 | map_addr = mmap((void *)vaddr, TARGET_PAGE_SIZE, prot, |
59817ccb FB |
1782 | MAP_SHARED | MAP_FIXED, phys_ram_fd, (pd & TARGET_PAGE_MASK)); |
1783 | if (map_addr == MAP_FAILED) { | |
1784 | cpu_abort(env, "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n", | |
1785 | paddr, vaddr); | |
9fa3e853 | 1786 | } |
9fa3e853 FB |
1787 | } |
1788 | } | |
1789 | } | |
1790 | #endif | |
1791 | return ret; | |
1792 | } | |
1793 | ||
1794 | /* called from signal handler: invalidate the code and unprotect the | |
1795 | page. Return TRUE if the fault was succesfully handled. */ | |
53a5960a | 1796 | int page_unprotect(target_ulong addr, unsigned long pc, void *puc) |
9fa3e853 FB |
1797 | { |
1798 | #if !defined(CONFIG_SOFTMMU) | |
1799 | VirtPageDesc *vp; | |
1800 | ||
1801 | #if defined(DEBUG_TLB) | |
1802 | printf("page_unprotect: addr=0x%08x\n", addr); | |
1803 | #endif | |
1804 | addr &= TARGET_PAGE_MASK; | |
59817ccb FB |
1805 | |
1806 | /* if it is not mapped, no need to worry here */ | |
1807 | if (addr >= MMAP_AREA_END) | |
1808 | return 0; | |
9fa3e853 FB |
1809 | vp = virt_page_find(addr >> TARGET_PAGE_BITS); |
1810 | if (!vp) | |
1811 | return 0; | |
1812 | /* NOTE: in this case, validate_tag is _not_ tested as it | |
1813 | validates only the code TLB */ | |
1814 | if (vp->valid_tag != virt_valid_tag) | |
1815 | return 0; | |
1816 | if (!(vp->prot & PAGE_WRITE)) | |
1817 | return 0; | |
1818 | #if defined(DEBUG_TLB) | |
5fafdf24 | 1819 | printf("page_unprotect: addr=0x%08x phys_addr=0x%08x prot=%x\n", |
9fa3e853 FB |
1820 | addr, vp->phys_addr, vp->prot); |
1821 | #endif | |
59817ccb FB |
1822 | if (mprotect((void *)addr, TARGET_PAGE_SIZE, vp->prot) < 0) |
1823 | cpu_abort(cpu_single_env, "error mprotect addr=0x%lx prot=%d\n", | |
1824 | (unsigned long)addr, vp->prot); | |
d720b93d | 1825 | /* set the dirty bit */ |
0a962c02 | 1826 | phys_ram_dirty[vp->phys_addr >> TARGET_PAGE_BITS] = 0xff; |
d720b93d FB |
1827 | /* flush the code inside */ |
1828 | tb_invalidate_phys_page(vp->phys_addr, pc, puc); | |
9fa3e853 FB |
1829 | return 1; |
1830 | #else | |
1831 | return 0; | |
1832 | #endif | |
33417e70 FB |
1833 | } |
1834 | ||
0124311e FB |
1835 | #else |
1836 | ||
ee8b7021 | 1837 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
1838 | { |
1839 | } | |
1840 | ||
2e12669a | 1841 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
1842 | { |
1843 | } | |
1844 | ||
5fafdf24 TS |
1845 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
1846 | target_phys_addr_t paddr, int prot, | |
6ebbf390 | 1847 | int mmu_idx, int is_softmmu) |
9fa3e853 FB |
1848 | { |
1849 | return 0; | |
1850 | } | |
0124311e | 1851 | |
9fa3e853 FB |
1852 | /* dump memory mappings */ |
1853 | void page_dump(FILE *f) | |
33417e70 | 1854 | { |
9fa3e853 FB |
1855 | unsigned long start, end; |
1856 | int i, j, prot, prot1; | |
1857 | PageDesc *p; | |
33417e70 | 1858 | |
9fa3e853 FB |
1859 | fprintf(f, "%-8s %-8s %-8s %s\n", |
1860 | "start", "end", "size", "prot"); | |
1861 | start = -1; | |
1862 | end = -1; | |
1863 | prot = 0; | |
1864 | for(i = 0; i <= L1_SIZE; i++) { | |
1865 | if (i < L1_SIZE) | |
1866 | p = l1_map[i]; | |
1867 | else | |
1868 | p = NULL; | |
1869 | for(j = 0;j < L2_SIZE; j++) { | |
1870 | if (!p) | |
1871 | prot1 = 0; | |
1872 | else | |
1873 | prot1 = p[j].flags; | |
1874 | if (prot1 != prot) { | |
1875 | end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS); | |
1876 | if (start != -1) { | |
1877 | fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", | |
5fafdf24 | 1878 | start, end, end - start, |
9fa3e853 FB |
1879 | prot & PAGE_READ ? 'r' : '-', |
1880 | prot & PAGE_WRITE ? 'w' : '-', | |
1881 | prot & PAGE_EXEC ? 'x' : '-'); | |
1882 | } | |
1883 | if (prot1 != 0) | |
1884 | start = end; | |
1885 | else | |
1886 | start = -1; | |
1887 | prot = prot1; | |
1888 | } | |
1889 | if (!p) | |
1890 | break; | |
1891 | } | |
33417e70 | 1892 | } |
33417e70 FB |
1893 | } |
1894 | ||
53a5960a | 1895 | int page_get_flags(target_ulong address) |
33417e70 | 1896 | { |
9fa3e853 FB |
1897 | PageDesc *p; |
1898 | ||
1899 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 1900 | if (!p) |
9fa3e853 FB |
1901 | return 0; |
1902 | return p->flags; | |
1903 | } | |
1904 | ||
1905 | /* modify the flags of a page and invalidate the code if | |
1906 | necessary. The flag PAGE_WRITE_ORG is positionned automatically | |
1907 | depending on PAGE_WRITE */ | |
53a5960a | 1908 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 FB |
1909 | { |
1910 | PageDesc *p; | |
53a5960a | 1911 | target_ulong addr; |
9fa3e853 FB |
1912 | |
1913 | start = start & TARGET_PAGE_MASK; | |
1914 | end = TARGET_PAGE_ALIGN(end); | |
1915 | if (flags & PAGE_WRITE) | |
1916 | flags |= PAGE_WRITE_ORG; | |
1917 | spin_lock(&tb_lock); | |
1918 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { | |
1919 | p = page_find_alloc(addr >> TARGET_PAGE_BITS); | |
1920 | /* if the write protection is set, then we invalidate the code | |
1921 | inside */ | |
5fafdf24 | 1922 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
1923 | (flags & PAGE_WRITE) && |
1924 | p->first_tb) { | |
d720b93d | 1925 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
1926 | } |
1927 | p->flags = flags; | |
1928 | } | |
1929 | spin_unlock(&tb_lock); | |
33417e70 FB |
1930 | } |
1931 | ||
3d97b40b TS |
1932 | int page_check_range(target_ulong start, target_ulong len, int flags) |
1933 | { | |
1934 | PageDesc *p; | |
1935 | target_ulong end; | |
1936 | target_ulong addr; | |
1937 | ||
1938 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ | |
1939 | start = start & TARGET_PAGE_MASK; | |
1940 | ||
1941 | if( end < start ) | |
1942 | /* we've wrapped around */ | |
1943 | return -1; | |
1944 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { | |
1945 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1946 | if( !p ) | |
1947 | return -1; | |
1948 | if( !(p->flags & PAGE_VALID) ) | |
1949 | return -1; | |
1950 | ||
dae3270c | 1951 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 1952 | return -1; |
dae3270c FB |
1953 | if (flags & PAGE_WRITE) { |
1954 | if (!(p->flags & PAGE_WRITE_ORG)) | |
1955 | return -1; | |
1956 | /* unprotect the page if it was put read-only because it | |
1957 | contains translated code */ | |
1958 | if (!(p->flags & PAGE_WRITE)) { | |
1959 | if (!page_unprotect(addr, 0, NULL)) | |
1960 | return -1; | |
1961 | } | |
1962 | return 0; | |
1963 | } | |
3d97b40b TS |
1964 | } |
1965 | return 0; | |
1966 | } | |
1967 | ||
9fa3e853 FB |
1968 | /* called from signal handler: invalidate the code and unprotect the |
1969 | page. Return TRUE if the fault was succesfully handled. */ | |
53a5960a | 1970 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 FB |
1971 | { |
1972 | unsigned int page_index, prot, pindex; | |
1973 | PageDesc *p, *p1; | |
53a5960a | 1974 | target_ulong host_start, host_end, addr; |
9fa3e853 | 1975 | |
83fb7adf | 1976 | host_start = address & qemu_host_page_mask; |
9fa3e853 FB |
1977 | page_index = host_start >> TARGET_PAGE_BITS; |
1978 | p1 = page_find(page_index); | |
1979 | if (!p1) | |
1980 | return 0; | |
83fb7adf | 1981 | host_end = host_start + qemu_host_page_size; |
9fa3e853 FB |
1982 | p = p1; |
1983 | prot = 0; | |
1984 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { | |
1985 | prot |= p->flags; | |
1986 | p++; | |
1987 | } | |
1988 | /* if the page was really writable, then we change its | |
1989 | protection back to writable */ | |
1990 | if (prot & PAGE_WRITE_ORG) { | |
1991 | pindex = (address - host_start) >> TARGET_PAGE_BITS; | |
1992 | if (!(p1[pindex].flags & PAGE_WRITE)) { | |
5fafdf24 | 1993 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
9fa3e853 FB |
1994 | (prot & PAGE_BITS) | PAGE_WRITE); |
1995 | p1[pindex].flags |= PAGE_WRITE; | |
1996 | /* and since the content will be modified, we must invalidate | |
1997 | the corresponding translated code. */ | |
d720b93d | 1998 | tb_invalidate_phys_page(address, pc, puc); |
9fa3e853 FB |
1999 | #ifdef DEBUG_TB_CHECK |
2000 | tb_invalidate_check(address); | |
2001 | #endif | |
2002 | return 1; | |
2003 | } | |
2004 | } | |
2005 | return 0; | |
2006 | } | |
2007 | ||
6a00d601 FB |
2008 | static inline void tlb_set_dirty(CPUState *env, |
2009 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2010 | { |
2011 | } | |
9fa3e853 FB |
2012 | #endif /* defined(CONFIG_USER_ONLY) */ |
2013 | ||
db7b5426 | 2014 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
00f82b8a AJ |
2015 | ram_addr_t memory); |
2016 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
2017 | ram_addr_t orig_memory); | |
db7b5426 BS |
2018 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2019 | need_subpage) \ | |
2020 | do { \ | |
2021 | if (addr > start_addr) \ | |
2022 | start_addr2 = 0; \ | |
2023 | else { \ | |
2024 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2025 | if (start_addr2 > 0) \ | |
2026 | need_subpage = 1; \ | |
2027 | } \ | |
2028 | \ | |
49e9fba2 | 2029 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2030 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2031 | else { \ | |
2032 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2033 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2034 | need_subpage = 1; \ | |
2035 | } \ | |
2036 | } while (0) | |
2037 | ||
33417e70 FB |
2038 | /* register physical memory. 'size' must be a multiple of the target |
2039 | page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
2040 | io memory page */ | |
5fafdf24 | 2041 | void cpu_register_physical_memory(target_phys_addr_t start_addr, |
00f82b8a AJ |
2042 | ram_addr_t size, |
2043 | ram_addr_t phys_offset) | |
33417e70 | 2044 | { |
108c49b8 | 2045 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2046 | PhysPageDesc *p; |
9d42037b | 2047 | CPUState *env; |
00f82b8a | 2048 | ram_addr_t orig_size = size; |
db7b5426 | 2049 | void *subpage; |
33417e70 | 2050 | |
5fd386f6 | 2051 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
49e9fba2 BS |
2052 | end_addr = start_addr + (target_phys_addr_t)size; |
2053 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { | |
db7b5426 BS |
2054 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2055 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
00f82b8a | 2056 | ram_addr_t orig_memory = p->phys_offset; |
db7b5426 BS |
2057 | target_phys_addr_t start_addr2, end_addr2; |
2058 | int need_subpage = 0; | |
2059 | ||
2060 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2061 | need_subpage); | |
4254fab8 | 2062 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2063 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2064 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
2065 | &p->phys_offset, orig_memory); | |
2066 | } else { | |
2067 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2068 | >> IO_MEM_SHIFT]; | |
2069 | } | |
2070 | subpage_register(subpage, start_addr2, end_addr2, phys_offset); | |
2071 | } else { | |
2072 | p->phys_offset = phys_offset; | |
2073 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2074 | (phys_offset & IO_MEM_ROMD)) | |
2075 | phys_offset += TARGET_PAGE_SIZE; | |
2076 | } | |
2077 | } else { | |
2078 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2079 | p->phys_offset = phys_offset; | |
2080 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2081 | (phys_offset & IO_MEM_ROMD)) | |
2082 | phys_offset += TARGET_PAGE_SIZE; | |
2083 | else { | |
2084 | target_phys_addr_t start_addr2, end_addr2; | |
2085 | int need_subpage = 0; | |
2086 | ||
2087 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2088 | end_addr2, need_subpage); | |
2089 | ||
4254fab8 | 2090 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2091 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
2092 | &p->phys_offset, IO_MEM_UNASSIGNED); | |
2093 | subpage_register(subpage, start_addr2, end_addr2, | |
2094 | phys_offset); | |
2095 | } | |
2096 | } | |
2097 | } | |
33417e70 | 2098 | } |
3b46e624 | 2099 | |
9d42037b FB |
2100 | /* since each CPU stores ram addresses in its TLB cache, we must |
2101 | reset the modified entries */ | |
2102 | /* XXX: slow ! */ | |
2103 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2104 | tlb_flush(env, 1); | |
2105 | } | |
33417e70 FB |
2106 | } |
2107 | ||
ba863458 | 2108 | /* XXX: temporary until new memory mapping API */ |
00f82b8a | 2109 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2110 | { |
2111 | PhysPageDesc *p; | |
2112 | ||
2113 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2114 | if (!p) | |
2115 | return IO_MEM_UNASSIGNED; | |
2116 | return p->phys_offset; | |
2117 | } | |
2118 | ||
e9a1ab19 | 2119 | /* XXX: better than nothing */ |
00f82b8a | 2120 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
e9a1ab19 FB |
2121 | { |
2122 | ram_addr_t addr; | |
7fb4fdcf | 2123 | if ((phys_ram_alloc_offset + size) > phys_ram_size) { |
00f82b8a | 2124 | fprintf(stderr, "Not enough memory (requested_size = %lu, max memory = %ld)\n", |
03875444 | 2125 | size, phys_ram_size); |
e9a1ab19 FB |
2126 | abort(); |
2127 | } | |
2128 | addr = phys_ram_alloc_offset; | |
2129 | phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size); | |
2130 | return addr; | |
2131 | } | |
2132 | ||
2133 | void qemu_ram_free(ram_addr_t addr) | |
2134 | { | |
2135 | } | |
2136 | ||
a4193c8a | 2137 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2138 | { |
67d3b957 | 2139 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2140 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 BS |
2141 | #endif |
2142 | #ifdef TARGET_SPARC | |
6c36d3fa | 2143 | do_unassigned_access(addr, 0, 0, 0); |
f1ccf904 TS |
2144 | #elif TARGET_CRIS |
2145 | do_unassigned_access(addr, 0, 0, 0); | |
67d3b957 | 2146 | #endif |
33417e70 FB |
2147 | return 0; |
2148 | } | |
2149 | ||
a4193c8a | 2150 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2151 | { |
67d3b957 | 2152 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2153 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2154 | #endif |
b4f0a316 | 2155 | #ifdef TARGET_SPARC |
6c36d3fa | 2156 | do_unassigned_access(addr, 1, 0, 0); |
f1ccf904 TS |
2157 | #elif TARGET_CRIS |
2158 | do_unassigned_access(addr, 1, 0, 0); | |
b4f0a316 | 2159 | #endif |
33417e70 FB |
2160 | } |
2161 | ||
2162 | static CPUReadMemoryFunc *unassigned_mem_read[3] = { | |
2163 | unassigned_mem_readb, | |
2164 | unassigned_mem_readb, | |
2165 | unassigned_mem_readb, | |
2166 | }; | |
2167 | ||
2168 | static CPUWriteMemoryFunc *unassigned_mem_write[3] = { | |
2169 | unassigned_mem_writeb, | |
2170 | unassigned_mem_writeb, | |
2171 | unassigned_mem_writeb, | |
2172 | }; | |
2173 | ||
3a7d929e | 2174 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
9fa3e853 | 2175 | { |
3a7d929e FB |
2176 | unsigned long ram_addr; |
2177 | int dirty_flags; | |
2178 | ram_addr = addr - (unsigned long)phys_ram_base; | |
2179 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
2180 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2181 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2182 | tb_invalidate_phys_page_fast(ram_addr, 1); |
2183 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2184 | #endif |
3a7d929e | 2185 | } |
c27004ec | 2186 | stb_p((uint8_t *)(long)addr, val); |
f32fc648 FB |
2187 | #ifdef USE_KQEMU |
2188 | if (cpu_single_env->kqemu_enabled && | |
2189 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2190 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2191 | #endif | |
f23db169 FB |
2192 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2193 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2194 | /* we remove the notdirty callback only if the code has been | |
2195 | flushed */ | |
2196 | if (dirty_flags == 0xff) | |
6a00d601 | 2197 | tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr); |
9fa3e853 FB |
2198 | } |
2199 | ||
3a7d929e | 2200 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
9fa3e853 | 2201 | { |
3a7d929e FB |
2202 | unsigned long ram_addr; |
2203 | int dirty_flags; | |
2204 | ram_addr = addr - (unsigned long)phys_ram_base; | |
2205 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
2206 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2207 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2208 | tb_invalidate_phys_page_fast(ram_addr, 2); |
2209 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2210 | #endif |
3a7d929e | 2211 | } |
c27004ec | 2212 | stw_p((uint8_t *)(long)addr, val); |
f32fc648 FB |
2213 | #ifdef USE_KQEMU |
2214 | if (cpu_single_env->kqemu_enabled && | |
2215 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2216 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2217 | #endif | |
f23db169 FB |
2218 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2219 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2220 | /* we remove the notdirty callback only if the code has been | |
2221 | flushed */ | |
2222 | if (dirty_flags == 0xff) | |
6a00d601 | 2223 | tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr); |
9fa3e853 FB |
2224 | } |
2225 | ||
3a7d929e | 2226 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
9fa3e853 | 2227 | { |
3a7d929e FB |
2228 | unsigned long ram_addr; |
2229 | int dirty_flags; | |
2230 | ram_addr = addr - (unsigned long)phys_ram_base; | |
2231 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
2232 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2233 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2234 | tb_invalidate_phys_page_fast(ram_addr, 4); |
2235 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2236 | #endif |
3a7d929e | 2237 | } |
c27004ec | 2238 | stl_p((uint8_t *)(long)addr, val); |
f32fc648 FB |
2239 | #ifdef USE_KQEMU |
2240 | if (cpu_single_env->kqemu_enabled && | |
2241 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) | |
2242 | kqemu_modify_page(cpu_single_env, ram_addr); | |
2243 | #endif | |
f23db169 FB |
2244 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2245 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2246 | /* we remove the notdirty callback only if the code has been | |
2247 | flushed */ | |
2248 | if (dirty_flags == 0xff) | |
6a00d601 | 2249 | tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr); |
9fa3e853 FB |
2250 | } |
2251 | ||
3a7d929e | 2252 | static CPUReadMemoryFunc *error_mem_read[3] = { |
9fa3e853 FB |
2253 | NULL, /* never used */ |
2254 | NULL, /* never used */ | |
2255 | NULL, /* never used */ | |
2256 | }; | |
2257 | ||
1ccde1cb FB |
2258 | static CPUWriteMemoryFunc *notdirty_mem_write[3] = { |
2259 | notdirty_mem_writeb, | |
2260 | notdirty_mem_writew, | |
2261 | notdirty_mem_writel, | |
2262 | }; | |
2263 | ||
6658ffb8 PB |
2264 | #if defined(CONFIG_SOFTMMU) |
2265 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, | |
2266 | so these check for a hit then pass through to the normal out-of-line | |
2267 | phys routines. */ | |
2268 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) | |
2269 | { | |
2270 | return ldub_phys(addr); | |
2271 | } | |
2272 | ||
2273 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) | |
2274 | { | |
2275 | return lduw_phys(addr); | |
2276 | } | |
2277 | ||
2278 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) | |
2279 | { | |
2280 | return ldl_phys(addr); | |
2281 | } | |
2282 | ||
2283 | /* Generate a debug exception if a watchpoint has been hit. | |
2284 | Returns the real physical address of the access. addr will be a host | |
d79acba4 | 2285 | address in case of a RAM location. */ |
6658ffb8 PB |
2286 | static target_ulong check_watchpoint(target_phys_addr_t addr) |
2287 | { | |
2288 | CPUState *env = cpu_single_env; | |
2289 | target_ulong watch; | |
2290 | target_ulong retaddr; | |
2291 | int i; | |
2292 | ||
2293 | retaddr = addr; | |
2294 | for (i = 0; i < env->nb_watchpoints; i++) { | |
2295 | watch = env->watchpoint[i].vaddr; | |
2296 | if (((env->mem_write_vaddr ^ watch) & TARGET_PAGE_MASK) == 0) { | |
d79acba4 | 2297 | retaddr = addr - env->watchpoint[i].addend; |
6658ffb8 PB |
2298 | if (((addr ^ watch) & ~TARGET_PAGE_MASK) == 0) { |
2299 | cpu_single_env->watchpoint_hit = i + 1; | |
2300 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_DEBUG); | |
2301 | break; | |
2302 | } | |
2303 | } | |
2304 | } | |
2305 | return retaddr; | |
2306 | } | |
2307 | ||
2308 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, | |
2309 | uint32_t val) | |
2310 | { | |
2311 | addr = check_watchpoint(addr); | |
2312 | stb_phys(addr, val); | |
2313 | } | |
2314 | ||
2315 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, | |
2316 | uint32_t val) | |
2317 | { | |
2318 | addr = check_watchpoint(addr); | |
2319 | stw_phys(addr, val); | |
2320 | } | |
2321 | ||
2322 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, | |
2323 | uint32_t val) | |
2324 | { | |
2325 | addr = check_watchpoint(addr); | |
2326 | stl_phys(addr, val); | |
2327 | } | |
2328 | ||
2329 | static CPUReadMemoryFunc *watch_mem_read[3] = { | |
2330 | watch_mem_readb, | |
2331 | watch_mem_readw, | |
2332 | watch_mem_readl, | |
2333 | }; | |
2334 | ||
2335 | static CPUWriteMemoryFunc *watch_mem_write[3] = { | |
2336 | watch_mem_writeb, | |
2337 | watch_mem_writew, | |
2338 | watch_mem_writel, | |
2339 | }; | |
2340 | #endif | |
2341 | ||
db7b5426 BS |
2342 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
2343 | unsigned int len) | |
2344 | { | |
db7b5426 BS |
2345 | uint32_t ret; |
2346 | unsigned int idx; | |
2347 | ||
2348 | idx = SUBPAGE_IDX(addr - mmio->base); | |
2349 | #if defined(DEBUG_SUBPAGE) | |
2350 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
2351 | mmio, len, addr, idx); | |
2352 | #endif | |
3ee89922 | 2353 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr); |
db7b5426 BS |
2354 | |
2355 | return ret; | |
2356 | } | |
2357 | ||
2358 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, | |
2359 | uint32_t value, unsigned int len) | |
2360 | { | |
db7b5426 BS |
2361 | unsigned int idx; |
2362 | ||
2363 | idx = SUBPAGE_IDX(addr - mmio->base); | |
2364 | #if defined(DEBUG_SUBPAGE) | |
2365 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, | |
2366 | mmio, len, addr, idx, value); | |
2367 | #endif | |
3ee89922 | 2368 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value); |
db7b5426 BS |
2369 | } |
2370 | ||
2371 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) | |
2372 | { | |
2373 | #if defined(DEBUG_SUBPAGE) | |
2374 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2375 | #endif | |
2376 | ||
2377 | return subpage_readlen(opaque, addr, 0); | |
2378 | } | |
2379 | ||
2380 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, | |
2381 | uint32_t value) | |
2382 | { | |
2383 | #if defined(DEBUG_SUBPAGE) | |
2384 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2385 | #endif | |
2386 | subpage_writelen(opaque, addr, value, 0); | |
2387 | } | |
2388 | ||
2389 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) | |
2390 | { | |
2391 | #if defined(DEBUG_SUBPAGE) | |
2392 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2393 | #endif | |
2394 | ||
2395 | return subpage_readlen(opaque, addr, 1); | |
2396 | } | |
2397 | ||
2398 | static void subpage_writew (void *opaque, target_phys_addr_t addr, | |
2399 | uint32_t value) | |
2400 | { | |
2401 | #if defined(DEBUG_SUBPAGE) | |
2402 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2403 | #endif | |
2404 | subpage_writelen(opaque, addr, value, 1); | |
2405 | } | |
2406 | ||
2407 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) | |
2408 | { | |
2409 | #if defined(DEBUG_SUBPAGE) | |
2410 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2411 | #endif | |
2412 | ||
2413 | return subpage_readlen(opaque, addr, 2); | |
2414 | } | |
2415 | ||
2416 | static void subpage_writel (void *opaque, | |
2417 | target_phys_addr_t addr, uint32_t value) | |
2418 | { | |
2419 | #if defined(DEBUG_SUBPAGE) | |
2420 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2421 | #endif | |
2422 | subpage_writelen(opaque, addr, value, 2); | |
2423 | } | |
2424 | ||
2425 | static CPUReadMemoryFunc *subpage_read[] = { | |
2426 | &subpage_readb, | |
2427 | &subpage_readw, | |
2428 | &subpage_readl, | |
2429 | }; | |
2430 | ||
2431 | static CPUWriteMemoryFunc *subpage_write[] = { | |
2432 | &subpage_writeb, | |
2433 | &subpage_writew, | |
2434 | &subpage_writel, | |
2435 | }; | |
2436 | ||
2437 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
00f82b8a | 2438 | ram_addr_t memory) |
db7b5426 BS |
2439 | { |
2440 | int idx, eidx; | |
4254fab8 | 2441 | unsigned int i; |
db7b5426 BS |
2442 | |
2443 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2444 | return -1; | |
2445 | idx = SUBPAGE_IDX(start); | |
2446 | eidx = SUBPAGE_IDX(end); | |
2447 | #if defined(DEBUG_SUBPAGE) | |
2448 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__, | |
2449 | mmio, start, end, idx, eidx, memory); | |
2450 | #endif | |
2451 | memory >>= IO_MEM_SHIFT; | |
2452 | for (; idx <= eidx; idx++) { | |
4254fab8 | 2453 | for (i = 0; i < 4; i++) { |
3ee89922 BS |
2454 | if (io_mem_read[memory][i]) { |
2455 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; | |
2456 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; | |
2457 | } | |
2458 | if (io_mem_write[memory][i]) { | |
2459 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; | |
2460 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; | |
2461 | } | |
4254fab8 | 2462 | } |
db7b5426 BS |
2463 | } |
2464 | ||
2465 | return 0; | |
2466 | } | |
2467 | ||
00f82b8a AJ |
2468 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2469 | ram_addr_t orig_memory) | |
db7b5426 BS |
2470 | { |
2471 | subpage_t *mmio; | |
2472 | int subpage_memory; | |
2473 | ||
2474 | mmio = qemu_mallocz(sizeof(subpage_t)); | |
2475 | if (mmio != NULL) { | |
2476 | mmio->base = base; | |
2477 | subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio); | |
2478 | #if defined(DEBUG_SUBPAGE) | |
2479 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, | |
2480 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
2481 | #endif | |
2482 | *phys = subpage_memory | IO_MEM_SUBPAGE; | |
2483 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory); | |
2484 | } | |
2485 | ||
2486 | return mmio; | |
2487 | } | |
2488 | ||
33417e70 FB |
2489 | static void io_mem_init(void) |
2490 | { | |
3a7d929e | 2491 | cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL); |
a4193c8a | 2492 | cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL); |
3a7d929e | 2493 | cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL); |
1ccde1cb FB |
2494 | io_mem_nb = 5; |
2495 | ||
6658ffb8 PB |
2496 | #if defined(CONFIG_SOFTMMU) |
2497 | io_mem_watch = cpu_register_io_memory(-1, watch_mem_read, | |
2498 | watch_mem_write, NULL); | |
2499 | #endif | |
1ccde1cb | 2500 | /* alloc dirty bits array */ |
0a962c02 | 2501 | phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS); |
3a7d929e | 2502 | memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS); |
33417e70 FB |
2503 | } |
2504 | ||
2505 | /* mem_read and mem_write are arrays of functions containing the | |
2506 | function to access byte (index 0), word (index 1) and dword (index | |
3ee89922 BS |
2507 | 2). Functions can be omitted with a NULL function pointer. The |
2508 | registered functions may be modified dynamically later. | |
2509 | If io_index is non zero, the corresponding io zone is | |
4254fab8 BS |
2510 | modified. If it is zero, a new io zone is allocated. The return |
2511 | value can be used with cpu_register_physical_memory(). (-1) is | |
2512 | returned if error. */ | |
33417e70 FB |
2513 | int cpu_register_io_memory(int io_index, |
2514 | CPUReadMemoryFunc **mem_read, | |
a4193c8a FB |
2515 | CPUWriteMemoryFunc **mem_write, |
2516 | void *opaque) | |
33417e70 | 2517 | { |
4254fab8 | 2518 | int i, subwidth = 0; |
33417e70 FB |
2519 | |
2520 | if (io_index <= 0) { | |
b5ff1b31 | 2521 | if (io_mem_nb >= IO_MEM_NB_ENTRIES) |
33417e70 FB |
2522 | return -1; |
2523 | io_index = io_mem_nb++; | |
2524 | } else { | |
2525 | if (io_index >= IO_MEM_NB_ENTRIES) | |
2526 | return -1; | |
2527 | } | |
b5ff1b31 | 2528 | |
33417e70 | 2529 | for(i = 0;i < 3; i++) { |
4254fab8 BS |
2530 | if (!mem_read[i] || !mem_write[i]) |
2531 | subwidth = IO_MEM_SUBWIDTH; | |
33417e70 FB |
2532 | io_mem_read[io_index][i] = mem_read[i]; |
2533 | io_mem_write[io_index][i] = mem_write[i]; | |
2534 | } | |
a4193c8a | 2535 | io_mem_opaque[io_index] = opaque; |
4254fab8 | 2536 | return (io_index << IO_MEM_SHIFT) | subwidth; |
33417e70 | 2537 | } |
61382a50 | 2538 | |
8926b517 FB |
2539 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index) |
2540 | { | |
2541 | return io_mem_write[io_index >> IO_MEM_SHIFT]; | |
2542 | } | |
2543 | ||
2544 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index) | |
2545 | { | |
2546 | return io_mem_read[io_index >> IO_MEM_SHIFT]; | |
2547 | } | |
2548 | ||
13eb76e0 FB |
2549 | /* physical memory access (slow version, mainly for debug) */ |
2550 | #if defined(CONFIG_USER_ONLY) | |
5fafdf24 | 2551 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
2552 | int len, int is_write) |
2553 | { | |
2554 | int l, flags; | |
2555 | target_ulong page; | |
53a5960a | 2556 | void * p; |
13eb76e0 FB |
2557 | |
2558 | while (len > 0) { | |
2559 | page = addr & TARGET_PAGE_MASK; | |
2560 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2561 | if (l > len) | |
2562 | l = len; | |
2563 | flags = page_get_flags(page); | |
2564 | if (!(flags & PAGE_VALID)) | |
2565 | return; | |
2566 | if (is_write) { | |
2567 | if (!(flags & PAGE_WRITE)) | |
2568 | return; | |
579a97f7 | 2569 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2570 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
579a97f7 FB |
2571 | /* FIXME - should this return an error rather than just fail? */ |
2572 | return; | |
72fb7daa AJ |
2573 | memcpy(p, buf, l); |
2574 | unlock_user(p, addr, l); | |
13eb76e0 FB |
2575 | } else { |
2576 | if (!(flags & PAGE_READ)) | |
2577 | return; | |
579a97f7 | 2578 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2579 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
579a97f7 FB |
2580 | /* FIXME - should this return an error rather than just fail? */ |
2581 | return; | |
72fb7daa | 2582 | memcpy(buf, p, l); |
5b257578 | 2583 | unlock_user(p, addr, 0); |
13eb76e0 FB |
2584 | } |
2585 | len -= l; | |
2586 | buf += l; | |
2587 | addr += l; | |
2588 | } | |
2589 | } | |
8df1cd07 | 2590 | |
13eb76e0 | 2591 | #else |
5fafdf24 | 2592 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
2593 | int len, int is_write) |
2594 | { | |
2595 | int l, io_index; | |
2596 | uint8_t *ptr; | |
2597 | uint32_t val; | |
2e12669a FB |
2598 | target_phys_addr_t page; |
2599 | unsigned long pd; | |
92e873b9 | 2600 | PhysPageDesc *p; |
3b46e624 | 2601 | |
13eb76e0 FB |
2602 | while (len > 0) { |
2603 | page = addr & TARGET_PAGE_MASK; | |
2604 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2605 | if (l > len) | |
2606 | l = len; | |
92e873b9 | 2607 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
2608 | if (!p) { |
2609 | pd = IO_MEM_UNASSIGNED; | |
2610 | } else { | |
2611 | pd = p->phys_offset; | |
2612 | } | |
3b46e624 | 2613 | |
13eb76e0 | 2614 | if (is_write) { |
3a7d929e | 2615 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
13eb76e0 | 2616 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
6a00d601 FB |
2617 | /* XXX: could force cpu_single_env to NULL to avoid |
2618 | potential bugs */ | |
13eb76e0 | 2619 | if (l >= 4 && ((addr & 3) == 0)) { |
1c213d19 | 2620 | /* 32 bit write access */ |
c27004ec | 2621 | val = ldl_p(buf); |
a4193c8a | 2622 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
13eb76e0 FB |
2623 | l = 4; |
2624 | } else if (l >= 2 && ((addr & 1) == 0)) { | |
1c213d19 | 2625 | /* 16 bit write access */ |
c27004ec | 2626 | val = lduw_p(buf); |
a4193c8a | 2627 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
13eb76e0 FB |
2628 | l = 2; |
2629 | } else { | |
1c213d19 | 2630 | /* 8 bit write access */ |
c27004ec | 2631 | val = ldub_p(buf); |
a4193c8a | 2632 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val); |
13eb76e0 FB |
2633 | l = 1; |
2634 | } | |
2635 | } else { | |
b448f2f3 FB |
2636 | unsigned long addr1; |
2637 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 2638 | /* RAM case */ |
b448f2f3 | 2639 | ptr = phys_ram_base + addr1; |
13eb76e0 | 2640 | memcpy(ptr, buf, l); |
3a7d929e FB |
2641 | if (!cpu_physical_memory_is_dirty(addr1)) { |
2642 | /* invalidate code */ | |
2643 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
2644 | /* set dirty bit */ | |
5fafdf24 | 2645 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
f23db169 | 2646 | (0xff & ~CODE_DIRTY_FLAG); |
3a7d929e | 2647 | } |
13eb76e0 FB |
2648 | } |
2649 | } else { | |
5fafdf24 | 2650 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 2651 | !(pd & IO_MEM_ROMD)) { |
13eb76e0 FB |
2652 | /* I/O case */ |
2653 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2654 | if (l >= 4 && ((addr & 3) == 0)) { | |
2655 | /* 32 bit read access */ | |
a4193c8a | 2656 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
c27004ec | 2657 | stl_p(buf, val); |
13eb76e0 FB |
2658 | l = 4; |
2659 | } else if (l >= 2 && ((addr & 1) == 0)) { | |
2660 | /* 16 bit read access */ | |
a4193c8a | 2661 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
c27004ec | 2662 | stw_p(buf, val); |
13eb76e0 FB |
2663 | l = 2; |
2664 | } else { | |
1c213d19 | 2665 | /* 8 bit read access */ |
a4193c8a | 2666 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr); |
c27004ec | 2667 | stb_p(buf, val); |
13eb76e0 FB |
2668 | l = 1; |
2669 | } | |
2670 | } else { | |
2671 | /* RAM case */ | |
5fafdf24 | 2672 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
2673 | (addr & ~TARGET_PAGE_MASK); |
2674 | memcpy(buf, ptr, l); | |
2675 | } | |
2676 | } | |
2677 | len -= l; | |
2678 | buf += l; | |
2679 | addr += l; | |
2680 | } | |
2681 | } | |
8df1cd07 | 2682 | |
d0ecd2aa | 2683 | /* used for ROM loading : can write in RAM and ROM */ |
5fafdf24 | 2684 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
2685 | const uint8_t *buf, int len) |
2686 | { | |
2687 | int l; | |
2688 | uint8_t *ptr; | |
2689 | target_phys_addr_t page; | |
2690 | unsigned long pd; | |
2691 | PhysPageDesc *p; | |
3b46e624 | 2692 | |
d0ecd2aa FB |
2693 | while (len > 0) { |
2694 | page = addr & TARGET_PAGE_MASK; | |
2695 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2696 | if (l > len) | |
2697 | l = len; | |
2698 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
2699 | if (!p) { | |
2700 | pd = IO_MEM_UNASSIGNED; | |
2701 | } else { | |
2702 | pd = p->phys_offset; | |
2703 | } | |
3b46e624 | 2704 | |
d0ecd2aa | 2705 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
2706 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
2707 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
2708 | /* do nothing */ |
2709 | } else { | |
2710 | unsigned long addr1; | |
2711 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
2712 | /* ROM/RAM case */ | |
2713 | ptr = phys_ram_base + addr1; | |
2714 | memcpy(ptr, buf, l); | |
2715 | } | |
2716 | len -= l; | |
2717 | buf += l; | |
2718 | addr += l; | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | ||
8df1cd07 FB |
2723 | /* warning: addr must be aligned */ |
2724 | uint32_t ldl_phys(target_phys_addr_t addr) | |
2725 | { | |
2726 | int io_index; | |
2727 | uint8_t *ptr; | |
2728 | uint32_t val; | |
2729 | unsigned long pd; | |
2730 | PhysPageDesc *p; | |
2731 | ||
2732 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2733 | if (!p) { | |
2734 | pd = IO_MEM_UNASSIGNED; | |
2735 | } else { | |
2736 | pd = p->phys_offset; | |
2737 | } | |
3b46e624 | 2738 | |
5fafdf24 | 2739 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 2740 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
2741 | /* I/O case */ |
2742 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2743 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
2744 | } else { | |
2745 | /* RAM case */ | |
5fafdf24 | 2746 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
2747 | (addr & ~TARGET_PAGE_MASK); |
2748 | val = ldl_p(ptr); | |
2749 | } | |
2750 | return val; | |
2751 | } | |
2752 | ||
84b7b8e7 FB |
2753 | /* warning: addr must be aligned */ |
2754 | uint64_t ldq_phys(target_phys_addr_t addr) | |
2755 | { | |
2756 | int io_index; | |
2757 | uint8_t *ptr; | |
2758 | uint64_t val; | |
2759 | unsigned long pd; | |
2760 | PhysPageDesc *p; | |
2761 | ||
2762 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2763 | if (!p) { | |
2764 | pd = IO_MEM_UNASSIGNED; | |
2765 | } else { | |
2766 | pd = p->phys_offset; | |
2767 | } | |
3b46e624 | 2768 | |
2a4188a3 FB |
2769 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2770 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
2771 | /* I/O case */ |
2772 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2773 | #ifdef TARGET_WORDS_BIGENDIAN | |
2774 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
2775 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
2776 | #else | |
2777 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
2778 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
2779 | #endif | |
2780 | } else { | |
2781 | /* RAM case */ | |
5fafdf24 | 2782 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
2783 | (addr & ~TARGET_PAGE_MASK); |
2784 | val = ldq_p(ptr); | |
2785 | } | |
2786 | return val; | |
2787 | } | |
2788 | ||
aab33094 FB |
2789 | /* XXX: optimize */ |
2790 | uint32_t ldub_phys(target_phys_addr_t addr) | |
2791 | { | |
2792 | uint8_t val; | |
2793 | cpu_physical_memory_read(addr, &val, 1); | |
2794 | return val; | |
2795 | } | |
2796 | ||
2797 | /* XXX: optimize */ | |
2798 | uint32_t lduw_phys(target_phys_addr_t addr) | |
2799 | { | |
2800 | uint16_t val; | |
2801 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); | |
2802 | return tswap16(val); | |
2803 | } | |
2804 | ||
8df1cd07 FB |
2805 | /* warning: addr must be aligned. The ram page is not masked as dirty |
2806 | and the code inside is not invalidated. It is useful if the dirty | |
2807 | bits are used to track modified PTEs */ | |
2808 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) | |
2809 | { | |
2810 | int io_index; | |
2811 | uint8_t *ptr; | |
2812 | unsigned long pd; | |
2813 | PhysPageDesc *p; | |
2814 | ||
2815 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2816 | if (!p) { | |
2817 | pd = IO_MEM_UNASSIGNED; | |
2818 | } else { | |
2819 | pd = p->phys_offset; | |
2820 | } | |
3b46e624 | 2821 | |
3a7d929e | 2822 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 FB |
2823 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
2824 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
2825 | } else { | |
5fafdf24 | 2826 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
2827 | (addr & ~TARGET_PAGE_MASK); |
2828 | stl_p(ptr, val); | |
2829 | } | |
2830 | } | |
2831 | ||
bc98a7ef JM |
2832 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
2833 | { | |
2834 | int io_index; | |
2835 | uint8_t *ptr; | |
2836 | unsigned long pd; | |
2837 | PhysPageDesc *p; | |
2838 | ||
2839 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2840 | if (!p) { | |
2841 | pd = IO_MEM_UNASSIGNED; | |
2842 | } else { | |
2843 | pd = p->phys_offset; | |
2844 | } | |
3b46e624 | 2845 | |
bc98a7ef JM |
2846 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
2847 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
2848 | #ifdef TARGET_WORDS_BIGENDIAN | |
2849 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
2850 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
2851 | #else | |
2852 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
2853 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
2854 | #endif | |
2855 | } else { | |
5fafdf24 | 2856 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
2857 | (addr & ~TARGET_PAGE_MASK); |
2858 | stq_p(ptr, val); | |
2859 | } | |
2860 | } | |
2861 | ||
8df1cd07 | 2862 | /* warning: addr must be aligned */ |
8df1cd07 FB |
2863 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
2864 | { | |
2865 | int io_index; | |
2866 | uint8_t *ptr; | |
2867 | unsigned long pd; | |
2868 | PhysPageDesc *p; | |
2869 | ||
2870 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2871 | if (!p) { | |
2872 | pd = IO_MEM_UNASSIGNED; | |
2873 | } else { | |
2874 | pd = p->phys_offset; | |
2875 | } | |
3b46e624 | 2876 | |
3a7d929e | 2877 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 FB |
2878 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
2879 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
2880 | } else { | |
2881 | unsigned long addr1; | |
2882 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
2883 | /* RAM case */ | |
2884 | ptr = phys_ram_base + addr1; | |
2885 | stl_p(ptr, val); | |
3a7d929e FB |
2886 | if (!cpu_physical_memory_is_dirty(addr1)) { |
2887 | /* invalidate code */ | |
2888 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
2889 | /* set dirty bit */ | |
f23db169 FB |
2890 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
2891 | (0xff & ~CODE_DIRTY_FLAG); | |
3a7d929e | 2892 | } |
8df1cd07 FB |
2893 | } |
2894 | } | |
2895 | ||
aab33094 FB |
2896 | /* XXX: optimize */ |
2897 | void stb_phys(target_phys_addr_t addr, uint32_t val) | |
2898 | { | |
2899 | uint8_t v = val; | |
2900 | cpu_physical_memory_write(addr, &v, 1); | |
2901 | } | |
2902 | ||
2903 | /* XXX: optimize */ | |
2904 | void stw_phys(target_phys_addr_t addr, uint32_t val) | |
2905 | { | |
2906 | uint16_t v = tswap16(val); | |
2907 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); | |
2908 | } | |
2909 | ||
2910 | /* XXX: optimize */ | |
2911 | void stq_phys(target_phys_addr_t addr, uint64_t val) | |
2912 | { | |
2913 | val = tswap64(val); | |
2914 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
2915 | } | |
2916 | ||
13eb76e0 FB |
2917 | #endif |
2918 | ||
2919 | /* virtual memory access for debug */ | |
5fafdf24 | 2920 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 2921 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2922 | { |
2923 | int l; | |
9b3c35e0 JM |
2924 | target_phys_addr_t phys_addr; |
2925 | target_ulong page; | |
13eb76e0 FB |
2926 | |
2927 | while (len > 0) { | |
2928 | page = addr & TARGET_PAGE_MASK; | |
2929 | phys_addr = cpu_get_phys_page_debug(env, page); | |
2930 | /* if no physical page mapped, return an error */ | |
2931 | if (phys_addr == -1) | |
2932 | return -1; | |
2933 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2934 | if (l > len) | |
2935 | l = len; | |
5fafdf24 | 2936 | cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK), |
b448f2f3 | 2937 | buf, l, is_write); |
13eb76e0 FB |
2938 | len -= l; |
2939 | buf += l; | |
2940 | addr += l; | |
2941 | } | |
2942 | return 0; | |
2943 | } | |
2944 | ||
e3db7226 FB |
2945 | void dump_exec_info(FILE *f, |
2946 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
2947 | { | |
2948 | int i, target_code_size, max_target_code_size; | |
2949 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
2950 | TranslationBlock *tb; | |
3b46e624 | 2951 | |
e3db7226 FB |
2952 | target_code_size = 0; |
2953 | max_target_code_size = 0; | |
2954 | cross_page = 0; | |
2955 | direct_jmp_count = 0; | |
2956 | direct_jmp2_count = 0; | |
2957 | for(i = 0; i < nb_tbs; i++) { | |
2958 | tb = &tbs[i]; | |
2959 | target_code_size += tb->size; | |
2960 | if (tb->size > max_target_code_size) | |
2961 | max_target_code_size = tb->size; | |
2962 | if (tb->page_addr[1] != -1) | |
2963 | cross_page++; | |
2964 | if (tb->tb_next_offset[0] != 0xffff) { | |
2965 | direct_jmp_count++; | |
2966 | if (tb->tb_next_offset[1] != 0xffff) { | |
2967 | direct_jmp2_count++; | |
2968 | } | |
2969 | } | |
2970 | } | |
2971 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 2972 | cpu_fprintf(f, "Translation buffer state:\n"); |
e3db7226 | 2973 | cpu_fprintf(f, "TB count %d\n", nb_tbs); |
5fafdf24 | 2974 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
2975 | nb_tbs ? target_code_size / nb_tbs : 0, |
2976 | max_target_code_size); | |
5fafdf24 | 2977 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
2978 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
2979 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
2980 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
2981 | cross_page, | |
e3db7226 FB |
2982 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
2983 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 2984 | direct_jmp_count, |
e3db7226 FB |
2985 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
2986 | direct_jmp2_count, | |
2987 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 2988 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
2989 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
2990 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
2991 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
57fec1fe FB |
2992 | #ifdef CONFIG_PROFILER |
2993 | { | |
2994 | int64_t tot; | |
2995 | tot = dyngen_interm_time + dyngen_code_time; | |
2996 | cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n", | |
2997 | tot, tot / 2.4e9); | |
2998 | cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", | |
2999 | dyngen_tb_count, | |
3000 | dyngen_tb_count1 - dyngen_tb_count, | |
3001 | dyngen_tb_count1 ? (double)(dyngen_tb_count1 - dyngen_tb_count) / dyngen_tb_count1 * 100.0 : 0); | |
3002 | cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n", | |
3003 | dyngen_tb_count ? (double)dyngen_op_count / dyngen_tb_count : 0, dyngen_op_count_max); | |
3004 | cpu_fprintf(f, "old ops/total ops %0.1f%%\n", | |
3005 | dyngen_op_count ? (double)dyngen_old_op_count / dyngen_op_count * 100.0 : 0); | |
3006 | cpu_fprintf(f, "deleted ops/TB %0.2f\n", | |
3007 | dyngen_tb_count ? | |
3008 | (double)dyngen_tcg_del_op_count / dyngen_tb_count : 0); | |
3009 | cpu_fprintf(f, "cycles/op %0.1f\n", | |
3010 | dyngen_op_count ? (double)tot / dyngen_op_count : 0); | |
3011 | cpu_fprintf(f, "cycles/in byte %0.1f\n", | |
3012 | dyngen_code_in_len ? (double)tot / dyngen_code_in_len : 0); | |
3013 | cpu_fprintf(f, "cycles/out byte %0.1f\n", | |
3014 | dyngen_code_out_len ? (double)tot / dyngen_code_out_len : 0); | |
3015 | if (tot == 0) | |
3016 | tot = 1; | |
3017 | cpu_fprintf(f, " gen_interm time %0.1f%%\n", | |
3018 | (double)dyngen_interm_time / tot * 100.0); | |
3019 | cpu_fprintf(f, " gen_code time %0.1f%%\n", | |
3020 | (double)dyngen_code_time / tot * 100.0); | |
3021 | cpu_fprintf(f, "cpu_restore count %" PRId64 "\n", | |
3022 | dyngen_restore_count); | |
3023 | cpu_fprintf(f, " avg cycles %0.1f\n", | |
3024 | dyngen_restore_count ? (double)dyngen_restore_time / dyngen_restore_count : 0); | |
3025 | { | |
3026 | extern void dump_op_count(void); | |
3027 | dump_op_count(); | |
3028 | } | |
3029 | } | |
3030 | #endif | |
e3db7226 FB |
3031 | } |
3032 | ||
5fafdf24 | 3033 | #if !defined(CONFIG_USER_ONLY) |
61382a50 FB |
3034 | |
3035 | #define MMUSUFFIX _cmmu | |
3036 | #define GETPC() NULL | |
3037 | #define env cpu_single_env | |
b769d8fe | 3038 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
3039 | |
3040 | #define SHIFT 0 | |
3041 | #include "softmmu_template.h" | |
3042 | ||
3043 | #define SHIFT 1 | |
3044 | #include "softmmu_template.h" | |
3045 | ||
3046 | #define SHIFT 2 | |
3047 | #include "softmmu_template.h" | |
3048 | ||
3049 | #define SHIFT 3 | |
3050 | #include "softmmu_template.h" | |
3051 | ||
3052 | #undef env | |
3053 | ||
3054 | #endif |