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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 | 26 | |
055403b2 | 27 | #include "qemu-common.h" |
6180a181 | 28 | #include "cpu.h" |
b67d9a52 | 29 | #include "tcg.h" |
b3c7724c | 30 | #include "hw/hw.h" |
cc9e98cb | 31 | #include "hw/qdev.h" |
1de7afc9 | 32 | #include "qemu/osdep.h" |
9c17d615 | 33 | #include "sysemu/kvm.h" |
0d09e41a | 34 | #include "hw/xen/xen.h" |
1de7afc9 PB |
35 | #include "qemu/timer.h" |
36 | #include "qemu/config-file.h" | |
022c62cb | 37 | #include "exec/memory.h" |
9c17d615 | 38 | #include "sysemu/dma.h" |
022c62cb | 39 | #include "exec/address-spaces.h" |
53a5960a PB |
40 | #if defined(CONFIG_USER_ONLY) |
41 | #include <qemu.h> | |
432d268c | 42 | #else /* !CONFIG_USER_ONLY */ |
9c17d615 | 43 | #include "sysemu/xen-mapcache.h" |
6506e4f9 | 44 | #include "trace.h" |
53a5960a | 45 | #endif |
0d6d3c87 | 46 | #include "exec/cpu-all.h" |
54936004 | 47 | |
022c62cb | 48 | #include "exec/cputlb.h" |
5b6dd868 | 49 | #include "translate-all.h" |
0cac1b66 | 50 | |
022c62cb | 51 | #include "exec/memory-internal.h" |
67d95c15 | 52 | |
db7b5426 | 53 | //#define DEBUG_SUBPAGE |
1196be37 | 54 | |
e2eef170 | 55 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 56 | int phys_ram_fd; |
74576198 | 57 | static int in_migration; |
94a6b54f | 58 | |
a3161038 | 59 | RAMList ram_list = { .blocks = QTAILQ_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
60 | |
61 | static MemoryRegion *system_memory; | |
309cb471 | 62 | static MemoryRegion *system_io; |
62152b8a | 63 | |
f6790af6 AK |
64 | AddressSpace address_space_io; |
65 | AddressSpace address_space_memory; | |
2673a5da | 66 | |
0844e007 | 67 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 68 | static MemoryRegion io_mem_unassigned; |
0e0df1e2 | 69 | |
e2eef170 | 70 | #endif |
9fa3e853 | 71 | |
9349b4f9 | 72 | CPUArchState *first_cpu; |
6a00d601 FB |
73 | /* current CPU in the current thread. It is only valid inside |
74 | cpu_exec() */ | |
9349b4f9 | 75 | DEFINE_TLS(CPUArchState *,cpu_single_env); |
2e70f6ef | 76 | /* 0 = Do not count executed instructions. |
bf20dc07 | 77 | 1 = Precise instruction counting. |
2e70f6ef | 78 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 79 | int use_icount; |
6a00d601 | 80 | |
e2eef170 | 81 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 82 | |
1db8abb1 PB |
83 | typedef struct PhysPageEntry PhysPageEntry; |
84 | ||
85 | struct PhysPageEntry { | |
86 | uint16_t is_leaf : 1; | |
87 | /* index into phys_sections (is_leaf) or phys_map_nodes (!is_leaf) */ | |
88 | uint16_t ptr : 15; | |
89 | }; | |
90 | ||
91 | struct AddressSpaceDispatch { | |
92 | /* This is a multi-level map on the physical address space. | |
93 | * The bottom level has pointers to MemoryRegionSections. | |
94 | */ | |
95 | PhysPageEntry phys_map; | |
96 | MemoryListener listener; | |
acc9d80b | 97 | AddressSpace *as; |
1db8abb1 PB |
98 | }; |
99 | ||
90260c6c JK |
100 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
101 | typedef struct subpage_t { | |
102 | MemoryRegion iomem; | |
acc9d80b | 103 | AddressSpace *as; |
90260c6c JK |
104 | hwaddr base; |
105 | uint16_t sub_section[TARGET_PAGE_SIZE]; | |
106 | } subpage_t; | |
107 | ||
5312bd8b AK |
108 | static MemoryRegionSection *phys_sections; |
109 | static unsigned phys_sections_nb, phys_sections_nb_alloc; | |
110 | static uint16_t phys_section_unassigned; | |
aa102231 AK |
111 | static uint16_t phys_section_notdirty; |
112 | static uint16_t phys_section_rom; | |
113 | static uint16_t phys_section_watch; | |
5312bd8b | 114 | |
d6f2ea22 AK |
115 | /* Simple allocator for PhysPageEntry nodes */ |
116 | static PhysPageEntry (*phys_map_nodes)[L2_SIZE]; | |
117 | static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc; | |
118 | ||
07f07b31 | 119 | #define PHYS_MAP_NODE_NIL (((uint16_t)~0) >> 1) |
d6f2ea22 | 120 | |
e2eef170 | 121 | static void io_mem_init(void); |
62152b8a | 122 | static void memory_map_init(void); |
8b9c99d9 | 123 | static void *qemu_safe_ram_ptr(ram_addr_t addr); |
e2eef170 | 124 | |
1ec9b909 | 125 | static MemoryRegion io_mem_watch; |
6658ffb8 | 126 | #endif |
fd6ce8f6 | 127 | |
6d9a1304 | 128 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 129 | |
f7bf5461 | 130 | static void phys_map_node_reserve(unsigned nodes) |
d6f2ea22 | 131 | { |
f7bf5461 | 132 | if (phys_map_nodes_nb + nodes > phys_map_nodes_nb_alloc) { |
d6f2ea22 AK |
133 | typedef PhysPageEntry Node[L2_SIZE]; |
134 | phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc * 2, 16); | |
f7bf5461 AK |
135 | phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc, |
136 | phys_map_nodes_nb + nodes); | |
d6f2ea22 AK |
137 | phys_map_nodes = g_renew(Node, phys_map_nodes, |
138 | phys_map_nodes_nb_alloc); | |
139 | } | |
f7bf5461 AK |
140 | } |
141 | ||
142 | static uint16_t phys_map_node_alloc(void) | |
143 | { | |
144 | unsigned i; | |
145 | uint16_t ret; | |
146 | ||
147 | ret = phys_map_nodes_nb++; | |
148 | assert(ret != PHYS_MAP_NODE_NIL); | |
149 | assert(ret != phys_map_nodes_nb_alloc); | |
d6f2ea22 | 150 | for (i = 0; i < L2_SIZE; ++i) { |
07f07b31 | 151 | phys_map_nodes[ret][i].is_leaf = 0; |
c19e8800 | 152 | phys_map_nodes[ret][i].ptr = PHYS_MAP_NODE_NIL; |
d6f2ea22 | 153 | } |
f7bf5461 | 154 | return ret; |
d6f2ea22 AK |
155 | } |
156 | ||
a8170e5e AK |
157 | static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index, |
158 | hwaddr *nb, uint16_t leaf, | |
2999097b | 159 | int level) |
f7bf5461 AK |
160 | { |
161 | PhysPageEntry *p; | |
162 | int i; | |
a8170e5e | 163 | hwaddr step = (hwaddr)1 << (level * L2_BITS); |
108c49b8 | 164 | |
07f07b31 | 165 | if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) { |
c19e8800 AK |
166 | lp->ptr = phys_map_node_alloc(); |
167 | p = phys_map_nodes[lp->ptr]; | |
f7bf5461 AK |
168 | if (level == 0) { |
169 | for (i = 0; i < L2_SIZE; i++) { | |
07f07b31 | 170 | p[i].is_leaf = 1; |
c19e8800 | 171 | p[i].ptr = phys_section_unassigned; |
4346ae3e | 172 | } |
67c4d23c | 173 | } |
f7bf5461 | 174 | } else { |
c19e8800 | 175 | p = phys_map_nodes[lp->ptr]; |
92e873b9 | 176 | } |
2999097b | 177 | lp = &p[(*index >> (level * L2_BITS)) & (L2_SIZE - 1)]; |
f7bf5461 | 178 | |
2999097b | 179 | while (*nb && lp < &p[L2_SIZE]) { |
07f07b31 AK |
180 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
181 | lp->is_leaf = true; | |
c19e8800 | 182 | lp->ptr = leaf; |
07f07b31 AK |
183 | *index += step; |
184 | *nb -= step; | |
2999097b AK |
185 | } else { |
186 | phys_page_set_level(lp, index, nb, leaf, level - 1); | |
187 | } | |
188 | ++lp; | |
f7bf5461 AK |
189 | } |
190 | } | |
191 | ||
ac1970fb | 192 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 193 | hwaddr index, hwaddr nb, |
2999097b | 194 | uint16_t leaf) |
f7bf5461 | 195 | { |
2999097b | 196 | /* Wildly overreserve - it doesn't matter much. */ |
07f07b31 | 197 | phys_map_node_reserve(3 * P_L2_LEVELS); |
5cd2c5b6 | 198 | |
ac1970fb | 199 | phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
200 | } |
201 | ||
149f54b5 | 202 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index) |
92e873b9 | 203 | { |
ac1970fb | 204 | PhysPageEntry lp = d->phys_map; |
31ab2b4a AK |
205 | PhysPageEntry *p; |
206 | int i; | |
f1f6e3b8 | 207 | |
07f07b31 | 208 | for (i = P_L2_LEVELS - 1; i >= 0 && !lp.is_leaf; i--) { |
c19e8800 | 209 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
fd298934 | 210 | return &phys_sections[phys_section_unassigned]; |
31ab2b4a | 211 | } |
c19e8800 | 212 | p = phys_map_nodes[lp.ptr]; |
31ab2b4a | 213 | lp = p[(index >> (i * L2_BITS)) & (L2_SIZE - 1)]; |
5312bd8b | 214 | } |
fd298934 | 215 | return &phys_sections[lp.ptr]; |
f3705d53 AK |
216 | } |
217 | ||
e5548617 BS |
218 | bool memory_region_is_unassigned(MemoryRegion *mr) |
219 | { | |
2a8e7499 | 220 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
5b6dd868 | 221 | && mr != &io_mem_watch; |
fd6ce8f6 | 222 | } |
149f54b5 | 223 | |
9f029603 | 224 | static MemoryRegionSection *address_space_lookup_region(AddressSpace *as, |
90260c6c JK |
225 | hwaddr addr, |
226 | bool resolve_subpage) | |
9f029603 | 227 | { |
90260c6c JK |
228 | MemoryRegionSection *section; |
229 | subpage_t *subpage; | |
230 | ||
231 | section = phys_page_find(as->dispatch, addr >> TARGET_PAGE_BITS); | |
232 | if (resolve_subpage && section->mr->subpage) { | |
233 | subpage = container_of(section->mr, subpage_t, iomem); | |
234 | section = &phys_sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; | |
235 | } | |
236 | return section; | |
9f029603 JK |
237 | } |
238 | ||
90260c6c JK |
239 | static MemoryRegionSection * |
240 | address_space_translate_internal(AddressSpace *as, hwaddr addr, hwaddr *xlat, | |
241 | hwaddr *plen, bool resolve_subpage) | |
149f54b5 PB |
242 | { |
243 | MemoryRegionSection *section; | |
244 | Int128 diff; | |
245 | ||
90260c6c | 246 | section = address_space_lookup_region(as, addr, resolve_subpage); |
149f54b5 PB |
247 | /* Compute offset within MemoryRegionSection */ |
248 | addr -= section->offset_within_address_space; | |
249 | ||
250 | /* Compute offset within MemoryRegion */ | |
251 | *xlat = addr + section->offset_within_region; | |
252 | ||
253 | diff = int128_sub(section->mr->size, int128_make64(addr)); | |
3752a036 | 254 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
149f54b5 PB |
255 | return section; |
256 | } | |
90260c6c | 257 | |
5c8a00ce PB |
258 | MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, |
259 | hwaddr *xlat, hwaddr *plen, | |
260 | bool is_write) | |
90260c6c | 261 | { |
30951157 AK |
262 | IOMMUTLBEntry iotlb; |
263 | MemoryRegionSection *section; | |
264 | MemoryRegion *mr; | |
265 | hwaddr len = *plen; | |
266 | ||
267 | for (;;) { | |
268 | section = address_space_translate_internal(as, addr, &addr, plen, true); | |
269 | mr = section->mr; | |
270 | ||
271 | if (!mr->iommu_ops) { | |
272 | break; | |
273 | } | |
274 | ||
275 | iotlb = mr->iommu_ops->translate(mr, addr); | |
276 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
277 | | (addr & iotlb.addr_mask)); | |
278 | len = MIN(len, (addr | iotlb.addr_mask) - addr + 1); | |
279 | if (!(iotlb.perm & (1 << is_write))) { | |
280 | mr = &io_mem_unassigned; | |
281 | break; | |
282 | } | |
283 | ||
284 | as = iotlb.target_as; | |
285 | } | |
286 | ||
287 | *plen = len; | |
288 | *xlat = addr; | |
289 | return mr; | |
90260c6c JK |
290 | } |
291 | ||
292 | MemoryRegionSection * | |
293 | address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat, | |
294 | hwaddr *plen) | |
295 | { | |
30951157 AK |
296 | MemoryRegionSection *section; |
297 | section = address_space_translate_internal(as, addr, xlat, plen, false); | |
298 | ||
299 | assert(!section->mr->iommu_ops); | |
300 | return section; | |
90260c6c | 301 | } |
5b6dd868 | 302 | #endif |
fd6ce8f6 | 303 | |
5b6dd868 | 304 | void cpu_exec_init_all(void) |
fdbb84d1 | 305 | { |
5b6dd868 | 306 | #if !defined(CONFIG_USER_ONLY) |
b2a8658e | 307 | qemu_mutex_init(&ram_list.mutex); |
5b6dd868 BS |
308 | memory_map_init(); |
309 | io_mem_init(); | |
fdbb84d1 | 310 | #endif |
5b6dd868 | 311 | } |
fdbb84d1 | 312 | |
b170fce3 | 313 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
314 | |
315 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 316 | { |
259186a7 | 317 | CPUState *cpu = opaque; |
a513fe19 | 318 | |
5b6dd868 BS |
319 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
320 | version_id is increased. */ | |
259186a7 AF |
321 | cpu->interrupt_request &= ~0x01; |
322 | tlb_flush(cpu->env_ptr, 1); | |
5b6dd868 BS |
323 | |
324 | return 0; | |
a513fe19 | 325 | } |
7501267e | 326 | |
1a1562f5 | 327 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
328 | .name = "cpu_common", |
329 | .version_id = 1, | |
330 | .minimum_version_id = 1, | |
331 | .minimum_version_id_old = 1, | |
332 | .post_load = cpu_common_post_load, | |
333 | .fields = (VMStateField []) { | |
259186a7 AF |
334 | VMSTATE_UINT32(halted, CPUState), |
335 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 BS |
336 | VMSTATE_END_OF_LIST() |
337 | } | |
338 | }; | |
1a1562f5 | 339 | |
5b6dd868 | 340 | #endif |
ea041c0e | 341 | |
38d8f5c8 | 342 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 343 | { |
5b6dd868 | 344 | CPUArchState *env = first_cpu; |
38d8f5c8 | 345 | CPUState *cpu = NULL; |
ea041c0e | 346 | |
5b6dd868 | 347 | while (env) { |
55e5c285 AF |
348 | cpu = ENV_GET_CPU(env); |
349 | if (cpu->cpu_index == index) { | |
5b6dd868 | 350 | break; |
55e5c285 | 351 | } |
5b6dd868 | 352 | env = env->next_cpu; |
ea041c0e | 353 | } |
5b6dd868 | 354 | |
d76fddae | 355 | return env ? cpu : NULL; |
ea041c0e FB |
356 | } |
357 | ||
d6b9e0d6 MT |
358 | void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data) |
359 | { | |
360 | CPUArchState *env = first_cpu; | |
361 | ||
362 | while (env) { | |
363 | func(ENV_GET_CPU(env), data); | |
364 | env = env->next_cpu; | |
365 | } | |
366 | } | |
367 | ||
5b6dd868 | 368 | void cpu_exec_init(CPUArchState *env) |
ea041c0e | 369 | { |
5b6dd868 | 370 | CPUState *cpu = ENV_GET_CPU(env); |
b170fce3 | 371 | CPUClass *cc = CPU_GET_CLASS(cpu); |
5b6dd868 BS |
372 | CPUArchState **penv; |
373 | int cpu_index; | |
374 | ||
375 | #if defined(CONFIG_USER_ONLY) | |
376 | cpu_list_lock(); | |
377 | #endif | |
378 | env->next_cpu = NULL; | |
379 | penv = &first_cpu; | |
380 | cpu_index = 0; | |
381 | while (*penv != NULL) { | |
382 | penv = &(*penv)->next_cpu; | |
383 | cpu_index++; | |
384 | } | |
55e5c285 | 385 | cpu->cpu_index = cpu_index; |
1b1ed8dc | 386 | cpu->numa_node = 0; |
5b6dd868 BS |
387 | QTAILQ_INIT(&env->breakpoints); |
388 | QTAILQ_INIT(&env->watchpoints); | |
389 | #ifndef CONFIG_USER_ONLY | |
390 | cpu->thread_id = qemu_get_thread_id(); | |
391 | #endif | |
392 | *penv = env; | |
393 | #if defined(CONFIG_USER_ONLY) | |
394 | cpu_list_unlock(); | |
395 | #endif | |
259186a7 | 396 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu); |
5b6dd868 | 397 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
398 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
399 | cpu_save, cpu_load, env); | |
b170fce3 | 400 | assert(cc->vmsd == NULL); |
5b6dd868 | 401 | #endif |
b170fce3 AF |
402 | if (cc->vmsd != NULL) { |
403 | vmstate_register(NULL, cpu_index, cc->vmsd, cpu); | |
404 | } | |
ea041c0e FB |
405 | } |
406 | ||
1fddef4b | 407 | #if defined(TARGET_HAS_ICE) |
94df27fd | 408 | #if defined(CONFIG_USER_ONLY) |
9349b4f9 | 409 | static void breakpoint_invalidate(CPUArchState *env, target_ulong pc) |
94df27fd PB |
410 | { |
411 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
412 | } | |
413 | #else | |
1e7855a5 MF |
414 | static void breakpoint_invalidate(CPUArchState *env, target_ulong pc) |
415 | { | |
9d70c4b7 MF |
416 | tb_invalidate_phys_addr(cpu_get_phys_page_debug(env, pc) | |
417 | (pc & ~TARGET_PAGE_MASK)); | |
1e7855a5 | 418 | } |
c27004ec | 419 | #endif |
94df27fd | 420 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 421 | |
c527ee8f | 422 | #if defined(CONFIG_USER_ONLY) |
9349b4f9 | 423 | void cpu_watchpoint_remove_all(CPUArchState *env, int mask) |
c527ee8f PB |
424 | |
425 | { | |
426 | } | |
427 | ||
9349b4f9 | 428 | int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, |
c527ee8f PB |
429 | int flags, CPUWatchpoint **watchpoint) |
430 | { | |
431 | return -ENOSYS; | |
432 | } | |
433 | #else | |
6658ffb8 | 434 | /* Add a watchpoint. */ |
9349b4f9 | 435 | int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, |
a1d1bb31 | 436 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 437 | { |
b4051334 | 438 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 439 | CPUWatchpoint *wp; |
6658ffb8 | 440 | |
b4051334 | 441 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
0dc23828 MF |
442 | if ((len & (len - 1)) || (addr & ~len_mask) || |
443 | len == 0 || len > TARGET_PAGE_SIZE) { | |
b4051334 AL |
444 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
445 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
446 | return -EINVAL; | |
447 | } | |
7267c094 | 448 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
449 | |
450 | wp->vaddr = addr; | |
b4051334 | 451 | wp->len_mask = len_mask; |
a1d1bb31 AL |
452 | wp->flags = flags; |
453 | ||
2dc9f411 | 454 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 455 | if (flags & BP_GDB) |
72cf2d4f | 456 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 457 | else |
72cf2d4f | 458 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 459 | |
6658ffb8 | 460 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
461 | |
462 | if (watchpoint) | |
463 | *watchpoint = wp; | |
464 | return 0; | |
6658ffb8 PB |
465 | } |
466 | ||
a1d1bb31 | 467 | /* Remove a specific watchpoint. */ |
9349b4f9 | 468 | int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, |
a1d1bb31 | 469 | int flags) |
6658ffb8 | 470 | { |
b4051334 | 471 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 472 | CPUWatchpoint *wp; |
6658ffb8 | 473 | |
72cf2d4f | 474 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 475 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 476 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 477 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
478 | return 0; |
479 | } | |
480 | } | |
a1d1bb31 | 481 | return -ENOENT; |
6658ffb8 PB |
482 | } |
483 | ||
a1d1bb31 | 484 | /* Remove a specific watchpoint by reference. */ |
9349b4f9 | 485 | void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) |
a1d1bb31 | 486 | { |
72cf2d4f | 487 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 488 | |
a1d1bb31 AL |
489 | tlb_flush_page(env, watchpoint->vaddr); |
490 | ||
7267c094 | 491 | g_free(watchpoint); |
a1d1bb31 AL |
492 | } |
493 | ||
494 | /* Remove all matching watchpoints. */ | |
9349b4f9 | 495 | void cpu_watchpoint_remove_all(CPUArchState *env, int mask) |
a1d1bb31 | 496 | { |
c0ce998e | 497 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 498 | |
72cf2d4f | 499 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
500 | if (wp->flags & mask) |
501 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 502 | } |
7d03f82f | 503 | } |
c527ee8f | 504 | #endif |
7d03f82f | 505 | |
a1d1bb31 | 506 | /* Add a breakpoint. */ |
9349b4f9 | 507 | int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, |
a1d1bb31 | 508 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 509 | { |
1fddef4b | 510 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 511 | CPUBreakpoint *bp; |
3b46e624 | 512 | |
7267c094 | 513 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 514 | |
a1d1bb31 AL |
515 | bp->pc = pc; |
516 | bp->flags = flags; | |
517 | ||
2dc9f411 | 518 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 519 | if (flags & BP_GDB) |
72cf2d4f | 520 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 521 | else |
72cf2d4f | 522 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 523 | |
d720b93d | 524 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
525 | |
526 | if (breakpoint) | |
527 | *breakpoint = bp; | |
4c3a88a2 FB |
528 | return 0; |
529 | #else | |
a1d1bb31 | 530 | return -ENOSYS; |
4c3a88a2 FB |
531 | #endif |
532 | } | |
533 | ||
a1d1bb31 | 534 | /* Remove a specific breakpoint. */ |
9349b4f9 | 535 | int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) |
a1d1bb31 | 536 | { |
7d03f82f | 537 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
538 | CPUBreakpoint *bp; |
539 | ||
72cf2d4f | 540 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
541 | if (bp->pc == pc && bp->flags == flags) { |
542 | cpu_breakpoint_remove_by_ref(env, bp); | |
543 | return 0; | |
544 | } | |
7d03f82f | 545 | } |
a1d1bb31 AL |
546 | return -ENOENT; |
547 | #else | |
548 | return -ENOSYS; | |
7d03f82f EI |
549 | #endif |
550 | } | |
551 | ||
a1d1bb31 | 552 | /* Remove a specific breakpoint by reference. */ |
9349b4f9 | 553 | void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) |
4c3a88a2 | 554 | { |
1fddef4b | 555 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 556 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 557 | |
a1d1bb31 AL |
558 | breakpoint_invalidate(env, breakpoint->pc); |
559 | ||
7267c094 | 560 | g_free(breakpoint); |
a1d1bb31 AL |
561 | #endif |
562 | } | |
563 | ||
564 | /* Remove all matching breakpoints. */ | |
9349b4f9 | 565 | void cpu_breakpoint_remove_all(CPUArchState *env, int mask) |
a1d1bb31 AL |
566 | { |
567 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 568 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 569 | |
72cf2d4f | 570 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
571 | if (bp->flags & mask) |
572 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 573 | } |
4c3a88a2 FB |
574 | #endif |
575 | } | |
576 | ||
c33a346e FB |
577 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
578 | CPU loop after each instruction */ | |
9349b4f9 | 579 | void cpu_single_step(CPUArchState *env, int enabled) |
c33a346e | 580 | { |
1fddef4b | 581 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
582 | if (env->singlestep_enabled != enabled) { |
583 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
584 | if (kvm_enabled()) |
585 | kvm_update_guest_debug(env, 0); | |
586 | else { | |
ccbb4d44 | 587 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
588 | /* XXX: only flush what is necessary */ |
589 | tb_flush(env); | |
590 | } | |
c33a346e FB |
591 | } |
592 | #endif | |
593 | } | |
594 | ||
9349b4f9 | 595 | void cpu_abort(CPUArchState *env, const char *fmt, ...) |
7501267e | 596 | { |
878096ee | 597 | CPUState *cpu = ENV_GET_CPU(env); |
7501267e | 598 | va_list ap; |
493ae1f0 | 599 | va_list ap2; |
7501267e FB |
600 | |
601 | va_start(ap, fmt); | |
493ae1f0 | 602 | va_copy(ap2, ap); |
7501267e FB |
603 | fprintf(stderr, "qemu: fatal: "); |
604 | vfprintf(stderr, fmt, ap); | |
605 | fprintf(stderr, "\n"); | |
878096ee | 606 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
93fcfe39 AL |
607 | if (qemu_log_enabled()) { |
608 | qemu_log("qemu: fatal: "); | |
609 | qemu_log_vprintf(fmt, ap2); | |
610 | qemu_log("\n"); | |
6fd2a026 | 611 | log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 612 | qemu_log_flush(); |
93fcfe39 | 613 | qemu_log_close(); |
924edcae | 614 | } |
493ae1f0 | 615 | va_end(ap2); |
f9373291 | 616 | va_end(ap); |
fd052bf6 RV |
617 | #if defined(CONFIG_USER_ONLY) |
618 | { | |
619 | struct sigaction act; | |
620 | sigfillset(&act.sa_mask); | |
621 | act.sa_handler = SIG_DFL; | |
622 | sigaction(SIGABRT, &act, NULL); | |
623 | } | |
624 | #endif | |
7501267e FB |
625 | abort(); |
626 | } | |
627 | ||
9349b4f9 | 628 | CPUArchState *cpu_copy(CPUArchState *env) |
c5be9f08 | 629 | { |
9349b4f9 AF |
630 | CPUArchState *new_env = cpu_init(env->cpu_model_str); |
631 | CPUArchState *next_cpu = new_env->next_cpu; | |
5a38f081 AL |
632 | #if defined(TARGET_HAS_ICE) |
633 | CPUBreakpoint *bp; | |
634 | CPUWatchpoint *wp; | |
635 | #endif | |
636 | ||
9349b4f9 | 637 | memcpy(new_env, env, sizeof(CPUArchState)); |
5a38f081 | 638 | |
55e5c285 | 639 | /* Preserve chaining. */ |
c5be9f08 | 640 | new_env->next_cpu = next_cpu; |
5a38f081 AL |
641 | |
642 | /* Clone all break/watchpoints. | |
643 | Note: Once we support ptrace with hw-debug register access, make sure | |
644 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
645 | QTAILQ_INIT(&env->breakpoints); |
646 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 647 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 648 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
649 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
650 | } | |
72cf2d4f | 651 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
652 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
653 | wp->flags, NULL); | |
654 | } | |
655 | #endif | |
656 | ||
c5be9f08 TS |
657 | return new_env; |
658 | } | |
659 | ||
0124311e | 660 | #if !defined(CONFIG_USER_ONLY) |
d24981d3 JQ |
661 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end, |
662 | uintptr_t length) | |
663 | { | |
664 | uintptr_t start1; | |
665 | ||
666 | /* we modify the TLB cache so that the dirty bit will be set again | |
667 | when accessing the range */ | |
668 | start1 = (uintptr_t)qemu_safe_ram_ptr(start); | |
669 | /* Check that we don't span multiple blocks - this breaks the | |
670 | address comparisons below. */ | |
671 | if ((uintptr_t)qemu_safe_ram_ptr(end - 1) - start1 | |
672 | != (end - 1) - start) { | |
673 | abort(); | |
674 | } | |
675 | cpu_tlb_reset_dirty_all(start1, length); | |
676 | ||
677 | } | |
678 | ||
5579c7f3 | 679 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 680 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 681 | int dirty_flags) |
1ccde1cb | 682 | { |
d24981d3 | 683 | uintptr_t length; |
1ccde1cb FB |
684 | |
685 | start &= TARGET_PAGE_MASK; | |
686 | end = TARGET_PAGE_ALIGN(end); | |
687 | ||
688 | length = end - start; | |
689 | if (length == 0) | |
690 | return; | |
f7c11b53 | 691 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
f23db169 | 692 | |
d24981d3 JQ |
693 | if (tcg_enabled()) { |
694 | tlb_reset_dirty_range_all(start, end, length); | |
5579c7f3 | 695 | } |
1ccde1cb FB |
696 | } |
697 | ||
8b9c99d9 | 698 | static int cpu_physical_memory_set_dirty_tracking(int enable) |
74576198 | 699 | { |
f6f3fbca | 700 | int ret = 0; |
74576198 | 701 | in_migration = enable; |
f6f3fbca | 702 | return ret; |
74576198 AL |
703 | } |
704 | ||
a8170e5e | 705 | hwaddr memory_region_section_get_iotlb(CPUArchState *env, |
149f54b5 PB |
706 | MemoryRegionSection *section, |
707 | target_ulong vaddr, | |
708 | hwaddr paddr, hwaddr xlat, | |
709 | int prot, | |
710 | target_ulong *address) | |
e5548617 | 711 | { |
a8170e5e | 712 | hwaddr iotlb; |
e5548617 BS |
713 | CPUWatchpoint *wp; |
714 | ||
cc5bea60 | 715 | if (memory_region_is_ram(section->mr)) { |
e5548617 BS |
716 | /* Normal RAM. */ |
717 | iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) | |
149f54b5 | 718 | + xlat; |
e5548617 BS |
719 | if (!section->readonly) { |
720 | iotlb |= phys_section_notdirty; | |
721 | } else { | |
722 | iotlb |= phys_section_rom; | |
723 | } | |
724 | } else { | |
e5548617 | 725 | iotlb = section - phys_sections; |
149f54b5 | 726 | iotlb += xlat; |
e5548617 BS |
727 | } |
728 | ||
729 | /* Make accesses to pages with watchpoints go via the | |
730 | watchpoint trap routines. */ | |
731 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
732 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { | |
733 | /* Avoid trapping reads of pages with a write breakpoint. */ | |
734 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
735 | iotlb = phys_section_watch + paddr; | |
736 | *address |= TLB_MMIO; | |
737 | break; | |
738 | } | |
739 | } | |
740 | } | |
741 | ||
742 | return iotlb; | |
743 | } | |
9fa3e853 FB |
744 | #endif /* defined(CONFIG_USER_ONLY) */ |
745 | ||
e2eef170 | 746 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 747 | |
c227f099 | 748 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 749 | uint16_t section); |
acc9d80b | 750 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base); |
54688b1e | 751 | |
5312bd8b AK |
752 | static uint16_t phys_section_add(MemoryRegionSection *section) |
753 | { | |
68f3f65b PB |
754 | /* The physical section number is ORed with a page-aligned |
755 | * pointer to produce the iotlb entries. Thus it should | |
756 | * never overflow into the page-aligned value. | |
757 | */ | |
758 | assert(phys_sections_nb < TARGET_PAGE_SIZE); | |
759 | ||
5312bd8b AK |
760 | if (phys_sections_nb == phys_sections_nb_alloc) { |
761 | phys_sections_nb_alloc = MAX(phys_sections_nb_alloc * 2, 16); | |
762 | phys_sections = g_renew(MemoryRegionSection, phys_sections, | |
763 | phys_sections_nb_alloc); | |
764 | } | |
765 | phys_sections[phys_sections_nb] = *section; | |
dfde4e6e | 766 | memory_region_ref(section->mr); |
5312bd8b AK |
767 | return phys_sections_nb++; |
768 | } | |
769 | ||
058bc4b5 PB |
770 | static void phys_section_destroy(MemoryRegion *mr) |
771 | { | |
dfde4e6e PB |
772 | memory_region_unref(mr); |
773 | ||
058bc4b5 PB |
774 | if (mr->subpage) { |
775 | subpage_t *subpage = container_of(mr, subpage_t, iomem); | |
776 | memory_region_destroy(&subpage->iomem); | |
777 | g_free(subpage); | |
778 | } | |
779 | } | |
780 | ||
5312bd8b AK |
781 | static void phys_sections_clear(void) |
782 | { | |
058bc4b5 PB |
783 | while (phys_sections_nb > 0) { |
784 | MemoryRegionSection *section = &phys_sections[--phys_sections_nb]; | |
785 | phys_section_destroy(section->mr); | |
786 | } | |
b7e95164 | 787 | phys_map_nodes_nb = 0; |
5312bd8b AK |
788 | } |
789 | ||
ac1970fb | 790 | static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section) |
0f0cb164 AK |
791 | { |
792 | subpage_t *subpage; | |
a8170e5e | 793 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 794 | & TARGET_PAGE_MASK; |
ac1970fb | 795 | MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS); |
0f0cb164 AK |
796 | MemoryRegionSection subsection = { |
797 | .offset_within_address_space = base, | |
052e87b0 | 798 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 799 | }; |
a8170e5e | 800 | hwaddr start, end; |
0f0cb164 | 801 | |
f3705d53 | 802 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 803 | |
f3705d53 | 804 | if (!(existing->mr->subpage)) { |
acc9d80b | 805 | subpage = subpage_init(d->as, base); |
0f0cb164 | 806 | subsection.mr = &subpage->iomem; |
ac1970fb | 807 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
2999097b | 808 | phys_section_add(&subsection)); |
0f0cb164 | 809 | } else { |
f3705d53 | 810 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
811 | } |
812 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 813 | end = start + int128_get64(section->size) - 1; |
0f0cb164 AK |
814 | subpage_register(subpage, start, end, phys_section_add(section)); |
815 | } | |
816 | ||
817 | ||
052e87b0 PB |
818 | static void register_multipage(AddressSpaceDispatch *d, |
819 | MemoryRegionSection *section) | |
33417e70 | 820 | { |
a8170e5e | 821 | hwaddr start_addr = section->offset_within_address_space; |
5312bd8b | 822 | uint16_t section_index = phys_section_add(section); |
052e87b0 PB |
823 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
824 | TARGET_PAGE_BITS)); | |
dd81124b | 825 | |
733d5ef5 PB |
826 | assert(num_pages); |
827 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
828 | } |
829 | ||
ac1970fb | 830 | static void mem_add(MemoryListener *listener, MemoryRegionSection *section) |
0f0cb164 | 831 | { |
ac1970fb | 832 | AddressSpaceDispatch *d = container_of(listener, AddressSpaceDispatch, listener); |
99b9cc06 | 833 | MemoryRegionSection now = *section, remain = *section; |
052e87b0 | 834 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 835 | |
733d5ef5 PB |
836 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
837 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
838 | - now.offset_within_address_space; | |
839 | ||
052e87b0 | 840 | now.size = int128_min(int128_make64(left), now.size); |
ac1970fb | 841 | register_subpage(d, &now); |
733d5ef5 | 842 | } else { |
052e87b0 | 843 | now.size = int128_zero(); |
733d5ef5 | 844 | } |
052e87b0 PB |
845 | while (int128_ne(remain.size, now.size)) { |
846 | remain.size = int128_sub(remain.size, now.size); | |
847 | remain.offset_within_address_space += int128_get64(now.size); | |
848 | remain.offset_within_region += int128_get64(now.size); | |
69b67646 | 849 | now = remain; |
052e87b0 | 850 | if (int128_lt(remain.size, page_size)) { |
733d5ef5 PB |
851 | register_subpage(d, &now); |
852 | } else if (remain.offset_within_region & ~TARGET_PAGE_MASK) { | |
052e87b0 | 853 | now.size = page_size; |
ac1970fb | 854 | register_subpage(d, &now); |
69b67646 | 855 | } else { |
052e87b0 | 856 | now.size = int128_and(now.size, int128_neg(page_size)); |
ac1970fb | 857 | register_multipage(d, &now); |
69b67646 | 858 | } |
0f0cb164 AK |
859 | } |
860 | } | |
861 | ||
62a2744c SY |
862 | void qemu_flush_coalesced_mmio_buffer(void) |
863 | { | |
864 | if (kvm_enabled()) | |
865 | kvm_flush_coalesced_mmio_buffer(); | |
866 | } | |
867 | ||
b2a8658e UD |
868 | void qemu_mutex_lock_ramlist(void) |
869 | { | |
870 | qemu_mutex_lock(&ram_list.mutex); | |
871 | } | |
872 | ||
873 | void qemu_mutex_unlock_ramlist(void) | |
874 | { | |
875 | qemu_mutex_unlock(&ram_list.mutex); | |
876 | } | |
877 | ||
c902760f MT |
878 | #if defined(__linux__) && !defined(TARGET_S390X) |
879 | ||
880 | #include <sys/vfs.h> | |
881 | ||
882 | #define HUGETLBFS_MAGIC 0x958458f6 | |
883 | ||
884 | static long gethugepagesize(const char *path) | |
885 | { | |
886 | struct statfs fs; | |
887 | int ret; | |
888 | ||
889 | do { | |
9742bf26 | 890 | ret = statfs(path, &fs); |
c902760f MT |
891 | } while (ret != 0 && errno == EINTR); |
892 | ||
893 | if (ret != 0) { | |
9742bf26 YT |
894 | perror(path); |
895 | return 0; | |
c902760f MT |
896 | } |
897 | ||
898 | if (fs.f_type != HUGETLBFS_MAGIC) | |
9742bf26 | 899 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
c902760f MT |
900 | |
901 | return fs.f_bsize; | |
902 | } | |
903 | ||
04b16653 AW |
904 | static void *file_ram_alloc(RAMBlock *block, |
905 | ram_addr_t memory, | |
906 | const char *path) | |
c902760f MT |
907 | { |
908 | char *filename; | |
8ca761f6 PF |
909 | char *sanitized_name; |
910 | char *c; | |
c902760f MT |
911 | void *area; |
912 | int fd; | |
913 | #ifdef MAP_POPULATE | |
914 | int flags; | |
915 | #endif | |
916 | unsigned long hpagesize; | |
917 | ||
918 | hpagesize = gethugepagesize(path); | |
919 | if (!hpagesize) { | |
9742bf26 | 920 | return NULL; |
c902760f MT |
921 | } |
922 | ||
923 | if (memory < hpagesize) { | |
924 | return NULL; | |
925 | } | |
926 | ||
927 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
928 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
929 | return NULL; | |
930 | } | |
931 | ||
8ca761f6 PF |
932 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ |
933 | sanitized_name = g_strdup(block->mr->name); | |
934 | for (c = sanitized_name; *c != '\0'; c++) { | |
935 | if (*c == '/') | |
936 | *c = '_'; | |
937 | } | |
938 | ||
939 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, | |
940 | sanitized_name); | |
941 | g_free(sanitized_name); | |
c902760f MT |
942 | |
943 | fd = mkstemp(filename); | |
944 | if (fd < 0) { | |
9742bf26 | 945 | perror("unable to create backing store for hugepages"); |
e4ada482 | 946 | g_free(filename); |
9742bf26 | 947 | return NULL; |
c902760f MT |
948 | } |
949 | unlink(filename); | |
e4ada482 | 950 | g_free(filename); |
c902760f MT |
951 | |
952 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
953 | ||
954 | /* | |
955 | * ftruncate is not supported by hugetlbfs in older | |
956 | * hosts, so don't bother bailing out on errors. | |
957 | * If anything goes wrong with it under other filesystems, | |
958 | * mmap will fail. | |
959 | */ | |
960 | if (ftruncate(fd, memory)) | |
9742bf26 | 961 | perror("ftruncate"); |
c902760f MT |
962 | |
963 | #ifdef MAP_POPULATE | |
964 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
965 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
966 | * to sidestep this quirk. | |
967 | */ | |
968 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
969 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
970 | #else | |
971 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
972 | #endif | |
973 | if (area == MAP_FAILED) { | |
9742bf26 YT |
974 | perror("file_ram_alloc: can't mmap RAM pages"); |
975 | close(fd); | |
976 | return (NULL); | |
c902760f | 977 | } |
04b16653 | 978 | block->fd = fd; |
c902760f MT |
979 | return area; |
980 | } | |
981 | #endif | |
982 | ||
d17b5288 | 983 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
984 | { |
985 | RAMBlock *block, *next_block; | |
3e837b2c | 986 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 987 | |
49cd9ac6 SH |
988 | assert(size != 0); /* it would hand out same offset multiple times */ |
989 | ||
a3161038 | 990 | if (QTAILQ_EMPTY(&ram_list.blocks)) |
04b16653 AW |
991 | return 0; |
992 | ||
a3161038 | 993 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
f15fbc4b | 994 | ram_addr_t end, next = RAM_ADDR_MAX; |
04b16653 AW |
995 | |
996 | end = block->offset + block->length; | |
997 | ||
a3161038 | 998 | QTAILQ_FOREACH(next_block, &ram_list.blocks, next) { |
04b16653 AW |
999 | if (next_block->offset >= end) { |
1000 | next = MIN(next, next_block->offset); | |
1001 | } | |
1002 | } | |
1003 | if (next - end >= size && next - end < mingap) { | |
3e837b2c | 1004 | offset = end; |
04b16653 AW |
1005 | mingap = next - end; |
1006 | } | |
1007 | } | |
3e837b2c AW |
1008 | |
1009 | if (offset == RAM_ADDR_MAX) { | |
1010 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1011 | (uint64_t)size); | |
1012 | abort(); | |
1013 | } | |
1014 | ||
04b16653 AW |
1015 | return offset; |
1016 | } | |
1017 | ||
652d7ec2 | 1018 | ram_addr_t last_ram_offset(void) |
d17b5288 AW |
1019 | { |
1020 | RAMBlock *block; | |
1021 | ram_addr_t last = 0; | |
1022 | ||
a3161038 | 1023 | QTAILQ_FOREACH(block, &ram_list.blocks, next) |
d17b5288 AW |
1024 | last = MAX(last, block->offset + block->length); |
1025 | ||
1026 | return last; | |
1027 | } | |
1028 | ||
ddb97f1d JB |
1029 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1030 | { | |
1031 | int ret; | |
1032 | QemuOpts *machine_opts; | |
1033 | ||
1034 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
1035 | machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); | |
1036 | if (machine_opts && | |
1037 | !qemu_opt_get_bool(machine_opts, "dump-guest-core", true)) { | |
1038 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); | |
1039 | if (ret) { | |
1040 | perror("qemu_madvise"); | |
1041 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1042 | "but dump_guest_core=off specified\n"); | |
1043 | } | |
1044 | } | |
1045 | } | |
1046 | ||
c5705a77 | 1047 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
84b89d78 CM |
1048 | { |
1049 | RAMBlock *new_block, *block; | |
1050 | ||
c5705a77 | 1051 | new_block = NULL; |
a3161038 | 1052 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
c5705a77 AK |
1053 | if (block->offset == addr) { |
1054 | new_block = block; | |
1055 | break; | |
1056 | } | |
1057 | } | |
1058 | assert(new_block); | |
1059 | assert(!new_block->idstr[0]); | |
84b89d78 | 1060 | |
09e5ab63 AL |
1061 | if (dev) { |
1062 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1063 | if (id) { |
1064 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1065 | g_free(id); |
84b89d78 CM |
1066 | } |
1067 | } | |
1068 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1069 | ||
b2a8658e UD |
1070 | /* This assumes the iothread lock is taken here too. */ |
1071 | qemu_mutex_lock_ramlist(); | |
a3161038 | 1072 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
c5705a77 | 1073 | if (block != new_block && !strcmp(block->idstr, new_block->idstr)) { |
84b89d78 CM |
1074 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1075 | new_block->idstr); | |
1076 | abort(); | |
1077 | } | |
1078 | } | |
b2a8658e | 1079 | qemu_mutex_unlock_ramlist(); |
c5705a77 AK |
1080 | } |
1081 | ||
8490fc78 LC |
1082 | static int memory_try_enable_merging(void *addr, size_t len) |
1083 | { | |
1084 | QemuOpts *opts; | |
1085 | ||
1086 | opts = qemu_opts_find(qemu_find_opts("machine"), 0); | |
1087 | if (opts && !qemu_opt_get_bool(opts, "mem-merge", true)) { | |
1088 | /* disabled by the user */ | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1093 | } | |
1094 | ||
c5705a77 AK |
1095 | ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
1096 | MemoryRegion *mr) | |
1097 | { | |
abb26d63 | 1098 | RAMBlock *block, *new_block; |
c5705a77 AK |
1099 | |
1100 | size = TARGET_PAGE_ALIGN(size); | |
1101 | new_block = g_malloc0(sizeof(*new_block)); | |
84b89d78 | 1102 | |
b2a8658e UD |
1103 | /* This assumes the iothread lock is taken here too. */ |
1104 | qemu_mutex_lock_ramlist(); | |
7c637366 | 1105 | new_block->mr = mr; |
432d268c | 1106 | new_block->offset = find_ram_offset(size); |
6977dfe6 YT |
1107 | if (host) { |
1108 | new_block->host = host; | |
cd19cfa2 | 1109 | new_block->flags |= RAM_PREALLOC_MASK; |
6977dfe6 YT |
1110 | } else { |
1111 | if (mem_path) { | |
c902760f | 1112 | #if defined (__linux__) && !defined(TARGET_S390X) |
6977dfe6 YT |
1113 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
1114 | if (!new_block->host) { | |
6eebf958 | 1115 | new_block->host = qemu_anon_ram_alloc(size); |
8490fc78 | 1116 | memory_try_enable_merging(new_block->host, size); |
6977dfe6 | 1117 | } |
c902760f | 1118 | #else |
6977dfe6 YT |
1119 | fprintf(stderr, "-mem-path option unsupported\n"); |
1120 | exit(1); | |
c902760f | 1121 | #endif |
6977dfe6 | 1122 | } else { |
868bb33f | 1123 | if (xen_enabled()) { |
fce537d4 | 1124 | xen_ram_alloc(new_block->offset, size, mr); |
fdec9918 CB |
1125 | } else if (kvm_enabled()) { |
1126 | /* some s390/kvm configurations have special constraints */ | |
6eebf958 | 1127 | new_block->host = kvm_ram_alloc(size); |
432d268c | 1128 | } else { |
6eebf958 | 1129 | new_block->host = qemu_anon_ram_alloc(size); |
432d268c | 1130 | } |
8490fc78 | 1131 | memory_try_enable_merging(new_block->host, size); |
6977dfe6 | 1132 | } |
c902760f | 1133 | } |
94a6b54f PB |
1134 | new_block->length = size; |
1135 | ||
abb26d63 PB |
1136 | /* Keep the list sorted from biggest to smallest block. */ |
1137 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { | |
1138 | if (block->length < new_block->length) { | |
1139 | break; | |
1140 | } | |
1141 | } | |
1142 | if (block) { | |
1143 | QTAILQ_INSERT_BEFORE(block, new_block, next); | |
1144 | } else { | |
1145 | QTAILQ_INSERT_TAIL(&ram_list.blocks, new_block, next); | |
1146 | } | |
0d6d3c87 | 1147 | ram_list.mru_block = NULL; |
94a6b54f | 1148 | |
f798b07f | 1149 | ram_list.version++; |
b2a8658e | 1150 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1151 | |
7267c094 | 1152 | ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, |
04b16653 | 1153 | last_ram_offset() >> TARGET_PAGE_BITS); |
5fda043f IM |
1154 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
1155 | 0, size >> TARGET_PAGE_BITS); | |
1720aeee | 1156 | cpu_physical_memory_set_dirty_range(new_block->offset, size, 0xff); |
94a6b54f | 1157 | |
ddb97f1d | 1158 | qemu_ram_setup_dump(new_block->host, size); |
ad0b5321 | 1159 | qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE); |
ddb97f1d | 1160 | |
6f0437e8 JK |
1161 | if (kvm_enabled()) |
1162 | kvm_setup_guest_memory(new_block->host, size); | |
1163 | ||
94a6b54f PB |
1164 | return new_block->offset; |
1165 | } | |
e9a1ab19 | 1166 | |
c5705a77 | 1167 | ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr) |
6977dfe6 | 1168 | { |
c5705a77 | 1169 | return qemu_ram_alloc_from_ptr(size, NULL, mr); |
6977dfe6 YT |
1170 | } |
1171 | ||
1f2e98b6 AW |
1172 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
1173 | { | |
1174 | RAMBlock *block; | |
1175 | ||
b2a8658e UD |
1176 | /* This assumes the iothread lock is taken here too. */ |
1177 | qemu_mutex_lock_ramlist(); | |
a3161038 | 1178 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
1f2e98b6 | 1179 | if (addr == block->offset) { |
a3161038 | 1180 | QTAILQ_REMOVE(&ram_list.blocks, block, next); |
0d6d3c87 | 1181 | ram_list.mru_block = NULL; |
f798b07f | 1182 | ram_list.version++; |
7267c094 | 1183 | g_free(block); |
b2a8658e | 1184 | break; |
1f2e98b6 AW |
1185 | } |
1186 | } | |
b2a8658e | 1187 | qemu_mutex_unlock_ramlist(); |
1f2e98b6 AW |
1188 | } |
1189 | ||
c227f099 | 1190 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 1191 | { |
04b16653 AW |
1192 | RAMBlock *block; |
1193 | ||
b2a8658e UD |
1194 | /* This assumes the iothread lock is taken here too. */ |
1195 | qemu_mutex_lock_ramlist(); | |
a3161038 | 1196 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
04b16653 | 1197 | if (addr == block->offset) { |
a3161038 | 1198 | QTAILQ_REMOVE(&ram_list.blocks, block, next); |
0d6d3c87 | 1199 | ram_list.mru_block = NULL; |
f798b07f | 1200 | ram_list.version++; |
cd19cfa2 HY |
1201 | if (block->flags & RAM_PREALLOC_MASK) { |
1202 | ; | |
1203 | } else if (mem_path) { | |
04b16653 AW |
1204 | #if defined (__linux__) && !defined(TARGET_S390X) |
1205 | if (block->fd) { | |
1206 | munmap(block->host, block->length); | |
1207 | close(block->fd); | |
1208 | } else { | |
e7a09b92 | 1209 | qemu_anon_ram_free(block->host, block->length); |
04b16653 | 1210 | } |
fd28aa13 JK |
1211 | #else |
1212 | abort(); | |
04b16653 AW |
1213 | #endif |
1214 | } else { | |
868bb33f | 1215 | if (xen_enabled()) { |
e41d7c69 | 1216 | xen_invalidate_map_cache_entry(block->host); |
432d268c | 1217 | } else { |
e7a09b92 | 1218 | qemu_anon_ram_free(block->host, block->length); |
432d268c | 1219 | } |
04b16653 | 1220 | } |
7267c094 | 1221 | g_free(block); |
b2a8658e | 1222 | break; |
04b16653 AW |
1223 | } |
1224 | } | |
b2a8658e | 1225 | qemu_mutex_unlock_ramlist(); |
04b16653 | 1226 | |
e9a1ab19 FB |
1227 | } |
1228 | ||
cd19cfa2 HY |
1229 | #ifndef _WIN32 |
1230 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
1231 | { | |
1232 | RAMBlock *block; | |
1233 | ram_addr_t offset; | |
1234 | int flags; | |
1235 | void *area, *vaddr; | |
1236 | ||
a3161038 | 1237 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
cd19cfa2 HY |
1238 | offset = addr - block->offset; |
1239 | if (offset < block->length) { | |
1240 | vaddr = block->host + offset; | |
1241 | if (block->flags & RAM_PREALLOC_MASK) { | |
1242 | ; | |
1243 | } else { | |
1244 | flags = MAP_FIXED; | |
1245 | munmap(vaddr, length); | |
1246 | if (mem_path) { | |
1247 | #if defined(__linux__) && !defined(TARGET_S390X) | |
1248 | if (block->fd) { | |
1249 | #ifdef MAP_POPULATE | |
1250 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : | |
1251 | MAP_PRIVATE; | |
1252 | #else | |
1253 | flags |= MAP_PRIVATE; | |
1254 | #endif | |
1255 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
1256 | flags, block->fd, offset); | |
1257 | } else { | |
1258 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
1259 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
1260 | flags, -1, 0); | |
1261 | } | |
fd28aa13 JK |
1262 | #else |
1263 | abort(); | |
cd19cfa2 HY |
1264 | #endif |
1265 | } else { | |
1266 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
1267 | flags |= MAP_SHARED | MAP_ANONYMOUS; | |
1268 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, | |
1269 | flags, -1, 0); | |
1270 | #else | |
1271 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
1272 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
1273 | flags, -1, 0); | |
1274 | #endif | |
1275 | } | |
1276 | if (area != vaddr) { | |
f15fbc4b AP |
1277 | fprintf(stderr, "Could not remap addr: " |
1278 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
cd19cfa2 HY |
1279 | length, addr); |
1280 | exit(1); | |
1281 | } | |
8490fc78 | 1282 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 1283 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 HY |
1284 | } |
1285 | return; | |
1286 | } | |
1287 | } | |
1288 | } | |
1289 | #endif /* !_WIN32 */ | |
1290 | ||
1b5ec234 | 1291 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
dc828ca1 | 1292 | { |
94a6b54f PB |
1293 | RAMBlock *block; |
1294 | ||
b2a8658e | 1295 | /* The list is protected by the iothread lock here. */ |
0d6d3c87 PB |
1296 | block = ram_list.mru_block; |
1297 | if (block && addr - block->offset < block->length) { | |
1298 | goto found; | |
1299 | } | |
a3161038 | 1300 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
f471a17e | 1301 | if (addr - block->offset < block->length) { |
0d6d3c87 | 1302 | goto found; |
f471a17e | 1303 | } |
94a6b54f | 1304 | } |
f471a17e AW |
1305 | |
1306 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1307 | abort(); | |
1308 | ||
0d6d3c87 PB |
1309 | found: |
1310 | ram_list.mru_block = block; | |
1b5ec234 PB |
1311 | return block; |
1312 | } | |
1313 | ||
1314 | /* Return a host pointer to ram allocated with qemu_ram_alloc. | |
1315 | With the exception of the softmmu code in this file, this should | |
1316 | only be used for local memory (e.g. video ram) that the device owns, | |
1317 | and knows it isn't going to access beyond the end of the block. | |
1318 | ||
1319 | It should not be used for general purpose DMA. | |
1320 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
1321 | */ | |
1322 | void *qemu_get_ram_ptr(ram_addr_t addr) | |
1323 | { | |
1324 | RAMBlock *block = qemu_get_ram_block(addr); | |
1325 | ||
0d6d3c87 PB |
1326 | if (xen_enabled()) { |
1327 | /* We need to check if the requested address is in the RAM | |
1328 | * because we don't want to map the entire memory in QEMU. | |
1329 | * In that case just map until the end of the page. | |
1330 | */ | |
1331 | if (block->offset == 0) { | |
1332 | return xen_map_cache(addr, 0, 0); | |
1333 | } else if (block->host == NULL) { | |
1334 | block->host = | |
1335 | xen_map_cache(block->offset, block->length, 1); | |
1336 | } | |
1337 | } | |
1338 | return block->host + (addr - block->offset); | |
dc828ca1 PB |
1339 | } |
1340 | ||
0d6d3c87 PB |
1341 | /* Return a host pointer to ram allocated with qemu_ram_alloc. Same as |
1342 | * qemu_get_ram_ptr but do not touch ram_list.mru_block. | |
1343 | * | |
1344 | * ??? Is this still necessary? | |
b2e0a138 | 1345 | */ |
8b9c99d9 | 1346 | static void *qemu_safe_ram_ptr(ram_addr_t addr) |
b2e0a138 MT |
1347 | { |
1348 | RAMBlock *block; | |
1349 | ||
b2a8658e | 1350 | /* The list is protected by the iothread lock here. */ |
a3161038 | 1351 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
b2e0a138 | 1352 | if (addr - block->offset < block->length) { |
868bb33f | 1353 | if (xen_enabled()) { |
432d268c JN |
1354 | /* We need to check if the requested address is in the RAM |
1355 | * because we don't want to map the entire memory in QEMU. | |
712c2b41 | 1356 | * In that case just map until the end of the page. |
432d268c JN |
1357 | */ |
1358 | if (block->offset == 0) { | |
e41d7c69 | 1359 | return xen_map_cache(addr, 0, 0); |
432d268c | 1360 | } else if (block->host == NULL) { |
e41d7c69 JK |
1361 | block->host = |
1362 | xen_map_cache(block->offset, block->length, 1); | |
432d268c JN |
1363 | } |
1364 | } | |
b2e0a138 MT |
1365 | return block->host + (addr - block->offset); |
1366 | } | |
1367 | } | |
1368 | ||
1369 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1370 | abort(); | |
1371 | ||
1372 | return NULL; | |
1373 | } | |
1374 | ||
38bee5dc SS |
1375 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
1376 | * but takes a size argument */ | |
8b9c99d9 | 1377 | static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) |
38bee5dc | 1378 | { |
8ab934f9 SS |
1379 | if (*size == 0) { |
1380 | return NULL; | |
1381 | } | |
868bb33f | 1382 | if (xen_enabled()) { |
e41d7c69 | 1383 | return xen_map_cache(addr, *size, 1); |
868bb33f | 1384 | } else { |
38bee5dc SS |
1385 | RAMBlock *block; |
1386 | ||
a3161038 | 1387 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
38bee5dc SS |
1388 | if (addr - block->offset < block->length) { |
1389 | if (addr - block->offset + *size > block->length) | |
1390 | *size = block->length - addr + block->offset; | |
1391 | return block->host + (addr - block->offset); | |
1392 | } | |
1393 | } | |
1394 | ||
1395 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1396 | abort(); | |
38bee5dc SS |
1397 | } |
1398 | } | |
1399 | ||
7443b437 PB |
1400 | /* Some of the softmmu routines need to translate from a host pointer |
1401 | (typically a TLB entry) back to a ram offset. */ | |
1b5ec234 | 1402 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
5579c7f3 | 1403 | { |
94a6b54f PB |
1404 | RAMBlock *block; |
1405 | uint8_t *host = ptr; | |
1406 | ||
868bb33f | 1407 | if (xen_enabled()) { |
e41d7c69 | 1408 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
1b5ec234 | 1409 | return qemu_get_ram_block(*ram_addr)->mr; |
712c2b41 SS |
1410 | } |
1411 | ||
23887b79 PB |
1412 | block = ram_list.mru_block; |
1413 | if (block && block->host && host - block->host < block->length) { | |
1414 | goto found; | |
1415 | } | |
1416 | ||
a3161038 | 1417 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { |
432d268c JN |
1418 | /* This case append when the block is not mapped. */ |
1419 | if (block->host == NULL) { | |
1420 | continue; | |
1421 | } | |
f471a17e | 1422 | if (host - block->host < block->length) { |
23887b79 | 1423 | goto found; |
f471a17e | 1424 | } |
94a6b54f | 1425 | } |
432d268c | 1426 | |
1b5ec234 | 1427 | return NULL; |
23887b79 PB |
1428 | |
1429 | found: | |
1430 | *ram_addr = block->offset + (host - block->host); | |
1b5ec234 | 1431 | return block->mr; |
e890261f | 1432 | } |
f471a17e | 1433 | |
a8170e5e | 1434 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, |
0e0df1e2 | 1435 | uint64_t val, unsigned size) |
9fa3e853 | 1436 | { |
3a7d929e | 1437 | int dirty_flags; |
f7c11b53 | 1438 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 1439 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
0e0df1e2 | 1440 | tb_invalidate_phys_page_fast(ram_addr, size); |
f7c11b53 | 1441 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 1442 | } |
0e0df1e2 AK |
1443 | switch (size) { |
1444 | case 1: | |
1445 | stb_p(qemu_get_ram_ptr(ram_addr), val); | |
1446 | break; | |
1447 | case 2: | |
1448 | stw_p(qemu_get_ram_ptr(ram_addr), val); | |
1449 | break; | |
1450 | case 4: | |
1451 | stl_p(qemu_get_ram_ptr(ram_addr), val); | |
1452 | break; | |
1453 | default: | |
1454 | abort(); | |
3a7d929e | 1455 | } |
f23db169 | 1456 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 1457 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
1458 | /* we remove the notdirty callback only if the code has been |
1459 | flushed */ | |
1460 | if (dirty_flags == 0xff) | |
2e70f6ef | 1461 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
1462 | } |
1463 | ||
b018ddf6 PB |
1464 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
1465 | unsigned size, bool is_write) | |
1466 | { | |
1467 | return is_write; | |
1468 | } | |
1469 | ||
0e0df1e2 | 1470 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 1471 | .write = notdirty_mem_write, |
b018ddf6 | 1472 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 1473 | .endianness = DEVICE_NATIVE_ENDIAN, |
1ccde1cb FB |
1474 | }; |
1475 | ||
0f459d16 | 1476 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 1477 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 | 1478 | { |
9349b4f9 | 1479 | CPUArchState *env = cpu_single_env; |
06d55cc1 | 1480 | target_ulong pc, cs_base; |
0f459d16 | 1481 | target_ulong vaddr; |
a1d1bb31 | 1482 | CPUWatchpoint *wp; |
06d55cc1 | 1483 | int cpu_flags; |
0f459d16 | 1484 | |
06d55cc1 AL |
1485 | if (env->watchpoint_hit) { |
1486 | /* We re-entered the check after replacing the TB. Now raise | |
1487 | * the debug interrupt so that is will trigger after the | |
1488 | * current instruction. */ | |
c3affe56 | 1489 | cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
1490 | return; |
1491 | } | |
2e70f6ef | 1492 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 1493 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
1494 | if ((vaddr == (wp->vaddr & len_mask) || |
1495 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
1496 | wp->flags |= BP_WATCHPOINT_HIT; |
1497 | if (!env->watchpoint_hit) { | |
1498 | env->watchpoint_hit = wp; | |
5a316526 | 1499 | tb_check_watchpoint(env); |
6e140f28 AL |
1500 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
1501 | env->exception_index = EXCP_DEBUG; | |
488d6577 | 1502 | cpu_loop_exit(env); |
6e140f28 AL |
1503 | } else { |
1504 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
1505 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
488d6577 | 1506 | cpu_resume_from_signal(env, NULL); |
6e140f28 | 1507 | } |
06d55cc1 | 1508 | } |
6e140f28 AL |
1509 | } else { |
1510 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
1511 | } |
1512 | } | |
1513 | } | |
1514 | ||
6658ffb8 PB |
1515 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
1516 | so these check for a hit then pass through to the normal out-of-line | |
1517 | phys routines. */ | |
a8170e5e | 1518 | static uint64_t watch_mem_read(void *opaque, hwaddr addr, |
1ec9b909 | 1519 | unsigned size) |
6658ffb8 | 1520 | { |
1ec9b909 AK |
1521 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ); |
1522 | switch (size) { | |
1523 | case 1: return ldub_phys(addr); | |
1524 | case 2: return lduw_phys(addr); | |
1525 | case 4: return ldl_phys(addr); | |
1526 | default: abort(); | |
1527 | } | |
6658ffb8 PB |
1528 | } |
1529 | ||
a8170e5e | 1530 | static void watch_mem_write(void *opaque, hwaddr addr, |
1ec9b909 | 1531 | uint64_t val, unsigned size) |
6658ffb8 | 1532 | { |
1ec9b909 AK |
1533 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE); |
1534 | switch (size) { | |
67364150 MF |
1535 | case 1: |
1536 | stb_phys(addr, val); | |
1537 | break; | |
1538 | case 2: | |
1539 | stw_phys(addr, val); | |
1540 | break; | |
1541 | case 4: | |
1542 | stl_phys(addr, val); | |
1543 | break; | |
1ec9b909 AK |
1544 | default: abort(); |
1545 | } | |
6658ffb8 PB |
1546 | } |
1547 | ||
1ec9b909 AK |
1548 | static const MemoryRegionOps watch_mem_ops = { |
1549 | .read = watch_mem_read, | |
1550 | .write = watch_mem_write, | |
1551 | .endianness = DEVICE_NATIVE_ENDIAN, | |
6658ffb8 | 1552 | }; |
6658ffb8 | 1553 | |
a8170e5e | 1554 | static uint64_t subpage_read(void *opaque, hwaddr addr, |
70c68e44 | 1555 | unsigned len) |
db7b5426 | 1556 | { |
acc9d80b JK |
1557 | subpage_t *subpage = opaque; |
1558 | uint8_t buf[4]; | |
791af8c8 | 1559 | |
db7b5426 | 1560 | #if defined(DEBUG_SUBPAGE) |
acc9d80b JK |
1561 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx "\n", __func__, |
1562 | subpage, len, addr); | |
db7b5426 | 1563 | #endif |
acc9d80b JK |
1564 | address_space_read(subpage->as, addr + subpage->base, buf, len); |
1565 | switch (len) { | |
1566 | case 1: | |
1567 | return ldub_p(buf); | |
1568 | case 2: | |
1569 | return lduw_p(buf); | |
1570 | case 4: | |
1571 | return ldl_p(buf); | |
1572 | default: | |
1573 | abort(); | |
1574 | } | |
db7b5426 BS |
1575 | } |
1576 | ||
a8170e5e | 1577 | static void subpage_write(void *opaque, hwaddr addr, |
70c68e44 | 1578 | uint64_t value, unsigned len) |
db7b5426 | 1579 | { |
acc9d80b JK |
1580 | subpage_t *subpage = opaque; |
1581 | uint8_t buf[4]; | |
1582 | ||
db7b5426 | 1583 | #if defined(DEBUG_SUBPAGE) |
70c68e44 | 1584 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx |
acc9d80b JK |
1585 | " value %"PRIx64"\n", |
1586 | __func__, subpage, len, addr, value); | |
db7b5426 | 1587 | #endif |
acc9d80b JK |
1588 | switch (len) { |
1589 | case 1: | |
1590 | stb_p(buf, value); | |
1591 | break; | |
1592 | case 2: | |
1593 | stw_p(buf, value); | |
1594 | break; | |
1595 | case 4: | |
1596 | stl_p(buf, value); | |
1597 | break; | |
1598 | default: | |
1599 | abort(); | |
1600 | } | |
1601 | address_space_write(subpage->as, addr + subpage->base, buf, len); | |
db7b5426 BS |
1602 | } |
1603 | ||
c353e4cc PB |
1604 | static bool subpage_accepts(void *opaque, hwaddr addr, |
1605 | unsigned size, bool is_write) | |
1606 | { | |
acc9d80b | 1607 | subpage_t *subpage = opaque; |
c353e4cc | 1608 | #if defined(DEBUG_SUBPAGE) |
acc9d80b JK |
1609 | printf("%s: subpage %p %c len %d addr " TARGET_FMT_plx "\n", |
1610 | __func__, subpage, is_write ? 'w' : 'r', len, addr); | |
c353e4cc PB |
1611 | #endif |
1612 | ||
acc9d80b JK |
1613 | return address_space_access_valid(subpage->as, addr + subpage->base, |
1614 | size, is_write); | |
c353e4cc PB |
1615 | } |
1616 | ||
70c68e44 AK |
1617 | static const MemoryRegionOps subpage_ops = { |
1618 | .read = subpage_read, | |
1619 | .write = subpage_write, | |
c353e4cc | 1620 | .valid.accepts = subpage_accepts, |
70c68e44 | 1621 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
1622 | }; |
1623 | ||
c227f099 | 1624 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1625 | uint16_t section) |
db7b5426 BS |
1626 | { |
1627 | int idx, eidx; | |
1628 | ||
1629 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
1630 | return -1; | |
1631 | idx = SUBPAGE_IDX(start); | |
1632 | eidx = SUBPAGE_IDX(end); | |
1633 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 1634 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
1635 | mmio, start, end, idx, eidx, memory); |
1636 | #endif | |
db7b5426 | 1637 | for (; idx <= eidx; idx++) { |
5312bd8b | 1638 | mmio->sub_section[idx] = section; |
db7b5426 BS |
1639 | } |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
acc9d80b | 1644 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base) |
db7b5426 | 1645 | { |
c227f099 | 1646 | subpage_t *mmio; |
db7b5426 | 1647 | |
7267c094 | 1648 | mmio = g_malloc0(sizeof(subpage_t)); |
1eec614b | 1649 | |
acc9d80b | 1650 | mmio->as = as; |
1eec614b | 1651 | mmio->base = base; |
2c9b15ca | 1652 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
70c68e44 | 1653 | "subpage", TARGET_PAGE_SIZE); |
b3b00c78 | 1654 | mmio->iomem.subpage = true; |
db7b5426 | 1655 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
1656 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
1657 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 1658 | #endif |
0f0cb164 | 1659 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, phys_section_unassigned); |
db7b5426 BS |
1660 | |
1661 | return mmio; | |
1662 | } | |
1663 | ||
5312bd8b AK |
1664 | static uint16_t dummy_section(MemoryRegion *mr) |
1665 | { | |
1666 | MemoryRegionSection section = { | |
1667 | .mr = mr, | |
1668 | .offset_within_address_space = 0, | |
1669 | .offset_within_region = 0, | |
052e87b0 | 1670 | .size = int128_2_64(), |
5312bd8b AK |
1671 | }; |
1672 | ||
1673 | return phys_section_add(§ion); | |
1674 | } | |
1675 | ||
a8170e5e | 1676 | MemoryRegion *iotlb_to_region(hwaddr index) |
aa102231 | 1677 | { |
37ec01d4 | 1678 | return phys_sections[index & ~TARGET_PAGE_MASK].mr; |
aa102231 AK |
1679 | } |
1680 | ||
e9179ce1 AK |
1681 | static void io_mem_init(void) |
1682 | { | |
2c9b15ca PB |
1683 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, "rom", UINT64_MAX); |
1684 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, | |
0e0df1e2 | 1685 | "unassigned", UINT64_MAX); |
2c9b15ca | 1686 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
0e0df1e2 | 1687 | "notdirty", UINT64_MAX); |
2c9b15ca | 1688 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1ec9b909 | 1689 | "watch", UINT64_MAX); |
e9179ce1 AK |
1690 | } |
1691 | ||
ac1970fb AK |
1692 | static void mem_begin(MemoryListener *listener) |
1693 | { | |
1694 | AddressSpaceDispatch *d = container_of(listener, AddressSpaceDispatch, listener); | |
1695 | ||
ac1970fb AK |
1696 | d->phys_map.ptr = PHYS_MAP_NODE_NIL; |
1697 | } | |
1698 | ||
50c1e149 AK |
1699 | static void core_begin(MemoryListener *listener) |
1700 | { | |
5312bd8b AK |
1701 | phys_sections_clear(); |
1702 | phys_section_unassigned = dummy_section(&io_mem_unassigned); | |
aa102231 AK |
1703 | phys_section_notdirty = dummy_section(&io_mem_notdirty); |
1704 | phys_section_rom = dummy_section(&io_mem_rom); | |
1705 | phys_section_watch = dummy_section(&io_mem_watch); | |
50c1e149 AK |
1706 | } |
1707 | ||
1d71148e | 1708 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 1709 | { |
9349b4f9 | 1710 | CPUArchState *env; |
117712c3 AK |
1711 | |
1712 | /* since each CPU stores ram addresses in its TLB cache, we must | |
1713 | reset the modified entries */ | |
1714 | /* XXX: slow ! */ | |
1715 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
1716 | tlb_flush(env, 1); | |
1717 | } | |
50c1e149 AK |
1718 | } |
1719 | ||
93632747 AK |
1720 | static void core_log_global_start(MemoryListener *listener) |
1721 | { | |
1722 | cpu_physical_memory_set_dirty_tracking(1); | |
1723 | } | |
1724 | ||
1725 | static void core_log_global_stop(MemoryListener *listener) | |
1726 | { | |
1727 | cpu_physical_memory_set_dirty_tracking(0); | |
1728 | } | |
1729 | ||
93632747 | 1730 | static MemoryListener core_memory_listener = { |
50c1e149 | 1731 | .begin = core_begin, |
93632747 AK |
1732 | .log_global_start = core_log_global_start, |
1733 | .log_global_stop = core_log_global_stop, | |
ac1970fb | 1734 | .priority = 1, |
93632747 AK |
1735 | }; |
1736 | ||
1d71148e AK |
1737 | static MemoryListener tcg_memory_listener = { |
1738 | .commit = tcg_commit, | |
1739 | }; | |
1740 | ||
ac1970fb AK |
1741 | void address_space_init_dispatch(AddressSpace *as) |
1742 | { | |
1743 | AddressSpaceDispatch *d = g_new(AddressSpaceDispatch, 1); | |
1744 | ||
1745 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .is_leaf = 0 }; | |
1746 | d->listener = (MemoryListener) { | |
1747 | .begin = mem_begin, | |
1748 | .region_add = mem_add, | |
1749 | .region_nop = mem_add, | |
1750 | .priority = 0, | |
1751 | }; | |
acc9d80b | 1752 | d->as = as; |
ac1970fb AK |
1753 | as->dispatch = d; |
1754 | memory_listener_register(&d->listener, as); | |
1755 | } | |
1756 | ||
83f3c251 AK |
1757 | void address_space_destroy_dispatch(AddressSpace *as) |
1758 | { | |
1759 | AddressSpaceDispatch *d = as->dispatch; | |
1760 | ||
1761 | memory_listener_unregister(&d->listener); | |
83f3c251 AK |
1762 | g_free(d); |
1763 | as->dispatch = NULL; | |
1764 | } | |
1765 | ||
62152b8a AK |
1766 | static void memory_map_init(void) |
1767 | { | |
7267c094 | 1768 | system_memory = g_malloc(sizeof(*system_memory)); |
2c9b15ca | 1769 | memory_region_init(system_memory, NULL, "system", INT64_MAX); |
7dca8043 | 1770 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 1771 | |
7267c094 | 1772 | system_io = g_malloc(sizeof(*system_io)); |
2c9b15ca | 1773 | memory_region_init(system_io, NULL, "io", 65536); |
7dca8043 | 1774 | address_space_init(&address_space_io, system_io, "I/O"); |
93632747 | 1775 | |
f6790af6 | 1776 | memory_listener_register(&core_memory_listener, &address_space_memory); |
f6790af6 | 1777 | memory_listener_register(&tcg_memory_listener, &address_space_memory); |
62152b8a AK |
1778 | } |
1779 | ||
1780 | MemoryRegion *get_system_memory(void) | |
1781 | { | |
1782 | return system_memory; | |
1783 | } | |
1784 | ||
309cb471 AK |
1785 | MemoryRegion *get_system_io(void) |
1786 | { | |
1787 | return system_io; | |
1788 | } | |
1789 | ||
e2eef170 PB |
1790 | #endif /* !defined(CONFIG_USER_ONLY) */ |
1791 | ||
13eb76e0 FB |
1792 | /* physical memory access (slow version, mainly for debug) */ |
1793 | #if defined(CONFIG_USER_ONLY) | |
9349b4f9 | 1794 | int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr, |
a68fe89c | 1795 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
1796 | { |
1797 | int l, flags; | |
1798 | target_ulong page; | |
53a5960a | 1799 | void * p; |
13eb76e0 FB |
1800 | |
1801 | while (len > 0) { | |
1802 | page = addr & TARGET_PAGE_MASK; | |
1803 | l = (page + TARGET_PAGE_SIZE) - addr; | |
1804 | if (l > len) | |
1805 | l = len; | |
1806 | flags = page_get_flags(page); | |
1807 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 1808 | return -1; |
13eb76e0 FB |
1809 | if (is_write) { |
1810 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 1811 | return -1; |
579a97f7 | 1812 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 1813 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 1814 | return -1; |
72fb7daa AJ |
1815 | memcpy(p, buf, l); |
1816 | unlock_user(p, addr, l); | |
13eb76e0 FB |
1817 | } else { |
1818 | if (!(flags & PAGE_READ)) | |
a68fe89c | 1819 | return -1; |
579a97f7 | 1820 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 1821 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 1822 | return -1; |
72fb7daa | 1823 | memcpy(buf, p, l); |
5b257578 | 1824 | unlock_user(p, addr, 0); |
13eb76e0 FB |
1825 | } |
1826 | len -= l; | |
1827 | buf += l; | |
1828 | addr += l; | |
1829 | } | |
a68fe89c | 1830 | return 0; |
13eb76e0 | 1831 | } |
8df1cd07 | 1832 | |
13eb76e0 | 1833 | #else |
51d7a9eb | 1834 | |
a8170e5e AK |
1835 | static void invalidate_and_set_dirty(hwaddr addr, |
1836 | hwaddr length) | |
51d7a9eb AP |
1837 | { |
1838 | if (!cpu_physical_memory_is_dirty(addr)) { | |
1839 | /* invalidate code */ | |
1840 | tb_invalidate_phys_page_range(addr, addr + length, 0); | |
1841 | /* set dirty bit */ | |
1842 | cpu_physical_memory_set_dirty_flags(addr, (0xff & ~CODE_DIRTY_FLAG)); | |
1843 | } | |
e226939d | 1844 | xen_modified_memory(addr, length); |
51d7a9eb AP |
1845 | } |
1846 | ||
2bbfa05d PB |
1847 | static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) |
1848 | { | |
1849 | if (memory_region_is_ram(mr)) { | |
1850 | return !(is_write && mr->readonly); | |
1851 | } | |
1852 | if (memory_region_is_romd(mr)) { | |
1853 | return !is_write; | |
1854 | } | |
1855 | ||
1856 | return false; | |
1857 | } | |
1858 | ||
f52cc467 | 1859 | static inline int memory_access_size(MemoryRegion *mr, int l, hwaddr addr) |
82f2563f | 1860 | { |
f52cc467 | 1861 | if (l >= 4 && (((addr & 3) == 0 || mr->ops->impl.unaligned))) { |
82f2563f PB |
1862 | return 4; |
1863 | } | |
f52cc467 | 1864 | if (l >= 2 && (((addr & 1) == 0) || mr->ops->impl.unaligned)) { |
82f2563f PB |
1865 | return 2; |
1866 | } | |
1867 | return 1; | |
1868 | } | |
1869 | ||
fd8aaa76 | 1870 | bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, |
ac1970fb | 1871 | int len, bool is_write) |
13eb76e0 | 1872 | { |
149f54b5 | 1873 | hwaddr l; |
13eb76e0 | 1874 | uint8_t *ptr; |
791af8c8 | 1875 | uint64_t val; |
149f54b5 | 1876 | hwaddr addr1; |
5c8a00ce | 1877 | MemoryRegion *mr; |
fd8aaa76 | 1878 | bool error = false; |
3b46e624 | 1879 | |
13eb76e0 | 1880 | while (len > 0) { |
149f54b5 | 1881 | l = len; |
5c8a00ce | 1882 | mr = address_space_translate(as, addr, &addr1, &l, is_write); |
3b46e624 | 1883 | |
13eb76e0 | 1884 | if (is_write) { |
5c8a00ce PB |
1885 | if (!memory_access_is_direct(mr, is_write)) { |
1886 | l = memory_access_size(mr, l, addr1); | |
6a00d601 FB |
1887 | /* XXX: could force cpu_single_env to NULL to avoid |
1888 | potential bugs */ | |
82f2563f | 1889 | if (l == 4) { |
1c213d19 | 1890 | /* 32 bit write access */ |
c27004ec | 1891 | val = ldl_p(buf); |
5c8a00ce | 1892 | error |= io_mem_write(mr, addr1, val, 4); |
82f2563f | 1893 | } else if (l == 2) { |
1c213d19 | 1894 | /* 16 bit write access */ |
c27004ec | 1895 | val = lduw_p(buf); |
5c8a00ce | 1896 | error |= io_mem_write(mr, addr1, val, 2); |
13eb76e0 | 1897 | } else { |
1c213d19 | 1898 | /* 8 bit write access */ |
c27004ec | 1899 | val = ldub_p(buf); |
5c8a00ce | 1900 | error |= io_mem_write(mr, addr1, val, 1); |
13eb76e0 | 1901 | } |
2bbfa05d | 1902 | } else { |
5c8a00ce | 1903 | addr1 += memory_region_get_ram_addr(mr); |
13eb76e0 | 1904 | /* RAM case */ |
5579c7f3 | 1905 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 1906 | memcpy(ptr, buf, l); |
51d7a9eb | 1907 | invalidate_and_set_dirty(addr1, l); |
13eb76e0 FB |
1908 | } |
1909 | } else { | |
5c8a00ce | 1910 | if (!memory_access_is_direct(mr, is_write)) { |
13eb76e0 | 1911 | /* I/O case */ |
5c8a00ce | 1912 | l = memory_access_size(mr, l, addr1); |
82f2563f | 1913 | if (l == 4) { |
13eb76e0 | 1914 | /* 32 bit read access */ |
5c8a00ce | 1915 | error |= io_mem_read(mr, addr1, &val, 4); |
c27004ec | 1916 | stl_p(buf, val); |
82f2563f | 1917 | } else if (l == 2) { |
13eb76e0 | 1918 | /* 16 bit read access */ |
5c8a00ce | 1919 | error |= io_mem_read(mr, addr1, &val, 2); |
c27004ec | 1920 | stw_p(buf, val); |
13eb76e0 | 1921 | } else { |
1c213d19 | 1922 | /* 8 bit read access */ |
5c8a00ce | 1923 | error |= io_mem_read(mr, addr1, &val, 1); |
c27004ec | 1924 | stb_p(buf, val); |
13eb76e0 FB |
1925 | } |
1926 | } else { | |
1927 | /* RAM case */ | |
5c8a00ce | 1928 | ptr = qemu_get_ram_ptr(mr->ram_addr + addr1); |
f3705d53 | 1929 | memcpy(buf, ptr, l); |
13eb76e0 FB |
1930 | } |
1931 | } | |
1932 | len -= l; | |
1933 | buf += l; | |
1934 | addr += l; | |
1935 | } | |
fd8aaa76 PB |
1936 | |
1937 | return error; | |
13eb76e0 | 1938 | } |
8df1cd07 | 1939 | |
fd8aaa76 | 1940 | bool address_space_write(AddressSpace *as, hwaddr addr, |
ac1970fb AK |
1941 | const uint8_t *buf, int len) |
1942 | { | |
fd8aaa76 | 1943 | return address_space_rw(as, addr, (uint8_t *)buf, len, true); |
ac1970fb AK |
1944 | } |
1945 | ||
fd8aaa76 | 1946 | bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len) |
ac1970fb | 1947 | { |
fd8aaa76 | 1948 | return address_space_rw(as, addr, buf, len, false); |
ac1970fb AK |
1949 | } |
1950 | ||
1951 | ||
a8170e5e | 1952 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
ac1970fb AK |
1953 | int len, int is_write) |
1954 | { | |
fd8aaa76 | 1955 | address_space_rw(&address_space_memory, addr, buf, len, is_write); |
ac1970fb AK |
1956 | } |
1957 | ||
d0ecd2aa | 1958 | /* used for ROM loading : can write in RAM and ROM */ |
a8170e5e | 1959 | void cpu_physical_memory_write_rom(hwaddr addr, |
d0ecd2aa FB |
1960 | const uint8_t *buf, int len) |
1961 | { | |
149f54b5 | 1962 | hwaddr l; |
d0ecd2aa | 1963 | uint8_t *ptr; |
149f54b5 | 1964 | hwaddr addr1; |
5c8a00ce | 1965 | MemoryRegion *mr; |
3b46e624 | 1966 | |
d0ecd2aa | 1967 | while (len > 0) { |
149f54b5 | 1968 | l = len; |
5c8a00ce PB |
1969 | mr = address_space_translate(&address_space_memory, |
1970 | addr, &addr1, &l, true); | |
3b46e624 | 1971 | |
5c8a00ce PB |
1972 | if (!(memory_region_is_ram(mr) || |
1973 | memory_region_is_romd(mr))) { | |
d0ecd2aa FB |
1974 | /* do nothing */ |
1975 | } else { | |
5c8a00ce | 1976 | addr1 += memory_region_get_ram_addr(mr); |
d0ecd2aa | 1977 | /* ROM/RAM case */ |
5579c7f3 | 1978 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa | 1979 | memcpy(ptr, buf, l); |
51d7a9eb | 1980 | invalidate_and_set_dirty(addr1, l); |
d0ecd2aa FB |
1981 | } |
1982 | len -= l; | |
1983 | buf += l; | |
1984 | addr += l; | |
1985 | } | |
1986 | } | |
1987 | ||
6d16c2f8 | 1988 | typedef struct { |
d3e71559 | 1989 | MemoryRegion *mr; |
6d16c2f8 | 1990 | void *buffer; |
a8170e5e AK |
1991 | hwaddr addr; |
1992 | hwaddr len; | |
6d16c2f8 AL |
1993 | } BounceBuffer; |
1994 | ||
1995 | static BounceBuffer bounce; | |
1996 | ||
ba223c29 AL |
1997 | typedef struct MapClient { |
1998 | void *opaque; | |
1999 | void (*callback)(void *opaque); | |
72cf2d4f | 2000 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
2001 | } MapClient; |
2002 | ||
72cf2d4f BS |
2003 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
2004 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
2005 | |
2006 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
2007 | { | |
7267c094 | 2008 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 AL |
2009 | |
2010 | client->opaque = opaque; | |
2011 | client->callback = callback; | |
72cf2d4f | 2012 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
2013 | return client; |
2014 | } | |
2015 | ||
8b9c99d9 | 2016 | static void cpu_unregister_map_client(void *_client) |
ba223c29 AL |
2017 | { |
2018 | MapClient *client = (MapClient *)_client; | |
2019 | ||
72cf2d4f | 2020 | QLIST_REMOVE(client, link); |
7267c094 | 2021 | g_free(client); |
ba223c29 AL |
2022 | } |
2023 | ||
2024 | static void cpu_notify_map_clients(void) | |
2025 | { | |
2026 | MapClient *client; | |
2027 | ||
72cf2d4f BS |
2028 | while (!QLIST_EMPTY(&map_client_list)) { |
2029 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 2030 | client->callback(client->opaque); |
34d5e948 | 2031 | cpu_unregister_map_client(client); |
ba223c29 AL |
2032 | } |
2033 | } | |
2034 | ||
51644ab7 PB |
2035 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write) |
2036 | { | |
5c8a00ce | 2037 | MemoryRegion *mr; |
51644ab7 PB |
2038 | hwaddr l, xlat; |
2039 | ||
2040 | while (len > 0) { | |
2041 | l = len; | |
5c8a00ce PB |
2042 | mr = address_space_translate(as, addr, &xlat, &l, is_write); |
2043 | if (!memory_access_is_direct(mr, is_write)) { | |
2044 | l = memory_access_size(mr, l, addr); | |
2045 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { | |
51644ab7 PB |
2046 | return false; |
2047 | } | |
2048 | } | |
2049 | ||
2050 | len -= l; | |
2051 | addr += l; | |
2052 | } | |
2053 | return true; | |
2054 | } | |
2055 | ||
6d16c2f8 AL |
2056 | /* Map a physical memory region into a host virtual address. |
2057 | * May map a subset of the requested range, given by and returned in *plen. | |
2058 | * May return NULL if resources needed to perform the mapping are exhausted. | |
2059 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
2060 | * Use cpu_register_map_client() to know when retrying the map operation is |
2061 | * likely to succeed. | |
6d16c2f8 | 2062 | */ |
ac1970fb | 2063 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
2064 | hwaddr addr, |
2065 | hwaddr *plen, | |
ac1970fb | 2066 | bool is_write) |
6d16c2f8 | 2067 | { |
a8170e5e | 2068 | hwaddr len = *plen; |
e3127ae0 PB |
2069 | hwaddr done = 0; |
2070 | hwaddr l, xlat, base; | |
2071 | MemoryRegion *mr, *this_mr; | |
2072 | ram_addr_t raddr; | |
6d16c2f8 | 2073 | |
e3127ae0 PB |
2074 | if (len == 0) { |
2075 | return NULL; | |
2076 | } | |
38bee5dc | 2077 | |
e3127ae0 PB |
2078 | l = len; |
2079 | mr = address_space_translate(as, addr, &xlat, &l, is_write); | |
2080 | if (!memory_access_is_direct(mr, is_write)) { | |
2081 | if (bounce.buffer) { | |
2082 | return NULL; | |
6d16c2f8 | 2083 | } |
e3127ae0 PB |
2084 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); |
2085 | bounce.addr = addr; | |
2086 | bounce.len = l; | |
d3e71559 PB |
2087 | |
2088 | memory_region_ref(mr); | |
2089 | bounce.mr = mr; | |
e3127ae0 PB |
2090 | if (!is_write) { |
2091 | address_space_read(as, addr, bounce.buffer, l); | |
8ab934f9 | 2092 | } |
6d16c2f8 | 2093 | |
e3127ae0 PB |
2094 | *plen = l; |
2095 | return bounce.buffer; | |
2096 | } | |
2097 | ||
2098 | base = xlat; | |
2099 | raddr = memory_region_get_ram_addr(mr); | |
2100 | ||
2101 | for (;;) { | |
6d16c2f8 AL |
2102 | len -= l; |
2103 | addr += l; | |
e3127ae0 PB |
2104 | done += l; |
2105 | if (len == 0) { | |
2106 | break; | |
2107 | } | |
2108 | ||
2109 | l = len; | |
2110 | this_mr = address_space_translate(as, addr, &xlat, &l, is_write); | |
2111 | if (this_mr != mr || xlat != base + done) { | |
2112 | break; | |
2113 | } | |
6d16c2f8 | 2114 | } |
e3127ae0 | 2115 | |
d3e71559 | 2116 | memory_region_ref(mr); |
e3127ae0 PB |
2117 | *plen = done; |
2118 | return qemu_ram_ptr_length(raddr + base, plen); | |
6d16c2f8 AL |
2119 | } |
2120 | ||
ac1970fb | 2121 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
2122 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
2123 | * the amount of memory that was actually read or written by the caller. | |
2124 | */ | |
a8170e5e AK |
2125 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
2126 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
2127 | { |
2128 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
2129 | MemoryRegion *mr; |
2130 | ram_addr_t addr1; | |
2131 | ||
2132 | mr = qemu_ram_addr_from_host(buffer, &addr1); | |
2133 | assert(mr != NULL); | |
6d16c2f8 | 2134 | if (is_write) { |
6d16c2f8 AL |
2135 | while (access_len) { |
2136 | unsigned l; | |
2137 | l = TARGET_PAGE_SIZE; | |
2138 | if (l > access_len) | |
2139 | l = access_len; | |
51d7a9eb | 2140 | invalidate_and_set_dirty(addr1, l); |
6d16c2f8 AL |
2141 | addr1 += l; |
2142 | access_len -= l; | |
2143 | } | |
2144 | } | |
868bb33f | 2145 | if (xen_enabled()) { |
e41d7c69 | 2146 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 2147 | } |
d3e71559 | 2148 | memory_region_unref(mr); |
6d16c2f8 AL |
2149 | return; |
2150 | } | |
2151 | if (is_write) { | |
ac1970fb | 2152 | address_space_write(as, bounce.addr, bounce.buffer, access_len); |
6d16c2f8 | 2153 | } |
f8a83245 | 2154 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 2155 | bounce.buffer = NULL; |
d3e71559 | 2156 | memory_region_unref(bounce.mr); |
ba223c29 | 2157 | cpu_notify_map_clients(); |
6d16c2f8 | 2158 | } |
d0ecd2aa | 2159 | |
a8170e5e AK |
2160 | void *cpu_physical_memory_map(hwaddr addr, |
2161 | hwaddr *plen, | |
ac1970fb AK |
2162 | int is_write) |
2163 | { | |
2164 | return address_space_map(&address_space_memory, addr, plen, is_write); | |
2165 | } | |
2166 | ||
a8170e5e AK |
2167 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
2168 | int is_write, hwaddr access_len) | |
ac1970fb AK |
2169 | { |
2170 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
2171 | } | |
2172 | ||
8df1cd07 | 2173 | /* warning: addr must be aligned */ |
a8170e5e | 2174 | static inline uint32_t ldl_phys_internal(hwaddr addr, |
1e78bcc1 | 2175 | enum device_endian endian) |
8df1cd07 | 2176 | { |
8df1cd07 | 2177 | uint8_t *ptr; |
791af8c8 | 2178 | uint64_t val; |
5c8a00ce | 2179 | MemoryRegion *mr; |
149f54b5 PB |
2180 | hwaddr l = 4; |
2181 | hwaddr addr1; | |
8df1cd07 | 2182 | |
5c8a00ce PB |
2183 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2184 | false); | |
2185 | if (l < 4 || !memory_access_is_direct(mr, false)) { | |
8df1cd07 | 2186 | /* I/O case */ |
5c8a00ce | 2187 | io_mem_read(mr, addr1, &val, 4); |
1e78bcc1 AG |
2188 | #if defined(TARGET_WORDS_BIGENDIAN) |
2189 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2190 | val = bswap32(val); | |
2191 | } | |
2192 | #else | |
2193 | if (endian == DEVICE_BIG_ENDIAN) { | |
2194 | val = bswap32(val); | |
2195 | } | |
2196 | #endif | |
8df1cd07 FB |
2197 | } else { |
2198 | /* RAM case */ | |
5c8a00ce | 2199 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
06ef3525 | 2200 | & TARGET_PAGE_MASK) |
149f54b5 | 2201 | + addr1); |
1e78bcc1 AG |
2202 | switch (endian) { |
2203 | case DEVICE_LITTLE_ENDIAN: | |
2204 | val = ldl_le_p(ptr); | |
2205 | break; | |
2206 | case DEVICE_BIG_ENDIAN: | |
2207 | val = ldl_be_p(ptr); | |
2208 | break; | |
2209 | default: | |
2210 | val = ldl_p(ptr); | |
2211 | break; | |
2212 | } | |
8df1cd07 FB |
2213 | } |
2214 | return val; | |
2215 | } | |
2216 | ||
a8170e5e | 2217 | uint32_t ldl_phys(hwaddr addr) |
1e78bcc1 AG |
2218 | { |
2219 | return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
2220 | } | |
2221 | ||
a8170e5e | 2222 | uint32_t ldl_le_phys(hwaddr addr) |
1e78bcc1 AG |
2223 | { |
2224 | return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
2225 | } | |
2226 | ||
a8170e5e | 2227 | uint32_t ldl_be_phys(hwaddr addr) |
1e78bcc1 AG |
2228 | { |
2229 | return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
2230 | } | |
2231 | ||
84b7b8e7 | 2232 | /* warning: addr must be aligned */ |
a8170e5e | 2233 | static inline uint64_t ldq_phys_internal(hwaddr addr, |
1e78bcc1 | 2234 | enum device_endian endian) |
84b7b8e7 | 2235 | { |
84b7b8e7 FB |
2236 | uint8_t *ptr; |
2237 | uint64_t val; | |
5c8a00ce | 2238 | MemoryRegion *mr; |
149f54b5 PB |
2239 | hwaddr l = 8; |
2240 | hwaddr addr1; | |
84b7b8e7 | 2241 | |
5c8a00ce PB |
2242 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2243 | false); | |
2244 | if (l < 8 || !memory_access_is_direct(mr, false)) { | |
84b7b8e7 | 2245 | /* I/O case */ |
5c8a00ce | 2246 | io_mem_read(mr, addr1, &val, 8); |
968a5627 PB |
2247 | #if defined(TARGET_WORDS_BIGENDIAN) |
2248 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2249 | val = bswap64(val); | |
2250 | } | |
2251 | #else | |
2252 | if (endian == DEVICE_BIG_ENDIAN) { | |
2253 | val = bswap64(val); | |
2254 | } | |
84b7b8e7 FB |
2255 | #endif |
2256 | } else { | |
2257 | /* RAM case */ | |
5c8a00ce | 2258 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
06ef3525 | 2259 | & TARGET_PAGE_MASK) |
149f54b5 | 2260 | + addr1); |
1e78bcc1 AG |
2261 | switch (endian) { |
2262 | case DEVICE_LITTLE_ENDIAN: | |
2263 | val = ldq_le_p(ptr); | |
2264 | break; | |
2265 | case DEVICE_BIG_ENDIAN: | |
2266 | val = ldq_be_p(ptr); | |
2267 | break; | |
2268 | default: | |
2269 | val = ldq_p(ptr); | |
2270 | break; | |
2271 | } | |
84b7b8e7 FB |
2272 | } |
2273 | return val; | |
2274 | } | |
2275 | ||
a8170e5e | 2276 | uint64_t ldq_phys(hwaddr addr) |
1e78bcc1 AG |
2277 | { |
2278 | return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
2279 | } | |
2280 | ||
a8170e5e | 2281 | uint64_t ldq_le_phys(hwaddr addr) |
1e78bcc1 AG |
2282 | { |
2283 | return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
2284 | } | |
2285 | ||
a8170e5e | 2286 | uint64_t ldq_be_phys(hwaddr addr) |
1e78bcc1 AG |
2287 | { |
2288 | return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
2289 | } | |
2290 | ||
aab33094 | 2291 | /* XXX: optimize */ |
a8170e5e | 2292 | uint32_t ldub_phys(hwaddr addr) |
aab33094 FB |
2293 | { |
2294 | uint8_t val; | |
2295 | cpu_physical_memory_read(addr, &val, 1); | |
2296 | return val; | |
2297 | } | |
2298 | ||
733f0b02 | 2299 | /* warning: addr must be aligned */ |
a8170e5e | 2300 | static inline uint32_t lduw_phys_internal(hwaddr addr, |
1e78bcc1 | 2301 | enum device_endian endian) |
aab33094 | 2302 | { |
733f0b02 MT |
2303 | uint8_t *ptr; |
2304 | uint64_t val; | |
5c8a00ce | 2305 | MemoryRegion *mr; |
149f54b5 PB |
2306 | hwaddr l = 2; |
2307 | hwaddr addr1; | |
733f0b02 | 2308 | |
5c8a00ce PB |
2309 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2310 | false); | |
2311 | if (l < 2 || !memory_access_is_direct(mr, false)) { | |
733f0b02 | 2312 | /* I/O case */ |
5c8a00ce | 2313 | io_mem_read(mr, addr1, &val, 2); |
1e78bcc1 AG |
2314 | #if defined(TARGET_WORDS_BIGENDIAN) |
2315 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2316 | val = bswap16(val); | |
2317 | } | |
2318 | #else | |
2319 | if (endian == DEVICE_BIG_ENDIAN) { | |
2320 | val = bswap16(val); | |
2321 | } | |
2322 | #endif | |
733f0b02 MT |
2323 | } else { |
2324 | /* RAM case */ | |
5c8a00ce | 2325 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr) |
06ef3525 | 2326 | & TARGET_PAGE_MASK) |
149f54b5 | 2327 | + addr1); |
1e78bcc1 AG |
2328 | switch (endian) { |
2329 | case DEVICE_LITTLE_ENDIAN: | |
2330 | val = lduw_le_p(ptr); | |
2331 | break; | |
2332 | case DEVICE_BIG_ENDIAN: | |
2333 | val = lduw_be_p(ptr); | |
2334 | break; | |
2335 | default: | |
2336 | val = lduw_p(ptr); | |
2337 | break; | |
2338 | } | |
733f0b02 MT |
2339 | } |
2340 | return val; | |
aab33094 FB |
2341 | } |
2342 | ||
a8170e5e | 2343 | uint32_t lduw_phys(hwaddr addr) |
1e78bcc1 AG |
2344 | { |
2345 | return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
2346 | } | |
2347 | ||
a8170e5e | 2348 | uint32_t lduw_le_phys(hwaddr addr) |
1e78bcc1 AG |
2349 | { |
2350 | return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
2351 | } | |
2352 | ||
a8170e5e | 2353 | uint32_t lduw_be_phys(hwaddr addr) |
1e78bcc1 AG |
2354 | { |
2355 | return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
2356 | } | |
2357 | ||
8df1cd07 FB |
2358 | /* warning: addr must be aligned. The ram page is not masked as dirty |
2359 | and the code inside is not invalidated. It is useful if the dirty | |
2360 | bits are used to track modified PTEs */ | |
a8170e5e | 2361 | void stl_phys_notdirty(hwaddr addr, uint32_t val) |
8df1cd07 | 2362 | { |
8df1cd07 | 2363 | uint8_t *ptr; |
5c8a00ce | 2364 | MemoryRegion *mr; |
149f54b5 PB |
2365 | hwaddr l = 4; |
2366 | hwaddr addr1; | |
8df1cd07 | 2367 | |
5c8a00ce PB |
2368 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2369 | true); | |
2370 | if (l < 4 || !memory_access_is_direct(mr, true)) { | |
2371 | io_mem_write(mr, addr1, val, 4); | |
8df1cd07 | 2372 | } else { |
5c8a00ce | 2373 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
5579c7f3 | 2374 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 2375 | stl_p(ptr, val); |
74576198 AL |
2376 | |
2377 | if (unlikely(in_migration)) { | |
2378 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
2379 | /* invalidate code */ | |
2380 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
2381 | /* set dirty bit */ | |
f7c11b53 YT |
2382 | cpu_physical_memory_set_dirty_flags( |
2383 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
74576198 AL |
2384 | } |
2385 | } | |
8df1cd07 FB |
2386 | } |
2387 | } | |
2388 | ||
2389 | /* warning: addr must be aligned */ | |
a8170e5e | 2390 | static inline void stl_phys_internal(hwaddr addr, uint32_t val, |
1e78bcc1 | 2391 | enum device_endian endian) |
8df1cd07 | 2392 | { |
8df1cd07 | 2393 | uint8_t *ptr; |
5c8a00ce | 2394 | MemoryRegion *mr; |
149f54b5 PB |
2395 | hwaddr l = 4; |
2396 | hwaddr addr1; | |
8df1cd07 | 2397 | |
5c8a00ce PB |
2398 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2399 | true); | |
2400 | if (l < 4 || !memory_access_is_direct(mr, true)) { | |
1e78bcc1 AG |
2401 | #if defined(TARGET_WORDS_BIGENDIAN) |
2402 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2403 | val = bswap32(val); | |
2404 | } | |
2405 | #else | |
2406 | if (endian == DEVICE_BIG_ENDIAN) { | |
2407 | val = bswap32(val); | |
2408 | } | |
2409 | #endif | |
5c8a00ce | 2410 | io_mem_write(mr, addr1, val, 4); |
8df1cd07 | 2411 | } else { |
8df1cd07 | 2412 | /* RAM case */ |
5c8a00ce | 2413 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
5579c7f3 | 2414 | ptr = qemu_get_ram_ptr(addr1); |
1e78bcc1 AG |
2415 | switch (endian) { |
2416 | case DEVICE_LITTLE_ENDIAN: | |
2417 | stl_le_p(ptr, val); | |
2418 | break; | |
2419 | case DEVICE_BIG_ENDIAN: | |
2420 | stl_be_p(ptr, val); | |
2421 | break; | |
2422 | default: | |
2423 | stl_p(ptr, val); | |
2424 | break; | |
2425 | } | |
51d7a9eb | 2426 | invalidate_and_set_dirty(addr1, 4); |
8df1cd07 FB |
2427 | } |
2428 | } | |
2429 | ||
a8170e5e | 2430 | void stl_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2431 | { |
2432 | stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); | |
2433 | } | |
2434 | ||
a8170e5e | 2435 | void stl_le_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2436 | { |
2437 | stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); | |
2438 | } | |
2439 | ||
a8170e5e | 2440 | void stl_be_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2441 | { |
2442 | stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN); | |
2443 | } | |
2444 | ||
aab33094 | 2445 | /* XXX: optimize */ |
a8170e5e | 2446 | void stb_phys(hwaddr addr, uint32_t val) |
aab33094 FB |
2447 | { |
2448 | uint8_t v = val; | |
2449 | cpu_physical_memory_write(addr, &v, 1); | |
2450 | } | |
2451 | ||
733f0b02 | 2452 | /* warning: addr must be aligned */ |
a8170e5e | 2453 | static inline void stw_phys_internal(hwaddr addr, uint32_t val, |
1e78bcc1 | 2454 | enum device_endian endian) |
aab33094 | 2455 | { |
733f0b02 | 2456 | uint8_t *ptr; |
5c8a00ce | 2457 | MemoryRegion *mr; |
149f54b5 PB |
2458 | hwaddr l = 2; |
2459 | hwaddr addr1; | |
733f0b02 | 2460 | |
5c8a00ce PB |
2461 | mr = address_space_translate(&address_space_memory, addr, &addr1, &l, |
2462 | true); | |
2463 | if (l < 2 || !memory_access_is_direct(mr, true)) { | |
1e78bcc1 AG |
2464 | #if defined(TARGET_WORDS_BIGENDIAN) |
2465 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
2466 | val = bswap16(val); | |
2467 | } | |
2468 | #else | |
2469 | if (endian == DEVICE_BIG_ENDIAN) { | |
2470 | val = bswap16(val); | |
2471 | } | |
2472 | #endif | |
5c8a00ce | 2473 | io_mem_write(mr, addr1, val, 2); |
733f0b02 | 2474 | } else { |
733f0b02 | 2475 | /* RAM case */ |
5c8a00ce | 2476 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
733f0b02 | 2477 | ptr = qemu_get_ram_ptr(addr1); |
1e78bcc1 AG |
2478 | switch (endian) { |
2479 | case DEVICE_LITTLE_ENDIAN: | |
2480 | stw_le_p(ptr, val); | |
2481 | break; | |
2482 | case DEVICE_BIG_ENDIAN: | |
2483 | stw_be_p(ptr, val); | |
2484 | break; | |
2485 | default: | |
2486 | stw_p(ptr, val); | |
2487 | break; | |
2488 | } | |
51d7a9eb | 2489 | invalidate_and_set_dirty(addr1, 2); |
733f0b02 | 2490 | } |
aab33094 FB |
2491 | } |
2492 | ||
a8170e5e | 2493 | void stw_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2494 | { |
2495 | stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); | |
2496 | } | |
2497 | ||
a8170e5e | 2498 | void stw_le_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2499 | { |
2500 | stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); | |
2501 | } | |
2502 | ||
a8170e5e | 2503 | void stw_be_phys(hwaddr addr, uint32_t val) |
1e78bcc1 AG |
2504 | { |
2505 | stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN); | |
2506 | } | |
2507 | ||
aab33094 | 2508 | /* XXX: optimize */ |
a8170e5e | 2509 | void stq_phys(hwaddr addr, uint64_t val) |
aab33094 FB |
2510 | { |
2511 | val = tswap64(val); | |
71d2b725 | 2512 | cpu_physical_memory_write(addr, &val, 8); |
aab33094 FB |
2513 | } |
2514 | ||
a8170e5e | 2515 | void stq_le_phys(hwaddr addr, uint64_t val) |
1e78bcc1 AG |
2516 | { |
2517 | val = cpu_to_le64(val); | |
2518 | cpu_physical_memory_write(addr, &val, 8); | |
2519 | } | |
2520 | ||
a8170e5e | 2521 | void stq_be_phys(hwaddr addr, uint64_t val) |
1e78bcc1 AG |
2522 | { |
2523 | val = cpu_to_be64(val); | |
2524 | cpu_physical_memory_write(addr, &val, 8); | |
2525 | } | |
2526 | ||
5e2972fd | 2527 | /* virtual memory access for debug (includes writing to ROM) */ |
9349b4f9 | 2528 | int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr, |
b448f2f3 | 2529 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2530 | { |
2531 | int l; | |
a8170e5e | 2532 | hwaddr phys_addr; |
9b3c35e0 | 2533 | target_ulong page; |
13eb76e0 FB |
2534 | |
2535 | while (len > 0) { | |
2536 | page = addr & TARGET_PAGE_MASK; | |
2537 | phys_addr = cpu_get_phys_page_debug(env, page); | |
2538 | /* if no physical page mapped, return an error */ | |
2539 | if (phys_addr == -1) | |
2540 | return -1; | |
2541 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2542 | if (l > len) | |
2543 | l = len; | |
5e2972fd | 2544 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
2545 | if (is_write) |
2546 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
2547 | else | |
5e2972fd | 2548 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
2549 | len -= l; |
2550 | buf += l; | |
2551 | addr += l; | |
2552 | } | |
2553 | return 0; | |
2554 | } | |
a68fe89c | 2555 | #endif |
13eb76e0 | 2556 | |
8e4a424b BS |
2557 | #if !defined(CONFIG_USER_ONLY) |
2558 | ||
2559 | /* | |
2560 | * A helper function for the _utterly broken_ virtio device model to find out if | |
2561 | * it's running on a big endian machine. Don't do this at home kids! | |
2562 | */ | |
2563 | bool virtio_is_big_endian(void); | |
2564 | bool virtio_is_big_endian(void) | |
2565 | { | |
2566 | #if defined(TARGET_WORDS_BIGENDIAN) | |
2567 | return true; | |
2568 | #else | |
2569 | return false; | |
2570 | #endif | |
2571 | } | |
2572 | ||
2573 | #endif | |
2574 | ||
76f35538 | 2575 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 2576 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 2577 | { |
5c8a00ce | 2578 | MemoryRegion*mr; |
149f54b5 | 2579 | hwaddr l = 1; |
76f35538 | 2580 | |
5c8a00ce PB |
2581 | mr = address_space_translate(&address_space_memory, |
2582 | phys_addr, &phys_addr, &l, false); | |
76f35538 | 2583 | |
5c8a00ce PB |
2584 | return !(memory_region_is_ram(mr) || |
2585 | memory_region_is_romd(mr)); | |
76f35538 | 2586 | } |
bd2fa51f MH |
2587 | |
2588 | void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) | |
2589 | { | |
2590 | RAMBlock *block; | |
2591 | ||
2592 | QTAILQ_FOREACH(block, &ram_list.blocks, next) { | |
2593 | func(block->host, block->offset, block->length, opaque); | |
2594 | } | |
2595 | } | |
ec3f8c99 | 2596 | #endif |