]>
Commit | Line | Data |
---|---|---|
54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 | 26 | |
055403b2 | 27 | #include "qemu-common.h" |
6180a181 | 28 | #include "cpu.h" |
b67d9a52 | 29 | #include "tcg.h" |
b3c7724c | 30 | #include "hw/hw.h" |
cc9e98cb | 31 | #include "hw/qdev.h" |
74576198 | 32 | #include "osdep.h" |
7ba1e619 | 33 | #include "kvm.h" |
432d268c | 34 | #include "hw/xen.h" |
29e922b6 | 35 | #include "qemu-timer.h" |
62152b8a AK |
36 | #include "memory.h" |
37 | #include "exec-memory.h" | |
53a5960a PB |
38 | #if defined(CONFIG_USER_ONLY) |
39 | #include <qemu.h> | |
f01576f1 JL |
40 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
41 | #include <sys/param.h> | |
42 | #if __FreeBSD_version >= 700104 | |
43 | #define HAVE_KINFO_GETVMMAP | |
44 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
45 | #include <sys/time.h> | |
46 | #include <sys/proc.h> | |
47 | #include <machine/profile.h> | |
48 | #define _KERNEL | |
49 | #include <sys/user.h> | |
50 | #undef _KERNEL | |
51 | #undef sigqueue | |
52 | #include <libutil.h> | |
53 | #endif | |
54 | #endif | |
432d268c JN |
55 | #else /* !CONFIG_USER_ONLY */ |
56 | #include "xen-mapcache.h" | |
6506e4f9 | 57 | #include "trace.h" |
53a5960a | 58 | #endif |
54936004 | 59 | |
67d95c15 AK |
60 | #define WANT_EXEC_OBSOLETE |
61 | #include "exec-obsolete.h" | |
62 | ||
fd6ce8f6 | 63 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 64 | //#define DEBUG_FLUSH |
9fa3e853 | 65 | //#define DEBUG_TLB |
67d3b957 | 66 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
67 | |
68 | /* make various TB consistency checks */ | |
5fafdf24 TS |
69 | //#define DEBUG_TB_CHECK |
70 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 71 | |
1196be37 | 72 | //#define DEBUG_IOPORT |
db7b5426 | 73 | //#define DEBUG_SUBPAGE |
1196be37 | 74 | |
99773bd4 PB |
75 | #if !defined(CONFIG_USER_ONLY) |
76 | /* TB consistency checks only implemented for usermode emulation. */ | |
77 | #undef DEBUG_TB_CHECK | |
78 | #endif | |
79 | ||
9fa3e853 FB |
80 | #define SMC_BITMAP_USE_THRESHOLD 10 |
81 | ||
bdaf78e0 | 82 | static TranslationBlock *tbs; |
24ab68ac | 83 | static int code_gen_max_blocks; |
9fa3e853 | 84 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 85 | static int nb_tbs; |
eb51d102 | 86 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 87 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 88 | |
141ac468 BS |
89 | #if defined(__arm__) || defined(__sparc_v9__) |
90 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
91 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
92 | section close to code segment. */ |
93 | #define code_gen_section \ | |
94 | __attribute__((__section__(".gen_code"))) \ | |
95 | __attribute__((aligned (32))) | |
f8e2af11 SW |
96 | #elif defined(_WIN32) |
97 | /* Maximum alignment for Win32 is 16. */ | |
98 | #define code_gen_section \ | |
99 | __attribute__((aligned (16))) | |
d03d860b BS |
100 | #else |
101 | #define code_gen_section \ | |
102 | __attribute__((aligned (32))) | |
103 | #endif | |
104 | ||
105 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
106 | static uint8_t *code_gen_buffer; |
107 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 108 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 109 | static unsigned long code_gen_buffer_max_size; |
24ab68ac | 110 | static uint8_t *code_gen_ptr; |
fd6ce8f6 | 111 | |
e2eef170 | 112 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 113 | int phys_ram_fd; |
74576198 | 114 | static int in_migration; |
94a6b54f | 115 | |
85d59fef | 116 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
117 | |
118 | static MemoryRegion *system_memory; | |
309cb471 | 119 | static MemoryRegion *system_io; |
62152b8a | 120 | |
0e0df1e2 | 121 | MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty; |
de712f94 | 122 | static MemoryRegion io_mem_subpage_ram; |
0e0df1e2 | 123 | |
e2eef170 | 124 | #endif |
9fa3e853 | 125 | |
6a00d601 FB |
126 | CPUState *first_cpu; |
127 | /* current CPU in the current thread. It is only valid inside | |
128 | cpu_exec() */ | |
b3c4bbe5 | 129 | DEFINE_TLS(CPUState *,cpu_single_env); |
2e70f6ef | 130 | /* 0 = Do not count executed instructions. |
bf20dc07 | 131 | 1 = Precise instruction counting. |
2e70f6ef PB |
132 | 2 = Adaptive rate instruction counting. */ |
133 | int use_icount = 0; | |
6a00d601 | 134 | |
54936004 | 135 | typedef struct PageDesc { |
92e873b9 | 136 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 137 | TranslationBlock *first_tb; |
9fa3e853 FB |
138 | /* in order to optimize self modifying code, we count the number |
139 | of lookups we do to a given page to use a bitmap */ | |
140 | unsigned int code_write_count; | |
141 | uint8_t *code_bitmap; | |
142 | #if defined(CONFIG_USER_ONLY) | |
143 | unsigned long flags; | |
144 | #endif | |
54936004 FB |
145 | } PageDesc; |
146 | ||
41c1b1c9 | 147 | /* In system mode we want L1_MAP to be based on ram offsets, |
5cd2c5b6 RH |
148 | while in user mode we want it to be based on virtual addresses. */ |
149 | #if !defined(CONFIG_USER_ONLY) | |
41c1b1c9 PB |
150 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
151 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
152 | #else | |
5cd2c5b6 | 153 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
41c1b1c9 | 154 | #endif |
bedb69ea | 155 | #else |
5cd2c5b6 | 156 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
bedb69ea | 157 | #endif |
54936004 | 158 | |
5cd2c5b6 RH |
159 | /* Size of the L2 (and L3, etc) page tables. */ |
160 | #define L2_BITS 10 | |
54936004 FB |
161 | #define L2_SIZE (1 << L2_BITS) |
162 | ||
3eef53df AK |
163 | #define P_L2_LEVELS \ |
164 | (((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / L2_BITS) + 1) | |
165 | ||
5cd2c5b6 | 166 | /* The bits remaining after N lower levels of page tables. */ |
5cd2c5b6 RH |
167 | #define V_L1_BITS_REM \ |
168 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
169 | ||
5cd2c5b6 RH |
170 | #if V_L1_BITS_REM < 4 |
171 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
172 | #else | |
173 | #define V_L1_BITS V_L1_BITS_REM | |
174 | #endif | |
175 | ||
5cd2c5b6 RH |
176 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) |
177 | ||
5cd2c5b6 RH |
178 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) |
179 | ||
83fb7adf | 180 | unsigned long qemu_real_host_page_size; |
83fb7adf FB |
181 | unsigned long qemu_host_page_size; |
182 | unsigned long qemu_host_page_mask; | |
54936004 | 183 | |
5cd2c5b6 RH |
184 | /* This is a multi-level map on the virtual address space. |
185 | The bottom level has pointers to PageDesc. */ | |
186 | static void *l1_map[V_L1_SIZE]; | |
54936004 | 187 | |
e2eef170 | 188 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e AK |
189 | typedef struct PhysPageEntry PhysPageEntry; |
190 | ||
5312bd8b AK |
191 | static MemoryRegionSection *phys_sections; |
192 | static unsigned phys_sections_nb, phys_sections_nb_alloc; | |
193 | static uint16_t phys_section_unassigned; | |
194 | ||
4346ae3e AK |
195 | struct PhysPageEntry { |
196 | union { | |
5312bd8b | 197 | uint16_t leaf; /* index into phys_sections */ |
d6f2ea22 | 198 | uint16_t node; /* index into phys_map_nodes */ |
4346ae3e AK |
199 | } u; |
200 | }; | |
201 | ||
d6f2ea22 AK |
202 | /* Simple allocator for PhysPageEntry nodes */ |
203 | static PhysPageEntry (*phys_map_nodes)[L2_SIZE]; | |
204 | static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc; | |
205 | ||
206 | #define PHYS_MAP_NODE_NIL ((uint16_t)~0) | |
207 | ||
5cd2c5b6 | 208 | /* This is a multi-level map on the physical address space. |
06ef3525 | 209 | The bottom level has pointers to MemoryRegionSections. */ |
d6f2ea22 | 210 | static PhysPageEntry phys_map = { .u.node = PHYS_MAP_NODE_NIL }; |
6d9a1304 | 211 | |
e2eef170 | 212 | static void io_mem_init(void); |
62152b8a | 213 | static void memory_map_init(void); |
e2eef170 | 214 | |
33417e70 | 215 | /* io memory support */ |
a621f38d | 216 | MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES]; |
511d2b14 | 217 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
1ec9b909 | 218 | static MemoryRegion io_mem_watch; |
6658ffb8 | 219 | #endif |
33417e70 | 220 | |
34865134 | 221 | /* log support */ |
1e8b27ca JR |
222 | #ifdef WIN32 |
223 | static const char *logfilename = "qemu.log"; | |
224 | #else | |
d9b630fd | 225 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 226 | #endif |
34865134 FB |
227 | FILE *logfile; |
228 | int loglevel; | |
e735b91c | 229 | static int log_append = 0; |
34865134 | 230 | |
e3db7226 | 231 | /* statistics */ |
b3755a91 | 232 | #if !defined(CONFIG_USER_ONLY) |
e3db7226 | 233 | static int tlb_flush_count; |
b3755a91 | 234 | #endif |
e3db7226 FB |
235 | static int tb_flush_count; |
236 | static int tb_phys_invalidate_count; | |
237 | ||
7cb69cae FB |
238 | #ifdef _WIN32 |
239 | static void map_exec(void *addr, long size) | |
240 | { | |
241 | DWORD old_protect; | |
242 | VirtualProtect(addr, size, | |
243 | PAGE_EXECUTE_READWRITE, &old_protect); | |
244 | ||
245 | } | |
246 | #else | |
247 | static void map_exec(void *addr, long size) | |
248 | { | |
4369415f | 249 | unsigned long start, end, page_size; |
7cb69cae | 250 | |
4369415f | 251 | page_size = getpagesize(); |
7cb69cae | 252 | start = (unsigned long)addr; |
4369415f | 253 | start &= ~(page_size - 1); |
7cb69cae FB |
254 | |
255 | end = (unsigned long)addr + size; | |
4369415f FB |
256 | end += page_size - 1; |
257 | end &= ~(page_size - 1); | |
7cb69cae FB |
258 | |
259 | mprotect((void *)start, end - start, | |
260 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
261 | } | |
262 | #endif | |
263 | ||
b346ff46 | 264 | static void page_init(void) |
54936004 | 265 | { |
83fb7adf | 266 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 267 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
268 | #ifdef _WIN32 |
269 | { | |
270 | SYSTEM_INFO system_info; | |
271 | ||
272 | GetSystemInfo(&system_info); | |
273 | qemu_real_host_page_size = system_info.dwPageSize; | |
274 | } | |
275 | #else | |
276 | qemu_real_host_page_size = getpagesize(); | |
277 | #endif | |
83fb7adf FB |
278 | if (qemu_host_page_size == 0) |
279 | qemu_host_page_size = qemu_real_host_page_size; | |
280 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
281 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
83fb7adf | 282 | qemu_host_page_mask = ~(qemu_host_page_size - 1); |
50a9569b | 283 | |
2e9a5713 | 284 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
50a9569b | 285 | { |
f01576f1 JL |
286 | #ifdef HAVE_KINFO_GETVMMAP |
287 | struct kinfo_vmentry *freep; | |
288 | int i, cnt; | |
289 | ||
290 | freep = kinfo_getvmmap(getpid(), &cnt); | |
291 | if (freep) { | |
292 | mmap_lock(); | |
293 | for (i = 0; i < cnt; i++) { | |
294 | unsigned long startaddr, endaddr; | |
295 | ||
296 | startaddr = freep[i].kve_start; | |
297 | endaddr = freep[i].kve_end; | |
298 | if (h2g_valid(startaddr)) { | |
299 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
300 | ||
301 | if (h2g_valid(endaddr)) { | |
302 | endaddr = h2g(endaddr); | |
fd436907 | 303 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
304 | } else { |
305 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
306 | endaddr = ~0ul; | |
fd436907 | 307 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
308 | #endif |
309 | } | |
310 | } | |
311 | } | |
312 | free(freep); | |
313 | mmap_unlock(); | |
314 | } | |
315 | #else | |
50a9569b | 316 | FILE *f; |
50a9569b | 317 | |
0776590d | 318 | last_brk = (unsigned long)sbrk(0); |
5cd2c5b6 | 319 | |
fd436907 | 320 | f = fopen("/compat/linux/proc/self/maps", "r"); |
50a9569b | 321 | if (f) { |
5cd2c5b6 RH |
322 | mmap_lock(); |
323 | ||
50a9569b | 324 | do { |
5cd2c5b6 RH |
325 | unsigned long startaddr, endaddr; |
326 | int n; | |
327 | ||
328 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
329 | ||
330 | if (n == 2 && h2g_valid(startaddr)) { | |
331 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
332 | ||
333 | if (h2g_valid(endaddr)) { | |
334 | endaddr = h2g(endaddr); | |
335 | } else { | |
336 | endaddr = ~0ul; | |
337 | } | |
338 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
50a9569b AZ |
339 | } |
340 | } while (!feof(f)); | |
5cd2c5b6 | 341 | |
50a9569b | 342 | fclose(f); |
5cd2c5b6 | 343 | mmap_unlock(); |
50a9569b | 344 | } |
f01576f1 | 345 | #endif |
50a9569b AZ |
346 | } |
347 | #endif | |
54936004 FB |
348 | } |
349 | ||
41c1b1c9 | 350 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
54936004 | 351 | { |
41c1b1c9 PB |
352 | PageDesc *pd; |
353 | void **lp; | |
354 | int i; | |
355 | ||
5cd2c5b6 | 356 | #if defined(CONFIG_USER_ONLY) |
7267c094 | 357 | /* We can't use g_malloc because it may recurse into a locked mutex. */ |
5cd2c5b6 RH |
358 | # define ALLOC(P, SIZE) \ |
359 | do { \ | |
360 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
361 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
5cd2c5b6 RH |
362 | } while (0) |
363 | #else | |
364 | # define ALLOC(P, SIZE) \ | |
7267c094 | 365 | do { P = g_malloc0(SIZE); } while (0) |
17e2377a | 366 | #endif |
434929bf | 367 | |
5cd2c5b6 RH |
368 | /* Level 1. Always allocated. */ |
369 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
370 | ||
371 | /* Level 2..N-1. */ | |
372 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
373 | void **p = *lp; | |
374 | ||
375 | if (p == NULL) { | |
376 | if (!alloc) { | |
377 | return NULL; | |
378 | } | |
379 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
380 | *lp = p; | |
17e2377a | 381 | } |
5cd2c5b6 RH |
382 | |
383 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
384 | } | |
385 | ||
386 | pd = *lp; | |
387 | if (pd == NULL) { | |
388 | if (!alloc) { | |
389 | return NULL; | |
390 | } | |
391 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
392 | *lp = pd; | |
54936004 | 393 | } |
5cd2c5b6 RH |
394 | |
395 | #undef ALLOC | |
5cd2c5b6 RH |
396 | |
397 | return pd + (index & (L2_SIZE - 1)); | |
54936004 FB |
398 | } |
399 | ||
41c1b1c9 | 400 | static inline PageDesc *page_find(tb_page_addr_t index) |
54936004 | 401 | { |
5cd2c5b6 | 402 | return page_find_alloc(index, 0); |
fd6ce8f6 FB |
403 | } |
404 | ||
6d9a1304 | 405 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 406 | |
f7bf5461 | 407 | static void phys_map_node_reserve(unsigned nodes) |
d6f2ea22 | 408 | { |
f7bf5461 | 409 | if (phys_map_nodes_nb + nodes > phys_map_nodes_nb_alloc) { |
d6f2ea22 AK |
410 | typedef PhysPageEntry Node[L2_SIZE]; |
411 | phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc * 2, 16); | |
f7bf5461 AK |
412 | phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc, |
413 | phys_map_nodes_nb + nodes); | |
d6f2ea22 AK |
414 | phys_map_nodes = g_renew(Node, phys_map_nodes, |
415 | phys_map_nodes_nb_alloc); | |
416 | } | |
f7bf5461 AK |
417 | } |
418 | ||
419 | static uint16_t phys_map_node_alloc(void) | |
420 | { | |
421 | unsigned i; | |
422 | uint16_t ret; | |
423 | ||
424 | ret = phys_map_nodes_nb++; | |
425 | assert(ret != PHYS_MAP_NODE_NIL); | |
426 | assert(ret != phys_map_nodes_nb_alloc); | |
d6f2ea22 AK |
427 | for (i = 0; i < L2_SIZE; ++i) { |
428 | phys_map_nodes[ret][i].u.node = PHYS_MAP_NODE_NIL; | |
429 | } | |
f7bf5461 | 430 | return ret; |
d6f2ea22 AK |
431 | } |
432 | ||
433 | static void phys_map_nodes_reset(void) | |
434 | { | |
435 | phys_map_nodes_nb = 0; | |
436 | } | |
437 | ||
92e873b9 | 438 | |
f7bf5461 AK |
439 | static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t index, |
440 | uint16_t leaf, int level) | |
441 | { | |
442 | PhysPageEntry *p; | |
443 | int i; | |
108c49b8 | 444 | |
f7bf5461 AK |
445 | if (lp->u.node == PHYS_MAP_NODE_NIL) { |
446 | lp->u.node = phys_map_node_alloc(); | |
447 | p = phys_map_nodes[lp->u.node]; | |
448 | if (level == 0) { | |
449 | for (i = 0; i < L2_SIZE; i++) { | |
450 | p[i].u.leaf = phys_section_unassigned; | |
4346ae3e | 451 | } |
67c4d23c | 452 | } |
f7bf5461 AK |
453 | } else { |
454 | p = phys_map_nodes[lp->u.node]; | |
92e873b9 | 455 | } |
f7bf5461 AK |
456 | lp = &p[(index >> (level * L2_BITS)) & (L2_SIZE - 1)]; |
457 | ||
458 | if (level == 0) { | |
459 | lp->u.leaf = leaf; | |
460 | } else { | |
461 | phys_page_set_level(lp, index, leaf, level - 1); | |
462 | } | |
463 | } | |
464 | ||
465 | static void phys_page_set(target_phys_addr_t index, uint16_t leaf) | |
466 | { | |
467 | phys_map_node_reserve(P_L2_LEVELS); | |
5cd2c5b6 | 468 | |
f7bf5461 | 469 | phys_page_set_level(&phys_map, index, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
470 | } |
471 | ||
06ef3525 | 472 | static MemoryRegionSection phys_page_find(target_phys_addr_t index) |
92e873b9 | 473 | { |
31ab2b4a AK |
474 | PhysPageEntry lp = phys_map; |
475 | PhysPageEntry *p; | |
476 | int i; | |
06ef3525 AK |
477 | MemoryRegionSection section; |
478 | target_phys_addr_t delta; | |
31ab2b4a | 479 | uint16_t s_index = phys_section_unassigned; |
f1f6e3b8 | 480 | |
31ab2b4a AK |
481 | for (i = P_L2_LEVELS - 1; i >= 0; i--) { |
482 | if (lp.u.node == PHYS_MAP_NODE_NIL) { | |
483 | goto not_found; | |
484 | } | |
485 | p = phys_map_nodes[lp.u.node]; | |
486 | lp = p[(index >> (i * L2_BITS)) & (L2_SIZE - 1)]; | |
5312bd8b | 487 | } |
31ab2b4a AK |
488 | |
489 | s_index = lp.u.leaf; | |
490 | not_found: | |
06ef3525 | 491 | section = phys_sections[s_index]; |
5312bd8b | 492 | index <<= TARGET_PAGE_BITS; |
06ef3525 AK |
493 | assert(section.offset_within_address_space <= index |
494 | && index <= section.offset_within_address_space + section.size-1); | |
495 | delta = index - section.offset_within_address_space; | |
496 | section.offset_within_address_space += delta; | |
497 | section.offset_within_region += delta; | |
498 | section.size -= delta; | |
499 | return section; | |
92e873b9 FB |
500 | } |
501 | ||
c227f099 AL |
502 | static void tlb_protect_code(ram_addr_t ram_addr); |
503 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 504 | target_ulong vaddr); |
c8a706fe PB |
505 | #define mmap_lock() do { } while(0) |
506 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 507 | #endif |
fd6ce8f6 | 508 | |
4369415f FB |
509 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
510 | ||
511 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 512 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
513 | user mode. It will change when a dedicated libc will be used */ |
514 | #define USE_STATIC_CODE_GEN_BUFFER | |
515 | #endif | |
516 | ||
517 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
ebf50fb3 AJ |
518 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
519 | __attribute__((aligned (CODE_GEN_ALIGN))); | |
4369415f FB |
520 | #endif |
521 | ||
8fcd3692 | 522 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 523 | { |
4369415f FB |
524 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
525 | code_gen_buffer = static_code_gen_buffer; | |
526 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
527 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
528 | #else | |
26a5f13b FB |
529 | code_gen_buffer_size = tb_size; |
530 | if (code_gen_buffer_size == 0) { | |
4369415f | 531 | #if defined(CONFIG_USER_ONLY) |
4369415f FB |
532 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
533 | #else | |
ccbb4d44 | 534 | /* XXX: needs adjustments */ |
94a6b54f | 535 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 536 | #endif |
26a5f13b FB |
537 | } |
538 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
539 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
540 | /* The code gen buffer location may have constraints depending on | |
541 | the host cpu and OS */ | |
542 | #if defined(__linux__) | |
543 | { | |
544 | int flags; | |
141ac468 BS |
545 | void *start = NULL; |
546 | ||
26a5f13b FB |
547 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
548 | #if defined(__x86_64__) | |
549 | flags |= MAP_32BIT; | |
550 | /* Cannot map more than that */ | |
551 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
552 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
553 | #elif defined(__sparc_v9__) |
554 | // Map the buffer below 2G, so we can use direct calls and branches | |
555 | flags |= MAP_FIXED; | |
556 | start = (void *) 0x60000000UL; | |
557 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
558 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 559 | #elif defined(__arm__) |
5c84bd90 | 560 | /* Keep the buffer no bigger than 16MB to branch between blocks */ |
1cb0661e AZ |
561 | if (code_gen_buffer_size > 16 * 1024 * 1024) |
562 | code_gen_buffer_size = 16 * 1024 * 1024; | |
eba0b893 RH |
563 | #elif defined(__s390x__) |
564 | /* Map the buffer so that we can use direct calls and branches. */ | |
565 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
566 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { | |
567 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; | |
568 | } | |
569 | start = (void *)0x90000000UL; | |
26a5f13b | 570 | #endif |
141ac468 BS |
571 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
572 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
573 | flags, -1, 0); |
574 | if (code_gen_buffer == MAP_FAILED) { | |
575 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
576 | exit(1); | |
577 | } | |
578 | } | |
cbb608a5 | 579 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
9f4b09a4 TN |
580 | || defined(__DragonFly__) || defined(__OpenBSD__) \ |
581 | || defined(__NetBSD__) | |
06e67a82 AL |
582 | { |
583 | int flags; | |
584 | void *addr = NULL; | |
585 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
586 | #if defined(__x86_64__) | |
587 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
588 | * 0x40000000 is free */ | |
589 | flags |= MAP_FIXED; | |
590 | addr = (void *)0x40000000; | |
591 | /* Cannot map more than that */ | |
592 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
593 | code_gen_buffer_size = (800 * 1024 * 1024); | |
4cd31ad2 BS |
594 | #elif defined(__sparc_v9__) |
595 | // Map the buffer below 2G, so we can use direct calls and branches | |
596 | flags |= MAP_FIXED; | |
597 | addr = (void *) 0x60000000UL; | |
598 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { | |
599 | code_gen_buffer_size = (512 * 1024 * 1024); | |
600 | } | |
06e67a82 AL |
601 | #endif |
602 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
603 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
604 | flags, -1, 0); | |
605 | if (code_gen_buffer == MAP_FAILED) { | |
606 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
607 | exit(1); | |
608 | } | |
609 | } | |
26a5f13b | 610 | #else |
7267c094 | 611 | code_gen_buffer = g_malloc(code_gen_buffer_size); |
26a5f13b FB |
612 | map_exec(code_gen_buffer, code_gen_buffer_size); |
613 | #endif | |
4369415f | 614 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b | 615 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
a884da8a PM |
616 | code_gen_buffer_max_size = code_gen_buffer_size - |
617 | (TCG_MAX_OP_SIZE * OPC_BUF_SIZE); | |
26a5f13b | 618 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
7267c094 | 619 | tbs = g_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); |
26a5f13b FB |
620 | } |
621 | ||
622 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
623 | (in bytes) allocated to the translation buffer. Zero means default | |
624 | size. */ | |
d5ab9713 | 625 | void tcg_exec_init(unsigned long tb_size) |
26a5f13b | 626 | { |
26a5f13b FB |
627 | cpu_gen_init(); |
628 | code_gen_alloc(tb_size); | |
629 | code_gen_ptr = code_gen_buffer; | |
4369415f | 630 | page_init(); |
9002ec79 RH |
631 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
632 | /* There's no guest base to take into account, so go ahead and | |
633 | initialize the prologue now. */ | |
634 | tcg_prologue_init(&tcg_ctx); | |
635 | #endif | |
26a5f13b FB |
636 | } |
637 | ||
d5ab9713 JK |
638 | bool tcg_enabled(void) |
639 | { | |
640 | return code_gen_buffer != NULL; | |
641 | } | |
642 | ||
643 | void cpu_exec_init_all(void) | |
644 | { | |
645 | #if !defined(CONFIG_USER_ONLY) | |
646 | memory_map_init(); | |
647 | io_mem_init(); | |
648 | #endif | |
649 | } | |
650 | ||
9656f324 PB |
651 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
652 | ||
e59fb374 | 653 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
654 | { |
655 | CPUState *env = opaque; | |
9656f324 | 656 | |
3098dba0 AJ |
657 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
658 | version_id is increased. */ | |
659 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
660 | tlb_flush(env, 1); |
661 | ||
662 | return 0; | |
663 | } | |
e7f4eff7 JQ |
664 | |
665 | static const VMStateDescription vmstate_cpu_common = { | |
666 | .name = "cpu_common", | |
667 | .version_id = 1, | |
668 | .minimum_version_id = 1, | |
669 | .minimum_version_id_old = 1, | |
e7f4eff7 JQ |
670 | .post_load = cpu_common_post_load, |
671 | .fields = (VMStateField []) { | |
672 | VMSTATE_UINT32(halted, CPUState), | |
673 | VMSTATE_UINT32(interrupt_request, CPUState), | |
674 | VMSTATE_END_OF_LIST() | |
675 | } | |
676 | }; | |
9656f324 PB |
677 | #endif |
678 | ||
950f1472 GC |
679 | CPUState *qemu_get_cpu(int cpu) |
680 | { | |
681 | CPUState *env = first_cpu; | |
682 | ||
683 | while (env) { | |
684 | if (env->cpu_index == cpu) | |
685 | break; | |
686 | env = env->next_cpu; | |
687 | } | |
688 | ||
689 | return env; | |
690 | } | |
691 | ||
6a00d601 | 692 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 693 | { |
6a00d601 FB |
694 | CPUState **penv; |
695 | int cpu_index; | |
696 | ||
c2764719 PB |
697 | #if defined(CONFIG_USER_ONLY) |
698 | cpu_list_lock(); | |
699 | #endif | |
6a00d601 FB |
700 | env->next_cpu = NULL; |
701 | penv = &first_cpu; | |
702 | cpu_index = 0; | |
703 | while (*penv != NULL) { | |
1e9fa730 | 704 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
705 | cpu_index++; |
706 | } | |
707 | env->cpu_index = cpu_index; | |
268a362c | 708 | env->numa_node = 0; |
72cf2d4f BS |
709 | QTAILQ_INIT(&env->breakpoints); |
710 | QTAILQ_INIT(&env->watchpoints); | |
dc7a09cf JK |
711 | #ifndef CONFIG_USER_ONLY |
712 | env->thread_id = qemu_get_thread_id(); | |
713 | #endif | |
6a00d601 | 714 | *penv = env; |
c2764719 PB |
715 | #if defined(CONFIG_USER_ONLY) |
716 | cpu_list_unlock(); | |
717 | #endif | |
b3c7724c | 718 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
0be71e32 AW |
719 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
720 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, | |
b3c7724c PB |
721 | cpu_save, cpu_load, env); |
722 | #endif | |
fd6ce8f6 FB |
723 | } |
724 | ||
d1a1eb74 TG |
725 | /* Allocate a new translation block. Flush the translation buffer if |
726 | too many translation blocks or too much generated code. */ | |
727 | static TranslationBlock *tb_alloc(target_ulong pc) | |
728 | { | |
729 | TranslationBlock *tb; | |
730 | ||
731 | if (nb_tbs >= code_gen_max_blocks || | |
732 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
733 | return NULL; | |
734 | tb = &tbs[nb_tbs++]; | |
735 | tb->pc = pc; | |
736 | tb->cflags = 0; | |
737 | return tb; | |
738 | } | |
739 | ||
740 | void tb_free(TranslationBlock *tb) | |
741 | { | |
742 | /* In practice this is mostly used for single use temporary TB | |
743 | Ignore the hard cases and just back up if this TB happens to | |
744 | be the last one generated. */ | |
745 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
746 | code_gen_ptr = tb->tc_ptr; | |
747 | nb_tbs--; | |
748 | } | |
749 | } | |
750 | ||
9fa3e853 FB |
751 | static inline void invalidate_page_bitmap(PageDesc *p) |
752 | { | |
753 | if (p->code_bitmap) { | |
7267c094 | 754 | g_free(p->code_bitmap); |
9fa3e853 FB |
755 | p->code_bitmap = NULL; |
756 | } | |
757 | p->code_write_count = 0; | |
758 | } | |
759 | ||
5cd2c5b6 RH |
760 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
761 | ||
762 | static void page_flush_tb_1 (int level, void **lp) | |
fd6ce8f6 | 763 | { |
5cd2c5b6 | 764 | int i; |
fd6ce8f6 | 765 | |
5cd2c5b6 RH |
766 | if (*lp == NULL) { |
767 | return; | |
768 | } | |
769 | if (level == 0) { | |
770 | PageDesc *pd = *lp; | |
7296abac | 771 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
772 | pd[i].first_tb = NULL; |
773 | invalidate_page_bitmap(pd + i); | |
fd6ce8f6 | 774 | } |
5cd2c5b6 RH |
775 | } else { |
776 | void **pp = *lp; | |
7296abac | 777 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
778 | page_flush_tb_1 (level - 1, pp + i); |
779 | } | |
780 | } | |
781 | } | |
782 | ||
783 | static void page_flush_tb(void) | |
784 | { | |
785 | int i; | |
786 | for (i = 0; i < V_L1_SIZE; i++) { | |
787 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
fd6ce8f6 FB |
788 | } |
789 | } | |
790 | ||
791 | /* flush all the translation blocks */ | |
d4e8164f | 792 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 793 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 794 | { |
6a00d601 | 795 | CPUState *env; |
0124311e | 796 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
797 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
798 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
799 | nb_tbs, nb_tbs > 0 ? | |
800 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 801 | #endif |
26a5f13b | 802 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
803 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
804 | ||
fd6ce8f6 | 805 | nb_tbs = 0; |
3b46e624 | 806 | |
6a00d601 FB |
807 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
808 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
809 | } | |
9fa3e853 | 810 | |
8a8a608f | 811 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 812 | page_flush_tb(); |
9fa3e853 | 813 | |
fd6ce8f6 | 814 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
815 | /* XXX: flush processor icache at this point if cache flush is |
816 | expensive */ | |
e3db7226 | 817 | tb_flush_count++; |
fd6ce8f6 FB |
818 | } |
819 | ||
820 | #ifdef DEBUG_TB_CHECK | |
821 | ||
bc98a7ef | 822 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
823 | { |
824 | TranslationBlock *tb; | |
825 | int i; | |
826 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
827 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
828 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
829 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
830 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
831 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
832 | " PC=%08lx size=%04x\n", | |
99773bd4 | 833 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
834 | } |
835 | } | |
836 | } | |
837 | } | |
838 | ||
839 | /* verify that all the pages have correct rights for code */ | |
840 | static void tb_page_check(void) | |
841 | { | |
842 | TranslationBlock *tb; | |
843 | int i, flags1, flags2; | |
3b46e624 | 844 | |
99773bd4 PB |
845 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
846 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
847 | flags1 = page_get_flags(tb->pc); |
848 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
849 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
850 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 851 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
852 | } |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | #endif | |
858 | ||
859 | /* invalidate one TB */ | |
860 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
861 | int next_offset) | |
862 | { | |
863 | TranslationBlock *tb1; | |
864 | for(;;) { | |
865 | tb1 = *ptb; | |
866 | if (tb1 == tb) { | |
867 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
868 | break; | |
869 | } | |
870 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
871 | } | |
872 | } | |
873 | ||
9fa3e853 FB |
874 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
875 | { | |
876 | TranslationBlock *tb1; | |
877 | unsigned int n1; | |
878 | ||
879 | for(;;) { | |
880 | tb1 = *ptb; | |
881 | n1 = (long)tb1 & 3; | |
882 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
883 | if (tb1 == tb) { | |
884 | *ptb = tb1->page_next[n1]; | |
885 | break; | |
886 | } | |
887 | ptb = &tb1->page_next[n1]; | |
888 | } | |
889 | } | |
890 | ||
d4e8164f FB |
891 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
892 | { | |
893 | TranslationBlock *tb1, **ptb; | |
894 | unsigned int n1; | |
895 | ||
896 | ptb = &tb->jmp_next[n]; | |
897 | tb1 = *ptb; | |
898 | if (tb1) { | |
899 | /* find tb(n) in circular list */ | |
900 | for(;;) { | |
901 | tb1 = *ptb; | |
902 | n1 = (long)tb1 & 3; | |
903 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
904 | if (n1 == n && tb1 == tb) | |
905 | break; | |
906 | if (n1 == 2) { | |
907 | ptb = &tb1->jmp_first; | |
908 | } else { | |
909 | ptb = &tb1->jmp_next[n1]; | |
910 | } | |
911 | } | |
912 | /* now we can suppress tb(n) from the list */ | |
913 | *ptb = tb->jmp_next[n]; | |
914 | ||
915 | tb->jmp_next[n] = NULL; | |
916 | } | |
917 | } | |
918 | ||
919 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
920 | another TB */ | |
921 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
922 | { | |
923 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
924 | } | |
925 | ||
41c1b1c9 | 926 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
fd6ce8f6 | 927 | { |
6a00d601 | 928 | CPUState *env; |
8a40a180 | 929 | PageDesc *p; |
d4e8164f | 930 | unsigned int h, n1; |
41c1b1c9 | 931 | tb_page_addr_t phys_pc; |
8a40a180 | 932 | TranslationBlock *tb1, *tb2; |
3b46e624 | 933 | |
8a40a180 FB |
934 | /* remove the TB from the hash list */ |
935 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
936 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 937 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
938 | offsetof(TranslationBlock, phys_hash_next)); |
939 | ||
940 | /* remove the TB from the page list */ | |
941 | if (tb->page_addr[0] != page_addr) { | |
942 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
943 | tb_page_remove(&p->first_tb, tb); | |
944 | invalidate_page_bitmap(p); | |
945 | } | |
946 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
947 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
948 | tb_page_remove(&p->first_tb, tb); | |
949 | invalidate_page_bitmap(p); | |
950 | } | |
951 | ||
36bdbe54 | 952 | tb_invalidated_flag = 1; |
59817ccb | 953 | |
fd6ce8f6 | 954 | /* remove the TB from the hash list */ |
8a40a180 | 955 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
956 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
957 | if (env->tb_jmp_cache[h] == tb) | |
958 | env->tb_jmp_cache[h] = NULL; | |
959 | } | |
d4e8164f FB |
960 | |
961 | /* suppress this TB from the two jump lists */ | |
962 | tb_jmp_remove(tb, 0); | |
963 | tb_jmp_remove(tb, 1); | |
964 | ||
965 | /* suppress any remaining jumps to this TB */ | |
966 | tb1 = tb->jmp_first; | |
967 | for(;;) { | |
968 | n1 = (long)tb1 & 3; | |
969 | if (n1 == 2) | |
970 | break; | |
971 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
972 | tb2 = tb1->jmp_next[n1]; | |
973 | tb_reset_jump(tb1, n1); | |
974 | tb1->jmp_next[n1] = NULL; | |
975 | tb1 = tb2; | |
976 | } | |
977 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 978 | |
e3db7226 | 979 | tb_phys_invalidate_count++; |
9fa3e853 FB |
980 | } |
981 | ||
982 | static inline void set_bits(uint8_t *tab, int start, int len) | |
983 | { | |
984 | int end, mask, end1; | |
985 | ||
986 | end = start + len; | |
987 | tab += start >> 3; | |
988 | mask = 0xff << (start & 7); | |
989 | if ((start & ~7) == (end & ~7)) { | |
990 | if (start < end) { | |
991 | mask &= ~(0xff << (end & 7)); | |
992 | *tab |= mask; | |
993 | } | |
994 | } else { | |
995 | *tab++ |= mask; | |
996 | start = (start + 8) & ~7; | |
997 | end1 = end & ~7; | |
998 | while (start < end1) { | |
999 | *tab++ = 0xff; | |
1000 | start += 8; | |
1001 | } | |
1002 | if (start < end) { | |
1003 | mask = ~(0xff << (end & 7)); | |
1004 | *tab |= mask; | |
1005 | } | |
1006 | } | |
1007 | } | |
1008 | ||
1009 | static void build_page_bitmap(PageDesc *p) | |
1010 | { | |
1011 | int n, tb_start, tb_end; | |
1012 | TranslationBlock *tb; | |
3b46e624 | 1013 | |
7267c094 | 1014 | p->code_bitmap = g_malloc0(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
1015 | |
1016 | tb = p->first_tb; | |
1017 | while (tb != NULL) { | |
1018 | n = (long)tb & 3; | |
1019 | tb = (TranslationBlock *)((long)tb & ~3); | |
1020 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1021 | if (n == 0) { | |
1022 | /* NOTE: tb_end may be after the end of the page, but | |
1023 | it is not a problem */ | |
1024 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
1025 | tb_end = tb_start + tb->size; | |
1026 | if (tb_end > TARGET_PAGE_SIZE) | |
1027 | tb_end = TARGET_PAGE_SIZE; | |
1028 | } else { | |
1029 | tb_start = 0; | |
1030 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1031 | } | |
1032 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
1033 | tb = tb->page_next[n]; | |
1034 | } | |
1035 | } | |
1036 | ||
2e70f6ef PB |
1037 | TranslationBlock *tb_gen_code(CPUState *env, |
1038 | target_ulong pc, target_ulong cs_base, | |
1039 | int flags, int cflags) | |
d720b93d FB |
1040 | { |
1041 | TranslationBlock *tb; | |
1042 | uint8_t *tc_ptr; | |
41c1b1c9 PB |
1043 | tb_page_addr_t phys_pc, phys_page2; |
1044 | target_ulong virt_page2; | |
d720b93d FB |
1045 | int code_gen_size; |
1046 | ||
41c1b1c9 | 1047 | phys_pc = get_page_addr_code(env, pc); |
c27004ec | 1048 | tb = tb_alloc(pc); |
d720b93d FB |
1049 | if (!tb) { |
1050 | /* flush must be done */ | |
1051 | tb_flush(env); | |
1052 | /* cannot fail at this point */ | |
c27004ec | 1053 | tb = tb_alloc(pc); |
2e70f6ef PB |
1054 | /* Don't forget to invalidate previous TB info. */ |
1055 | tb_invalidated_flag = 1; | |
d720b93d FB |
1056 | } |
1057 | tc_ptr = code_gen_ptr; | |
1058 | tb->tc_ptr = tc_ptr; | |
1059 | tb->cs_base = cs_base; | |
1060 | tb->flags = flags; | |
1061 | tb->cflags = cflags; | |
d07bde88 | 1062 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 1063 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 1064 | |
d720b93d | 1065 | /* check next page if needed */ |
c27004ec | 1066 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 1067 | phys_page2 = -1; |
c27004ec | 1068 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
41c1b1c9 | 1069 | phys_page2 = get_page_addr_code(env, virt_page2); |
d720b93d | 1070 | } |
41c1b1c9 | 1071 | tb_link_page(tb, phys_pc, phys_page2); |
2e70f6ef | 1072 | return tb; |
d720b93d | 1073 | } |
3b46e624 | 1074 | |
9fa3e853 FB |
1075 | /* invalidate all TBs which intersect with the target physical page |
1076 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
1077 | the same physical page. 'is_cpu_write_access' should be true if called |
1078 | from a real cpu write access: the virtual CPU will exit the current | |
1079 | TB if code is modified inside this TB. */ | |
41c1b1c9 | 1080 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
d720b93d FB |
1081 | int is_cpu_write_access) |
1082 | { | |
6b917547 | 1083 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 1084 | CPUState *env = cpu_single_env; |
41c1b1c9 | 1085 | tb_page_addr_t tb_start, tb_end; |
6b917547 AL |
1086 | PageDesc *p; |
1087 | int n; | |
1088 | #ifdef TARGET_HAS_PRECISE_SMC | |
1089 | int current_tb_not_found = is_cpu_write_access; | |
1090 | TranslationBlock *current_tb = NULL; | |
1091 | int current_tb_modified = 0; | |
1092 | target_ulong current_pc = 0; | |
1093 | target_ulong current_cs_base = 0; | |
1094 | int current_flags = 0; | |
1095 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1096 | |
1097 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 1098 | if (!p) |
9fa3e853 | 1099 | return; |
5fafdf24 | 1100 | if (!p->code_bitmap && |
d720b93d FB |
1101 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
1102 | is_cpu_write_access) { | |
9fa3e853 FB |
1103 | /* build code bitmap */ |
1104 | build_page_bitmap(p); | |
1105 | } | |
1106 | ||
1107 | /* we remove all the TBs in the range [start, end[ */ | |
1108 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
1109 | tb = p->first_tb; | |
1110 | while (tb != NULL) { | |
1111 | n = (long)tb & 3; | |
1112 | tb = (TranslationBlock *)((long)tb & ~3); | |
1113 | tb_next = tb->page_next[n]; | |
1114 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1115 | if (n == 0) { | |
1116 | /* NOTE: tb_end may be after the end of the page, but | |
1117 | it is not a problem */ | |
1118 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1119 | tb_end = tb_start + tb->size; | |
1120 | } else { | |
1121 | tb_start = tb->page_addr[1]; | |
1122 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1123 | } | |
1124 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
1125 | #ifdef TARGET_HAS_PRECISE_SMC |
1126 | if (current_tb_not_found) { | |
1127 | current_tb_not_found = 0; | |
1128 | current_tb = NULL; | |
2e70f6ef | 1129 | if (env->mem_io_pc) { |
d720b93d | 1130 | /* now we have a real cpu fault */ |
2e70f6ef | 1131 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
1132 | } |
1133 | } | |
1134 | if (current_tb == tb && | |
2e70f6ef | 1135 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1136 | /* If we are modifying the current TB, we must stop |
1137 | its execution. We could be more precise by checking | |
1138 | that the modification is after the current PC, but it | |
1139 | would require a specialized function to partially | |
1140 | restore the CPU state */ | |
3b46e624 | 1141 | |
d720b93d | 1142 | current_tb_modified = 1; |
618ba8e6 | 1143 | cpu_restore_state(current_tb, env, env->mem_io_pc); |
6b917547 AL |
1144 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1145 | ¤t_flags); | |
d720b93d FB |
1146 | } |
1147 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
1148 | /* we need to do that to handle the case where a signal |
1149 | occurs while doing tb_phys_invalidate() */ | |
1150 | saved_tb = NULL; | |
1151 | if (env) { | |
1152 | saved_tb = env->current_tb; | |
1153 | env->current_tb = NULL; | |
1154 | } | |
9fa3e853 | 1155 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
1156 | if (env) { |
1157 | env->current_tb = saved_tb; | |
1158 | if (env->interrupt_request && env->current_tb) | |
1159 | cpu_interrupt(env, env->interrupt_request); | |
1160 | } | |
9fa3e853 FB |
1161 | } |
1162 | tb = tb_next; | |
1163 | } | |
1164 | #if !defined(CONFIG_USER_ONLY) | |
1165 | /* if no code remaining, no need to continue to use slow writes */ | |
1166 | if (!p->first_tb) { | |
1167 | invalidate_page_bitmap(p); | |
d720b93d | 1168 | if (is_cpu_write_access) { |
2e70f6ef | 1169 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1170 | } |
1171 | } | |
1172 | #endif | |
1173 | #ifdef TARGET_HAS_PRECISE_SMC | |
1174 | if (current_tb_modified) { | |
1175 | /* we generate a block containing just the instruction | |
1176 | modifying the memory. It will ensure that it cannot modify | |
1177 | itself */ | |
ea1c1802 | 1178 | env->current_tb = NULL; |
2e70f6ef | 1179 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1180 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1181 | } |
fd6ce8f6 | 1182 | #endif |
9fa3e853 | 1183 | } |
fd6ce8f6 | 1184 | |
9fa3e853 | 1185 | /* len must be <= 8 and start must be a multiple of len */ |
41c1b1c9 | 1186 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
9fa3e853 FB |
1187 | { |
1188 | PageDesc *p; | |
1189 | int offset, b; | |
59817ccb | 1190 | #if 0 |
a4193c8a | 1191 | if (1) { |
93fcfe39 AL |
1192 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1193 | cpu_single_env->mem_io_vaddr, len, | |
1194 | cpu_single_env->eip, | |
1195 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1196 | } |
1197 | #endif | |
9fa3e853 | 1198 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1199 | if (!p) |
9fa3e853 FB |
1200 | return; |
1201 | if (p->code_bitmap) { | |
1202 | offset = start & ~TARGET_PAGE_MASK; | |
1203 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1204 | if (b & ((1 << len) - 1)) | |
1205 | goto do_invalidate; | |
1206 | } else { | |
1207 | do_invalidate: | |
d720b93d | 1208 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1209 | } |
1210 | } | |
1211 | ||
9fa3e853 | 1212 | #if !defined(CONFIG_SOFTMMU) |
41c1b1c9 | 1213 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d720b93d | 1214 | unsigned long pc, void *puc) |
9fa3e853 | 1215 | { |
6b917547 | 1216 | TranslationBlock *tb; |
9fa3e853 | 1217 | PageDesc *p; |
6b917547 | 1218 | int n; |
d720b93d | 1219 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1220 | TranslationBlock *current_tb = NULL; |
d720b93d | 1221 | CPUState *env = cpu_single_env; |
6b917547 AL |
1222 | int current_tb_modified = 0; |
1223 | target_ulong current_pc = 0; | |
1224 | target_ulong current_cs_base = 0; | |
1225 | int current_flags = 0; | |
d720b93d | 1226 | #endif |
9fa3e853 FB |
1227 | |
1228 | addr &= TARGET_PAGE_MASK; | |
1229 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1230 | if (!p) |
9fa3e853 FB |
1231 | return; |
1232 | tb = p->first_tb; | |
d720b93d FB |
1233 | #ifdef TARGET_HAS_PRECISE_SMC |
1234 | if (tb && pc != 0) { | |
1235 | current_tb = tb_find_pc(pc); | |
1236 | } | |
1237 | #endif | |
9fa3e853 FB |
1238 | while (tb != NULL) { |
1239 | n = (long)tb & 3; | |
1240 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1241 | #ifdef TARGET_HAS_PRECISE_SMC |
1242 | if (current_tb == tb && | |
2e70f6ef | 1243 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1244 | /* If we are modifying the current TB, we must stop |
1245 | its execution. We could be more precise by checking | |
1246 | that the modification is after the current PC, but it | |
1247 | would require a specialized function to partially | |
1248 | restore the CPU state */ | |
3b46e624 | 1249 | |
d720b93d | 1250 | current_tb_modified = 1; |
618ba8e6 | 1251 | cpu_restore_state(current_tb, env, pc); |
6b917547 AL |
1252 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1253 | ¤t_flags); | |
d720b93d FB |
1254 | } |
1255 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1256 | tb_phys_invalidate(tb, addr); |
1257 | tb = tb->page_next[n]; | |
1258 | } | |
fd6ce8f6 | 1259 | p->first_tb = NULL; |
d720b93d FB |
1260 | #ifdef TARGET_HAS_PRECISE_SMC |
1261 | if (current_tb_modified) { | |
1262 | /* we generate a block containing just the instruction | |
1263 | modifying the memory. It will ensure that it cannot modify | |
1264 | itself */ | |
ea1c1802 | 1265 | env->current_tb = NULL; |
2e70f6ef | 1266 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1267 | cpu_resume_from_signal(env, puc); |
1268 | } | |
1269 | #endif | |
fd6ce8f6 | 1270 | } |
9fa3e853 | 1271 | #endif |
fd6ce8f6 FB |
1272 | |
1273 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1274 | static inline void tb_alloc_page(TranslationBlock *tb, |
41c1b1c9 | 1275 | unsigned int n, tb_page_addr_t page_addr) |
fd6ce8f6 FB |
1276 | { |
1277 | PageDesc *p; | |
4429ab44 JQ |
1278 | #ifndef CONFIG_USER_ONLY |
1279 | bool page_already_protected; | |
1280 | #endif | |
9fa3e853 FB |
1281 | |
1282 | tb->page_addr[n] = page_addr; | |
5cd2c5b6 | 1283 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
9fa3e853 | 1284 | tb->page_next[n] = p->first_tb; |
4429ab44 JQ |
1285 | #ifndef CONFIG_USER_ONLY |
1286 | page_already_protected = p->first_tb != NULL; | |
1287 | #endif | |
9fa3e853 FB |
1288 | p->first_tb = (TranslationBlock *)((long)tb | n); |
1289 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1290 | |
107db443 | 1291 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1292 | |
9fa3e853 | 1293 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1294 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1295 | target_ulong addr; |
1296 | PageDesc *p2; | |
9fa3e853 FB |
1297 | int prot; |
1298 | ||
fd6ce8f6 FB |
1299 | /* force the host page as non writable (writes will have a |
1300 | page fault + mprotect overhead) */ | |
53a5960a | 1301 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1302 | prot = 0; |
53a5960a PB |
1303 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1304 | addr += TARGET_PAGE_SIZE) { | |
1305 | ||
1306 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1307 | if (!p2) | |
1308 | continue; | |
1309 | prot |= p2->flags; | |
1310 | p2->flags &= ~PAGE_WRITE; | |
53a5960a | 1311 | } |
5fafdf24 | 1312 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1313 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1314 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1315 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1316 | page_addr); |
fd6ce8f6 | 1317 | #endif |
fd6ce8f6 | 1318 | } |
9fa3e853 FB |
1319 | #else |
1320 | /* if some code is already present, then the pages are already | |
1321 | protected. So we handle the case where only the first TB is | |
1322 | allocated in a physical page */ | |
4429ab44 | 1323 | if (!page_already_protected) { |
6a00d601 | 1324 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1325 | } |
1326 | #endif | |
d720b93d FB |
1327 | |
1328 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1329 | } |
1330 | ||
9fa3e853 FB |
1331 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1332 | (-1) to indicate that only one page contains the TB. */ | |
41c1b1c9 PB |
1333 | void tb_link_page(TranslationBlock *tb, |
1334 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) | |
d4e8164f | 1335 | { |
9fa3e853 FB |
1336 | unsigned int h; |
1337 | TranslationBlock **ptb; | |
1338 | ||
c8a706fe PB |
1339 | /* Grab the mmap lock to stop another thread invalidating this TB |
1340 | before we are done. */ | |
1341 | mmap_lock(); | |
9fa3e853 FB |
1342 | /* add in the physical hash table */ |
1343 | h = tb_phys_hash_func(phys_pc); | |
1344 | ptb = &tb_phys_hash[h]; | |
1345 | tb->phys_hash_next = *ptb; | |
1346 | *ptb = tb; | |
fd6ce8f6 FB |
1347 | |
1348 | /* add in the page list */ | |
9fa3e853 FB |
1349 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1350 | if (phys_page2 != -1) | |
1351 | tb_alloc_page(tb, 1, phys_page2); | |
1352 | else | |
1353 | tb->page_addr[1] = -1; | |
9fa3e853 | 1354 | |
d4e8164f FB |
1355 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1356 | tb->jmp_next[0] = NULL; | |
1357 | tb->jmp_next[1] = NULL; | |
1358 | ||
1359 | /* init original jump addresses */ | |
1360 | if (tb->tb_next_offset[0] != 0xffff) | |
1361 | tb_reset_jump(tb, 0); | |
1362 | if (tb->tb_next_offset[1] != 0xffff) | |
1363 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1364 | |
1365 | #ifdef DEBUG_TB_CHECK | |
1366 | tb_page_check(); | |
1367 | #endif | |
c8a706fe | 1368 | mmap_unlock(); |
fd6ce8f6 FB |
1369 | } |
1370 | ||
9fa3e853 FB |
1371 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1372 | tb[1].tc_ptr. Return NULL if not found */ | |
1373 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1374 | { |
9fa3e853 FB |
1375 | int m_min, m_max, m; |
1376 | unsigned long v; | |
1377 | TranslationBlock *tb; | |
a513fe19 FB |
1378 | |
1379 | if (nb_tbs <= 0) | |
1380 | return NULL; | |
1381 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1382 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1383 | return NULL; | |
1384 | /* binary search (cf Knuth) */ | |
1385 | m_min = 0; | |
1386 | m_max = nb_tbs - 1; | |
1387 | while (m_min <= m_max) { | |
1388 | m = (m_min + m_max) >> 1; | |
1389 | tb = &tbs[m]; | |
1390 | v = (unsigned long)tb->tc_ptr; | |
1391 | if (v == tc_ptr) | |
1392 | return tb; | |
1393 | else if (tc_ptr < v) { | |
1394 | m_max = m - 1; | |
1395 | } else { | |
1396 | m_min = m + 1; | |
1397 | } | |
5fafdf24 | 1398 | } |
a513fe19 FB |
1399 | return &tbs[m_max]; |
1400 | } | |
7501267e | 1401 | |
ea041c0e FB |
1402 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1403 | ||
1404 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1405 | { | |
1406 | TranslationBlock *tb1, *tb_next, **ptb; | |
1407 | unsigned int n1; | |
1408 | ||
1409 | tb1 = tb->jmp_next[n]; | |
1410 | if (tb1 != NULL) { | |
1411 | /* find head of list */ | |
1412 | for(;;) { | |
1413 | n1 = (long)tb1 & 3; | |
1414 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1415 | if (n1 == 2) | |
1416 | break; | |
1417 | tb1 = tb1->jmp_next[n1]; | |
1418 | } | |
1419 | /* we are now sure now that tb jumps to tb1 */ | |
1420 | tb_next = tb1; | |
1421 | ||
1422 | /* remove tb from the jmp_first list */ | |
1423 | ptb = &tb_next->jmp_first; | |
1424 | for(;;) { | |
1425 | tb1 = *ptb; | |
1426 | n1 = (long)tb1 & 3; | |
1427 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1428 | if (n1 == n && tb1 == tb) | |
1429 | break; | |
1430 | ptb = &tb1->jmp_next[n1]; | |
1431 | } | |
1432 | *ptb = tb->jmp_next[n]; | |
1433 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1434 | |
ea041c0e FB |
1435 | /* suppress the jump to next tb in generated code */ |
1436 | tb_reset_jump(tb, n); | |
1437 | ||
0124311e | 1438 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1439 | tb_reset_jump_recursive(tb_next); |
1440 | } | |
1441 | } | |
1442 | ||
1443 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1444 | { | |
1445 | tb_reset_jump_recursive2(tb, 0); | |
1446 | tb_reset_jump_recursive2(tb, 1); | |
1447 | } | |
1448 | ||
1fddef4b | 1449 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1450 | #if defined(CONFIG_USER_ONLY) |
1451 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1452 | { | |
1453 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1454 | } | |
1455 | #else | |
d720b93d FB |
1456 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1457 | { | |
c227f099 | 1458 | target_phys_addr_t addr; |
c227f099 | 1459 | ram_addr_t ram_addr; |
06ef3525 | 1460 | MemoryRegionSection section; |
d720b93d | 1461 | |
c2f07f81 | 1462 | addr = cpu_get_phys_page_debug(env, pc); |
06ef3525 AK |
1463 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
1464 | if (!(memory_region_is_ram(section.mr) | |
1465 | || (section.mr->rom_device && section.mr->readable))) { | |
1466 | return; | |
1467 | } | |
1468 | ram_addr = (memory_region_get_ram_addr(section.mr) | |
1469 | + section.offset_within_region) & TARGET_PAGE_MASK; | |
1470 | ram_addr |= (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1471 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1472 | } |
c27004ec | 1473 | #endif |
94df27fd | 1474 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1475 | |
c527ee8f PB |
1476 | #if defined(CONFIG_USER_ONLY) |
1477 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1478 | ||
1479 | { | |
1480 | } | |
1481 | ||
1482 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1483 | int flags, CPUWatchpoint **watchpoint) | |
1484 | { | |
1485 | return -ENOSYS; | |
1486 | } | |
1487 | #else | |
6658ffb8 | 1488 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1489 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1490 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1491 | { |
b4051334 | 1492 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1493 | CPUWatchpoint *wp; |
6658ffb8 | 1494 | |
b4051334 AL |
1495 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1496 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1497 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1498 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1499 | return -EINVAL; | |
1500 | } | |
7267c094 | 1501 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1502 | |
1503 | wp->vaddr = addr; | |
b4051334 | 1504 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1505 | wp->flags = flags; |
1506 | ||
2dc9f411 | 1507 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1508 | if (flags & BP_GDB) |
72cf2d4f | 1509 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1510 | else |
72cf2d4f | 1511 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1512 | |
6658ffb8 | 1513 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1514 | |
1515 | if (watchpoint) | |
1516 | *watchpoint = wp; | |
1517 | return 0; | |
6658ffb8 PB |
1518 | } |
1519 | ||
a1d1bb31 AL |
1520 | /* Remove a specific watchpoint. */ |
1521 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1522 | int flags) | |
6658ffb8 | 1523 | { |
b4051334 | 1524 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1525 | CPUWatchpoint *wp; |
6658ffb8 | 1526 | |
72cf2d4f | 1527 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1528 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1529 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1530 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1531 | return 0; |
1532 | } | |
1533 | } | |
a1d1bb31 | 1534 | return -ENOENT; |
6658ffb8 PB |
1535 | } |
1536 | ||
a1d1bb31 AL |
1537 | /* Remove a specific watchpoint by reference. */ |
1538 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1539 | { | |
72cf2d4f | 1540 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1541 | |
a1d1bb31 AL |
1542 | tlb_flush_page(env, watchpoint->vaddr); |
1543 | ||
7267c094 | 1544 | g_free(watchpoint); |
a1d1bb31 AL |
1545 | } |
1546 | ||
1547 | /* Remove all matching watchpoints. */ | |
1548 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1549 | { | |
c0ce998e | 1550 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1551 | |
72cf2d4f | 1552 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1553 | if (wp->flags & mask) |
1554 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1555 | } |
7d03f82f | 1556 | } |
c527ee8f | 1557 | #endif |
7d03f82f | 1558 | |
a1d1bb31 AL |
1559 | /* Add a breakpoint. */ |
1560 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1561 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1562 | { |
1fddef4b | 1563 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1564 | CPUBreakpoint *bp; |
3b46e624 | 1565 | |
7267c094 | 1566 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 1567 | |
a1d1bb31 AL |
1568 | bp->pc = pc; |
1569 | bp->flags = flags; | |
1570 | ||
2dc9f411 | 1571 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1572 | if (flags & BP_GDB) |
72cf2d4f | 1573 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1574 | else |
72cf2d4f | 1575 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1576 | |
d720b93d | 1577 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1578 | |
1579 | if (breakpoint) | |
1580 | *breakpoint = bp; | |
4c3a88a2 FB |
1581 | return 0; |
1582 | #else | |
a1d1bb31 | 1583 | return -ENOSYS; |
4c3a88a2 FB |
1584 | #endif |
1585 | } | |
1586 | ||
a1d1bb31 AL |
1587 | /* Remove a specific breakpoint. */ |
1588 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1589 | { | |
7d03f82f | 1590 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1591 | CPUBreakpoint *bp; |
1592 | ||
72cf2d4f | 1593 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1594 | if (bp->pc == pc && bp->flags == flags) { |
1595 | cpu_breakpoint_remove_by_ref(env, bp); | |
1596 | return 0; | |
1597 | } | |
7d03f82f | 1598 | } |
a1d1bb31 AL |
1599 | return -ENOENT; |
1600 | #else | |
1601 | return -ENOSYS; | |
7d03f82f EI |
1602 | #endif |
1603 | } | |
1604 | ||
a1d1bb31 AL |
1605 | /* Remove a specific breakpoint by reference. */ |
1606 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1607 | { |
1fddef4b | 1608 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1609 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1610 | |
a1d1bb31 AL |
1611 | breakpoint_invalidate(env, breakpoint->pc); |
1612 | ||
7267c094 | 1613 | g_free(breakpoint); |
a1d1bb31 AL |
1614 | #endif |
1615 | } | |
1616 | ||
1617 | /* Remove all matching breakpoints. */ | |
1618 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1619 | { | |
1620 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1621 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1622 | |
72cf2d4f | 1623 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1624 | if (bp->flags & mask) |
1625 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1626 | } |
4c3a88a2 FB |
1627 | #endif |
1628 | } | |
1629 | ||
c33a346e FB |
1630 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1631 | CPU loop after each instruction */ | |
1632 | void cpu_single_step(CPUState *env, int enabled) | |
1633 | { | |
1fddef4b | 1634 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1635 | if (env->singlestep_enabled != enabled) { |
1636 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1637 | if (kvm_enabled()) |
1638 | kvm_update_guest_debug(env, 0); | |
1639 | else { | |
ccbb4d44 | 1640 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1641 | /* XXX: only flush what is necessary */ |
1642 | tb_flush(env); | |
1643 | } | |
c33a346e FB |
1644 | } |
1645 | #endif | |
1646 | } | |
1647 | ||
34865134 FB |
1648 | /* enable or disable low levels log */ |
1649 | void cpu_set_log(int log_flags) | |
1650 | { | |
1651 | loglevel = log_flags; | |
1652 | if (loglevel && !logfile) { | |
11fcfab4 | 1653 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1654 | if (!logfile) { |
1655 | perror(logfilename); | |
1656 | _exit(1); | |
1657 | } | |
9fa3e853 FB |
1658 | #if !defined(CONFIG_SOFTMMU) |
1659 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1660 | { | |
b55266b5 | 1661 | static char logfile_buf[4096]; |
9fa3e853 FB |
1662 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1663 | } | |
daf767b1 SW |
1664 | #elif defined(_WIN32) |
1665 | /* Win32 doesn't support line-buffering, so use unbuffered output. */ | |
1666 | setvbuf(logfile, NULL, _IONBF, 0); | |
1667 | #else | |
34865134 | 1668 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1669 | #endif |
e735b91c PB |
1670 | log_append = 1; |
1671 | } | |
1672 | if (!loglevel && logfile) { | |
1673 | fclose(logfile); | |
1674 | logfile = NULL; | |
34865134 FB |
1675 | } |
1676 | } | |
1677 | ||
1678 | void cpu_set_log_filename(const char *filename) | |
1679 | { | |
1680 | logfilename = strdup(filename); | |
e735b91c PB |
1681 | if (logfile) { |
1682 | fclose(logfile); | |
1683 | logfile = NULL; | |
1684 | } | |
1685 | cpu_set_log(loglevel); | |
34865134 | 1686 | } |
c33a346e | 1687 | |
3098dba0 | 1688 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1689 | { |
3098dba0 AJ |
1690 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1691 | problem and hope the cpu will stop of its own accord. For userspace | |
1692 | emulation this often isn't actually as bad as it sounds. Often | |
1693 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1694 | TranslationBlock *tb; |
c227f099 | 1695 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1696 | |
cab1b4bd | 1697 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1698 | tb = env->current_tb; |
1699 | /* if the cpu is currently executing code, we must unlink it and | |
1700 | all the potentially executing TB */ | |
f76cfe56 | 1701 | if (tb) { |
3098dba0 AJ |
1702 | env->current_tb = NULL; |
1703 | tb_reset_jump_recursive(tb); | |
be214e6c | 1704 | } |
cab1b4bd | 1705 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1706 | } |
1707 | ||
97ffbd8d | 1708 | #ifndef CONFIG_USER_ONLY |
3098dba0 | 1709 | /* mask must never be zero, except for A20 change call */ |
ec6959d0 | 1710 | static void tcg_handle_interrupt(CPUState *env, int mask) |
3098dba0 AJ |
1711 | { |
1712 | int old_mask; | |
be214e6c | 1713 | |
2e70f6ef | 1714 | old_mask = env->interrupt_request; |
68a79315 | 1715 | env->interrupt_request |= mask; |
3098dba0 | 1716 | |
8edac960 AL |
1717 | /* |
1718 | * If called from iothread context, wake the target cpu in | |
1719 | * case its halted. | |
1720 | */ | |
b7680cb6 | 1721 | if (!qemu_cpu_is_self(env)) { |
8edac960 AL |
1722 | qemu_cpu_kick(env); |
1723 | return; | |
1724 | } | |
8edac960 | 1725 | |
2e70f6ef | 1726 | if (use_icount) { |
266910c4 | 1727 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1728 | if (!can_do_io(env) |
be214e6c | 1729 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1730 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1731 | } | |
2e70f6ef | 1732 | } else { |
3098dba0 | 1733 | cpu_unlink_tb(env); |
ea041c0e FB |
1734 | } |
1735 | } | |
1736 | ||
ec6959d0 JK |
1737 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; |
1738 | ||
97ffbd8d JK |
1739 | #else /* CONFIG_USER_ONLY */ |
1740 | ||
1741 | void cpu_interrupt(CPUState *env, int mask) | |
1742 | { | |
1743 | env->interrupt_request |= mask; | |
1744 | cpu_unlink_tb(env); | |
1745 | } | |
1746 | #endif /* CONFIG_USER_ONLY */ | |
1747 | ||
b54ad049 FB |
1748 | void cpu_reset_interrupt(CPUState *env, int mask) |
1749 | { | |
1750 | env->interrupt_request &= ~mask; | |
1751 | } | |
1752 | ||
3098dba0 AJ |
1753 | void cpu_exit(CPUState *env) |
1754 | { | |
1755 | env->exit_request = 1; | |
1756 | cpu_unlink_tb(env); | |
1757 | } | |
1758 | ||
c7cd6a37 | 1759 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1760 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1761 | "show generated host assembly code for each compiled TB" }, |
1762 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1763 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1764 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1765 | "show micro ops for each compiled TB" }, |
f193c797 | 1766 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1767 | "show micro ops " |
1768 | #ifdef TARGET_I386 | |
1769 | "before eflags optimization and " | |
f193c797 | 1770 | #endif |
e01a1157 | 1771 | "after liveness analysis" }, |
f193c797 FB |
1772 | { CPU_LOG_INT, "int", |
1773 | "show interrupts/exceptions in short format" }, | |
1774 | { CPU_LOG_EXEC, "exec", | |
1775 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1776 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1777 | "show CPU state before block translation" }, |
f193c797 FB |
1778 | #ifdef TARGET_I386 |
1779 | { CPU_LOG_PCALL, "pcall", | |
1780 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1781 | { CPU_LOG_RESET, "cpu_reset", |
1782 | "show CPU state before CPU resets" }, | |
f193c797 | 1783 | #endif |
8e3a9fd2 | 1784 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1785 | { CPU_LOG_IOPORT, "ioport", |
1786 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1787 | #endif |
f193c797 FB |
1788 | { 0, NULL, NULL }, |
1789 | }; | |
1790 | ||
1791 | static int cmp1(const char *s1, int n, const char *s2) | |
1792 | { | |
1793 | if (strlen(s2) != n) | |
1794 | return 0; | |
1795 | return memcmp(s1, s2, n) == 0; | |
1796 | } | |
3b46e624 | 1797 | |
f193c797 FB |
1798 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1799 | int cpu_str_to_log_mask(const char *str) | |
1800 | { | |
c7cd6a37 | 1801 | const CPULogItem *item; |
f193c797 FB |
1802 | int mask; |
1803 | const char *p, *p1; | |
1804 | ||
1805 | p = str; | |
1806 | mask = 0; | |
1807 | for(;;) { | |
1808 | p1 = strchr(p, ','); | |
1809 | if (!p1) | |
1810 | p1 = p + strlen(p); | |
9742bf26 YT |
1811 | if(cmp1(p,p1-p,"all")) { |
1812 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1813 | mask |= item->mask; | |
1814 | } | |
1815 | } else { | |
1816 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1817 | if (cmp1(p, p1 - p, item->name)) | |
1818 | goto found; | |
1819 | } | |
1820 | return 0; | |
f193c797 | 1821 | } |
f193c797 FB |
1822 | found: |
1823 | mask |= item->mask; | |
1824 | if (*p1 != ',') | |
1825 | break; | |
1826 | p = p1 + 1; | |
1827 | } | |
1828 | return mask; | |
1829 | } | |
ea041c0e | 1830 | |
7501267e FB |
1831 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1832 | { | |
1833 | va_list ap; | |
493ae1f0 | 1834 | va_list ap2; |
7501267e FB |
1835 | |
1836 | va_start(ap, fmt); | |
493ae1f0 | 1837 | va_copy(ap2, ap); |
7501267e FB |
1838 | fprintf(stderr, "qemu: fatal: "); |
1839 | vfprintf(stderr, fmt, ap); | |
1840 | fprintf(stderr, "\n"); | |
1841 | #ifdef TARGET_I386 | |
7fe48483 FB |
1842 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1843 | #else | |
1844 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1845 | #endif |
93fcfe39 AL |
1846 | if (qemu_log_enabled()) { |
1847 | qemu_log("qemu: fatal: "); | |
1848 | qemu_log_vprintf(fmt, ap2); | |
1849 | qemu_log("\n"); | |
f9373291 | 1850 | #ifdef TARGET_I386 |
93fcfe39 | 1851 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1852 | #else |
93fcfe39 | 1853 | log_cpu_state(env, 0); |
f9373291 | 1854 | #endif |
31b1a7b4 | 1855 | qemu_log_flush(); |
93fcfe39 | 1856 | qemu_log_close(); |
924edcae | 1857 | } |
493ae1f0 | 1858 | va_end(ap2); |
f9373291 | 1859 | va_end(ap); |
fd052bf6 RV |
1860 | #if defined(CONFIG_USER_ONLY) |
1861 | { | |
1862 | struct sigaction act; | |
1863 | sigfillset(&act.sa_mask); | |
1864 | act.sa_handler = SIG_DFL; | |
1865 | sigaction(SIGABRT, &act, NULL); | |
1866 | } | |
1867 | #endif | |
7501267e FB |
1868 | abort(); |
1869 | } | |
1870 | ||
c5be9f08 TS |
1871 | CPUState *cpu_copy(CPUState *env) |
1872 | { | |
01ba9816 | 1873 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1874 | CPUState *next_cpu = new_env->next_cpu; |
1875 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1876 | #if defined(TARGET_HAS_ICE) |
1877 | CPUBreakpoint *bp; | |
1878 | CPUWatchpoint *wp; | |
1879 | #endif | |
1880 | ||
c5be9f08 | 1881 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1882 | |
1883 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1884 | new_env->next_cpu = next_cpu; |
1885 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1886 | |
1887 | /* Clone all break/watchpoints. | |
1888 | Note: Once we support ptrace with hw-debug register access, make sure | |
1889 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1890 | QTAILQ_INIT(&env->breakpoints); |
1891 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1892 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1893 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1894 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1895 | } | |
72cf2d4f | 1896 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1897 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1898 | wp->flags, NULL); | |
1899 | } | |
1900 | #endif | |
1901 | ||
c5be9f08 TS |
1902 | return new_env; |
1903 | } | |
1904 | ||
0124311e FB |
1905 | #if !defined(CONFIG_USER_ONLY) |
1906 | ||
5c751e99 EI |
1907 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1908 | { | |
1909 | unsigned int i; | |
1910 | ||
1911 | /* Discard jump cache entries for any tb which might potentially | |
1912 | overlap the flushed page. */ | |
1913 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1914 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1915 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1916 | |
1917 | i = tb_jmp_cache_hash_page(addr); | |
1918 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1919 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1920 | } |
1921 | ||
08738984 IK |
1922 | static CPUTLBEntry s_cputlb_empty_entry = { |
1923 | .addr_read = -1, | |
1924 | .addr_write = -1, | |
1925 | .addr_code = -1, | |
1926 | .addend = -1, | |
1927 | }; | |
1928 | ||
771124e1 PM |
1929 | /* NOTE: |
1930 | * If flush_global is true (the usual case), flush all tlb entries. | |
1931 | * If flush_global is false, flush (at least) all tlb entries not | |
1932 | * marked global. | |
1933 | * | |
1934 | * Since QEMU doesn't currently implement a global/not-global flag | |
1935 | * for tlb entries, at the moment tlb_flush() will also flush all | |
1936 | * tlb entries in the flush_global == false case. This is OK because | |
1937 | * CPU architectures generally permit an implementation to drop | |
1938 | * entries from the TLB at any time, so flushing more entries than | |
1939 | * required is only an efficiency issue, not a correctness issue. | |
1940 | */ | |
ee8b7021 | 1941 | void tlb_flush(CPUState *env, int flush_global) |
33417e70 | 1942 | { |
33417e70 | 1943 | int i; |
0124311e | 1944 | |
9fa3e853 FB |
1945 | #if defined(DEBUG_TLB) |
1946 | printf("tlb_flush:\n"); | |
1947 | #endif | |
0124311e FB |
1948 | /* must reset current TB so that interrupts cannot modify the |
1949 | links while we are modifying them */ | |
1950 | env->current_tb = NULL; | |
1951 | ||
33417e70 | 1952 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1953 | int mmu_idx; |
1954 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1955 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1956 | } |
33417e70 | 1957 | } |
9fa3e853 | 1958 | |
8a40a180 | 1959 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1960 | |
d4c430a8 PB |
1961 | env->tlb_flush_addr = -1; |
1962 | env->tlb_flush_mask = 0; | |
e3db7226 | 1963 | tlb_flush_count++; |
33417e70 FB |
1964 | } |
1965 | ||
274da6b2 | 1966 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1967 | { |
5fafdf24 | 1968 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1969 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1970 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1971 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1972 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 1973 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 1974 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 1975 | } |
61382a50 FB |
1976 | } |
1977 | ||
2e12669a | 1978 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1979 | { |
8a40a180 | 1980 | int i; |
cfde4bd9 | 1981 | int mmu_idx; |
0124311e | 1982 | |
9fa3e853 | 1983 | #if defined(DEBUG_TLB) |
108c49b8 | 1984 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1985 | #endif |
d4c430a8 PB |
1986 | /* Check if we need to flush due to large pages. */ |
1987 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { | |
1988 | #if defined(DEBUG_TLB) | |
1989 | printf("tlb_flush_page: forced full flush (" | |
1990 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", | |
1991 | env->tlb_flush_addr, env->tlb_flush_mask); | |
1992 | #endif | |
1993 | tlb_flush(env, 1); | |
1994 | return; | |
1995 | } | |
0124311e FB |
1996 | /* must reset current TB so that interrupts cannot modify the |
1997 | links while we are modifying them */ | |
1998 | env->current_tb = NULL; | |
61382a50 FB |
1999 | |
2000 | addr &= TARGET_PAGE_MASK; | |
2001 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
2002 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2003 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 2004 | |
5c751e99 | 2005 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
2006 | } |
2007 | ||
9fa3e853 FB |
2008 | /* update the TLBs so that writes to code in the virtual page 'addr' |
2009 | can be detected */ | |
c227f099 | 2010 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 2011 | { |
5fafdf24 | 2012 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
2013 | ram_addr + TARGET_PAGE_SIZE, |
2014 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
2015 | } |
2016 | ||
9fa3e853 | 2017 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 2018 | tested for self modifying code */ |
c227f099 | 2019 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 2020 | target_ulong vaddr) |
9fa3e853 | 2021 | { |
f7c11b53 | 2022 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
1ccde1cb FB |
2023 | } |
2024 | ||
5fafdf24 | 2025 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
2026 | unsigned long start, unsigned long length) |
2027 | { | |
2028 | unsigned long addr; | |
0e0df1e2 | 2029 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) { |
84b7b8e7 | 2030 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
1ccde1cb | 2031 | if ((addr - start) < length) { |
0f459d16 | 2032 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
2033 | } |
2034 | } | |
2035 | } | |
2036 | ||
5579c7f3 | 2037 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 2038 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 2039 | int dirty_flags) |
1ccde1cb FB |
2040 | { |
2041 | CPUState *env; | |
4f2ac237 | 2042 | unsigned long length, start1; |
f7c11b53 | 2043 | int i; |
1ccde1cb FB |
2044 | |
2045 | start &= TARGET_PAGE_MASK; | |
2046 | end = TARGET_PAGE_ALIGN(end); | |
2047 | ||
2048 | length = end - start; | |
2049 | if (length == 0) | |
2050 | return; | |
f7c11b53 | 2051 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
f23db169 | 2052 | |
1ccde1cb FB |
2053 | /* we modify the TLB cache so that the dirty bit will be set again |
2054 | when accessing the range */ | |
b2e0a138 | 2055 | start1 = (unsigned long)qemu_safe_ram_ptr(start); |
a57d23e4 | 2056 | /* Check that we don't span multiple blocks - this breaks the |
5579c7f3 | 2057 | address comparisons below. */ |
b2e0a138 | 2058 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 |
5579c7f3 PB |
2059 | != (end - 1) - start) { |
2060 | abort(); | |
2061 | } | |
2062 | ||
6a00d601 | 2063 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
2064 | int mmu_idx; |
2065 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2066 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2067 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2068 | start1, length); | |
2069 | } | |
6a00d601 | 2070 | } |
1ccde1cb FB |
2071 | } |
2072 | ||
74576198 AL |
2073 | int cpu_physical_memory_set_dirty_tracking(int enable) |
2074 | { | |
f6f3fbca | 2075 | int ret = 0; |
74576198 | 2076 | in_migration = enable; |
f6f3fbca | 2077 | return ret; |
74576198 AL |
2078 | } |
2079 | ||
3a7d929e FB |
2080 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2081 | { | |
c227f099 | 2082 | ram_addr_t ram_addr; |
5579c7f3 | 2083 | void *p; |
3a7d929e | 2084 | |
0e0df1e2 | 2085 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) { |
5579c7f3 PB |
2086 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2087 | + tlb_entry->addend); | |
e890261f | 2088 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
3a7d929e | 2089 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2090 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2091 | } |
2092 | } | |
2093 | } | |
2094 | ||
2095 | /* update the TLB according to the current state of the dirty bits */ | |
2096 | void cpu_tlb_update_dirty(CPUState *env) | |
2097 | { | |
2098 | int i; | |
cfde4bd9 IY |
2099 | int mmu_idx; |
2100 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2101 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2102 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2103 | } | |
3a7d929e FB |
2104 | } |
2105 | ||
0f459d16 | 2106 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2107 | { |
0f459d16 PB |
2108 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2109 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2110 | } |
2111 | ||
0f459d16 PB |
2112 | /* update the TLB corresponding to virtual page vaddr |
2113 | so that it is no longer dirty */ | |
2114 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2115 | { |
1ccde1cb | 2116 | int i; |
cfde4bd9 | 2117 | int mmu_idx; |
1ccde1cb | 2118 | |
0f459d16 | 2119 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2120 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2121 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2122 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2123 | } |
2124 | ||
d4c430a8 PB |
2125 | /* Our TLB does not support large pages, so remember the area covered by |
2126 | large pages and trigger a full TLB flush if these are invalidated. */ | |
2127 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, | |
2128 | target_ulong size) | |
2129 | { | |
2130 | target_ulong mask = ~(size - 1); | |
2131 | ||
2132 | if (env->tlb_flush_addr == (target_ulong)-1) { | |
2133 | env->tlb_flush_addr = vaddr & mask; | |
2134 | env->tlb_flush_mask = mask; | |
2135 | return; | |
2136 | } | |
2137 | /* Extend the existing region to include the new page. | |
2138 | This is a compromise between unnecessary flushes and the cost | |
2139 | of maintaining a full variable size TLB. */ | |
2140 | mask &= env->tlb_flush_mask; | |
2141 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { | |
2142 | mask <<= 1; | |
2143 | } | |
2144 | env->tlb_flush_addr &= mask; | |
2145 | env->tlb_flush_mask = mask; | |
2146 | } | |
2147 | ||
06ef3525 | 2148 | static bool is_ram_rom(MemoryRegionSection *s) |
1d393fa2 | 2149 | { |
06ef3525 | 2150 | return memory_region_is_ram(s->mr); |
1d393fa2 AK |
2151 | } |
2152 | ||
06ef3525 | 2153 | static bool is_romd(MemoryRegionSection *s) |
75c578dc | 2154 | { |
06ef3525 | 2155 | MemoryRegion *mr = s->mr; |
75c578dc | 2156 | |
75c578dc AK |
2157 | return mr->rom_device && mr->readable; |
2158 | } | |
2159 | ||
06ef3525 | 2160 | static bool is_ram_rom_romd(MemoryRegionSection *s) |
1d393fa2 | 2161 | { |
06ef3525 | 2162 | return is_ram_rom(s) || is_romd(s); |
1d393fa2 AK |
2163 | } |
2164 | ||
d4c430a8 PB |
2165 | /* Add a new TLB entry. At most one entry for a given virtual address |
2166 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | |
2167 | supplied size is only used by tlb_flush_page. */ | |
2168 | void tlb_set_page(CPUState *env, target_ulong vaddr, | |
2169 | target_phys_addr_t paddr, int prot, | |
2170 | int mmu_idx, target_ulong size) | |
9fa3e853 | 2171 | { |
06ef3525 | 2172 | MemoryRegionSection section; |
9fa3e853 | 2173 | unsigned int index; |
4f2ac237 | 2174 | target_ulong address; |
0f459d16 | 2175 | target_ulong code_address; |
355b1943 | 2176 | unsigned long addend; |
84b7b8e7 | 2177 | CPUTLBEntry *te; |
a1d1bb31 | 2178 | CPUWatchpoint *wp; |
c227f099 | 2179 | target_phys_addr_t iotlb; |
9fa3e853 | 2180 | |
d4c430a8 PB |
2181 | assert(size >= TARGET_PAGE_SIZE); |
2182 | if (size != TARGET_PAGE_SIZE) { | |
2183 | tlb_add_large_page(env, vaddr, size); | |
2184 | } | |
06ef3525 | 2185 | section = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 | 2186 | #if defined(DEBUG_TLB) |
7fd3f494 SW |
2187 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
2188 | " prot=%x idx=%d pd=0x%08lx\n", | |
2189 | vaddr, paddr, prot, mmu_idx, pd); | |
9fa3e853 FB |
2190 | #endif |
2191 | ||
0f459d16 | 2192 | address = vaddr; |
06ef3525 | 2193 | if (!is_ram_rom_romd(§ion)) { |
0f459d16 PB |
2194 | /* IO memory case (romd handled later) */ |
2195 | address |= TLB_MMIO; | |
2196 | } | |
06ef3525 AK |
2197 | if (is_ram_rom_romd(§ion)) { |
2198 | addend = (unsigned long)(memory_region_get_ram_ptr(section.mr) | |
2199 | + section.offset_within_region); | |
2200 | } else { | |
2201 | addend = 0; | |
2202 | } | |
2203 | if (is_ram_rom(§ion)) { | |
0f459d16 | 2204 | /* Normal RAM. */ |
06ef3525 AK |
2205 | iotlb = (memory_region_get_ram_addr(section.mr) |
2206 | + section.offset_within_region) & TARGET_PAGE_MASK; | |
2207 | if (!section.readonly) | |
0e0df1e2 | 2208 | iotlb |= io_mem_notdirty.ram_addr; |
0f459d16 | 2209 | else |
0e0df1e2 | 2210 | iotlb |= io_mem_rom.ram_addr; |
0f459d16 | 2211 | } else { |
ccbb4d44 | 2212 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2213 | It would be nice to pass an offset from the base address |
2214 | of that region. This would avoid having to special case RAM, | |
2215 | and avoid full address decoding in every device. | |
2216 | We can't use the high bits of pd for this because | |
2217 | IO_MEM_ROMD uses these as a ram address. */ | |
06ef3525 AK |
2218 | iotlb = memory_region_get_ram_addr(section.mr) & ~TARGET_PAGE_MASK; |
2219 | iotlb += section.offset_within_region; | |
0f459d16 PB |
2220 | } |
2221 | ||
2222 | code_address = address; | |
2223 | /* Make accesses to pages with watchpoints go via the | |
2224 | watchpoint trap routines. */ | |
72cf2d4f | 2225 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2226 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
bf298f83 JK |
2227 | /* Avoid trapping reads of pages with a write breakpoint. */ |
2228 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
1ec9b909 | 2229 | iotlb = io_mem_watch.ram_addr + paddr; |
bf298f83 JK |
2230 | address |= TLB_MMIO; |
2231 | break; | |
2232 | } | |
6658ffb8 | 2233 | } |
0f459d16 | 2234 | } |
d79acba4 | 2235 | |
0f459d16 PB |
2236 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2237 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2238 | te = &env->tlb_table[mmu_idx][index]; | |
2239 | te->addend = addend - vaddr; | |
2240 | if (prot & PAGE_READ) { | |
2241 | te->addr_read = address; | |
2242 | } else { | |
2243 | te->addr_read = -1; | |
2244 | } | |
5c751e99 | 2245 | |
0f459d16 PB |
2246 | if (prot & PAGE_EXEC) { |
2247 | te->addr_code = code_address; | |
2248 | } else { | |
2249 | te->addr_code = -1; | |
2250 | } | |
2251 | if (prot & PAGE_WRITE) { | |
06ef3525 AK |
2252 | if ((memory_region_is_ram(section.mr) && section.readonly) |
2253 | || is_romd(§ion)) { | |
0f459d16 PB |
2254 | /* Write access calls the I/O callback. */ |
2255 | te->addr_write = address | TLB_MMIO; | |
06ef3525 AK |
2256 | } else if (memory_region_is_ram(section.mr) |
2257 | && !cpu_physical_memory_is_dirty( | |
2258 | section.mr->ram_addr | |
2259 | + section.offset_within_region)) { | |
0f459d16 | 2260 | te->addr_write = address | TLB_NOTDIRTY; |
9fa3e853 | 2261 | } else { |
0f459d16 | 2262 | te->addr_write = address; |
9fa3e853 | 2263 | } |
0f459d16 PB |
2264 | } else { |
2265 | te->addr_write = -1; | |
9fa3e853 | 2266 | } |
9fa3e853 FB |
2267 | } |
2268 | ||
0124311e FB |
2269 | #else |
2270 | ||
ee8b7021 | 2271 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2272 | { |
2273 | } | |
2274 | ||
2e12669a | 2275 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2276 | { |
2277 | } | |
2278 | ||
edf8e2af MW |
2279 | /* |
2280 | * Walks guest process memory "regions" one by one | |
2281 | * and calls callback function 'fn' for each region. | |
2282 | */ | |
5cd2c5b6 RH |
2283 | |
2284 | struct walk_memory_regions_data | |
2285 | { | |
2286 | walk_memory_regions_fn fn; | |
2287 | void *priv; | |
2288 | unsigned long start; | |
2289 | int prot; | |
2290 | }; | |
2291 | ||
2292 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
b480d9b7 | 2293 | abi_ulong end, int new_prot) |
5cd2c5b6 RH |
2294 | { |
2295 | if (data->start != -1ul) { | |
2296 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2297 | if (rc != 0) { | |
2298 | return rc; | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | data->start = (new_prot ? end : -1ul); | |
2303 | data->prot = new_prot; | |
2304 | ||
2305 | return 0; | |
2306 | } | |
2307 | ||
2308 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
b480d9b7 | 2309 | abi_ulong base, int level, void **lp) |
5cd2c5b6 | 2310 | { |
b480d9b7 | 2311 | abi_ulong pa; |
5cd2c5b6 RH |
2312 | int i, rc; |
2313 | ||
2314 | if (*lp == NULL) { | |
2315 | return walk_memory_regions_end(data, base, 0); | |
2316 | } | |
2317 | ||
2318 | if (level == 0) { | |
2319 | PageDesc *pd = *lp; | |
7296abac | 2320 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
2321 | int prot = pd[i].flags; |
2322 | ||
2323 | pa = base | (i << TARGET_PAGE_BITS); | |
2324 | if (prot != data->prot) { | |
2325 | rc = walk_memory_regions_end(data, pa, prot); | |
2326 | if (rc != 0) { | |
2327 | return rc; | |
9fa3e853 | 2328 | } |
9fa3e853 | 2329 | } |
5cd2c5b6 RH |
2330 | } |
2331 | } else { | |
2332 | void **pp = *lp; | |
7296abac | 2333 | for (i = 0; i < L2_SIZE; ++i) { |
b480d9b7 PB |
2334 | pa = base | ((abi_ulong)i << |
2335 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
5cd2c5b6 RH |
2336 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
2337 | if (rc != 0) { | |
2338 | return rc; | |
2339 | } | |
2340 | } | |
2341 | } | |
2342 | ||
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2347 | { | |
2348 | struct walk_memory_regions_data data; | |
2349 | unsigned long i; | |
2350 | ||
2351 | data.fn = fn; | |
2352 | data.priv = priv; | |
2353 | data.start = -1ul; | |
2354 | data.prot = 0; | |
2355 | ||
2356 | for (i = 0; i < V_L1_SIZE; i++) { | |
b480d9b7 | 2357 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
5cd2c5b6 RH |
2358 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
2359 | if (rc != 0) { | |
2360 | return rc; | |
9fa3e853 | 2361 | } |
33417e70 | 2362 | } |
5cd2c5b6 RH |
2363 | |
2364 | return walk_memory_regions_end(&data, 0, 0); | |
edf8e2af MW |
2365 | } |
2366 | ||
b480d9b7 PB |
2367 | static int dump_region(void *priv, abi_ulong start, |
2368 | abi_ulong end, unsigned long prot) | |
edf8e2af MW |
2369 | { |
2370 | FILE *f = (FILE *)priv; | |
2371 | ||
b480d9b7 PB |
2372 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
2373 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
edf8e2af MW |
2374 | start, end, end - start, |
2375 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2376 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2377 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2378 | ||
2379 | return (0); | |
2380 | } | |
2381 | ||
2382 | /* dump memory mappings */ | |
2383 | void page_dump(FILE *f) | |
2384 | { | |
2385 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2386 | "start", "end", "size", "prot"); | |
2387 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2388 | } |
2389 | ||
53a5960a | 2390 | int page_get_flags(target_ulong address) |
33417e70 | 2391 | { |
9fa3e853 FB |
2392 | PageDesc *p; |
2393 | ||
2394 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2395 | if (!p) |
9fa3e853 FB |
2396 | return 0; |
2397 | return p->flags; | |
2398 | } | |
2399 | ||
376a7909 RH |
2400 | /* Modify the flags of a page and invalidate the code if necessary. |
2401 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2402 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
53a5960a | 2403 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 | 2404 | { |
376a7909 RH |
2405 | target_ulong addr, len; |
2406 | ||
2407 | /* This function should never be called with addresses outside the | |
2408 | guest address space. If this assert fires, it probably indicates | |
2409 | a missing call to h2g_valid. */ | |
b480d9b7 PB |
2410 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2411 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2412 | #endif |
2413 | assert(start < end); | |
9fa3e853 FB |
2414 | |
2415 | start = start & TARGET_PAGE_MASK; | |
2416 | end = TARGET_PAGE_ALIGN(end); | |
376a7909 RH |
2417 | |
2418 | if (flags & PAGE_WRITE) { | |
9fa3e853 | 2419 | flags |= PAGE_WRITE_ORG; |
376a7909 RH |
2420 | } |
2421 | ||
2422 | for (addr = start, len = end - start; | |
2423 | len != 0; | |
2424 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2425 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2426 | ||
2427 | /* If the write protection bit is set, then we invalidate | |
2428 | the code inside. */ | |
5fafdf24 | 2429 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2430 | (flags & PAGE_WRITE) && |
2431 | p->first_tb) { | |
d720b93d | 2432 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2433 | } |
2434 | p->flags = flags; | |
2435 | } | |
33417e70 FB |
2436 | } |
2437 | ||
3d97b40b TS |
2438 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2439 | { | |
2440 | PageDesc *p; | |
2441 | target_ulong end; | |
2442 | target_ulong addr; | |
2443 | ||
376a7909 RH |
2444 | /* This function should never be called with addresses outside the |
2445 | guest address space. If this assert fires, it probably indicates | |
2446 | a missing call to h2g_valid. */ | |
338e9e6c BS |
2447 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2448 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2449 | #endif |
2450 | ||
3e0650a9 RH |
2451 | if (len == 0) { |
2452 | return 0; | |
2453 | } | |
376a7909 RH |
2454 | if (start + len - 1 < start) { |
2455 | /* We've wrapped around. */ | |
55f280c9 | 2456 | return -1; |
376a7909 | 2457 | } |
55f280c9 | 2458 | |
3d97b40b TS |
2459 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2460 | start = start & TARGET_PAGE_MASK; | |
2461 | ||
376a7909 RH |
2462 | for (addr = start, len = end - start; |
2463 | len != 0; | |
2464 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
3d97b40b TS |
2465 | p = page_find(addr >> TARGET_PAGE_BITS); |
2466 | if( !p ) | |
2467 | return -1; | |
2468 | if( !(p->flags & PAGE_VALID) ) | |
2469 | return -1; | |
2470 | ||
dae3270c | 2471 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2472 | return -1; |
dae3270c FB |
2473 | if (flags & PAGE_WRITE) { |
2474 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2475 | return -1; | |
2476 | /* unprotect the page if it was put read-only because it | |
2477 | contains translated code */ | |
2478 | if (!(p->flags & PAGE_WRITE)) { | |
2479 | if (!page_unprotect(addr, 0, NULL)) | |
2480 | return -1; | |
2481 | } | |
2482 | return 0; | |
2483 | } | |
3d97b40b TS |
2484 | } |
2485 | return 0; | |
2486 | } | |
2487 | ||
9fa3e853 | 2488 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2489 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2490 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 | 2491 | { |
45d679d6 AJ |
2492 | unsigned int prot; |
2493 | PageDesc *p; | |
53a5960a | 2494 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2495 | |
c8a706fe PB |
2496 | /* Technically this isn't safe inside a signal handler. However we |
2497 | know this only ever happens in a synchronous SEGV handler, so in | |
2498 | practice it seems to be ok. */ | |
2499 | mmap_lock(); | |
2500 | ||
45d679d6 AJ |
2501 | p = page_find(address >> TARGET_PAGE_BITS); |
2502 | if (!p) { | |
c8a706fe | 2503 | mmap_unlock(); |
9fa3e853 | 2504 | return 0; |
c8a706fe | 2505 | } |
45d679d6 | 2506 | |
9fa3e853 FB |
2507 | /* if the page was really writable, then we change its |
2508 | protection back to writable */ | |
45d679d6 AJ |
2509 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
2510 | host_start = address & qemu_host_page_mask; | |
2511 | host_end = host_start + qemu_host_page_size; | |
2512 | ||
2513 | prot = 0; | |
2514 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
2515 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2516 | p->flags |= PAGE_WRITE; | |
2517 | prot |= p->flags; | |
2518 | ||
9fa3e853 FB |
2519 | /* and since the content will be modified, we must invalidate |
2520 | the corresponding translated code. */ | |
45d679d6 | 2521 | tb_invalidate_phys_page(addr, pc, puc); |
9fa3e853 | 2522 | #ifdef DEBUG_TB_CHECK |
45d679d6 | 2523 | tb_invalidate_check(addr); |
9fa3e853 | 2524 | #endif |
9fa3e853 | 2525 | } |
45d679d6 AJ |
2526 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
2527 | prot & PAGE_BITS); | |
2528 | ||
2529 | mmap_unlock(); | |
2530 | return 1; | |
9fa3e853 | 2531 | } |
c8a706fe | 2532 | mmap_unlock(); |
9fa3e853 FB |
2533 | return 0; |
2534 | } | |
2535 | ||
6a00d601 FB |
2536 | static inline void tlb_set_dirty(CPUState *env, |
2537 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2538 | { |
2539 | } | |
9fa3e853 FB |
2540 | #endif /* defined(CONFIG_USER_ONLY) */ |
2541 | ||
e2eef170 | 2542 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2543 | |
c04b2b78 PB |
2544 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2545 | typedef struct subpage_t { | |
70c68e44 | 2546 | MemoryRegion iomem; |
c04b2b78 | 2547 | target_phys_addr_t base; |
5312bd8b | 2548 | uint16_t sub_section[TARGET_PAGE_SIZE]; |
c04b2b78 PB |
2549 | } subpage_t; |
2550 | ||
c227f099 | 2551 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 2552 | uint16_t section); |
0f0cb164 | 2553 | static subpage_t *subpage_init(target_phys_addr_t base); |
5312bd8b | 2554 | static void destroy_page_desc(uint16_t section_index) |
54688b1e | 2555 | { |
5312bd8b AK |
2556 | MemoryRegionSection *section = &phys_sections[section_index]; |
2557 | MemoryRegion *mr = section->mr; | |
54688b1e AK |
2558 | |
2559 | if (mr->subpage) { | |
2560 | subpage_t *subpage = container_of(mr, subpage_t, iomem); | |
2561 | memory_region_destroy(&subpage->iomem); | |
2562 | g_free(subpage); | |
2563 | } | |
2564 | } | |
2565 | ||
4346ae3e | 2566 | static void destroy_l2_mapping(PhysPageEntry *lp, unsigned level) |
54688b1e AK |
2567 | { |
2568 | unsigned i; | |
d6f2ea22 | 2569 | PhysPageEntry *p; |
54688b1e | 2570 | |
d6f2ea22 | 2571 | if (lp->u.node == PHYS_MAP_NODE_NIL) { |
54688b1e AK |
2572 | return; |
2573 | } | |
2574 | ||
d6f2ea22 | 2575 | p = phys_map_nodes[lp->u.node]; |
4346ae3e AK |
2576 | for (i = 0; i < L2_SIZE; ++i) { |
2577 | if (level > 0) { | |
54688b1e | 2578 | destroy_l2_mapping(&p[i], level - 1); |
4346ae3e AK |
2579 | } else { |
2580 | destroy_page_desc(p[i].u.leaf); | |
54688b1e | 2581 | } |
54688b1e | 2582 | } |
d6f2ea22 | 2583 | lp->u.node = PHYS_MAP_NODE_NIL; |
54688b1e AK |
2584 | } |
2585 | ||
2586 | static void destroy_all_mappings(void) | |
2587 | { | |
3eef53df | 2588 | destroy_l2_mapping(&phys_map, P_L2_LEVELS - 1); |
d6f2ea22 | 2589 | phys_map_nodes_reset(); |
54688b1e AK |
2590 | } |
2591 | ||
5312bd8b AK |
2592 | static uint16_t phys_section_add(MemoryRegionSection *section) |
2593 | { | |
2594 | if (phys_sections_nb == phys_sections_nb_alloc) { | |
2595 | phys_sections_nb_alloc = MAX(phys_sections_nb_alloc * 2, 16); | |
2596 | phys_sections = g_renew(MemoryRegionSection, phys_sections, | |
2597 | phys_sections_nb_alloc); | |
2598 | } | |
2599 | phys_sections[phys_sections_nb] = *section; | |
2600 | return phys_sections_nb++; | |
2601 | } | |
2602 | ||
2603 | static void phys_sections_clear(void) | |
2604 | { | |
2605 | phys_sections_nb = 0; | |
2606 | } | |
2607 | ||
8f2498f9 MT |
2608 | /* register physical memory. |
2609 | For RAM, 'size' must be a multiple of the target page size. | |
2610 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2611 | io memory page. The address used when calling the IO function is |
2612 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2613 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2614 | before calculating this offset. This should not be a problem unless |
2615 | the low bits of start_addr and region_offset differ. */ | |
0f0cb164 AK |
2616 | static void register_subpage(MemoryRegionSection *section) |
2617 | { | |
2618 | subpage_t *subpage; | |
2619 | target_phys_addr_t base = section->offset_within_address_space | |
2620 | & TARGET_PAGE_MASK; | |
2621 | MemoryRegionSection existing = phys_page_find(base >> TARGET_PAGE_BITS); | |
2622 | MemoryRegionSection subsection = { | |
2623 | .offset_within_address_space = base, | |
2624 | .size = TARGET_PAGE_SIZE, | |
2625 | }; | |
0f0cb164 AK |
2626 | target_phys_addr_t start, end; |
2627 | ||
2628 | assert(existing.mr->subpage || existing.mr == &io_mem_unassigned); | |
2629 | ||
2630 | if (!(existing.mr->subpage)) { | |
2631 | subpage = subpage_init(base); | |
2632 | subsection.mr = &subpage->iomem; | |
a3918432 | 2633 | phys_page_set(base >> TARGET_PAGE_BITS, phys_section_add(&subsection)); |
0f0cb164 AK |
2634 | } else { |
2635 | subpage = container_of(existing.mr, subpage_t, iomem); | |
2636 | } | |
2637 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
2638 | end = start + section->size; | |
2639 | subpage_register(subpage, start, end, phys_section_add(section)); | |
2640 | } | |
2641 | ||
2642 | ||
2643 | static void register_multipage(MemoryRegionSection *section) | |
33417e70 | 2644 | { |
dd81124b AK |
2645 | target_phys_addr_t start_addr = section->offset_within_address_space; |
2646 | ram_addr_t size = section->size; | |
c227f099 | 2647 | target_phys_addr_t addr, end_addr; |
5312bd8b | 2648 | uint16_t section_index = phys_section_add(section); |
dd81124b | 2649 | |
3b8e6a2d | 2650 | assert(size); |
f6f3fbca | 2651 | |
c227f099 | 2652 | end_addr = start_addr + (target_phys_addr_t)size; |
3b8e6a2d EI |
2653 | |
2654 | addr = start_addr; | |
2655 | do { | |
a3918432 | 2656 | phys_page_set(addr >> TARGET_PAGE_BITS, section_index); |
3b8e6a2d EI |
2657 | addr += TARGET_PAGE_SIZE; |
2658 | } while (addr != end_addr); | |
33417e70 FB |
2659 | } |
2660 | ||
0f0cb164 AK |
2661 | void cpu_register_physical_memory_log(MemoryRegionSection *section, |
2662 | bool readonly) | |
2663 | { | |
2664 | MemoryRegionSection now = *section, remain = *section; | |
2665 | ||
2666 | if ((now.offset_within_address_space & ~TARGET_PAGE_MASK) | |
2667 | || (now.size < TARGET_PAGE_SIZE)) { | |
2668 | now.size = MIN(TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
2669 | - now.offset_within_address_space, | |
2670 | now.size); | |
2671 | register_subpage(&now); | |
2672 | remain.size -= now.size; | |
2673 | remain.offset_within_address_space += now.size; | |
2674 | remain.offset_within_region += now.size; | |
2675 | } | |
2676 | now = remain; | |
2677 | now.size &= TARGET_PAGE_MASK; | |
2678 | if (now.size) { | |
2679 | register_multipage(&now); | |
2680 | remain.size -= now.size; | |
2681 | remain.offset_within_address_space += now.size; | |
2682 | remain.offset_within_region += now.size; | |
2683 | } | |
2684 | now = remain; | |
2685 | if (now.size) { | |
2686 | register_subpage(&now); | |
2687 | } | |
2688 | } | |
2689 | ||
2690 | ||
c227f099 | 2691 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2692 | { |
2693 | if (kvm_enabled()) | |
2694 | kvm_coalesce_mmio_region(addr, size); | |
2695 | } | |
2696 | ||
c227f099 | 2697 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2698 | { |
2699 | if (kvm_enabled()) | |
2700 | kvm_uncoalesce_mmio_region(addr, size); | |
2701 | } | |
2702 | ||
62a2744c SY |
2703 | void qemu_flush_coalesced_mmio_buffer(void) |
2704 | { | |
2705 | if (kvm_enabled()) | |
2706 | kvm_flush_coalesced_mmio_buffer(); | |
2707 | } | |
2708 | ||
c902760f MT |
2709 | #if defined(__linux__) && !defined(TARGET_S390X) |
2710 | ||
2711 | #include <sys/vfs.h> | |
2712 | ||
2713 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2714 | ||
2715 | static long gethugepagesize(const char *path) | |
2716 | { | |
2717 | struct statfs fs; | |
2718 | int ret; | |
2719 | ||
2720 | do { | |
9742bf26 | 2721 | ret = statfs(path, &fs); |
c902760f MT |
2722 | } while (ret != 0 && errno == EINTR); |
2723 | ||
2724 | if (ret != 0) { | |
9742bf26 YT |
2725 | perror(path); |
2726 | return 0; | |
c902760f MT |
2727 | } |
2728 | ||
2729 | if (fs.f_type != HUGETLBFS_MAGIC) | |
9742bf26 | 2730 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
c902760f MT |
2731 | |
2732 | return fs.f_bsize; | |
2733 | } | |
2734 | ||
04b16653 AW |
2735 | static void *file_ram_alloc(RAMBlock *block, |
2736 | ram_addr_t memory, | |
2737 | const char *path) | |
c902760f MT |
2738 | { |
2739 | char *filename; | |
2740 | void *area; | |
2741 | int fd; | |
2742 | #ifdef MAP_POPULATE | |
2743 | int flags; | |
2744 | #endif | |
2745 | unsigned long hpagesize; | |
2746 | ||
2747 | hpagesize = gethugepagesize(path); | |
2748 | if (!hpagesize) { | |
9742bf26 | 2749 | return NULL; |
c902760f MT |
2750 | } |
2751 | ||
2752 | if (memory < hpagesize) { | |
2753 | return NULL; | |
2754 | } | |
2755 | ||
2756 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2757 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2758 | return NULL; | |
2759 | } | |
2760 | ||
2761 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
9742bf26 | 2762 | return NULL; |
c902760f MT |
2763 | } |
2764 | ||
2765 | fd = mkstemp(filename); | |
2766 | if (fd < 0) { | |
9742bf26 YT |
2767 | perror("unable to create backing store for hugepages"); |
2768 | free(filename); | |
2769 | return NULL; | |
c902760f MT |
2770 | } |
2771 | unlink(filename); | |
2772 | free(filename); | |
2773 | ||
2774 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2775 | ||
2776 | /* | |
2777 | * ftruncate is not supported by hugetlbfs in older | |
2778 | * hosts, so don't bother bailing out on errors. | |
2779 | * If anything goes wrong with it under other filesystems, | |
2780 | * mmap will fail. | |
2781 | */ | |
2782 | if (ftruncate(fd, memory)) | |
9742bf26 | 2783 | perror("ftruncate"); |
c902760f MT |
2784 | |
2785 | #ifdef MAP_POPULATE | |
2786 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2787 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2788 | * to sidestep this quirk. | |
2789 | */ | |
2790 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2791 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2792 | #else | |
2793 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2794 | #endif | |
2795 | if (area == MAP_FAILED) { | |
9742bf26 YT |
2796 | perror("file_ram_alloc: can't mmap RAM pages"); |
2797 | close(fd); | |
2798 | return (NULL); | |
c902760f | 2799 | } |
04b16653 | 2800 | block->fd = fd; |
c902760f MT |
2801 | return area; |
2802 | } | |
2803 | #endif | |
2804 | ||
d17b5288 | 2805 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
2806 | { |
2807 | RAMBlock *block, *next_block; | |
3e837b2c | 2808 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 AW |
2809 | |
2810 | if (QLIST_EMPTY(&ram_list.blocks)) | |
2811 | return 0; | |
2812 | ||
2813 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
f15fbc4b | 2814 | ram_addr_t end, next = RAM_ADDR_MAX; |
04b16653 AW |
2815 | |
2816 | end = block->offset + block->length; | |
2817 | ||
2818 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { | |
2819 | if (next_block->offset >= end) { | |
2820 | next = MIN(next, next_block->offset); | |
2821 | } | |
2822 | } | |
2823 | if (next - end >= size && next - end < mingap) { | |
3e837b2c | 2824 | offset = end; |
04b16653 AW |
2825 | mingap = next - end; |
2826 | } | |
2827 | } | |
3e837b2c AW |
2828 | |
2829 | if (offset == RAM_ADDR_MAX) { | |
2830 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
2831 | (uint64_t)size); | |
2832 | abort(); | |
2833 | } | |
2834 | ||
04b16653 AW |
2835 | return offset; |
2836 | } | |
2837 | ||
2838 | static ram_addr_t last_ram_offset(void) | |
d17b5288 AW |
2839 | { |
2840 | RAMBlock *block; | |
2841 | ram_addr_t last = 0; | |
2842 | ||
2843 | QLIST_FOREACH(block, &ram_list.blocks, next) | |
2844 | last = MAX(last, block->offset + block->length); | |
2845 | ||
2846 | return last; | |
2847 | } | |
2848 | ||
c5705a77 | 2849 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
84b89d78 CM |
2850 | { |
2851 | RAMBlock *new_block, *block; | |
2852 | ||
c5705a77 AK |
2853 | new_block = NULL; |
2854 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2855 | if (block->offset == addr) { | |
2856 | new_block = block; | |
2857 | break; | |
2858 | } | |
2859 | } | |
2860 | assert(new_block); | |
2861 | assert(!new_block->idstr[0]); | |
84b89d78 CM |
2862 | |
2863 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { | |
2864 | char *id = dev->parent_bus->info->get_dev_path(dev); | |
2865 | if (id) { | |
2866 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 2867 | g_free(id); |
84b89d78 CM |
2868 | } |
2869 | } | |
2870 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2871 | ||
2872 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
c5705a77 | 2873 | if (block != new_block && !strcmp(block->idstr, new_block->idstr)) { |
84b89d78 CM |
2874 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
2875 | new_block->idstr); | |
2876 | abort(); | |
2877 | } | |
2878 | } | |
c5705a77 AK |
2879 | } |
2880 | ||
2881 | ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, | |
2882 | MemoryRegion *mr) | |
2883 | { | |
2884 | RAMBlock *new_block; | |
2885 | ||
2886 | size = TARGET_PAGE_ALIGN(size); | |
2887 | new_block = g_malloc0(sizeof(*new_block)); | |
84b89d78 | 2888 | |
7c637366 | 2889 | new_block->mr = mr; |
432d268c | 2890 | new_block->offset = find_ram_offset(size); |
6977dfe6 YT |
2891 | if (host) { |
2892 | new_block->host = host; | |
cd19cfa2 | 2893 | new_block->flags |= RAM_PREALLOC_MASK; |
6977dfe6 YT |
2894 | } else { |
2895 | if (mem_path) { | |
c902760f | 2896 | #if defined (__linux__) && !defined(TARGET_S390X) |
6977dfe6 YT |
2897 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
2898 | if (!new_block->host) { | |
2899 | new_block->host = qemu_vmalloc(size); | |
e78815a5 | 2900 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2901 | } |
c902760f | 2902 | #else |
6977dfe6 YT |
2903 | fprintf(stderr, "-mem-path option unsupported\n"); |
2904 | exit(1); | |
c902760f | 2905 | #endif |
6977dfe6 | 2906 | } else { |
6b02494d | 2907 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
ff83678a CB |
2908 | /* S390 KVM requires the topmost vma of the RAM to be smaller than |
2909 | an system defined value, which is at least 256GB. Larger systems | |
2910 | have larger values. We put the guest between the end of data | |
2911 | segment (system break) and this value. We use 32GB as a base to | |
2912 | have enough room for the system break to grow. */ | |
2913 | new_block->host = mmap((void*)0x800000000, size, | |
6977dfe6 | 2914 | PROT_EXEC|PROT_READ|PROT_WRITE, |
ff83678a | 2915 | MAP_SHARED | MAP_ANONYMOUS | MAP_FIXED, -1, 0); |
fb8b2735 AG |
2916 | if (new_block->host == MAP_FAILED) { |
2917 | fprintf(stderr, "Allocating RAM failed\n"); | |
2918 | abort(); | |
2919 | } | |
6b02494d | 2920 | #else |
868bb33f | 2921 | if (xen_enabled()) { |
fce537d4 | 2922 | xen_ram_alloc(new_block->offset, size, mr); |
432d268c JN |
2923 | } else { |
2924 | new_block->host = qemu_vmalloc(size); | |
2925 | } | |
6b02494d | 2926 | #endif |
e78815a5 | 2927 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2928 | } |
c902760f | 2929 | } |
94a6b54f PB |
2930 | new_block->length = size; |
2931 | ||
f471a17e | 2932 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
94a6b54f | 2933 | |
7267c094 | 2934 | ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, |
04b16653 | 2935 | last_ram_offset() >> TARGET_PAGE_BITS); |
d17b5288 | 2936 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
94a6b54f PB |
2937 | 0xff, size >> TARGET_PAGE_BITS); |
2938 | ||
6f0437e8 JK |
2939 | if (kvm_enabled()) |
2940 | kvm_setup_guest_memory(new_block->host, size); | |
2941 | ||
94a6b54f PB |
2942 | return new_block->offset; |
2943 | } | |
e9a1ab19 | 2944 | |
c5705a77 | 2945 | ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr) |
6977dfe6 | 2946 | { |
c5705a77 | 2947 | return qemu_ram_alloc_from_ptr(size, NULL, mr); |
6977dfe6 YT |
2948 | } |
2949 | ||
1f2e98b6 AW |
2950 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
2951 | { | |
2952 | RAMBlock *block; | |
2953 | ||
2954 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2955 | if (addr == block->offset) { | |
2956 | QLIST_REMOVE(block, next); | |
7267c094 | 2957 | g_free(block); |
1f2e98b6 AW |
2958 | return; |
2959 | } | |
2960 | } | |
2961 | } | |
2962 | ||
c227f099 | 2963 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2964 | { |
04b16653 AW |
2965 | RAMBlock *block; |
2966 | ||
2967 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2968 | if (addr == block->offset) { | |
2969 | QLIST_REMOVE(block, next); | |
cd19cfa2 HY |
2970 | if (block->flags & RAM_PREALLOC_MASK) { |
2971 | ; | |
2972 | } else if (mem_path) { | |
04b16653 AW |
2973 | #if defined (__linux__) && !defined(TARGET_S390X) |
2974 | if (block->fd) { | |
2975 | munmap(block->host, block->length); | |
2976 | close(block->fd); | |
2977 | } else { | |
2978 | qemu_vfree(block->host); | |
2979 | } | |
fd28aa13 JK |
2980 | #else |
2981 | abort(); | |
04b16653 AW |
2982 | #endif |
2983 | } else { | |
2984 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
2985 | munmap(block->host, block->length); | |
2986 | #else | |
868bb33f | 2987 | if (xen_enabled()) { |
e41d7c69 | 2988 | xen_invalidate_map_cache_entry(block->host); |
432d268c JN |
2989 | } else { |
2990 | qemu_vfree(block->host); | |
2991 | } | |
04b16653 AW |
2992 | #endif |
2993 | } | |
7267c094 | 2994 | g_free(block); |
04b16653 AW |
2995 | return; |
2996 | } | |
2997 | } | |
2998 | ||
e9a1ab19 FB |
2999 | } |
3000 | ||
cd19cfa2 HY |
3001 | #ifndef _WIN32 |
3002 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
3003 | { | |
3004 | RAMBlock *block; | |
3005 | ram_addr_t offset; | |
3006 | int flags; | |
3007 | void *area, *vaddr; | |
3008 | ||
3009 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3010 | offset = addr - block->offset; | |
3011 | if (offset < block->length) { | |
3012 | vaddr = block->host + offset; | |
3013 | if (block->flags & RAM_PREALLOC_MASK) { | |
3014 | ; | |
3015 | } else { | |
3016 | flags = MAP_FIXED; | |
3017 | munmap(vaddr, length); | |
3018 | if (mem_path) { | |
3019 | #if defined(__linux__) && !defined(TARGET_S390X) | |
3020 | if (block->fd) { | |
3021 | #ifdef MAP_POPULATE | |
3022 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : | |
3023 | MAP_PRIVATE; | |
3024 | #else | |
3025 | flags |= MAP_PRIVATE; | |
3026 | #endif | |
3027 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3028 | flags, block->fd, offset); | |
3029 | } else { | |
3030 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3031 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3032 | flags, -1, 0); | |
3033 | } | |
fd28aa13 JK |
3034 | #else |
3035 | abort(); | |
cd19cfa2 HY |
3036 | #endif |
3037 | } else { | |
3038 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
3039 | flags |= MAP_SHARED | MAP_ANONYMOUS; | |
3040 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, | |
3041 | flags, -1, 0); | |
3042 | #else | |
3043 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3044 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3045 | flags, -1, 0); | |
3046 | #endif | |
3047 | } | |
3048 | if (area != vaddr) { | |
f15fbc4b AP |
3049 | fprintf(stderr, "Could not remap addr: " |
3050 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
cd19cfa2 HY |
3051 | length, addr); |
3052 | exit(1); | |
3053 | } | |
3054 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); | |
3055 | } | |
3056 | return; | |
3057 | } | |
3058 | } | |
3059 | } | |
3060 | #endif /* !_WIN32 */ | |
3061 | ||
dc828ca1 | 3062 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
3063 | With the exception of the softmmu code in this file, this should |
3064 | only be used for local memory (e.g. video ram) that the device owns, | |
3065 | and knows it isn't going to access beyond the end of the block. | |
3066 | ||
3067 | It should not be used for general purpose DMA. | |
3068 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
3069 | */ | |
c227f099 | 3070 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 3071 | { |
94a6b54f PB |
3072 | RAMBlock *block; |
3073 | ||
f471a17e AW |
3074 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
3075 | if (addr - block->offset < block->length) { | |
7d82af38 VP |
3076 | /* Move this entry to to start of the list. */ |
3077 | if (block != QLIST_FIRST(&ram_list.blocks)) { | |
3078 | QLIST_REMOVE(block, next); | |
3079 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); | |
3080 | } | |
868bb33f | 3081 | if (xen_enabled()) { |
432d268c JN |
3082 | /* We need to check if the requested address is in the RAM |
3083 | * because we don't want to map the entire memory in QEMU. | |
712c2b41 | 3084 | * In that case just map until the end of the page. |
432d268c JN |
3085 | */ |
3086 | if (block->offset == 0) { | |
e41d7c69 | 3087 | return xen_map_cache(addr, 0, 0); |
432d268c | 3088 | } else if (block->host == NULL) { |
e41d7c69 JK |
3089 | block->host = |
3090 | xen_map_cache(block->offset, block->length, 1); | |
432d268c JN |
3091 | } |
3092 | } | |
f471a17e AW |
3093 | return block->host + (addr - block->offset); |
3094 | } | |
94a6b54f | 3095 | } |
f471a17e AW |
3096 | |
3097 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3098 | abort(); | |
3099 | ||
3100 | return NULL; | |
dc828ca1 PB |
3101 | } |
3102 | ||
b2e0a138 MT |
3103 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
3104 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. | |
3105 | */ | |
3106 | void *qemu_safe_ram_ptr(ram_addr_t addr) | |
3107 | { | |
3108 | RAMBlock *block; | |
3109 | ||
3110 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3111 | if (addr - block->offset < block->length) { | |
868bb33f | 3112 | if (xen_enabled()) { |
432d268c JN |
3113 | /* We need to check if the requested address is in the RAM |
3114 | * because we don't want to map the entire memory in QEMU. | |
712c2b41 | 3115 | * In that case just map until the end of the page. |
432d268c JN |
3116 | */ |
3117 | if (block->offset == 0) { | |
e41d7c69 | 3118 | return xen_map_cache(addr, 0, 0); |
432d268c | 3119 | } else if (block->host == NULL) { |
e41d7c69 JK |
3120 | block->host = |
3121 | xen_map_cache(block->offset, block->length, 1); | |
432d268c JN |
3122 | } |
3123 | } | |
b2e0a138 MT |
3124 | return block->host + (addr - block->offset); |
3125 | } | |
3126 | } | |
3127 | ||
3128 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3129 | abort(); | |
3130 | ||
3131 | return NULL; | |
3132 | } | |
3133 | ||
38bee5dc SS |
3134 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
3135 | * but takes a size argument */ | |
8ab934f9 | 3136 | void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) |
38bee5dc | 3137 | { |
8ab934f9 SS |
3138 | if (*size == 0) { |
3139 | return NULL; | |
3140 | } | |
868bb33f | 3141 | if (xen_enabled()) { |
e41d7c69 | 3142 | return xen_map_cache(addr, *size, 1); |
868bb33f | 3143 | } else { |
38bee5dc SS |
3144 | RAMBlock *block; |
3145 | ||
3146 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3147 | if (addr - block->offset < block->length) { | |
3148 | if (addr - block->offset + *size > block->length) | |
3149 | *size = block->length - addr + block->offset; | |
3150 | return block->host + (addr - block->offset); | |
3151 | } | |
3152 | } | |
3153 | ||
3154 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3155 | abort(); | |
38bee5dc SS |
3156 | } |
3157 | } | |
3158 | ||
050a0ddf AP |
3159 | void qemu_put_ram_ptr(void *addr) |
3160 | { | |
3161 | trace_qemu_put_ram_ptr(addr); | |
050a0ddf AP |
3162 | } |
3163 | ||
e890261f | 3164 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
5579c7f3 | 3165 | { |
94a6b54f PB |
3166 | RAMBlock *block; |
3167 | uint8_t *host = ptr; | |
3168 | ||
868bb33f | 3169 | if (xen_enabled()) { |
e41d7c69 | 3170 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
712c2b41 SS |
3171 | return 0; |
3172 | } | |
3173 | ||
f471a17e | 3174 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
432d268c JN |
3175 | /* This case append when the block is not mapped. */ |
3176 | if (block->host == NULL) { | |
3177 | continue; | |
3178 | } | |
f471a17e | 3179 | if (host - block->host < block->length) { |
e890261f MT |
3180 | *ram_addr = block->offset + (host - block->host); |
3181 | return 0; | |
f471a17e | 3182 | } |
94a6b54f | 3183 | } |
432d268c | 3184 | |
e890261f MT |
3185 | return -1; |
3186 | } | |
f471a17e | 3187 | |
e890261f MT |
3188 | /* Some of the softmmu routines need to translate from a host pointer |
3189 | (typically a TLB entry) back to a ram offset. */ | |
3190 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) | |
3191 | { | |
3192 | ram_addr_t ram_addr; | |
f471a17e | 3193 | |
e890261f MT |
3194 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
3195 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
3196 | abort(); | |
3197 | } | |
3198 | return ram_addr; | |
5579c7f3 PB |
3199 | } |
3200 | ||
0e0df1e2 AK |
3201 | static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr, |
3202 | unsigned size) | |
e18231a3 BS |
3203 | { |
3204 | #ifdef DEBUG_UNASSIGNED | |
3205 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3206 | #endif | |
5b450407 | 3207 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
0e0df1e2 | 3208 | cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); |
e18231a3 BS |
3209 | #endif |
3210 | return 0; | |
3211 | } | |
3212 | ||
0e0df1e2 AK |
3213 | static void unassigned_mem_write(void *opaque, target_phys_addr_t addr, |
3214 | uint64_t val, unsigned size) | |
e18231a3 BS |
3215 | { |
3216 | #ifdef DEBUG_UNASSIGNED | |
0e0df1e2 | 3217 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); |
e18231a3 | 3218 | #endif |
5b450407 | 3219 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
0e0df1e2 | 3220 | cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); |
67d3b957 | 3221 | #endif |
33417e70 FB |
3222 | } |
3223 | ||
0e0df1e2 AK |
3224 | static const MemoryRegionOps unassigned_mem_ops = { |
3225 | .read = unassigned_mem_read, | |
3226 | .write = unassigned_mem_write, | |
3227 | .endianness = DEVICE_NATIVE_ENDIAN, | |
3228 | }; | |
e18231a3 | 3229 | |
0e0df1e2 AK |
3230 | static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr, |
3231 | unsigned size) | |
e18231a3 | 3232 | { |
0e0df1e2 | 3233 | abort(); |
e18231a3 BS |
3234 | } |
3235 | ||
0e0df1e2 AK |
3236 | static void error_mem_write(void *opaque, target_phys_addr_t addr, |
3237 | uint64_t value, unsigned size) | |
e18231a3 | 3238 | { |
0e0df1e2 | 3239 | abort(); |
33417e70 FB |
3240 | } |
3241 | ||
0e0df1e2 AK |
3242 | static const MemoryRegionOps error_mem_ops = { |
3243 | .read = error_mem_read, | |
3244 | .write = error_mem_write, | |
3245 | .endianness = DEVICE_NATIVE_ENDIAN, | |
33417e70 FB |
3246 | }; |
3247 | ||
0e0df1e2 AK |
3248 | static const MemoryRegionOps rom_mem_ops = { |
3249 | .read = error_mem_read, | |
3250 | .write = unassigned_mem_write, | |
3251 | .endianness = DEVICE_NATIVE_ENDIAN, | |
33417e70 FB |
3252 | }; |
3253 | ||
0e0df1e2 AK |
3254 | static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr, |
3255 | uint64_t val, unsigned size) | |
9fa3e853 | 3256 | { |
3a7d929e | 3257 | int dirty_flags; |
f7c11b53 | 3258 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3259 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3260 | #if !defined(CONFIG_USER_ONLY) |
0e0df1e2 | 3261 | tb_invalidate_phys_page_fast(ram_addr, size); |
f7c11b53 | 3262 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3263 | #endif |
3a7d929e | 3264 | } |
0e0df1e2 AK |
3265 | switch (size) { |
3266 | case 1: | |
3267 | stb_p(qemu_get_ram_ptr(ram_addr), val); | |
3268 | break; | |
3269 | case 2: | |
3270 | stw_p(qemu_get_ram_ptr(ram_addr), val); | |
3271 | break; | |
3272 | case 4: | |
3273 | stl_p(qemu_get_ram_ptr(ram_addr), val); | |
3274 | break; | |
3275 | default: | |
3276 | abort(); | |
3a7d929e | 3277 | } |
f23db169 | 3278 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3279 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3280 | /* we remove the notdirty callback only if the code has been |
3281 | flushed */ | |
3282 | if (dirty_flags == 0xff) | |
2e70f6ef | 3283 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3284 | } |
3285 | ||
0e0df1e2 AK |
3286 | static const MemoryRegionOps notdirty_mem_ops = { |
3287 | .read = error_mem_read, | |
3288 | .write = notdirty_mem_write, | |
3289 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1ccde1cb FB |
3290 | }; |
3291 | ||
0f459d16 | 3292 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 3293 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
3294 | { |
3295 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
3296 | target_ulong pc, cs_base; |
3297 | TranslationBlock *tb; | |
0f459d16 | 3298 | target_ulong vaddr; |
a1d1bb31 | 3299 | CPUWatchpoint *wp; |
06d55cc1 | 3300 | int cpu_flags; |
0f459d16 | 3301 | |
06d55cc1 AL |
3302 | if (env->watchpoint_hit) { |
3303 | /* We re-entered the check after replacing the TB. Now raise | |
3304 | * the debug interrupt so that is will trigger after the | |
3305 | * current instruction. */ | |
3306 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
3307 | return; | |
3308 | } | |
2e70f6ef | 3309 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 3310 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
3311 | if ((vaddr == (wp->vaddr & len_mask) || |
3312 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
3313 | wp->flags |= BP_WATCHPOINT_HIT; |
3314 | if (!env->watchpoint_hit) { | |
3315 | env->watchpoint_hit = wp; | |
3316 | tb = tb_find_pc(env->mem_io_pc); | |
3317 | if (!tb) { | |
3318 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
3319 | "pc=%p", (void *)env->mem_io_pc); | |
3320 | } | |
618ba8e6 | 3321 | cpu_restore_state(tb, env, env->mem_io_pc); |
6e140f28 AL |
3322 | tb_phys_invalidate(tb, -1); |
3323 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
3324 | env->exception_index = EXCP_DEBUG; | |
3325 | } else { | |
3326 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
3327 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
3328 | } | |
3329 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 3330 | } |
6e140f28 AL |
3331 | } else { |
3332 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
3333 | } |
3334 | } | |
3335 | } | |
3336 | ||
6658ffb8 PB |
3337 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
3338 | so these check for a hit then pass through to the normal out-of-line | |
3339 | phys routines. */ | |
1ec9b909 AK |
3340 | static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr, |
3341 | unsigned size) | |
6658ffb8 | 3342 | { |
1ec9b909 AK |
3343 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ); |
3344 | switch (size) { | |
3345 | case 1: return ldub_phys(addr); | |
3346 | case 2: return lduw_phys(addr); | |
3347 | case 4: return ldl_phys(addr); | |
3348 | default: abort(); | |
3349 | } | |
6658ffb8 PB |
3350 | } |
3351 | ||
1ec9b909 AK |
3352 | static void watch_mem_write(void *opaque, target_phys_addr_t addr, |
3353 | uint64_t val, unsigned size) | |
6658ffb8 | 3354 | { |
1ec9b909 AK |
3355 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE); |
3356 | switch (size) { | |
3357 | case 1: stb_phys(addr, val); | |
3358 | case 2: stw_phys(addr, val); | |
3359 | case 4: stl_phys(addr, val); | |
3360 | default: abort(); | |
3361 | } | |
6658ffb8 PB |
3362 | } |
3363 | ||
1ec9b909 AK |
3364 | static const MemoryRegionOps watch_mem_ops = { |
3365 | .read = watch_mem_read, | |
3366 | .write = watch_mem_write, | |
3367 | .endianness = DEVICE_NATIVE_ENDIAN, | |
6658ffb8 | 3368 | }; |
6658ffb8 | 3369 | |
70c68e44 AK |
3370 | static uint64_t subpage_read(void *opaque, target_phys_addr_t addr, |
3371 | unsigned len) | |
db7b5426 | 3372 | { |
70c68e44 | 3373 | subpage_t *mmio = opaque; |
f6405247 | 3374 | unsigned int idx = SUBPAGE_IDX(addr); |
5312bd8b | 3375 | MemoryRegionSection *section; |
db7b5426 BS |
3376 | #if defined(DEBUG_SUBPAGE) |
3377 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3378 | mmio, len, addr, idx); | |
3379 | #endif | |
db7b5426 | 3380 | |
5312bd8b AK |
3381 | section = &phys_sections[mmio->sub_section[idx]]; |
3382 | addr += mmio->base; | |
3383 | addr -= section->offset_within_address_space; | |
3384 | addr += section->offset_within_region; | |
3385 | return io_mem_read(section->mr->ram_addr, addr, len); | |
db7b5426 BS |
3386 | } |
3387 | ||
70c68e44 AK |
3388 | static void subpage_write(void *opaque, target_phys_addr_t addr, |
3389 | uint64_t value, unsigned len) | |
db7b5426 | 3390 | { |
70c68e44 | 3391 | subpage_t *mmio = opaque; |
f6405247 | 3392 | unsigned int idx = SUBPAGE_IDX(addr); |
5312bd8b | 3393 | MemoryRegionSection *section; |
db7b5426 | 3394 | #if defined(DEBUG_SUBPAGE) |
70c68e44 AK |
3395 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx |
3396 | " idx %d value %"PRIx64"\n", | |
f6405247 | 3397 | __func__, mmio, len, addr, idx, value); |
db7b5426 | 3398 | #endif |
f6405247 | 3399 | |
5312bd8b AK |
3400 | section = &phys_sections[mmio->sub_section[idx]]; |
3401 | addr += mmio->base; | |
3402 | addr -= section->offset_within_address_space; | |
3403 | addr += section->offset_within_region; | |
3404 | io_mem_write(section->mr->ram_addr, addr, value, len); | |
db7b5426 BS |
3405 | } |
3406 | ||
70c68e44 AK |
3407 | static const MemoryRegionOps subpage_ops = { |
3408 | .read = subpage_read, | |
3409 | .write = subpage_write, | |
3410 | .endianness = DEVICE_NATIVE_ENDIAN, | |
db7b5426 BS |
3411 | }; |
3412 | ||
de712f94 AK |
3413 | static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr, |
3414 | unsigned size) | |
56384e8b AF |
3415 | { |
3416 | ram_addr_t raddr = addr; | |
3417 | void *ptr = qemu_get_ram_ptr(raddr); | |
de712f94 AK |
3418 | switch (size) { |
3419 | case 1: return ldub_p(ptr); | |
3420 | case 2: return lduw_p(ptr); | |
3421 | case 4: return ldl_p(ptr); | |
3422 | default: abort(); | |
3423 | } | |
56384e8b AF |
3424 | } |
3425 | ||
de712f94 AK |
3426 | static void subpage_ram_write(void *opaque, target_phys_addr_t addr, |
3427 | uint64_t value, unsigned size) | |
56384e8b AF |
3428 | { |
3429 | ram_addr_t raddr = addr; | |
3430 | void *ptr = qemu_get_ram_ptr(raddr); | |
de712f94 AK |
3431 | switch (size) { |
3432 | case 1: return stb_p(ptr, value); | |
3433 | case 2: return stw_p(ptr, value); | |
3434 | case 4: return stl_p(ptr, value); | |
3435 | default: abort(); | |
3436 | } | |
56384e8b AF |
3437 | } |
3438 | ||
de712f94 AK |
3439 | static const MemoryRegionOps subpage_ram_ops = { |
3440 | .read = subpage_ram_read, | |
3441 | .write = subpage_ram_write, | |
3442 | .endianness = DEVICE_NATIVE_ENDIAN, | |
56384e8b AF |
3443 | }; |
3444 | ||
c227f099 | 3445 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 3446 | uint16_t section) |
db7b5426 BS |
3447 | { |
3448 | int idx, eidx; | |
3449 | ||
3450 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3451 | return -1; | |
3452 | idx = SUBPAGE_IDX(start); | |
3453 | eidx = SUBPAGE_IDX(end); | |
3454 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 3455 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
3456 | mmio, start, end, idx, eidx, memory); |
3457 | #endif | |
5312bd8b AK |
3458 | if (memory_region_is_ram(phys_sections[section].mr)) { |
3459 | MemoryRegionSection new_section = phys_sections[section]; | |
3460 | new_section.mr = &io_mem_subpage_ram; | |
3461 | section = phys_section_add(&new_section); | |
56384e8b | 3462 | } |
db7b5426 | 3463 | for (; idx <= eidx; idx++) { |
5312bd8b | 3464 | mmio->sub_section[idx] = section; |
db7b5426 BS |
3465 | } |
3466 | ||
3467 | return 0; | |
3468 | } | |
3469 | ||
0f0cb164 | 3470 | static subpage_t *subpage_init(target_phys_addr_t base) |
db7b5426 | 3471 | { |
c227f099 | 3472 | subpage_t *mmio; |
db7b5426 | 3473 | |
7267c094 | 3474 | mmio = g_malloc0(sizeof(subpage_t)); |
1eec614b AL |
3475 | |
3476 | mmio->base = base; | |
70c68e44 AK |
3477 | memory_region_init_io(&mmio->iomem, &subpage_ops, mmio, |
3478 | "subpage", TARGET_PAGE_SIZE); | |
b3b00c78 | 3479 | mmio->iomem.subpage = true; |
db7b5426 | 3480 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3481 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3482 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3483 | #endif |
0f0cb164 | 3484 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, phys_section_unassigned); |
db7b5426 BS |
3485 | |
3486 | return mmio; | |
3487 | } | |
3488 | ||
88715657 AL |
3489 | static int get_free_io_mem_idx(void) |
3490 | { | |
3491 | int i; | |
3492 | ||
3493 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3494 | if (!io_mem_used[i]) { | |
3495 | io_mem_used[i] = 1; | |
3496 | return i; | |
3497 | } | |
c6703b47 | 3498 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3499 | return -1; |
3500 | } | |
3501 | ||
33417e70 FB |
3502 | /* mem_read and mem_write are arrays of functions containing the |
3503 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3504 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3505 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3506 | modified. If it is zero, a new io zone is allocated. The return |
3507 | value can be used with cpu_register_physical_memory(). (-1) is | |
3508 | returned if error. */ | |
a621f38d | 3509 | static int cpu_register_io_memory_fixed(int io_index, MemoryRegion *mr) |
33417e70 | 3510 | { |
33417e70 | 3511 | if (io_index <= 0) { |
88715657 AL |
3512 | io_index = get_free_io_mem_idx(); |
3513 | if (io_index == -1) | |
3514 | return io_index; | |
33417e70 FB |
3515 | } else { |
3516 | if (io_index >= IO_MEM_NB_ENTRIES) | |
3517 | return -1; | |
3518 | } | |
b5ff1b31 | 3519 | |
a621f38d | 3520 | io_mem_region[io_index] = mr; |
f6405247 | 3521 | |
11c7ef0c | 3522 | return io_index; |
33417e70 | 3523 | } |
61382a50 | 3524 | |
a621f38d | 3525 | int cpu_register_io_memory(MemoryRegion *mr) |
1eed09cb | 3526 | { |
a621f38d | 3527 | return cpu_register_io_memory_fixed(0, mr); |
1eed09cb AK |
3528 | } |
3529 | ||
11c7ef0c | 3530 | void cpu_unregister_io_memory(int io_index) |
88715657 | 3531 | { |
a621f38d | 3532 | io_mem_region[io_index] = NULL; |
88715657 AL |
3533 | io_mem_used[io_index] = 0; |
3534 | } | |
3535 | ||
5312bd8b AK |
3536 | static uint16_t dummy_section(MemoryRegion *mr) |
3537 | { | |
3538 | MemoryRegionSection section = { | |
3539 | .mr = mr, | |
3540 | .offset_within_address_space = 0, | |
3541 | .offset_within_region = 0, | |
3542 | .size = UINT64_MAX, | |
3543 | }; | |
3544 | ||
3545 | return phys_section_add(§ion); | |
3546 | } | |
3547 | ||
e9179ce1 AK |
3548 | static void io_mem_init(void) |
3549 | { | |
3550 | int i; | |
3551 | ||
0e0df1e2 AK |
3552 | /* Must be first: */ |
3553 | memory_region_init_io(&io_mem_ram, &error_mem_ops, NULL, "ram", UINT64_MAX); | |
3554 | assert(io_mem_ram.ram_addr == 0); | |
3555 | memory_region_init_io(&io_mem_rom, &rom_mem_ops, NULL, "rom", UINT64_MAX); | |
3556 | memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL, | |
3557 | "unassigned", UINT64_MAX); | |
3558 | memory_region_init_io(&io_mem_notdirty, ¬dirty_mem_ops, NULL, | |
3559 | "notdirty", UINT64_MAX); | |
de712f94 AK |
3560 | memory_region_init_io(&io_mem_subpage_ram, &subpage_ram_ops, NULL, |
3561 | "subpage-ram", UINT64_MAX); | |
e9179ce1 AK |
3562 | for (i=0; i<5; i++) |
3563 | io_mem_used[i] = 1; | |
3564 | ||
1ec9b909 AK |
3565 | memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL, |
3566 | "watch", UINT64_MAX); | |
e9179ce1 AK |
3567 | } |
3568 | ||
50c1e149 AK |
3569 | static void core_begin(MemoryListener *listener) |
3570 | { | |
54688b1e | 3571 | destroy_all_mappings(); |
5312bd8b | 3572 | phys_sections_clear(); |
d6f2ea22 | 3573 | phys_map.u.node = PHYS_MAP_NODE_NIL; |
5312bd8b | 3574 | phys_section_unassigned = dummy_section(&io_mem_unassigned); |
50c1e149 AK |
3575 | } |
3576 | ||
3577 | static void core_commit(MemoryListener *listener) | |
3578 | { | |
117712c3 AK |
3579 | CPUState *env; |
3580 | ||
3581 | /* since each CPU stores ram addresses in its TLB cache, we must | |
3582 | reset the modified entries */ | |
3583 | /* XXX: slow ! */ | |
3584 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
3585 | tlb_flush(env, 1); | |
3586 | } | |
50c1e149 AK |
3587 | } |
3588 | ||
93632747 AK |
3589 | static void core_region_add(MemoryListener *listener, |
3590 | MemoryRegionSection *section) | |
3591 | { | |
4855d41a | 3592 | cpu_register_physical_memory_log(section, section->readonly); |
93632747 AK |
3593 | } |
3594 | ||
3595 | static void core_region_del(MemoryListener *listener, | |
3596 | MemoryRegionSection *section) | |
3597 | { | |
93632747 AK |
3598 | } |
3599 | ||
50c1e149 AK |
3600 | static void core_region_nop(MemoryListener *listener, |
3601 | MemoryRegionSection *section) | |
3602 | { | |
54688b1e | 3603 | cpu_register_physical_memory_log(section, section->readonly); |
50c1e149 AK |
3604 | } |
3605 | ||
93632747 AK |
3606 | static void core_log_start(MemoryListener *listener, |
3607 | MemoryRegionSection *section) | |
3608 | { | |
3609 | } | |
3610 | ||
3611 | static void core_log_stop(MemoryListener *listener, | |
3612 | MemoryRegionSection *section) | |
3613 | { | |
3614 | } | |
3615 | ||
3616 | static void core_log_sync(MemoryListener *listener, | |
3617 | MemoryRegionSection *section) | |
3618 | { | |
3619 | } | |
3620 | ||
3621 | static void core_log_global_start(MemoryListener *listener) | |
3622 | { | |
3623 | cpu_physical_memory_set_dirty_tracking(1); | |
3624 | } | |
3625 | ||
3626 | static void core_log_global_stop(MemoryListener *listener) | |
3627 | { | |
3628 | cpu_physical_memory_set_dirty_tracking(0); | |
3629 | } | |
3630 | ||
3631 | static void core_eventfd_add(MemoryListener *listener, | |
3632 | MemoryRegionSection *section, | |
3633 | bool match_data, uint64_t data, int fd) | |
3634 | { | |
3635 | } | |
3636 | ||
3637 | static void core_eventfd_del(MemoryListener *listener, | |
3638 | MemoryRegionSection *section, | |
3639 | bool match_data, uint64_t data, int fd) | |
3640 | { | |
3641 | } | |
3642 | ||
50c1e149 AK |
3643 | static void io_begin(MemoryListener *listener) |
3644 | { | |
3645 | } | |
3646 | ||
3647 | static void io_commit(MemoryListener *listener) | |
3648 | { | |
3649 | } | |
3650 | ||
4855d41a AK |
3651 | static void io_region_add(MemoryListener *listener, |
3652 | MemoryRegionSection *section) | |
3653 | { | |
3654 | iorange_init(§ion->mr->iorange, &memory_region_iorange_ops, | |
3655 | section->offset_within_address_space, section->size); | |
3656 | ioport_register(§ion->mr->iorange); | |
3657 | } | |
3658 | ||
3659 | static void io_region_del(MemoryListener *listener, | |
3660 | MemoryRegionSection *section) | |
3661 | { | |
3662 | isa_unassign_ioport(section->offset_within_address_space, section->size); | |
3663 | } | |
3664 | ||
50c1e149 AK |
3665 | static void io_region_nop(MemoryListener *listener, |
3666 | MemoryRegionSection *section) | |
3667 | { | |
3668 | } | |
3669 | ||
4855d41a AK |
3670 | static void io_log_start(MemoryListener *listener, |
3671 | MemoryRegionSection *section) | |
3672 | { | |
3673 | } | |
3674 | ||
3675 | static void io_log_stop(MemoryListener *listener, | |
3676 | MemoryRegionSection *section) | |
3677 | { | |
3678 | } | |
3679 | ||
3680 | static void io_log_sync(MemoryListener *listener, | |
3681 | MemoryRegionSection *section) | |
3682 | { | |
3683 | } | |
3684 | ||
3685 | static void io_log_global_start(MemoryListener *listener) | |
3686 | { | |
3687 | } | |
3688 | ||
3689 | static void io_log_global_stop(MemoryListener *listener) | |
3690 | { | |
3691 | } | |
3692 | ||
3693 | static void io_eventfd_add(MemoryListener *listener, | |
3694 | MemoryRegionSection *section, | |
3695 | bool match_data, uint64_t data, int fd) | |
3696 | { | |
3697 | } | |
3698 | ||
3699 | static void io_eventfd_del(MemoryListener *listener, | |
3700 | MemoryRegionSection *section, | |
3701 | bool match_data, uint64_t data, int fd) | |
3702 | { | |
3703 | } | |
3704 | ||
93632747 | 3705 | static MemoryListener core_memory_listener = { |
50c1e149 AK |
3706 | .begin = core_begin, |
3707 | .commit = core_commit, | |
93632747 AK |
3708 | .region_add = core_region_add, |
3709 | .region_del = core_region_del, | |
50c1e149 | 3710 | .region_nop = core_region_nop, |
93632747 AK |
3711 | .log_start = core_log_start, |
3712 | .log_stop = core_log_stop, | |
3713 | .log_sync = core_log_sync, | |
3714 | .log_global_start = core_log_global_start, | |
3715 | .log_global_stop = core_log_global_stop, | |
3716 | .eventfd_add = core_eventfd_add, | |
3717 | .eventfd_del = core_eventfd_del, | |
3718 | .priority = 0, | |
3719 | }; | |
3720 | ||
4855d41a | 3721 | static MemoryListener io_memory_listener = { |
50c1e149 AK |
3722 | .begin = io_begin, |
3723 | .commit = io_commit, | |
4855d41a AK |
3724 | .region_add = io_region_add, |
3725 | .region_del = io_region_del, | |
50c1e149 | 3726 | .region_nop = io_region_nop, |
4855d41a AK |
3727 | .log_start = io_log_start, |
3728 | .log_stop = io_log_stop, | |
3729 | .log_sync = io_log_sync, | |
3730 | .log_global_start = io_log_global_start, | |
3731 | .log_global_stop = io_log_global_stop, | |
3732 | .eventfd_add = io_eventfd_add, | |
3733 | .eventfd_del = io_eventfd_del, | |
3734 | .priority = 0, | |
3735 | }; | |
3736 | ||
62152b8a AK |
3737 | static void memory_map_init(void) |
3738 | { | |
7267c094 | 3739 | system_memory = g_malloc(sizeof(*system_memory)); |
8417cebf | 3740 | memory_region_init(system_memory, "system", INT64_MAX); |
62152b8a | 3741 | set_system_memory_map(system_memory); |
309cb471 | 3742 | |
7267c094 | 3743 | system_io = g_malloc(sizeof(*system_io)); |
309cb471 AK |
3744 | memory_region_init(system_io, "io", 65536); |
3745 | set_system_io_map(system_io); | |
93632747 | 3746 | |
4855d41a AK |
3747 | memory_listener_register(&core_memory_listener, system_memory); |
3748 | memory_listener_register(&io_memory_listener, system_io); | |
62152b8a AK |
3749 | } |
3750 | ||
3751 | MemoryRegion *get_system_memory(void) | |
3752 | { | |
3753 | return system_memory; | |
3754 | } | |
3755 | ||
309cb471 AK |
3756 | MemoryRegion *get_system_io(void) |
3757 | { | |
3758 | return system_io; | |
3759 | } | |
3760 | ||
e2eef170 PB |
3761 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3762 | ||
13eb76e0 FB |
3763 | /* physical memory access (slow version, mainly for debug) */ |
3764 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3765 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3766 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3767 | { |
3768 | int l, flags; | |
3769 | target_ulong page; | |
53a5960a | 3770 | void * p; |
13eb76e0 FB |
3771 | |
3772 | while (len > 0) { | |
3773 | page = addr & TARGET_PAGE_MASK; | |
3774 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3775 | if (l > len) | |
3776 | l = len; | |
3777 | flags = page_get_flags(page); | |
3778 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3779 | return -1; |
13eb76e0 FB |
3780 | if (is_write) { |
3781 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3782 | return -1; |
579a97f7 | 3783 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3784 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3785 | return -1; |
72fb7daa AJ |
3786 | memcpy(p, buf, l); |
3787 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3788 | } else { |
3789 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3790 | return -1; |
579a97f7 | 3791 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3792 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3793 | return -1; |
72fb7daa | 3794 | memcpy(buf, p, l); |
5b257578 | 3795 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3796 | } |
3797 | len -= l; | |
3798 | buf += l; | |
3799 | addr += l; | |
3800 | } | |
a68fe89c | 3801 | return 0; |
13eb76e0 | 3802 | } |
8df1cd07 | 3803 | |
13eb76e0 | 3804 | #else |
c227f099 | 3805 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3806 | int len, int is_write) |
3807 | { | |
3808 | int l, io_index; | |
3809 | uint8_t *ptr; | |
3810 | uint32_t val; | |
c227f099 | 3811 | target_phys_addr_t page; |
06ef3525 | 3812 | MemoryRegionSection section; |
3b46e624 | 3813 | |
13eb76e0 FB |
3814 | while (len > 0) { |
3815 | page = addr & TARGET_PAGE_MASK; | |
3816 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3817 | if (l > len) | |
3818 | l = len; | |
06ef3525 | 3819 | section = phys_page_find(page >> TARGET_PAGE_BITS); |
3b46e624 | 3820 | |
13eb76e0 | 3821 | if (is_write) { |
06ef3525 | 3822 | if (!memory_region_is_ram(section.mr)) { |
f1f6e3b8 | 3823 | target_phys_addr_t addr1; |
06ef3525 AK |
3824 | io_index = memory_region_get_ram_addr(section.mr) |
3825 | & (IO_MEM_NB_ENTRIES - 1); | |
3826 | addr1 = (addr & ~TARGET_PAGE_MASK) | |
3827 | + section.offset_within_region; | |
6a00d601 FB |
3828 | /* XXX: could force cpu_single_env to NULL to avoid |
3829 | potential bugs */ | |
6c2934db | 3830 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3831 | /* 32 bit write access */ |
c27004ec | 3832 | val = ldl_p(buf); |
acbbec5d | 3833 | io_mem_write(io_index, addr1, val, 4); |
13eb76e0 | 3834 | l = 4; |
6c2934db | 3835 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3836 | /* 16 bit write access */ |
c27004ec | 3837 | val = lduw_p(buf); |
acbbec5d | 3838 | io_mem_write(io_index, addr1, val, 2); |
13eb76e0 FB |
3839 | l = 2; |
3840 | } else { | |
1c213d19 | 3841 | /* 8 bit write access */ |
c27004ec | 3842 | val = ldub_p(buf); |
acbbec5d | 3843 | io_mem_write(io_index, addr1, val, 1); |
13eb76e0 FB |
3844 | l = 1; |
3845 | } | |
06ef3525 | 3846 | } else if (!section.readonly) { |
8ca5692d | 3847 | ram_addr_t addr1; |
06ef3525 AK |
3848 | addr1 = (memory_region_get_ram_addr(section.mr) |
3849 | + section.offset_within_region) | |
3850 | | (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3851 | /* RAM case */ |
5579c7f3 | 3852 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3853 | memcpy(ptr, buf, l); |
3a7d929e FB |
3854 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3855 | /* invalidate code */ | |
3856 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3857 | /* set dirty bit */ | |
f7c11b53 YT |
3858 | cpu_physical_memory_set_dirty_flags( |
3859 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3860 | } |
050a0ddf | 3861 | qemu_put_ram_ptr(ptr); |
13eb76e0 FB |
3862 | } |
3863 | } else { | |
06ef3525 | 3864 | if (!is_ram_rom_romd(§ion)) { |
f1f6e3b8 | 3865 | target_phys_addr_t addr1; |
13eb76e0 | 3866 | /* I/O case */ |
06ef3525 AK |
3867 | io_index = memory_region_get_ram_addr(section.mr) |
3868 | & (IO_MEM_NB_ENTRIES - 1); | |
3869 | addr1 = (addr & ~TARGET_PAGE_MASK) | |
3870 | + section.offset_within_region; | |
6c2934db | 3871 | if (l >= 4 && ((addr1 & 3) == 0)) { |
13eb76e0 | 3872 | /* 32 bit read access */ |
acbbec5d | 3873 | val = io_mem_read(io_index, addr1, 4); |
c27004ec | 3874 | stl_p(buf, val); |
13eb76e0 | 3875 | l = 4; |
6c2934db | 3876 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3877 | /* 16 bit read access */ |
acbbec5d | 3878 | val = io_mem_read(io_index, addr1, 2); |
c27004ec | 3879 | stw_p(buf, val); |
13eb76e0 FB |
3880 | l = 2; |
3881 | } else { | |
1c213d19 | 3882 | /* 8 bit read access */ |
acbbec5d | 3883 | val = io_mem_read(io_index, addr1, 1); |
c27004ec | 3884 | stb_p(buf, val); |
13eb76e0 FB |
3885 | l = 1; |
3886 | } | |
3887 | } else { | |
3888 | /* RAM case */ | |
06ef3525 AK |
3889 | ptr = qemu_get_ram_ptr(section.mr->ram_addr |
3890 | + section.offset_within_region); | |
050a0ddf AP |
3891 | memcpy(buf, ptr + (addr & ~TARGET_PAGE_MASK), l); |
3892 | qemu_put_ram_ptr(ptr); | |
13eb76e0 FB |
3893 | } |
3894 | } | |
3895 | len -= l; | |
3896 | buf += l; | |
3897 | addr += l; | |
3898 | } | |
3899 | } | |
8df1cd07 | 3900 | |
d0ecd2aa | 3901 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3902 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3903 | const uint8_t *buf, int len) |
3904 | { | |
3905 | int l; | |
3906 | uint8_t *ptr; | |
c227f099 | 3907 | target_phys_addr_t page; |
06ef3525 | 3908 | MemoryRegionSection section; |
3b46e624 | 3909 | |
d0ecd2aa FB |
3910 | while (len > 0) { |
3911 | page = addr & TARGET_PAGE_MASK; | |
3912 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3913 | if (l > len) | |
3914 | l = len; | |
06ef3525 | 3915 | section = phys_page_find(page >> TARGET_PAGE_BITS); |
3b46e624 | 3916 | |
06ef3525 | 3917 | if (!is_ram_rom_romd(§ion)) { |
d0ecd2aa FB |
3918 | /* do nothing */ |
3919 | } else { | |
3920 | unsigned long addr1; | |
06ef3525 AK |
3921 | addr1 = (memory_region_get_ram_addr(section.mr) |
3922 | + section.offset_within_region) | |
3923 | + (addr & ~TARGET_PAGE_MASK); | |
d0ecd2aa | 3924 | /* ROM/RAM case */ |
5579c7f3 | 3925 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa | 3926 | memcpy(ptr, buf, l); |
050a0ddf | 3927 | qemu_put_ram_ptr(ptr); |
d0ecd2aa FB |
3928 | } |
3929 | len -= l; | |
3930 | buf += l; | |
3931 | addr += l; | |
3932 | } | |
3933 | } | |
3934 | ||
6d16c2f8 AL |
3935 | typedef struct { |
3936 | void *buffer; | |
c227f099 AL |
3937 | target_phys_addr_t addr; |
3938 | target_phys_addr_t len; | |
6d16c2f8 AL |
3939 | } BounceBuffer; |
3940 | ||
3941 | static BounceBuffer bounce; | |
3942 | ||
ba223c29 AL |
3943 | typedef struct MapClient { |
3944 | void *opaque; | |
3945 | void (*callback)(void *opaque); | |
72cf2d4f | 3946 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3947 | } MapClient; |
3948 | ||
72cf2d4f BS |
3949 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3950 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3951 | |
3952 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3953 | { | |
7267c094 | 3954 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 AL |
3955 | |
3956 | client->opaque = opaque; | |
3957 | client->callback = callback; | |
72cf2d4f | 3958 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3959 | return client; |
3960 | } | |
3961 | ||
3962 | void cpu_unregister_map_client(void *_client) | |
3963 | { | |
3964 | MapClient *client = (MapClient *)_client; | |
3965 | ||
72cf2d4f | 3966 | QLIST_REMOVE(client, link); |
7267c094 | 3967 | g_free(client); |
ba223c29 AL |
3968 | } |
3969 | ||
3970 | static void cpu_notify_map_clients(void) | |
3971 | { | |
3972 | MapClient *client; | |
3973 | ||
72cf2d4f BS |
3974 | while (!QLIST_EMPTY(&map_client_list)) { |
3975 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3976 | client->callback(client->opaque); |
34d5e948 | 3977 | cpu_unregister_map_client(client); |
ba223c29 AL |
3978 | } |
3979 | } | |
3980 | ||
6d16c2f8 AL |
3981 | /* Map a physical memory region into a host virtual address. |
3982 | * May map a subset of the requested range, given by and returned in *plen. | |
3983 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3984 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3985 | * Use cpu_register_map_client() to know when retrying the map operation is |
3986 | * likely to succeed. | |
6d16c2f8 | 3987 | */ |
c227f099 AL |
3988 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3989 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3990 | int is_write) |
3991 | { | |
c227f099 | 3992 | target_phys_addr_t len = *plen; |
38bee5dc | 3993 | target_phys_addr_t todo = 0; |
6d16c2f8 | 3994 | int l; |
c227f099 | 3995 | target_phys_addr_t page; |
06ef3525 | 3996 | MemoryRegionSection section; |
f15fbc4b | 3997 | ram_addr_t raddr = RAM_ADDR_MAX; |
8ab934f9 SS |
3998 | ram_addr_t rlen; |
3999 | void *ret; | |
6d16c2f8 AL |
4000 | |
4001 | while (len > 0) { | |
4002 | page = addr & TARGET_PAGE_MASK; | |
4003 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4004 | if (l > len) | |
4005 | l = len; | |
06ef3525 | 4006 | section = phys_page_find(page >> TARGET_PAGE_BITS); |
6d16c2f8 | 4007 | |
06ef3525 | 4008 | if (!(memory_region_is_ram(section.mr) && !section.readonly)) { |
38bee5dc | 4009 | if (todo || bounce.buffer) { |
6d16c2f8 AL |
4010 | break; |
4011 | } | |
4012 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
4013 | bounce.addr = addr; | |
4014 | bounce.len = l; | |
4015 | if (!is_write) { | |
54f7b4a3 | 4016 | cpu_physical_memory_read(addr, bounce.buffer, l); |
6d16c2f8 | 4017 | } |
38bee5dc SS |
4018 | |
4019 | *plen = l; | |
4020 | return bounce.buffer; | |
6d16c2f8 | 4021 | } |
8ab934f9 | 4022 | if (!todo) { |
06ef3525 AK |
4023 | raddr = memory_region_get_ram_addr(section.mr) |
4024 | + section.offset_within_region | |
4025 | + (addr & ~TARGET_PAGE_MASK); | |
8ab934f9 | 4026 | } |
6d16c2f8 AL |
4027 | |
4028 | len -= l; | |
4029 | addr += l; | |
38bee5dc | 4030 | todo += l; |
6d16c2f8 | 4031 | } |
8ab934f9 SS |
4032 | rlen = todo; |
4033 | ret = qemu_ram_ptr_length(raddr, &rlen); | |
4034 | *plen = rlen; | |
4035 | return ret; | |
6d16c2f8 AL |
4036 | } |
4037 | ||
4038 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
4039 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
4040 | * the amount of memory that was actually read or written by the caller. | |
4041 | */ | |
c227f099 AL |
4042 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
4043 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
4044 | { |
4045 | if (buffer != bounce.buffer) { | |
4046 | if (is_write) { | |
e890261f | 4047 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
6d16c2f8 AL |
4048 | while (access_len) { |
4049 | unsigned l; | |
4050 | l = TARGET_PAGE_SIZE; | |
4051 | if (l > access_len) | |
4052 | l = access_len; | |
4053 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4054 | /* invalidate code */ | |
4055 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
4056 | /* set dirty bit */ | |
f7c11b53 YT |
4057 | cpu_physical_memory_set_dirty_flags( |
4058 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
6d16c2f8 AL |
4059 | } |
4060 | addr1 += l; | |
4061 | access_len -= l; | |
4062 | } | |
4063 | } | |
868bb33f | 4064 | if (xen_enabled()) { |
e41d7c69 | 4065 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 4066 | } |
6d16c2f8 AL |
4067 | return; |
4068 | } | |
4069 | if (is_write) { | |
4070 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
4071 | } | |
f8a83245 | 4072 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 4073 | bounce.buffer = NULL; |
ba223c29 | 4074 | cpu_notify_map_clients(); |
6d16c2f8 | 4075 | } |
d0ecd2aa | 4076 | |
8df1cd07 | 4077 | /* warning: addr must be aligned */ |
1e78bcc1 AG |
4078 | static inline uint32_t ldl_phys_internal(target_phys_addr_t addr, |
4079 | enum device_endian endian) | |
8df1cd07 FB |
4080 | { |
4081 | int io_index; | |
4082 | uint8_t *ptr; | |
4083 | uint32_t val; | |
06ef3525 | 4084 | MemoryRegionSection section; |
8df1cd07 | 4085 | |
06ef3525 | 4086 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
3b46e624 | 4087 | |
06ef3525 | 4088 | if (!is_ram_rom_romd(§ion)) { |
8df1cd07 | 4089 | /* I/O case */ |
06ef3525 AK |
4090 | io_index = memory_region_get_ram_addr(section.mr) |
4091 | & (IO_MEM_NB_ENTRIES - 1); | |
4092 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
acbbec5d | 4093 | val = io_mem_read(io_index, addr, 4); |
1e78bcc1 AG |
4094 | #if defined(TARGET_WORDS_BIGENDIAN) |
4095 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
4096 | val = bswap32(val); | |
4097 | } | |
4098 | #else | |
4099 | if (endian == DEVICE_BIG_ENDIAN) { | |
4100 | val = bswap32(val); | |
4101 | } | |
4102 | #endif | |
8df1cd07 FB |
4103 | } else { |
4104 | /* RAM case */ | |
06ef3525 AK |
4105 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section.mr) |
4106 | & TARGET_PAGE_MASK) | |
4107 | + section.offset_within_region) + | |
8df1cd07 | 4108 | (addr & ~TARGET_PAGE_MASK); |
1e78bcc1 AG |
4109 | switch (endian) { |
4110 | case DEVICE_LITTLE_ENDIAN: | |
4111 | val = ldl_le_p(ptr); | |
4112 | break; | |
4113 | case DEVICE_BIG_ENDIAN: | |
4114 | val = ldl_be_p(ptr); | |
4115 | break; | |
4116 | default: | |
4117 | val = ldl_p(ptr); | |
4118 | break; | |
4119 | } | |
8df1cd07 FB |
4120 | } |
4121 | return val; | |
4122 | } | |
4123 | ||
1e78bcc1 AG |
4124 | uint32_t ldl_phys(target_phys_addr_t addr) |
4125 | { | |
4126 | return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
4127 | } | |
4128 | ||
4129 | uint32_t ldl_le_phys(target_phys_addr_t addr) | |
4130 | { | |
4131 | return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
4132 | } | |
4133 | ||
4134 | uint32_t ldl_be_phys(target_phys_addr_t addr) | |
4135 | { | |
4136 | return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
4137 | } | |
4138 | ||
84b7b8e7 | 4139 | /* warning: addr must be aligned */ |
1e78bcc1 AG |
4140 | static inline uint64_t ldq_phys_internal(target_phys_addr_t addr, |
4141 | enum device_endian endian) | |
84b7b8e7 FB |
4142 | { |
4143 | int io_index; | |
4144 | uint8_t *ptr; | |
4145 | uint64_t val; | |
06ef3525 | 4146 | MemoryRegionSection section; |
84b7b8e7 | 4147 | |
06ef3525 | 4148 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
3b46e624 | 4149 | |
06ef3525 | 4150 | if (!is_ram_rom_romd(§ion)) { |
84b7b8e7 | 4151 | /* I/O case */ |
06ef3525 AK |
4152 | io_index = memory_region_get_ram_addr(section.mr) |
4153 | & (IO_MEM_NB_ENTRIES - 1); | |
4154 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
1e78bcc1 AG |
4155 | |
4156 | /* XXX This is broken when device endian != cpu endian. | |
4157 | Fix and add "endian" variable check */ | |
84b7b8e7 | 4158 | #ifdef TARGET_WORDS_BIGENDIAN |
acbbec5d AK |
4159 | val = io_mem_read(io_index, addr, 4) << 32; |
4160 | val |= io_mem_read(io_index, addr + 4, 4); | |
84b7b8e7 | 4161 | #else |
acbbec5d AK |
4162 | val = io_mem_read(io_index, addr, 4); |
4163 | val |= io_mem_read(io_index, addr + 4, 4) << 32; | |
84b7b8e7 FB |
4164 | #endif |
4165 | } else { | |
4166 | /* RAM case */ | |
06ef3525 AK |
4167 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section.mr) |
4168 | & TARGET_PAGE_MASK) | |
4169 | + section.offset_within_region) | |
4170 | + (addr & ~TARGET_PAGE_MASK); | |
1e78bcc1 AG |
4171 | switch (endian) { |
4172 | case DEVICE_LITTLE_ENDIAN: | |
4173 | val = ldq_le_p(ptr); | |
4174 | break; | |
4175 | case DEVICE_BIG_ENDIAN: | |
4176 | val = ldq_be_p(ptr); | |
4177 | break; | |
4178 | default: | |
4179 | val = ldq_p(ptr); | |
4180 | break; | |
4181 | } | |
84b7b8e7 FB |
4182 | } |
4183 | return val; | |
4184 | } | |
4185 | ||
1e78bcc1 AG |
4186 | uint64_t ldq_phys(target_phys_addr_t addr) |
4187 | { | |
4188 | return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
4189 | } | |
4190 | ||
4191 | uint64_t ldq_le_phys(target_phys_addr_t addr) | |
4192 | { | |
4193 | return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
4194 | } | |
4195 | ||
4196 | uint64_t ldq_be_phys(target_phys_addr_t addr) | |
4197 | { | |
4198 | return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
4199 | } | |
4200 | ||
aab33094 | 4201 | /* XXX: optimize */ |
c227f099 | 4202 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
4203 | { |
4204 | uint8_t val; | |
4205 | cpu_physical_memory_read(addr, &val, 1); | |
4206 | return val; | |
4207 | } | |
4208 | ||
733f0b02 | 4209 | /* warning: addr must be aligned */ |
1e78bcc1 AG |
4210 | static inline uint32_t lduw_phys_internal(target_phys_addr_t addr, |
4211 | enum device_endian endian) | |
aab33094 | 4212 | { |
733f0b02 MT |
4213 | int io_index; |
4214 | uint8_t *ptr; | |
4215 | uint64_t val; | |
06ef3525 | 4216 | MemoryRegionSection section; |
733f0b02 | 4217 | |
06ef3525 | 4218 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
733f0b02 | 4219 | |
06ef3525 | 4220 | if (!is_ram_rom_romd(§ion)) { |
733f0b02 | 4221 | /* I/O case */ |
06ef3525 AK |
4222 | io_index = memory_region_get_ram_addr(section.mr) |
4223 | & (IO_MEM_NB_ENTRIES - 1); | |
4224 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
acbbec5d | 4225 | val = io_mem_read(io_index, addr, 2); |
1e78bcc1 AG |
4226 | #if defined(TARGET_WORDS_BIGENDIAN) |
4227 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
4228 | val = bswap16(val); | |
4229 | } | |
4230 | #else | |
4231 | if (endian == DEVICE_BIG_ENDIAN) { | |
4232 | val = bswap16(val); | |
4233 | } | |
4234 | #endif | |
733f0b02 MT |
4235 | } else { |
4236 | /* RAM case */ | |
06ef3525 AK |
4237 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section.mr) |
4238 | & TARGET_PAGE_MASK) | |
4239 | + section.offset_within_region) | |
4240 | + (addr & ~TARGET_PAGE_MASK); | |
1e78bcc1 AG |
4241 | switch (endian) { |
4242 | case DEVICE_LITTLE_ENDIAN: | |
4243 | val = lduw_le_p(ptr); | |
4244 | break; | |
4245 | case DEVICE_BIG_ENDIAN: | |
4246 | val = lduw_be_p(ptr); | |
4247 | break; | |
4248 | default: | |
4249 | val = lduw_p(ptr); | |
4250 | break; | |
4251 | } | |
733f0b02 MT |
4252 | } |
4253 | return val; | |
aab33094 FB |
4254 | } |
4255 | ||
1e78bcc1 AG |
4256 | uint32_t lduw_phys(target_phys_addr_t addr) |
4257 | { | |
4258 | return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN); | |
4259 | } | |
4260 | ||
4261 | uint32_t lduw_le_phys(target_phys_addr_t addr) | |
4262 | { | |
4263 | return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN); | |
4264 | } | |
4265 | ||
4266 | uint32_t lduw_be_phys(target_phys_addr_t addr) | |
4267 | { | |
4268 | return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN); | |
4269 | } | |
4270 | ||
8df1cd07 FB |
4271 | /* warning: addr must be aligned. The ram page is not masked as dirty |
4272 | and the code inside is not invalidated. It is useful if the dirty | |
4273 | bits are used to track modified PTEs */ | |
c227f099 | 4274 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
4275 | { |
4276 | int io_index; | |
4277 | uint8_t *ptr; | |
06ef3525 | 4278 | MemoryRegionSection section; |
8df1cd07 | 4279 | |
06ef3525 | 4280 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
3b46e624 | 4281 | |
06ef3525 AK |
4282 | if (!memory_region_is_ram(section.mr) || section.readonly) { |
4283 | if (memory_region_is_ram(section.mr)) { | |
4284 | io_index = io_mem_rom.ram_addr; | |
4285 | } else { | |
4286 | io_index = memory_region_get_ram_addr(section.mr); | |
4287 | } | |
4288 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
acbbec5d | 4289 | io_mem_write(io_index, addr, val, 4); |
8df1cd07 | 4290 | } else { |
06ef3525 AK |
4291 | unsigned long addr1 = (memory_region_get_ram_addr(section.mr) |
4292 | & TARGET_PAGE_MASK) | |
4293 | + section.offset_within_region | |
4294 | + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 4295 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 4296 | stl_p(ptr, val); |
74576198 AL |
4297 | |
4298 | if (unlikely(in_migration)) { | |
4299 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4300 | /* invalidate code */ | |
4301 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4302 | /* set dirty bit */ | |
f7c11b53 YT |
4303 | cpu_physical_memory_set_dirty_flags( |
4304 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
74576198 AL |
4305 | } |
4306 | } | |
8df1cd07 FB |
4307 | } |
4308 | } | |
4309 | ||
c227f099 | 4310 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
4311 | { |
4312 | int io_index; | |
4313 | uint8_t *ptr; | |
06ef3525 | 4314 | MemoryRegionSection section; |
bc98a7ef | 4315 | |
06ef3525 | 4316 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
3b46e624 | 4317 | |
06ef3525 AK |
4318 | if (!memory_region_is_ram(section.mr) || section.readonly) { |
4319 | if (memory_region_is_ram(section.mr)) { | |
4320 | io_index = io_mem_rom.ram_addr; | |
4321 | } else { | |
4322 | io_index = memory_region_get_ram_addr(section.mr) | |
4323 | & (IO_MEM_NB_ENTRIES - 1); | |
4324 | } | |
4325 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
bc98a7ef | 4326 | #ifdef TARGET_WORDS_BIGENDIAN |
acbbec5d AK |
4327 | io_mem_write(io_index, addr, val >> 32, 4); |
4328 | io_mem_write(io_index, addr + 4, (uint32_t)val, 4); | |
bc98a7ef | 4329 | #else |
acbbec5d AK |
4330 | io_mem_write(io_index, addr, (uint32_t)val, 4); |
4331 | io_mem_write(io_index, addr + 4, val >> 32, 4); | |
bc98a7ef JM |
4332 | #endif |
4333 | } else { | |
06ef3525 AK |
4334 | ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section.mr) |
4335 | & TARGET_PAGE_MASK) | |
4336 | + section.offset_within_region) | |
4337 | + (addr & ~TARGET_PAGE_MASK); | |
bc98a7ef JM |
4338 | stq_p(ptr, val); |
4339 | } | |
4340 | } | |
4341 | ||
8df1cd07 | 4342 | /* warning: addr must be aligned */ |
1e78bcc1 AG |
4343 | static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val, |
4344 | enum device_endian endian) | |
8df1cd07 FB |
4345 | { |
4346 | int io_index; | |
4347 | uint8_t *ptr; | |
06ef3525 | 4348 | MemoryRegionSection section; |
8df1cd07 | 4349 | |
06ef3525 | 4350 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
3b46e624 | 4351 | |
06ef3525 AK |
4352 | if (!memory_region_is_ram(section.mr) || section.readonly) { |
4353 | if (memory_region_is_ram(section.mr)) { | |
4354 | io_index = io_mem_rom.ram_addr; | |
4355 | } else { | |
4356 | io_index = memory_region_get_ram_addr(section.mr) | |
4357 | & (IO_MEM_NB_ENTRIES - 1); | |
4358 | } | |
4359 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
1e78bcc1 AG |
4360 | #if defined(TARGET_WORDS_BIGENDIAN) |
4361 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
4362 | val = bswap32(val); | |
4363 | } | |
4364 | #else | |
4365 | if (endian == DEVICE_BIG_ENDIAN) { | |
4366 | val = bswap32(val); | |
4367 | } | |
4368 | #endif | |
acbbec5d | 4369 | io_mem_write(io_index, addr, val, 4); |
8df1cd07 FB |
4370 | } else { |
4371 | unsigned long addr1; | |
06ef3525 AK |
4372 | addr1 = (memory_region_get_ram_addr(section.mr) & TARGET_PAGE_MASK) |
4373 | + section.offset_within_region | |
4374 | + (addr & ~TARGET_PAGE_MASK); | |
8df1cd07 | 4375 | /* RAM case */ |
5579c7f3 | 4376 | ptr = qemu_get_ram_ptr(addr1); |
1e78bcc1 AG |
4377 | switch (endian) { |
4378 | case DEVICE_LITTLE_ENDIAN: | |
4379 | stl_le_p(ptr, val); | |
4380 | break; | |
4381 | case DEVICE_BIG_ENDIAN: | |
4382 | stl_be_p(ptr, val); | |
4383 | break; | |
4384 | default: | |
4385 | stl_p(ptr, val); | |
4386 | break; | |
4387 | } | |
3a7d929e FB |
4388 | if (!cpu_physical_memory_is_dirty(addr1)) { |
4389 | /* invalidate code */ | |
4390 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4391 | /* set dirty bit */ | |
f7c11b53 YT |
4392 | cpu_physical_memory_set_dirty_flags(addr1, |
4393 | (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 4394 | } |
8df1cd07 FB |
4395 | } |
4396 | } | |
4397 | ||
1e78bcc1 AG |
4398 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
4399 | { | |
4400 | stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); | |
4401 | } | |
4402 | ||
4403 | void stl_le_phys(target_phys_addr_t addr, uint32_t val) | |
4404 | { | |
4405 | stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); | |
4406 | } | |
4407 | ||
4408 | void stl_be_phys(target_phys_addr_t addr, uint32_t val) | |
4409 | { | |
4410 | stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN); | |
4411 | } | |
4412 | ||
aab33094 | 4413 | /* XXX: optimize */ |
c227f099 | 4414 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
4415 | { |
4416 | uint8_t v = val; | |
4417 | cpu_physical_memory_write(addr, &v, 1); | |
4418 | } | |
4419 | ||
733f0b02 | 4420 | /* warning: addr must be aligned */ |
1e78bcc1 AG |
4421 | static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val, |
4422 | enum device_endian endian) | |
aab33094 | 4423 | { |
733f0b02 MT |
4424 | int io_index; |
4425 | uint8_t *ptr; | |
06ef3525 | 4426 | MemoryRegionSection section; |
733f0b02 | 4427 | |
06ef3525 | 4428 | section = phys_page_find(addr >> TARGET_PAGE_BITS); |
733f0b02 | 4429 | |
06ef3525 AK |
4430 | if (!memory_region_is_ram(section.mr) || section.readonly) { |
4431 | if (memory_region_is_ram(section.mr)) { | |
4432 | io_index = io_mem_rom.ram_addr; | |
4433 | } else { | |
4434 | io_index = memory_region_get_ram_addr(section.mr) | |
4435 | & (IO_MEM_NB_ENTRIES - 1); | |
4436 | } | |
4437 | addr = (addr & ~TARGET_PAGE_MASK) + section.offset_within_region; | |
1e78bcc1 AG |
4438 | #if defined(TARGET_WORDS_BIGENDIAN) |
4439 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
4440 | val = bswap16(val); | |
4441 | } | |
4442 | #else | |
4443 | if (endian == DEVICE_BIG_ENDIAN) { | |
4444 | val = bswap16(val); | |
4445 | } | |
4446 | #endif | |
acbbec5d | 4447 | io_mem_write(io_index, addr, val, 2); |
733f0b02 MT |
4448 | } else { |
4449 | unsigned long addr1; | |
06ef3525 AK |
4450 | addr1 = (memory_region_get_ram_addr(section.mr) & TARGET_PAGE_MASK) |
4451 | + section.offset_within_region + (addr & ~TARGET_PAGE_MASK); | |
733f0b02 MT |
4452 | /* RAM case */ |
4453 | ptr = qemu_get_ram_ptr(addr1); | |
1e78bcc1 AG |
4454 | switch (endian) { |
4455 | case DEVICE_LITTLE_ENDIAN: | |
4456 | stw_le_p(ptr, val); | |
4457 | break; | |
4458 | case DEVICE_BIG_ENDIAN: | |
4459 | stw_be_p(ptr, val); | |
4460 | break; | |
4461 | default: | |
4462 | stw_p(ptr, val); | |
4463 | break; | |
4464 | } | |
733f0b02 MT |
4465 | if (!cpu_physical_memory_is_dirty(addr1)) { |
4466 | /* invalidate code */ | |
4467 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); | |
4468 | /* set dirty bit */ | |
4469 | cpu_physical_memory_set_dirty_flags(addr1, | |
4470 | (0xff & ~CODE_DIRTY_FLAG)); | |
4471 | } | |
4472 | } | |
aab33094 FB |
4473 | } |
4474 | ||
1e78bcc1 AG |
4475 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
4476 | { | |
4477 | stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); | |
4478 | } | |
4479 | ||
4480 | void stw_le_phys(target_phys_addr_t addr, uint32_t val) | |
4481 | { | |
4482 | stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); | |
4483 | } | |
4484 | ||
4485 | void stw_be_phys(target_phys_addr_t addr, uint32_t val) | |
4486 | { | |
4487 | stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN); | |
4488 | } | |
4489 | ||
aab33094 | 4490 | /* XXX: optimize */ |
c227f099 | 4491 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
4492 | { |
4493 | val = tswap64(val); | |
71d2b725 | 4494 | cpu_physical_memory_write(addr, &val, 8); |
aab33094 FB |
4495 | } |
4496 | ||
1e78bcc1 AG |
4497 | void stq_le_phys(target_phys_addr_t addr, uint64_t val) |
4498 | { | |
4499 | val = cpu_to_le64(val); | |
4500 | cpu_physical_memory_write(addr, &val, 8); | |
4501 | } | |
4502 | ||
4503 | void stq_be_phys(target_phys_addr_t addr, uint64_t val) | |
4504 | { | |
4505 | val = cpu_to_be64(val); | |
4506 | cpu_physical_memory_write(addr, &val, 8); | |
4507 | } | |
4508 | ||
5e2972fd | 4509 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 4510 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 4511 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
4512 | { |
4513 | int l; | |
c227f099 | 4514 | target_phys_addr_t phys_addr; |
9b3c35e0 | 4515 | target_ulong page; |
13eb76e0 FB |
4516 | |
4517 | while (len > 0) { | |
4518 | page = addr & TARGET_PAGE_MASK; | |
4519 | phys_addr = cpu_get_phys_page_debug(env, page); | |
4520 | /* if no physical page mapped, return an error */ | |
4521 | if (phys_addr == -1) | |
4522 | return -1; | |
4523 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4524 | if (l > len) | |
4525 | l = len; | |
5e2972fd | 4526 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
4527 | if (is_write) |
4528 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
4529 | else | |
5e2972fd | 4530 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
4531 | len -= l; |
4532 | buf += l; | |
4533 | addr += l; | |
4534 | } | |
4535 | return 0; | |
4536 | } | |
a68fe89c | 4537 | #endif |
13eb76e0 | 4538 | |
2e70f6ef PB |
4539 | /* in deterministic execution mode, instructions doing device I/Os |
4540 | must be at the end of the TB */ | |
4541 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
4542 | { | |
4543 | TranslationBlock *tb; | |
4544 | uint32_t n, cflags; | |
4545 | target_ulong pc, cs_base; | |
4546 | uint64_t flags; | |
4547 | ||
4548 | tb = tb_find_pc((unsigned long)retaddr); | |
4549 | if (!tb) { | |
4550 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
4551 | retaddr); | |
4552 | } | |
4553 | n = env->icount_decr.u16.low + tb->icount; | |
618ba8e6 | 4554 | cpu_restore_state(tb, env, (unsigned long)retaddr); |
2e70f6ef | 4555 | /* Calculate how many instructions had been executed before the fault |
bf20dc07 | 4556 | occurred. */ |
2e70f6ef PB |
4557 | n = n - env->icount_decr.u16.low; |
4558 | /* Generate a new TB ending on the I/O insn. */ | |
4559 | n++; | |
4560 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
4561 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 4562 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
4563 | branch. */ |
4564 | #if defined(TARGET_MIPS) | |
4565 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
4566 | env->active_tc.PC -= 4; | |
4567 | env->icount_decr.u16.low++; | |
4568 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
4569 | } | |
4570 | #elif defined(TARGET_SH4) | |
4571 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
4572 | && n > 1) { | |
4573 | env->pc -= 2; | |
4574 | env->icount_decr.u16.low++; | |
4575 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
4576 | } | |
4577 | #endif | |
4578 | /* This should never happen. */ | |
4579 | if (n > CF_COUNT_MASK) | |
4580 | cpu_abort(env, "TB too big during recompile"); | |
4581 | ||
4582 | cflags = n | CF_LAST_IO; | |
4583 | pc = tb->pc; | |
4584 | cs_base = tb->cs_base; | |
4585 | flags = tb->flags; | |
4586 | tb_phys_invalidate(tb, -1); | |
4587 | /* FIXME: In theory this could raise an exception. In practice | |
4588 | we have already translated the block once so it's probably ok. */ | |
4589 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 4590 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
4591 | the first in the TB) then we end up generating a whole new TB and |
4592 | repeating the fault, which is horribly inefficient. | |
4593 | Better would be to execute just this insn uncached, or generate a | |
4594 | second new TB. */ | |
4595 | cpu_resume_from_signal(env, NULL); | |
4596 | } | |
4597 | ||
b3755a91 PB |
4598 | #if !defined(CONFIG_USER_ONLY) |
4599 | ||
055403b2 | 4600 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
e3db7226 FB |
4601 | { |
4602 | int i, target_code_size, max_target_code_size; | |
4603 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
4604 | TranslationBlock *tb; | |
3b46e624 | 4605 | |
e3db7226 FB |
4606 | target_code_size = 0; |
4607 | max_target_code_size = 0; | |
4608 | cross_page = 0; | |
4609 | direct_jmp_count = 0; | |
4610 | direct_jmp2_count = 0; | |
4611 | for(i = 0; i < nb_tbs; i++) { | |
4612 | tb = &tbs[i]; | |
4613 | target_code_size += tb->size; | |
4614 | if (tb->size > max_target_code_size) | |
4615 | max_target_code_size = tb->size; | |
4616 | if (tb->page_addr[1] != -1) | |
4617 | cross_page++; | |
4618 | if (tb->tb_next_offset[0] != 0xffff) { | |
4619 | direct_jmp_count++; | |
4620 | if (tb->tb_next_offset[1] != 0xffff) { | |
4621 | direct_jmp2_count++; | |
4622 | } | |
4623 | } | |
4624 | } | |
4625 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 4626 | cpu_fprintf(f, "Translation buffer state:\n"); |
055403b2 | 4627 | cpu_fprintf(f, "gen code size %td/%ld\n", |
26a5f13b FB |
4628 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
4629 | cpu_fprintf(f, "TB count %d/%d\n", | |
4630 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 4631 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
4632 | nb_tbs ? target_code_size / nb_tbs : 0, |
4633 | max_target_code_size); | |
055403b2 | 4634 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
4635 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
4636 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
4637 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
4638 | cross_page, | |
e3db7226 FB |
4639 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
4640 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 4641 | direct_jmp_count, |
e3db7226 FB |
4642 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
4643 | direct_jmp2_count, | |
4644 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 4645 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
4646 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
4647 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
4648 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 4649 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
4650 | } |
4651 | ||
d39e8222 AK |
4652 | /* NOTE: this function can trigger an exception */ |
4653 | /* NOTE2: the returned address is not exactly the physical address: it | |
4654 | is the offset relative to phys_ram_base */ | |
4655 | tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) | |
4656 | { | |
4657 | int mmu_idx, page_index, pd; | |
4658 | void *p; | |
4659 | ||
4660 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
4661 | mmu_idx = cpu_mmu_index(env1); | |
4662 | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != | |
4663 | (addr & TARGET_PAGE_MASK))) { | |
4664 | ldub_code(addr); | |
4665 | } | |
4666 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; | |
0e0df1e2 | 4667 | if (pd != io_mem_ram.ram_addr && pd != io_mem_rom.ram_addr |
06ef3525 | 4668 | && !io_mem_region[pd]->rom_device) { |
d39e8222 AK |
4669 | #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) |
4670 | cpu_unassigned_access(env1, addr, 0, 1, 0, 4); | |
4671 | #else | |
4672 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); | |
4673 | #endif | |
4674 | } | |
4675 | p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend); | |
4676 | return qemu_ram_addr_from_host_nofail(p); | |
4677 | } | |
4678 | ||
82afa586 BH |
4679 | /* |
4680 | * A helper function for the _utterly broken_ virtio device model to find out if | |
4681 | * it's running on a big endian machine. Don't do this at home kids! | |
4682 | */ | |
4683 | bool virtio_is_big_endian(void); | |
4684 | bool virtio_is_big_endian(void) | |
4685 | { | |
4686 | #if defined(TARGET_WORDS_BIGENDIAN) | |
4687 | return true; | |
4688 | #else | |
4689 | return false; | |
4690 | #endif | |
4691 | } | |
4692 | ||
61382a50 | 4693 | #define MMUSUFFIX _cmmu |
3917149d | 4694 | #undef GETPC |
61382a50 FB |
4695 | #define GETPC() NULL |
4696 | #define env cpu_single_env | |
b769d8fe | 4697 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
4698 | |
4699 | #define SHIFT 0 | |
4700 | #include "softmmu_template.h" | |
4701 | ||
4702 | #define SHIFT 1 | |
4703 | #include "softmmu_template.h" | |
4704 | ||
4705 | #define SHIFT 2 | |
4706 | #include "softmmu_template.h" | |
4707 | ||
4708 | #define SHIFT 3 | |
4709 | #include "softmmu_template.h" | |
4710 | ||
4711 | #undef env | |
4712 | ||
4713 | #endif |