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c5986054 | 1 | /* Save and restore call-clobbered registers which are live across a call. |
a446b4e8 | 2 | Copyright (C) 1989, 1992, 1994, 1995, 1997, 1998, 1999, 2000, |
e90b336f | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
66647d44 | 4 | Free Software Foundation, Inc. |
c5986054 | 5 | |
1322177d | 6 | This file is part of GCC. |
c5986054 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
c5986054 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
c5986054 RS |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
c5986054 RS |
21 | |
22 | #include "config.h" | |
670ee920 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
c5986054 | 26 | #include "rtl.h" |
7932a3db | 27 | #include "regs.h" |
c5986054 RS |
28 | #include "insn-config.h" |
29 | #include "flags.h" | |
c5986054 RS |
30 | #include "hard-reg-set.h" |
31 | #include "recog.h" | |
32 | #include "basic-block.h" | |
7a8cba34 | 33 | #include "df.h" |
c5986054 | 34 | #include "reload.h" |
49ad7cfa | 35 | #include "function.h" |
c5986054 | 36 | #include "expr.h" |
718f9c0f | 37 | #include "diagnostic-core.h" |
63290521 | 38 | #include "tm_p.h" |
f6c4ed08 | 39 | #include "addresses.h" |
78187f5a | 40 | #include "ggc.h" |
7ee2468b | 41 | #include "dumpfile.h" |
c5986054 | 42 | |
7609e720 BS |
43 | #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) |
44 | ||
bcbaaba1 RS |
45 | #define regno_save_mode \ |
46 | (this_target_reload->x_regno_save_mode) | |
cc14227f RS |
47 | #define cached_reg_save_code \ |
48 | (this_target_reload->x_cached_reg_save_code) | |
49 | #define cached_reg_restore_code \ | |
50 | (this_target_reload->x_cached_reg_restore_code) | |
c5986054 RS |
51 | |
52 | /* For each hard register, a place on the stack where it can be saved, | |
53 | if needed. */ | |
54 | ||
d329e058 | 55 | static rtx |
ef0e53ce | 56 | regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; |
c5986054 | 57 | |
058e97ec VM |
58 | /* The number of elements in the subsequent array. */ |
59 | static int save_slots_num; | |
60 | ||
61 | /* Allocated slots so far. */ | |
62 | static rtx save_slots[FIRST_PSEUDO_REGISTER]; | |
63 | ||
c5986054 RS |
64 | /* Set of hard regs currently residing in save area (during insn scan). */ |
65 | ||
66 | static HARD_REG_SET hard_regs_saved; | |
67 | ||
7609e720 | 68 | /* Number of registers currently in hard_regs_saved. */ |
f95361c8 | 69 | |
7609e720 | 70 | static int n_regs_saved; |
f95361c8 | 71 | |
7609e720 BS |
72 | /* Computed by mark_referenced_regs, all regs referenced in a given |
73 | insn. */ | |
74 | static HARD_REG_SET referenced_regs; | |
c5986054 | 75 | |
7609e720 | 76 | |
b5b8b0ac AO |
77 | typedef void refmarker_fn (rtx *loc, enum machine_mode mode, int hardregno, |
78 | void *mark_arg); | |
79 | ||
058e97ec VM |
80 | static int reg_save_code (int, enum machine_mode); |
81 | static int reg_restore_code (int, enum machine_mode); | |
82 | ||
83 | struct saved_hard_reg; | |
84 | static void initiate_saved_hard_regs (void); | |
e16b6fd0 | 85 | static void new_saved_hard_reg (int, int); |
058e97ec VM |
86 | static void finish_saved_hard_regs (void); |
87 | static int saved_hard_reg_compare_func (const void *, const void *); | |
88 | ||
7bc980e1 | 89 | static void mark_set_regs (rtx, const_rtx, void *); |
b5b8b0ac AO |
90 | static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); |
91 | static refmarker_fn mark_reg_as_referenced; | |
92 | static refmarker_fn replace_reg_with_saved_mem; | |
d329e058 AJ |
93 | static int insert_save (struct insn_chain *, int, int, HARD_REG_SET *, |
94 | enum machine_mode *); | |
95 | static int insert_restore (struct insn_chain *, int, int, int, | |
96 | enum machine_mode *); | |
97 | static struct insn_chain *insert_one_insn (struct insn_chain *, int, int, | |
98 | rtx); | |
7bc980e1 | 99 | static void add_stored_regs (rtx, const_rtx, void *); |
058e97ec | 100 | |
c5986054 | 101 | \f |
058e97ec | 102 | |
78187f5a JH |
103 | static GTY(()) rtx savepat; |
104 | static GTY(()) rtx restpat; | |
105 | static GTY(()) rtx test_reg; | |
106 | static GTY(()) rtx test_mem; | |
107 | static GTY(()) rtx saveinsn; | |
108 | static GTY(()) rtx restinsn; | |
109 | ||
110 | /* Return the INSN_CODE used to save register REG in mode MODE. */ | |
111 | static int | |
112 | reg_save_code (int reg, enum machine_mode mode) | |
113 | { | |
114 | bool ok; | |
115 | if (cached_reg_save_code[reg][mode]) | |
116 | return cached_reg_save_code[reg][mode]; | |
117 | if (!HARD_REGNO_MODE_OK (reg, mode)) | |
f57e2756 JR |
118 | { |
119 | /* Depending on how HARD_REGNO_MODE_OK is defined, range propagation | |
120 | might deduce here that reg >= FIRST_PSEUDO_REGISTER. So the assert | |
121 | below silences a warning. */ | |
122 | gcc_assert (reg < FIRST_PSEUDO_REGISTER); | |
123 | cached_reg_save_code[reg][mode] = -1; | |
124 | cached_reg_restore_code[reg][mode] = -1; | |
125 | return -1; | |
126 | } | |
78187f5a JH |
127 | |
128 | /* Update the register number and modes of the register | |
129 | and memory operand. */ | |
5444da31 | 130 | SET_REGNO_RAW (test_reg, reg); |
78187f5a JH |
131 | PUT_MODE (test_reg, mode); |
132 | PUT_MODE (test_mem, mode); | |
133 | ||
134 | /* Force re-recognition of the modified insns. */ | |
135 | INSN_CODE (saveinsn) = -1; | |
f81e79b5 | 136 | INSN_CODE (restinsn) = -1; |
78187f5a JH |
137 | |
138 | cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); | |
139 | cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); | |
140 | ||
141 | /* Now extract both insns and see if we can meet their | |
142 | constraints. */ | |
143 | ok = (cached_reg_save_code[reg][mode] != -1 | |
144 | && cached_reg_restore_code[reg][mode] != -1); | |
145 | if (ok) | |
146 | { | |
147 | extract_insn (saveinsn); | |
148 | ok = constrain_operands (1); | |
149 | extract_insn (restinsn); | |
150 | ok &= constrain_operands (1); | |
151 | } | |
152 | ||
153 | if (! ok) | |
154 | { | |
155 | cached_reg_save_code[reg][mode] = -1; | |
156 | cached_reg_restore_code[reg][mode] = -1; | |
157 | } | |
158 | gcc_assert (cached_reg_save_code[reg][mode]); | |
159 | return cached_reg_save_code[reg][mode]; | |
160 | } | |
161 | ||
162 | /* Return the INSN_CODE used to restore register REG in mode MODE. */ | |
163 | static int | |
164 | reg_restore_code (int reg, enum machine_mode mode) | |
165 | { | |
166 | if (cached_reg_restore_code[reg][mode]) | |
167 | return cached_reg_restore_code[reg][mode]; | |
168 | /* Populate our cache. */ | |
169 | reg_save_code (reg, mode); | |
170 | return cached_reg_restore_code[reg][mode]; | |
171 | } | |
172 | \f | |
c5986054 RS |
173 | /* Initialize for caller-save. |
174 | ||
175 | Look at all the hard registers that are used by a call and for which | |
328e13b7 | 176 | reginfo.c has not already excluded from being used across a call. |
c5986054 | 177 | |
d329e058 | 178 | Ensure that we can find a mode to save the register and that there is a |
c5986054 RS |
179 | simple insn to save and restore the register. This latter check avoids |
180 | problems that would occur if we tried to save the MQ register of some | |
181 | machines directly into memory. */ | |
182 | ||
183 | void | |
d329e058 | 184 | init_caller_save (void) |
c5986054 | 185 | { |
c5986054 RS |
186 | rtx addr_reg; |
187 | int offset; | |
188 | rtx address; | |
f95361c8 | 189 | int i, j; |
c5986054 | 190 | |
dc12b70e JZ |
191 | if (caller_save_initialized_p) |
192 | return; | |
193 | ||
194 | caller_save_initialized_p = true; | |
195 | ||
058e97ec | 196 | CLEAR_HARD_REG_SET (no_caller_save_reg_set); |
c5986054 RS |
197 | /* First find all the registers that we need to deal with and all |
198 | the modes that they can have. If we can't find a mode to use, | |
199 | we can't have the register live over calls. */ | |
200 | ||
201 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
202 | { | |
adee59ae AS |
203 | if (call_used_regs[i] |
204 | && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) | |
c5986054 | 205 | { |
7609e720 | 206 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
c5986054 | 207 | { |
787dc842 JH |
208 | regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, |
209 | VOIDmode); | |
f95361c8 JL |
210 | if (regno_save_mode[i][j] == VOIDmode && j == 1) |
211 | { | |
f95361c8 JL |
212 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
213 | } | |
c5986054 RS |
214 | } |
215 | } | |
216 | else | |
f95361c8 | 217 | regno_save_mode[i][1] = VOIDmode; |
c5986054 RS |
218 | } |
219 | ||
220 | /* The following code tries to approximate the conditions under which | |
221 | we can easily save and restore a register without scratch registers or | |
222 | other complexities. It will usually work, except under conditions where | |
223 | the validity of an insn operand is dependent on the address offset. | |
224 | No such cases are currently known. | |
225 | ||
226 | We first find a typical offset from some BASE_REG_CLASS register. | |
227 | This address is chosen by finding the first register in the class | |
228 | and by finding the smallest power of two that is a valid offset from | |
229 | that register in every mode we will use to save registers. */ | |
230 | ||
231 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3dcc68a4 NC |
232 | if (TEST_HARD_REG_BIT |
233 | (reg_class_contents | |
86fc3d06 UW |
234 | [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, |
235 | PLUS, CONST_INT)], i)) | |
c5986054 RS |
236 | break; |
237 | ||
366de0ce | 238 | gcc_assert (i < FIRST_PSEUDO_REGISTER); |
c5986054 | 239 | |
38a448ca | 240 | addr_reg = gen_rtx_REG (Pmode, i); |
c5986054 RS |
241 | |
242 | for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) | |
243 | { | |
38a448ca | 244 | address = gen_rtx_PLUS (Pmode, addr_reg, GEN_INT (offset)); |
c5986054 RS |
245 | |
246 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f95361c8 JL |
247 | if (regno_save_mode[i][1] != VOIDmode |
248 | && ! strict_memory_address_p (regno_save_mode[i][1], address)) | |
c5986054 RS |
249 | break; |
250 | ||
251 | if (i == FIRST_PSEUDO_REGISTER) | |
252 | break; | |
253 | } | |
254 | ||
255 | /* If we didn't find a valid address, we must use register indirect. */ | |
256 | if (offset == 0) | |
257 | address = addr_reg; | |
258 | ||
259 | /* Next we try to form an insn to save and restore the register. We | |
d329e058 | 260 | see if such an insn is recognized and meets its constraints. |
bf1660a6 JL |
261 | |
262 | To avoid lots of unnecessary RTL allocation, we construct all the RTL | |
263 | once, then modify the memory and register operands in-place. */ | |
264 | ||
265 | test_reg = gen_rtx_REG (VOIDmode, 0); | |
266 | test_mem = gen_rtx_MEM (VOIDmode, address); | |
267 | savepat = gen_rtx_SET (VOIDmode, test_mem, test_reg); | |
268 | restpat = gen_rtx_SET (VOIDmode, test_reg, test_mem); | |
c5986054 | 269 | |
418e920f BS |
270 | saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, savepat, 0, -1, 0); |
271 | restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, restpat, 0, -1, 0); | |
0db79a6b | 272 | |
787dc842 JH |
273 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
274 | for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
78187f5a | 275 | if (reg_save_code (i,regno_save_mode[i][j]) == -1) |
787dc842 JH |
276 | { |
277 | regno_save_mode[i][j] = VOIDmode; | |
278 | if (j == 1) | |
279 | { | |
787dc842 | 280 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
058e97ec VM |
281 | if (call_used_regs[i]) |
282 | SET_HARD_REG_BIT (no_caller_save_reg_set, i); | |
787dc842 JH |
283 | } |
284 | } | |
c5986054 | 285 | } |
058e97ec | 286 | |
c5986054 | 287 | \f |
058e97ec | 288 | |
c5986054 RS |
289 | /* Initialize save areas by showing that we haven't allocated any yet. */ |
290 | ||
291 | void | |
d329e058 | 292 | init_save_areas (void) |
c5986054 | 293 | { |
f95361c8 | 294 | int i, j; |
c5986054 RS |
295 | |
296 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7609e720 | 297 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
f95361c8 | 298 | regno_save_mem[i][j] = 0; |
058e97ec | 299 | save_slots_num = 0; |
b8698a0f | 300 | |
058e97ec VM |
301 | } |
302 | ||
303 | /* The structure represents a hard register which should be saved | |
304 | through the call. It is used when the integrated register | |
305 | allocator (IRA) is used and sharing save slots is on. */ | |
306 | struct saved_hard_reg | |
307 | { | |
308 | /* Order number starting with 0. */ | |
309 | int num; | |
310 | /* The hard regno. */ | |
311 | int hard_regno; | |
312 | /* Execution frequency of all calls through which given hard | |
313 | register should be saved. */ | |
314 | int call_freq; | |
315 | /* Stack slot reserved to save the hard register through calls. */ | |
316 | rtx slot; | |
317 | /* True if it is first hard register in the chain of hard registers | |
318 | sharing the same stack slot. */ | |
319 | int first_p; | |
320 | /* Order number of the next hard register structure with the same | |
321 | slot in the chain. -1 represents end of the chain. */ | |
322 | int next; | |
323 | }; | |
324 | ||
325 | /* Map: hard register number to the corresponding structure. */ | |
326 | static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; | |
327 | ||
328 | /* The number of all structures representing hard registers should be | |
329 | saved, in order words, the number of used elements in the following | |
330 | array. */ | |
331 | static int saved_regs_num; | |
332 | ||
333 | /* Pointers to all the structures. Index is the order number of the | |
334 | corresponding structure. */ | |
335 | static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; | |
336 | ||
337 | /* First called function for work with saved hard registers. */ | |
338 | static void | |
339 | initiate_saved_hard_regs (void) | |
340 | { | |
341 | int i; | |
342 | ||
343 | saved_regs_num = 0; | |
344 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
345 | hard_reg_map[i] = NULL; | |
346 | } | |
347 | ||
348 | /* Allocate and return new saved hard register with given REGNO and | |
349 | CALL_FREQ. */ | |
e16b6fd0 | 350 | static void |
058e97ec VM |
351 | new_saved_hard_reg (int regno, int call_freq) |
352 | { | |
353 | struct saved_hard_reg *saved_reg; | |
354 | ||
355 | saved_reg | |
356 | = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); | |
357 | hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; | |
358 | saved_reg->num = saved_regs_num++; | |
359 | saved_reg->hard_regno = regno; | |
360 | saved_reg->call_freq = call_freq; | |
361 | saved_reg->first_p = FALSE; | |
362 | saved_reg->next = -1; | |
058e97ec VM |
363 | } |
364 | ||
365 | /* Free memory allocated for the saved hard registers. */ | |
366 | static void | |
367 | finish_saved_hard_regs (void) | |
368 | { | |
369 | int i; | |
370 | ||
371 | for (i = 0; i < saved_regs_num; i++) | |
372 | free (all_saved_regs[i]); | |
373 | } | |
374 | ||
375 | /* The function is used to sort the saved hard register structures | |
376 | according their frequency. */ | |
377 | static int | |
378 | saved_hard_reg_compare_func (const void *v1p, const void *v2p) | |
379 | { | |
380 | const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; | |
381 | const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; | |
b8698a0f | 382 | |
058e97ec VM |
383 | if (flag_omit_frame_pointer) |
384 | { | |
385 | if (p1->call_freq - p2->call_freq != 0) | |
386 | return p1->call_freq - p2->call_freq; | |
387 | } | |
388 | else if (p2->call_freq - p1->call_freq != 0) | |
389 | return p2->call_freq - p1->call_freq; | |
390 | ||
391 | return p1->num - p2->num; | |
c5986054 RS |
392 | } |
393 | ||
394 | /* Allocate save areas for any hard registers that might need saving. | |
395 | We take a conservative approach here and look for call-clobbered hard | |
396 | registers that are assigned to pseudos that cross calls. This may | |
397 | overestimate slightly (especially if some of these registers are later | |
398 | used as spill registers), but it should not be significant. | |
399 | ||
058e97ec VM |
400 | For IRA we use priority coloring to decrease stack slots needed for |
401 | saving hard registers through calls. We build conflicts for them | |
402 | to do coloring. | |
403 | ||
f95361c8 JL |
404 | Future work: |
405 | ||
406 | In the fallback case we should iterate backwards across all possible | |
d329e058 | 407 | modes for the save, choosing the largest available one instead of |
f95361c8 JL |
408 | falling back to the smallest mode immediately. (eg TF -> DF -> SF). |
409 | ||
410 | We do not try to use "move multiple" instructions that exist | |
d329e058 | 411 | on some machines (such as the 68k moveml). It could be a win to try |
f95361c8 | 412 | and use them when possible. The hard part is doing it in a way that is |
d329e058 | 413 | machine independent since they might be saving non-consecutive |
f95361c8 | 414 | registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ |
c5986054 | 415 | |
437a710d | 416 | void |
d329e058 | 417 | setup_save_areas (void) |
c5986054 | 418 | { |
e90b336f | 419 | int i, j, k, freq; |
f95361c8 | 420 | HARD_REG_SET hard_regs_used; |
e90b336f JL |
421 | struct saved_hard_reg *saved_reg; |
422 | rtx insn; | |
423 | struct insn_chain *chain, *next; | |
424 | unsigned int regno; | |
425 | HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; | |
426 | reg_set_iterator rsi; | |
f95361c8 | 427 | |
f95361c8 | 428 | CLEAR_HARD_REG_SET (hard_regs_used); |
f95361c8 | 429 | |
e90b336f JL |
430 | /* Find every CALL_INSN and record which hard regs are live across the |
431 | call into HARD_REG_MAP and HARD_REGS_USED. */ | |
432 | initiate_saved_hard_regs (); | |
433 | /* Create hard reg saved regs. */ | |
434 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
058e97ec | 435 | { |
e384e6b5 BS |
436 | rtx cheap; |
437 | ||
e90b336f JL |
438 | insn = chain->insn; |
439 | next = chain->next; | |
440 | if (!CALL_P (insn) | |
441 | || find_reg_note (insn, REG_NORETURN, NULL)) | |
442 | continue; | |
443 | freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); | |
444 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
445 | &chain->live_throughout); | |
446 | COPY_HARD_REG_SET (used_regs, call_used_reg_set); | |
447 | ||
448 | /* Record all registers set in this call insn. These don't | |
449 | need to be saved. N.B. the call insn might set a subreg | |
450 | of a multi-hard-reg pseudo; then the pseudo is considered | |
451 | live during the call, but the subreg that is set | |
452 | isn't. */ | |
453 | CLEAR_HARD_REG_SET (this_insn_sets); | |
454 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
455 | /* Sibcalls are considered to set the return value. */ | |
456 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) | |
457 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
458 | ||
459 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
460 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
461 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
462 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
463 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
464 | { | |
465 | if (hard_reg_map[regno] != NULL) | |
466 | hard_reg_map[regno]->call_freq += freq; | |
467 | else | |
e16b6fd0 | 468 | new_saved_hard_reg (regno, freq); |
e90b336f JL |
469 | SET_HARD_REG_BIT (hard_regs_used, regno); |
470 | } | |
e384e6b5 BS |
471 | cheap = find_reg_note (insn, REG_RETURNED, NULL); |
472 | if (cheap) | |
473 | cheap = XEXP (cheap, 0); | |
e90b336f JL |
474 | /* Look through all live pseudos, mark their hard registers. */ |
475 | EXECUTE_IF_SET_IN_REG_SET | |
476 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
058e97ec | 477 | { |
e90b336f JL |
478 | int r = reg_renumber[regno]; |
479 | int bound; | |
058e97ec | 480 | |
e384e6b5 | 481 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
e90b336f | 482 | continue; |
058e97ec | 483 | |
e90b336f JL |
484 | bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
485 | for (; r < bound; r++) | |
486 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
058e97ec | 487 | { |
e90b336f JL |
488 | if (hard_reg_map[r] != NULL) |
489 | hard_reg_map[r]->call_freq += freq; | |
058e97ec | 490 | else |
e16b6fd0 | 491 | new_saved_hard_reg (r, freq); |
e90b336f JL |
492 | SET_HARD_REG_BIT (hard_regs_to_save, r); |
493 | SET_HARD_REG_BIT (hard_regs_used, r); | |
058e97ec | 494 | } |
e90b336f JL |
495 | } |
496 | } | |
b8698a0f | 497 | |
e90b336f JL |
498 | /* If requested, figure out which hard regs can share save slots. */ |
499 | if (optimize && flag_ira_share_save_slots) | |
500 | { | |
501 | rtx slot; | |
502 | char *saved_reg_conflicts; | |
503 | int next_k; | |
504 | struct saved_hard_reg *saved_reg2, *saved_reg3; | |
505 | int call_saved_regs_num; | |
506 | struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; | |
507 | int best_slot_num; | |
508 | int prev_save_slots_num; | |
509 | rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; | |
b8698a0f | 510 | |
058e97ec VM |
511 | /* Find saved hard register conflicts. */ |
512 | saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); | |
513 | memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); | |
514 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
515 | { | |
e384e6b5 | 516 | rtx cheap; |
058e97ec VM |
517 | call_saved_regs_num = 0; |
518 | insn = chain->insn; | |
519 | next = chain->next; | |
481683e1 | 520 | if (!CALL_P (insn) |
058e97ec VM |
521 | || find_reg_note (insn, REG_NORETURN, NULL)) |
522 | continue; | |
e384e6b5 BS |
523 | |
524 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
525 | if (cheap) | |
526 | cheap = XEXP (cheap, 0); | |
527 | ||
058e97ec VM |
528 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, |
529 | &chain->live_throughout); | |
530 | COPY_HARD_REG_SET (used_regs, call_used_reg_set); | |
531 | ||
532 | /* Record all registers set in this call insn. These don't | |
533 | need to be saved. N.B. the call insn might set a subreg | |
534 | of a multi-hard-reg pseudo; then the pseudo is considered | |
535 | live during the call, but the subreg that is set | |
536 | isn't. */ | |
537 | CLEAR_HARD_REG_SET (this_insn_sets); | |
538 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
539 | /* Sibcalls are considered to set the return value, | |
912eb5a4 | 540 | compare df-scan.c:df_get_call_refs. */ |
058e97ec VM |
541 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) |
542 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
543 | ||
544 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
545 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
546 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
547 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
548 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
549 | { | |
550 | gcc_assert (hard_reg_map[regno] != NULL); | |
551 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; | |
552 | } | |
553 | /* Look through all live pseudos, mark their hard registers. */ | |
554 | EXECUTE_IF_SET_IN_REG_SET | |
555 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
c5986054 | 556 | { |
058e97ec VM |
557 | int r = reg_renumber[regno]; |
558 | int bound; | |
b8698a0f | 559 | |
e384e6b5 | 560 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
058e97ec VM |
561 | continue; |
562 | ||
563 | bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; | |
564 | for (; r < bound; r++) | |
565 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
566 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; | |
c5986054 | 567 | } |
058e97ec VM |
568 | for (i = 0; i < call_saved_regs_num; i++) |
569 | { | |
570 | saved_reg = call_saved_regs[i]; | |
571 | for (j = 0; j < call_saved_regs_num; j++) | |
572 | if (i != j) | |
573 | { | |
574 | saved_reg2 = call_saved_regs[j]; | |
575 | saved_reg_conflicts[saved_reg->num * saved_regs_num | |
576 | + saved_reg2->num] | |
577 | = saved_reg_conflicts[saved_reg2->num * saved_regs_num | |
578 | + saved_reg->num] | |
579 | = TRUE; | |
580 | } | |
581 | } | |
582 | } | |
583 | /* Sort saved hard regs. */ | |
584 | qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), | |
585 | saved_hard_reg_compare_func); | |
586 | /* Initiate slots available from the previous reload | |
587 | iteration. */ | |
588 | prev_save_slots_num = save_slots_num; | |
589 | memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); | |
590 | save_slots_num = 0; | |
591 | /* Allocate stack slots for the saved hard registers. */ | |
592 | for (i = 0; i < saved_regs_num; i++) | |
593 | { | |
594 | saved_reg = all_saved_regs[i]; | |
595 | regno = saved_reg->hard_regno; | |
596 | for (j = 0; j < i; j++) | |
597 | { | |
598 | saved_reg2 = all_saved_regs[j]; | |
599 | if (! saved_reg2->first_p) | |
600 | continue; | |
601 | slot = saved_reg2->slot; | |
602 | for (k = j; k >= 0; k = next_k) | |
603 | { | |
604 | saved_reg3 = all_saved_regs[k]; | |
605 | next_k = saved_reg3->next; | |
606 | if (saved_reg_conflicts[saved_reg->num * saved_regs_num | |
607 | + saved_reg3->num]) | |
608 | break; | |
609 | } | |
610 | if (k < 0 | |
611 | && (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
612 | <= GET_MODE_SIZE (regno_save_mode | |
613 | [saved_reg2->hard_regno][1]))) | |
614 | { | |
615 | saved_reg->slot | |
616 | = adjust_address_nv | |
617 | (slot, regno_save_mode[saved_reg->hard_regno][1], 0); | |
618 | regno_save_mem[regno][1] = saved_reg->slot; | |
619 | saved_reg->next = saved_reg2->next; | |
620 | saved_reg2->next = i; | |
621 | if (dump_file != NULL) | |
622 | fprintf (dump_file, "%d uses slot of %d\n", | |
623 | regno, saved_reg2->hard_regno); | |
624 | break; | |
625 | } | |
626 | } | |
627 | if (j == i) | |
628 | { | |
629 | saved_reg->first_p = TRUE; | |
630 | for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) | |
631 | { | |
632 | slot = prev_save_slots[j]; | |
633 | if (slot == NULL_RTX) | |
634 | continue; | |
635 | if (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
636 | <= GET_MODE_SIZE (GET_MODE (slot)) | |
637 | && best_slot_num < 0) | |
638 | best_slot_num = j; | |
639 | if (GET_MODE (slot) == regno_save_mode[regno][1]) | |
640 | break; | |
641 | } | |
642 | if (best_slot_num >= 0) | |
643 | { | |
644 | saved_reg->slot = prev_save_slots[best_slot_num]; | |
645 | saved_reg->slot | |
646 | = adjust_address_nv | |
647 | (saved_reg->slot, | |
648 | regno_save_mode[saved_reg->hard_regno][1], 0); | |
649 | if (dump_file != NULL) | |
650 | fprintf (dump_file, | |
651 | "%d uses a slot from prev iteration\n", regno); | |
652 | prev_save_slots[best_slot_num] = NULL_RTX; | |
653 | if (best_slot_num + 1 == prev_save_slots_num) | |
654 | prev_save_slots_num--; | |
655 | } | |
656 | else | |
657 | { | |
658 | saved_reg->slot | |
659 | = assign_stack_local_1 | |
660 | (regno_save_mode[regno][1], | |
80a832cd JJ |
661 | GET_MODE_SIZE (regno_save_mode[regno][1]), 0, |
662 | ASLK_REDUCE_ALIGN); | |
058e97ec VM |
663 | if (dump_file != NULL) |
664 | fprintf (dump_file, "%d uses a new slot\n", regno); | |
665 | } | |
666 | regno_save_mem[regno][1] = saved_reg->slot; | |
667 | save_slots[save_slots_num++] = saved_reg->slot; | |
668 | } | |
669 | } | |
670 | free (saved_reg_conflicts); | |
671 | finish_saved_hard_regs (); | |
672 | } | |
673 | else | |
674 | { | |
e90b336f JL |
675 | /* We are not sharing slots. |
676 | ||
677 | Run through all the call-used hard-registers and allocate | |
678 | space for each in the caller-save area. Try to allocate space | |
058e97ec | 679 | in a manner which allows multi-register saves/restores to be done. */ |
b8698a0f | 680 | |
058e97ec VM |
681 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
682 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
683 | { | |
684 | int do_save = 1; | |
b8698a0f | 685 | |
058e97ec VM |
686 | /* If no mode exists for this size, try another. Also break out |
687 | if we have already saved this hard register. */ | |
688 | if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) | |
689 | continue; | |
b8698a0f | 690 | |
058e97ec VM |
691 | /* See if any register in this group has been saved. */ |
692 | for (k = 0; k < j; k++) | |
693 | if (regno_save_mem[i + k][1]) | |
694 | { | |
695 | do_save = 0; | |
696 | break; | |
697 | } | |
698 | if (! do_save) | |
699 | continue; | |
b8698a0f | 700 | |
058e97ec VM |
701 | for (k = 0; k < j; k++) |
702 | if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) | |
703 | { | |
704 | do_save = 0; | |
705 | break; | |
706 | } | |
707 | if (! do_save) | |
708 | continue; | |
b8698a0f | 709 | |
058e97ec VM |
710 | /* We have found an acceptable mode to store in. Since |
711 | hard register is always saved in the widest mode | |
712 | available, the mode may be wider than necessary, it is | |
713 | OK to reduce the alignment of spill space. We will | |
714 | verify that it is equal to or greater than required | |
715 | when we restore and save the hard register in | |
716 | insert_restore and insert_save. */ | |
717 | regno_save_mem[i][j] | |
718 | = assign_stack_local_1 (regno_save_mode[i][j], | |
719 | GET_MODE_SIZE (regno_save_mode[i][j]), | |
80a832cd | 720 | 0, ASLK_REDUCE_ALIGN); |
b8698a0f | 721 | |
058e97ec VM |
722 | /* Setup single word save area just in case... */ |
723 | for (k = 0; k < j; k++) | |
724 | /* This should not depend on WORDS_BIG_ENDIAN. | |
725 | The order of words in regs is the same as in memory. */ | |
726 | regno_save_mem[i + k][1] | |
727 | = adjust_address_nv (regno_save_mem[i][j], | |
728 | regno_save_mode[i + k][1], | |
729 | k * UNITS_PER_WORD); | |
730 | } | |
731 | } | |
3bdf5ad1 RK |
732 | |
733 | /* Now loop again and set the alias set of any save areas we made to | |
734 | the alias set used to represent frame objects. */ | |
735 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
736 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
737 | if (regno_save_mem[i][j] != 0) | |
ba4828e0 | 738 | set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); |
c5986054 | 739 | } |
058e97ec | 740 | |
c5986054 | 741 | \f |
058e97ec | 742 | |
437a710d | 743 | /* Find the places where hard regs are live across calls and save them. */ |
3bdf5ad1 | 744 | |
c5986054 | 745 | void |
d329e058 | 746 | save_call_clobbered_regs (void) |
c5986054 | 747 | { |
169e464e | 748 | struct insn_chain *chain, *next, *last = NULL; |
787dc842 | 749 | enum machine_mode save_mode [FIRST_PSEUDO_REGISTER]; |
7609e720 | 750 | |
e30edd6c R |
751 | /* Computed in mark_set_regs, holds all registers set by the current |
752 | instruction. */ | |
753 | HARD_REG_SET this_insn_sets; | |
754 | ||
7609e720 BS |
755 | CLEAR_HARD_REG_SET (hard_regs_saved); |
756 | n_regs_saved = 0; | |
c5986054 | 757 | |
7609e720 | 758 | for (chain = reload_insn_chain; chain != 0; chain = next) |
c5986054 | 759 | { |
7609e720 BS |
760 | rtx insn = chain->insn; |
761 | enum rtx_code code = GET_CODE (insn); | |
762 | ||
763 | next = chain->next; | |
764 | ||
366de0ce | 765 | gcc_assert (!chain->is_caller_save_insn); |
7609e720 | 766 | |
b5b8b0ac | 767 | if (NONDEBUG_INSN_P (insn)) |
c5986054 | 768 | { |
7609e720 BS |
769 | /* If some registers have been saved, see if INSN references |
770 | any of them. We must restore them before the insn if so. */ | |
c5986054 | 771 | |
7609e720 | 772 | if (n_regs_saved) |
c5986054 | 773 | { |
7609e720 | 774 | int regno; |
14292418 | 775 | HARD_REG_SET this_insn_sets; |
7609e720 BS |
776 | |
777 | if (code == JUMP_INSN) | |
778 | /* Restore all registers if this is a JUMP_INSN. */ | |
779 | COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); | |
0e6362d9 | 780 | else |
0887bd4b | 781 | { |
7609e720 | 782 | CLEAR_HARD_REG_SET (referenced_regs); |
b5b8b0ac AO |
783 | mark_referenced_regs (&PATTERN (insn), |
784 | mark_reg_as_referenced, NULL); | |
7609e720 | 785 | AND_HARD_REG_SET (referenced_regs, hard_regs_saved); |
0887bd4b | 786 | } |
c5986054 | 787 | |
7609e720 BS |
788 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
789 | if (TEST_HARD_REG_BIT (referenced_regs, regno)) | |
14292418 BS |
790 | regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, |
791 | save_mode); | |
792 | /* If a saved register is set after the call, this means we no | |
793 | longer should restore it. This can happen when parts of a | |
794 | multi-word pseudo do not conflict with other pseudos, so | |
795 | IRA may allocate the same hard register for both. One may | |
796 | be live across the call, while the other is set | |
797 | afterwards. */ | |
798 | CLEAR_HARD_REG_SET (this_insn_sets); | |
799 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
800 | AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); | |
c5986054 RS |
801 | } |
802 | ||
ed765125 PB |
803 | if (code == CALL_INSN |
804 | && ! SIBLING_CALL_P (insn) | |
805 | && ! find_reg_note (insn, REG_NORETURN, NULL)) | |
7609e720 | 806 | { |
3cd8c58a | 807 | unsigned regno; |
7609e720 | 808 | HARD_REG_SET hard_regs_to_save; |
a2041967 | 809 | reg_set_iterator rsi; |
e384e6b5 BS |
810 | rtx cheap; |
811 | ||
812 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
813 | if (cheap) | |
814 | cheap = XEXP (cheap, 0); | |
7609e720 BS |
815 | |
816 | /* Use the register life information in CHAIN to compute which | |
285f3cf0 R |
817 | regs are live during the call. */ |
818 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
239a0f5b | 819 | &chain->live_throughout); |
f63d1bf7 | 820 | /* Save hard registers always in the widest mode available. */ |
787dc842 JH |
821 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
822 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
823 | save_mode [regno] = regno_save_mode [regno][1]; | |
824 | else | |
825 | save_mode [regno] = VOIDmode; | |
826 | ||
f5143c46 | 827 | /* Look through all live pseudos, mark their hard registers |
787dc842 JH |
828 | and choose proper mode for saving. */ |
829 | EXECUTE_IF_SET_IN_REG_SET | |
a2041967 KH |
830 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) |
831 | { | |
832 | int r = reg_renumber[regno]; | |
833 | int nregs; | |
834 | enum machine_mode mode; | |
835 | ||
e384e6b5 | 836 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
058e97ec | 837 | continue; |
a2041967 KH |
838 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
839 | mode = HARD_REGNO_CALLER_SAVE_MODE | |
840 | (r, nregs, PSEUDO_REGNO_MODE (regno)); | |
841 | if (GET_MODE_BITSIZE (mode) | |
842 | > GET_MODE_BITSIZE (save_mode[r])) | |
843 | save_mode[r] = mode; | |
844 | while (nregs-- > 0) | |
845 | SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); | |
846 | } | |
7609e720 BS |
847 | |
848 | /* Record all registers set in this call insn. These don't need | |
285f3cf0 R |
849 | to be saved. N.B. the call insn might set a subreg of a |
850 | multi-hard-reg pseudo; then the pseudo is considered live | |
851 | during the call, but the subreg that is set isn't. */ | |
7609e720 | 852 | CLEAR_HARD_REG_SET (this_insn_sets); |
e30edd6c | 853 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); |
7609e720 BS |
854 | |
855 | /* Compute which hard regs must be saved before this call. */ | |
856 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); | |
857 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); | |
858 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); | |
859 | AND_HARD_REG_SET (hard_regs_to_save, call_used_reg_set); | |
860 | ||
7609e720 BS |
861 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
862 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
787dc842 | 863 | regno += insert_save (chain, 1, regno, &hard_regs_to_save, save_mode); |
7609e720 BS |
864 | |
865 | /* Must recompute n_regs_saved. */ | |
866 | n_regs_saved = 0; | |
867 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
868 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
869 | n_regs_saved++; | |
e384e6b5 BS |
870 | |
871 | if (cheap | |
872 | && HARD_REGISTER_P (cheap) | |
873 | && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) | |
874 | { | |
1d2944a3 BS |
875 | rtx dest, newpat; |
876 | rtx pat = PATTERN (insn); | |
877 | if (GET_CODE (pat) == PARALLEL) | |
878 | pat = XVECEXP (pat, 0, 0); | |
879 | dest = SET_DEST (pat); | |
880 | newpat = gen_rtx_SET (VOIDmode, cheap, copy_rtx (dest)); | |
881 | chain = insert_one_insn (chain, 0, -1, newpat); | |
e384e6b5 | 882 | } |
7609e720 | 883 | } |
169e464e | 884 | last = chain; |
7609e720 | 885 | } |
b5b8b0ac AO |
886 | else if (DEBUG_INSN_P (insn) && n_regs_saved) |
887 | mark_referenced_regs (&PATTERN (insn), | |
888 | replace_reg_with_saved_mem, | |
889 | save_mode); | |
c5986054 | 890 | |
058e97ec | 891 | if (chain->next == 0 || chain->next->block != chain->block) |
7609e720 BS |
892 | { |
893 | int regno; | |
894 | /* At the end of the basic block, we must restore any registers that | |
895 | remain saved. If the last insn in the block is a JUMP_INSN, put | |
896 | the restore before the insn, otherwise, put it after the insn. */ | |
897 | ||
49b48605 JJ |
898 | if (n_regs_saved |
899 | && DEBUG_INSN_P (insn) | |
900 | && last | |
901 | && last->block == chain->block) | |
169e464e JJ |
902 | { |
903 | rtx ins, prev; | |
904 | basic_block bb = BLOCK_FOR_INSN (insn); | |
905 | ||
906 | /* When adding hard reg restores after a DEBUG_INSN, move | |
907 | all notes between last real insn and this DEBUG_INSN after | |
908 | the DEBUG_INSN, otherwise we could get code | |
909 | -g/-g0 differences. */ | |
910 | for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) | |
911 | { | |
912 | prev = PREV_INSN (ins); | |
913 | if (NOTE_P (ins)) | |
914 | { | |
915 | NEXT_INSN (prev) = NEXT_INSN (ins); | |
916 | PREV_INSN (NEXT_INSN (ins)) = prev; | |
917 | PREV_INSN (ins) = insn; | |
918 | NEXT_INSN (ins) = NEXT_INSN (insn); | |
919 | NEXT_INSN (insn) = ins; | |
920 | if (NEXT_INSN (ins)) | |
921 | PREV_INSN (NEXT_INSN (ins)) = ins; | |
922 | if (BB_END (bb) == insn) | |
923 | BB_END (bb) = ins; | |
924 | } | |
925 | else | |
926 | gcc_assert (DEBUG_INSN_P (ins)); | |
927 | } | |
928 | } | |
929 | last = NULL; | |
930 | ||
7609e720 BS |
931 | if (n_regs_saved) |
932 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
933 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
4b4bf941 | 934 | regno += insert_restore (chain, JUMP_P (insn), |
787dc842 | 935 | regno, MOVE_MAX_WORDS, save_mode); |
7609e720 | 936 | } |
d329e058 | 937 | } |
c5986054 RS |
938 | } |
939 | ||
e30edd6c R |
940 | /* Here from note_stores, or directly from save_call_clobbered_regs, when |
941 | an insn stores a value in a register. | |
7609e720 | 942 | Set the proper bit or bits in this_insn_sets. All pseudos that have |
c5986054 RS |
943 | been assigned hard regs have had their register number changed already, |
944 | so we can ignore pseudos. */ | |
c5986054 | 945 | static void |
7bc980e1 | 946 | mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) |
c5986054 | 947 | { |
b3694847 | 948 | int regno, endregno, i; |
f883e0a7 | 949 | HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; |
c5986054 RS |
950 | |
951 | if (GET_CODE (reg) == SUBREG) | |
952 | { | |
ddef6bc7 | 953 | rtx inner = SUBREG_REG (reg); |
f8cfc6aa | 954 | if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 955 | return; |
6f9e3578 | 956 | regno = subreg_regno (reg); |
f1f4e530 | 957 | endregno = regno + subreg_nregs (reg); |
ddef6bc7 | 958 | } |
f8cfc6aa | 959 | else if (REG_P (reg) |
ddef6bc7 | 960 | && REGNO (reg) < FIRST_PSEUDO_REGISTER) |
f1f4e530 JM |
961 | { |
962 | regno = REGNO (reg); | |
09e18274 | 963 | endregno = END_HARD_REGNO (reg); |
f1f4e530 | 964 | } |
ddef6bc7 | 965 | else |
c5986054 RS |
966 | return; |
967 | ||
c5986054 | 968 | for (i = regno; i < endregno; i++) |
e30edd6c | 969 | SET_HARD_REG_BIT (*this_insn_sets, i); |
c5986054 RS |
970 | } |
971 | ||
285f3cf0 R |
972 | /* Here from note_stores when an insn stores a value in a register. |
973 | Set the proper bit or bits in the passed regset. All pseudos that have | |
974 | been assigned hard regs have had their register number changed already, | |
975 | so we can ignore pseudos. */ | |
976 | static void | |
7bc980e1 | 977 | add_stored_regs (rtx reg, const_rtx setter, void *data) |
285f3cf0 | 978 | { |
b3694847 | 979 | int regno, endregno, i; |
285f3cf0 | 980 | enum machine_mode mode = GET_MODE (reg); |
ddef6bc7 | 981 | int offset = 0; |
285f3cf0 R |
982 | |
983 | if (GET_CODE (setter) == CLOBBER) | |
984 | return; | |
985 | ||
a446b4e8 JM |
986 | if (GET_CODE (reg) == SUBREG |
987 | && REG_P (SUBREG_REG (reg)) | |
988 | && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) | |
285f3cf0 | 989 | { |
ddef6bc7 JJ |
990 | offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), |
991 | GET_MODE (SUBREG_REG (reg)), | |
992 | SUBREG_BYTE (reg), | |
993 | GET_MODE (reg)); | |
a446b4e8 | 994 | regno = REGNO (SUBREG_REG (reg)) + offset; |
f1f4e530 | 995 | endregno = regno + subreg_nregs (reg); |
285f3cf0 | 996 | } |
f1f4e530 JM |
997 | else |
998 | { | |
999 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
1000 | return; | |
285f3cf0 | 1001 | |
f1f4e530 | 1002 | regno = REGNO (reg) + offset; |
09e18274 | 1003 | endregno = end_hard_regno (mode, regno); |
f1f4e530 | 1004 | } |
285f3cf0 R |
1005 | |
1006 | for (i = regno; i < endregno; i++) | |
1007 | SET_REGNO_REG_SET ((regset) data, i); | |
1008 | } | |
1009 | ||
7609e720 | 1010 | /* Walk X and record all referenced registers in REFERENCED_REGS. */ |
c5986054 | 1011 | static void |
b5b8b0ac | 1012 | mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) |
c5986054 | 1013 | { |
b5b8b0ac | 1014 | enum rtx_code code = GET_CODE (*loc); |
6f7d635c | 1015 | const char *fmt; |
c5986054 RS |
1016 | int i, j; |
1017 | ||
7609e720 | 1018 | if (code == SET) |
b5b8b0ac | 1019 | mark_referenced_regs (&SET_SRC (*loc), mark, arg); |
7609e720 BS |
1020 | if (code == SET || code == CLOBBER) |
1021 | { | |
b5b8b0ac AO |
1022 | loc = &SET_DEST (*loc); |
1023 | code = GET_CODE (*loc); | |
1024 | if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) | |
4d450e9a | 1025 | || code == PC || code == CC0 |
b5b8b0ac AO |
1026 | || (code == SUBREG && REG_P (SUBREG_REG (*loc)) |
1027 | && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER | |
2696f6a4 AO |
1028 | /* If we're setting only part of a multi-word register, |
1029 | we shall mark it as referenced, because the words | |
1030 | that are not being set should be restored. */ | |
b5b8b0ac AO |
1031 | && ((GET_MODE_SIZE (GET_MODE (*loc)) |
1032 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc)))) | |
1033 | || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc))) | |
2696f6a4 | 1034 | <= UNITS_PER_WORD)))) |
7609e720 BS |
1035 | return; |
1036 | } | |
1037 | if (code == MEM || code == SUBREG) | |
1038 | { | |
b5b8b0ac AO |
1039 | loc = &XEXP (*loc, 0); |
1040 | code = GET_CODE (*loc); | |
7609e720 | 1041 | } |
f95361c8 | 1042 | |
c5986054 RS |
1043 | if (code == REG) |
1044 | { | |
b5b8b0ac | 1045 | int regno = REGNO (*loc); |
7609e720 BS |
1046 | int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno |
1047 | : reg_renumber[regno]); | |
c5986054 | 1048 | |
7609e720 | 1049 | if (hardregno >= 0) |
b5b8b0ac AO |
1050 | mark (loc, GET_MODE (*loc), hardregno, arg); |
1051 | else if (arg) | |
1052 | /* ??? Will we ever end up with an equiv expression in a debug | |
1053 | insn, that would have required restoring a reg, or will | |
1054 | reload take care of it for us? */ | |
1055 | return; | |
7609e720 BS |
1056 | /* If this is a pseudo that did not get a hard register, scan its |
1057 | memory location, since it might involve the use of another | |
1058 | register, which might be saved. */ | |
f2034d06 JL |
1059 | else if (reg_equiv_mem (regno) != 0) |
1060 | mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); | |
1061 | else if (reg_equiv_address (regno) != 0) | |
1062 | mark_referenced_regs (®_equiv_address (regno), mark, arg); | |
c5986054 RS |
1063 | return; |
1064 | } | |
7609e720 | 1065 | |
c5986054 RS |
1066 | fmt = GET_RTX_FORMAT (code); |
1067 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1068 | { | |
1069 | if (fmt[i] == 'e') | |
b5b8b0ac | 1070 | mark_referenced_regs (&XEXP (*loc, i), mark, arg); |
c5986054 | 1071 | else if (fmt[i] == 'E') |
b5b8b0ac AO |
1072 | for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) |
1073 | mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | /* Parameter function for mark_referenced_regs() that adds registers | |
1078 | present in the insn and in equivalent mems and addresses to | |
1079 | referenced_regs. */ | |
1080 | ||
1081 | static void | |
1082 | mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, | |
1083 | enum machine_mode mode, | |
1084 | int hardregno, | |
1085 | void *arg ATTRIBUTE_UNUSED) | |
1086 | { | |
1087 | add_to_hard_reg_set (&referenced_regs, mode, hardregno); | |
1088 | } | |
1089 | ||
1090 | /* Parameter function for mark_referenced_regs() that replaces | |
1091 | registers referenced in a debug_insn that would have been restored, | |
1092 | should it be a non-debug_insn, with their save locations. */ | |
1093 | ||
1094 | static void | |
1095 | replace_reg_with_saved_mem (rtx *loc, | |
1096 | enum machine_mode mode, | |
1097 | int regno, | |
1098 | void *arg) | |
1099 | { | |
1100 | unsigned int i, nregs = hard_regno_nregs [regno][mode]; | |
1101 | rtx mem; | |
1102 | enum machine_mode *save_mode = (enum machine_mode *)arg; | |
1103 | ||
1104 | for (i = 0; i < nregs; i++) | |
1105 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1106 | break; | |
1107 | ||
1108 | /* If none of the registers in the range would need restoring, we're | |
1109 | all set. */ | |
1110 | if (i == nregs) | |
1111 | return; | |
1112 | ||
1113 | while (++i < nregs) | |
1114 | if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1115 | break; | |
1116 | ||
1117 | if (i == nregs | |
1118 | && regno_save_mem[regno][nregs]) | |
1119 | { | |
1120 | mem = copy_rtx (regno_save_mem[regno][nregs]); | |
1121 | ||
1122 | if (nregs == (unsigned int) hard_regno_nregs[regno][save_mode[regno]]) | |
1123 | mem = adjust_address_nv (mem, save_mode[regno], 0); | |
1124 | ||
1125 | if (GET_MODE (mem) != mode) | |
1126 | { | |
1127 | /* This is gen_lowpart_if_possible(), but without validating | |
1128 | the newly-formed address. */ | |
1129 | int offset = 0; | |
1130 | ||
1131 | if (WORDS_BIG_ENDIAN) | |
1132 | offset = (MAX (GET_MODE_SIZE (GET_MODE (mem)), UNITS_PER_WORD) | |
1133 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1134 | if (BYTES_BIG_ENDIAN) | |
1135 | /* Adjust the address so that the address-after-the-data is | |
1136 | unchanged. */ | |
1137 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1138 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (mem)))); | |
1139 | ||
1140 | mem = adjust_address_nv (mem, mode, offset); | |
1141 | } | |
c5986054 | 1142 | } |
b5b8b0ac AO |
1143 | else |
1144 | { | |
1145 | mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); | |
1146 | for (i = 0; i < nregs; i++) | |
1147 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1148 | { | |
1149 | gcc_assert (regno_save_mem[regno + i][1]); | |
1150 | XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); | |
1151 | } | |
1152 | else | |
1153 | { | |
1154 | gcc_assert (save_mode[regno] != VOIDmode); | |
1155 | XVECEXP (mem, 0, i) = gen_rtx_REG (save_mode [regno], | |
1156 | regno + i); | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | gcc_assert (GET_MODE (mem) == mode); | |
1161 | *loc = mem; | |
c5986054 | 1162 | } |
b5b8b0ac | 1163 | |
c5986054 | 1164 | \f |
7609e720 BS |
1165 | /* Insert a sequence of insns to restore. Place these insns in front of |
1166 | CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is | |
1167 | the maximum number of registers which should be restored during this call. | |
1168 | It should never be less than 1 since we only work with entire registers. | |
c5986054 RS |
1169 | |
1170 | Note that we have verified in init_caller_save that we can do this | |
1171 | with a simple SET, so use it. Set INSN_CODE to what we save there | |
1172 | since the address might not be valid so the insn might not be recognized. | |
1173 | These insns will be reloaded and have register elimination done by | |
f95361c8 | 1174 | find_reload, so we need not worry about that here. |
c5986054 | 1175 | |
f95361c8 JL |
1176 | Return the extra number of registers saved. */ |
1177 | ||
1178 | static int | |
d329e058 AJ |
1179 | insert_restore (struct insn_chain *chain, int before_p, int regno, |
1180 | int maxrestore, enum machine_mode *save_mode) | |
c5986054 | 1181 | { |
285f3cf0 | 1182 | int i, k; |
aefdd5ab | 1183 | rtx pat = NULL_RTX; |
830a47ec | 1184 | int code; |
787dc842 | 1185 | unsigned int numregs = 0; |
32e9fa48 | 1186 | struct insn_chain *new_chain; |
787dc842 | 1187 | rtx mem; |
c5986054 | 1188 | |
41806d92 NS |
1189 | /* A common failure mode if register status is not correct in the |
1190 | RTL is for this routine to be called with a REGNO we didn't | |
1191 | expect to save. That will cause us to write an insn with a (nil) | |
1192 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1193 | later, check for this common case here instead. This will remove | |
1194 | one step in debugging such problems. */ | |
366de0ce | 1195 | gcc_assert (regno_save_mem[regno][1]); |
09835ed2 | 1196 | |
7609e720 | 1197 | /* Get the pattern to emit and update our status. |
4554e20d | 1198 | |
7609e720 | 1199 | See if we can restore `maxrestore' registers at once. Work |
4554e20d JL |
1200 | backwards to the single register case. */ |
1201 | for (i = maxrestore; i > 0; i--) | |
c5986054 | 1202 | { |
285f3cf0 | 1203 | int j; |
7609e720 BS |
1204 | int ok = 1; |
1205 | ||
1206 | if (regno_save_mem[regno][i] == 0) | |
4554e20d JL |
1207 | continue; |
1208 | ||
7609e720 BS |
1209 | for (j = 0; j < i; j++) |
1210 | if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) | |
1211 | { | |
1212 | ok = 0; | |
1213 | break; | |
1214 | } | |
f9da5064 | 1215 | /* Must do this one restore at a time. */ |
4554e20d JL |
1216 | if (! ok) |
1217 | continue; | |
7609e720 | 1218 | |
4554e20d JL |
1219 | numregs = i; |
1220 | break; | |
1221 | } | |
f95361c8 | 1222 | |
787dc842 JH |
1223 | mem = regno_save_mem [regno][numregs]; |
1224 | if (save_mode [regno] != VOIDmode | |
1225 | && save_mode [regno] != GET_MODE (mem) | |
c3c96e68 L |
1226 | && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] |
1227 | /* Check that insn to restore REGNO in save_mode[regno] is | |
1228 | correct. */ | |
1229 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
8d2547f2 | 1230 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
ce7b36a4 JW |
1231 | else |
1232 | mem = copy_rtx (mem); | |
76fe54f0 L |
1233 | |
1234 | /* Verify that the alignment of spill space is equal to or greater | |
1235 | than required. */ | |
058e97ec VM |
1236 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1237 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
76fe54f0 | 1238 | |
285f3cf0 | 1239 | pat = gen_rtx_SET (VOIDmode, |
d329e058 | 1240 | gen_rtx_REG (GET_MODE (mem), |
787dc842 | 1241 | regno), mem); |
78187f5a | 1242 | code = reg_restore_code (regno, GET_MODE (mem)); |
32e9fa48 | 1243 | new_chain = insert_one_insn (chain, before_p, code, pat); |
285f3cf0 R |
1244 | |
1245 | /* Clear status for all registers we restored. */ | |
1246 | for (k = 0; k < i; k++) | |
1247 | { | |
1248 | CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); | |
32e9fa48 | 1249 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
285f3cf0 R |
1250 | n_regs_saved--; |
1251 | } | |
1252 | ||
6614fd40 | 1253 | /* Tell our callers how many extra registers we saved/restored. */ |
4554e20d JL |
1254 | return numregs - 1; |
1255 | } | |
f95361c8 | 1256 | |
7609e720 | 1257 | /* Like insert_restore above, but save registers instead. */ |
2cc2d4bb | 1258 | |
4554e20d | 1259 | static int |
d329e058 AJ |
1260 | insert_save (struct insn_chain *chain, int before_p, int regno, |
1261 | HARD_REG_SET (*to_save), enum machine_mode *save_mode) | |
4554e20d | 1262 | { |
787dc842 JH |
1263 | int i; |
1264 | unsigned int k; | |
4554e20d | 1265 | rtx pat = NULL_RTX; |
830a47ec | 1266 | int code; |
787dc842 | 1267 | unsigned int numregs = 0; |
32e9fa48 | 1268 | struct insn_chain *new_chain; |
787dc842 | 1269 | rtx mem; |
f95361c8 | 1270 | |
41806d92 NS |
1271 | /* A common failure mode if register status is not correct in the |
1272 | RTL is for this routine to be called with a REGNO we didn't | |
1273 | expect to save. That will cause us to write an insn with a (nil) | |
1274 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1275 | later, check for this common case here. This will remove one | |
4554e20d | 1276 | step in debugging such problems. */ |
366de0ce | 1277 | gcc_assert (regno_save_mem[regno][1]); |
c5986054 | 1278 | |
7609e720 | 1279 | /* Get the pattern to emit and update our status. |
f95361c8 | 1280 | |
d329e058 | 1281 | See if we can save several registers with a single instruction. |
4554e20d | 1282 | Work backwards to the single register case. */ |
7609e720 | 1283 | for (i = MOVE_MAX_WORDS; i > 0; i--) |
4554e20d | 1284 | { |
285f3cf0 | 1285 | int j; |
7609e720 BS |
1286 | int ok = 1; |
1287 | if (regno_save_mem[regno][i] == 0) | |
4554e20d | 1288 | continue; |
f95361c8 | 1289 | |
7609e720 BS |
1290 | for (j = 0; j < i; j++) |
1291 | if (! TEST_HARD_REG_BIT (*to_save, regno + j)) | |
1292 | { | |
1293 | ok = 0; | |
1294 | break; | |
1295 | } | |
f9da5064 | 1296 | /* Must do this one save at a time. */ |
4554e20d JL |
1297 | if (! ok) |
1298 | continue; | |
1299 | ||
4554e20d JL |
1300 | numregs = i; |
1301 | break; | |
f95361c8 | 1302 | } |
c5986054 | 1303 | |
787dc842 JH |
1304 | mem = regno_save_mem [regno][numregs]; |
1305 | if (save_mode [regno] != VOIDmode | |
1306 | && save_mode [regno] != GET_MODE (mem) | |
c3c96e68 L |
1307 | && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] |
1308 | /* Check that insn to save REGNO in save_mode[regno] is | |
1309 | correct. */ | |
1310 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
8d2547f2 | 1311 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
ce7b36a4 JW |
1312 | else |
1313 | mem = copy_rtx (mem); | |
76fe54f0 L |
1314 | |
1315 | /* Verify that the alignment of spill space is equal to or greater | |
1316 | than required. */ | |
058e97ec VM |
1317 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1318 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
76fe54f0 | 1319 | |
787dc842 JH |
1320 | pat = gen_rtx_SET (VOIDmode, mem, |
1321 | gen_rtx_REG (GET_MODE (mem), | |
285f3cf0 | 1322 | regno)); |
78187f5a | 1323 | code = reg_save_code (regno, GET_MODE (mem)); |
32e9fa48 | 1324 | new_chain = insert_one_insn (chain, before_p, code, pat); |
285f3cf0 R |
1325 | |
1326 | /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ | |
1327 | for (k = 0; k < numregs; k++) | |
1328 | { | |
1329 | SET_HARD_REG_BIT (hard_regs_saved, regno + k); | |
32e9fa48 | 1330 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
285f3cf0 R |
1331 | n_regs_saved++; |
1332 | } | |
f95361c8 | 1333 | |
6614fd40 | 1334 | /* Tell our callers how many extra registers we saved/restored. */ |
f95361c8 | 1335 | return numregs - 1; |
c5986054 | 1336 | } |
4554e20d | 1337 | |
574af2d6 RS |
1338 | /* A for_each_rtx callback used by add_used_regs. Add the hard-register |
1339 | equivalent of each REG to regset DATA. */ | |
1340 | ||
1341 | static int | |
1342 | add_used_regs_1 (rtx *loc, void *data) | |
1343 | { | |
f773c2bd | 1344 | unsigned int regno; |
574af2d6 RS |
1345 | regset live; |
1346 | rtx x; | |
1347 | ||
1348 | x = *loc; | |
1349 | live = (regset) data; | |
1350 | if (REG_P (x)) | |
1351 | { | |
1352 | regno = REGNO (x); | |
f773c2bd AS |
1353 | if (HARD_REGISTER_NUM_P (regno)) |
1354 | bitmap_set_range (live, regno, hard_regno_nregs[regno][GET_MODE (x)]); | |
1355 | else | |
574af2d6 | 1356 | regno = reg_renumber[regno]; |
574af2d6 RS |
1357 | } |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | /* A note_uses callback used by insert_one_insn. Add the hard-register | |
1362 | equivalent of each REG to regset DATA. */ | |
1363 | ||
1364 | static void | |
1365 | add_used_regs (rtx *loc, void *data) | |
1366 | { | |
1367 | for_each_rtx (loc, add_used_regs_1, data); | |
1368 | } | |
1369 | ||
7609e720 | 1370 | /* Emit a new caller-save insn and set the code. */ |
285f3cf0 | 1371 | static struct insn_chain * |
d329e058 | 1372 | insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat) |
4554e20d | 1373 | { |
7609e720 | 1374 | rtx insn = chain->insn; |
32e9fa48 | 1375 | struct insn_chain *new_chain; |
d329e058 | 1376 | |
4554e20d JL |
1377 | #ifdef HAVE_cc0 |
1378 | /* If INSN references CC0, put our insns in front of the insn that sets | |
1379 | CC0. This is always safe, since the only way we could be passed an | |
1380 | insn that references CC0 is for a restore, and doing a restore earlier | |
1381 | isn't a problem. We do, however, assume here that CALL_INSNs don't | |
1382 | reference CC0. Guard against non-INSN's like CODE_LABEL. */ | |
1383 | ||
4b4bf941 | 1384 | if ((NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
4554e20d JL |
1385 | && before_p |
1386 | && reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
7609e720 | 1387 | chain = chain->prev, insn = chain->insn; |
4554e20d JL |
1388 | #endif |
1389 | ||
32e9fa48 | 1390 | new_chain = new_insn_chain (); |
4554e20d JL |
1391 | if (before_p) |
1392 | { | |
285f3cf0 R |
1393 | rtx link; |
1394 | ||
32e9fa48 KG |
1395 | new_chain->prev = chain->prev; |
1396 | if (new_chain->prev != 0) | |
1397 | new_chain->prev->next = new_chain; | |
7609e720 | 1398 | else |
32e9fa48 | 1399 | reload_insn_chain = new_chain; |
7609e720 | 1400 | |
32e9fa48 KG |
1401 | chain->prev = new_chain; |
1402 | new_chain->next = chain; | |
1403 | new_chain->insn = emit_insn_before (pat, insn); | |
92691d7d JL |
1404 | /* ??? It would be nice if we could exclude the already / still saved |
1405 | registers from the live sets. */ | |
32e9fa48 | 1406 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
574af2d6 RS |
1407 | note_uses (&PATTERN (chain->insn), add_used_regs, |
1408 | &new_chain->live_throughout); | |
ac8bc93e PB |
1409 | /* If CHAIN->INSN is a call, then the registers which contain |
1410 | the arguments to the function are live in the new insn. */ | |
1411 | if (CALL_P (chain->insn)) | |
574af2d6 RS |
1412 | for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); |
1413 | link != NULL_RTX; | |
1414 | link = XEXP (link, 1)) | |
1415 | note_uses (&XEXP (link, 0), add_used_regs, | |
1416 | &new_chain->live_throughout); | |
ac8bc93e | 1417 | |
32e9fa48 | 1418 | CLEAR_REG_SET (&new_chain->dead_or_set); |
a813c111 | 1419 | if (chain->insn == BB_HEAD (BASIC_BLOCK (chain->block))) |
32e9fa48 | 1420 | BB_HEAD (BASIC_BLOCK (chain->block)) = new_chain->insn; |
4554e20d JL |
1421 | } |
1422 | else | |
1423 | { | |
32e9fa48 KG |
1424 | new_chain->next = chain->next; |
1425 | if (new_chain->next != 0) | |
1426 | new_chain->next->prev = new_chain; | |
1427 | chain->next = new_chain; | |
1428 | new_chain->prev = chain; | |
1429 | new_chain->insn = emit_insn_after (pat, insn); | |
92691d7d JL |
1430 | /* ??? It would be nice if we could exclude the already / still saved |
1431 | registers from the live sets, and observe REG_UNUSED notes. */ | |
32e9fa48 | 1432 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
285f3cf0 | 1433 | /* Registers that are set in CHAIN->INSN live in the new insn. |
c22cacf3 | 1434 | (Unless there is a REG_UNUSED note for them, but we don't |
285f3cf0 R |
1435 | look for them here.) */ |
1436 | note_stores (PATTERN (chain->insn), add_stored_regs, | |
32e9fa48 KG |
1437 | &new_chain->live_throughout); |
1438 | CLEAR_REG_SET (&new_chain->dead_or_set); | |
a813c111 | 1439 | if (chain->insn == BB_END (BASIC_BLOCK (chain->block))) |
32e9fa48 | 1440 | BB_END (BASIC_BLOCK (chain->block)) = new_chain->insn; |
4554e20d | 1441 | } |
32e9fa48 KG |
1442 | new_chain->block = chain->block; |
1443 | new_chain->is_caller_save_insn = 1; | |
437a710d | 1444 | |
32e9fa48 KG |
1445 | INSN_CODE (new_chain->insn) = code; |
1446 | return new_chain; | |
4554e20d | 1447 | } |
78187f5a | 1448 | #include "gt-caller-save.h" |