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08b1e29a | 1 | ;; Constraint definitions for IA-32 and x86-64. |
7adcbafe | 2 | ;; Copyright (C) 2006-2022 Free Software Foundation, Inc. |
08b1e29a RS |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
08b1e29a RS |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
08b1e29a RS |
19 | |
20 | ;;; Unused letters: | |
6041d142 | 21 | ;;; H |
d5e254e1 | 22 | ;;; h j z |
08b1e29a RS |
23 | |
24 | ;; Integer register constraints. | |
25 | ;; It is not necessary to define 'r' here. | |
26 | (define_register_constraint "R" "LEGACY_REGS" | |
27 | "Legacy register---the eight integer registers available on all | |
28 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
29 | @code{si}, @code{di}, @code{bp}, @code{sp}).") | |
30 | ||
31 | (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" | |
32 | "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
33 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") | |
34 | ||
35 | (define_register_constraint "Q" "Q_REGS" | |
36 | "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
37 | @code{c}, and @code{d}.") | |
38 | ||
39 | (define_register_constraint "l" "INDEX_REGS" | |
40 | "@internal Any register that can be used as the index in a base+index | |
41 | memory access: that is, any general register except the stack pointer.") | |
42 | ||
43 | (define_register_constraint "a" "AREG" | |
44 | "The @code{a} register.") | |
45 | ||
46 | (define_register_constraint "b" "BREG" | |
47 | "The @code{b} register.") | |
48 | ||
49 | (define_register_constraint "c" "CREG" | |
50 | "The @code{c} register.") | |
51 | ||
52 | (define_register_constraint "d" "DREG" | |
53 | "The @code{d} register.") | |
54 | ||
55 | (define_register_constraint "S" "SIREG" | |
56 | "The @code{si} register.") | |
57 | ||
58 | (define_register_constraint "D" "DIREG" | |
59 | "The @code{di} register.") | |
60 | ||
61 | (define_register_constraint "A" "AD_REGS" | |
62 | "The @code{a} and @code{d} registers, as a pair (for instructions | |
63 | that return half the result in one and half in the other).") | |
64 | ||
ac2e563f RH |
65 | (define_register_constraint "U" "CLOBBERED_REGS" |
66 | "The call-clobbered integer registers.") | |
67 | ||
08b1e29a RS |
68 | ;; Floating-point register constraints. |
69 | (define_register_constraint "f" | |
70 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" | |
71 | "Any 80387 floating-point (stack) register.") | |
72 | ||
73 | (define_register_constraint "t" | |
74 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" | |
75 | "Top of 80387 floating-point stack (@code{%st(0)}).") | |
76 | ||
77 | (define_register_constraint "u" | |
78 | "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" | |
79 | "Second from top of 80387 floating-point stack (@code{%st(1)}).") | |
80 | ||
d18cbbf6 | 81 | (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS" |
85a77221 AI |
82 | "@internal Any mask register that can be used as predicate, i.e. k1-k7.") |
83 | ||
d18cbbf6 | 84 | (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS" |
85a77221 AI |
85 | "@internal Any mask register.") |
86 | ||
08b1e29a RS |
87 | ;; Vector registers (also used for plain floating point nowadays). |
88 | (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" | |
89 | "Any MMX register.") | |
90 | ||
91 | (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" | |
92 | "Any SSE register.") | |
93 | ||
1828d3e6 UB |
94 | (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" |
95 | "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") | |
96 | ||
50961141 | 97 | ;; We use the Y prefix to denote any number of conditional register sets: |
e2520c41 | 98 | ;; z First SSE register. |
8d75ab4d | 99 | ;; d any EVEX encodable SSE register for AVX512DQ target or |
038acbba | 100 | ;; any SSE register for SSE4_1 target. |
1657d923 | 101 | ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled |
904eea2c | 102 | ;; a Integer register when zero extensions with AND are disabled |
de86ff8f L |
103 | ;; b Any register that can be used as the GOT base when calling |
104 | ;; ___tls_get_addr: that is, any general register except EAX | |
105 | ;; and ESP, for -fno-plt if linker supports it. Otherwise, | |
106 | ;; EBX. | |
593c0ddd | 107 | ;; f x87 register when 80387 floating point arithmetic is enabled |
45392c76 IE |
108 | ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled |
109 | ;; and all SSE regs otherwise | |
1657d923 UB |
110 | ;; v any EVEX encodable SSE register for AVX512VL target, |
111 | ;; otherwise any SSE register | |
74e299b9 | 112 | ;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL |
a18ebd6c | 113 | ;; target, otherwise any SSE register. |
3bb345c9 JJ |
114 | ;; W any EVEX encodable SSE register for AVX512BW target, |
115 | ;; otherwise any SSE register. | |
50961141 | 116 | |
e2520c41 | 117 | (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" |
c3b9a8d6 L |
118 | "First SSE register (@code{%xmm0}).") |
119 | ||
1657d923 | 120 | (define_register_constraint "Yd" |
038acbba UB |
121 | "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS" |
122 | "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.") | |
1657d923 | 123 | |
78d8c16c UB |
124 | (define_register_constraint "Yp" |
125 | "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" | |
126 | "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") | |
127 | ||
904eea2c UB |
128 | (define_register_constraint "Ya" |
129 | "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) | |
130 | ? NO_REGS : GENERAL_REGS" | |
131 | "@internal Any integer register when zero extensions with AND are disabled.") | |
132 | ||
de86ff8f L |
133 | (define_register_constraint "Yb" |
134 | "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG" | |
135 | "@internal Any register that can be used as the GOT base when calling | |
136 | ___tls_get_addr: that is, any general register except @code{a} and | |
137 | @code{sp} registers, for -fno-plt if linker supports it. Otherwise, | |
138 | @code{b} register.") | |
139 | ||
593c0ddd UB |
140 | (define_register_constraint "Yf" |
141 | "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" | |
142 | "@internal Any x87 register when 80387 FP arithmetic is enabled.") | |
143 | ||
45392c76 | 144 | (define_register_constraint "Yr" |
8e0dc054 | 145 | "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS" |
45392c76 IE |
146 | "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") |
147 | ||
40bd4bf9 JJ |
148 | (define_register_constraint "Yv" |
149 | "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" | |
150 | "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") | |
151 | ||
74e299b9 | 152 | (define_register_constraint "Yw" |
a18ebd6c JJ |
153 | "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" |
154 | "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.") | |
74e299b9 | 155 | |
3bb345c9 JJ |
156 | (define_register_constraint "YW" |
157 | "TARGET_AVX512BW ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" | |
158 | "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target, otherwise any SSE register.") | |
159 | ||
1828d3e6 | 160 | ;; We use the B prefix to denote any number of internal operands: |
f767f583 | 161 | ;; f FLAGS_REG |
f70d27e0 | 162 | ;; g GOT memory operand. |
3f50525d | 163 | ;; m Vector memory operand |
4b6d0c0e | 164 | ;; c Constant memory operand |
5c8617dc | 165 | ;; n Memory operand without REX prefix |
1828d3e6 UB |
166 | ;; s Sibcall memory operand, not valid for TARGET_X32 |
167 | ;; w Call memory operand, not valid for TARGET_X32 | |
168 | ;; z Constant call address operand. | |
3d7ccbc1 L |
169 | ;; C Integer SSE constant with all bits set operand. |
170 | ;; F Floating-point SSE constant with all bits set operand. | |
9407058a | 171 | ;; M x86-64 memory operand. |
6041d142 | 172 | |
f767f583 RH |
173 | (define_constraint "Bf" |
174 | "@internal Flags register operand." | |
175 | (match_operand 0 "flags_reg_operand")) | |
176 | ||
f70d27e0 L |
177 | (define_constraint "Bg" |
178 | "@internal GOT memory operand." | |
179 | (match_operand 0 "GOT_memory_operand")) | |
180 | ||
9eb1ca69 | 181 | (define_special_memory_constraint "Bm" |
3f50525d L |
182 | "@internal Vector memory operand." |
183 | (match_operand 0 "vector_memory_operand")) | |
184 | ||
4b6d0c0e UB |
185 | (define_special_memory_constraint "Bc" |
186 | "@internal Constant memory operand." | |
187 | (and (match_operand 0 "memory_operand") | |
188 | (match_test "constant_address_p (XEXP (op, 0))"))) | |
189 | ||
b5844cb0 | 190 | (define_memory_constraint "Bk" |
191 | "@internal TLS address that allows insn using non-integer registers." | |
192 | (and (match_operand 0 "memory_operand") | |
193 | (not (match_test "ix86_gpr_tls_address_pattern_p (op)")))) | |
194 | ||
5c8617dc UB |
195 | (define_special_memory_constraint "Bn" |
196 | "@internal Memory operand without REX prefix." | |
197 | (match_operand 0 "norex_memory_operand")) | |
198 | ||
7026bb95 | 199 | (define_special_memory_constraint "Br" |
200 | "@internal bcst memory operand." | |
201 | (match_operand 0 "bcst_mem_operand")) | |
202 | ||
6041d142 KT |
203 | (define_constraint "Bs" |
204 | "@internal Sibcall memory operand." | |
c2c601b2 | 205 | (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
4a5a0497 | 206 | (not (match_test "TARGET_X32")) |
fa87d16d | 207 | (match_operand 0 "sibcall_memory_operand")) |
09bf5279 UB |
208 | (and (match_test "TARGET_X32") |
209 | (match_test "Pmode == DImode") | |
fa87d16d | 210 | (match_operand 0 "GOT_memory_operand")))) |
6041d142 | 211 | |
1828d3e6 | 212 | (define_constraint "Bw" |
6025b127 | 213 | "@internal Call memory operand." |
c2c601b2 | 214 | (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
4a5a0497 | 215 | (not (match_test "TARGET_X32")) |
fa87d16d | 216 | (match_operand 0 "memory_operand")) |
09bf5279 UB |
217 | (and (match_test "TARGET_X32") |
218 | (match_test "Pmode == DImode") | |
fa87d16d | 219 | (match_operand 0 "GOT_memory_operand")))) |
6025b127 | 220 | |
1828d3e6 UB |
221 | (define_constraint "Bz" |
222 | "@internal Constant call address operand." | |
223 | (match_operand 0 "constant_call_address_operand")) | |
224 | ||
aec0b19e | 225 | (define_constraint "BC" |
3d7ccbc1 | 226 | "@internal integer SSE constant with all bits set operand." |
55284a77 | 227 | (and (match_test "TARGET_SSE") |
90f82260 | 228 | (ior (match_test "op == constm1_rtx") |
55284a77 | 229 | (match_operand 0 "vector_all_ones_operand")))) |
aec0b19e | 230 | |
3d7ccbc1 L |
231 | (define_constraint "BF" |
232 | "@internal floating-point SSE constant with all bits set operand." | |
233 | (and (match_test "TARGET_SSE") | |
234 | (match_operand 0 "float_vector_all_ones_operand"))) | |
235 | ||
9407058a L |
236 | ;; NB: Similar to 'm', but don't use define_memory_constraint on x86-64 |
237 | ;; to prevent LRA from converting the operand to the form '(mem (reg X))' | |
238 | ;; where X is a base register. | |
239 | (define_constraint "BM" | |
240 | "@internal x86-64 memory operand." | |
241 | (and (match_code "mem") | |
242 | (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0), | |
243 | MEM_ADDR_SPACE (op))"))) | |
244 | ||
08b1e29a | 245 | ;; Integer constant constraints. |
a56c2518 | 246 | (define_constraint "Wb" |
247 | "Integer constant in the range 0 @dots{} 7, for 8-bit shifts." | |
248 | (and (match_code "const_int") | |
249 | (match_test "IN_RANGE (ival, 0, 7)"))) | |
250 | ||
251 | (define_constraint "Ww" | |
252 | "Integer constant in the range 0 @dots{} 15, for 16-bit shifts." | |
253 | (and (match_code "const_int") | |
254 | (match_test "IN_RANGE (ival, 0, 15)"))) | |
255 | ||
08b1e29a RS |
256 | (define_constraint "I" |
257 | "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." | |
258 | (and (match_code "const_int") | |
8dde5924 | 259 | (match_test "IN_RANGE (ival, 0, 31)"))) |
08b1e29a RS |
260 | |
261 | (define_constraint "J" | |
262 | "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." | |
263 | (and (match_code "const_int") | |
8dde5924 | 264 | (match_test "IN_RANGE (ival, 0, 63)"))) |
08b1e29a RS |
265 | |
266 | (define_constraint "K" | |
267 | "Signed 8-bit integer constant." | |
268 | (and (match_code "const_int") | |
8dde5924 | 269 | (match_test "IN_RANGE (ival, -128, 127)"))) |
08b1e29a RS |
270 | |
271 | (define_constraint "L" | |
f148a434 UB |
272 | "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} |
273 | for AND as a zero-extending move." | |
08b1e29a | 274 | (and (match_code "const_int") |
09bf5279 UB |
275 | (ior (match_test "ival == 0xff") |
276 | (match_test "ival == 0xffff") | |
277 | (match_test "ival == (HOST_WIDE_INT) 0xffffffff")))) | |
08b1e29a RS |
278 | |
279 | (define_constraint "M" | |
280 | "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." | |
281 | (and (match_code "const_int") | |
8dde5924 | 282 | (match_test "IN_RANGE (ival, 0, 3)"))) |
08b1e29a RS |
283 | |
284 | (define_constraint "N" | |
4f3f76e6 | 285 | "Unsigned 8-bit integer constant (for @code{in} and @code{out} |
08b1e29a RS |
286 | instructions)." |
287 | (and (match_code "const_int") | |
8dde5924 | 288 | (match_test "IN_RANGE (ival, 0, 255)"))) |
08b1e29a RS |
289 | |
290 | (define_constraint "O" | |
291 | "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." | |
292 | (and (match_code "const_int") | |
8dde5924 | 293 | (match_test "IN_RANGE (ival, 0, 127)"))) |
08b1e29a RS |
294 | |
295 | ;; Floating-point constant constraints. | |
296 | ;; We allow constants even if TARGET_80387 isn't set, because the | |
297 | ;; stack register converter may need to load 0.0 into the function | |
298 | ;; value register (top of stack). | |
299 | (define_constraint "G" | |
300 | "Standard 80387 floating point constant." | |
301 | (and (match_code "const_double") | |
479fecd3 | 302 | (match_test "standard_80387_constant_p (op) > 0"))) |
08b1e29a RS |
303 | |
304 | ;; This can theoretically be any mode's CONST0_RTX. | |
305 | (define_constraint "C" | |
808d8de5 UB |
306 | "Constant zero operand." |
307 | (ior (match_test "op == const0_rtx") | |
308 | (match_operand 0 "const0_operand"))) | |
08b1e29a RS |
309 | |
310 | ;; Constant-or-symbol-reference constraints. | |
311 | ||
312 | (define_constraint "e" | |
313 | "32-bit signed integer constant, or a symbolic reference known | |
314 | to fit that range (for immediate operands in sign-extending x86-64 | |
315 | instructions)." | |
316 | (match_operand 0 "x86_64_immediate_operand")) | |
317 | ||
3cb2b15b UB |
318 | ;; We use W prefix to denote any number of |
319 | ;; constant-or-symbol-reference constraints | |
320 | ||
d1873c57 JJ |
321 | (define_constraint "We" |
322 | "32-bit signed integer constant, or a symbolic reference known | |
323 | to fit that range (for sign-extending conversion operations that | |
324 | require non-VOIDmode immediate operands)." | |
325 | (and (match_operand 0 "x86_64_immediate_operand") | |
09bf5279 | 326 | (match_test "mode != VOIDmode"))) |
d1873c57 | 327 | |
3cb2b15b UB |
328 | (define_constraint "Wz" |
329 | "32-bit unsigned integer constant, or a symbolic reference known | |
330 | to fit that range (for zero-extending conversion operations that | |
331 | require non-VOIDmode immediate operands)." | |
332 | (and (match_operand 0 "x86_64_zext_immediate_operand") | |
09bf5279 | 333 | (match_test "mode != VOIDmode"))) |
3cb2b15b | 334 | |
31ed1665 JJ |
335 | (define_constraint "Wd" |
336 | "128-bit integer constant where both the high and low 64-bit word | |
337 | of it satisfies the e constraint." | |
338 | (match_operand 0 "x86_64_hilo_int_operand")) | |
339 | ||
47a6cc4e JJ |
340 | (define_constraint "Wf" |
341 | "32-bit signed integer constant zero extended from word size | |
342 | to double word size." | |
343 | (match_operand 0 "x86_64_dwzext_immediate_operand")) | |
344 | ||
08b1e29a RS |
345 | (define_constraint "Z" |
346 | "32-bit unsigned integer constant, or a symbolic reference known | |
347 | to fit that range (for immediate operands in zero-extending x86-64 | |
348 | instructions)." | |
349 | (match_operand 0 "x86_64_zext_immediate_operand")) | |
66d6cbaa IE |
350 | |
351 | ;; T prefix is used for different address constraints | |
65e95828 UB |
352 | ;; v - VSIB address |
353 | ;; s - address with no segment register | |
d5e254e1 IE |
354 | ;; i - address with no index and no rip |
355 | ;; b - address with no base and no rip | |
66d6cbaa | 356 | |
65e95828 UB |
357 | (define_address_constraint "Tv" |
358 | "VSIB address operand" | |
359 | (match_operand 0 "vsib_address_operand")) | |
360 | ||
361 | (define_address_constraint "Ts" | |
362 | "Address operand without segment register" | |
363 | (match_operand 0 "address_no_seg_operand")) |