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7d9ae20a | 1 | /* Definitions of target machine for GCC for IA-32. |
9526f064 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
038d1e19 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
4 | Free Software Foundation, Inc. | |
43b83681 | 5 | |
7d9ae20a | 6 | This file is part of GCC. |
43b83681 | 7 | |
7d9ae20a | 8 | GCC is free software; you can redistribute it and/or modify |
43b83681 | 9 | it under the terms of the GNU General Public License as published by |
038d1e19 | 10 | the Free Software Foundation; either version 3, or (at your option) |
43b83681 | 11 | any later version. |
12 | ||
7d9ae20a | 13 | GCC is distributed in the hope that it will be useful, |
43b83681 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
43b83681 | 21 | |
0bbe9142 | 22 | /* The purpose of this file is to define the characteristics of the i386, |
23 | independent of assembler syntax or operating system. | |
24 | ||
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
36 | ||
e44348b5 | 37 | /* Redefines for option macros. */ |
38 | ||
39 | #define TARGET_64BIT OPTION_ISA_64BIT | |
40 | #define TARGET_MMX OPTION_ISA_MMX | |
41 | #define TARGET_3DNOW OPTION_ISA_3DNOW | |
42 | #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A | |
43 | #define TARGET_SSE OPTION_ISA_SSE | |
44 | #define TARGET_SSE2 OPTION_ISA_SSE2 | |
45 | #define TARGET_SSE3 OPTION_ISA_SSE3 | |
46 | #define TARGET_SSSE3 OPTION_ISA_SSSE3 | |
47 | #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 | |
f25d51c3 | 48 | #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 |
e44348b5 | 49 | #define TARGET_SSE4A OPTION_ISA_SSE4A |
448e99f5 | 50 | #define TARGET_SSE5 OPTION_ISA_SSE5 |
51 | #define TARGET_ROUND OPTION_ISA_ROUND | |
46f8e3b0 | 52 | #define TARGET_ABM OPTION_ISA_ABM |
53 | #define TARGET_POPCNT OPTION_ISA_POPCNT | |
54 | #define TARGET_SAHF OPTION_ISA_SAHF | |
55 | #define TARGET_AES OPTION_ISA_AES | |
56 | #define TARGET_PCLMUL OPTION_ISA_PCLMUL | |
57 | #define TARGET_CMPXCHG16B OPTION_ISA_CX16 | |
58 | ||
448e99f5 | 59 | |
60 | /* SSE5 and SSE4.1 define the same round instructions */ | |
61 | #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5) | |
62 | #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) | |
e44348b5 | 63 | |
2522d9ea | 64 | #include "config/vxworks-dummy.h" |
65 | ||
ab608690 | 66 | /* Algorithm to expand string function with. */ |
67 | enum stringop_alg | |
68 | { | |
69 | no_stringop, | |
70 | libcall, | |
71 | rep_prefix_1_byte, | |
72 | rep_prefix_4_byte, | |
73 | rep_prefix_8_byte, | |
74 | loop_1_byte, | |
75 | loop, | |
76 | unrolled_loop | |
77 | }; | |
0bbe9142 | 78 | |
ab608690 | 79 | #define NAX_STRINGOP_ALGS 4 |
0bbe9142 | 80 | |
ab608690 | 81 | /* Specify what algorithm to use for stringops on known size. |
82 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
83 | known at compile time or estimated via feedback, the SIZE array | |
84 | is walked in order until MAX is greater then the estimate (or -1 | |
009b318f | 85 | means infinity). Corresponding ALG is used then. |
ab608690 | 86 | For example initializer: |
009b318f | 87 | {{256, loop}, {-1, rep_prefix_4_byte}} |
ab608690 | 88 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
0bbe9142 | 89 | be used otherwise. */ |
ab608690 | 90 | struct stringop_algs |
91 | { | |
92 | const enum stringop_alg unknown_size; | |
93 | const struct stringop_strategy { | |
94 | const int max; | |
95 | const enum stringop_alg alg; | |
96 | } size [NAX_STRINGOP_ALGS]; | |
97 | }; | |
98 | ||
9af5c5d1 | 99 | /* Define the specific costs for a given cpu */ |
100 | ||
101 | struct processor_costs { | |
e99c3a1d | 102 | const int add; /* cost of an add instruction */ |
103 | const int lea; /* cost of a lea instruction */ | |
104 | const int shift_var; /* variable shift costs */ | |
105 | const int shift_const; /* constant shift costs */ | |
9e7454d0 | 106 | const int mult_init[5]; /* cost of starting a multiply |
805e22b2 | 107 | in QImode, HImode, SImode, DImode, TImode*/ |
e99c3a1d | 108 | const int mult_bit; /* cost of multiply per each bit set */ |
9e7454d0 | 109 | const int divide[5]; /* cost of a divide/mod |
805e22b2 | 110 | in QImode, HImode, SImode, DImode, TImode*/ |
78ac78d9 | 111 | int movsx; /* The cost of movsx operation. */ |
112 | int movzx; /* The cost of movzx operation. */ | |
e99c3a1d | 113 | const int large_insn; /* insns larger than this cost more */ |
114 | const int move_ratio; /* The threshold of number of scalar | |
b8e3cf86 | 115 | memory-to-memory move insns. */ |
e99c3a1d | 116 | const int movzbl_load; /* cost of loading using movzbl */ |
117 | const int int_load[3]; /* cost of loading integer registers | |
3ab61a4d | 118 | in QImode, HImode and SImode relative |
119 | to reg-reg move (2). */ | |
e99c3a1d | 120 | const int int_store[3]; /* cost of storing integer register |
3ab61a4d | 121 | in QImode, HImode and SImode */ |
e99c3a1d | 122 | const int fp_move; /* cost of reg,reg fld/fst */ |
123 | const int fp_load[3]; /* cost of loading FP register | |
3ab61a4d | 124 | in SFmode, DFmode and XFmode */ |
e99c3a1d | 125 | const int fp_store[3]; /* cost of storing FP register |
3ab61a4d | 126 | in SFmode, DFmode and XFmode */ |
e99c3a1d | 127 | const int mmx_move; /* cost of moving MMX register. */ |
128 | const int mmx_load[2]; /* cost of loading MMX register | |
4f3e5c20 | 129 | in SImode and DImode */ |
e99c3a1d | 130 | const int mmx_store[2]; /* cost of storing MMX register |
4f3e5c20 | 131 | in SImode and DImode */ |
e99c3a1d | 132 | const int sse_move; /* cost of moving SSE register. */ |
133 | const int sse_load[3]; /* cost of loading SSE register | |
4f3e5c20 | 134 | in SImode, DImode and TImode*/ |
e99c3a1d | 135 | const int sse_store[3]; /* cost of storing SSE register |
4f3e5c20 | 136 | in SImode, DImode and TImode*/ |
e99c3a1d | 137 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
4f3e5c20 | 138 | integer and vice versa. */ |
0c916a7b | 139 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
140 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
afa6d980 | 141 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
142 | const int simultaneous_prefetches; /* number of parallel prefetch | |
143 | operations. */ | |
805e22b2 | 144 | const int branch_cost; /* Default value for BRANCH_COST. */ |
b80ce4a8 | 145 | const int fadd; /* cost of FADD and FSUB instructions. */ |
146 | const int fmul; /* cost of FMUL instruction. */ | |
147 | const int fdiv; /* cost of FDIV instruction. */ | |
148 | const int fabs; /* cost of FABS instruction. */ | |
149 | const int fchs; /* cost of FCHS instruction. */ | |
150 | const int fsqrt; /* cost of FSQRT instruction. */ | |
ab608690 | 151 | /* Specify what algorithm |
152 | to use for stringops on unknown size. */ | |
153 | struct stringop_algs memcpy[2], memset[2]; | |
6202d4db | 154 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
155 | load and store. */ | |
156 | const int scalar_load_cost; /* Cost of scalar load. */ | |
157 | const int scalar_store_cost; /* Cost of scalar store. */ | |
158 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
159 | load, store, vector-to-scalar and | |
160 | scalar-to-vector operation. */ | |
161 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
162 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
009b318f | 163 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
6202d4db | 164 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
165 | const int vec_store_cost; /* Cost of vector store. */ | |
166 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
167 | cost model. */ | |
168 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
169 | vectorizer cost model. */ | |
9af5c5d1 | 170 | }; |
171 | ||
e99c3a1d | 172 | extern const struct processor_costs *ix86_cost; |
f08b701c | 173 | extern const struct processor_costs ix86_size_cost; |
174 | ||
175 | #define ix86_cur_cost() \ | |
176 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
9af5c5d1 | 177 | |
43b83681 | 178 | /* Macros used in the machine description to test the flags. */ |
179 | ||
01cc3b75 | 180 | /* configure can arrange to make this 2, to force a 486. */ |
ce71a9e6 | 181 | |
f0c53df0 | 182 | #ifndef TARGET_CPU_DEFAULT |
9db3d688 | 183 | #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic |
028f8cc7 | 184 | #endif |
f0c53df0 | 185 | |
e3f17334 | 186 | #ifndef TARGET_FPMATH_DEFAULT |
187 | #define TARGET_FPMATH_DEFAULT \ | |
188 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
189 | #endif | |
190 | ||
0c44645a | 191 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
bfa936ad | 192 | |
54113cf5 | 193 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
194 | compile-time constant. */ | |
195 | #ifdef IN_LIBGCC2 | |
0c44645a | 196 | #undef TARGET_64BIT |
54113cf5 | 197 | #ifdef __x86_64__ |
198 | #define TARGET_64BIT 1 | |
199 | #else | |
200 | #define TARGET_64BIT 0 | |
201 | #endif | |
202 | #else | |
0c44645a | 203 | #ifndef TARGET_BI_ARCH |
204 | #undef TARGET_64BIT | |
76b5af68 | 205 | #if TARGET_64BIT_DEFAULT |
6c52fa55 | 206 | #define TARGET_64BIT 1 |
207 | #else | |
208 | #define TARGET_64BIT 0 | |
209 | #endif | |
210 | #endif | |
54113cf5 | 211 | #endif |
bacf1c2a | 212 | |
4f18499c | 213 | #define HAS_LONG_COND_BRANCH 1 |
214 | #define HAS_LONG_UNCOND_BRANCH 1 | |
215 | ||
706b598d | 216 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
217 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
218 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
219 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
5c34451e | 220 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
706b598d | 221 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
222 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
223 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
224 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
805e22b2 | 225 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
0fda5f41 | 226 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
11361ecb | 227 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
9db3d688 | 228 | #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) |
229 | #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
230 | #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
3d775f8e | 231 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
f3e2ae00 | 232 | |
e9f301ea | 233 | /* Feature tests against the various tunings. */ |
234 | enum ix86_tune_indices { | |
235 | X86_TUNE_USE_LEAVE, | |
236 | X86_TUNE_PUSH_MEMORY, | |
237 | X86_TUNE_ZERO_EXTEND_WITH_AND, | |
238 | X86_TUNE_USE_BIT_TEST, | |
239 | X86_TUNE_UNROLL_STRLEN, | |
240 | X86_TUNE_DEEP_BRANCH_PREDICTION, | |
241 | X86_TUNE_BRANCH_PREDICTION_HINTS, | |
242 | X86_TUNE_DOUBLE_WITH_ADD, | |
4d9301a8 | 243 | X86_TUNE_USE_SAHF, |
e9f301ea | 244 | X86_TUNE_MOVX, |
245 | X86_TUNE_PARTIAL_REG_STALL, | |
246 | X86_TUNE_PARTIAL_FLAG_REG_STALL, | |
247 | X86_TUNE_USE_HIMODE_FIOP, | |
248 | X86_TUNE_USE_SIMODE_FIOP, | |
249 | X86_TUNE_USE_MOV0, | |
250 | X86_TUNE_USE_CLTD, | |
251 | X86_TUNE_USE_XCHGB, | |
252 | X86_TUNE_SPLIT_LONG_MOVES, | |
253 | X86_TUNE_READ_MODIFY_WRITE, | |
254 | X86_TUNE_READ_MODIFY, | |
255 | X86_TUNE_PROMOTE_QIMODE, | |
256 | X86_TUNE_FAST_PREFIX, | |
257 | X86_TUNE_SINGLE_STRINGOP, | |
258 | X86_TUNE_QIMODE_MATH, | |
259 | X86_TUNE_HIMODE_MATH, | |
260 | X86_TUNE_PROMOTE_QI_REGS, | |
261 | X86_TUNE_PROMOTE_HI_REGS, | |
262 | X86_TUNE_ADD_ESP_4, | |
263 | X86_TUNE_ADD_ESP_8, | |
264 | X86_TUNE_SUB_ESP_4, | |
265 | X86_TUNE_SUB_ESP_8, | |
266 | X86_TUNE_INTEGER_DFMODE_MOVES, | |
267 | X86_TUNE_PARTIAL_REG_DEPENDENCY, | |
268 | X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, | |
269 | X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, | |
270 | X86_TUNE_SSE_SPLIT_REGS, | |
271 | X86_TUNE_SSE_TYPELESS_STORES, | |
272 | X86_TUNE_SSE_LOAD0_BY_PXOR, | |
273 | X86_TUNE_MEMORY_MISMATCH_STALL, | |
274 | X86_TUNE_PROLOGUE_USING_MOVE, | |
275 | X86_TUNE_EPILOGUE_USING_MOVE, | |
276 | X86_TUNE_SHIFT1, | |
277 | X86_TUNE_USE_FFREEP, | |
278 | X86_TUNE_INTER_UNIT_MOVES, | |
ff1f087e | 279 | X86_TUNE_INTER_UNIT_CONVERSIONS, |
e9f301ea | 280 | X86_TUNE_FOUR_JUMP_LIMIT, |
281 | X86_TUNE_SCHEDULE, | |
282 | X86_TUNE_USE_BT, | |
283 | X86_TUNE_USE_INCDEC, | |
284 | X86_TUNE_PAD_RETURNS, | |
285 | X86_TUNE_EXT_80387_CONSTANTS, | |
c6f562ed | 286 | X86_TUNE_SHORTEN_X87_SSE, |
287 | X86_TUNE_AVOID_VECTOR_DECODE, | |
58c9a086 | 288 | X86_TUNE_PROMOTE_HIMODE_IMUL, |
c6f562ed | 289 | X86_TUNE_SLOW_IMUL_IMM32_MEM, |
290 | X86_TUNE_SLOW_IMUL_IMM8, | |
291 | X86_TUNE_MOVE_M1_VIA_OR, | |
292 | X86_TUNE_NOT_UNPAIRABLE, | |
293 | X86_TUNE_NOT_VECTORMODE, | |
650269ca | 294 | X86_TUNE_USE_VECTOR_CONVERTS, |
7d709e5f | 295 | X86_TUNE_FUSE_CMP_AND_BRANCH, |
e9f301ea | 296 | |
297 | X86_TUNE_LAST | |
298 | }; | |
299 | ||
46f8e3b0 | 300 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
e9f301ea | 301 | |
302 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
303 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
304 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
305 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
306 | #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST] | |
307 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] | |
308 | #define TARGET_DEEP_BRANCH_PREDICTION \ | |
309 | ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] | |
310 | #define TARGET_BRANCH_PREDICTION_HINTS \ | |
311 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
312 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
313 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
314 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
315 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
316 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
317 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
318 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] | |
319 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
320 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
321 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
322 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
323 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
324 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
325 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
326 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
327 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
328 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
329 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] | |
330 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
331 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
332 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
333 | #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] | |
334 | #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] | |
335 | #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] | |
336 | #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] | |
337 | #define TARGET_INTEGER_DFMODE_MOVES \ | |
338 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
339 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
340 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
341 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
342 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
343 | #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ | |
344 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] | |
345 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] | |
346 | #define TARGET_SSE_TYPELESS_STORES \ | |
347 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
348 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
349 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
350 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
351 | #define TARGET_PROLOGUE_USING_MOVE \ | |
352 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
353 | #define TARGET_EPILOGUE_USING_MOVE \ | |
354 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
355 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
356 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
357 | #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] | |
ff1f087e | 358 | #define TARGET_INTER_UNIT_CONVERSIONS\ |
359 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] | |
e9f301ea | 360 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
361 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
362 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
363 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
364 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
365 | #define TARGET_EXT_80387_CONSTANTS \ | |
366 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
c6f562ed | 367 | #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] |
368 | #define TARGET_AVOID_VECTOR_DECODE \ | |
369 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
58c9a086 | 370 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
371 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
c6f562ed | 372 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
373 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
374 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
375 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
376 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
377 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
7d709e5f | 378 | #define TARGET_USE_VECTOR_CONVERTS \ |
379 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
380 | #define TARGET_FUSE_CMP_AND_BRANCH \ | |
381 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] | |
e9f301ea | 382 | |
383 | /* Feature tests against the various architecture variations. */ | |
384 | enum ix86_arch_indices { | |
385 | X86_ARCH_CMOVE, /* || TARGET_SSE */ | |
386 | X86_ARCH_CMPXCHG, | |
387 | X86_ARCH_CMPXCHG8B, | |
388 | X86_ARCH_XADD, | |
389 | X86_ARCH_BSWAP, | |
390 | ||
391 | X86_ARCH_LAST | |
392 | }; | |
009b318f | 393 | |
46f8e3b0 | 394 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
e9f301ea | 395 | |
396 | #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE] | |
397 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] | |
398 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
399 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
400 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
401 | ||
402 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) | |
403 | ||
404 | extern int x86_prefetch_sse; | |
e44348b5 | 405 | |
e9f301ea | 406 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
407 | ||
e9f301ea | 408 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
409 | ||
410 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
411 | #define TARGET_MIX_SSE_I387 \ | |
412 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
413 | ||
414 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
415 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
416 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
417 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
0f0a601a | 418 | |
e44348b5 | 419 | extern int ix86_isa_flags; |
420 | ||
76b5af68 | 421 | #ifndef TARGET_64BIT_DEFAULT |
422 | #define TARGET_64BIT_DEFAULT 0 | |
bacf1c2a | 423 | #endif |
a3a49880 | 424 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
425 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
426 | #endif | |
bacf1c2a | 427 | |
5b5037b3 | 428 | /* Fence to use after loop using storent. */ |
429 | ||
430 | extern tree x86_mfence; | |
431 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
432 | ||
39d31f69 | 433 | /* Once GDB has been enhanced to deal with functions without frame |
434 | pointers, we can change this to allow for elimination of | |
435 | the frame pointer in leaf functions. */ | |
436 | #define TARGET_DEFAULT 0 | |
76b5af68 | 437 | |
e44348b5 | 438 | /* Extra bits to force. */ |
439 | #define TARGET_SUBTARGET_DEFAULT 0 | |
440 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
441 | ||
442 | /* Extra bits to force on w/ 32-bit mode. */ | |
443 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
444 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
445 | ||
0bbe9142 | 446 | /* Extra bits to force on w/ 64-bit mode. */ |
447 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
e44348b5 | 448 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
0bbe9142 | 449 | |
ffd05090 | 450 | /* This is not really a target flag, but is done this way so that |
451 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
452 | redefines this to 1. */ | |
453 | #define TARGET_MACHO 0 | |
454 | ||
0bbe9142 | 455 | /* Likewise, for the Windows 64-bit ABI. */ |
d3feb168 | 456 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
457 | ||
458 | /* Available call abi. */ | |
5f57a8b1 | 459 | enum calling_abi |
d3feb168 | 460 | { |
461 | SYSV_ABI = 0, | |
462 | MS_ABI = 1 | |
463 | }; | |
464 | ||
465 | /* The default abi form used by target. */ | |
466 | #define DEFAULT_ABI SYSV_ABI | |
0bbe9142 | 467 | |
b2a566d1 | 468 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
469 | with the rounding mode forced to 53 bits. */ | |
470 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
471 | ||
0bf9a70a | 472 | /* Sometimes certain combinations of command options do not make |
473 | sense on a particular target machine. You can define a macro | |
474 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
475 | defined, is executed once just after all the command options have | |
476 | been parsed. | |
477 | ||
478 | Don't use this macro to turn on various extra optimizations for | |
479 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
480 | ||
46f8e3b0 | 481 | #define OVERRIDE_OPTIONS override_options (true) |
0bf9a70a | 482 | |
9af5c5d1 | 483 | /* Define this to change the optimizations performed by default. */ |
1b12cfd7 | 484 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
485 | optimization_options ((LEVEL), (SIZE)) | |
9af5c5d1 | 486 | |
852c5acb | 487 | /* -march=native handling only makes sense with compiler running on |
488 | an x86 or x86_64 chip. If changing this condition, also change | |
489 | the condition in driver-i386.c. */ | |
490 | #if defined(__i386__) || defined(__x86_64__) | |
4009b53f | 491 | /* In driver-i386.c. */ |
492 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
493 | #define EXTRA_SPEC_FUNCTIONS \ | |
494 | { "local_cpu_detect", host_detect_local_cpu }, | |
852c5acb | 495 | #define HAVE_LOCAL_CPU_DETECT |
4009b53f | 496 | #endif |
497 | ||
f067c6b7 | 498 | #if TARGET_64BIT_DEFAULT |
499 | #define OPT_ARCH64 "!m32" | |
500 | #define OPT_ARCH32 "m32" | |
501 | #else | |
502 | #define OPT_ARCH64 "m64" | |
503 | #define OPT_ARCH32 "!m64" | |
504 | #endif | |
505 | ||
3e883b09 | 506 | /* Support for configure-time defaults of some command line options. |
507 | The order here is important so that -march doesn't squash the | |
508 | tune or cpu values. */ | |
c300d1d8 | 509 | #define OPTION_DEFAULT_SPECS \ |
173ac007 | 510 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
f067c6b7 | 511 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
512 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
c300d1d8 | 513 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
f067c6b7 | 514 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
515 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
516 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
517 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
518 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7dd97ab6 | 519 | |
8fad0667 | 520 | /* Specs for the compiler proper */ |
521 | ||
d17e16d2 | 522 | #ifndef CC1_CPU_SPEC |
4009b53f | 523 | #define CC1_CPU_SPEC_1 "\ |
47a66cd7 | 524 | %{mcpu=*:-mtune=%* \ |
c2d4d40a | 525 | %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ |
47a66cd7 | 526 | %<mcpu=* \ |
25b31391 | 527 | %{mintel-syntax:-masm=intel \ |
528 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
529 | %{mno-intel-syntax:-masm=att \ | |
530 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
4009b53f | 531 | |
852c5acb | 532 | #ifndef HAVE_LOCAL_CPU_DETECT |
4009b53f | 533 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
534 | #else | |
535 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
10e818c2 | 536 | "%{march=native:%<march=native %:local_cpu_detect(arch) \ |
537 | %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ | |
4009b53f | 538 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" |
539 | #endif | |
8fad0667 | 540 | #endif |
43b83681 | 541 | \f |
7dbd6483 | 542 | /* Target CPU builtins. */ |
46f8e3b0 | 543 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
544 | ||
545 | /* Target Pragmas. */ | |
546 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
7dbd6483 | 547 | |
2dd515a3 | 548 | enum target_cpu_default |
549 | { | |
550 | TARGET_CPU_DEFAULT_generic = 0, | |
551 | ||
552 | TARGET_CPU_DEFAULT_i386, | |
553 | TARGET_CPU_DEFAULT_i486, | |
554 | TARGET_CPU_DEFAULT_pentium, | |
555 | TARGET_CPU_DEFAULT_pentium_mmx, | |
556 | TARGET_CPU_DEFAULT_pentiumpro, | |
557 | TARGET_CPU_DEFAULT_pentium2, | |
558 | TARGET_CPU_DEFAULT_pentium3, | |
559 | TARGET_CPU_DEFAULT_pentium4, | |
560 | TARGET_CPU_DEFAULT_pentium_m, | |
561 | TARGET_CPU_DEFAULT_prescott, | |
562 | TARGET_CPU_DEFAULT_nocona, | |
563 | TARGET_CPU_DEFAULT_core2, | |
564 | ||
565 | TARGET_CPU_DEFAULT_geode, | |
566 | TARGET_CPU_DEFAULT_k6, | |
567 | TARGET_CPU_DEFAULT_k6_2, | |
568 | TARGET_CPU_DEFAULT_k6_3, | |
569 | TARGET_CPU_DEFAULT_athlon, | |
570 | TARGET_CPU_DEFAULT_athlon_sse, | |
571 | TARGET_CPU_DEFAULT_k8, | |
572 | TARGET_CPU_DEFAULT_amdfam10, | |
573 | ||
574 | TARGET_CPU_DEFAULT_max | |
575 | }; | |
6c52fa55 | 576 | |
d17e16d2 | 577 | #ifndef CC1_SPEC |
18870143 | 578 | #define CC1_SPEC "%(cc1_cpu) " |
d17e16d2 | 579 | #endif |
580 | ||
581 | /* This macro defines names of additional specifications to put in the | |
582 | specs that can be used in various specifications like CC1_SPEC. Its | |
583 | definition is an initializer with a subgrouping for each command option. | |
2bc9393a | 584 | |
585 | Each subgrouping contains a string constant, that defines the | |
7d9ae20a | 586 | specification name, and a string constant that used by the GCC driver |
2bc9393a | 587 | program. |
588 | ||
589 | Do not define this macro if it does not need to do anything. */ | |
590 | ||
591 | #ifndef SUBTARGET_EXTRA_SPECS | |
592 | #define SUBTARGET_EXTRA_SPECS | |
593 | #endif | |
594 | ||
595 | #define EXTRA_SPECS \ | |
d17e16d2 | 596 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
2bc9393a | 597 | SUBTARGET_EXTRA_SPECS |
598 | \f | |
c300d1d8 | 599 | |
f3dde807 | 600 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
601 | FPU, assume that the fpcw is set to extended precision; when using | |
602 | only SSE, rounding is correct; when using both SSE and the FPU, | |
603 | the rounding precision is indeterminate, since either may be chosen | |
604 | apparently at random. */ | |
605 | #define TARGET_FLT_EVAL_METHOD \ | |
d5c660fd | 606 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0898f59e | 607 | |
46de89e7 | 608 | /* target machine storage layout */ |
609 | ||
c7f5f345 | 610 | #define SHORT_TYPE_SIZE 16 |
611 | #define INT_TYPE_SIZE 32 | |
612 | #define FLOAT_TYPE_SIZE 32 | |
613 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
c7f5f345 | 614 | #define DOUBLE_TYPE_SIZE 64 |
615 | #define LONG_LONG_TYPE_SIZE 64 | |
46de89e7 | 616 | #define LONG_DOUBLE_TYPE_SIZE 80 |
617 | ||
618 | #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE | |
c7f5f345 | 619 | |
76b5af68 | 620 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
6c52fa55 | 621 | #define MAX_BITS_PER_WORD 64 |
6c52fa55 | 622 | #else |
623 | #define MAX_BITS_PER_WORD 32 | |
6c52fa55 | 624 | #endif |
625 | ||
43b83681 | 626 | /* Define this if most significant byte of a word is the lowest numbered. */ |
627 | /* That is true on the 80386. */ | |
628 | ||
629 | #define BITS_BIG_ENDIAN 0 | |
630 | ||
631 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
632 | /* That is not true on the 80386. */ | |
633 | #define BYTES_BIG_ENDIAN 0 | |
634 | ||
635 | /* Define this if most significant word of a multiword number is the lowest | |
636 | numbered. */ | |
637 | /* Not true for 80386 */ | |
638 | #define WORDS_BIG_ENDIAN 0 | |
639 | ||
43b83681 | 640 | /* Width of a word, in units (bytes). */ |
c7f5f345 | 641 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
52cb7411 | 642 | #ifdef IN_LIBGCC2 |
643 | #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
644 | #else | |
645 | #define MIN_UNITS_PER_WORD 4 | |
646 | #endif | |
43b83681 | 647 | |
43b83681 | 648 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
c7f5f345 | 649 | #define PARM_BOUNDARY BITS_PER_WORD |
43b83681 | 650 | |
ce71a9e6 | 651 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
d3feb168 | 652 | #define STACK_BOUNDARY (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 \ |
653 | : BITS_PER_WORD) | |
43b83681 | 654 | |
27a7a23a | 655 | /* Stack boundary of the main function guaranteed by OS. */ |
656 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
657 | ||
0de6a16a | 658 | /* Minimum stack boundary. */ |
659 | #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
27a7a23a | 660 | |
fcbfedc7 | 661 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
bc0eb8c6 | 662 | aligned; the compiler cannot rely on having this alignment. */ |
ce71a9e6 | 663 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
88451936 | 664 | |
0de6a16a | 665 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
27a7a23a | 666 | both 32bit and 64bit, to support codes that need 128 bit stack |
667 | alignment for SSE instructions, but can't realign the stack. */ | |
668 | #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 | |
669 | ||
670 | /* 1 if -mstackrealign should be turned on by default. It will | |
671 | generate an alternate prologue and epilogue that realigns the | |
672 | runtime stack if nessary. This supports mixing codes that keep a | |
673 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
674 | need a 16-byte aligned stack, as required by SSE instructions. If | |
675 | STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is | |
676 | 128, stacks for all functions may be realigned. */ | |
677 | #define STACK_REALIGN_DEFAULT 0 | |
678 | ||
679 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
680 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
3ca5a306 | 681 | |
751bdb92 | 682 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
683 | mandatory for the 64-bit ABI, and may or may not be true for other | |
684 | operating systems. */ | |
685 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
686 | ||
fc5cb4c0 | 687 | /* Minimum allocation boundary for the code of a function. */ |
688 | #define FUNCTION_BOUNDARY 8 | |
689 | ||
690 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
691 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
43b83681 | 692 | |
bb441676 | 693 | /* Alignment of field after `int : 0' in a structure. */ |
43b83681 | 694 | |
c7f5f345 | 695 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
43b83681 | 696 | |
697 | /* Minimum size in bits of the largest boundary to which any | |
698 | and all fundamental data types supported by the hardware | |
699 | might need to be aligned. No data type wants to be aligned | |
4e17b634 | 700 | rounder than this. |
d4983fea | 701 | |
fcbfedc7 | 702 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
4e17b634 | 703 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
704 | ||
705 | #define BIGGEST_ALIGNMENT 128 | |
706 | ||
27a7a23a | 707 | /* Maximum stack alignment. */ |
708 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
709 | ||
2feb8eca | 710 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
f01b0085 | 711 | #define ALIGN_MODE_128(MODE) \ |
c4e709d6 | 712 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
f01b0085 | 713 | |
4e17b634 | 714 | /* The published ABIs say that doubles should be aligned on word |
fcbfedc7 | 715 | boundaries, so lower the alignment for structure fields unless |
040f791a | 716 | -malign-double is set. */ |
bd0f3c40 | 717 | |
6e5d72bd | 718 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
719 | supports no vector modes, cut out the complexity and fall back | |
720 | on BIGGEST_FIELD_ALIGNMENT. */ | |
721 | #ifdef IN_TARGET_LIBS | |
aa867d91 | 722 | #ifdef __x86_64__ |
723 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
724 | #else | |
6e5d72bd | 725 | #define BIGGEST_FIELD_ALIGNMENT 32 |
aa867d91 | 726 | #endif |
6e5d72bd | 727 | #else |
bd0f3c40 | 728 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
729 | x86_field_alignment (FIELD, COMPUTED) | |
6e5d72bd | 730 | #endif |
43b83681 | 731 | |
f7d6703c | 732 | /* If defined, a C expression to compute the alignment given to a |
f01b0085 | 733 | constant that is being placed in memory. EXP is the constant |
f7d6703c | 734 | and ALIGN is the alignment that the object would ordinarily have. |
735 | The value of this macro is used instead of that alignment to align | |
736 | the object. | |
737 | ||
738 | If this macro is not defined, then ALIGN is used. | |
739 | ||
740 | The typical use of this macro is to increase alignment for string | |
741 | constants to be word aligned so that `strcpy' calls that copy | |
742 | constants can be done inline. */ | |
743 | ||
1b12cfd7 | 744 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
9af5c5d1 | 745 | |
ed45e834 | 746 | /* If defined, a C expression to compute the alignment for a static |
747 | variable. TYPE is the data type, and ALIGN is the alignment that | |
748 | the object would ordinarily have. The value of this macro is used | |
749 | instead of that alignment to align the object. | |
750 | ||
751 | If this macro is not defined, then ALIGN is used. | |
752 | ||
753 | One use of this macro is to increase alignment of medium-size | |
754 | data to make it all fit in fewer cache lines. Another is to | |
755 | cause character arrays to be word-aligned so that `strcpy' calls | |
756 | that copy constants to character arrays can be done inline. */ | |
757 | ||
1b12cfd7 | 758 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
9bd87fd2 | 759 | |
760 | /* If defined, a C expression to compute the alignment for a local | |
761 | variable. TYPE is the data type, and ALIGN is the alignment that | |
762 | the object would ordinarily have. The value of this macro is used | |
763 | instead of that alignment to align the object. | |
764 | ||
765 | If this macro is not defined, then ALIGN is used. | |
766 | ||
767 | One use of this macro is to increase alignment of medium-size | |
768 | data to make it all fit in fewer cache lines. */ | |
769 | ||
ad33891d | 770 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
771 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
772 | ||
773 | /* If defined, a C expression to compute the alignment for stack slot. | |
774 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
775 | is the alignment that the slot would ordinarily have. The value of | |
776 | this macro is used instead of that alignment to align the slot. | |
777 | ||
778 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
779 | Otherwise, LOCAL_ALIGNMENT will be used. | |
780 | ||
781 | One use of this macro is to set alignment of stack slot to the | |
782 | maximum alignment of all possible modes which the slot may have. */ | |
783 | ||
784 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
785 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
ed45e834 | 786 | |
e4bf866d | 787 | /* If defined, a C expression that gives the alignment boundary, in |
788 | bits, of an argument with the specified mode and type. If it is | |
789 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
790 | ||
1b12cfd7 | 791 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
792 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
e4bf866d | 793 | |
c46dc351 | 794 | /* Set this nonzero if move instructions will actually fail to work |
43b83681 | 795 | when given unaligned data. */ |
bdf74c8a | 796 | #define STRICT_ALIGNMENT 0 |
43b83681 | 797 | |
798 | /* If bit field type is int, don't let it cross an int, | |
799 | and give entire struct the alignment of an int. */ | |
ceb2fe0f | 800 | /* Required on the 386 since it doesn't have bit-field insns. */ |
43b83681 | 801 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
43b83681 | 802 | \f |
803 | /* Standard register usage. */ | |
804 | ||
805 | /* This processor has special stack-like registers. See reg-stack.c | |
bb441676 | 806 | for details. */ |
43b83681 | 807 | |
808 | #define STACK_REGS | |
c300d1d8 | 809 | |
1b12cfd7 | 810 | #define IS_STACK_MODE(MODE) \ |
897f76b2 | 811 | (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ |
812 | || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ | |
813 | || (MODE) == XFmode) | |
43b83681 | 814 | |
815 | /* Number of actual hardware registers. | |
816 | The hardware registers are assigned numbers for the compiler | |
817 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
818 | All registers that the compiler knows about must be given numbers, | |
819 | even those that are not normally considered general registers. | |
820 | ||
821 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
822 | We number the floating point registers 8-15. | |
823 | Note that registers 0-7 can be accessed as a short or int, | |
824 | while only 0-3 may be used with byte `mov' instructions. | |
825 | ||
826 | Reg 16 does not correspond to any hardware register, but instead | |
827 | appears in the RTL as an argument pointer prior to reload, and is | |
828 | eliminated during reloading in favor of either the stack or frame | |
bb441676 | 829 | pointer. */ |
43b83681 | 830 | |
0a9ae7b1 | 831 | #define FIRST_PSEUDO_REGISTER 53 |
43b83681 | 832 | |
55de61ac | 833 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
834 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
835 | ||
836 | #define DWARF_FRAME_REGISTERS 17 | |
837 | ||
43b83681 | 838 | /* 1 for registers that have pervasive standard uses |
839 | and are not available for the register allocator. | |
c6d93f09 | 840 | On the 80386, the stack pointer is such, as is the arg pointer. |
d4983fea | 841 | |
78d46568 | 842 | The value is zero if the register is not fixed on either 32 or |
843 | 64 bit targets, one if the register if fixed on both 32 and 64 | |
844 | bit targets, two if it is only fixed on 32bit targets and three | |
845 | if its only fixed on 64bit targets. | |
846 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
c6d93f09 | 847 | */ |
f01b0085 | 848 | #define FIXED_REGISTERS \ |
849 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
78d46568 | 850 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
0a9ae7b1 | 851 | /*arg,flags,fpsr,fpcr,frame*/ \ |
852 | 1, 1, 1, 1, 1, \ | |
f01b0085 | 853 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
854 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
855 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ | |
c6d93f09 | 856 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
857 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
78d46568 | 858 | 2, 2, 2, 2, 2, 2, 2, 2, \ |
c6d93f09 | 859 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
c300d1d8 | 860 | 2, 2, 2, 2, 2, 2, 2, 2 } |
d4983fea | 861 | |
43b83681 | 862 | |
863 | /* 1 for registers not available across function calls. | |
864 | These must include the FIXED_REGISTERS and also any | |
865 | registers that can be used without being saved. | |
866 | The latter must include the registers where values are returned | |
867 | and the register where structure-value addresses are passed. | |
d4983fea | 868 | Aside from that, you can include as many other registers as you like. |
869 | ||
abf198ab | 870 | The value is zero if the register is not call used on either 32 or |
871 | 64 bit targets, one if the register if call used on both 32 and 64 | |
872 | bit targets, two if it is only call used on 32bit targets and three | |
873 | if its only call used on 64bit targets. | |
78d46568 | 874 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. |
c6d93f09 | 875 | */ |
f01b0085 | 876 | #define CALL_USED_REGISTERS \ |
877 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
78d46568 | 878 | { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
0a9ae7b1 | 879 | /*arg,flags,fpsr,fpcr,frame*/ \ |
880 | 1, 1, 1, 1, 1, \ | |
f01b0085 | 881 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
d1918706 | 882 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
f01b0085 | 883 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ |
78d46568 | 884 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
c6d93f09 | 885 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
78d46568 | 886 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
c6d93f09 | 887 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
c300d1d8 | 888 | 1, 1, 1, 1, 1, 1, 1, 1 } |
43b83681 | 889 | |
60206704 | 890 | /* Order in which to allocate registers. Each register must be |
891 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
892 | late and fixed registers last. Note that, in general, we prefer | |
893 | registers listed in CALL_USED_REGISTERS, keeping the others | |
894 | available for storage of persistent values. | |
895 | ||
717db2f5 | 896 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
897 | so this is just empty initializer for array. */ | |
60206704 | 898 | |
717db2f5 | 899 | #define REG_ALLOC_ORDER \ |
900 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
901 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
902 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
0a9ae7b1 | 903 | 48, 49, 50, 51, 52 } |
60206704 | 904 | |
717db2f5 | 905 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
906 | to be rearranged based on a particular function. When using sse math, | |
d1918706 | 907 | we want to allocate SSE before x87 registers and vice versa. */ |
60206704 | 908 | |
717db2f5 | 909 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
60206704 | 910 | |
0bf9a70a | 911 | |
d3feb168 | 912 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
913 | ||
43b83681 | 914 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
f01b0085 | 915 | #define CONDITIONAL_REGISTER_USAGE \ |
1b12cfd7 | 916 | do { \ |
c6d93f09 | 917 | int i; \ |
ae451f6e | 918 | unsigned int j; \ |
c6d93f09 | 919 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
920 | { \ | |
78d46568 | 921 | if (fixed_regs[i] > 1) \ |
922 | fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ | |
923 | if (call_used_regs[i] > 1) \ | |
924 | call_used_regs[i] = (call_used_regs[i] \ | |
925 | == (TARGET_64BIT ? 3 : 2)); \ | |
c6d93f09 | 926 | } \ |
ae451f6e | 927 | j = PIC_OFFSET_TABLE_REGNUM; \ |
9f525417 | 928 | if (j != INVALID_REGNUM) \ |
f01b0085 | 929 | { \ |
9f525417 | 930 | fixed_regs[j] = 1; \ |
931 | call_used_regs[j] = 1; \ | |
f01b0085 | 932 | } \ |
933 | if (! TARGET_MMX) \ | |
934 | { \ | |
935 | int i; \ | |
936 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
937 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
6ee52ba2 | 938 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
f01b0085 | 939 | } \ |
940 | if (! TARGET_SSE) \ | |
941 | { \ | |
942 | int i; \ | |
943 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
944 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
6ee52ba2 | 945 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
f01b0085 | 946 | } \ |
947 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ | |
948 | { \ | |
949 | int i; \ | |
950 | HARD_REG_SET x; \ | |
951 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
952 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
953 | if (TEST_HARD_REG_BIT (x, i)) \ | |
6ee52ba2 | 954 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
955 | } \ | |
956 | if (! TARGET_64BIT) \ | |
957 | { \ | |
958 | int i; \ | |
959 | for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ | |
960 | reg_names[i] = ""; \ | |
961 | for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ | |
962 | reg_names[i] = ""; \ | |
f01b0085 | 963 | } \ |
d3feb168 | 964 | if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) \ |
992aa3bc | 965 | { \ |
966 | call_used_regs[4 /*RSI*/] = 0; \ | |
967 | call_used_regs[5 /*RDI*/] = 0; \ | |
968 | } \ | |
1b12cfd7 | 969 | } while (0) |
43b83681 | 970 | |
971 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
972 | to hold something of mode MODE. | |
973 | This is ordinarily the length in words of a value of mode MODE | |
974 | but can be less for certain modes in special long registers. | |
975 | ||
d4983fea | 976 | Actually there are no two word move instructions for consecutive |
43b83681 | 977 | registers. And only registers 0-3 may have mov byte instructions |
978 | applied to them. | |
979 | */ | |
980 | ||
c300d1d8 | 981 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
699a9fea | 982 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
983 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
e07e720e | 984 | : ((MODE) == XFmode \ |
699a9fea | 985 | ? (TARGET_64BIT ? 2 : 3) \ |
e07e720e | 986 | : (MODE) == XCmode \ |
699a9fea | 987 | ? (TARGET_64BIT ? 4 : 6) \ |
0cd8258d | 988 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
43b83681 | 989 | |
695595bc | 990 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
991 | ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
992 | ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
993 | ? 0 \ | |
994 | : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
995 | : 0) | |
996 | ||
997 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
998 | ||
c300d1d8 | 999 | #define VALID_SSE2_REG_MODE(MODE) \ |
1000 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1001 | || (MODE) == V2DImode || (MODE) == DFmode) | |
b0556a84 | 1002 | |
1b12cfd7 | 1003 | #define VALID_SSE_REG_MODE(MODE) \ |
c300d1d8 | 1004 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ |
1005 | || (MODE) == SFmode || (MODE) == TFmode) | |
f01b0085 | 1006 | |
d5e0afe2 | 1007 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
c300d1d8 | 1008 | ((MODE) == V2SFmode || (MODE) == SFmode) |
d5e0afe2 | 1009 | |
1b12cfd7 | 1010 | #define VALID_MMX_REG_MODE(MODE) \ |
7916ca8a | 1011 | ((MODE == V1DImode) || (MODE) == DImode \ |
1012 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1013 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
f01b0085 | 1014 | |
0017aae3 | 1015 | /* ??? No autovectorization into MMX or 3DNOW until we can reliably |
1016 | place emms and femms instructions. */ | |
cbc9c660 | 1017 | #define UNITS_PER_SIMD_WORD(MODE) (TARGET_SSE ? 16 : UNITS_PER_WORD) |
697bc112 | 1018 | |
c300d1d8 | 1019 | #define VALID_DFP_MODE_P(MODE) \ |
1020 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
26042839 | 1021 | |
1b12cfd7 | 1022 | #define VALID_FP_MODE_P(MODE) \ |
c300d1d8 | 1023 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1024 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
0698f0cc | 1025 | |
1b12cfd7 | 1026 | #define VALID_INT_MODE_P(MODE) \ |
c300d1d8 | 1027 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1028 | || (MODE) == DImode \ | |
1029 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1030 | || (MODE) == CDImode \ | |
1031 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1032 | || (MODE) == TFmode || (MODE) == TCmode))) | |
0698f0cc | 1033 | |
2feb8eca | 1034 | /* Return true for modes passed in SSE registers. */ |
c300d1d8 | 1035 | #define SSE_REG_MODE_P(MODE) \ |
1036 | ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ | |
2feb8eca | 1037 | || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ |
1038 | || (MODE) == V4SFmode || (MODE) == V4SImode) | |
1039 | ||
ce71a9e6 | 1040 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
5dd8ee04 | 1041 | |
0698f0cc | 1042 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
1b12cfd7 | 1043 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
43b83681 | 1044 | |
1045 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1046 | when one has mode MODE1 and one has mode MODE2. | |
1047 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1048 | for any hard reg, then this must be 0 for correct output. */ | |
1049 | ||
deac3726 | 1050 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
2ede69f5 | 1051 | |
804e497b | 1052 | /* It is possible to write patterns to move flags; but until someone |
1053 | does it, */ | |
1054 | #define AVOID_CCMODE_COPIES | |
43b83681 | 1055 | |
ce71a9e6 | 1056 | /* Specify the modes required to caller save a given hard regno. |
301652e2 | 1057 | We do this on i386 to prevent flags from being saved at all. |
ce71a9e6 | 1058 | |
301652e2 | 1059 | Kill any attempts to combine saving of modes. */ |
1060 | ||
1b12cfd7 | 1061 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1062 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1063 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
c300d1d8 | 1064 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
1b12cfd7 | 1065 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ |
1066 | : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ | |
2ede69f5 | 1067 | : (MODE)) |
c300d1d8 | 1068 | |
43b83681 | 1069 | /* Specify the registers used for certain standard purposes. |
1070 | The values of these macros are register numbers. */ | |
1071 | ||
1072 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1073 | register. The ordinary mov instructions won't work */ | |
1074 | /* #define PC_REGNUM */ | |
1075 | ||
1076 | /* Register to use for pushing function arguments. */ | |
1077 | #define STACK_POINTER_REGNUM 7 | |
1078 | ||
1079 | /* Base register for access to local variables of the function. */ | |
8c5dc77f | 1080 | #define HARD_FRAME_POINTER_REGNUM 6 |
1081 | ||
1082 | /* Base register for access to local variables of the function. */ | |
0a9ae7b1 | 1083 | #define FRAME_POINTER_REGNUM 20 |
43b83681 | 1084 | |
1085 | /* First floating point reg */ | |
1086 | #define FIRST_FLOAT_REG 8 | |
1087 | ||
1088 | /* First & last stack-like regs */ | |
1089 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1090 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1091 | ||
f01b0085 | 1092 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1093 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
d4983fea | 1094 | |
f01b0085 | 1095 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
1096 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1097 | ||
c6d93f09 | 1098 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
1099 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1100 | ||
1101 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1102 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1103 | ||
43b83681 | 1104 | /* Value should be nonzero if functions must have frame pointers. |
1105 | Zero means the frame pointer need not be set up (and parms | |
1106 | may be accessed via the stack pointer) in functions that seem suitable. | |
1107 | This is computed in `reload', in reload1.c. */ | |
15b10465 | 1108 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
1109 | ||
06b27565 | 1110 | /* Override this in other tm.h files to cope with various OS lossage |
15b10465 | 1111 | requiring a frame pointer. */ |
1112 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1113 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1114 | #endif | |
1115 | ||
1116 | /* Make sure we can access arbitrary call frames. */ | |
1117 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
43b83681 | 1118 | |
1119 | /* Base register for access to arguments of the function. */ | |
1120 | #define ARG_POINTER_REGNUM 16 | |
1121 | ||
2ede69f5 | 1122 | /* Register in which static-chain is passed to a function. |
1123 | We do use ECX as static chain register for 32 bit ABI. On the | |
1124 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
ffc0b1ed | 1125 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG) |
43b83681 | 1126 | |
1127 | /* Register to hold the addressing base for position independent | |
df9f5cf8 | 1128 | code access to data items. We don't use PIC pointer for 64bit |
1129 | mode. Define the regnum to dummy value to prevent gcc from | |
d4983fea | 1130 | pessimizing code dealing with EBX. |
e3abf694 | 1131 | |
1132 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1133 | the pic register when possible. The change is visible after the | |
1134 | prologue has been emitted. */ | |
1135 | ||
27a7a23a | 1136 | #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG |
e3abf694 | 1137 | |
1138 | #define PIC_OFFSET_TABLE_REGNUM \ | |
43e4a084 | 1139 | ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ |
1140 | || !flag_pic ? INVALID_REGNUM \ | |
e3abf694 | 1141 | : reload_completed ? REGNO (pic_offset_table_rtx) \ |
1142 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
43b83681 | 1143 | |
c4797f24 | 1144 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1145 | ||
f52eff0c | 1146 | /* This is overridden by <cygwin.h>. */ |
32512c79 | 1147 | #define MS_AGGREGATE_RETURN 0 |
1148 | ||
634f7a13 | 1149 | /* This is overridden by <netware.h>. */ |
1150 | #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
43b83681 | 1151 | \f |
1152 | /* Define the classes of registers for register constraints in the | |
1153 | machine description. Also define ranges of constants. | |
1154 | ||
1155 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1156 | If there is more than one class, another class must be named NO_REGS | |
1157 | and contain no registers. | |
1158 | ||
1159 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1160 | another name such as ALL_REGS). This is the class of registers | |
1161 | that is allowed by "g" or "r" in a register constraint. | |
1162 | Also, registers outside this class are allocated only when | |
1163 | instructions express preferences for them. | |
1164 | ||
1165 | The classes must be numbered in nondecreasing order; that is, | |
1166 | a larger-numbered class must never be contained completely | |
1167 | in a smaller-numbered class. | |
1168 | ||
1169 | For any two classes, it is very desirable that there be another | |
5d70629f | 1170 | class that represents their union. |
1171 | ||
1172 | It might seem that class BREG is unnecessary, since no useful 386 | |
1173 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
ce71a9e6 | 1174 | and the "b" register constraint is useful in asms for syscalls. |
1175 | ||
d1918706 | 1176 | The flags, fpsr and fpcr registers are in no class. */ |
43b83681 | 1177 | |
1178 | enum reg_class | |
1179 | { | |
1180 | NO_REGS, | |
ce71a9e6 | 1181 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
7f6a3ac8 | 1182 | AD_REGS, /* %eax/%edx for DImode */ |
43b83681 | 1183 | Q_REGS, /* %eax %ebx %ecx %edx */ |
8c5dc77f | 1184 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
43b83681 | 1185 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
c6d93f09 | 1186 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1187 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
43b83681 | 1188 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1189 | FLOAT_REGS, | |
f0dd3deb | 1190 | SSE_FIRST_REG, |
f01b0085 | 1191 | SSE_REGS, |
1192 | MMX_REGS, | |
394c6a4a | 1193 | FP_TOP_SSE_REGS, |
1194 | FP_SECOND_SSE_REGS, | |
1195 | FLOAT_SSE_REGS, | |
1196 | FLOAT_INT_REGS, | |
1197 | INT_SSE_REGS, | |
1198 | FLOAT_INT_SSE_REGS, | |
43b83681 | 1199 | ALL_REGS, LIM_REG_CLASSES |
1200 | }; | |
1201 | ||
1b12cfd7 | 1202 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1203 | ||
1204 | #define INTEGER_CLASS_P(CLASS) \ | |
1205 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1206 | #define FLOAT_CLASS_P(CLASS) \ | |
1207 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1208 | #define SSE_CLASS_P(CLASS) \ | |
f0dd3deb | 1209 | reg_class_subset_p ((CLASS), SSE_REGS) |
1b12cfd7 | 1210 | #define MMX_CLASS_P(CLASS) \ |
279495ad | 1211 | ((CLASS) == MMX_REGS) |
1b12cfd7 | 1212 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1213 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1214 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1215 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1216 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1217 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1218 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1219 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1220 | ||
1221 | #define Q_CLASS_P(CLASS) \ | |
1222 | reg_class_subset_p ((CLASS), Q_REGS) | |
8dc6dd95 | 1223 | |
d697f1db | 1224 | /* Give names of register classes as strings for dump file. */ |
43b83681 | 1225 | |
1226 | #define REG_CLASS_NAMES \ | |
1227 | { "NO_REGS", \ | |
5d70629f | 1228 | "AREG", "DREG", "CREG", "BREG", \ |
43b83681 | 1229 | "SIREG", "DIREG", \ |
ce71a9e6 | 1230 | "AD_REGS", \ |
1231 | "Q_REGS", "NON_Q_REGS", \ | |
43b83681 | 1232 | "INDEX_REGS", \ |
c6d93f09 | 1233 | "LEGACY_REGS", \ |
43b83681 | 1234 | "GENERAL_REGS", \ |
1235 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1236 | "FLOAT_REGS", \ | |
d3ec8b3b | 1237 | "SSE_FIRST_REG", \ |
f01b0085 | 1238 | "SSE_REGS", \ |
1239 | "MMX_REGS", \ | |
394c6a4a | 1240 | "FP_TOP_SSE_REGS", \ |
1241 | "FP_SECOND_SSE_REGS", \ | |
1242 | "FLOAT_SSE_REGS", \ | |
a648dfa9 | 1243 | "FLOAT_INT_REGS", \ |
394c6a4a | 1244 | "INT_SSE_REGS", \ |
1245 | "FLOAT_INT_SSE_REGS", \ | |
43b83681 | 1246 | "ALL_REGS" } |
1247 | ||
1248 | /* Define which registers fit in which classes. | |
1249 | This is an initializer for a vector of HARD_REG_SET | |
1250 | of length N_REG_CLASSES. */ | |
1251 | ||
f01b0085 | 1252 | #define REG_CLASS_CONTENTS \ |
c6d93f09 | 1253 | { { 0x00, 0x0 }, \ |
1254 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1255 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1256 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1257 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1258 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
0a9ae7b1 | 1259 | { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ |
1260 | { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1261 | { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1262 | { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
c6d93f09 | 1263 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ |
1264 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
d3ec8b3b | 1265 | { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ |
0a9ae7b1 | 1266 | { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ |
1267 | { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1268 | { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1269 | { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1270 | { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \ | |
1271 | { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1272 | { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1273 | { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1274 | { 0xffffffff,0x1fffff } \ | |
ce71a9e6 | 1275 | } |
43b83681 | 1276 | |
47dd2e78 | 1277 | /* The following macro defines cover classes for Integrated Register |
1278 | Allocator. Cover classes is a set of non-intersected register | |
1279 | classes covering all hard registers used for register allocation | |
1280 | purpose. Any move between two registers of a cover class should be | |
1281 | cheaper than load or store of the registers. The macro value is | |
1282 | array of register classes with LIM_REG_CLASSES used as the end | |
1283 | marker. */ | |
1284 | ||
1285 | #define IRA_COVER_CLASSES \ | |
1286 | { \ | |
1287 | GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES \ | |
1288 | } | |
1289 | ||
43b83681 | 1290 | /* The same information, inverted: |
1291 | Return the class number of the smallest class containing | |
1292 | reg number REGNO. This could be a conditional expression | |
1293 | or could index an array. */ | |
1294 | ||
43b83681 | 1295 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1296 | ||
1297 | /* When defined, the compiler allows registers explicitly used in the | |
1298 | rtl to be used as spill registers but prevents the compiler from | |
bb441676 | 1299 | extending the lifetime of these registers. */ |
43b83681 | 1300 | |
f1db295a | 1301 | #define SMALL_REGISTER_CLASSES 1 |
43b83681 | 1302 | |
3cc68209 | 1303 | #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4) |
c6d93f09 | 1304 | |
1b12cfd7 | 1305 | #define GENERAL_REGNO_P(N) \ |
3cc68209 | 1306 | ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) |
c6d93f09 | 1307 | |
1308 | #define GENERAL_REG_P(X) \ | |
cbf58688 | 1309 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
c6d93f09 | 1310 | |
1311 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1312 | ||
3cc68209 | 1313 | #define REX_INT_REGNO_P(N) \ |
1314 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
c6d93f09 | 1315 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1316 | ||
43b83681 | 1317 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
3cc68209 | 1318 | #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
394c6a4a | 1319 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
1b12cfd7 | 1320 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
f01b0085 | 1321 | |
ed01e173 | 1322 | #define X87_FLOAT_MODE_P(MODE) \ |
d26e00d8 | 1323 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) |
ed01e173 | 1324 | |
3cc68209 | 1325 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) |
1326 | #define SSE_REGNO_P(N) \ | |
1327 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
1328 | || REX_SSE_REGNO_P (N)) | |
c6d93f09 | 1329 | |
805e22b2 | 1330 | #define REX_SSE_REGNO_P(N) \ |
3cc68209 | 1331 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
805e22b2 | 1332 | |
1b12cfd7 | 1333 | #define SSE_REGNO(N) \ |
1334 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
394c6a4a | 1335 | |
1b12cfd7 | 1336 | #define SSE_FLOAT_MODE_P(MODE) \ |
780f86b7 | 1337 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
f01b0085 | 1338 | |
2a466fea | 1339 | #define SSE_VEC_FLOAT_MODE_P(MODE) \ |
1340 | ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) | |
1341 | ||
1b12cfd7 | 1342 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) |
3cc68209 | 1343 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
d4983fea | 1344 | |
3cc68209 | 1345 | #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) |
3cc68209 | 1346 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
43b83681 | 1347 | |
1b12cfd7 | 1348 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
43b83681 | 1349 | |
ce71a9e6 | 1350 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1351 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1352 | ||
43b83681 | 1353 | /* The class value for index registers, and the one for base regs. */ |
1354 | ||
1355 | #define INDEX_REG_CLASS INDEX_REGS | |
1356 | #define BASE_REG_CLASS GENERAL_REGS | |
1357 | ||
43b83681 | 1358 | /* Place additional restrictions on the register class to use when it |
76170098 | 1359 | is necessary to be able to hold a value of mode MODE in a reload |
bb441676 | 1360 | register for which class CLASS would ordinarily be used. */ |
43b83681 | 1361 | |
2ede69f5 | 1362 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1363 | ((MODE) == QImode && !TARGET_64BIT \ | |
c0a5a33a | 1364 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1365 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
43b83681 | 1366 | ? Q_REGS : (CLASS)) |
1367 | ||
1368 | /* Given an rtx X being reloaded into a reg required to be | |
1369 | in class CLASS, return the class of reg to actually use. | |
1370 | In general this is just CLASS; but on some machines | |
1371 | in some cases it is preferable to use a more restrictive class. | |
1372 | On the 80386 series, we prevent floating constants from being | |
1373 | reloaded into floating registers (since no move-insn can do that) | |
1374 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1375 | ||
3eba6fa0 | 1376 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
43b83681 | 1377 | QImode must go into class Q_REGS. |
3eba6fa0 | 1378 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
bb441676 | 1379 | movdf to do mem-to-mem moves through integer regs. */ |
43b83681 | 1380 | |
1b12cfd7 | 1381 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1382 | ix86_preferred_reload_class ((X), (CLASS)) | |
9a0e8e92 | 1383 | |
897f76b2 | 1384 | /* Discourage putting floating-point values in SSE registers unless |
1385 | SSE math is being used, and likewise for the 387 registers. */ | |
1386 | ||
1387 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
1388 | ix86_preferred_output_reload_class ((X), (CLASS)) | |
1389 | ||
9a0e8e92 | 1390 | /* If we are copying between general and FP registers, we need a memory |
ea073cb0 | 1391 | location. The same is true for SSE and MMX registers. */ |
1b12cfd7 | 1392 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1393 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
ce71a9e6 | 1394 | |
296a3469 | 1395 | /* Get_secondary_mem widens integral modes to BITS_PER_WORD. |
1396 | There is no need to emit full 64 bit move on 64 bit targets | |
1397 | for integral modes that can be moved using 32 bit move. */ | |
1398 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1399 | (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1400 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1401 | : MODE) | |
1402 | ||
43b83681 | 1403 | /* Return the maximum number of consecutive registers |
1404 | needed to represent mode MODE in a register of class CLASS. */ | |
1405 | /* On the 80386, this is the size of MODE in words, | |
e07e720e | 1406 | except in the FP regs, where a single reg is always enough. */ |
f01b0085 | 1407 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
699a9fea | 1408 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1409 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
e07e720e | 1410 | : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ |
1411 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
0bf9a70a | 1412 | |
1413 | /* A C expression whose value is nonzero if pseudos that have been | |
1414 | assigned to registers of class CLASS would likely be spilled | |
1415 | because registers of CLASS are needed for spill registers. | |
1416 | ||
1417 | The default value of this macro returns 1 if CLASS has exactly one | |
1418 | register and zero otherwise. On most machines, this default | |
1419 | should be used. Only define this macro to some other expression | |
1420 | if pseudo allocated by `local-alloc.c' end up in memory because | |
01cc3b75 | 1421 | their hard registers were needed for spill registers. If this |
0bf9a70a | 1422 | macro returns nonzero for those classes, those pseudos will only |
1423 | be allocated by `global.c', which knows how to reallocate the | |
1424 | pseudo to another register. If there would not be another | |
1425 | register available for reallocation, you should not change the | |
1426 | definition of this macro since the only effect of such a | |
1427 | definition would be to slow down register allocation. */ | |
1428 | ||
1429 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1430 | (((CLASS) == AREG) \ | |
1431 | || ((CLASS) == DREG) \ | |
1432 | || ((CLASS) == CREG) \ | |
1433 | || ((CLASS) == BREG) \ | |
1434 | || ((CLASS) == AD_REGS) \ | |
1435 | || ((CLASS) == SIREG) \ | |
eeb0109f | 1436 | || ((CLASS) == DIREG) \ |
1437 | || ((CLASS) == FP_TOP_REG) \ | |
1438 | || ((CLASS) == FP_SECOND_REG)) | |
0bf9a70a | 1439 | |
5d258b81 | 1440 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1441 | ||
1442 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1443 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
43b83681 | 1444 | \f |
1445 | /* Stack layout; function entry, exit and calling. */ | |
1446 | ||
1447 | /* Define this if pushing a word on the stack | |
1448 | makes the stack pointer a smaller address. */ | |
1449 | #define STACK_GROWS_DOWNWARD | |
1450 | ||
3ce7ff97 | 1451 | /* Define this to nonzero if the nominal address of the stack frame |
43b83681 | 1452 | is at the high-address end of the local variables; |
1453 | that is, each additional local variable allocated | |
1454 | goes at a more negative offset in the frame. */ | |
d28d5017 | 1455 | #define FRAME_GROWS_DOWNWARD 1 |
43b83681 | 1456 | |
1457 | /* Offset within stack frame to start allocating local variables at. | |
1458 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1459 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1460 | of the first local allocated. */ | |
1461 | #define STARTING_FRAME_OFFSET 0 | |
1462 | ||
1463 | /* If we generate an insn to push BYTES bytes, | |
1464 | this says how many the stack pointer really advances by. | |
3cb7a129 | 1465 | On 386, we have pushw instruction that decrements by exactly 2 no |
1466 | matter what the position was, there is no pushb. | |
1467 | But as CIE data alignment factor on this arch is -4, we need to make | |
1468 | sure all stack pointer adjustments are in multiple of 4. | |
d4983fea | 1469 | |
2ede69f5 | 1470 | For 64bit ABI we round up to 8 bytes. |
1471 | */ | |
43b83681 | 1472 | |
2ede69f5 | 1473 | #define PUSH_ROUNDING(BYTES) \ |
1474 | (TARGET_64BIT \ | |
1475 | ? (((BYTES) + 7) & (-8)) \ | |
3cb7a129 | 1476 | : (((BYTES) + 3) & (-4))) |
43b83681 | 1477 | |
4448f543 | 1478 | /* If defined, the maximum amount of space required for outgoing arguments will |
1479 | be computed and placed into the variable | |
abe32cce | 1480 | `crtl->outgoing_args_size'. No space will be pushed onto the |
4448f543 | 1481 | stack for each call; instead, the function prologue should increase the stack |
1482 | frame size by this amount. */ | |
1483 | ||
1484 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
1485 | ||
1486 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1487 | instructions to pass outgoing arguments. */ | |
1488 | ||
1489 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1490 | ||
2a8e54a4 | 1491 | /* We want the stack and args grow in opposite directions, even if |
1492 | PUSH_ARGS is 0. */ | |
1493 | #define PUSH_ARGS_REVERSED 1 | |
1494 | ||
43b83681 | 1495 | /* Offset of first parameter from the argument pointer register value. */ |
1496 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1497 | ||
f01b0085 | 1498 | /* Define this macro if functions should assume that stack space has been |
1499 | allocated for arguments even when their values are passed in registers. | |
1500 | ||
1501 | The value of this macro is the size, in bytes, of the area reserved for | |
1502 | arguments passed in registers for the function represented by FNDECL. | |
1503 | ||
1504 | This space can be allocated by the caller, or be a part of the | |
1505 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1506 | which. */ | |
d3feb168 | 1507 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1508 | ||
1509 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) (ix86_function_type_abi (FNTYPE) == MS_ABI ? 1 : 0) | |
1510 | ||
43b83681 | 1511 | /* Value is the number of bytes of arguments automatically |
1512 | popped when returning from a subroutine call. | |
97a18f26 | 1513 | FUNDECL is the declaration node of the function (as a tree), |
43b83681 | 1514 | FUNTYPE is the data type of the function (as a tree), |
1515 | or for a library call it is an identifier node for the subroutine name. | |
1516 | SIZE is the number of bytes of arguments passed on the stack. | |
1517 | ||
1518 | On the 80386, the RTD insn may be used to pop them if the number | |
1519 | of args is fixed, but if the number is variable then the caller | |
1520 | must pop them all. RTD can't be used for library calls now | |
1521 | because the library is compiled with the Unix compiler. | |
1522 | Use of RTD is a selectable option, since it is incompatible with | |
1523 | standard Unix calling sequences. If the option is not selected, | |
bfa936ad | 1524 | the caller must always pop the args. |
1525 | ||
1526 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
43b83681 | 1527 | |
1b12cfd7 | 1528 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1529 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
43b83681 | 1530 | |
e4bf866d | 1531 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1532 | ix86_function_value_regno_p (N) | |
43b83681 | 1533 | |
1534 | /* Define how to find the value returned by a library function | |
1535 | assuming the value has mode MODE. */ | |
1536 | ||
1537 | #define LIBCALL_VALUE(MODE) \ | |
e4bf866d | 1538 | ix86_libcall_value (MODE) |
43b83681 | 1539 | |
f202941c | 1540 | /* Define the size of the result block used for communication between |
1541 | untyped_call and untyped_return. The block contains a DImode value | |
1542 | followed by the block used by fnsave and frstor. */ | |
1543 | ||
1544 | #define APPLY_RESULT_SIZE (8+108) | |
1545 | ||
bfa936ad | 1546 | /* 1 if N is a possible register number for function argument passing. */ |
e4bf866d | 1547 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
43b83681 | 1548 | |
1549 | /* Define a data type for recording info about an argument list | |
1550 | during the scan of that argument list. This data type should | |
1551 | hold all necessary information about the function itself | |
1552 | and about the args processed so far, enough to enable macros | |
bfa936ad | 1553 | such as FUNCTION_ARG to determine where the next arg should go. */ |
43b83681 | 1554 | |
ce71a9e6 | 1555 | typedef struct ix86_args { |
bae5345b | 1556 | int words; /* # words passed so far */ |
bfa936ad | 1557 | int nregs; /* # registers available for passing */ |
1558 | int regno; /* next available register number */ | |
abf198ab | 1559 | int fastcall; /* fastcall calling convention is used */ |
bae5345b | 1560 | int sse_words; /* # sse words passed so far */ |
f01b0085 | 1561 | int sse_nregs; /* # sse registers available for passing */ |
e92554cb | 1562 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
bae5345b | 1563 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1564 | int sse_regno; /* next available sse register number */ | |
1565 | int mmx_words; /* # mmx words passed so far */ | |
6ef4a624 | 1566 | int mmx_nregs; /* # mmx registers available for passing */ |
1567 | int mmx_regno; /* next available mmx register number */ | |
bb441676 | 1568 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
3524624e | 1569 | int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should |
1570 | be passed in SSE registers. Otherwise 0. */ | |
d3feb168 | 1571 | int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
1572 | MS_ABI for ms abi. */ | |
bfa936ad | 1573 | } CUMULATIVE_ARGS; |
43b83681 | 1574 | |
1575 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1576 | for a call to a function whose data type is FNTYPE. | |
bfa936ad | 1577 | For a library call, FNTYPE is 0. */ |
43b83681 | 1578 | |
30c70355 | 1579 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
80a85d8a | 1580 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
43b83681 | 1581 | |
1582 | /* Update the data in CUM to advance over an argument | |
1583 | of mode MODE and data type TYPE. | |
1584 | (TYPE is null for libcalls where that information may not be available.) */ | |
1585 | ||
1b12cfd7 | 1586 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1587 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
43b83681 | 1588 | |
1589 | /* Define where to put the arguments to a function. | |
1590 | Value is zero to push the argument on the stack, | |
1591 | or a hard register in which to store the argument. | |
1592 | ||
1593 | MODE is the argument's machine mode. | |
1594 | TYPE is the data type of the argument (as a tree). | |
1595 | This is null for libcalls where that information may | |
1596 | not be available. | |
1597 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1598 | the preceding args and about the function being called. | |
1599 | NAMED is nonzero if this argument is a named parameter | |
1600 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1601 | ||
43b83681 | 1602 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1b12cfd7 | 1603 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
43b83681 | 1604 | |
f6940372 | 1605 | #define TARGET_ASM_FILE_END ix86_file_end |
1606 | #define NEED_INDICATE_EXEC_STACK 0 | |
42c2e1fa | 1607 | |
43b83681 | 1608 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1609 | for profiling a function entry. */ | |
1610 | ||
af23924f | 1611 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1612 | ||
1613 | #define MCOUNT_NAME "_mcount" | |
1614 | ||
1615 | #define PROFILE_COUNT_REGISTER "edx" | |
43b83681 | 1616 | |
1617 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1618 | the stack pointer does not matter. The value is tested only in | |
1619 | functions that have frame pointers. | |
1620 | No definition is equivalent to always zero. */ | |
d4983fea | 1621 | /* Note on the 386 it might be more efficient not to define this since |
43b83681 | 1622 | we have to restore it ourselves from the frame pointer, in order to |
1623 | use pop */ | |
1624 | ||
1625 | #define EXIT_IGNORE_STACK 1 | |
1626 | ||
43b83681 | 1627 | /* Output assembler code for a block containing the constant parts |
1628 | of a trampoline, leaving space for the variable parts. */ | |
1629 | ||
f3e2ae00 | 1630 | /* On the 386, the trampoline contains two instructions: |
43b83681 | 1631 | mov #STATIC,ecx |
f3e2ae00 | 1632 | jmp FUNCTION |
1633 | The trampoline is generated entirely at runtime. The operand of JMP | |
1634 | is the address of FUNCTION relative to the instruction following the | |
1635 | JMP (which is 5 bytes long). */ | |
43b83681 | 1636 | |
1637 | /* Length in units of the trampoline for entering a nested function. */ | |
1638 | ||
e246b648 | 1639 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
43b83681 | 1640 | |
1641 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1642 | FNADDR is an RTX for the address of the function's pure code. | |
1643 | CXT is an RTX for the static chain value for the function. */ | |
1644 | ||
1b12cfd7 | 1645 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1646 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
43b83681 | 1647 | \f |
1648 | /* Definitions for register eliminations. | |
1649 | ||
1650 | This is an array of structures. Each structure initializes one pair | |
1651 | of eliminable registers. The "from" register number is given first, | |
1652 | followed by "to". Eliminations of the same "from" register are listed | |
1653 | in order of preference. | |
1654 | ||
0be394dd | 1655 | There are two registers that can always be eliminated on the i386. |
1656 | The frame pointer and the arg pointer can be replaced by either the | |
1657 | hard frame pointer or to the stack pointer, depending upon the | |
1658 | circumstances. The hard frame pointer is not used before reload and | |
1659 | so it is not eligible for elimination. */ | |
43b83681 | 1660 | |
8c5dc77f | 1661 | #define ELIMINABLE_REGS \ |
1662 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1663 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1664 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1665 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
43b83681 | 1666 | |
83070725 | 1667 | /* Given FROM and TO register numbers, say whether this elimination is |
27a7a23a | 1668 | allowed. */ |
43b83681 | 1669 | |
27a7a23a | 1670 | #define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO)) |
43b83681 | 1671 | |
1672 | /* Define the offset between two registers, one to be eliminated, and the other | |
1673 | its replacement, at the start of a routine. */ | |
1674 | ||
1b12cfd7 | 1675 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1676 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
43b83681 | 1677 | \f |
1678 | /* Addressing modes, and classification of registers for them. */ | |
1679 | ||
43b83681 | 1680 | /* Macros to check register numbers against specific register classes. */ |
1681 | ||
1682 | /* These assume that REGNO is a hard or pseudo reg number. | |
1683 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1684 | or a pseudo reg currently allocated to a suitable hard reg. | |
1685 | Since they use reg_renumber, they are safe only once reg_renumber | |
1686 | has been allocated, which happens in local-alloc.c. */ | |
1687 | ||
c6d93f09 | 1688 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1689 | ((REGNO) < STACK_POINTER_REGNUM \ | |
3cc68209 | 1690 | || REX_INT_REGNO_P (REGNO) \ |
1691 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1692 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
43b83681 | 1693 | |
c6d93f09 | 1694 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
3cc68209 | 1695 | (GENERAL_REGNO_P (REGNO) \ |
c6d93f09 | 1696 | || (REGNO) == ARG_POINTER_REGNUM \ |
1697 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
3cc68209 | 1698 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
43b83681 | 1699 | |
43b83681 | 1700 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1701 | and check its validity for a certain class. | |
1702 | We have two alternate definitions for each of them. | |
1703 | The usual definition accepts all pseudo regs; the other rejects | |
1704 | them unless they have been allocated suitable hard regs. | |
1705 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1706 | ||
1707 | Most source files want to accept pseudo regs in the hope that | |
1708 | they will get allocated to the class that the insn wants them to be in. | |
1709 | Source files for reload pass need to be strict. | |
1710 | After reload, it makes no difference, since pseudo regs have | |
1711 | been eliminated by then. */ | |
1712 | ||
43b83681 | 1713 | |
1d60d981 | 1714 | /* Non strict versions, pseudos are ok. */ |
60206704 | 1715 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1716 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
3cc68209 | 1717 | || REX_INT_REGNO_P (REGNO (X)) \ |
43b83681 | 1718 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1719 | ||
60206704 | 1720 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
3cc68209 | 1721 | (GENERAL_REGNO_P (REGNO (X)) \ |
60206704 | 1722 | || REGNO (X) == ARG_POINTER_REGNUM \ |
c6d93f09 | 1723 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
60206704 | 1724 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
43b83681 | 1725 | |
60206704 | 1726 | /* Strict versions, hard registers only */ |
1727 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1728 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
43b83681 | 1729 | |
60206704 | 1730 | #ifndef REG_OK_STRICT |
1b12cfd7 | 1731 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1732 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
60206704 | 1733 | |
1734 | #else | |
1b12cfd7 | 1735 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1736 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
43b83681 | 1737 | #endif |
1738 | ||
1739 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1740 | that is a valid memory address for an instruction. | |
1741 | The MODE argument is the machine mode for the MEM expression | |
1742 | that wants to use this address. | |
1743 | ||
1744 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1745 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1746 | ||
1747 | See legitimize_pic_address in i386.c for details as to what | |
1748 | constitutes a legitimate address when -fpic is used. */ | |
1749 | ||
1750 | #define MAX_REGS_PER_ADDRESS 2 | |
1751 | ||
2d6788fe | 1752 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
43b83681 | 1753 | |
1754 | /* Nonzero if the constant value X is a legitimate general operand. | |
1755 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1756 | ||
2d6788fe | 1757 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
43b83681 | 1758 | |
60206704 | 1759 | #ifdef REG_OK_STRICT |
1760 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1b12cfd7 | 1761 | do { \ |
1762 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
60206704 | 1763 | goto ADDR; \ |
1b12cfd7 | 1764 | } while (0) |
43b83681 | 1765 | |
60206704 | 1766 | #else |
1767 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1b12cfd7 | 1768 | do { \ |
1769 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
43b83681 | 1770 | goto ADDR; \ |
1b12cfd7 | 1771 | } while (0) |
43b83681 | 1772 | |
60206704 | 1773 | #endif |
1774 | ||
15750b1e | 1775 | /* If defined, a C expression to determine the base term of address X. |
1776 | This macro is used in only one place: `find_base_term' in alias.c. | |
1777 | ||
1778 | It is always safe for this macro to not be defined. It exists so | |
1779 | that alias analysis can understand machine-dependent addresses. | |
1780 | ||
1781 | The typical use of this macro is to handle addresses containing | |
1782 | a label_ref or symbol_ref within an UNSPEC. */ | |
1783 | ||
1b12cfd7 | 1784 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
15750b1e | 1785 | |
43b83681 | 1786 | /* Try machine-dependent ways of modifying an illegitimate address |
1787 | to be legitimate. If we find one, return the new, valid address. | |
1788 | This macro is used in only one place: `memory_address' in explow.c. | |
1789 | ||
1790 | OLDX is the address as it was before break_out_memory_refs was called. | |
1791 | In some cases it is useful to look at this to decide what needs to be done. | |
1792 | ||
1793 | MODE and WIN are passed so that this macro can use | |
1794 | GO_IF_LEGITIMATE_ADDRESS. | |
1795 | ||
1796 | It is always safe for this macro to do nothing. It exists to recognize | |
1797 | opportunities to optimize the output. | |
1798 | ||
1799 | For the 80386, we handle X+REG by loading X into a register R and | |
1800 | using R+REG. R will go in a general reg and indexing will be used. | |
1801 | However, if REG is a broken-out memory address or multiplication, | |
1802 | nothing needs to be done because REG can certainly go in a general reg. | |
1803 | ||
1804 | When -fpic is used, special handling is needed for symbolic references. | |
1805 | See comments by legitimize_pic_address in i386.c for details. */ | |
1806 | ||
60206704 | 1807 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1b12cfd7 | 1808 | do { \ |
1809 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
1810 | if (memory_address_p ((MODE), (X))) \ | |
60206704 | 1811 | goto WIN; \ |
1b12cfd7 | 1812 | } while (0) |
43b83681 | 1813 | |
1814 | /* Nonzero if the constant value X is a legitimate general operand | |
d4983fea | 1815 | when generating PIC code. It is given that flag_pic is on and |
43b83681 | 1816 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1817 | ||
2d6788fe | 1818 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
43b83681 | 1819 | |
1820 | #define SYMBOLIC_CONST(X) \ | |
1b12cfd7 | 1821 | (GET_CODE (X) == SYMBOL_REF \ |
1822 | || GET_CODE (X) == LABEL_REF \ | |
1823 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
43b83681 | 1824 | |
1825 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1826 | has an effect that depends on the machine mode it is used for. | |
1827 | On the 80386, only postdecrement and postincrement address depend thus | |
cad2a6b5 | 1828 | (the amount of decrement or increment being the length of the operand). |
1829 | These are now caught in recog.c. */ | |
1830 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
43b83681 | 1831 | \f |
bfa936ad | 1832 | /* Max number of args passed in registers. If this is more than 3, we will |
1833 | have problems with ebx (register #4), since it is a caller save register and | |
1834 | is also used as the pic register in ELF. So for now, don't allow more than | |
1835 | 3 registers to be passed in registers. */ | |
1836 | ||
d3feb168 | 1837 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1838 | #define X86_64_REGPARM_MAX 6 | |
1839 | #define X64_REGPARM_MAX 4 | |
1840 | #define X86_32_REGPARM_MAX 3 | |
1841 | ||
1842 | #define X86_64_SSE_REGPARM_MAX 8 | |
1843 | #define X64_SSE_REGPARM_MAX 4 | |
1844 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0) | |
1845 | ||
1846 | #define REGPARM_MAX (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \ | |
1847 | : X86_64_REGPARM_MAX) \ | |
1848 | : X86_32_REGPARM_MAX) | |
2ede69f5 | 1849 | |
d3feb168 | 1850 | #define SSE_REGPARM_MAX (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \ |
1851 | : X86_64_SSE_REGPARM_MAX) \ | |
1852 | : X86_32_SSE_REGPARM_MAX) | |
6ef4a624 | 1853 | |
1854 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
bfa936ad | 1855 | |
43b83681 | 1856 | \f |
1857 | /* Specify the machine mode that this machine uses | |
1858 | for the index in the tablejump instruction. */ | |
5fe80ef0 | 1859 | #define CASE_VECTOR_MODE \ |
1860 | (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) | |
43b83681 | 1861 | |
43b83681 | 1862 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1863 | #define DEFAULT_SIGNED_CHAR 1 | |
1864 | ||
1865 | /* Max number of bytes we can move from memory to memory | |
1866 | in one reasonably fast instruction. */ | |
c7f5f345 | 1867 | #define MOVE_MAX 16 |
1868 | ||
1869 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1870 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
bb441676 | 1871 | number of bytes we can move with a single instruction. */ |
c7f5f345 | 1872 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
43b83681 | 1873 | |
cbdc0179 | 1874 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
008c057d | 1875 | move-instruction pairs, we will do a movmem or libcall instead. |
cbdc0179 | 1876 | Increasing the value will always make code faster, but eventually |
1877 | incurs high cost in increased code size. | |
43b83681 | 1878 | |
a746fd01 | 1879 | If you don't define this, a reasonable default is used. */ |
43b83681 | 1880 | |
a746fd01 | 1881 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
43b83681 | 1882 | |
025d4f81 | 1883 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1884 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1885 | ||
46de89e7 | 1886 | #define CLEAR_RATIO (optimize_size ? 2 : MIN (6, ix86_cost->move_ratio)) |
025d4f81 | 1887 | |
43b83681 | 1888 | /* Define if shifts truncate the shift count |
1889 | which implies one can omit a sign-extension or zero-extension | |
1890 | of a shift count. */ | |
bb441676 | 1891 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
43b83681 | 1892 | |
1893 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1894 | ||
1895 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1896 | is done just by pretending it is already truncated. */ | |
1897 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1898 | ||
c41f04da | 1899 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1900 | TYPE and which has the specified mode and signedness is to be | |
1901 | stored in a register. This macro is only called when TYPE is a | |
1902 | scalar type. | |
1903 | ||
8ef587dc | 1904 | On i386 it is sometimes useful to promote HImode and QImode |
c41f04da | 1905 | quantities to SImode. The choice depends on target type. */ |
1906 | ||
1907 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1b12cfd7 | 1908 | do { \ |
c41f04da | 1909 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1910 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
1b12cfd7 | 1911 | (MODE) = SImode; \ |
1912 | } while (0) | |
c41f04da | 1913 | |
43b83681 | 1914 | /* Specify the machine mode that pointers have. |
1915 | After generation of rtl, the compiler makes no further distinction | |
1916 | between pointers and any other objects of this machine mode. */ | |
c7f5f345 | 1917 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
43b83681 | 1918 | |
1919 | /* A function address in a call instruction | |
1920 | is a byte address (for indexing purposes) | |
1921 | so give the MEM rtx a byte's mode. */ | |
1922 | #define FUNCTION_MODE QImode | |
9af5c5d1 | 1923 | \f |
3ab61a4d | 1924 | /* A C expression for the cost of moving data from a register in class FROM to |
1925 | one in class TO. The classes are expressed using the enumeration values | |
1926 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
1927 | interpreted relative to that. | |
9af5c5d1 | 1928 | |
3ab61a4d | 1929 | It is not required that the cost always equal 2 when FROM is the same as TO; |
1930 | on some machines it is expensive to move between registers if they are not | |
ea073cb0 | 1931 | general registers. */ |
9af5c5d1 | 1932 | |
ea073cb0 | 1933 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
1b12cfd7 | 1934 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
9af5c5d1 | 1935 | |
1936 | /* A C expression for the cost of moving data of mode M between a | |
1937 | register and memory. A value of 2 is the default; this cost is | |
1938 | relative to those in `REGISTER_MOVE_COST'. | |
1939 | ||
1940 | If moving between registers and memory is more expensive than | |
1941 | between two registers, you should define this macro to express the | |
4f3e5c20 | 1942 | relative cost. */ |
9af5c5d1 | 1943 | |
1b12cfd7 | 1944 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
1945 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
9af5c5d1 | 1946 | |
1947 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1948 | is the default; other values are interpreted relative to that. */ | |
1949 | ||
ce71a9e6 | 1950 | #define BRANCH_COST ix86_branch_cost |
9af5c5d1 | 1951 | |
1952 | /* Define this macro as a C expression which is nonzero if accessing | |
1953 | less than a word of memory (i.e. a `char' or a `short') is no | |
1954 | faster than accessing a word of memory, i.e., if such access | |
1955 | require more than one instruction or if there is no difference in | |
1956 | cost between byte and (aligned) word loads. | |
1957 | ||
1958 | When this macro is not defined, the compiler will access a field by | |
1959 | finding the smallest containing object; when it is defined, a | |
1960 | fullword load will be used if alignment permits. Unless bytes | |
1961 | accesses are faster than word accesses, using word accesses is | |
1962 | preferable since it may eliminate subsequent memory access if | |
1963 | subsequent accesses occur to other fields in the same word of the | |
1964 | structure, but to different bytes. */ | |
1965 | ||
1966 | #define SLOW_BYTE_ACCESS 0 | |
1967 | ||
1968 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1969 | #define SLOW_SHORT_ACCESS 0 | |
1970 | ||
9af5c5d1 | 1971 | /* Define this macro to be the value 1 if unaligned accesses have a |
1972 | cost many times greater than aligned accesses, for example if they | |
1973 | are emulated in a trap handler. | |
1974 | ||
c46dc351 | 1975 | When this macro is nonzero, the compiler will act as if |
1976 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
9af5c5d1 | 1977 | moves. This can cause significantly more instructions to be |
c46dc351 | 1978 | produced. Therefore, do not set this macro nonzero if unaligned |
9af5c5d1 | 1979 | accesses only add a cycle or two to the time for a memory access. |
1980 | ||
1981 | If the value of this macro is always zero, it need not be defined. */ | |
1982 | ||
9439ebf7 | 1983 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
9af5c5d1 | 1984 | |
9af5c5d1 | 1985 | /* Define this macro if it is as good or better to call a constant |
1986 | function address than to call an address kept in a register. | |
1987 | ||
1988 | Desirable on the 386 because a CALL with a constant address is | |
1989 | faster than one with a register address. */ | |
1990 | ||
1991 | #define NO_FUNCTION_CSE | |
43b83681 | 1992 | \f |
b15e0bba | 1993 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1994 | return the mode to be used for the comparison. | |
1995 | ||
1996 | For floating-point equality comparisons, CCFPEQmode should be used. | |
ce71a9e6 | 1997 | VOIDmode should be used in all other cases. |
b15e0bba | 1998 | |
979a64df | 1999 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
ce71a9e6 | 2000 | possible, to allow for more combinations. */ |
43b83681 | 2001 | |
1b12cfd7 | 2002 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
59112222 | 2003 | |
c46dc351 | 2004 | /* Return nonzero if MODE implies a floating point inequality can be |
59112222 | 2005 | reversed. */ |
2006 | ||
2007 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2008 | ||
2009 | /* A C expression whose value is reversed condition code of the CODE for | |
2010 | comparison done in CC_MODE mode. */ | |
41252d26 | 2011 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
59112222 | 2012 | |
43b83681 | 2013 | \f |
2014 | /* Control the assembler format that we output, to the extent | |
2015 | this does not vary between assemblers. */ | |
2016 | ||
2017 | /* How to refer to registers in assembler output. | |
bb441676 | 2018 | This sequence is indexed by compiler's hard-register-number (see above). */ |
43b83681 | 2019 | |
5b865faf | 2020 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
43b83681 | 2021 | For non floating point regs, the following are the HImode names. |
2022 | ||
2023 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
474bb692 | 2024 | instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ |
43b83681 | 2025 | |
f01b0085 | 2026 | #define HI_REGISTER_NAMES \ |
2027 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
d535f7e3 | 2028 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
0a9ae7b1 | 2029 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
f01b0085 | 2030 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
d1918706 | 2031 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
c6d93f09 | 2032 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
2033 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
f01b0085 | 2034 | |
43b83681 | 2035 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2036 | ||
2037 | /* Table of additional register names to use in user input. */ | |
2038 | ||
2039 | #define ADDITIONAL_REGISTER_NAMES \ | |
ebf7b427 | 2040 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2041 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
c6d93f09 | 2042 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
2043 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
ebf7b427 | 2044 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
126a70bb | 2045 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } |
43b83681 | 2046 | |
2047 | /* Note we are omitting these since currently I don't know how | |
2048 | to get gcc to use these, since they want the same but different | |
2049 | number as al, and ax. | |
2050 | */ | |
2051 | ||
43b83681 | 2052 | #define QI_REGISTER_NAMES \ |
c6d93f09 | 2053 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
43b83681 | 2054 | |
2055 | /* These parallel the array above, and can be used to access bits 8:15 | |
bb441676 | 2056 | of regs 0 through 3. */ |
43b83681 | 2057 | |
2058 | #define QI_HIGH_REGISTER_NAMES \ | |
2059 | {"ah", "dh", "ch", "bh", } | |
2060 | ||
2061 | /* How to renumber registers for dbx and gdb. */ | |
2062 | ||
1b12cfd7 | 2063 | #define DBX_REGISTER_NUMBER(N) \ |
2064 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
eb26ca2c | 2065 | |
92df0d3c | 2066 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2067 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2068 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
43b83681 | 2069 | |
df78b73b | 2070 | /* Before the prologue, RA is at 0(%esp). */ |
2071 | #define INCOMING_RETURN_ADDR_RTX \ | |
5c6cf936 | 2072 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
d4983fea | 2073 | |
0870676d | 2074 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
287edcbf | 2075 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2076 | ((COUNT) == 0 \ | |
2077 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
2078 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
0870676d | 2079 | |
bb441676 | 2080 | /* PC is dbx register 8; let's use that column for RA. */ |
62c74046 | 2081 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
df78b73b | 2082 | |
19bce576 | 2083 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
62c74046 | 2084 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
19bce576 | 2085 | |
287edcbf | 2086 | /* Describe how we implement __builtin_eh_return. */ |
2087 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
2088 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
2089 | ||
9532742b | 2090 | |
038bfd6b | 2091 | /* Select a format to encode pointers in exception handling data. CODE |
2092 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2093 | true if the symbol may be affected by dynamic relocations. | |
2094 | ||
2095 | ??? All x86 object file formats are capable of representing this. | |
2096 | After all, the relocation needed is the same as for the call insn. | |
2097 | Whether or not a particular assembler allows us to enter such, I | |
2098 | guess we'll have to see. */ | |
1b12cfd7 | 2099 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
5e6d8953 | 2100 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
038bfd6b | 2101 | |
43b83681 | 2102 | /* This is how to output an insn to push a register on the stack. |
2103 | It need not be very fast code. */ | |
2104 | ||
1b12cfd7 | 2105 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
44c0bfa7 | 2106 | do { \ |
2107 | if (TARGET_64BIT) \ | |
2108 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2109 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2110 | else \ | |
2111 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2112 | } while (0) | |
43b83681 | 2113 | |
2114 | /* This is how to output an insn to pop a register from the stack. | |
2115 | It need not be very fast code. */ | |
2116 | ||
1b12cfd7 | 2117 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
44c0bfa7 | 2118 | do { \ |
2119 | if (TARGET_64BIT) \ | |
2120 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2121 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2122 | else \ | |
2123 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2124 | } while (0) | |
43b83681 | 2125 | |
bb006a84 | 2126 | /* This is how to output an element of a case-vector that is absolute. */ |
43b83681 | 2127 | |
2128 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1b12cfd7 | 2129 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
43b83681 | 2130 | |
bb006a84 | 2131 | /* This is how to output an element of a case-vector that is relative. */ |
43b83681 | 2132 | |
9eaab178 | 2133 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
1b12cfd7 | 2134 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
bb006a84 | 2135 | |
3ebc7dec | 2136 | /* Under some conditions we need jump tables in the text section, |
2137 | because the assembler cannot handle label differences between | |
2138 | sections. This is the case for x86_64 on Mach-O for example. */ | |
bb006a84 | 2139 | |
2140 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
3ebc7dec | 2141 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2142 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
43b83681 | 2143 | |
e1ff7102 | 2144 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2145 | and switch back. For x86 we do this only to save a few bytes that | |
2146 | would otherwise be unused in the text section. */ | |
2147 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2148 | asm (SECTION_OP "\n\t" \ | |
2149 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
2150 | TEXT_SECTION_ASM_OP); | |
a40a0ed3 | 2151 | \f |
43b83681 | 2152 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2153 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
e0f05f0c | 2154 | Effect of various CODE letters is described in i386.c near |
2155 | print_operand function. */ | |
43b83681 | 2156 | |
1b12cfd7 | 2157 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
724fa541 | 2158 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') |
43b83681 | 2159 | |
2160 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1b12cfd7 | 2161 | print_operand ((FILE), (X), (CODE)) |
43b83681 | 2162 | |
2163 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1b12cfd7 | 2164 | print_operand_address ((FILE), (ADDR)) |
43b83681 | 2165 | |
2d6788fe | 2166 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
2167 | do { \ | |
2168 | if (! output_addr_const_extra (FILE, (X))) \ | |
2169 | goto FAIL; \ | |
2170 | } while (0); | |
9af5c5d1 | 2171 | \f |
d25a2a8c | 2172 | /* Which processor to schedule for. The cpu attribute defines a list that |
2173 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
2174 | ||
2175 | enum processor_type | |
2176 | { | |
8ba8ec53 | 2177 | PROCESSOR_I386 = 0, /* 80386 */ |
d25a2a8c | 2178 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2179 | PROCESSOR_PENTIUM, | |
2180 | PROCESSOR_PENTIUMPRO, | |
5c34451e | 2181 | PROCESSOR_GEODE, |
d25a2a8c | 2182 | PROCESSOR_K6, |
2183 | PROCESSOR_ATHLON, | |
2184 | PROCESSOR_PENTIUM4, | |
805e22b2 | 2185 | PROCESSOR_K8, |
0fda5f41 | 2186 | PROCESSOR_NOCONA, |
11361ecb | 2187 | PROCESSOR_CORE2, |
9db3d688 | 2188 | PROCESSOR_GENERIC32, |
2189 | PROCESSOR_GENERIC64, | |
3d775f8e | 2190 | PROCESSOR_AMDFAM10, |
d25a2a8c | 2191 | PROCESSOR_max |
2192 | }; | |
2193 | ||
706b598d | 2194 | extern enum processor_type ix86_tune; |
d25a2a8c | 2195 | extern enum processor_type ix86_arch; |
d25a2a8c | 2196 | |
2197 | enum fpmath_unit | |
2198 | { | |
2199 | FPMATH_387 = 1, | |
2200 | FPMATH_SSE = 2 | |
2201 | }; | |
2202 | ||
2203 | extern enum fpmath_unit ix86_fpmath; | |
d25a2a8c | 2204 | |
2d6788fe | 2205 | enum tls_dialect |
2206 | { | |
2207 | TLS_DIALECT_GNU, | |
4a55687c | 2208 | TLS_DIALECT_GNU2, |
2d6788fe | 2209 | TLS_DIALECT_SUN |
2210 | }; | |
2211 | ||
2212 | extern enum tls_dialect ix86_tls_dialect; | |
2d6788fe | 2213 | |
cbf58688 | 2214 | enum cmodel { |
d25a2a8c | 2215 | CM_32, /* The traditional 32-bit ABI. */ |
2216 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
2217 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
2218 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
2219 | CM_LARGE, /* No assumptions. */ | |
43e4a084 | 2220 | CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ |
5fe80ef0 | 2221 | CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ |
2222 | CM_LARGE_PIC /* No assumptions. */ | |
cbf58688 | 2223 | }; |
2224 | ||
d25a2a8c | 2225 | extern enum cmodel ix86_cmodel; |
d25a2a8c | 2226 | |
8eafd985 | 2227 | /* Size of the RED_ZONE area. */ |
2228 | #define RED_ZONE_SIZE 128 | |
2229 | /* Reserved area of the red zone for temporaries. */ | |
2230 | #define RED_ZONE_RESERVE 8 | |
25b31391 | 2231 | |
2232 | enum asm_dialect { | |
2233 | ASM_ATT, | |
2234 | ASM_INTEL | |
2235 | }; | |
d25a2a8c | 2236 | |
60b0f8fb | 2237 | extern enum asm_dialect ix86_asm_dialect; |
38413c80 | 2238 | extern unsigned int ix86_preferred_stack_boundary; |
27a7a23a | 2239 | extern unsigned int ix86_incoming_stack_boundary; |
43e4a084 | 2240 | extern int ix86_branch_cost, ix86_section_threshold; |
d25a2a8c | 2241 | |
2242 | /* Smallest class containing REGNO. */ | |
2243 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2244 | ||
1b12cfd7 | 2245 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
2246 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
0f0a601a | 2247 | extern rtx ix86_compare_emitted; |
be0c5fcb | 2248 | \f |
2249 | /* To properly truncate FP values into integers, we need to set i387 control | |
2250 | word. We can't emit proper mode switching code before reload, as spills | |
2251 | generated by reload may truncate values incorrectly, but we still can avoid | |
2252 | redundant computation of new control word by the mode switching pass. | |
2253 | The fldcw instructions are still emitted redundantly, but this is probably | |
2254 | not going to be noticeable problem, as most CPUs do have fast path for | |
d4983fea | 2255 | the sequence. |
be0c5fcb | 2256 | |
2257 | The machinery is to emit simple truncation instructions and split them | |
2258 | before reload to instructions having USEs of two memory locations that | |
2259 | are filled by this code to old and new control word. | |
d4983fea | 2260 | |
be0c5fcb | 2261 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2262 | needed. */ | |
2263 | ||
19cd29a7 | 2264 | enum ix86_entity |
2265 | { | |
2266 | I387_TRUNC = 0, | |
2267 | I387_FLOOR, | |
2268 | I387_CEIL, | |
2269 | I387_MASK_PM, | |
2270 | MAX_386_ENTITIES | |
2271 | }; | |
2272 | ||
3e883b09 | 2273 | enum ix86_stack_slot |
19cd29a7 | 2274 | { |
69ddc71a | 2275 | SLOT_VIRTUAL = 0, |
2276 | SLOT_TEMP, | |
19cd29a7 | 2277 | SLOT_CW_STORED, |
2278 | SLOT_CW_TRUNC, | |
2279 | SLOT_CW_FLOOR, | |
2280 | SLOT_CW_CEIL, | |
2281 | SLOT_CW_MASK_PM, | |
2282 | MAX_386_STACK_LOCALS | |
2283 | }; | |
be0c5fcb | 2284 | |
2285 | /* Define this macro if the port needs extra instructions inserted | |
2286 | for mode switching in an optimizing compilation. */ | |
2287 | ||
19cd29a7 | 2288 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2289 | ix86_optimize_mode_switching[(ENTITY)] | |
be0c5fcb | 2290 | |
2291 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2292 | initializer for an array of integers. Each initializer element N | |
2293 | refers to an entity that needs mode switching, and specifies the | |
2294 | number of different modes that might need to be set for this | |
2295 | entity. The position of the initializer in the initializer - | |
2296 | starting counting at zero - determines the integer that is used to | |
2297 | refer to the mode-switched entity in question. */ | |
2298 | ||
19cd29a7 | 2299 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2300 | { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
be0c5fcb | 2301 | |
2302 | /* ENTITY is an integer specifying a mode-switched entity. If | |
2303 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
2304 | return an integer value not larger than the corresponding element | |
2305 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
19cd29a7 | 2306 | must be switched into prior to the execution of INSN. */ |
2307 | ||
2308 | #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) | |
be0c5fcb | 2309 | |
2310 | /* This macro specifies the order in which modes for ENTITY are | |
2311 | processed. 0 is the highest priority. */ | |
2312 | ||
1b12cfd7 | 2313 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
be0c5fcb | 2314 | |
2315 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
2316 | is the set of hard registers live at the point where the insn(s) | |
2317 | are to be inserted. */ | |
2318 | ||
2319 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
4cf2e75a | 2320 | ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ |
19cd29a7 | 2321 | ? emit_i387_cw_initialization (MODE), 0 \ |
be0c5fcb | 2322 | : 0) |
19cd29a7 | 2323 | |
483f30d9 | 2324 | \f |
2325 | /* Avoid renaming of stack registers, as doing so in combination with | |
2326 | scheduling just increases amount of live registers at time and in | |
2327 | the turn amount of fxch instructions needed. | |
2328 | ||
d697f1db | 2329 | ??? Maybe Pentium chips benefits from renaming, someone can try.... */ |
483f30d9 | 2330 | |
1b12cfd7 | 2331 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
3cc68209 | 2332 | (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) |
be0c5fcb | 2333 | |
60206704 | 2334 | \f |
54f917d1 | 2335 | #define FASTCALL_PREFIX '@' |
6ce54148 | 2336 | \f |
2337 | struct machine_function GTY(()) | |
2338 | { | |
2339 | struct stack_local_entry *stack_locals; | |
2340 | const char *some_ld_name; | |
2341 | int save_varrargs_registers; | |
2342 | int accesses_prev_frame; | |
19cd29a7 | 2343 | int optimize_mode_switching[MAX_386_ENTITIES]; |
144c3e90 | 2344 | int needs_cld; |
2345 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue | |
2346 | expander to determine the style used. */ | |
4eda18af | 2347 | int use_fast_prologue_epilogue; |
fda56ed1 | 2348 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed |
2349 | for. */ | |
2350 | int use_fast_prologue_epilogue_nregs; | |
4a55687c | 2351 | /* If true, the current function needs the default PIC register, not |
2352 | an alternate register (on x86) and must not use the red zone (on | |
2353 | x86_64), even if it's a leaf function. We don't want the | |
2354 | function to be regarded as non-leaf because TLS calls need not | |
2355 | affect register allocation. This flag is set when a TLS call | |
2356 | instruction is expanded within a function, and never reset, even | |
2357 | if all such instructions are optimized away. Use the | |
2358 | ix86_current_function_calls_tls_descriptor macro for a better | |
2359 | approximation. */ | |
2360 | int tls_descriptor_call_expanded_p; | |
d3feb168 | 2361 | /* This value is used for amd64 targets and specifies the current abi |
2362 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
2363 | int call_abi; | |
6ce54148 | 2364 | }; |
2365 | ||
2366 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
2367 | #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) | |
2368 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
144c3e90 | 2369 | #define ix86_current_function_needs_cld (cfun->machine->needs_cld) |
4a55687c | 2370 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2371 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2372 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2373 | calls are optimized away, we try to detect cases in which it was | |
2374 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2375 | verify whether there's any such instruction live by testing that | |
2376 | REG_SP is live. */ | |
2377 | #define ix86_current_function_calls_tls_descriptor \ | |
3072d30e | 2378 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
78177281 | 2379 | |
92c473b8 | 2380 | /* Control behavior of x86_file_start. */ |
2381 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2382 | #define X86_FILE_START_FLTUSED false | |
2383 | ||
43e4a084 | 2384 | /* Flag to mark data that is in the large address area. */ |
2385 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2386 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2387 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
dd1a226e | 2388 | |
2389 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2390 | have defined always, to avoid ifdefing. */ | |
2391 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2392 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2393 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2394 | ||
2395 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2396 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2397 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2398 | ||
6202d4db | 2399 | /* Model costs for vectorizer. */ |
2400 | ||
2401 | /* Cost of conditional branch. */ | |
2402 | #undef TARG_COND_BRANCH_COST | |
2403 | #define TARG_COND_BRANCH_COST ix86_cost->branch_cost | |
2404 | ||
5f57a8b1 | 2405 | /* Enum through the target specific extra va_list types. Please, do not |
2406 | iterate the base va_list type name. */ | |
2407 | #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \ | |
2408 | (!TARGET_64BIT ? 0 : ix86_enum_va_list (IDX, PNAME, PTYPE)) | |
2409 | ||
6202d4db | 2410 | /* Cost of any scalar operation, excluding load and store. */ |
2411 | #undef TARG_SCALAR_STMT_COST | |
2412 | #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost | |
2413 | ||
2414 | /* Cost of scalar load. */ | |
2415 | #undef TARG_SCALAR_LOAD_COST | |
2416 | #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost | |
2417 | ||
2418 | /* Cost of scalar store. */ | |
2419 | #undef TARG_SCALAR_STORE_COST | |
2420 | #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost | |
2421 | ||
2422 | /* Cost of any vector operation, excluding load, store or vector to scalar | |
009b318f | 2423 | operation. */ |
6202d4db | 2424 | #undef TARG_VEC_STMT_COST |
2425 | #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost | |
2426 | ||
2427 | /* Cost of vector to scalar operation. */ | |
2428 | #undef TARG_VEC_TO_SCALAR_COST | |
2429 | #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost | |
2430 | ||
2431 | /* Cost of scalar to vector operation. */ | |
2432 | #undef TARG_SCALAR_TO_VEC_COST | |
2433 | #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost | |
2434 | ||
2435 | /* Cost of aligned vector load. */ | |
2436 | #undef TARG_VEC_LOAD_COST | |
2437 | #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost | |
2438 | ||
2439 | /* Cost of misaligned vector load. */ | |
2440 | #undef TARG_VEC_UNALIGNED_LOAD_COST | |
2441 | #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost | |
2442 | ||
2443 | /* Cost of vector store. */ | |
2444 | #undef TARG_VEC_STORE_COST | |
2445 | #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost | |
2446 | ||
2447 | /* Cost of conditional taken branch for vectorizer cost model. */ | |
2448 | #undef TARG_COND_TAKEN_BRANCH_COST | |
2449 | #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost | |
2450 | ||
2451 | /* Cost of conditional not taken branch for vectorizer cost model. */ | |
2452 | #undef TARG_COND_NOT_TAKEN_BRANCH_COST | |
2453 | #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost | |
2454 | ||
43b83681 | 2455 | /* |
2456 | Local variables: | |
2457 | version-control: t | |
2458 | End: | |
2459 | */ |