]>
Commit | Line | Data |
---|---|---|
c65ebc55 | 1 | /* Definitions of target machine for GNU compiler. |
a5544970 | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
c65ebc55 | 3 | Contributed by James E. Wilson <wilson@cygnus.com> and |
9c808aad | 4 | David Mosberger <davidm@hpl.hp.com>. |
c65ebc55 | 5 | |
3bed2930 | 6 | This file is part of GCC. |
c65ebc55 | 7 | |
3bed2930 | 8 | GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
11 | any later version. |
12 | ||
3bed2930 | 13 | GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
c65ebc55 | 21 | |
8fcc61f8 RS |
22 | #define IN_TARGET_CODE 1 |
23 | ||
c65ebc55 | 24 | #include "config.h" |
ed9ccd8a | 25 | #include "system.h" |
4977bab6 | 26 | #include "coretypes.h" |
c7131fb2 | 27 | #include "backend.h" |
e11c4407 | 28 | #include "target.h" |
c65ebc55 | 29 | #include "rtl.h" |
e11c4407 | 30 | #include "tree.h" |
e73cf9a2 | 31 | #include "memmodel.h" |
e11c4407 | 32 | #include "cfghooks.h" |
c7131fb2 | 33 | #include "df.h" |
e11c4407 AM |
34 | #include "tm_p.h" |
35 | #include "stringpool.h" | |
314e6352 | 36 | #include "attribs.h" |
e11c4407 AM |
37 | #include "optabs.h" |
38 | #include "regs.h" | |
39 | #include "emit-rtl.h" | |
40 | #include "recog.h" | |
41 | #include "diagnostic-core.h" | |
40e23961 | 42 | #include "alias.h" |
40e23961 | 43 | #include "fold-const.h" |
d8a2d370 DN |
44 | #include "stor-layout.h" |
45 | #include "calls.h" | |
46 | #include "varasm.h" | |
c65ebc55 JW |
47 | #include "output.h" |
48 | #include "insn-attr.h" | |
49 | #include "flags.h" | |
36566b39 | 50 | #include "explow.h" |
c65ebc55 | 51 | #include "expr.h" |
60393bbc | 52 | #include "cfgrtl.h" |
f2972bf8 | 53 | #include "libfuncs.h" |
2130b7fb | 54 | #include "sched-int.h" |
7b84aac0 | 55 | #include "common/common-target.h" |
08744705 | 56 | #include "langhooks.h" |
45b0be94 | 57 | #include "gimplify.h" |
4de67c26 | 58 | #include "intl.h" |
658f32fd | 59 | #include "debug.h" |
bb83aa4b | 60 | #include "params.h" |
6fb5fa3c | 61 | #include "dbgcnt.h" |
13f70342 | 62 | #include "tm-constrs.h" |
388092d5 | 63 | #include "sel-sched.h" |
69e18c09 | 64 | #include "reload.h" |
96e45421 | 65 | #include "opts.h" |
7ee2468b | 66 | #include "dumpfile.h" |
9b2b7279 | 67 | #include "builtins.h" |
c65ebc55 | 68 | |
994c5d85 | 69 | /* This file should be included last. */ |
d58627a0 RS |
70 | #include "target-def.h" |
71 | ||
c65ebc55 JW |
72 | /* This is used for communication between ASM_OUTPUT_LABEL and |
73 | ASM_OUTPUT_LABELREF. */ | |
74 | int ia64_asm_output_label = 0; | |
75 | ||
c65ebc55 | 76 | /* Register names for ia64_expand_prologue. */ |
3b572406 | 77 | static const char * const ia64_reg_numbers[96] = |
c65ebc55 JW |
78 | { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
79 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
80 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
81 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
82 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
83 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
84 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
85 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
86 | "r96", "r97", "r98", "r99", "r100","r101","r102","r103", | |
87 | "r104","r105","r106","r107","r108","r109","r110","r111", | |
88 | "r112","r113","r114","r115","r116","r117","r118","r119", | |
89 | "r120","r121","r122","r123","r124","r125","r126","r127"}; | |
90 | ||
91 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 92 | static const char * const ia64_input_reg_names[8] = |
c65ebc55 JW |
93 | { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" }; |
94 | ||
95 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 96 | static const char * const ia64_local_reg_names[80] = |
c65ebc55 JW |
97 | { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", |
98 | "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", | |
99 | "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", | |
100 | "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", | |
101 | "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", | |
102 | "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", | |
103 | "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", | |
104 | "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", | |
105 | "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", | |
106 | "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" }; | |
107 | ||
108 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 109 | static const char * const ia64_output_reg_names[8] = |
c65ebc55 JW |
110 | { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" }; |
111 | ||
c65ebc55 JW |
112 | /* Variables which are this size or smaller are put in the sdata/sbss |
113 | sections. */ | |
114 | ||
3b572406 | 115 | unsigned int ia64_section_threshold; |
30028c85 VM |
116 | |
117 | /* The following variable is used by the DFA insn scheduler. The value is | |
118 | TRUE if we do insn bundling instead of insn scheduling. */ | |
119 | int bundling_p = 0; | |
120 | ||
6fb5fa3c DB |
121 | enum ia64_frame_regs |
122 | { | |
123 | reg_fp, | |
124 | reg_save_b0, | |
125 | reg_save_pr, | |
126 | reg_save_ar_pfs, | |
127 | reg_save_ar_unat, | |
128 | reg_save_ar_lc, | |
129 | reg_save_gp, | |
130 | number_of_ia64_frame_regs | |
131 | }; | |
132 | ||
599aedd9 RH |
133 | /* Structure to be filled in by ia64_compute_frame_size with register |
134 | save masks and offsets for the current function. */ | |
135 | ||
136 | struct ia64_frame_info | |
137 | { | |
138 | HOST_WIDE_INT total_size; /* size of the stack frame, not including | |
139 | the caller's scratch area. */ | |
140 | HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */ | |
141 | HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */ | |
142 | HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */ | |
143 | HARD_REG_SET mask; /* mask of saved registers. */ | |
9c808aad | 144 | unsigned int gr_used_mask; /* mask of registers in use as gr spill |
599aedd9 RH |
145 | registers or long-term scratches. */ |
146 | int n_spilled; /* number of spilled registers. */ | |
6fb5fa3c | 147 | int r[number_of_ia64_frame_regs]; /* Frame related registers. */ |
599aedd9 RH |
148 | int n_input_regs; /* number of input registers used. */ |
149 | int n_local_regs; /* number of local registers used. */ | |
150 | int n_output_regs; /* number of output registers used. */ | |
151 | int n_rotate_regs; /* number of rotating registers used. */ | |
152 | ||
153 | char need_regstk; /* true if a .regstk directive needed. */ | |
154 | char initialized; /* true if the data is finalized. */ | |
155 | }; | |
156 | ||
157 | /* Current frame information calculated by ia64_compute_frame_size. */ | |
158 | static struct ia64_frame_info current_frame_info; | |
6fb5fa3c DB |
159 | /* The actual registers that are emitted. */ |
160 | static int emitted_frame_related_regs[number_of_ia64_frame_regs]; | |
3b572406 | 161 | \f |
9c808aad | 162 | static int ia64_first_cycle_multipass_dfa_lookahead (void); |
ce1ce33a | 163 | static void ia64_dependencies_evaluation_hook (rtx_insn *, rtx_insn *); |
9c808aad AJ |
164 | static void ia64_init_dfa_pre_cycle_insn (void); |
165 | static rtx ia64_dfa_pre_cycle_insn (void); | |
ac44248e DM |
166 | static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *, int); |
167 | static int ia64_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *); | |
048d0d36 | 168 | static void ia64_h_i_d_extended (void); |
388092d5 AB |
169 | static void * ia64_alloc_sched_context (void); |
170 | static void ia64_init_sched_context (void *, bool); | |
171 | static void ia64_set_sched_context (void *); | |
172 | static void ia64_clear_sched_context (void *); | |
173 | static void ia64_free_sched_context (void *); | |
ef4bddc2 | 174 | static int ia64_mode_to_int (machine_mode); |
048d0d36 | 175 | static void ia64_set_sched_flags (spec_info_t); |
ac44248e DM |
176 | static ds_t ia64_get_insn_spec_ds (rtx_insn *); |
177 | static ds_t ia64_get_insn_checked_ds (rtx_insn *); | |
388092d5 | 178 | static bool ia64_skip_rtx_p (const_rtx); |
ac44248e | 179 | static int ia64_speculate_insn (rtx_insn *, ds_t, rtx *); |
8e90de43 | 180 | static bool ia64_needs_block_p (ds_t); |
ac44248e | 181 | static rtx ia64_gen_spec_check (rtx_insn *, rtx_insn *, ds_t); |
048d0d36 MK |
182 | static int ia64_spec_check_p (rtx); |
183 | static int ia64_spec_check_src_p (rtx); | |
9c808aad AJ |
184 | static rtx gen_tls_get_addr (void); |
185 | static rtx gen_thread_pointer (void); | |
6fb5fa3c | 186 | static int find_gr_spill (enum ia64_frame_regs, int); |
9c808aad AJ |
187 | static int next_scratch_gr_reg (void); |
188 | static void mark_reg_gr_used_mask (rtx, void *); | |
189 | static void ia64_compute_frame_size (HOST_WIDE_INT); | |
190 | static void setup_spill_pointers (int, rtx, HOST_WIDE_INT); | |
191 | static void finish_spill_pointers (void); | |
192 | static rtx spill_restore_mem (rtx, HOST_WIDE_INT); | |
193 | static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx); | |
194 | static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT); | |
195 | static rtx gen_movdi_x (rtx, rtx, rtx); | |
196 | static rtx gen_fr_spill_x (rtx, rtx, rtx); | |
197 | static rtx gen_fr_restore_x (rtx, rtx, rtx); | |
198 | ||
930572b9 | 199 | static void ia64_option_override (void); |
7b5cbb57 | 200 | static bool ia64_can_eliminate (const int, const int); |
ef4bddc2 | 201 | static machine_mode hfa_element_mode (const_tree, bool); |
e7056ca4 RS |
202 | static void ia64_setup_incoming_varargs (cumulative_args_t, |
203 | const function_arg_info &, | |
204 | int *, int); | |
a7c81bc1 RS |
205 | static int ia64_arg_partial_bytes (cumulative_args_t, |
206 | const function_arg_info &); | |
6783fdb7 | 207 | static rtx ia64_function_arg (cumulative_args_t, const function_arg_info &); |
d5cc9181 | 208 | static rtx ia64_function_incoming_arg (cumulative_args_t, |
6783fdb7 | 209 | const function_arg_info &); |
6930c98c RS |
210 | static void ia64_function_arg_advance (cumulative_args_t, |
211 | const function_arg_info &); | |
76b0cbf8 | 212 | static pad_direction ia64_function_arg_padding (machine_mode, const_tree); |
ef4bddc2 | 213 | static unsigned int ia64_function_arg_boundary (machine_mode, |
c2ed6cf8 | 214 | const_tree); |
9c808aad | 215 | static bool ia64_function_ok_for_sibcall (tree, tree); |
586de218 | 216 | static bool ia64_return_in_memory (const_tree, const_tree); |
ba90d838 | 217 | static rtx ia64_function_value (const_tree, const_tree, bool); |
ef4bddc2 | 218 | static rtx ia64_libcall_value (machine_mode, const_rtx); |
ba90d838 | 219 | static bool ia64_function_value_regno_p (const unsigned int); |
ef4bddc2 | 220 | static int ia64_register_move_cost (machine_mode, reg_class_t, |
c21fc181 | 221 | reg_class_t); |
ef4bddc2 | 222 | static int ia64_memory_move_cost (machine_mode mode, reg_class_t, |
69e18c09 | 223 | bool); |
e548c9df | 224 | static bool ia64_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
215b063c | 225 | static int ia64_unspec_may_trap_p (const_rtx, unsigned); |
9c808aad AJ |
226 | static void fix_range (const char *); |
227 | static struct machine_function * ia64_init_machine_status (void); | |
228 | static void emit_insn_group_barriers (FILE *); | |
229 | static void emit_all_insn_group_barriers (FILE *); | |
230 | static void final_emit_insn_group_barriers (FILE *); | |
231 | static void emit_predicate_relation_info (void); | |
232 | static void ia64_reorg (void); | |
3101faab | 233 | static bool ia64_in_small_data_p (const_tree); |
658f32fd | 234 | static void process_epilogue (FILE *, rtx, bool, bool); |
9c808aad | 235 | |
9c808aad | 236 | static bool ia64_assemble_integer (rtx, unsigned int, int); |
42776416 RS |
237 | static void ia64_output_function_prologue (FILE *); |
238 | static void ia64_output_function_epilogue (FILE *); | |
9c808aad AJ |
239 | static void ia64_output_function_end_prologue (FILE *); |
240 | ||
5e50b799 | 241 | static void ia64_print_operand (FILE *, rtx, int); |
cc8ca59e | 242 | static void ia64_print_operand_address (FILE *, machine_mode, rtx); |
5e50b799 AS |
243 | static bool ia64_print_operand_punct_valid_p (unsigned char code); |
244 | ||
9c808aad | 245 | static int ia64_issue_rate (void); |
b505225b | 246 | static int ia64_adjust_cost (rtx_insn *, int, rtx_insn *, int, dw_t); |
9c808aad | 247 | static void ia64_sched_init (FILE *, int, int); |
048d0d36 MK |
248 | static void ia64_sched_init_global (FILE *, int, int); |
249 | static void ia64_sched_finish_global (FILE *, int); | |
9c808aad | 250 | static void ia64_sched_finish (FILE *, int); |
ce1ce33a DM |
251 | static int ia64_dfa_sched_reorder (FILE *, int, rtx_insn **, int *, int, int); |
252 | static int ia64_sched_reorder (FILE *, int, rtx_insn **, int *, int); | |
253 | static int ia64_sched_reorder2 (FILE *, int, rtx_insn **, int *, int); | |
ac44248e | 254 | static int ia64_variable_issue (FILE *, int, rtx_insn *, int); |
9c808aad | 255 | |
ac44248e | 256 | static void ia64_asm_unwind_emit (FILE *, rtx_insn *); |
a68b5e52 RH |
257 | static void ia64_asm_emit_except_personality (rtx); |
258 | static void ia64_asm_init_sections (void); | |
259 | ||
f0a0390e | 260 | static enum unwind_info_type ia64_debug_unwind_info (void); |
f0a0390e | 261 | |
9c808aad AJ |
262 | static struct bundle_state *get_free_bundle_state (void); |
263 | static void free_bundle_state (struct bundle_state *); | |
264 | static void initiate_bundle_states (void); | |
265 | static void finish_bundle_states (void); | |
9c808aad AJ |
266 | static int insert_bundle_state (struct bundle_state *); |
267 | static void initiate_bundle_state_table (void); | |
268 | static void finish_bundle_state_table (void); | |
269 | static int try_issue_nops (struct bundle_state *, int); | |
270 | static int try_issue_insn (struct bundle_state *, rtx); | |
b32d5189 DM |
271 | static void issue_nops_and_insn (struct bundle_state *, int, rtx_insn *, |
272 | int, int); | |
9c808aad AJ |
273 | static int get_max_pos (state_t); |
274 | static int get_template (state_t, int); | |
275 | ||
b32d5189 | 276 | static rtx_insn *get_next_important_insn (rtx_insn *, rtx_insn *); |
647d790d DM |
277 | static bool important_for_bundling_p (rtx_insn *); |
278 | static bool unknown_for_bundling_p (rtx_insn *); | |
b32d5189 | 279 | static void bundling (FILE *, int, rtx_insn *, rtx_insn *); |
9c808aad AJ |
280 | |
281 | static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
282 | HOST_WIDE_INT, tree); | |
283 | static void ia64_file_start (void); | |
812b587e | 284 | static void ia64_globalize_decl_name (FILE *, tree); |
9c808aad | 285 | |
9b580a0b RH |
286 | static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED; |
287 | static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED; | |
ef4bddc2 | 288 | static section *ia64_select_rtx_section (machine_mode, rtx, |
d6b5193b | 289 | unsigned HOST_WIDE_INT); |
fdbe66f2 EB |
290 | static void ia64_output_dwarf_dtprel (FILE *, int, rtx) |
291 | ATTRIBUTE_UNUSED; | |
abb8b19a | 292 | static unsigned int ia64_section_type_flags (tree, const char *, int); |
1f7aa7cd SE |
293 | static void ia64_init_libfuncs (void) |
294 | ATTRIBUTE_UNUSED; | |
c15c90bb ZW |
295 | static void ia64_hpux_init_libfuncs (void) |
296 | ATTRIBUTE_UNUSED; | |
6bc709c1 L |
297 | static void ia64_sysv4_init_libfuncs (void) |
298 | ATTRIBUTE_UNUSED; | |
738e7b39 RK |
299 | static void ia64_vms_init_libfuncs (void) |
300 | ATTRIBUTE_UNUSED; | |
c252db20 L |
301 | static void ia64_soft_fp_init_libfuncs (void) |
302 | ATTRIBUTE_UNUSED; | |
095a2d76 | 303 | static bool ia64_vms_valid_pointer_mode (scalar_int_mode mode) |
f2972bf8 | 304 | ATTRIBUTE_UNUSED; |
30ed9d3d TG |
305 | static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *) |
306 | ATTRIBUTE_UNUSED; | |
a5fe455b | 307 | |
d8def3cf | 308 | static bool ia64_attribute_takes_identifier_p (const_tree); |
a32767e4 | 309 | static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *); |
812b587e | 310 | static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *); |
a32767e4 | 311 | static void ia64_encode_section_info (tree, rtx, int); |
351a758b | 312 | static rtx ia64_struct_value_rtx (tree, int); |
726a989a | 313 | static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
18e2a8b8 | 314 | static bool ia64_scalar_mode_supported_p (scalar_mode mode); |
ef4bddc2 | 315 | static bool ia64_vector_mode_supported_p (machine_mode mode); |
ef4bddc2 RS |
316 | static bool ia64_legitimate_constant_p (machine_mode, rtx); |
317 | static bool ia64_legitimate_address_p (machine_mode, rtx, bool); | |
318 | static bool ia64_cannot_force_const_mem (machine_mode, rtx); | |
3101faab KG |
319 | static const char *ia64_mangle_type (const_tree); |
320 | static const char *ia64_invalid_conversion (const_tree, const_tree); | |
321 | static const char *ia64_invalid_unary_op (int, const_tree); | |
322 | static const char *ia64_invalid_binary_op (int, const_tree, const_tree); | |
ef4bddc2 | 323 | static machine_mode ia64_c_mode_for_suffix (char); |
2a1211e5 | 324 | static void ia64_trampoline_init (rtx, tree, rtx); |
2b7e2984 | 325 | static void ia64_override_options_after_change (void); |
ef4bddc2 | 326 | static bool ia64_member_type_forces_blk (const_tree, machine_mode); |
5c255b57 | 327 | |
b6ca982f | 328 | static tree ia64_fold_builtin (tree, int, tree *, bool); |
b14446e2 | 329 | static tree ia64_builtin_decl (unsigned, bool); |
ab177ad5 AS |
330 | |
331 | static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t); | |
ef1d3b57 | 332 | static fixed_size_mode ia64_get_reg_raw_mode (int regno); |
f16d3f39 JH |
333 | static section * ia64_hpux_function_section (tree, enum node_frequency, |
334 | bool, bool); | |
e6431744 | 335 | |
f151c9e1 RS |
336 | static bool ia64_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, |
337 | const vec_perm_indices &); | |
e6431744 | 338 | |
c43f4279 | 339 | static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode); |
f939c3e6 | 340 | static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode); |
99e1629f | 341 | static bool ia64_modes_tieable_p (machine_mode, machine_mode); |
0d803030 RS |
342 | static bool ia64_can_change_mode_class (machine_mode, machine_mode, |
343 | reg_class_t); | |
f939c3e6 | 344 | |
e6431744 RH |
345 | #define MAX_VECT_LEN 8 |
346 | ||
347 | struct expand_vec_perm_d | |
348 | { | |
349 | rtx target, op0, op1; | |
350 | unsigned char perm[MAX_VECT_LEN]; | |
ef4bddc2 | 351 | machine_mode vmode; |
e6431744 RH |
352 | unsigned char nelt; |
353 | bool one_operand_p; | |
354 | bool testing_p; | |
355 | }; | |
356 | ||
357 | static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d); | |
358 | ||
672a6f42 | 359 | \f |
e6542f4e RH |
360 | /* Table of valid machine attributes. */ |
361 | static const struct attribute_spec ia64_attribute_table[] = | |
362 | { | |
4849deb1 JJ |
363 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, |
364 | affects_type_identity, handler, exclude } */ | |
365 | { "syscall_linkage", 0, 0, false, true, true, false, NULL, NULL }, | |
366 | { "model", 1, 1, true, false, false, false, | |
367 | ia64_handle_model_attribute, NULL }, | |
30ed9d3d | 368 | #if TARGET_ABI_OPEN_VMS |
4849deb1 JJ |
369 | { "common_object", 1, 1, true, false, false, false, |
370 | ia64_vms_common_object_attribute, NULL }, | |
30ed9d3d | 371 | #endif |
4849deb1 JJ |
372 | { "version_id", 1, 1, true, false, false, false, |
373 | ia64_handle_version_id_attribute, NULL }, | |
374 | { NULL, 0, 0, false, false, false, false, NULL, NULL } | |
e6542f4e RH |
375 | }; |
376 | ||
672a6f42 | 377 | /* Initialize the GCC target structure. */ |
91d231cb JM |
378 | #undef TARGET_ATTRIBUTE_TABLE |
379 | #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table | |
672a6f42 | 380 | |
f6155fda SS |
381 | #undef TARGET_INIT_BUILTINS |
382 | #define TARGET_INIT_BUILTINS ia64_init_builtins | |
383 | ||
b6ca982f UB |
384 | #undef TARGET_FOLD_BUILTIN |
385 | #define TARGET_FOLD_BUILTIN ia64_fold_builtin | |
386 | ||
f6155fda SS |
387 | #undef TARGET_EXPAND_BUILTIN |
388 | #define TARGET_EXPAND_BUILTIN ia64_expand_builtin | |
389 | ||
b14446e2 SE |
390 | #undef TARGET_BUILTIN_DECL |
391 | #define TARGET_BUILTIN_DECL ia64_builtin_decl | |
392 | ||
301d03af RS |
393 | #undef TARGET_ASM_BYTE_OP |
394 | #define TARGET_ASM_BYTE_OP "\tdata1\t" | |
395 | #undef TARGET_ASM_ALIGNED_HI_OP | |
396 | #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t" | |
397 | #undef TARGET_ASM_ALIGNED_SI_OP | |
398 | #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t" | |
399 | #undef TARGET_ASM_ALIGNED_DI_OP | |
400 | #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t" | |
401 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
402 | #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t" | |
403 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
404 | #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t" | |
405 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
406 | #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t" | |
407 | #undef TARGET_ASM_INTEGER | |
408 | #define TARGET_ASM_INTEGER ia64_assemble_integer | |
409 | ||
930572b9 AS |
410 | #undef TARGET_OPTION_OVERRIDE |
411 | #define TARGET_OPTION_OVERRIDE ia64_option_override | |
412 | ||
08c148a8 NB |
413 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
414 | #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue | |
b4c25db2 NB |
415 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE |
416 | #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue | |
08c148a8 NB |
417 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
418 | #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue | |
419 | ||
5e50b799 AS |
420 | #undef TARGET_PRINT_OPERAND |
421 | #define TARGET_PRINT_OPERAND ia64_print_operand | |
422 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
423 | #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address | |
424 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
425 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p | |
426 | ||
ae46c4e0 RH |
427 | #undef TARGET_IN_SMALL_DATA_P |
428 | #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p | |
429 | ||
b505225b TS |
430 | #undef TARGET_SCHED_ADJUST_COST |
431 | #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost | |
c237e94a ZW |
432 | #undef TARGET_SCHED_ISSUE_RATE |
433 | #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate | |
434 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
435 | #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue | |
436 | #undef TARGET_SCHED_INIT | |
437 | #define TARGET_SCHED_INIT ia64_sched_init | |
438 | #undef TARGET_SCHED_FINISH | |
439 | #define TARGET_SCHED_FINISH ia64_sched_finish | |
048d0d36 MK |
440 | #undef TARGET_SCHED_INIT_GLOBAL |
441 | #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global | |
442 | #undef TARGET_SCHED_FINISH_GLOBAL | |
443 | #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global | |
c237e94a ZW |
444 | #undef TARGET_SCHED_REORDER |
445 | #define TARGET_SCHED_REORDER ia64_sched_reorder | |
446 | #undef TARGET_SCHED_REORDER2 | |
447 | #define TARGET_SCHED_REORDER2 ia64_sched_reorder2 | |
c237e94a | 448 | |
30028c85 VM |
449 | #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK |
450 | #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook | |
451 | ||
30028c85 VM |
452 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
453 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead | |
454 | ||
455 | #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN | |
456 | #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn | |
457 | #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN | |
458 | #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn | |
459 | ||
460 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD | |
461 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\ | |
462 | ia64_first_cycle_multipass_dfa_lookahead_guard | |
463 | ||
464 | #undef TARGET_SCHED_DFA_NEW_CYCLE | |
465 | #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle | |
466 | ||
048d0d36 MK |
467 | #undef TARGET_SCHED_H_I_D_EXTENDED |
468 | #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended | |
469 | ||
388092d5 AB |
470 | #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT |
471 | #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context | |
472 | ||
473 | #undef TARGET_SCHED_INIT_SCHED_CONTEXT | |
474 | #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context | |
475 | ||
476 | #undef TARGET_SCHED_SET_SCHED_CONTEXT | |
477 | #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context | |
478 | ||
479 | #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT | |
480 | #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context | |
481 | ||
482 | #undef TARGET_SCHED_FREE_SCHED_CONTEXT | |
483 | #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context | |
484 | ||
048d0d36 MK |
485 | #undef TARGET_SCHED_SET_SCHED_FLAGS |
486 | #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags | |
487 | ||
388092d5 AB |
488 | #undef TARGET_SCHED_GET_INSN_SPEC_DS |
489 | #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds | |
490 | ||
491 | #undef TARGET_SCHED_GET_INSN_CHECKED_DS | |
492 | #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds | |
493 | ||
048d0d36 MK |
494 | #undef TARGET_SCHED_SPECULATE_INSN |
495 | #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn | |
496 | ||
497 | #undef TARGET_SCHED_NEEDS_BLOCK_P | |
498 | #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p | |
499 | ||
e855c69d | 500 | #undef TARGET_SCHED_GEN_SPEC_CHECK |
388092d5 | 501 | #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check |
048d0d36 | 502 | |
388092d5 AB |
503 | #undef TARGET_SCHED_SKIP_RTX_P |
504 | #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p | |
505 | ||
599aedd9 RH |
506 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
507 | #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall | |
78a52f11 RH |
508 | #undef TARGET_ARG_PARTIAL_BYTES |
509 | #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes | |
ffa88471 SE |
510 | #undef TARGET_FUNCTION_ARG |
511 | #define TARGET_FUNCTION_ARG ia64_function_arg | |
512 | #undef TARGET_FUNCTION_INCOMING_ARG | |
513 | #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg | |
514 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
515 | #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance | |
76b0cbf8 RS |
516 | #undef TARGET_FUNCTION_ARG_PADDING |
517 | #define TARGET_FUNCTION_ARG_PADDING ia64_function_arg_padding | |
c2ed6cf8 NF |
518 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
519 | #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary | |
599aedd9 | 520 | |
c590b625 RH |
521 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
522 | #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk | |
3961e8fe | 523 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 524 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 525 | |
1bc7c5b6 ZW |
526 | #undef TARGET_ASM_FILE_START |
527 | #define TARGET_ASM_FILE_START ia64_file_start | |
528 | ||
812b587e SE |
529 | #undef TARGET_ASM_GLOBALIZE_DECL_NAME |
530 | #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name | |
531 | ||
de8f4b07 AS |
532 | #undef TARGET_REGISTER_MOVE_COST |
533 | #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost | |
69e18c09 AS |
534 | #undef TARGET_MEMORY_MOVE_COST |
535 | #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost | |
3c50106f RH |
536 | #undef TARGET_RTX_COSTS |
537 | #define TARGET_RTX_COSTS ia64_rtx_costs | |
dcefdf67 | 538 | #undef TARGET_ADDRESS_COST |
b413068c | 539 | #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 |
3c50106f | 540 | |
215b063c PB |
541 | #undef TARGET_UNSPEC_MAY_TRAP_P |
542 | #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p | |
543 | ||
18dbd950 RS |
544 | #undef TARGET_MACHINE_DEPENDENT_REORG |
545 | #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg | |
546 | ||
a32767e4 DM |
547 | #undef TARGET_ENCODE_SECTION_INFO |
548 | #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info | |
549 | ||
abb8b19a AM |
550 | #undef TARGET_SECTION_TYPE_FLAGS |
551 | #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags | |
552 | ||
fdbe66f2 EB |
553 | #ifdef HAVE_AS_TLS |
554 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
555 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel | |
556 | #endif | |
557 | ||
351a758b KH |
558 | /* ??? Investigate. */ |
559 | #if 0 | |
560 | #undef TARGET_PROMOTE_PROTOTYPES | |
561 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
562 | #endif | |
563 | ||
ba90d838 AS |
564 | #undef TARGET_FUNCTION_VALUE |
565 | #define TARGET_FUNCTION_VALUE ia64_function_value | |
566 | #undef TARGET_LIBCALL_VALUE | |
567 | #define TARGET_LIBCALL_VALUE ia64_libcall_value | |
568 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
569 | #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p | |
570 | ||
351a758b KH |
571 | #undef TARGET_STRUCT_VALUE_RTX |
572 | #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx | |
573 | #undef TARGET_RETURN_IN_MEMORY | |
574 | #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory | |
351a758b KH |
575 | #undef TARGET_SETUP_INCOMING_VARARGS |
576 | #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs | |
577 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
578 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
fe984136 RH |
579 | #undef TARGET_MUST_PASS_IN_STACK |
580 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
ffa88471 SE |
581 | #undef TARGET_GET_RAW_RESULT_MODE |
582 | #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode | |
583 | #undef TARGET_GET_RAW_ARG_MODE | |
584 | #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode | |
351a758b | 585 | |
d9886a9e L |
586 | #undef TARGET_MEMBER_TYPE_FORCES_BLK |
587 | #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk | |
588 | ||
cd3ce9b4 JM |
589 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
590 | #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg | |
591 | ||
38f8b050 | 592 | #undef TARGET_ASM_UNWIND_EMIT |
a68b5e52 RH |
593 | #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit |
594 | #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY | |
595 | #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality | |
596 | #undef TARGET_ASM_INIT_SECTIONS | |
597 | #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections | |
951120ea | 598 | |
f0a0390e RH |
599 | #undef TARGET_DEBUG_UNWIND_INFO |
600 | #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info | |
f0a0390e | 601 | |
88ed5ef5 SE |
602 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
603 | #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p | |
f61134e8 RH |
604 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
605 | #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p | |
88ed5ef5 | 606 | |
1a627b35 RS |
607 | #undef TARGET_LEGITIMATE_CONSTANT_P |
608 | #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p | |
903a9601 AS |
609 | #undef TARGET_LEGITIMATE_ADDRESS_P |
610 | #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p | |
1a627b35 | 611 | |
d81db636 SB |
612 | #undef TARGET_LRA_P |
613 | #define TARGET_LRA_P hook_bool_void_false | |
614 | ||
5e6c8b64 RH |
615 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
616 | #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem | |
617 | ||
608063c3 JB |
618 | #undef TARGET_MANGLE_TYPE |
619 | #define TARGET_MANGLE_TYPE ia64_mangle_type | |
cac24f06 | 620 | |
4de67c26 JM |
621 | #undef TARGET_INVALID_CONVERSION |
622 | #define TARGET_INVALID_CONVERSION ia64_invalid_conversion | |
623 | #undef TARGET_INVALID_UNARY_OP | |
624 | #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op | |
625 | #undef TARGET_INVALID_BINARY_OP | |
626 | #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op | |
627 | ||
a31fa2e0 SE |
628 | #undef TARGET_C_MODE_FOR_SUFFIX |
629 | #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix | |
630 | ||
7b5cbb57 AS |
631 | #undef TARGET_CAN_ELIMINATE |
632 | #define TARGET_CAN_ELIMINATE ia64_can_eliminate | |
633 | ||
2a1211e5 RH |
634 | #undef TARGET_TRAMPOLINE_INIT |
635 | #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init | |
636 | ||
1d0216c8 RS |
637 | #undef TARGET_CAN_USE_DOLOOP_P |
638 | #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost | |
810d71d0 | 639 | #undef TARGET_INVALID_WITHIN_DOLOOP |
ac44248e | 640 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null |
810d71d0 | 641 | |
2b7e2984 SE |
642 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
643 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change | |
644 | ||
ab177ad5 AS |
645 | #undef TARGET_PREFERRED_RELOAD_CLASS |
646 | #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class | |
647 | ||
2ba42841 AO |
648 | #undef TARGET_DELAY_SCHED2 |
649 | #define TARGET_DELAY_SCHED2 true | |
650 | ||
651 | /* Variable tracking should be run after all optimizations which | |
652 | change order of insns. It also needs a valid CFG. */ | |
653 | #undef TARGET_DELAY_VARTRACK | |
654 | #define TARGET_DELAY_VARTRACK true | |
655 | ||
f151c9e1 RS |
656 | #undef TARGET_VECTORIZE_VEC_PERM_CONST |
657 | #define TARGET_VECTORIZE_VEC_PERM_CONST ia64_vectorize_vec_perm_const | |
e6431744 | 658 | |
d8def3cf JJ |
659 | #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P |
660 | #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P ia64_attribute_takes_identifier_p | |
661 | ||
86f98087 EB |
662 | #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS |
663 | #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 0 | |
664 | ||
c43f4279 RS |
665 | #undef TARGET_HARD_REGNO_NREGS |
666 | #define TARGET_HARD_REGNO_NREGS ia64_hard_regno_nregs | |
f939c3e6 RS |
667 | #undef TARGET_HARD_REGNO_MODE_OK |
668 | #define TARGET_HARD_REGNO_MODE_OK ia64_hard_regno_mode_ok | |
669 | ||
99e1629f RS |
670 | #undef TARGET_MODES_TIEABLE_P |
671 | #define TARGET_MODES_TIEABLE_P ia64_modes_tieable_p | |
672 | ||
0d803030 RS |
673 | #undef TARGET_CAN_CHANGE_MODE_CLASS |
674 | #define TARGET_CAN_CHANGE_MODE_CLASS ia64_can_change_mode_class | |
675 | ||
58e17cf8 RS |
676 | #undef TARGET_CONSTANT_ALIGNMENT |
677 | #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings | |
678 | ||
f6897b10 | 679 | struct gcc_target targetm = TARGET_INITIALIZER; |
3b572406 | 680 | \f |
d8def3cf JJ |
681 | /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain |
682 | identifier as an argument, so the front end shouldn't look it up. */ | |
683 | ||
684 | static bool | |
685 | ia64_attribute_takes_identifier_p (const_tree attr_id) | |
686 | { | |
687 | if (is_attribute_p ("model", attr_id)) | |
688 | return true; | |
689 | #if TARGET_ABI_OPEN_VMS | |
690 | if (is_attribute_p ("common_object", attr_id)) | |
691 | return true; | |
692 | #endif | |
693 | return false; | |
694 | } | |
695 | ||
a32767e4 DM |
696 | typedef enum |
697 | { | |
698 | ADDR_AREA_NORMAL, /* normal address area */ | |
699 | ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */ | |
700 | } | |
701 | ia64_addr_area; | |
702 | ||
703 | static GTY(()) tree small_ident1; | |
704 | static GTY(()) tree small_ident2; | |
705 | ||
706 | static void | |
707 | init_idents (void) | |
708 | { | |
709 | if (small_ident1 == 0) | |
710 | { | |
711 | small_ident1 = get_identifier ("small"); | |
712 | small_ident2 = get_identifier ("__small__"); | |
713 | } | |
714 | } | |
715 | ||
716 | /* Retrieve the address area that has been chosen for the given decl. */ | |
717 | ||
718 | static ia64_addr_area | |
719 | ia64_get_addr_area (tree decl) | |
720 | { | |
721 | tree model_attr; | |
722 | ||
723 | model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); | |
724 | if (model_attr) | |
725 | { | |
726 | tree id; | |
727 | ||
728 | init_idents (); | |
729 | id = TREE_VALUE (TREE_VALUE (model_attr)); | |
730 | if (id == small_ident1 || id == small_ident2) | |
731 | return ADDR_AREA_SMALL; | |
732 | } | |
733 | return ADDR_AREA_NORMAL; | |
734 | } | |
735 | ||
736 | static tree | |
f61134e8 RH |
737 | ia64_handle_model_attribute (tree *node, tree name, tree args, |
738 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
a32767e4 DM |
739 | { |
740 | ia64_addr_area addr_area = ADDR_AREA_NORMAL; | |
741 | ia64_addr_area area; | |
742 | tree arg, decl = *node; | |
743 | ||
744 | init_idents (); | |
745 | arg = TREE_VALUE (args); | |
746 | if (arg == small_ident1 || arg == small_ident2) | |
747 | { | |
748 | addr_area = ADDR_AREA_SMALL; | |
749 | } | |
750 | else | |
751 | { | |
29d08eba JM |
752 | warning (OPT_Wattributes, "invalid argument of %qE attribute", |
753 | name); | |
a32767e4 DM |
754 | *no_add_attrs = true; |
755 | } | |
756 | ||
757 | switch (TREE_CODE (decl)) | |
758 | { | |
759 | case VAR_DECL: | |
760 | if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl)) | |
761 | == FUNCTION_DECL) | |
762 | && !TREE_STATIC (decl)) | |
763 | { | |
c5d75364 MLI |
764 | error_at (DECL_SOURCE_LOCATION (decl), |
765 | "an address area attribute cannot be specified for " | |
766 | "local variables"); | |
a32767e4 DM |
767 | *no_add_attrs = true; |
768 | } | |
769 | area = ia64_get_addr_area (decl); | |
770 | if (area != ADDR_AREA_NORMAL && addr_area != area) | |
771 | { | |
dee15844 JM |
772 | error ("address area of %q+D conflicts with previous " |
773 | "declaration", decl); | |
a32767e4 DM |
774 | *no_add_attrs = true; |
775 | } | |
776 | break; | |
777 | ||
778 | case FUNCTION_DECL: | |
c5d75364 | 779 | error_at (DECL_SOURCE_LOCATION (decl), |
d575725b L |
780 | "address area attribute cannot be specified for " |
781 | "functions"); | |
a32767e4 DM |
782 | *no_add_attrs = true; |
783 | break; | |
784 | ||
785 | default: | |
29d08eba JM |
786 | warning (OPT_Wattributes, "%qE attribute ignored", |
787 | name); | |
a32767e4 DM |
788 | *no_add_attrs = true; |
789 | break; | |
790 | } | |
791 | ||
792 | return NULL_TREE; | |
793 | } | |
794 | ||
30ed9d3d TG |
795 | /* Part of the low level implementation of DEC Ada pragma Common_Object which |
796 | enables the shared use of variables stored in overlaid linker areas | |
797 | corresponding to the use of Fortran COMMON. */ | |
798 | ||
799 | static tree | |
800 | ia64_vms_common_object_attribute (tree *node, tree name, tree args, | |
801 | int flags ATTRIBUTE_UNUSED, | |
802 | bool *no_add_attrs) | |
803 | { | |
804 | tree decl = *node; | |
fe5798c0 TG |
805 | tree id; |
806 | ||
807 | gcc_assert (DECL_P (decl)); | |
30ed9d3d TG |
808 | |
809 | DECL_COMMON (decl) = 1; | |
810 | id = TREE_VALUE (args); | |
fe5798c0 | 811 | if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST) |
30ed9d3d | 812 | { |
fe5798c0 | 813 | error ("%qE attribute requires a string constant argument", name); |
30ed9d3d TG |
814 | *no_add_attrs = true; |
815 | return NULL_TREE; | |
816 | } | |
30ed9d3d TG |
817 | return NULL_TREE; |
818 | } | |
819 | ||
820 | /* Part of the low level implementation of DEC Ada pragma Common_Object. */ | |
821 | ||
822 | void | |
823 | ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name, | |
824 | unsigned HOST_WIDE_INT size, | |
825 | unsigned int align) | |
826 | { | |
827 | tree attr = DECL_ATTRIBUTES (decl); | |
828 | ||
fe5798c0 | 829 | if (attr) |
30ed9d3d | 830 | attr = lookup_attribute ("common_object", attr); |
fe5798c0 | 831 | if (attr) |
30ed9d3d | 832 | { |
fe5798c0 TG |
833 | tree id = TREE_VALUE (TREE_VALUE (attr)); |
834 | const char *name; | |
30ed9d3d | 835 | |
fe5798c0 TG |
836 | if (TREE_CODE (id) == IDENTIFIER_NODE) |
837 | name = IDENTIFIER_POINTER (id); | |
838 | else if (TREE_CODE (id) == STRING_CST) | |
839 | name = TREE_STRING_POINTER (id); | |
840 | else | |
841 | abort (); | |
30ed9d3d | 842 | |
fe5798c0 | 843 | fprintf (file, "\t.vms_common\t\"%s\",", name); |
30ed9d3d | 844 | } |
fe5798c0 TG |
845 | else |
846 | fprintf (file, "%s", COMMON_ASM_OP); | |
30ed9d3d | 847 | |
fe5798c0 TG |
848 | /* Code from elfos.h. */ |
849 | assemble_name (file, name); | |
16998094 | 850 | fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED",%u", |
fe5798c0 | 851 | size, align / BITS_PER_UNIT); |
30ed9d3d | 852 | |
fe5798c0 | 853 | fputc ('\n', file); |
30ed9d3d TG |
854 | } |
855 | ||
a32767e4 DM |
856 | static void |
857 | ia64_encode_addr_area (tree decl, rtx symbol) | |
858 | { | |
859 | int flags; | |
860 | ||
861 | flags = SYMBOL_REF_FLAGS (symbol); | |
862 | switch (ia64_get_addr_area (decl)) | |
863 | { | |
864 | case ADDR_AREA_NORMAL: break; | |
865 | case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break; | |
e820471b | 866 | default: gcc_unreachable (); |
a32767e4 DM |
867 | } |
868 | SYMBOL_REF_FLAGS (symbol) = flags; | |
869 | } | |
870 | ||
871 | static void | |
872 | ia64_encode_section_info (tree decl, rtx rtl, int first) | |
873 | { | |
874 | default_encode_section_info (decl, rtl, first); | |
875 | ||
2897f1d4 | 876 | /* Careful not to prod global register variables. */ |
a32767e4 | 877 | if (TREE_CODE (decl) == VAR_DECL |
2897f1d4 L |
878 | && GET_CODE (DECL_RTL (decl)) == MEM |
879 | && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF | |
a32767e4 DM |
880 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) |
881 | ia64_encode_addr_area (decl, XEXP (rtl, 0)); | |
882 | } | |
883 | \f | |
557b9df5 RH |
884 | /* Return 1 if the operands of a move are ok. */ |
885 | ||
886 | int | |
9c808aad | 887 | ia64_move_ok (rtx dst, rtx src) |
557b9df5 RH |
888 | { |
889 | /* If we're under init_recog_no_volatile, we'll not be able to use | |
890 | memory_operand. So check the code directly and don't worry about | |
891 | the validity of the underlying address, which should have been | |
892 | checked elsewhere anyway. */ | |
893 | if (GET_CODE (dst) != MEM) | |
894 | return 1; | |
895 | if (GET_CODE (src) == MEM) | |
896 | return 0; | |
897 | if (register_operand (src, VOIDmode)) | |
898 | return 1; | |
899 | ||
900 | /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */ | |
901 | if (INTEGRAL_MODE_P (GET_MODE (dst))) | |
902 | return src == const0_rtx; | |
903 | else | |
13f70342 | 904 | return satisfies_constraint_G (src); |
557b9df5 | 905 | } |
9b7bf67d | 906 | |
a71aef0b JB |
907 | /* Return 1 if the operands are ok for a floating point load pair. */ |
908 | ||
909 | int | |
910 | ia64_load_pair_ok (rtx dst, rtx src) | |
911 | { | |
22be5918 EB |
912 | /* ??? There is a thinko in the implementation of the "x" constraint and the |
913 | FP_REGS class. The constraint will also reject (reg f30:TI) so we must | |
914 | also return false for it. */ | |
915 | if (GET_CODE (dst) != REG | |
916 | || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1))) | |
a71aef0b JB |
917 | return 0; |
918 | if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src)) | |
919 | return 0; | |
920 | switch (GET_CODE (XEXP (src, 0))) | |
921 | { | |
922 | case REG: | |
923 | case POST_INC: | |
924 | break; | |
925 | case POST_DEC: | |
926 | return 0; | |
927 | case POST_MODIFY: | |
928 | { | |
929 | rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1); | |
930 | ||
931 | if (GET_CODE (adjust) != CONST_INT | |
932 | || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src))) | |
933 | return 0; | |
934 | } | |
935 | break; | |
936 | default: | |
937 | abort (); | |
938 | } | |
939 | return 1; | |
940 | } | |
941 | ||
08744705 | 942 | int |
9c808aad | 943 | addp4_optimize_ok (rtx op1, rtx op2) |
08744705 | 944 | { |
08744705 SE |
945 | return (basereg_operand (op1, GET_MODE(op1)) != |
946 | basereg_operand (op2, GET_MODE(op2))); | |
947 | } | |
948 | ||
9e4f94de | 949 | /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction. |
041f25e6 RH |
950 | Return the length of the field, or <= 0 on failure. */ |
951 | ||
952 | int | |
9c808aad | 953 | ia64_depz_field_mask (rtx rop, rtx rshift) |
041f25e6 RH |
954 | { |
955 | unsigned HOST_WIDE_INT op = INTVAL (rop); | |
956 | unsigned HOST_WIDE_INT shift = INTVAL (rshift); | |
957 | ||
958 | /* Get rid of the zero bits we're shifting in. */ | |
959 | op >>= shift; | |
960 | ||
961 | /* We must now have a solid block of 1's at bit 0. */ | |
962 | return exact_log2 (op + 1); | |
963 | } | |
964 | ||
5e6c8b64 RH |
965 | /* Return the TLS model to use for ADDR. */ |
966 | ||
967 | static enum tls_model | |
968 | tls_symbolic_operand_type (rtx addr) | |
969 | { | |
81f40b79 | 970 | enum tls_model tls_kind = TLS_MODEL_NONE; |
5e6c8b64 RH |
971 | |
972 | if (GET_CODE (addr) == CONST) | |
973 | { | |
974 | if (GET_CODE (XEXP (addr, 0)) == PLUS | |
975 | && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF) | |
976 | tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0)); | |
977 | } | |
978 | else if (GET_CODE (addr) == SYMBOL_REF) | |
979 | tls_kind = SYMBOL_REF_TLS_MODEL (addr); | |
980 | ||
981 | return tls_kind; | |
982 | } | |
983 | ||
903a9601 AS |
984 | /* Returns true if REG (assumed to be a `reg' RTX) is valid for use |
985 | as a base register. */ | |
986 | ||
987 | static inline bool | |
988 | ia64_reg_ok_for_base_p (const_rtx reg, bool strict) | |
989 | { | |
990 | if (strict | |
991 | && REGNO_OK_FOR_BASE_P (REGNO (reg))) | |
992 | return true; | |
993 | else if (!strict | |
994 | && (GENERAL_REGNO_P (REGNO (reg)) | |
995 | || !HARD_REGISTER_P (reg))) | |
996 | return true; | |
997 | else | |
998 | return false; | |
999 | } | |
1000 | ||
1001 | static bool | |
1002 | ia64_legitimate_address_reg (const_rtx reg, bool strict) | |
1003 | { | |
1004 | if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict)) | |
1005 | || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0)) | |
1006 | && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict))) | |
1007 | return true; | |
1008 | ||
1009 | return false; | |
1010 | } | |
1011 | ||
1012 | static bool | |
1013 | ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict) | |
1014 | { | |
1015 | if (GET_CODE (disp) == PLUS | |
1016 | && rtx_equal_p (reg, XEXP (disp, 0)) | |
1017 | && (ia64_legitimate_address_reg (XEXP (disp, 1), strict) | |
1018 | || (CONST_INT_P (XEXP (disp, 1)) | |
1019 | && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255)))) | |
1020 | return true; | |
1021 | ||
1022 | return false; | |
1023 | } | |
1024 | ||
1025 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ | |
1026 | ||
1027 | static bool | |
ef4bddc2 | 1028 | ia64_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
903a9601 AS |
1029 | rtx x, bool strict) |
1030 | { | |
1031 | if (ia64_legitimate_address_reg (x, strict)) | |
1032 | return true; | |
1033 | else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
1034 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
1035 | && XEXP (x, 0) != arg_pointer_rtx) | |
1036 | return true; | |
1037 | else if (GET_CODE (x) == POST_MODIFY | |
1038 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
1039 | && XEXP (x, 0) != arg_pointer_rtx | |
1040 | && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict)) | |
1041 | return true; | |
1042 | else | |
1043 | return false; | |
1044 | } | |
1045 | ||
5e6c8b64 RH |
1046 | /* Return true if X is a constant that is valid for some immediate |
1047 | field in an instruction. */ | |
1048 | ||
1a627b35 | 1049 | static bool |
ef4bddc2 | 1050 | ia64_legitimate_constant_p (machine_mode mode, rtx x) |
5e6c8b64 RH |
1051 | { |
1052 | switch (GET_CODE (x)) | |
1053 | { | |
1054 | case CONST_INT: | |
1055 | case LABEL_REF: | |
1056 | return true; | |
1057 | ||
1058 | case CONST_DOUBLE: | |
1a627b35 | 1059 | if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode) |
5e6c8b64 | 1060 | return true; |
13f70342 | 1061 | return satisfies_constraint_G (x); |
5e6c8b64 RH |
1062 | |
1063 | case CONST: | |
1064 | case SYMBOL_REF: | |
d0970db2 JW |
1065 | /* ??? Short term workaround for PR 28490. We must make the code here |
1066 | match the code in ia64_expand_move and move_operand, even though they | |
1067 | are both technically wrong. */ | |
1068 | if (tls_symbolic_operand_type (x) == 0) | |
1069 | { | |
1070 | HOST_WIDE_INT addend = 0; | |
1071 | rtx op = x; | |
1072 | ||
1073 | if (GET_CODE (op) == CONST | |
1074 | && GET_CODE (XEXP (op, 0)) == PLUS | |
1075 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT) | |
1076 | { | |
1077 | addend = INTVAL (XEXP (XEXP (op, 0), 1)); | |
1078 | op = XEXP (XEXP (op, 0), 0); | |
1079 | } | |
1080 | ||
1a627b35 RS |
1081 | if (any_offset_symbol_operand (op, mode) |
1082 | || function_operand (op, mode)) | |
7ab62966 | 1083 | return true; |
1a627b35 | 1084 | if (aligned_offset_symbol_operand (op, mode)) |
d0970db2 JW |
1085 | return (addend & 0x3fff) == 0; |
1086 | return false; | |
1087 | } | |
1088 | return false; | |
5e6c8b64 | 1089 | |
b4e3537b | 1090 | case CONST_VECTOR: |
1a627b35 RS |
1091 | if (mode == V2SFmode) |
1092 | return satisfies_constraint_Y (x); | |
b4e3537b | 1093 | |
1a627b35 RS |
1094 | return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT |
1095 | && GET_MODE_SIZE (mode) <= 8); | |
b4e3537b | 1096 | |
5e6c8b64 RH |
1097 | default: |
1098 | return false; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | /* Don't allow TLS addresses to get spilled to memory. */ | |
1103 | ||
1104 | static bool | |
ef4bddc2 | 1105 | ia64_cannot_force_const_mem (machine_mode mode, rtx x) |
5e6c8b64 | 1106 | { |
fbbf66e7 | 1107 | if (mode == RFmode) |
103a6411 | 1108 | return true; |
5e6c8b64 RH |
1109 | return tls_symbolic_operand_type (x) != 0; |
1110 | } | |
1111 | ||
9b7bf67d | 1112 | /* Expand a symbolic constant load. */ |
9b7bf67d | 1113 | |
5e6c8b64 | 1114 | bool |
9c808aad | 1115 | ia64_expand_load_address (rtx dest, rtx src) |
9b7bf67d | 1116 | { |
e820471b | 1117 | gcc_assert (GET_CODE (dest) == REG); |
7b6e506e | 1118 | |
ae49d6e5 RH |
1119 | /* ILP32 mode still loads 64-bits of data from the GOT. This avoids |
1120 | having to pointer-extend the value afterward. Other forms of address | |
1121 | computation below are also more natural to compute as 64-bit quantities. | |
1122 | If we've been given an SImode destination register, change it. */ | |
1123 | if (GET_MODE (dest) != Pmode) | |
38ae7651 RS |
1124 | dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), |
1125 | byte_lowpart_offset (Pmode, GET_MODE (dest))); | |
ae49d6e5 | 1126 | |
5e6c8b64 RH |
1127 | if (TARGET_NO_PIC) |
1128 | return false; | |
1129 | if (small_addr_symbolic_operand (src, VOIDmode)) | |
1130 | return false; | |
1131 | ||
1132 | if (TARGET_AUTO_PIC) | |
1133 | emit_insn (gen_load_gprel64 (dest, src)); | |
1cdbd630 | 1134 | else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src)) |
5e6c8b64 | 1135 | emit_insn (gen_load_fptr (dest, src)); |
21515593 | 1136 | else if (sdata_symbolic_operand (src, VOIDmode)) |
5e6c8b64 | 1137 | emit_insn (gen_load_gprel (dest, src)); |
face88a1 ST |
1138 | else if (local_symbolic_operand64 (src, VOIDmode)) |
1139 | { | |
1140 | /* We want to use @gprel rather than @ltoff relocations for local | |
1141 | symbols: | |
1142 | - @gprel does not require dynamic linker | |
1143 | - and does not use .sdata section | |
1144 | https://gcc.gnu.org/bugzilla/60465 */ | |
1145 | emit_insn (gen_load_gprel64 (dest, src)); | |
1146 | } | |
5e6c8b64 | 1147 | else |
21515593 | 1148 | { |
5e6c8b64 RH |
1149 | HOST_WIDE_INT addend = 0; |
1150 | rtx tmp; | |
21515593 | 1151 | |
5e6c8b64 RH |
1152 | /* We did split constant offsets in ia64_expand_move, and we did try |
1153 | to keep them split in move_operand, but we also allowed reload to | |
1154 | rematerialize arbitrary constants rather than spill the value to | |
1155 | the stack and reload it. So we have to be prepared here to split | |
1156 | them apart again. */ | |
1157 | if (GET_CODE (src) == CONST) | |
1158 | { | |
1159 | HOST_WIDE_INT hi, lo; | |
9b7bf67d | 1160 | |
5e6c8b64 RH |
1161 | hi = INTVAL (XEXP (XEXP (src, 0), 1)); |
1162 | lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000; | |
1163 | hi = hi - lo; | |
9b7bf67d | 1164 | |
5e6c8b64 RH |
1165 | if (lo != 0) |
1166 | { | |
1167 | addend = lo; | |
0a81f074 | 1168 | src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi); |
5e6c8b64 RH |
1169 | } |
1170 | } | |
ae49d6e5 RH |
1171 | |
1172 | tmp = gen_rtx_HIGH (Pmode, src); | |
1173 | tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx); | |
f7df4a84 | 1174 | emit_insn (gen_rtx_SET (dest, tmp)); |
ae49d6e5 | 1175 | |
1f88caaa | 1176 | tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src); |
f7df4a84 | 1177 | emit_insn (gen_rtx_SET (dest, tmp)); |
5e6c8b64 RH |
1178 | |
1179 | if (addend) | |
1180 | { | |
1181 | tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend)); | |
f7df4a84 | 1182 | emit_insn (gen_rtx_SET (dest, tmp)); |
5e6c8b64 | 1183 | } |
ae49d6e5 | 1184 | } |
5e6c8b64 RH |
1185 | |
1186 | return true; | |
9b7bf67d | 1187 | } |
97e242b0 | 1188 | |
e2500fed | 1189 | static GTY(()) rtx gen_tls_tga; |
7b6e506e | 1190 | static rtx |
9c808aad | 1191 | gen_tls_get_addr (void) |
7b6e506e | 1192 | { |
e2500fed | 1193 | if (!gen_tls_tga) |
21515593 | 1194 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); |
e2500fed | 1195 | return gen_tls_tga; |
7b6e506e RH |
1196 | } |
1197 | ||
e2500fed | 1198 | static GTY(()) rtx thread_pointer_rtx; |
7b6e506e | 1199 | static rtx |
9c808aad | 1200 | gen_thread_pointer (void) |
7b6e506e | 1201 | { |
e2500fed | 1202 | if (!thread_pointer_rtx) |
389fdba0 | 1203 | thread_pointer_rtx = gen_rtx_REG (Pmode, 13); |
135ca7b2 | 1204 | return thread_pointer_rtx; |
7b6e506e RH |
1205 | } |
1206 | ||
21515593 | 1207 | static rtx |
5e6c8b64 | 1208 | ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1, |
b15b83fb | 1209 | rtx orig_op1, HOST_WIDE_INT addend) |
21515593 | 1210 | { |
dd3d2b35 DM |
1211 | rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp; |
1212 | rtx_insn *insns; | |
b15b83fb | 1213 | rtx orig_op0 = op0; |
5e6c8b64 RH |
1214 | HOST_WIDE_INT addend_lo, addend_hi; |
1215 | ||
21515593 RH |
1216 | switch (tls_kind) |
1217 | { | |
1218 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1219 | start_sequence (); | |
1220 | ||
1221 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1222 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1223 | |
1224 | tga_op2 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1225 | emit_insn (gen_load_dtprel (tga_op2, op1)); |
9c808aad | 1226 | |
21515593 | 1227 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, |
db69559b RS |
1228 | LCT_CONST, Pmode, |
1229 | tga_op1, Pmode, tga_op2, Pmode); | |
21515593 RH |
1230 | |
1231 | insns = get_insns (); | |
1232 | end_sequence (); | |
1233 | ||
0d433a6a RH |
1234 | if (GET_MODE (op0) != Pmode) |
1235 | op0 = tga_ret; | |
21515593 | 1236 | emit_libcall_block (insns, op0, tga_ret, op1); |
0d433a6a | 1237 | break; |
21515593 RH |
1238 | |
1239 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1240 | /* ??? This isn't the completely proper way to do local-dynamic | |
1241 | If the call to __tls_get_addr is used only by a single symbol, | |
1242 | then we should (somehow) move the dtprel to the second arg | |
1243 | to avoid the extra add. */ | |
1244 | start_sequence (); | |
1245 | ||
1246 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1247 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1248 | |
1249 | tga_op2 = const0_rtx; | |
1250 | ||
1251 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, | |
db69559b RS |
1252 | LCT_CONST, Pmode, |
1253 | tga_op1, Pmode, tga_op2, Pmode); | |
21515593 RH |
1254 | |
1255 | insns = get_insns (); | |
1256 | end_sequence (); | |
1257 | ||
1258 | tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1259 | UNSPEC_LD_BASE); | |
1260 | tmp = gen_reg_rtx (Pmode); | |
1261 | emit_libcall_block (insns, tmp, tga_ret, tga_eqv); | |
1262 | ||
0d433a6a RH |
1263 | if (!register_operand (op0, Pmode)) |
1264 | op0 = gen_reg_rtx (Pmode); | |
21515593 RH |
1265 | if (TARGET_TLS64) |
1266 | { | |
0d433a6a RH |
1267 | emit_insn (gen_load_dtprel (op0, op1)); |
1268 | emit_insn (gen_adddi3 (op0, tmp, op0)); | |
21515593 RH |
1269 | } |
1270 | else | |
5e6c8b64 | 1271 | emit_insn (gen_add_dtprel (op0, op1, tmp)); |
0d433a6a | 1272 | break; |
21515593 RH |
1273 | |
1274 | case TLS_MODEL_INITIAL_EXEC: | |
b15b83fb JJ |
1275 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; |
1276 | addend_hi = addend - addend_lo; | |
1277 | ||
0a81f074 | 1278 | op1 = plus_constant (Pmode, op1, addend_hi); |
5e6c8b64 RH |
1279 | addend = addend_lo; |
1280 | ||
21515593 | 1281 | tmp = gen_reg_rtx (Pmode); |
5e6c8b64 | 1282 | emit_insn (gen_load_tprel (tmp, op1)); |
21515593 | 1283 | |
0d433a6a RH |
1284 | if (!register_operand (op0, Pmode)) |
1285 | op0 = gen_reg_rtx (Pmode); | |
1286 | emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ())); | |
1287 | break; | |
21515593 RH |
1288 | |
1289 | case TLS_MODEL_LOCAL_EXEC: | |
0d433a6a RH |
1290 | if (!register_operand (op0, Pmode)) |
1291 | op0 = gen_reg_rtx (Pmode); | |
5e6c8b64 RH |
1292 | |
1293 | op1 = orig_op1; | |
1294 | addend = 0; | |
21515593 RH |
1295 | if (TARGET_TLS64) |
1296 | { | |
0d433a6a | 1297 | emit_insn (gen_load_tprel (op0, op1)); |
5e6c8b64 | 1298 | emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ())); |
21515593 RH |
1299 | } |
1300 | else | |
5e6c8b64 | 1301 | emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ())); |
0d433a6a | 1302 | break; |
21515593 RH |
1303 | |
1304 | default: | |
e820471b | 1305 | gcc_unreachable (); |
21515593 | 1306 | } |
0d433a6a | 1307 | |
5e6c8b64 RH |
1308 | if (addend) |
1309 | op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend), | |
1310 | orig_op0, 1, OPTAB_DIRECT); | |
0d433a6a RH |
1311 | if (orig_op0 == op0) |
1312 | return NULL_RTX; | |
1313 | if (GET_MODE (orig_op0) == Pmode) | |
1314 | return op0; | |
1315 | return gen_lowpart (GET_MODE (orig_op0), op0); | |
21515593 RH |
1316 | } |
1317 | ||
7b6e506e | 1318 | rtx |
9c808aad | 1319 | ia64_expand_move (rtx op0, rtx op1) |
7b6e506e | 1320 | { |
ef4bddc2 | 1321 | machine_mode mode = GET_MODE (op0); |
7b6e506e RH |
1322 | |
1323 | if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1)) | |
1324 | op1 = force_reg (mode, op1); | |
1325 | ||
21515593 | 1326 | if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode)) |
7b6e506e | 1327 | { |
5e6c8b64 | 1328 | HOST_WIDE_INT addend = 0; |
7b6e506e | 1329 | enum tls_model tls_kind; |
5e6c8b64 RH |
1330 | rtx sym = op1; |
1331 | ||
1332 | if (GET_CODE (op1) == CONST | |
1333 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
1334 | && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT) | |
1335 | { | |
1336 | addend = INTVAL (XEXP (XEXP (op1, 0), 1)); | |
1337 | sym = XEXP (XEXP (op1, 0), 0); | |
1338 | } | |
1339 | ||
1340 | tls_kind = tls_symbolic_operand_type (sym); | |
1341 | if (tls_kind) | |
b15b83fb | 1342 | return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend); |
5e6c8b64 RH |
1343 | |
1344 | if (any_offset_symbol_operand (sym, mode)) | |
1345 | addend = 0; | |
1346 | else if (aligned_offset_symbol_operand (sym, mode)) | |
1347 | { | |
1348 | HOST_WIDE_INT addend_lo, addend_hi; | |
1349 | ||
1350 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; | |
1351 | addend_hi = addend - addend_lo; | |
1352 | ||
1353 | if (addend_lo != 0) | |
1354 | { | |
0a81f074 | 1355 | op1 = plus_constant (mode, sym, addend_hi); |
5e6c8b64 RH |
1356 | addend = addend_lo; |
1357 | } | |
21e43850 L |
1358 | else |
1359 | addend = 0; | |
5e6c8b64 RH |
1360 | } |
1361 | else | |
1362 | op1 = sym; | |
1363 | ||
1364 | if (reload_completed) | |
1365 | { | |
1366 | /* We really should have taken care of this offset earlier. */ | |
1367 | gcc_assert (addend == 0); | |
1368 | if (ia64_expand_load_address (op0, op1)) | |
1369 | return NULL_RTX; | |
1370 | } | |
21515593 | 1371 | |
5e6c8b64 | 1372 | if (addend) |
7b6e506e | 1373 | { |
b3a13419 | 1374 | rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode); |
5e6c8b64 | 1375 | |
f7df4a84 | 1376 | emit_insn (gen_rtx_SET (subtarget, op1)); |
5e6c8b64 RH |
1377 | |
1378 | op1 = expand_simple_binop (mode, PLUS, subtarget, | |
1379 | GEN_INT (addend), op0, 1, OPTAB_DIRECT); | |
1380 | if (op0 == op1) | |
1381 | return NULL_RTX; | |
7b6e506e RH |
1382 | } |
1383 | } | |
1384 | ||
1385 | return op1; | |
1386 | } | |
1387 | ||
21515593 RH |
1388 | /* Split a move from OP1 to OP0 conditional on COND. */ |
1389 | ||
1390 | void | |
9c808aad | 1391 | ia64_emit_cond_move (rtx op0, rtx op1, rtx cond) |
21515593 | 1392 | { |
dd3d2b35 | 1393 | rtx_insn *insn, *first = get_last_insn (); |
21515593 RH |
1394 | |
1395 | emit_move_insn (op0, op1); | |
1396 | ||
1397 | for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn)) | |
1398 | if (INSN_P (insn)) | |
1399 | PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), | |
1400 | PATTERN (insn)); | |
1401 | } | |
1402 | ||
f57fc998 | 1403 | /* Split a post-reload TImode or TFmode reference into two DImode |
2ffe0e02 ZW |
1404 | components. This is made extra difficult by the fact that we do |
1405 | not get any scratch registers to work with, because reload cannot | |
1406 | be prevented from giving us a scratch that overlaps the register | |
1407 | pair involved. So instead, when addressing memory, we tweak the | |
1408 | pointer register up and back down with POST_INCs. Or up and not | |
1409 | back down when we can get away with it. | |
1410 | ||
1411 | REVERSED is true when the loads must be done in reversed order | |
1412 | (high word first) for correctness. DEAD is true when the pointer | |
1413 | dies with the second insn we generate and therefore the second | |
1414 | address must not carry a postmodify. | |
1415 | ||
1416 | May return an insn which is to be emitted after the moves. */ | |
3f622353 | 1417 | |
f57fc998 | 1418 | static rtx |
2ffe0e02 | 1419 | ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) |
3f622353 | 1420 | { |
2ffe0e02 ZW |
1421 | rtx fixup = 0; |
1422 | ||
3f622353 RH |
1423 | switch (GET_CODE (in)) |
1424 | { | |
1425 | case REG: | |
2ffe0e02 ZW |
1426 | out[reversed] = gen_rtx_REG (DImode, REGNO (in)); |
1427 | out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1); | |
1428 | break; | |
3f622353 RH |
1429 | |
1430 | case CONST_INT: | |
1431 | case CONST_DOUBLE: | |
2ffe0e02 | 1432 | /* Cannot occur reversed. */ |
e820471b | 1433 | gcc_assert (!reversed); |
2ffe0e02 | 1434 | |
f57fc998 ZW |
1435 | if (GET_MODE (in) != TFmode) |
1436 | split_double (in, &out[0], &out[1]); | |
1437 | else | |
1438 | /* split_double does not understand how to split a TFmode | |
1439 | quantity into a pair of DImode constants. */ | |
1440 | { | |
f57fc998 ZW |
1441 | unsigned HOST_WIDE_INT p[2]; |
1442 | long l[4]; /* TFmode is 128 bits */ | |
1443 | ||
34a72c33 | 1444 | real_to_target (l, CONST_DOUBLE_REAL_VALUE (in), TFmode); |
f57fc998 ZW |
1445 | |
1446 | if (FLOAT_WORDS_BIG_ENDIAN) | |
1447 | { | |
1448 | p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1]; | |
1449 | p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3]; | |
1450 | } | |
1451 | else | |
1452 | { | |
9eb578c8 L |
1453 | p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0]; |
1454 | p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2]; | |
f57fc998 ZW |
1455 | } |
1456 | out[0] = GEN_INT (p[0]); | |
1457 | out[1] = GEN_INT (p[1]); | |
1458 | } | |
2ffe0e02 ZW |
1459 | break; |
1460 | ||
1461 | case MEM: | |
1462 | { | |
1463 | rtx base = XEXP (in, 0); | |
1464 | rtx offset; | |
1465 | ||
1466 | switch (GET_CODE (base)) | |
1467 | { | |
1468 | case REG: | |
1469 | if (!reversed) | |
1470 | { | |
1471 | out[0] = adjust_automodify_address | |
1472 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1473 | out[1] = adjust_automodify_address | |
1474 | (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8); | |
1475 | } | |
1476 | else | |
1477 | { | |
1478 | /* Reversal requires a pre-increment, which can only | |
1479 | be done as a separate insn. */ | |
1480 | emit_insn (gen_adddi3 (base, base, GEN_INT (8))); | |
1481 | out[0] = adjust_automodify_address | |
1482 | (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8); | |
1483 | out[1] = adjust_address (in, DImode, 0); | |
1484 | } | |
1485 | break; | |
1486 | ||
1487 | case POST_INC: | |
e820471b NS |
1488 | gcc_assert (!reversed && !dead); |
1489 | ||
2ffe0e02 ZW |
1490 | /* Just do the increment in two steps. */ |
1491 | out[0] = adjust_automodify_address (in, DImode, 0, 0); | |
1492 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1493 | break; | |
1494 | ||
1495 | case POST_DEC: | |
e820471b NS |
1496 | gcc_assert (!reversed && !dead); |
1497 | ||
2ffe0e02 ZW |
1498 | /* Add 8, subtract 24. */ |
1499 | base = XEXP (base, 0); | |
1500 | out[0] = adjust_automodify_address | |
1501 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1502 | out[1] = adjust_automodify_address | |
1503 | (in, DImode, | |
0a81f074 RS |
1504 | gen_rtx_POST_MODIFY (Pmode, base, |
1505 | plus_constant (Pmode, base, -24)), | |
2ffe0e02 ZW |
1506 | 8); |
1507 | break; | |
1508 | ||
1509 | case POST_MODIFY: | |
e820471b NS |
1510 | gcc_assert (!reversed && !dead); |
1511 | ||
2ffe0e02 ZW |
1512 | /* Extract and adjust the modification. This case is |
1513 | trickier than the others, because we might have an | |
1514 | index register, or we might have a combined offset that | |
1515 | doesn't fit a signed 9-bit displacement field. We can | |
1516 | assume the incoming expression is already legitimate. */ | |
1517 | offset = XEXP (base, 1); | |
1518 | base = XEXP (base, 0); | |
1519 | ||
1520 | out[0] = adjust_automodify_address | |
1521 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1522 | ||
1523 | if (GET_CODE (XEXP (offset, 1)) == REG) | |
1524 | { | |
1525 | /* Can't adjust the postmodify to match. Emit the | |
1526 | original, then a separate addition insn. */ | |
1527 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1528 | fixup = gen_adddi3 (base, base, GEN_INT (-8)); | |
1529 | } | |
2ffe0e02 ZW |
1530 | else |
1531 | { | |
e820471b NS |
1532 | gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT); |
1533 | if (INTVAL (XEXP (offset, 1)) < -256 + 8) | |
1534 | { | |
1535 | /* Again the postmodify cannot be made to match, | |
1536 | but in this case it's more efficient to get rid | |
1537 | of the postmodify entirely and fix up with an | |
1538 | add insn. */ | |
1539 | out[1] = adjust_automodify_address (in, DImode, base, 8); | |
1540 | fixup = gen_adddi3 | |
1541 | (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8)); | |
1542 | } | |
1543 | else | |
1544 | { | |
1545 | /* Combined offset still fits in the displacement field. | |
1546 | (We cannot overflow it at the high end.) */ | |
1547 | out[1] = adjust_automodify_address | |
1548 | (in, DImode, gen_rtx_POST_MODIFY | |
1549 | (Pmode, base, gen_rtx_PLUS | |
1550 | (Pmode, base, | |
1551 | GEN_INT (INTVAL (XEXP (offset, 1)) - 8))), | |
1552 | 8); | |
1553 | } | |
2ffe0e02 ZW |
1554 | } |
1555 | break; | |
1556 | ||
1557 | default: | |
e820471b | 1558 | gcc_unreachable (); |
2ffe0e02 ZW |
1559 | } |
1560 | break; | |
1561 | } | |
3f622353 RH |
1562 | |
1563 | default: | |
e820471b | 1564 | gcc_unreachable (); |
3f622353 | 1565 | } |
2ffe0e02 ZW |
1566 | |
1567 | return fixup; | |
3f622353 RH |
1568 | } |
1569 | ||
f57fc998 ZW |
1570 | /* Split a TImode or TFmode move instruction after reload. |
1571 | This is used by *movtf_internal and *movti_internal. */ | |
1572 | void | |
1573 | ia64_split_tmode_move (rtx operands[]) | |
1574 | { | |
2ffe0e02 ZW |
1575 | rtx in[2], out[2], insn; |
1576 | rtx fixup[2]; | |
1577 | bool dead = false; | |
1578 | bool reversed = false; | |
1579 | ||
1580 | /* It is possible for reload to decide to overwrite a pointer with | |
1581 | the value it points to. In that case we have to do the loads in | |
1582 | the appropriate order so that the pointer is not destroyed too | |
1583 | early. Also we must not generate a postmodify for that second | |
6d3f673c KY |
1584 | load, or rws_access_regno will die. And we must not generate a |
1585 | postmodify for the second load if the destination register | |
1586 | overlaps with the base register. */ | |
2ffe0e02 ZW |
1587 | if (GET_CODE (operands[1]) == MEM |
1588 | && reg_overlap_mentioned_p (operands[0], operands[1])) | |
f57fc998 | 1589 | { |
2ffe0e02 ZW |
1590 | rtx base = XEXP (operands[1], 0); |
1591 | while (GET_CODE (base) != REG) | |
1592 | base = XEXP (base, 0); | |
f57fc998 | 1593 | |
2ffe0e02 | 1594 | if (REGNO (base) == REGNO (operands[0])) |
6d3f673c | 1595 | reversed = true; |
2430d1e2 | 1596 | |
6d3f673c KY |
1597 | if (refers_to_regno_p (REGNO (operands[0]), |
1598 | REGNO (operands[0])+2, | |
1599 | base, 0)) | |
2430d1e2 | 1600 | dead = true; |
2ffe0e02 ZW |
1601 | } |
1602 | /* Another reason to do the moves in reversed order is if the first | |
1603 | element of the target register pair is also the second element of | |
1604 | the source register pair. */ | |
1605 | if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG | |
1606 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
1607 | reversed = true; | |
1608 | ||
1609 | fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead); | |
1610 | fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead); | |
1611 | ||
1612 | #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \ | |
1613 | if (GET_CODE (EXP) == MEM \ | |
1614 | && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \ | |
1615 | || GET_CODE (XEXP (EXP, 0)) == POST_INC \ | |
1616 | || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \ | |
bbbbb16a | 1617 | add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0)) |
2ffe0e02 | 1618 | |
f7df4a84 | 1619 | insn = emit_insn (gen_rtx_SET (out[0], in[0])); |
2ffe0e02 ZW |
1620 | MAYBE_ADD_REG_INC_NOTE (insn, in[0]); |
1621 | MAYBE_ADD_REG_INC_NOTE (insn, out[0]); | |
1622 | ||
f7df4a84 | 1623 | insn = emit_insn (gen_rtx_SET (out[1], in[1])); |
2ffe0e02 ZW |
1624 | MAYBE_ADD_REG_INC_NOTE (insn, in[1]); |
1625 | MAYBE_ADD_REG_INC_NOTE (insn, out[1]); | |
1626 | ||
1627 | if (fixup[0]) | |
1628 | emit_insn (fixup[0]); | |
1629 | if (fixup[1]) | |
1630 | emit_insn (fixup[1]); | |
1631 | ||
1632 | #undef MAYBE_ADD_REG_INC_NOTE | |
f57fc998 ZW |
1633 | } |
1634 | ||
02befdf4 | 1635 | /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go |
3f622353 | 1636 | through memory plus an extra GR scratch register. Except that you can |
f15643d4 RS |
1637 | either get the first from TARGET_SECONDARY_MEMORY_NEEDED or the second |
1638 | from SECONDARY_RELOAD_CLASS, but not both. | |
3f622353 RH |
1639 | |
1640 | We got into problems in the first place by allowing a construct like | |
02befdf4 | 1641 | (subreg:XF (reg:TI)), which we got from a union containing a long double. |
f5143c46 | 1642 | This solution attempts to prevent this situation from occurring. When |
3f622353 RH |
1643 | we see something like the above, we spill the inner register to memory. */ |
1644 | ||
4de67c26 | 1645 | static rtx |
ef4bddc2 | 1646 | spill_xfmode_rfmode_operand (rtx in, int force, machine_mode mode) |
3f622353 RH |
1647 | { |
1648 | if (GET_CODE (in) == SUBREG | |
1649 | && GET_MODE (SUBREG_REG (in)) == TImode | |
1650 | && GET_CODE (SUBREG_REG (in)) == REG) | |
1651 | { | |
9474e8ab | 1652 | rtx memt = assign_stack_temp (TImode, 16); |
68d22aa5 | 1653 | emit_move_insn (memt, SUBREG_REG (in)); |
4de67c26 | 1654 | return adjust_address (memt, mode, 0); |
3f622353 RH |
1655 | } |
1656 | else if (force && GET_CODE (in) == REG) | |
1657 | { | |
9474e8ab | 1658 | rtx memx = assign_stack_temp (mode, 16); |
68d22aa5 RH |
1659 | emit_move_insn (memx, in); |
1660 | return memx; | |
3f622353 | 1661 | } |
3f622353 RH |
1662 | else |
1663 | return in; | |
1664 | } | |
f2f90c63 | 1665 | |
4de67c26 JM |
1666 | /* Expand the movxf or movrf pattern (MODE says which) with the given |
1667 | OPERANDS, returning true if the pattern should then invoke | |
1668 | DONE. */ | |
1669 | ||
1670 | bool | |
ef4bddc2 | 1671 | ia64_expand_movxf_movrf (machine_mode mode, rtx operands[]) |
4de67c26 JM |
1672 | { |
1673 | rtx op0 = operands[0]; | |
1674 | ||
1675 | if (GET_CODE (op0) == SUBREG) | |
1676 | op0 = SUBREG_REG (op0); | |
1677 | ||
1678 | /* We must support XFmode loads into general registers for stdarg/vararg, | |
1679 | unprototyped calls, and a rare case where a long double is passed as | |
1680 | an argument after a float HFA fills the FP registers. We split them into | |
1681 | DImode loads for convenience. We also need to support XFmode stores | |
1682 | for the last case. This case does not happen for stdarg/vararg routines, | |
1683 | because we do a block store to memory of unnamed arguments. */ | |
1684 | ||
1685 | if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0))) | |
1686 | { | |
1687 | rtx out[2]; | |
1688 | ||
1689 | /* We're hoping to transform everything that deals with XFmode | |
1690 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1691 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1692 | |
1693 | /* Struct to register can just use TImode instead. */ | |
1694 | if ((GET_CODE (operands[1]) == SUBREG | |
1695 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
1696 | || (GET_CODE (operands[1]) == REG | |
1697 | && GR_REGNO_P (REGNO (operands[1])))) | |
1698 | { | |
1699 | rtx op1 = operands[1]; | |
1700 | ||
1701 | if (GET_CODE (op1) == SUBREG) | |
1702 | op1 = SUBREG_REG (op1); | |
1703 | else | |
1704 | op1 = gen_rtx_REG (TImode, REGNO (op1)); | |
1705 | ||
1706 | emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); | |
1707 | return true; | |
1708 | } | |
1709 | ||
1710 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1711 | { | |
ae4d3291 | 1712 | /* Don't word-swap when reading in the constant. */ |
4de67c26 | 1713 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)), |
ae4d3291 JW |
1714 | operand_subword (operands[1], WORDS_BIG_ENDIAN, |
1715 | 0, mode)); | |
4de67c26 | 1716 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1), |
ae4d3291 JW |
1717 | operand_subword (operands[1], !WORDS_BIG_ENDIAN, |
1718 | 0, mode)); | |
4de67c26 JM |
1719 | return true; |
1720 | } | |
1721 | ||
1722 | /* If the quantity is in a register not known to be GR, spill it. */ | |
1723 | if (register_operand (operands[1], mode)) | |
1724 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode); | |
1725 | ||
1726 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
1727 | ||
ae4d3291 JW |
1728 | /* Don't word-swap when reading in the value. */ |
1729 | out[0] = gen_rtx_REG (DImode, REGNO (op0)); | |
1730 | out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1); | |
4de67c26 JM |
1731 | |
1732 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); | |
1733 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
1734 | return true; | |
1735 | } | |
1736 | ||
1737 | if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1]))) | |
1738 | { | |
1739 | /* We're hoping to transform everything that deals with XFmode | |
1740 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1741 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1742 | |
1743 | /* Op0 can't be a GR_REG here, as that case is handled above. | |
1744 | If op0 is a register, then we spill op1, so that we now have a | |
1745 | MEM operand. This requires creating an XFmode subreg of a TImode reg | |
1746 | to force the spill. */ | |
1747 | if (register_operand (operands[0], mode)) | |
1748 | { | |
1749 | rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1])); | |
1750 | op1 = gen_rtx_SUBREG (mode, op1, 0); | |
1751 | operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode); | |
1752 | } | |
1753 | ||
1754 | else | |
1755 | { | |
1756 | rtx in[2]; | |
1757 | ||
ae4d3291 JW |
1758 | gcc_assert (GET_CODE (operands[0]) == MEM); |
1759 | ||
1760 | /* Don't word-swap when writing out the value. */ | |
1761 | in[0] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1762 | in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1); | |
4de67c26 JM |
1763 | |
1764 | emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]); | |
1765 | emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]); | |
1766 | return true; | |
1767 | } | |
1768 | } | |
1769 | ||
1770 | if (!reload_in_progress && !reload_completed) | |
1771 | { | |
1772 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode); | |
1773 | ||
1774 | if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG) | |
1775 | { | |
1776 | rtx memt, memx, in = operands[1]; | |
1777 | if (CONSTANT_P (in)) | |
1778 | in = validize_mem (force_const_mem (mode, in)); | |
1779 | if (GET_CODE (in) == MEM) | |
1780 | memt = adjust_address (in, TImode, 0); | |
1781 | else | |
1782 | { | |
9474e8ab | 1783 | memt = assign_stack_temp (TImode, 16); |
4de67c26 JM |
1784 | memx = adjust_address (memt, mode, 0); |
1785 | emit_move_insn (memx, in); | |
1786 | } | |
1787 | emit_move_insn (op0, memt); | |
1788 | return true; | |
1789 | } | |
1790 | ||
1791 | if (!ia64_move_ok (operands[0], operands[1])) | |
1792 | operands[1] = force_reg (mode, operands[1]); | |
1793 | } | |
1794 | ||
1795 | return false; | |
1796 | } | |
1797 | ||
f90b7a5a PB |
1798 | /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1 |
1799 | with the expression that holds the compare result (in VOIDmode). */ | |
f2f90c63 | 1800 | |
24ea7948 ZW |
1801 | static GTY(()) rtx cmptf_libfunc; |
1802 | ||
f90b7a5a PB |
1803 | void |
1804 | ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1) | |
f2f90c63 | 1805 | { |
f90b7a5a | 1806 | enum rtx_code code = GET_CODE (*expr); |
f2f90c63 RH |
1807 | rtx cmp; |
1808 | ||
1809 | /* If we have a BImode input, then we already have a compare result, and | |
1810 | do not need to emit another comparison. */ | |
f90b7a5a | 1811 | if (GET_MODE (*op0) == BImode) |
f2f90c63 | 1812 | { |
f90b7a5a PB |
1813 | gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx); |
1814 | cmp = *op0; | |
f2f90c63 | 1815 | } |
24ea7948 ZW |
1816 | /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a |
1817 | magic number as its third argument, that indicates what to do. | |
1818 | The return value is an integer to be compared against zero. */ | |
f90b7a5a | 1819 | else if (TARGET_HPUX && GET_MODE (*op0) == TFmode) |
24ea7948 ZW |
1820 | { |
1821 | enum qfcmp_magic { | |
8fc53a5f | 1822 | QCMP_INV = 1, /* Raise FP_INVALID on NaNs as a side effect. */ |
24ea7948 ZW |
1823 | QCMP_UNORD = 2, |
1824 | QCMP_EQ = 4, | |
1825 | QCMP_LT = 8, | |
1826 | QCMP_GT = 16 | |
32e8bb8e ILT |
1827 | }; |
1828 | int magic; | |
24ea7948 | 1829 | enum rtx_code ncode; |
9b2ea071 | 1830 | rtx ret; |
e820471b | 1831 | |
f90b7a5a | 1832 | gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode); |
24ea7948 ZW |
1833 | switch (code) |
1834 | { | |
1835 | /* 1 = equal, 0 = not equal. Equality operators do | |
8fc53a5f | 1836 | not raise FP_INVALID when given a NaN operand. */ |
24ea7948 ZW |
1837 | case EQ: magic = QCMP_EQ; ncode = NE; break; |
1838 | case NE: magic = QCMP_EQ; ncode = EQ; break; | |
1839 | /* isunordered() from C99. */ | |
1840 | case UNORDERED: magic = QCMP_UNORD; ncode = NE; break; | |
b1346fa3 | 1841 | case ORDERED: magic = QCMP_UNORD; ncode = EQ; break; |
24ea7948 | 1842 | /* Relational operators raise FP_INVALID when given |
8fc53a5f | 1843 | a NaN operand. */ |
24ea7948 ZW |
1844 | case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break; |
1845 | case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
1846 | case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break; | |
1847 | case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
8fc53a5f EB |
1848 | /* Unordered relational operators do not raise FP_INVALID |
1849 | when given a NaN operand. */ | |
1850 | case UNLT: magic = QCMP_LT |QCMP_UNORD; ncode = NE; break; | |
1851 | case UNLE: magic = QCMP_LT|QCMP_EQ|QCMP_UNORD; ncode = NE; break; | |
1852 | case UNGT: magic = QCMP_GT |QCMP_UNORD; ncode = NE; break; | |
1853 | case UNGE: magic = QCMP_GT|QCMP_EQ|QCMP_UNORD; ncode = NE; break; | |
1854 | /* Not supported. */ | |
1855 | case UNEQ: | |
1856 | case LTGT: | |
e820471b | 1857 | default: gcc_unreachable (); |
24ea7948 ZW |
1858 | } |
1859 | ||
1860 | start_sequence (); | |
1861 | ||
db69559b | 1862 | ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, |
f90b7a5a | 1863 | *op0, TFmode, *op1, TFmode, |
24ea7948 ZW |
1864 | GEN_INT (magic), DImode); |
1865 | cmp = gen_reg_rtx (BImode); | |
f7df4a84 RS |
1866 | emit_insn (gen_rtx_SET (cmp, gen_rtx_fmt_ee (ncode, BImode, |
1867 | ret, const0_rtx))); | |
24ea7948 | 1868 | |
9b2ea071 | 1869 | rtx_insn *insns = get_insns (); |
24ea7948 ZW |
1870 | end_sequence (); |
1871 | ||
1872 | emit_libcall_block (insns, cmp, cmp, | |
f90b7a5a | 1873 | gen_rtx_fmt_ee (code, BImode, *op0, *op1)); |
24ea7948 ZW |
1874 | code = NE; |
1875 | } | |
f2f90c63 RH |
1876 | else |
1877 | { | |
1878 | cmp = gen_reg_rtx (BImode); | |
f7df4a84 | 1879 | emit_insn (gen_rtx_SET (cmp, gen_rtx_fmt_ee (code, BImode, *op0, *op1))); |
f2f90c63 RH |
1880 | code = NE; |
1881 | } | |
1882 | ||
f90b7a5a PB |
1883 | *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx); |
1884 | *op0 = cmp; | |
1885 | *op1 = const0_rtx; | |
f2f90c63 | 1886 | } |
2ed4af6f | 1887 | |
e934ca47 RH |
1888 | /* Generate an integral vector comparison. Return true if the condition has |
1889 | been reversed, and so the sense of the comparison should be inverted. */ | |
f61134e8 RH |
1890 | |
1891 | static bool | |
ef4bddc2 | 1892 | ia64_expand_vecint_compare (enum rtx_code code, machine_mode mode, |
f61134e8 RH |
1893 | rtx dest, rtx op0, rtx op1) |
1894 | { | |
1895 | bool negate = false; | |
1896 | rtx x; | |
1897 | ||
e934ca47 | 1898 | /* Canonicalize the comparison to EQ, GT, GTU. */ |
f61134e8 RH |
1899 | switch (code) |
1900 | { | |
1901 | case EQ: | |
1902 | case GT: | |
e934ca47 | 1903 | case GTU: |
f61134e8 RH |
1904 | break; |
1905 | ||
1906 | case NE: | |
f61134e8 | 1907 | case LE: |
e934ca47 RH |
1908 | case LEU: |
1909 | code = reverse_condition (code); | |
f61134e8 RH |
1910 | negate = true; |
1911 | break; | |
1912 | ||
1913 | case GE: | |
e934ca47 RH |
1914 | case GEU: |
1915 | code = reverse_condition (code); | |
f61134e8 RH |
1916 | negate = true; |
1917 | /* FALLTHRU */ | |
1918 | ||
1919 | case LT: | |
f61134e8 | 1920 | case LTU: |
e934ca47 RH |
1921 | code = swap_condition (code); |
1922 | x = op0, op0 = op1, op1 = x; | |
1923 | break; | |
f61134e8 | 1924 | |
e934ca47 RH |
1925 | default: |
1926 | gcc_unreachable (); | |
1927 | } | |
f61134e8 | 1928 | |
e934ca47 | 1929 | /* Unsigned parallel compare is not supported by the hardware. Play some |
6283ba26 | 1930 | tricks to turn this into a signed comparison against 0. */ |
e934ca47 RH |
1931 | if (code == GTU) |
1932 | { | |
1933 | switch (mode) | |
1934 | { | |
4e10a5a7 | 1935 | case E_V2SImode: |
f61134e8 | 1936 | { |
e934ca47 RH |
1937 | rtx t1, t2, mask; |
1938 | ||
9540f5ef SE |
1939 | /* Subtract (-(INT MAX) - 1) from both operands to make |
1940 | them signed. */ | |
6a8b00eb | 1941 | mask = gen_int_mode (0x80000000, SImode); |
59d06c05 | 1942 | mask = gen_const_vec_duplicate (V2SImode, mask); |
9540f5ef SE |
1943 | mask = force_reg (mode, mask); |
1944 | t1 = gen_reg_rtx (mode); | |
1945 | emit_insn (gen_subv2si3 (t1, op0, mask)); | |
1946 | t2 = gen_reg_rtx (mode); | |
1947 | emit_insn (gen_subv2si3 (t2, op1, mask)); | |
1948 | op0 = t1; | |
1949 | op1 = t2; | |
6283ba26 | 1950 | code = GT; |
f61134e8 | 1951 | } |
e934ca47 RH |
1952 | break; |
1953 | ||
4e10a5a7 RS |
1954 | case E_V8QImode: |
1955 | case E_V4HImode: | |
e934ca47 RH |
1956 | /* Perform a parallel unsigned saturating subtraction. */ |
1957 | x = gen_reg_rtx (mode); | |
f7df4a84 | 1958 | emit_insn (gen_rtx_SET (x, gen_rtx_US_MINUS (mode, op0, op1))); |
6283ba26 RH |
1959 | |
1960 | code = EQ; | |
1961 | op0 = x; | |
1962 | op1 = CONST0_RTX (mode); | |
1963 | negate = !negate; | |
e934ca47 RH |
1964 | break; |
1965 | ||
1966 | default: | |
1967 | gcc_unreachable (); | |
1968 | } | |
f61134e8 RH |
1969 | } |
1970 | ||
1971 | x = gen_rtx_fmt_ee (code, mode, op0, op1); | |
f7df4a84 | 1972 | emit_insn (gen_rtx_SET (dest, x)); |
f61134e8 RH |
1973 | |
1974 | return negate; | |
1975 | } | |
1976 | ||
f61134e8 RH |
1977 | /* Emit an integral vector conditional move. */ |
1978 | ||
1979 | void | |
1980 | ia64_expand_vecint_cmov (rtx operands[]) | |
1981 | { | |
ef4bddc2 | 1982 | machine_mode mode = GET_MODE (operands[0]); |
f61134e8 RH |
1983 | enum rtx_code code = GET_CODE (operands[3]); |
1984 | bool negate; | |
1985 | rtx cmp, x, ot, of; | |
1986 | ||
f61134e8 RH |
1987 | cmp = gen_reg_rtx (mode); |
1988 | negate = ia64_expand_vecint_compare (code, mode, cmp, | |
1989 | operands[4], operands[5]); | |
1990 | ||
1991 | ot = operands[1+negate]; | |
1992 | of = operands[2-negate]; | |
1993 | ||
1994 | if (ot == CONST0_RTX (mode)) | |
1995 | { | |
1996 | if (of == CONST0_RTX (mode)) | |
1997 | { | |
1998 | emit_move_insn (operands[0], ot); | |
1999 | return; | |
2000 | } | |
2001 | ||
2002 | x = gen_rtx_NOT (mode, cmp); | |
2003 | x = gen_rtx_AND (mode, x, of); | |
f7df4a84 | 2004 | emit_insn (gen_rtx_SET (operands[0], x)); |
f61134e8 RH |
2005 | } |
2006 | else if (of == CONST0_RTX (mode)) | |
2007 | { | |
2008 | x = gen_rtx_AND (mode, cmp, ot); | |
f7df4a84 | 2009 | emit_insn (gen_rtx_SET (operands[0], x)); |
f61134e8 RH |
2010 | } |
2011 | else | |
2012 | { | |
2013 | rtx t, f; | |
2014 | ||
2015 | t = gen_reg_rtx (mode); | |
2016 | x = gen_rtx_AND (mode, cmp, operands[1+negate]); | |
f7df4a84 | 2017 | emit_insn (gen_rtx_SET (t, x)); |
f61134e8 RH |
2018 | |
2019 | f = gen_reg_rtx (mode); | |
2020 | x = gen_rtx_NOT (mode, cmp); | |
2021 | x = gen_rtx_AND (mode, x, operands[2-negate]); | |
f7df4a84 | 2022 | emit_insn (gen_rtx_SET (f, x)); |
f61134e8 RH |
2023 | |
2024 | x = gen_rtx_IOR (mode, t, f); | |
f7df4a84 | 2025 | emit_insn (gen_rtx_SET (operands[0], x)); |
f61134e8 RH |
2026 | } |
2027 | } | |
2028 | ||
2029 | /* Emit an integral vector min or max operation. Return true if all done. */ | |
2030 | ||
2031 | bool | |
ef4bddc2 | 2032 | ia64_expand_vecint_minmax (enum rtx_code code, machine_mode mode, |
f61134e8 RH |
2033 | rtx operands[]) |
2034 | { | |
cabddb23 | 2035 | rtx xops[6]; |
f61134e8 RH |
2036 | |
2037 | /* These four combinations are supported directly. */ | |
2038 | if (mode == V8QImode && (code == UMIN || code == UMAX)) | |
2039 | return false; | |
2040 | if (mode == V4HImode && (code == SMIN || code == SMAX)) | |
2041 | return false; | |
2042 | ||
93b4080b RH |
2043 | /* This combination can be implemented with only saturating subtraction. */ |
2044 | if (mode == V4HImode && code == UMAX) | |
2045 | { | |
2046 | rtx x, tmp = gen_reg_rtx (mode); | |
2047 | ||
2048 | x = gen_rtx_US_MINUS (mode, operands[1], operands[2]); | |
f7df4a84 | 2049 | emit_insn (gen_rtx_SET (tmp, x)); |
93b4080b RH |
2050 | |
2051 | emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2])); | |
2052 | return true; | |
2053 | } | |
2054 | ||
f61134e8 RH |
2055 | /* Everything else implemented via vector comparisons. */ |
2056 | xops[0] = operands[0]; | |
2057 | xops[4] = xops[1] = operands[1]; | |
2058 | xops[5] = xops[2] = operands[2]; | |
2059 | ||
2060 | switch (code) | |
2061 | { | |
2062 | case UMIN: | |
2063 | code = LTU; | |
2064 | break; | |
2065 | case UMAX: | |
2066 | code = GTU; | |
2067 | break; | |
2068 | case SMIN: | |
2069 | code = LT; | |
2070 | break; | |
2071 | case SMAX: | |
2072 | code = GT; | |
2073 | break; | |
2074 | default: | |
e820471b | 2075 | gcc_unreachable (); |
f61134e8 RH |
2076 | } |
2077 | xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]); | |
2078 | ||
2079 | ia64_expand_vecint_cmov (xops); | |
2080 | return true; | |
2081 | } | |
2082 | ||
55eaaa5b RH |
2083 | /* The vectors LO and HI each contain N halves of a double-wide vector. |
2084 | Reassemble either the first N/2 or the second N/2 elements. */ | |
604e3ff3 RH |
2085 | |
2086 | void | |
55eaaa5b | 2087 | ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp) |
604e3ff3 | 2088 | { |
ef4bddc2 | 2089 | machine_mode vmode = GET_MODE (lo); |
e6431744 RH |
2090 | unsigned int i, high, nelt = GET_MODE_NUNITS (vmode); |
2091 | struct expand_vec_perm_d d; | |
2092 | bool ok; | |
604e3ff3 | 2093 | |
e6431744 RH |
2094 | d.target = gen_lowpart (vmode, out); |
2095 | d.op0 = (TARGET_BIG_ENDIAN ? hi : lo); | |
2096 | d.op1 = (TARGET_BIG_ENDIAN ? lo : hi); | |
2097 | d.vmode = vmode; | |
2098 | d.nelt = nelt; | |
2099 | d.one_operand_p = false; | |
2100 | d.testing_p = false; | |
2101 | ||
2102 | high = (highp ? nelt / 2 : 0); | |
2103 | for (i = 0; i < nelt / 2; ++i) | |
604e3ff3 | 2104 | { |
e6431744 RH |
2105 | d.perm[i * 2] = i + high; |
2106 | d.perm[i * 2 + 1] = i + high + nelt; | |
604e3ff3 RH |
2107 | } |
2108 | ||
e6431744 RH |
2109 | ok = ia64_expand_vec_perm_const_1 (&d); |
2110 | gcc_assert (ok); | |
604e3ff3 RH |
2111 | } |
2112 | ||
55eaaa5b | 2113 | /* Return a vector of the sign-extension of VEC. */ |
e898620c | 2114 | |
55eaaa5b RH |
2115 | static rtx |
2116 | ia64_unpack_sign (rtx vec, bool unsignedp) | |
e898620c | 2117 | { |
ef4bddc2 | 2118 | machine_mode mode = GET_MODE (vec); |
55eaaa5b | 2119 | rtx zero = CONST0_RTX (mode); |
e898620c | 2120 | |
e898620c | 2121 | if (unsignedp) |
55eaaa5b | 2122 | return zero; |
e898620c RH |
2123 | else |
2124 | { | |
55eaaa5b | 2125 | rtx sign = gen_reg_rtx (mode); |
e898620c RH |
2126 | bool neg; |
2127 | ||
55eaaa5b | 2128 | neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero); |
e898620c | 2129 | gcc_assert (!neg); |
55eaaa5b RH |
2130 | |
2131 | return sign; | |
e898620c | 2132 | } |
55eaaa5b | 2133 | } |
e898620c | 2134 | |
55eaaa5b | 2135 | /* Emit an integral vector unpack operation. */ |
e898620c | 2136 | |
55eaaa5b RH |
2137 | void |
2138 | ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp) | |
2139 | { | |
2140 | rtx sign = ia64_unpack_sign (operands[1], unsignedp); | |
2141 | ia64_unpack_assemble (operands[0], operands[1], sign, highp); | |
e898620c RH |
2142 | } |
2143 | ||
55eaaa5b RH |
2144 | /* Emit an integral vector widening sum operations. */ |
2145 | ||
604e3ff3 | 2146 | void |
55eaaa5b | 2147 | ia64_expand_widen_sum (rtx operands[3], bool unsignedp) |
604e3ff3 | 2148 | { |
ef4bddc2 | 2149 | machine_mode wmode; |
55eaaa5b | 2150 | rtx l, h, t, sign; |
604e3ff3 | 2151 | |
55eaaa5b RH |
2152 | sign = ia64_unpack_sign (operands[1], unsignedp); |
2153 | ||
2154 | wmode = GET_MODE (operands[0]); | |
2155 | l = gen_reg_rtx (wmode); | |
2156 | h = gen_reg_rtx (wmode); | |
604e3ff3 | 2157 | |
55eaaa5b RH |
2158 | ia64_unpack_assemble (l, operands[1], sign, false); |
2159 | ia64_unpack_assemble (h, operands[1], sign, true); | |
604e3ff3 | 2160 | |
55eaaa5b RH |
2161 | t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT); |
2162 | t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT); | |
2163 | if (t != operands[0]) | |
2164 | emit_move_insn (operands[0], t); | |
604e3ff3 RH |
2165 | } |
2166 | ||
2ed4af6f RH |
2167 | /* Emit the appropriate sequence for a call. */ |
2168 | ||
2169 | void | |
9c808aad AJ |
2170 | ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED, |
2171 | int sibcall_p) | |
2ed4af6f | 2172 | { |
599aedd9 | 2173 | rtx insn, b0; |
2ed4af6f RH |
2174 | |
2175 | addr = XEXP (addr, 0); | |
c8083186 | 2176 | addr = convert_memory_address (DImode, addr); |
2ed4af6f | 2177 | b0 = gen_rtx_REG (DImode, R_BR (0)); |
2ed4af6f | 2178 | |
599aedd9 | 2179 | /* ??? Should do this for functions known to bind local too. */ |
2ed4af6f RH |
2180 | if (TARGET_NO_PIC || TARGET_AUTO_PIC) |
2181 | { | |
2182 | if (sibcall_p) | |
599aedd9 | 2183 | insn = gen_sibcall_nogp (addr); |
2ed4af6f | 2184 | else if (! retval) |
599aedd9 | 2185 | insn = gen_call_nogp (addr, b0); |
2ed4af6f | 2186 | else |
599aedd9 RH |
2187 | insn = gen_call_value_nogp (retval, addr, b0); |
2188 | insn = emit_call_insn (insn); | |
2ed4af6f | 2189 | } |
2ed4af6f | 2190 | else |
599aedd9 RH |
2191 | { |
2192 | if (sibcall_p) | |
2193 | insn = gen_sibcall_gp (addr); | |
2194 | else if (! retval) | |
2195 | insn = gen_call_gp (addr, b0); | |
2196 | else | |
2197 | insn = gen_call_value_gp (retval, addr, b0); | |
2198 | insn = emit_call_insn (insn); | |
2ed4af6f | 2199 | |
599aedd9 RH |
2200 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2201 | } | |
6dad5a56 | 2202 | |
599aedd9 | 2203 | if (sibcall_p) |
4e14f1f9 | 2204 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0); |
f2972bf8 DR |
2205 | |
2206 | if (TARGET_ABI_OPEN_VMS) | |
2207 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2208 | gen_rtx_REG (DImode, GR_REG (25))); | |
599aedd9 RH |
2209 | } |
2210 | ||
6fb5fa3c DB |
2211 | static void |
2212 | reg_emitted (enum ia64_frame_regs r) | |
2213 | { | |
2214 | if (emitted_frame_related_regs[r] == 0) | |
2215 | emitted_frame_related_regs[r] = current_frame_info.r[r]; | |
2216 | else | |
2217 | gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]); | |
2218 | } | |
2219 | ||
2220 | static int | |
2221 | get_reg (enum ia64_frame_regs r) | |
2222 | { | |
2223 | reg_emitted (r); | |
2224 | return current_frame_info.r[r]; | |
2225 | } | |
2226 | ||
2227 | static bool | |
2228 | is_emitted (int regno) | |
2229 | { | |
09639a83 | 2230 | unsigned int r; |
6fb5fa3c DB |
2231 | |
2232 | for (r = reg_fp; r < number_of_ia64_frame_regs; r++) | |
2233 | if (emitted_frame_related_regs[r] == regno) | |
2234 | return true; | |
2235 | return false; | |
2236 | } | |
2237 | ||
599aedd9 | 2238 | void |
9c808aad | 2239 | ia64_reload_gp (void) |
599aedd9 RH |
2240 | { |
2241 | rtx tmp; | |
2242 | ||
6fb5fa3c DB |
2243 | if (current_frame_info.r[reg_save_gp]) |
2244 | { | |
2245 | tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp)); | |
2246 | } | |
2ed4af6f | 2247 | else |
599aedd9 RH |
2248 | { |
2249 | HOST_WIDE_INT offset; | |
13f70342 | 2250 | rtx offset_r; |
599aedd9 RH |
2251 | |
2252 | offset = (current_frame_info.spill_cfa_off | |
2253 | + current_frame_info.spill_size); | |
2254 | if (frame_pointer_needed) | |
2255 | { | |
2256 | tmp = hard_frame_pointer_rtx; | |
2257 | offset = -offset; | |
2258 | } | |
2259 | else | |
2260 | { | |
2261 | tmp = stack_pointer_rtx; | |
2262 | offset = current_frame_info.total_size - offset; | |
2263 | } | |
2264 | ||
13f70342 RH |
2265 | offset_r = GEN_INT (offset); |
2266 | if (satisfies_constraint_I (offset_r)) | |
2267 | emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r)); | |
599aedd9 RH |
2268 | else |
2269 | { | |
13f70342 | 2270 | emit_move_insn (pic_offset_table_rtx, offset_r); |
599aedd9 RH |
2271 | emit_insn (gen_adddi3 (pic_offset_table_rtx, |
2272 | pic_offset_table_rtx, tmp)); | |
2273 | } | |
2274 | ||
2275 | tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx); | |
2276 | } | |
2277 | ||
2278 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2279 | } | |
2280 | ||
2281 | void | |
9c808aad AJ |
2282 | ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r, |
2283 | rtx scratch_b, int noreturn_p, int sibcall_p) | |
599aedd9 RH |
2284 | { |
2285 | rtx insn; | |
2286 | bool is_desc = false; | |
2287 | ||
2288 | /* If we find we're calling through a register, then we're actually | |
2289 | calling through a descriptor, so load up the values. */ | |
4e14f1f9 | 2290 | if (REG_P (addr) && GR_REGNO_P (REGNO (addr))) |
599aedd9 RH |
2291 | { |
2292 | rtx tmp; | |
2293 | bool addr_dead_p; | |
2294 | ||
2295 | /* ??? We are currently constrained to *not* use peep2, because | |
2a43945f | 2296 | we can legitimately change the global lifetime of the GP |
9c808aad | 2297 | (in the form of killing where previously live). This is |
599aedd9 RH |
2298 | because a call through a descriptor doesn't use the previous |
2299 | value of the GP, while a direct call does, and we do not | |
2300 | commit to either form until the split here. | |
2301 | ||
2302 | That said, this means that we lack precise life info for | |
2303 | whether ADDR is dead after this call. This is not terribly | |
2304 | important, since we can fix things up essentially for free | |
2305 | with the POST_DEC below, but it's nice to not use it when we | |
2306 | can immediately tell it's not necessary. */ | |
2307 | addr_dead_p = ((noreturn_p || sibcall_p | |
2308 | || TEST_HARD_REG_BIT (regs_invalidated_by_call, | |
2309 | REGNO (addr))) | |
2310 | && !FUNCTION_ARG_REGNO_P (REGNO (addr))); | |
2311 | ||
2312 | /* Load the code address into scratch_b. */ | |
2313 | tmp = gen_rtx_POST_INC (Pmode, addr); | |
2314 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2315 | emit_move_insn (scratch_r, tmp); | |
2316 | emit_move_insn (scratch_b, scratch_r); | |
2317 | ||
2318 | /* Load the GP address. If ADDR is not dead here, then we must | |
2319 | revert the change made above via the POST_INCREMENT. */ | |
2320 | if (!addr_dead_p) | |
2321 | tmp = gen_rtx_POST_DEC (Pmode, addr); | |
2322 | else | |
2323 | tmp = addr; | |
2324 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2325 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2326 | ||
2327 | is_desc = true; | |
2328 | addr = scratch_b; | |
2329 | } | |
2ed4af6f | 2330 | |
6dad5a56 | 2331 | if (sibcall_p) |
599aedd9 RH |
2332 | insn = gen_sibcall_nogp (addr); |
2333 | else if (retval) | |
2334 | insn = gen_call_value_nogp (retval, addr, retaddr); | |
6dad5a56 | 2335 | else |
599aedd9 | 2336 | insn = gen_call_nogp (addr, retaddr); |
6dad5a56 | 2337 | emit_call_insn (insn); |
2ed4af6f | 2338 | |
599aedd9 RH |
2339 | if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p) |
2340 | ia64_reload_gp (); | |
2ed4af6f | 2341 | } |
16df4ee6 RH |
2342 | |
2343 | /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically. | |
2344 | ||
2345 | This differs from the generic code in that we know about the zero-extending | |
2346 | properties of cmpxchg, and the zero-extending requirements of ar.ccv. We | |
2347 | also know that ld.acq+cmpxchg.rel equals a full barrier. | |
2348 | ||
2349 | The loop we want to generate looks like | |
2350 | ||
2351 | cmp_reg = mem; | |
2352 | label: | |
2353 | old_reg = cmp_reg; | |
2354 | new_reg = cmp_reg op val; | |
2355 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) | |
2356 | if (cmp_reg != old_reg) | |
2357 | goto label; | |
2358 | ||
2359 | Note that we only do the plain load from memory once. Subsequent | |
2360 | iterations use the value loaded by the compare-and-swap pattern. */ | |
2361 | ||
2362 | void | |
2363 | ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
28875d67 | 2364 | rtx old_dst, rtx new_dst, enum memmodel model) |
16df4ee6 | 2365 | { |
ef4bddc2 | 2366 | machine_mode mode = GET_MODE (mem); |
16df4ee6 RH |
2367 | rtx old_reg, new_reg, cmp_reg, ar_ccv, label; |
2368 | enum insn_code icode; | |
2369 | ||
2370 | /* Special case for using fetchadd. */ | |
dca13767 JJ |
2371 | if ((mode == SImode || mode == DImode) |
2372 | && (code == PLUS || code == MINUS) | |
2373 | && fetchadd_operand (val, mode)) | |
16df4ee6 | 2374 | { |
dca13767 JJ |
2375 | if (code == MINUS) |
2376 | val = GEN_INT (-INTVAL (val)); | |
2377 | ||
16df4ee6 RH |
2378 | if (!old_dst) |
2379 | old_dst = gen_reg_rtx (mode); | |
2380 | ||
28875d67 RH |
2381 | switch (model) |
2382 | { | |
2383 | case MEMMODEL_ACQ_REL: | |
2384 | case MEMMODEL_SEQ_CST: | |
46b35980 | 2385 | case MEMMODEL_SYNC_SEQ_CST: |
28875d67 RH |
2386 | emit_insn (gen_memory_barrier ()); |
2387 | /* FALLTHRU */ | |
2388 | case MEMMODEL_RELAXED: | |
2389 | case MEMMODEL_ACQUIRE: | |
46b35980 | 2390 | case MEMMODEL_SYNC_ACQUIRE: |
28875d67 RH |
2391 | case MEMMODEL_CONSUME: |
2392 | if (mode == SImode) | |
2393 | icode = CODE_FOR_fetchadd_acq_si; | |
2394 | else | |
2395 | icode = CODE_FOR_fetchadd_acq_di; | |
2396 | break; | |
2397 | case MEMMODEL_RELEASE: | |
46b35980 | 2398 | case MEMMODEL_SYNC_RELEASE: |
28875d67 RH |
2399 | if (mode == SImode) |
2400 | icode = CODE_FOR_fetchadd_rel_si; | |
2401 | else | |
2402 | icode = CODE_FOR_fetchadd_rel_di; | |
2403 | break; | |
2404 | ||
2405 | default: | |
2406 | gcc_unreachable (); | |
2407 | } | |
16df4ee6 | 2408 | |
16df4ee6 RH |
2409 | emit_insn (GEN_FCN (icode) (old_dst, mem, val)); |
2410 | ||
2411 | if (new_dst) | |
2412 | { | |
2413 | new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst, | |
2414 | true, OPTAB_WIDEN); | |
2415 | if (new_reg != new_dst) | |
2416 | emit_move_insn (new_dst, new_reg); | |
2417 | } | |
2418 | return; | |
2419 | } | |
2420 | ||
2421 | /* Because of the volatile mem read, we get an ld.acq, which is the | |
28875d67 RH |
2422 | front half of the full barrier. The end half is the cmpxchg.rel. |
2423 | For relaxed and release memory models, we don't need this. But we | |
2424 | also don't bother trying to prevent it either. */ | |
46b35980 | 2425 | gcc_assert (is_mm_relaxed (model) || is_mm_release (model) |
28875d67 | 2426 | || MEM_VOLATILE_P (mem)); |
16df4ee6 RH |
2427 | |
2428 | old_reg = gen_reg_rtx (DImode); | |
2429 | cmp_reg = gen_reg_rtx (DImode); | |
2430 | label = gen_label_rtx (); | |
2431 | ||
2432 | if (mode != DImode) | |
2433 | { | |
2434 | val = simplify_gen_subreg (DImode, val, mode, 0); | |
2435 | emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1)); | |
2436 | } | |
2437 | else | |
2438 | emit_move_insn (cmp_reg, mem); | |
2439 | ||
2440 | emit_label (label); | |
2441 | ||
2442 | ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM); | |
2443 | emit_move_insn (old_reg, cmp_reg); | |
2444 | emit_move_insn (ar_ccv, cmp_reg); | |
2445 | ||
2446 | if (old_dst) | |
2447 | emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg)); | |
2448 | ||
2449 | new_reg = cmp_reg; | |
2450 | if (code == NOT) | |
2451 | { | |
974920dc UB |
2452 | new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX, |
2453 | true, OPTAB_DIRECT); | |
2454 | new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true); | |
16df4ee6 | 2455 | } |
974920dc UB |
2456 | else |
2457 | new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX, | |
2458 | true, OPTAB_DIRECT); | |
16df4ee6 RH |
2459 | |
2460 | if (mode != DImode) | |
2461 | new_reg = gen_lowpart (mode, new_reg); | |
2462 | if (new_dst) | |
2463 | emit_move_insn (new_dst, new_reg); | |
2464 | ||
28875d67 | 2465 | switch (model) |
16df4ee6 | 2466 | { |
28875d67 RH |
2467 | case MEMMODEL_RELAXED: |
2468 | case MEMMODEL_ACQUIRE: | |
46b35980 | 2469 | case MEMMODEL_SYNC_ACQUIRE: |
28875d67 RH |
2470 | case MEMMODEL_CONSUME: |
2471 | switch (mode) | |
2472 | { | |
4e10a5a7 RS |
2473 | case E_QImode: icode = CODE_FOR_cmpxchg_acq_qi; break; |
2474 | case E_HImode: icode = CODE_FOR_cmpxchg_acq_hi; break; | |
2475 | case E_SImode: icode = CODE_FOR_cmpxchg_acq_si; break; | |
2476 | case E_DImode: icode = CODE_FOR_cmpxchg_acq_di; break; | |
28875d67 RH |
2477 | default: |
2478 | gcc_unreachable (); | |
2479 | } | |
2480 | break; | |
2481 | ||
2482 | case MEMMODEL_RELEASE: | |
46b35980 | 2483 | case MEMMODEL_SYNC_RELEASE: |
28875d67 RH |
2484 | case MEMMODEL_ACQ_REL: |
2485 | case MEMMODEL_SEQ_CST: | |
46b35980 | 2486 | case MEMMODEL_SYNC_SEQ_CST: |
28875d67 RH |
2487 | switch (mode) |
2488 | { | |
4e10a5a7 RS |
2489 | case E_QImode: icode = CODE_FOR_cmpxchg_rel_qi; break; |
2490 | case E_HImode: icode = CODE_FOR_cmpxchg_rel_hi; break; | |
2491 | case E_SImode: icode = CODE_FOR_cmpxchg_rel_si; break; | |
2492 | case E_DImode: icode = CODE_FOR_cmpxchg_rel_di; break; | |
28875d67 RH |
2493 | default: |
2494 | gcc_unreachable (); | |
2495 | } | |
2496 | break; | |
2497 | ||
16df4ee6 RH |
2498 | default: |
2499 | gcc_unreachable (); | |
2500 | } | |
2501 | ||
2502 | emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg)); | |
2503 | ||
6819a463 | 2504 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label); |
16df4ee6 | 2505 | } |
809d4ef1 | 2506 | \f |
3b572406 RH |
2507 | /* Begin the assembly file. */ |
2508 | ||
1bc7c5b6 | 2509 | static void |
9c808aad | 2510 | ia64_file_start (void) |
1bc7c5b6 ZW |
2511 | { |
2512 | default_file_start (); | |
2513 | emit_safe_across_calls (); | |
2514 | } | |
2515 | ||
3b572406 | 2516 | void |
9c808aad | 2517 | emit_safe_across_calls (void) |
3b572406 RH |
2518 | { |
2519 | unsigned int rs, re; | |
2520 | int out_state; | |
2521 | ||
2522 | rs = 1; | |
2523 | out_state = 0; | |
2524 | while (1) | |
2525 | { | |
2526 | while (rs < 64 && call_used_regs[PR_REG (rs)]) | |
2527 | rs++; | |
2528 | if (rs >= 64) | |
2529 | break; | |
2530 | for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++) | |
2531 | continue; | |
2532 | if (out_state == 0) | |
2533 | { | |
1bc7c5b6 | 2534 | fputs ("\t.pred.safe_across_calls ", asm_out_file); |
3b572406 RH |
2535 | out_state = 1; |
2536 | } | |
2537 | else | |
1bc7c5b6 | 2538 | fputc (',', asm_out_file); |
3b572406 | 2539 | if (re == rs + 1) |
1bc7c5b6 | 2540 | fprintf (asm_out_file, "p%u", rs); |
3b572406 | 2541 | else |
1bc7c5b6 | 2542 | fprintf (asm_out_file, "p%u-p%u", rs, re - 1); |
3b572406 RH |
2543 | rs = re + 1; |
2544 | } | |
2545 | if (out_state) | |
1bc7c5b6 | 2546 | fputc ('\n', asm_out_file); |
3b572406 RH |
2547 | } |
2548 | ||
812b587e SE |
2549 | /* Globalize a declaration. */ |
2550 | ||
2551 | static void | |
2552 | ia64_globalize_decl_name (FILE * stream, tree decl) | |
2553 | { | |
2554 | const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
2555 | tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl)); | |
2556 | if (version_attr) | |
2557 | { | |
2558 | tree v = TREE_VALUE (TREE_VALUE (version_attr)); | |
2559 | const char *p = TREE_STRING_POINTER (v); | |
2560 | fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p); | |
2561 | } | |
2562 | targetm.asm_out.globalize_label (stream, name); | |
2563 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2564 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); | |
2565 | } | |
2566 | ||
97e242b0 RH |
2567 | /* Helper function for ia64_compute_frame_size: find an appropriate general |
2568 | register to spill some special register to. SPECIAL_SPILL_MASK contains | |
2569 | bits in GR0 to GR31 that have already been allocated by this routine. | |
2570 | TRY_LOCALS is true if we should attempt to locate a local regnum. */ | |
c65ebc55 | 2571 | |
97e242b0 | 2572 | static int |
6fb5fa3c | 2573 | find_gr_spill (enum ia64_frame_regs r, int try_locals) |
97e242b0 RH |
2574 | { |
2575 | int regno; | |
2576 | ||
6fb5fa3c DB |
2577 | if (emitted_frame_related_regs[r] != 0) |
2578 | { | |
2579 | regno = emitted_frame_related_regs[r]; | |
2951f79b JJ |
2580 | if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed) |
2581 | && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1) | |
6fb5fa3c | 2582 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; |
416ff32e | 2583 | else if (crtl->is_leaf |
6fb5fa3c DB |
2584 | && regno >= GR_REG (1) && regno <= GR_REG (31)) |
2585 | current_frame_info.gr_used_mask |= 1 << regno; | |
2586 | ||
2587 | return regno; | |
2588 | } | |
2589 | ||
97e242b0 RH |
2590 | /* If this is a leaf function, first try an otherwise unused |
2591 | call-clobbered register. */ | |
416ff32e | 2592 | if (crtl->is_leaf) |
97e242b0 RH |
2593 | { |
2594 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) | |
6fb5fa3c | 2595 | if (! df_regs_ever_live_p (regno) |
97e242b0 RH |
2596 | && call_used_regs[regno] |
2597 | && ! fixed_regs[regno] | |
2598 | && ! global_regs[regno] | |
6fb5fa3c DB |
2599 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0 |
2600 | && ! is_emitted (regno)) | |
97e242b0 RH |
2601 | { |
2602 | current_frame_info.gr_used_mask |= 1 << regno; | |
2603 | return regno; | |
2604 | } | |
2605 | } | |
2606 | ||
2607 | if (try_locals) | |
2608 | { | |
2609 | regno = current_frame_info.n_local_regs; | |
9502c558 JW |
2610 | /* If there is a frame pointer, then we can't use loc79, because |
2611 | that is HARD_FRAME_POINTER_REGNUM. In particular, see the | |
2612 | reg_name switching code in ia64_expand_prologue. */ | |
2951f79b JJ |
2613 | while (regno < (80 - frame_pointer_needed)) |
2614 | if (! is_emitted (LOC_REG (regno++))) | |
2615 | { | |
2616 | current_frame_info.n_local_regs = regno; | |
2617 | return LOC_REG (regno - 1); | |
2618 | } | |
97e242b0 RH |
2619 | } |
2620 | ||
2621 | /* Failed to find a general register to spill to. Must use stack. */ | |
2622 | return 0; | |
2623 | } | |
2624 | ||
2625 | /* In order to make for nice schedules, we try to allocate every temporary | |
2626 | to a different register. We must of course stay away from call-saved, | |
2627 | fixed, and global registers. We must also stay away from registers | |
2628 | allocated in current_frame_info.gr_used_mask, since those include regs | |
2629 | used all through the prologue. | |
2630 | ||
2631 | Any register allocated here must be used immediately. The idea is to | |
2632 | aid scheduling, not to solve data flow problems. */ | |
2633 | ||
2634 | static int last_scratch_gr_reg; | |
2635 | ||
2636 | static int | |
9c808aad | 2637 | next_scratch_gr_reg (void) |
97e242b0 RH |
2638 | { |
2639 | int i, regno; | |
2640 | ||
2641 | for (i = 0; i < 32; ++i) | |
2642 | { | |
2643 | regno = (last_scratch_gr_reg + i + 1) & 31; | |
2644 | if (call_used_regs[regno] | |
2645 | && ! fixed_regs[regno] | |
2646 | && ! global_regs[regno] | |
2647 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0) | |
2648 | { | |
2649 | last_scratch_gr_reg = regno; | |
2650 | return regno; | |
2651 | } | |
2652 | } | |
2653 | ||
2654 | /* There must be _something_ available. */ | |
e820471b | 2655 | gcc_unreachable (); |
97e242b0 RH |
2656 | } |
2657 | ||
2658 | /* Helper function for ia64_compute_frame_size, called through | |
2659 | diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */ | |
2660 | ||
2661 | static void | |
9c808aad | 2662 | mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED) |
c65ebc55 | 2663 | { |
97e242b0 RH |
2664 | unsigned int regno = REGNO (reg); |
2665 | if (regno < 32) | |
f95e79cc | 2666 | { |
462a99aa | 2667 | unsigned int i, n = REG_NREGS (reg); |
f95e79cc RH |
2668 | for (i = 0; i < n; ++i) |
2669 | current_frame_info.gr_used_mask |= 1 << (regno + i); | |
2670 | } | |
c65ebc55 JW |
2671 | } |
2672 | ||
6fb5fa3c | 2673 | |
c65ebc55 JW |
2674 | /* Returns the number of bytes offset between the frame pointer and the stack |
2675 | pointer for the current function. SIZE is the number of bytes of space | |
2676 | needed for local variables. */ | |
97e242b0 RH |
2677 | |
2678 | static void | |
9c808aad | 2679 | ia64_compute_frame_size (HOST_WIDE_INT size) |
c65ebc55 | 2680 | { |
97e242b0 RH |
2681 | HOST_WIDE_INT total_size; |
2682 | HOST_WIDE_INT spill_size = 0; | |
2683 | HOST_WIDE_INT extra_spill_size = 0; | |
2684 | HOST_WIDE_INT pretend_args_size; | |
c65ebc55 | 2685 | HARD_REG_SET mask; |
97e242b0 RH |
2686 | int n_spilled = 0; |
2687 | int spilled_gr_p = 0; | |
2688 | int spilled_fr_p = 0; | |
2689 | unsigned int regno; | |
2951f79b JJ |
2690 | int min_regno; |
2691 | int max_regno; | |
97e242b0 | 2692 | int i; |
c65ebc55 | 2693 | |
97e242b0 RH |
2694 | if (current_frame_info.initialized) |
2695 | return; | |
294dac80 | 2696 | |
97e242b0 | 2697 | memset (¤t_frame_info, 0, sizeof current_frame_info); |
c65ebc55 JW |
2698 | CLEAR_HARD_REG_SET (mask); |
2699 | ||
97e242b0 RH |
2700 | /* Don't allocate scratches to the return register. */ |
2701 | diddle_return_value (mark_reg_gr_used_mask, NULL); | |
2702 | ||
2703 | /* Don't allocate scratches to the EH scratch registers. */ | |
2704 | if (cfun->machine->ia64_eh_epilogue_sp) | |
2705 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL); | |
2706 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
2707 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL); | |
c65ebc55 | 2708 | |
7b84aac0 | 2709 | /* Static stack checking uses r2 and r3. */ |
9c1b56c4 JL |
2710 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK |
2711 | || flag_stack_clash_protection) | |
7b84aac0 EB |
2712 | current_frame_info.gr_used_mask |= 0xc; |
2713 | ||
97e242b0 RH |
2714 | /* Find the size of the register stack frame. We have only 80 local |
2715 | registers, because we reserve 8 for the inputs and 8 for the | |
2716 | outputs. */ | |
2717 | ||
2718 | /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed, | |
2719 | since we'll be adjusting that down later. */ | |
2720 | regno = LOC_REG (78) + ! frame_pointer_needed; | |
2721 | for (; regno >= LOC_REG (0); regno--) | |
6fb5fa3c | 2722 | if (df_regs_ever_live_p (regno) && !is_emitted (regno)) |
97e242b0 RH |
2723 | break; |
2724 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; | |
c65ebc55 | 2725 | |
3f67ac08 DM |
2726 | /* For functions marked with the syscall_linkage attribute, we must mark |
2727 | all eight input registers as in use, so that locals aren't visible to | |
2728 | the caller. */ | |
2729 | ||
2730 | if (cfun->machine->n_varargs > 0 | |
2731 | || lookup_attribute ("syscall_linkage", | |
2732 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
97e242b0 RH |
2733 | current_frame_info.n_input_regs = 8; |
2734 | else | |
2735 | { | |
2736 | for (regno = IN_REG (7); regno >= IN_REG (0); regno--) | |
6fb5fa3c | 2737 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2738 | break; |
2739 | current_frame_info.n_input_regs = regno - IN_REG (0) + 1; | |
2740 | } | |
2741 | ||
2742 | for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--) | |
6fb5fa3c | 2743 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2744 | break; |
2745 | i = regno - OUT_REG (0) + 1; | |
2746 | ||
d26afa4f | 2747 | #ifndef PROFILE_HOOK |
97e242b0 | 2748 | /* When -p profiling, we need one output register for the mcount argument. |
9e4f94de | 2749 | Likewise for -a profiling for the bb_init_func argument. For -ax |
97e242b0 RH |
2750 | profiling, we need two output registers for the two bb_init_trace_func |
2751 | arguments. */ | |
e3b5732b | 2752 | if (crtl->profile) |
97e242b0 | 2753 | i = MAX (i, 1); |
d26afa4f | 2754 | #endif |
97e242b0 RH |
2755 | current_frame_info.n_output_regs = i; |
2756 | ||
2757 | /* ??? No rotating register support yet. */ | |
2758 | current_frame_info.n_rotate_regs = 0; | |
2759 | ||
2760 | /* Discover which registers need spilling, and how much room that | |
9c808aad | 2761 | will take. Begin with floating point and general registers, |
97e242b0 RH |
2762 | which will always wind up on the stack. */ |
2763 | ||
2764 | for (regno = FR_REG (2); regno <= FR_REG (127); regno++) | |
6fb5fa3c | 2765 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2766 | { |
2767 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2768 | spill_size += 16; |
2769 | n_spilled += 1; | |
2770 | spilled_fr_p = 1; | |
c65ebc55 JW |
2771 | } |
2772 | ||
97e242b0 | 2773 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) |
6fb5fa3c | 2774 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2775 | { |
2776 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2777 | spill_size += 8; |
2778 | n_spilled += 1; | |
2779 | spilled_gr_p = 1; | |
c65ebc55 JW |
2780 | } |
2781 | ||
97e242b0 | 2782 | for (regno = BR_REG (1); regno <= BR_REG (7); regno++) |
6fb5fa3c | 2783 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2784 | { |
2785 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2786 | spill_size += 8; |
2787 | n_spilled += 1; | |
c65ebc55 JW |
2788 | } |
2789 | ||
97e242b0 RH |
2790 | /* Now come all special registers that might get saved in other |
2791 | general registers. */ | |
9c808aad | 2792 | |
97e242b0 RH |
2793 | if (frame_pointer_needed) |
2794 | { | |
6fb5fa3c | 2795 | current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1); |
0c35f902 JW |
2796 | /* If we did not get a register, then we take LOC79. This is guaranteed |
2797 | to be free, even if regs_ever_live is already set, because this is | |
2798 | HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs, | |
2799 | as we don't count loc79 above. */ | |
6fb5fa3c | 2800 | if (current_frame_info.r[reg_fp] == 0) |
0c35f902 | 2801 | { |
6fb5fa3c DB |
2802 | current_frame_info.r[reg_fp] = LOC_REG (79); |
2803 | current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1; | |
0c35f902 | 2804 | } |
97e242b0 RH |
2805 | } |
2806 | ||
416ff32e | 2807 | if (! crtl->is_leaf) |
c65ebc55 | 2808 | { |
97e242b0 RH |
2809 | /* Emit a save of BR0 if we call other functions. Do this even |
2810 | if this function doesn't return, as EH depends on this to be | |
2811 | able to unwind the stack. */ | |
2812 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
2813 | ||
6fb5fa3c DB |
2814 | current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1); |
2815 | if (current_frame_info.r[reg_save_b0] == 0) | |
97e242b0 | 2816 | { |
ae1e2d4c | 2817 | extra_spill_size += 8; |
97e242b0 RH |
2818 | n_spilled += 1; |
2819 | } | |
2820 | ||
2821 | /* Similarly for ar.pfs. */ | |
2822 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2823 | current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1); |
2824 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
97e242b0 RH |
2825 | { |
2826 | extra_spill_size += 8; | |
2827 | n_spilled += 1; | |
2828 | } | |
599aedd9 RH |
2829 | |
2830 | /* Similarly for gp. Note that if we're calling setjmp, the stacked | |
2831 | registers are clobbered, so we fall back to the stack. */ | |
6fb5fa3c | 2832 | current_frame_info.r[reg_save_gp] |
e3b5732b | 2833 | = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1)); |
6fb5fa3c | 2834 | if (current_frame_info.r[reg_save_gp] == 0) |
599aedd9 RH |
2835 | { |
2836 | SET_HARD_REG_BIT (mask, GR_REG (1)); | |
2837 | spill_size += 8; | |
2838 | n_spilled += 1; | |
2839 | } | |
c65ebc55 JW |
2840 | } |
2841 | else | |
97e242b0 | 2842 | { |
6fb5fa3c | 2843 | if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)]) |
97e242b0 RH |
2844 | { |
2845 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
ae1e2d4c | 2846 | extra_spill_size += 8; |
97e242b0 RH |
2847 | n_spilled += 1; |
2848 | } | |
f5bdba44 | 2849 | |
6fb5fa3c | 2850 | if (df_regs_ever_live_p (AR_PFS_REGNUM)) |
f5bdba44 RH |
2851 | { |
2852 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2853 | current_frame_info.r[reg_save_ar_pfs] |
2854 | = find_gr_spill (reg_save_ar_pfs, 1); | |
2855 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
f5bdba44 RH |
2856 | { |
2857 | extra_spill_size += 8; | |
2858 | n_spilled += 1; | |
2859 | } | |
2860 | } | |
97e242b0 | 2861 | } |
c65ebc55 | 2862 | |
97e242b0 RH |
2863 | /* Unwind descriptor hackery: things are most efficient if we allocate |
2864 | consecutive GR save registers for RP, PFS, FP in that order. However, | |
2865 | it is absolutely critical that FP get the only hard register that's | |
2866 | guaranteed to be free, so we allocated it first. If all three did | |
2867 | happen to be allocated hard regs, and are consecutive, rearrange them | |
6fb5fa3c DB |
2868 | into the preferred order now. |
2869 | ||
2870 | If we have already emitted code for any of those registers, | |
2871 | then it's already too late to change. */ | |
2951f79b JJ |
2872 | min_regno = MIN (current_frame_info.r[reg_fp], |
2873 | MIN (current_frame_info.r[reg_save_b0], | |
2874 | current_frame_info.r[reg_save_ar_pfs])); | |
2875 | max_regno = MAX (current_frame_info.r[reg_fp], | |
2876 | MAX (current_frame_info.r[reg_save_b0], | |
2877 | current_frame_info.r[reg_save_ar_pfs])); | |
2878 | if (min_regno > 0 | |
2879 | && min_regno + 2 == max_regno | |
2880 | && (current_frame_info.r[reg_fp] == min_regno + 1 | |
2881 | || current_frame_info.r[reg_save_b0] == min_regno + 1 | |
2882 | || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1) | |
2883 | && (emitted_frame_related_regs[reg_save_b0] == 0 | |
2884 | || emitted_frame_related_regs[reg_save_b0] == min_regno) | |
2885 | && (emitted_frame_related_regs[reg_save_ar_pfs] == 0 | |
2886 | || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1) | |
2887 | && (emitted_frame_related_regs[reg_fp] == 0 | |
2888 | || emitted_frame_related_regs[reg_fp] == min_regno + 2)) | |
5527bf14 | 2889 | { |
2951f79b JJ |
2890 | current_frame_info.r[reg_save_b0] = min_regno; |
2891 | current_frame_info.r[reg_save_ar_pfs] = min_regno + 1; | |
2892 | current_frame_info.r[reg_fp] = min_regno + 2; | |
5527bf14 RH |
2893 | } |
2894 | ||
97e242b0 RH |
2895 | /* See if we need to store the predicate register block. */ |
2896 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2897 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
97e242b0 RH |
2898 | break; |
2899 | if (regno <= PR_REG (63)) | |
c65ebc55 | 2900 | { |
97e242b0 | 2901 | SET_HARD_REG_BIT (mask, PR_REG (0)); |
6fb5fa3c DB |
2902 | current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1); |
2903 | if (current_frame_info.r[reg_save_pr] == 0) | |
97e242b0 RH |
2904 | { |
2905 | extra_spill_size += 8; | |
2906 | n_spilled += 1; | |
2907 | } | |
2908 | ||
2909 | /* ??? Mark them all as used so that register renaming and such | |
2910 | are free to use them. */ | |
2911 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2912 | df_set_regs_ever_live (regno, true); |
c65ebc55 JW |
2913 | } |
2914 | ||
97e242b0 | 2915 | /* If we're forced to use st8.spill, we're forced to save and restore |
f5bdba44 RH |
2916 | ar.unat as well. The check for existing liveness allows inline asm |
2917 | to touch ar.unat. */ | |
2918 | if (spilled_gr_p || cfun->machine->n_varargs | |
6fb5fa3c | 2919 | || df_regs_ever_live_p (AR_UNAT_REGNUM)) |
97e242b0 | 2920 | { |
6fb5fa3c | 2921 | df_set_regs_ever_live (AR_UNAT_REGNUM, true); |
97e242b0 | 2922 | SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM); |
6fb5fa3c DB |
2923 | current_frame_info.r[reg_save_ar_unat] |
2924 | = find_gr_spill (reg_save_ar_unat, spill_size == 0); | |
2925 | if (current_frame_info.r[reg_save_ar_unat] == 0) | |
97e242b0 RH |
2926 | { |
2927 | extra_spill_size += 8; | |
2928 | n_spilled += 1; | |
2929 | } | |
2930 | } | |
2931 | ||
6fb5fa3c | 2932 | if (df_regs_ever_live_p (AR_LC_REGNUM)) |
97e242b0 RH |
2933 | { |
2934 | SET_HARD_REG_BIT (mask, AR_LC_REGNUM); | |
6fb5fa3c DB |
2935 | current_frame_info.r[reg_save_ar_lc] |
2936 | = find_gr_spill (reg_save_ar_lc, spill_size == 0); | |
2937 | if (current_frame_info.r[reg_save_ar_lc] == 0) | |
97e242b0 RH |
2938 | { |
2939 | extra_spill_size += 8; | |
2940 | n_spilled += 1; | |
2941 | } | |
2942 | } | |
2943 | ||
2944 | /* If we have an odd number of words of pretend arguments written to | |
2945 | the stack, then the FR save area will be unaligned. We round the | |
2946 | size of this area up to keep things 16 byte aligned. */ | |
2947 | if (spilled_fr_p) | |
38173d38 | 2948 | pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size); |
97e242b0 | 2949 | else |
38173d38 | 2950 | pretend_args_size = crtl->args.pretend_args_size; |
97e242b0 RH |
2951 | |
2952 | total_size = (spill_size + extra_spill_size + size + pretend_args_size | |
38173d38 | 2953 | + crtl->outgoing_args_size); |
97e242b0 RH |
2954 | total_size = IA64_STACK_ALIGN (total_size); |
2955 | ||
2956 | /* We always use the 16-byte scratch area provided by the caller, but | |
2957 | if we are a leaf function, there's no one to which we need to provide | |
44bd7f65 EB |
2958 | a scratch area. However, if the function allocates dynamic stack space, |
2959 | the dynamic offset is computed early and contains STACK_POINTER_OFFSET, | |
2960 | so we need to cope. */ | |
2961 | if (crtl->is_leaf && !cfun->calls_alloca) | |
97e242b0 RH |
2962 | total_size = MAX (0, total_size - 16); |
2963 | ||
c65ebc55 | 2964 | current_frame_info.total_size = total_size; |
97e242b0 RH |
2965 | current_frame_info.spill_cfa_off = pretend_args_size - 16; |
2966 | current_frame_info.spill_size = spill_size; | |
2967 | current_frame_info.extra_spill_size = extra_spill_size; | |
6576d245 | 2968 | current_frame_info.mask = mask; |
97e242b0 | 2969 | current_frame_info.n_spilled = n_spilled; |
c65ebc55 | 2970 | current_frame_info.initialized = reload_completed; |
97e242b0 RH |
2971 | } |
2972 | ||
7b5cbb57 AS |
2973 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
2974 | ||
2975 | bool | |
2976 | ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
2977 | { | |
416ff32e | 2978 | return (to == BR_REG (0) ? crtl->is_leaf : true); |
7b5cbb57 AS |
2979 | } |
2980 | ||
97e242b0 RH |
2981 | /* Compute the initial difference between the specified pair of registers. */ |
2982 | ||
2983 | HOST_WIDE_INT | |
9c808aad | 2984 | ia64_initial_elimination_offset (int from, int to) |
97e242b0 RH |
2985 | { |
2986 | HOST_WIDE_INT offset; | |
2987 | ||
2988 | ia64_compute_frame_size (get_frame_size ()); | |
2989 | switch (from) | |
2990 | { | |
2991 | case FRAME_POINTER_REGNUM: | |
e820471b | 2992 | switch (to) |
97e242b0 | 2993 | { |
e820471b | 2994 | case HARD_FRAME_POINTER_REGNUM: |
44bd7f65 EB |
2995 | offset = -current_frame_info.total_size; |
2996 | if (!crtl->is_leaf || cfun->calls_alloca) | |
2997 | offset += 16 + crtl->outgoing_args_size; | |
e820471b NS |
2998 | break; |
2999 | ||
3000 | case STACK_POINTER_REGNUM: | |
44bd7f65 EB |
3001 | offset = 0; |
3002 | if (!crtl->is_leaf || cfun->calls_alloca) | |
3003 | offset += 16 + crtl->outgoing_args_size; | |
e820471b NS |
3004 | break; |
3005 | ||
3006 | default: | |
3007 | gcc_unreachable (); | |
97e242b0 | 3008 | } |
97e242b0 | 3009 | break; |
c65ebc55 | 3010 | |
97e242b0 RH |
3011 | case ARG_POINTER_REGNUM: |
3012 | /* Arguments start above the 16 byte save area, unless stdarg | |
3013 | in which case we store through the 16 byte save area. */ | |
e820471b NS |
3014 | switch (to) |
3015 | { | |
3016 | case HARD_FRAME_POINTER_REGNUM: | |
38173d38 | 3017 | offset = 16 - crtl->args.pretend_args_size; |
e820471b NS |
3018 | break; |
3019 | ||
3020 | case STACK_POINTER_REGNUM: | |
3021 | offset = (current_frame_info.total_size | |
38173d38 | 3022 | + 16 - crtl->args.pretend_args_size); |
e820471b NS |
3023 | break; |
3024 | ||
3025 | default: | |
3026 | gcc_unreachable (); | |
3027 | } | |
97e242b0 RH |
3028 | break; |
3029 | ||
97e242b0 | 3030 | default: |
e820471b | 3031 | gcc_unreachable (); |
97e242b0 RH |
3032 | } |
3033 | ||
3034 | return offset; | |
c65ebc55 JW |
3035 | } |
3036 | ||
97e242b0 RH |
3037 | /* If there are more than a trivial number of register spills, we use |
3038 | two interleaved iterators so that we can get two memory references | |
3039 | per insn group. | |
3040 | ||
3041 | In order to simplify things in the prologue and epilogue expanders, | |
3042 | we use helper functions to fix up the memory references after the | |
3043 | fact with the appropriate offsets to a POST_MODIFY memory mode. | |
3044 | The following data structure tracks the state of the two iterators | |
3045 | while insns are being emitted. */ | |
3046 | ||
3047 | struct spill_fill_data | |
c65ebc55 | 3048 | { |
dd3d2b35 | 3049 | rtx_insn *init_after; /* point at which to emit initializations */ |
97e242b0 RH |
3050 | rtx init_reg[2]; /* initial base register */ |
3051 | rtx iter_reg[2]; /* the iterator registers */ | |
3052 | rtx *prev_addr[2]; /* address of last memory use */ | |
dd3d2b35 | 3053 | rtx_insn *prev_insn[2]; /* the insn corresponding to prev_addr */ |
97e242b0 RH |
3054 | HOST_WIDE_INT prev_off[2]; /* last offset */ |
3055 | int n_iter; /* number of iterators in use */ | |
3056 | int next_iter; /* next iterator to use */ | |
3057 | unsigned int save_gr_used_mask; | |
3058 | }; | |
3059 | ||
3060 | static struct spill_fill_data spill_fill_data; | |
c65ebc55 | 3061 | |
97e242b0 | 3062 | static void |
9c808aad | 3063 | setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3064 | { |
3065 | int i; | |
3066 | ||
3067 | spill_fill_data.init_after = get_last_insn (); | |
3068 | spill_fill_data.init_reg[0] = init_reg; | |
3069 | spill_fill_data.init_reg[1] = init_reg; | |
3070 | spill_fill_data.prev_addr[0] = NULL; | |
3071 | spill_fill_data.prev_addr[1] = NULL; | |
703cf211 BS |
3072 | spill_fill_data.prev_insn[0] = NULL; |
3073 | spill_fill_data.prev_insn[1] = NULL; | |
97e242b0 RH |
3074 | spill_fill_data.prev_off[0] = cfa_off; |
3075 | spill_fill_data.prev_off[1] = cfa_off; | |
3076 | spill_fill_data.next_iter = 0; | |
3077 | spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask; | |
3078 | ||
3079 | spill_fill_data.n_iter = 1 + (n_spills > 2); | |
3080 | for (i = 0; i < spill_fill_data.n_iter; ++i) | |
c65ebc55 | 3081 | { |
97e242b0 RH |
3082 | int regno = next_scratch_gr_reg (); |
3083 | spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno); | |
3084 | current_frame_info.gr_used_mask |= 1 << regno; | |
3085 | } | |
3086 | } | |
3087 | ||
3088 | static void | |
9c808aad | 3089 | finish_spill_pointers (void) |
97e242b0 RH |
3090 | { |
3091 | current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask; | |
3092 | } | |
c65ebc55 | 3093 | |
97e242b0 | 3094 | static rtx |
9c808aad | 3095 | spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3096 | { |
3097 | int iter = spill_fill_data.next_iter; | |
3098 | HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off; | |
3099 | rtx disp_rtx = GEN_INT (disp); | |
3100 | rtx mem; | |
3101 | ||
3102 | if (spill_fill_data.prev_addr[iter]) | |
3103 | { | |
13f70342 | 3104 | if (satisfies_constraint_N (disp_rtx)) |
703cf211 BS |
3105 | { |
3106 | *spill_fill_data.prev_addr[iter] | |
3107 | = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter], | |
3108 | gen_rtx_PLUS (DImode, | |
3109 | spill_fill_data.iter_reg[iter], | |
3110 | disp_rtx)); | |
bbbbb16a ILT |
3111 | add_reg_note (spill_fill_data.prev_insn[iter], |
3112 | REG_INC, spill_fill_data.iter_reg[iter]); | |
703cf211 | 3113 | } |
c65ebc55 JW |
3114 | else |
3115 | { | |
97e242b0 | 3116 | /* ??? Could use register post_modify for loads. */ |
13f70342 | 3117 | if (!satisfies_constraint_I (disp_rtx)) |
97e242b0 RH |
3118 | { |
3119 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); | |
3120 | emit_move_insn (tmp, disp_rtx); | |
3121 | disp_rtx = tmp; | |
3122 | } | |
3123 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3124 | spill_fill_data.iter_reg[iter], disp_rtx)); | |
c65ebc55 | 3125 | } |
97e242b0 RH |
3126 | } |
3127 | /* Micro-optimization: if we've created a frame pointer, it's at | |
3128 | CFA 0, which may allow the real iterator to be initialized lower, | |
3129 | slightly increasing parallelism. Also, if there are few saves | |
3130 | it may eliminate the iterator entirely. */ | |
3131 | else if (disp == 0 | |
3132 | && spill_fill_data.init_reg[iter] == stack_pointer_rtx | |
3133 | && frame_pointer_needed) | |
3134 | { | |
3135 | mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx); | |
ba4828e0 | 3136 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
97e242b0 RH |
3137 | return mem; |
3138 | } | |
3139 | else | |
3140 | { | |
dd3d2b35 DM |
3141 | rtx seq; |
3142 | rtx_insn *insn; | |
809d4ef1 | 3143 | |
97e242b0 RH |
3144 | if (disp == 0) |
3145 | seq = gen_movdi (spill_fill_data.iter_reg[iter], | |
3146 | spill_fill_data.init_reg[iter]); | |
3147 | else | |
c65ebc55 | 3148 | { |
97e242b0 RH |
3149 | start_sequence (); |
3150 | ||
13f70342 | 3151 | if (!satisfies_constraint_I (disp_rtx)) |
c65ebc55 | 3152 | { |
97e242b0 RH |
3153 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); |
3154 | emit_move_insn (tmp, disp_rtx); | |
3155 | disp_rtx = tmp; | |
c65ebc55 | 3156 | } |
97e242b0 RH |
3157 | |
3158 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3159 | spill_fill_data.init_reg[iter], | |
3160 | disp_rtx)); | |
3161 | ||
2f937369 | 3162 | seq = get_insns (); |
97e242b0 | 3163 | end_sequence (); |
c65ebc55 | 3164 | } |
809d4ef1 | 3165 | |
97e242b0 RH |
3166 | /* Careful for being the first insn in a sequence. */ |
3167 | if (spill_fill_data.init_after) | |
892a4e60 | 3168 | insn = emit_insn_after (seq, spill_fill_data.init_after); |
97e242b0 | 3169 | else |
bc08aefe | 3170 | { |
dd3d2b35 | 3171 | rtx_insn *first = get_insns (); |
bc08aefe | 3172 | if (first) |
892a4e60 | 3173 | insn = emit_insn_before (seq, first); |
bc08aefe | 3174 | else |
892a4e60 | 3175 | insn = emit_insn (seq); |
bc08aefe | 3176 | } |
892a4e60 | 3177 | spill_fill_data.init_after = insn; |
97e242b0 | 3178 | } |
c65ebc55 | 3179 | |
97e242b0 | 3180 | mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]); |
c65ebc55 | 3181 | |
97e242b0 RH |
3182 | /* ??? Not all of the spills are for varargs, but some of them are. |
3183 | The rest of the spills belong in an alias set of their own. But | |
3184 | it doesn't actually hurt to include them here. */ | |
ba4828e0 | 3185 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
809d4ef1 | 3186 | |
97e242b0 RH |
3187 | spill_fill_data.prev_addr[iter] = &XEXP (mem, 0); |
3188 | spill_fill_data.prev_off[iter] = cfa_off; | |
c65ebc55 | 3189 | |
97e242b0 RH |
3190 | if (++iter >= spill_fill_data.n_iter) |
3191 | iter = 0; | |
3192 | spill_fill_data.next_iter = iter; | |
c65ebc55 | 3193 | |
97e242b0 RH |
3194 | return mem; |
3195 | } | |
5527bf14 | 3196 | |
97e242b0 | 3197 | static void |
9c808aad AJ |
3198 | do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off, |
3199 | rtx frame_reg) | |
97e242b0 | 3200 | { |
703cf211 | 3201 | int iter = spill_fill_data.next_iter; |
dd3d2b35 DM |
3202 | rtx mem; |
3203 | rtx_insn *insn; | |
5527bf14 | 3204 | |
97e242b0 | 3205 | mem = spill_restore_mem (reg, cfa_off); |
870f9ec0 | 3206 | insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off))); |
703cf211 | 3207 | spill_fill_data.prev_insn[iter] = insn; |
5527bf14 | 3208 | |
97e242b0 RH |
3209 | if (frame_reg) |
3210 | { | |
3211 | rtx base; | |
3212 | HOST_WIDE_INT off; | |
3213 | ||
3214 | RTX_FRAME_RELATED_P (insn) = 1; | |
3215 | ||
9c808aad | 3216 | /* Don't even pretend that the unwind code can intuit its way |
97e242b0 RH |
3217 | through a pair of interleaved post_modify iterators. Just |
3218 | provide the correct answer. */ | |
3219 | ||
3220 | if (frame_pointer_needed) | |
3221 | { | |
3222 | base = hard_frame_pointer_rtx; | |
3223 | off = - cfa_off; | |
5527bf14 | 3224 | } |
97e242b0 RH |
3225 | else |
3226 | { | |
3227 | base = stack_pointer_rtx; | |
3228 | off = current_frame_info.total_size - cfa_off; | |
3229 | } | |
3230 | ||
5c255b57 | 3231 | add_reg_note (insn, REG_CFA_OFFSET, |
f7df4a84 | 3232 | gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg), |
0a81f074 RS |
3233 | plus_constant (Pmode, |
3234 | base, off)), | |
bbbbb16a | 3235 | frame_reg)); |
c65ebc55 JW |
3236 | } |
3237 | } | |
3238 | ||
97e242b0 | 3239 | static void |
9c808aad | 3240 | do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 | 3241 | { |
703cf211 | 3242 | int iter = spill_fill_data.next_iter; |
dd3d2b35 | 3243 | rtx_insn *insn; |
703cf211 BS |
3244 | |
3245 | insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off), | |
3246 | GEN_INT (cfa_off))); | |
3247 | spill_fill_data.prev_insn[iter] = insn; | |
97e242b0 RH |
3248 | } |
3249 | ||
870f9ec0 RH |
3250 | /* Wrapper functions that discards the CONST_INT spill offset. These |
3251 | exist so that we can give gr_spill/gr_fill the offset they need and | |
9e4f94de | 3252 | use a consistent function interface. */ |
870f9ec0 RH |
3253 | |
3254 | static rtx | |
9c808aad | 3255 | gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3256 | { |
3257 | return gen_movdi (dest, src); | |
3258 | } | |
3259 | ||
3260 | static rtx | |
9c808aad | 3261 | gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3262 | { |
3263 | return gen_fr_spill (dest, src); | |
3264 | } | |
3265 | ||
3266 | static rtx | |
9c808aad | 3267 | gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3268 | { |
3269 | return gen_fr_restore (dest, src); | |
3270 | } | |
c65ebc55 | 3271 | |
7b84aac0 EB |
3272 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) |
3273 | ||
3274 | /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */ | |
3275 | #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0) | |
3276 | ||
3277 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
0dca9cd8 EB |
3278 | inclusive. These are offsets from the current stack pointer. BS_SIZE |
3279 | is the size of the backing store. ??? This clobbers r2 and r3. */ | |
7b84aac0 EB |
3280 | |
3281 | static void | |
0dca9cd8 EB |
3282 | ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size, |
3283 | int bs_size) | |
7b84aac0 | 3284 | { |
7b84aac0 EB |
3285 | rtx r2 = gen_rtx_REG (Pmode, GR_REG (2)); |
3286 | rtx r3 = gen_rtx_REG (Pmode, GR_REG (3)); | |
0dca9cd8 EB |
3287 | rtx p6 = gen_rtx_REG (BImode, PR_REG (6)); |
3288 | ||
3289 | /* On the IA-64 there is a second stack in memory, namely the Backing Store | |
3290 | of the Register Stack Engine. We also need to probe it after checking | |
3291 | that the 2 stacks don't overlap. */ | |
3292 | emit_insn (gen_bsp_value (r3)); | |
3293 | emit_move_insn (r2, GEN_INT (-(first + size))); | |
3294 | ||
3295 | /* Compare current value of BSP and SP registers. */ | |
f7df4a84 RS |
3296 | emit_insn (gen_rtx_SET (p6, gen_rtx_fmt_ee (LTU, BImode, |
3297 | r3, stack_pointer_rtx))); | |
0dca9cd8 EB |
3298 | |
3299 | /* Compute the address of the probe for the Backing Store (which grows | |
3300 | towards higher addresses). We probe only at the first offset of | |
3301 | the next page because some OS (eg Linux/ia64) only extend the | |
3302 | backing store when this specific address is hit (but generate a SEGV | |
3303 | on other address). Page size is the worst case (4KB). The reserve | |
3304 | size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough. | |
3305 | Also compute the address of the last probe for the memory stack | |
3306 | (which grows towards lower addresses). */ | |
f7df4a84 RS |
3307 | emit_insn (gen_rtx_SET (r3, plus_constant (Pmode, r3, 4095))); |
3308 | emit_insn (gen_rtx_SET (r2, gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
0dca9cd8 EB |
3309 | |
3310 | /* Compare them and raise SEGV if the former has topped the latter. */ | |
3311 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3312 | gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx), | |
f7df4a84 RS |
3313 | gen_rtx_SET (p6, gen_rtx_fmt_ee (GEU, BImode, |
3314 | r3, r2)))); | |
3315 | emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12), | |
0dca9cd8 EB |
3316 | const0_rtx), |
3317 | const0_rtx)); | |
3318 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3319 | gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx), | |
3320 | gen_rtx_TRAP_IF (VOIDmode, const1_rtx, | |
3321 | GEN_INT (11)))); | |
7b84aac0 EB |
3322 | |
3323 | /* Probe the Backing Store if necessary. */ | |
3324 | if (bs_size > 0) | |
3325 | emit_stack_probe (r3); | |
3326 | ||
3327 | /* Probe the memory stack if necessary. */ | |
3328 | if (size == 0) | |
3329 | ; | |
3330 | ||
3331 | /* See if we have a constant small number of probes to generate. If so, | |
3332 | that's the easy case. */ | |
3333 | else if (size <= PROBE_INTERVAL) | |
3334 | emit_stack_probe (r2); | |
3335 | ||
73866e0d | 3336 | /* The run-time loop is made up of 9 insns in the generic case while this |
7b84aac0 EB |
3337 | compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */ |
3338 | else if (size <= 4 * PROBE_INTERVAL) | |
3339 | { | |
3340 | HOST_WIDE_INT i; | |
3341 | ||
3342 | emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL))); | |
f7df4a84 | 3343 | emit_insn (gen_rtx_SET (r2, |
7b84aac0 EB |
3344 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); |
3345 | emit_stack_probe (r2); | |
3346 | ||
3347 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until | |
3348 | it exceeds SIZE. If only two probes are needed, this will not | |
3349 | generate any code. Then probe at FIRST + SIZE. */ | |
3350 | for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
3351 | { | |
f7df4a84 | 3352 | emit_insn (gen_rtx_SET (r2, |
f65e3801 | 3353 | plus_constant (Pmode, r2, -PROBE_INTERVAL))); |
7b84aac0 EB |
3354 | emit_stack_probe (r2); |
3355 | } | |
3356 | ||
f7df4a84 | 3357 | emit_insn (gen_rtx_SET (r2, |
f65e3801 | 3358 | plus_constant (Pmode, r2, |
7b84aac0 EB |
3359 | (i - PROBE_INTERVAL) - size))); |
3360 | emit_stack_probe (r2); | |
3361 | } | |
3362 | ||
3363 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
3364 | extra careful with variables wrapping around because we might be at | |
3365 | the very top (or the very bottom) of the address space and we have | |
3366 | to be able to handle this case properly; in particular, we use an | |
3367 | equality test for the loop condition. */ | |
3368 | else | |
3369 | { | |
3370 | HOST_WIDE_INT rounded_size; | |
3371 | ||
3372 | emit_move_insn (r2, GEN_INT (-first)); | |
3373 | ||
3374 | ||
3375 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
3376 | ||
3377 | rounded_size = size & -PROBE_INTERVAL; | |
3378 | ||
3379 | ||
3380 | /* Step 2: compute initial and final value of the loop counter. */ | |
3381 | ||
3382 | /* TEST_ADDR = SP + FIRST. */ | |
f7df4a84 | 3383 | emit_insn (gen_rtx_SET (r2, |
7b84aac0 EB |
3384 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); |
3385 | ||
3386 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
3387 | if (rounded_size > (1 << 21)) | |
3388 | { | |
3389 | emit_move_insn (r3, GEN_INT (-rounded_size)); | |
f7df4a84 | 3390 | emit_insn (gen_rtx_SET (r3, gen_rtx_PLUS (Pmode, r2, r3))); |
7b84aac0 EB |
3391 | } |
3392 | else | |
f7df4a84 RS |
3393 | emit_insn (gen_rtx_SET (r3, gen_rtx_PLUS (Pmode, r2, |
3394 | GEN_INT (-rounded_size)))); | |
7b84aac0 EB |
3395 | |
3396 | ||
3397 | /* Step 3: the loop | |
3398 | ||
73866e0d | 3399 | do |
7b84aac0 EB |
3400 | { |
3401 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
3402 | probe at TEST_ADDR | |
3403 | } | |
73866e0d | 3404 | while (TEST_ADDR != LAST_ADDR) |
7b84aac0 EB |
3405 | |
3406 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
3407 | until it is equal to ROUNDED_SIZE. */ | |
3408 | ||
3409 | emit_insn (gen_probe_stack_range (r2, r2, r3)); | |
3410 | ||
3411 | ||
3412 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
3413 | that SIZE is equal to ROUNDED_SIZE. */ | |
3414 | ||
3415 | /* TEMP = SIZE - ROUNDED_SIZE. */ | |
3416 | if (size != rounded_size) | |
3417 | { | |
f7df4a84 RS |
3418 | emit_insn (gen_rtx_SET (r2, plus_constant (Pmode, r2, |
3419 | rounded_size - size))); | |
7b84aac0 EB |
3420 | emit_stack_probe (r2); |
3421 | } | |
3422 | } | |
3423 | ||
3424 | /* Make sure nothing is scheduled before we are done. */ | |
3425 | emit_insn (gen_blockage ()); | |
3426 | } | |
3427 | ||
3428 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
3429 | absolute addresses. */ | |
3430 | ||
3431 | const char * | |
3432 | output_probe_stack_range (rtx reg1, rtx reg2) | |
3433 | { | |
3434 | static int labelno = 0; | |
73866e0d | 3435 | char loop_lab[32]; |
7b84aac0 EB |
3436 | rtx xops[3]; |
3437 | ||
73866e0d | 3438 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++); |
7b84aac0 | 3439 | |
73866e0d | 3440 | /* Loop. */ |
7b84aac0 EB |
3441 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); |
3442 | ||
7b84aac0 | 3443 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ |
73866e0d | 3444 | xops[0] = reg1; |
7b84aac0 EB |
3445 | xops[1] = GEN_INT (-PROBE_INTERVAL); |
3446 | output_asm_insn ("addl %0 = %1, %0", xops); | |
3447 | fputs ("\t;;\n", asm_out_file); | |
3448 | ||
73866e0d | 3449 | /* Probe at TEST_ADDR. */ |
7b84aac0 | 3450 | output_asm_insn ("probe.w.fault %0, 0", xops); |
73866e0d EB |
3451 | |
3452 | /* Test if TEST_ADDR == LAST_ADDR. */ | |
3453 | xops[1] = reg2; | |
3454 | xops[2] = gen_rtx_REG (BImode, PR_REG (6)); | |
3455 | output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops); | |
3456 | ||
3457 | /* Branch. */ | |
3458 | fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [PR_REG (7)]); | |
7b84aac0 EB |
3459 | assemble_name_raw (asm_out_file, loop_lab); |
3460 | fputc ('\n', asm_out_file); | |
3461 | ||
7b84aac0 EB |
3462 | return ""; |
3463 | } | |
3464 | ||
c65ebc55 JW |
3465 | /* Called after register allocation to add any instructions needed for the |
3466 | prologue. Using a prologue insn is favored compared to putting all of the | |
08c148a8 | 3467 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3468 | to intermix instructions with the saves of the caller saved registers. In |
3469 | some cases, it might be necessary to emit a barrier instruction as the last | |
3470 | insn to prevent such scheduling. | |
3471 | ||
3472 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
97e242b0 RH |
3473 | so that the debug info generation code can handle them properly. |
3474 | ||
073a8998 | 3475 | The register save area is laid out like so: |
97e242b0 RH |
3476 | cfa+16 |
3477 | [ varargs spill area ] | |
3478 | [ fr register spill area ] | |
3479 | [ br register spill area ] | |
3480 | [ ar register spill area ] | |
3481 | [ pr register spill area ] | |
3482 | [ gr register spill area ] */ | |
c65ebc55 JW |
3483 | |
3484 | /* ??? Get inefficient code when the frame size is larger than can fit in an | |
3485 | adds instruction. */ | |
3486 | ||
c65ebc55 | 3487 | void |
9c808aad | 3488 | ia64_expand_prologue (void) |
c65ebc55 | 3489 | { |
dd3d2b35 DM |
3490 | rtx_insn *insn; |
3491 | rtx ar_pfs_save_reg, ar_unat_save_reg; | |
97e242b0 RH |
3492 | int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs; |
3493 | rtx reg, alt_reg; | |
3494 | ||
3495 | ia64_compute_frame_size (get_frame_size ()); | |
3496 | last_scratch_gr_reg = 15; | |
3497 | ||
a11e0df4 | 3498 | if (flag_stack_usage_info) |
d3c12306 EB |
3499 | current_function_static_stack_size = current_frame_info.total_size; |
3500 | ||
9c1b56c4 JL |
3501 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK |
3502 | || flag_stack_clash_protection) | |
0dca9cd8 EB |
3503 | { |
3504 | HOST_WIDE_INT size = current_frame_info.total_size; | |
3505 | int bs_size = BACKING_STORE_SIZE (current_frame_info.n_input_regs | |
3506 | + current_frame_info.n_local_regs); | |
3507 | ||
3508 | if (crtl->is_leaf && !cfun->calls_alloca) | |
3509 | { | |
8c1dd970 JL |
3510 | if (size > PROBE_INTERVAL && size > get_stack_check_protect ()) |
3511 | ia64_emit_probe_stack_range (get_stack_check_protect (), | |
3512 | size - get_stack_check_protect (), | |
0dca9cd8 | 3513 | bs_size); |
8c1dd970 JL |
3514 | else if (size + bs_size > get_stack_check_protect ()) |
3515 | ia64_emit_probe_stack_range (get_stack_check_protect (), | |
3516 | 0, bs_size); | |
0dca9cd8 EB |
3517 | } |
3518 | else if (size + bs_size > 0) | |
8c1dd970 | 3519 | ia64_emit_probe_stack_range (get_stack_check_protect (), size, bs_size); |
0dca9cd8 | 3520 | } |
7b84aac0 | 3521 | |
6fb5fa3c DB |
3522 | if (dump_file) |
3523 | { | |
3524 | fprintf (dump_file, "ia64 frame related registers " | |
3525 | "recorded in current_frame_info.r[]:\n"); | |
3526 | #define PRINTREG(a) if (current_frame_info.r[a]) \ | |
3527 | fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a]) | |
3528 | PRINTREG(reg_fp); | |
3529 | PRINTREG(reg_save_b0); | |
3530 | PRINTREG(reg_save_pr); | |
3531 | PRINTREG(reg_save_ar_pfs); | |
3532 | PRINTREG(reg_save_ar_unat); | |
3533 | PRINTREG(reg_save_ar_lc); | |
3534 | PRINTREG(reg_save_gp); | |
3535 | #undef PRINTREG | |
3536 | } | |
3537 | ||
97e242b0 RH |
3538 | /* If there is no epilogue, then we don't need some prologue insns. |
3539 | We need to avoid emitting the dead prologue insns, because flow | |
3540 | will complain about them. */ | |
c65ebc55 JW |
3541 | if (optimize) |
3542 | { | |
97e242b0 | 3543 | edge e; |
9924d7d8 | 3544 | edge_iterator ei; |
97e242b0 | 3545 | |
fefa31b5 | 3546 | FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) |
c65ebc55 JW |
3547 | if ((e->flags & EDGE_FAKE) == 0 |
3548 | && (e->flags & EDGE_FALLTHRU) != 0) | |
3549 | break; | |
3550 | epilogue_p = (e != NULL); | |
3551 | } | |
3552 | else | |
3553 | epilogue_p = 1; | |
3554 | ||
97e242b0 RH |
3555 | /* Set the local, input, and output register names. We need to do this |
3556 | for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in | |
3557 | half. If we use in/loc/out register names, then we get assembler errors | |
3558 | in crtn.S because there is no alloc insn or regstk directive in there. */ | |
3559 | if (! TARGET_REG_NAMES) | |
3560 | { | |
3561 | int inputs = current_frame_info.n_input_regs; | |
3562 | int locals = current_frame_info.n_local_regs; | |
3563 | int outputs = current_frame_info.n_output_regs; | |
3564 | ||
3565 | for (i = 0; i < inputs; i++) | |
3566 | reg_names[IN_REG (i)] = ia64_reg_numbers[i]; | |
3567 | for (i = 0; i < locals; i++) | |
3568 | reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i]; | |
3569 | for (i = 0; i < outputs; i++) | |
3570 | reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i]; | |
3571 | } | |
c65ebc55 | 3572 | |
97e242b0 RH |
3573 | /* Set the frame pointer register name. The regnum is logically loc79, |
3574 | but of course we'll not have allocated that many locals. Rather than | |
3575 | worrying about renumbering the existing rtxs, we adjust the name. */ | |
9502c558 JW |
3576 | /* ??? This code means that we can never use one local register when |
3577 | there is a frame pointer. loc79 gets wasted in this case, as it is | |
3578 | renamed to a register that will never be used. See also the try_locals | |
3579 | code in find_gr_spill. */ | |
6fb5fa3c | 3580 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
3581 | { |
3582 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
3583 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
3584 | = reg_names[current_frame_info.r[reg_fp]]; |
3585 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
97e242b0 | 3586 | } |
c65ebc55 | 3587 | |
97e242b0 RH |
3588 | /* We don't need an alloc instruction if we've used no outputs or locals. */ |
3589 | if (current_frame_info.n_local_regs == 0 | |
2ed4af6f | 3590 | && current_frame_info.n_output_regs == 0 |
38173d38 | 3591 | && current_frame_info.n_input_regs <= crtl->args.info.int_regs |
f5bdba44 | 3592 | && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
97e242b0 RH |
3593 | { |
3594 | /* If there is no alloc, but there are input registers used, then we | |
3595 | need a .regstk directive. */ | |
3596 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
3597 | ar_pfs_save_reg = NULL_RTX; | |
3598 | } | |
3599 | else | |
3600 | { | |
3601 | current_frame_info.need_regstk = 0; | |
c65ebc55 | 3602 | |
6fb5fa3c DB |
3603 | if (current_frame_info.r[reg_save_ar_pfs]) |
3604 | { | |
3605 | regno = current_frame_info.r[reg_save_ar_pfs]; | |
3606 | reg_emitted (reg_save_ar_pfs); | |
3607 | } | |
97e242b0 RH |
3608 | else |
3609 | regno = next_scratch_gr_reg (); | |
3610 | ar_pfs_save_reg = gen_rtx_REG (DImode, regno); | |
3611 | ||
9c808aad | 3612 | insn = emit_insn (gen_alloc (ar_pfs_save_reg, |
97e242b0 RH |
3613 | GEN_INT (current_frame_info.n_input_regs), |
3614 | GEN_INT (current_frame_info.n_local_regs), | |
3615 | GEN_INT (current_frame_info.n_output_regs), | |
3616 | GEN_INT (current_frame_info.n_rotate_regs))); | |
9f2ff8e5 RH |
3617 | if (current_frame_info.r[reg_save_ar_pfs]) |
3618 | { | |
3619 | RTX_FRAME_RELATED_P (insn) = 1; | |
3620 | add_reg_note (insn, REG_CFA_REGISTER, | |
f7df4a84 | 3621 | gen_rtx_SET (ar_pfs_save_reg, |
9f2ff8e5 RH |
3622 | gen_rtx_REG (DImode, AR_PFS_REGNUM))); |
3623 | } | |
97e242b0 | 3624 | } |
c65ebc55 | 3625 | |
97e242b0 | 3626 | /* Set up frame pointer, stack pointer, and spill iterators. */ |
c65ebc55 | 3627 | |
26a110f5 | 3628 | n_varargs = cfun->machine->n_varargs; |
97e242b0 RH |
3629 | setup_spill_pointers (current_frame_info.n_spilled + n_varargs, |
3630 | stack_pointer_rtx, 0); | |
c65ebc55 | 3631 | |
97e242b0 RH |
3632 | if (frame_pointer_needed) |
3633 | { | |
3634 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
3635 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3636 | |
3637 | /* Force the unwind info to recognize this as defining a new CFA, | |
3638 | rather than some temp register setup. */ | |
3639 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX); | |
97e242b0 | 3640 | } |
c65ebc55 | 3641 | |
97e242b0 RH |
3642 | if (current_frame_info.total_size != 0) |
3643 | { | |
3644 | rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size); | |
3645 | rtx offset; | |
c65ebc55 | 3646 | |
13f70342 | 3647 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
3648 | offset = frame_size_rtx; |
3649 | else | |
3650 | { | |
3651 | regno = next_scratch_gr_reg (); | |
9c808aad | 3652 | offset = gen_rtx_REG (DImode, regno); |
97e242b0 RH |
3653 | emit_move_insn (offset, frame_size_rtx); |
3654 | } | |
c65ebc55 | 3655 | |
97e242b0 RH |
3656 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, |
3657 | stack_pointer_rtx, offset)); | |
c65ebc55 | 3658 | |
97e242b0 RH |
3659 | if (! frame_pointer_needed) |
3660 | { | |
3661 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 3662 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
f7df4a84 | 3663 | gen_rtx_SET (stack_pointer_rtx, |
5c255b57 RH |
3664 | gen_rtx_PLUS (DImode, |
3665 | stack_pointer_rtx, | |
3666 | frame_size_rtx))); | |
97e242b0 | 3667 | } |
c65ebc55 | 3668 | |
97e242b0 RH |
3669 | /* ??? At this point we must generate a magic insn that appears to |
3670 | modify the stack pointer, the frame pointer, and all spill | |
3671 | iterators. This would allow the most scheduling freedom. For | |
3672 | now, just hard stop. */ | |
3673 | emit_insn (gen_blockage ()); | |
3674 | } | |
c65ebc55 | 3675 | |
97e242b0 RH |
3676 | /* Must copy out ar.unat before doing any integer spills. */ |
3677 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
c65ebc55 | 3678 | { |
6fb5fa3c DB |
3679 | if (current_frame_info.r[reg_save_ar_unat]) |
3680 | { | |
3681 | ar_unat_save_reg | |
3682 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3683 | reg_emitted (reg_save_ar_unat); | |
3684 | } | |
97e242b0 | 3685 | else |
c65ebc55 | 3686 | { |
97e242b0 RH |
3687 | alt_regno = next_scratch_gr_reg (); |
3688 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3689 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
c65ebc55 | 3690 | } |
c65ebc55 | 3691 | |
97e242b0 RH |
3692 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
3693 | insn = emit_move_insn (ar_unat_save_reg, reg); | |
5c255b57 RH |
3694 | if (current_frame_info.r[reg_save_ar_unat]) |
3695 | { | |
3696 | RTX_FRAME_RELATED_P (insn) = 1; | |
3697 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); | |
3698 | } | |
97e242b0 RH |
3699 | |
3700 | /* Even if we're not going to generate an epilogue, we still | |
3701 | need to save the register so that EH works. */ | |
6fb5fa3c | 3702 | if (! epilogue_p && current_frame_info.r[reg_save_ar_unat]) |
d0e82870 | 3703 | emit_insn (gen_prologue_use (ar_unat_save_reg)); |
c65ebc55 JW |
3704 | } |
3705 | else | |
97e242b0 RH |
3706 | ar_unat_save_reg = NULL_RTX; |
3707 | ||
3708 | /* Spill all varargs registers. Do this before spilling any GR registers, | |
3709 | since we want the UNAT bits for the GR registers to override the UNAT | |
3710 | bits from varargs, which we don't care about. */ | |
c65ebc55 | 3711 | |
97e242b0 RH |
3712 | cfa_off = -16; |
3713 | for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno) | |
c65ebc55 | 3714 | { |
97e242b0 | 3715 | reg = gen_rtx_REG (DImode, regno); |
870f9ec0 | 3716 | do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX); |
c65ebc55 | 3717 | } |
c65ebc55 | 3718 | |
97e242b0 RH |
3719 | /* Locate the bottom of the register save area. */ |
3720 | cfa_off = (current_frame_info.spill_cfa_off | |
3721 | + current_frame_info.spill_size | |
3722 | + current_frame_info.extra_spill_size); | |
c65ebc55 | 3723 | |
97e242b0 RH |
3724 | /* Save the predicate register block either in a register or in memory. */ |
3725 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3726 | { | |
3727 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
6fb5fa3c | 3728 | if (current_frame_info.r[reg_save_pr] != 0) |
1ff5b671 | 3729 | { |
6fb5fa3c DB |
3730 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); |
3731 | reg_emitted (reg_save_pr); | |
97e242b0 | 3732 | insn = emit_move_insn (alt_reg, reg); |
1ff5b671 | 3733 | |
97e242b0 RH |
3734 | /* ??? Denote pr spill/fill by a DImode move that modifies all |
3735 | 64 hard registers. */ | |
1ff5b671 | 3736 | RTX_FRAME_RELATED_P (insn) = 1; |
5c255b57 | 3737 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
46327bc5 | 3738 | |
97e242b0 RH |
3739 | /* Even if we're not going to generate an epilogue, we still |
3740 | need to save the register so that EH works. */ | |
3741 | if (! epilogue_p) | |
d0e82870 | 3742 | emit_insn (gen_prologue_use (alt_reg)); |
1ff5b671 JW |
3743 | } |
3744 | else | |
97e242b0 RH |
3745 | { |
3746 | alt_regno = next_scratch_gr_reg (); | |
3747 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3748 | insn = emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3749 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3750 | cfa_off -= 8; |
3751 | } | |
c65ebc55 JW |
3752 | } |
3753 | ||
97e242b0 RH |
3754 | /* Handle AR regs in numerical order. All of them get special handling. */ |
3755 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM) | |
6fb5fa3c | 3756 | && current_frame_info.r[reg_save_ar_unat] == 0) |
c65ebc55 | 3757 | { |
97e242b0 | 3758 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
870f9ec0 | 3759 | do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg); |
97e242b0 | 3760 | cfa_off -= 8; |
c65ebc55 | 3761 | } |
97e242b0 RH |
3762 | |
3763 | /* The alloc insn already copied ar.pfs into a general register. The | |
3764 | only thing we have to do now is copy that register to a stack slot | |
3765 | if we'd not allocated a local register for the job. */ | |
f5bdba44 | 3766 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM) |
6fb5fa3c | 3767 | && current_frame_info.r[reg_save_ar_pfs] == 0) |
c65ebc55 | 3768 | { |
97e242b0 | 3769 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
870f9ec0 | 3770 | do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg); |
97e242b0 RH |
3771 | cfa_off -= 8; |
3772 | } | |
3773 | ||
3774 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3775 | { | |
3776 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
6fb5fa3c | 3777 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
97e242b0 | 3778 | { |
6fb5fa3c DB |
3779 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); |
3780 | reg_emitted (reg_save_ar_lc); | |
97e242b0 RH |
3781 | insn = emit_move_insn (alt_reg, reg); |
3782 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 3783 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
97e242b0 RH |
3784 | |
3785 | /* Even if we're not going to generate an epilogue, we still | |
3786 | need to save the register so that EH works. */ | |
3787 | if (! epilogue_p) | |
d0e82870 | 3788 | emit_insn (gen_prologue_use (alt_reg)); |
97e242b0 | 3789 | } |
c65ebc55 JW |
3790 | else |
3791 | { | |
97e242b0 RH |
3792 | alt_regno = next_scratch_gr_reg (); |
3793 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3794 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3795 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3796 | cfa_off -= 8; |
3797 | } | |
3798 | } | |
3799 | ||
ae1e2d4c AS |
3800 | /* Save the return pointer. */ |
3801 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
3802 | { | |
3803 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
6fb5fa3c | 3804 | if (current_frame_info.r[reg_save_b0] != 0) |
ae1e2d4c | 3805 | { |
6fb5fa3c DB |
3806 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); |
3807 | reg_emitted (reg_save_b0); | |
ae1e2d4c AS |
3808 | insn = emit_move_insn (alt_reg, reg); |
3809 | RTX_FRAME_RELATED_P (insn) = 1; | |
f7df4a84 | 3810 | add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (alt_reg, pc_rtx)); |
ae1e2d4c AS |
3811 | |
3812 | /* Even if we're not going to generate an epilogue, we still | |
3813 | need to save the register so that EH works. */ | |
3814 | if (! epilogue_p) | |
3815 | emit_insn (gen_prologue_use (alt_reg)); | |
3816 | } | |
3817 | else | |
3818 | { | |
3819 | alt_regno = next_scratch_gr_reg (); | |
3820 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3821 | emit_move_insn (alt_reg, reg); | |
3822 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); | |
3823 | cfa_off -= 8; | |
3824 | } | |
3825 | } | |
3826 | ||
6fb5fa3c | 3827 | if (current_frame_info.r[reg_save_gp]) |
599aedd9 | 3828 | { |
6fb5fa3c | 3829 | reg_emitted (reg_save_gp); |
599aedd9 | 3830 | insn = emit_move_insn (gen_rtx_REG (DImode, |
6fb5fa3c | 3831 | current_frame_info.r[reg_save_gp]), |
599aedd9 | 3832 | pic_offset_table_rtx); |
599aedd9 RH |
3833 | } |
3834 | ||
97e242b0 | 3835 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
3836 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
3837 | + current_frame_info.spill_size)); | |
97e242b0 RH |
3838 | |
3839 | /* Spill all general registers. */ | |
3840 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
3841 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3842 | { | |
3843 | reg = gen_rtx_REG (DImode, regno); | |
3844 | do_spill (gen_gr_spill, reg, cfa_off, reg); | |
3845 | cfa_off -= 8; | |
3846 | } | |
3847 | ||
97e242b0 RH |
3848 | /* Spill the rest of the BR registers. */ |
3849 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) | |
3850 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3851 | { | |
3852 | alt_regno = next_scratch_gr_reg (); | |
3853 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3854 | reg = gen_rtx_REG (DImode, regno); | |
3855 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3856 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3857 | cfa_off -= 8; |
3858 | } | |
3859 | ||
3860 | /* Align the frame and spill all FR registers. */ | |
3861 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
3862 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3863 | { | |
e820471b | 3864 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 3865 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 3866 | do_spill (gen_fr_spill_x, reg, cfa_off, reg); |
97e242b0 RH |
3867 | cfa_off -= 16; |
3868 | } | |
3869 | ||
e820471b | 3870 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
3871 | |
3872 | finish_spill_pointers (); | |
c65ebc55 JW |
3873 | } |
3874 | ||
8e7745dc DR |
3875 | /* Output the textual info surrounding the prologue. */ |
3876 | ||
3877 | void | |
3878 | ia64_start_function (FILE *file, const char *fnname, | |
3879 | tree decl ATTRIBUTE_UNUSED) | |
3880 | { | |
4b12e93d TG |
3881 | #if TARGET_ABI_OPEN_VMS |
3882 | vms_start_function (fnname); | |
8e7745dc DR |
3883 | #endif |
3884 | ||
3885 | fputs ("\t.proc ", file); | |
3886 | assemble_name (file, fnname); | |
3887 | fputc ('\n', file); | |
3888 | ASM_OUTPUT_LABEL (file, fnname); | |
3889 | } | |
3890 | ||
c65ebc55 | 3891 | /* Called after register allocation to add any instructions needed for the |
5519a4f9 | 3892 | epilogue. Using an epilogue insn is favored compared to putting all of the |
08c148a8 | 3893 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3894 | to intermix instructions with the saves of the caller saved registers. In |
3895 | some cases, it might be necessary to emit a barrier instruction as the last | |
3896 | insn to prevent such scheduling. */ | |
3897 | ||
3898 | void | |
9c808aad | 3899 | ia64_expand_epilogue (int sibcall_p) |
c65ebc55 | 3900 | { |
dd3d2b35 DM |
3901 | rtx_insn *insn; |
3902 | rtx reg, alt_reg, ar_unat_save_reg; | |
97e242b0 RH |
3903 | int regno, alt_regno, cfa_off; |
3904 | ||
3905 | ia64_compute_frame_size (get_frame_size ()); | |
3906 | ||
3907 | /* If there is a frame pointer, then we use it instead of the stack | |
3908 | pointer, so that the stack pointer does not need to be valid when | |
3909 | the epilogue starts. See EXIT_IGNORE_STACK. */ | |
3910 | if (frame_pointer_needed) | |
3911 | setup_spill_pointers (current_frame_info.n_spilled, | |
3912 | hard_frame_pointer_rtx, 0); | |
3913 | else | |
9c808aad | 3914 | setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx, |
97e242b0 RH |
3915 | current_frame_info.total_size); |
3916 | ||
3917 | if (current_frame_info.total_size != 0) | |
3918 | { | |
3919 | /* ??? At this point we must generate a magic insn that appears to | |
3920 | modify the spill iterators and the frame pointer. This would | |
3921 | allow the most scheduling freedom. For now, just hard stop. */ | |
3922 | emit_insn (gen_blockage ()); | |
3923 | } | |
3924 | ||
3925 | /* Locate the bottom of the register save area. */ | |
3926 | cfa_off = (current_frame_info.spill_cfa_off | |
3927 | + current_frame_info.spill_size | |
3928 | + current_frame_info.extra_spill_size); | |
3929 | ||
3930 | /* Restore the predicate registers. */ | |
3931 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3932 | { | |
6fb5fa3c DB |
3933 | if (current_frame_info.r[reg_save_pr] != 0) |
3934 | { | |
3935 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); | |
3936 | reg_emitted (reg_save_pr); | |
3937 | } | |
97e242b0 RH |
3938 | else |
3939 | { | |
3940 | alt_regno = next_scratch_gr_reg (); | |
3941 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3942 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3943 | cfa_off -= 8; |
3944 | } | |
3945 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
3946 | emit_move_insn (reg, alt_reg); | |
3947 | } | |
3948 | ||
3949 | /* Restore the application registers. */ | |
3950 | ||
3951 | /* Load the saved unat from the stack, but do not restore it until | |
3952 | after the GRs have been restored. */ | |
3953 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
3954 | { | |
6fb5fa3c DB |
3955 | if (current_frame_info.r[reg_save_ar_unat] != 0) |
3956 | { | |
3957 | ar_unat_save_reg | |
3958 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3959 | reg_emitted (reg_save_ar_unat); | |
3960 | } | |
97e242b0 RH |
3961 | else |
3962 | { | |
3963 | alt_regno = next_scratch_gr_reg (); | |
3964 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3965 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
870f9ec0 | 3966 | do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off); |
97e242b0 RH |
3967 | cfa_off -= 8; |
3968 | } | |
3969 | } | |
3970 | else | |
3971 | ar_unat_save_reg = NULL_RTX; | |
9c808aad | 3972 | |
6fb5fa3c | 3973 | if (current_frame_info.r[reg_save_ar_pfs] != 0) |
97e242b0 | 3974 | { |
6fb5fa3c DB |
3975 | reg_emitted (reg_save_ar_pfs); |
3976 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]); | |
97e242b0 RH |
3977 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
3978 | emit_move_insn (reg, alt_reg); | |
3979 | } | |
4e14f1f9 | 3980 | else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
c65ebc55 | 3981 | { |
97e242b0 RH |
3982 | alt_regno = next_scratch_gr_reg (); |
3983 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3984 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3985 | cfa_off -= 8; |
3986 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); | |
3987 | emit_move_insn (reg, alt_reg); | |
3988 | } | |
3989 | ||
3990 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3991 | { | |
6fb5fa3c DB |
3992 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
3993 | { | |
3994 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); | |
3995 | reg_emitted (reg_save_ar_lc); | |
3996 | } | |
97e242b0 RH |
3997 | else |
3998 | { | |
3999 | alt_regno = next_scratch_gr_reg (); | |
4000 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 4001 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
4002 | cfa_off -= 8; |
4003 | } | |
4004 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
4005 | emit_move_insn (reg, alt_reg); | |
4006 | } | |
4007 | ||
ae1e2d4c AS |
4008 | /* Restore the return pointer. */ |
4009 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
4010 | { | |
6fb5fa3c DB |
4011 | if (current_frame_info.r[reg_save_b0] != 0) |
4012 | { | |
4013 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
4014 | reg_emitted (reg_save_b0); | |
4015 | } | |
ae1e2d4c AS |
4016 | else |
4017 | { | |
4018 | alt_regno = next_scratch_gr_reg (); | |
4019 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
4020 | do_restore (gen_movdi_x, alt_reg, cfa_off); | |
4021 | cfa_off -= 8; | |
4022 | } | |
4023 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
4024 | emit_move_insn (reg, alt_reg); | |
4025 | } | |
4026 | ||
97e242b0 | 4027 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
4028 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
4029 | + current_frame_info.spill_size)); | |
97e242b0 | 4030 | |
599aedd9 RH |
4031 | /* The GP may be stored on the stack in the prologue, but it's |
4032 | never restored in the epilogue. Skip the stack slot. */ | |
4033 | if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1))) | |
4034 | cfa_off -= 8; | |
4035 | ||
97e242b0 | 4036 | /* Restore all general registers. */ |
599aedd9 | 4037 | for (regno = GR_REG (2); regno <= GR_REG (31); ++regno) |
97e242b0 | 4038 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) |
0c96007e | 4039 | { |
97e242b0 RH |
4040 | reg = gen_rtx_REG (DImode, regno); |
4041 | do_restore (gen_gr_restore, reg, cfa_off); | |
4042 | cfa_off -= 8; | |
0c96007e | 4043 | } |
9c808aad | 4044 | |
ae1e2d4c | 4045 | /* Restore the branch registers. */ |
97e242b0 RH |
4046 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) |
4047 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
0c96007e | 4048 | { |
97e242b0 RH |
4049 | alt_regno = next_scratch_gr_reg (); |
4050 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 4051 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
4052 | cfa_off -= 8; |
4053 | reg = gen_rtx_REG (DImode, regno); | |
4054 | emit_move_insn (reg, alt_reg); | |
4055 | } | |
c65ebc55 | 4056 | |
97e242b0 RH |
4057 | /* Restore floating point registers. */ |
4058 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
4059 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4060 | { | |
e820471b | 4061 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 4062 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 4063 | do_restore (gen_fr_restore_x, reg, cfa_off); |
97e242b0 | 4064 | cfa_off -= 16; |
0c96007e | 4065 | } |
97e242b0 RH |
4066 | |
4067 | /* Restore ar.unat for real. */ | |
4068 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
4069 | { | |
4070 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); | |
4071 | emit_move_insn (reg, ar_unat_save_reg); | |
c65ebc55 JW |
4072 | } |
4073 | ||
e820471b | 4074 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
4075 | |
4076 | finish_spill_pointers (); | |
c65ebc55 | 4077 | |
c93646bd JJ |
4078 | if (current_frame_info.total_size |
4079 | || cfun->machine->ia64_eh_epilogue_sp | |
4080 | || frame_pointer_needed) | |
97e242b0 RH |
4081 | { |
4082 | /* ??? At this point we must generate a magic insn that appears to | |
4083 | modify the spill iterators, the stack pointer, and the frame | |
4084 | pointer. This would allow the most scheduling freedom. For now, | |
4085 | just hard stop. */ | |
4086 | emit_insn (gen_blockage ()); | |
4087 | } | |
c65ebc55 | 4088 | |
97e242b0 RH |
4089 | if (cfun->machine->ia64_eh_epilogue_sp) |
4090 | emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp); | |
4091 | else if (frame_pointer_needed) | |
4092 | { | |
4093 | insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
4094 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 4095 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL); |
97e242b0 RH |
4096 | } |
4097 | else if (current_frame_info.total_size) | |
0c96007e | 4098 | { |
97e242b0 RH |
4099 | rtx offset, frame_size_rtx; |
4100 | ||
4101 | frame_size_rtx = GEN_INT (current_frame_info.total_size); | |
13f70342 | 4102 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
4103 | offset = frame_size_rtx; |
4104 | else | |
4105 | { | |
4106 | regno = next_scratch_gr_reg (); | |
4107 | offset = gen_rtx_REG (DImode, regno); | |
4108 | emit_move_insn (offset, frame_size_rtx); | |
4109 | } | |
4110 | ||
4111 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
4112 | offset)); | |
4113 | ||
4114 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 4115 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
f7df4a84 | 4116 | gen_rtx_SET (stack_pointer_rtx, |
5c255b57 RH |
4117 | gen_rtx_PLUS (DImode, |
4118 | stack_pointer_rtx, | |
4119 | frame_size_rtx))); | |
0c96007e | 4120 | } |
97e242b0 RH |
4121 | |
4122 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
4123 | emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp)); | |
9c808aad | 4124 | |
2ed4af6f RH |
4125 | if (! sibcall_p) |
4126 | emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0)))); | |
25250265 | 4127 | else |
8206fc89 AM |
4128 | { |
4129 | int fp = GR_REG (2); | |
5c255b57 RH |
4130 | /* We need a throw away register here, r0 and r1 are reserved, |
4131 | so r2 is the first available call clobbered register. If | |
4132 | there was a frame_pointer register, we may have swapped the | |
4133 | names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make | |
4134 | sure we're using the string "r2" when emitting the register | |
4135 | name for the assembler. */ | |
6fb5fa3c DB |
4136 | if (current_frame_info.r[reg_fp] |
4137 | && current_frame_info.r[reg_fp] == GR_REG (2)) | |
8206fc89 AM |
4138 | fp = HARD_FRAME_POINTER_REGNUM; |
4139 | ||
4140 | /* We must emit an alloc to force the input registers to become output | |
4141 | registers. Otherwise, if the callee tries to pass its parameters | |
4142 | through to another call without an intervening alloc, then these | |
4143 | values get lost. */ | |
4144 | /* ??? We don't need to preserve all input registers. We only need to | |
4145 | preserve those input registers used as arguments to the sibling call. | |
4146 | It is unclear how to compute that number here. */ | |
4147 | if (current_frame_info.n_input_regs != 0) | |
a8f5224e DM |
4148 | { |
4149 | rtx n_inputs = GEN_INT (current_frame_info.n_input_regs); | |
c2b40eba | 4150 | |
a8f5224e DM |
4151 | insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp), |
4152 | const0_rtx, const0_rtx, | |
4153 | n_inputs, const0_rtx)); | |
4154 | RTX_FRAME_RELATED_P (insn) = 1; | |
c2b40eba RH |
4155 | |
4156 | /* ??? We need to mark the alloc as frame-related so that it gets | |
4157 | passed into ia64_asm_unwind_emit for ia64-specific unwinding. | |
4158 | But there's nothing dwarf2 related to be done wrt the register | |
4159 | windows. If we do nothing, dwarf2out will abort on the UNSPEC; | |
4160 | the empty parallel means dwarf2out will not see anything. */ | |
4161 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
4162 | gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0))); | |
a8f5224e | 4163 | } |
8206fc89 | 4164 | } |
c65ebc55 JW |
4165 | } |
4166 | ||
97e242b0 RH |
4167 | /* Return 1 if br.ret can do all the work required to return from a |
4168 | function. */ | |
4169 | ||
4170 | int | |
9c808aad | 4171 | ia64_direct_return (void) |
97e242b0 RH |
4172 | { |
4173 | if (reload_completed && ! frame_pointer_needed) | |
4174 | { | |
4175 | ia64_compute_frame_size (get_frame_size ()); | |
4176 | ||
4177 | return (current_frame_info.total_size == 0 | |
4178 | && current_frame_info.n_spilled == 0 | |
6fb5fa3c DB |
4179 | && current_frame_info.r[reg_save_b0] == 0 |
4180 | && current_frame_info.r[reg_save_pr] == 0 | |
4181 | && current_frame_info.r[reg_save_ar_pfs] == 0 | |
4182 | && current_frame_info.r[reg_save_ar_unat] == 0 | |
4183 | && current_frame_info.r[reg_save_ar_lc] == 0); | |
97e242b0 RH |
4184 | } |
4185 | return 0; | |
4186 | } | |
4187 | ||
af1e5518 RH |
4188 | /* Return the magic cookie that we use to hold the return address |
4189 | during early compilation. */ | |
4190 | ||
4191 | rtx | |
9c808aad | 4192 | ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED) |
af1e5518 RH |
4193 | { |
4194 | if (count != 0) | |
4195 | return NULL; | |
4196 | return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR); | |
4197 | } | |
4198 | ||
4199 | /* Split this value after reload, now that we know where the return | |
4200 | address is saved. */ | |
4201 | ||
4202 | void | |
9c808aad | 4203 | ia64_split_return_addr_rtx (rtx dest) |
af1e5518 RH |
4204 | { |
4205 | rtx src; | |
4206 | ||
4207 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
4208 | { | |
6fb5fa3c DB |
4209 | if (current_frame_info.r[reg_save_b0] != 0) |
4210 | { | |
4211 | src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
4212 | reg_emitted (reg_save_b0); | |
4213 | } | |
af1e5518 RH |
4214 | else |
4215 | { | |
4216 | HOST_WIDE_INT off; | |
4217 | unsigned int regno; | |
13f70342 | 4218 | rtx off_r; |
af1e5518 RH |
4219 | |
4220 | /* Compute offset from CFA for BR0. */ | |
4221 | /* ??? Must be kept in sync with ia64_expand_prologue. */ | |
4222 | off = (current_frame_info.spill_cfa_off | |
4223 | + current_frame_info.spill_size); | |
4224 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
4225 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4226 | off -= 8; | |
4227 | ||
4228 | /* Convert CFA offset to a register based offset. */ | |
4229 | if (frame_pointer_needed) | |
4230 | src = hard_frame_pointer_rtx; | |
4231 | else | |
4232 | { | |
4233 | src = stack_pointer_rtx; | |
4234 | off += current_frame_info.total_size; | |
4235 | } | |
4236 | ||
4237 | /* Load address into scratch register. */ | |
13f70342 RH |
4238 | off_r = GEN_INT (off); |
4239 | if (satisfies_constraint_I (off_r)) | |
4240 | emit_insn (gen_adddi3 (dest, src, off_r)); | |
af1e5518 RH |
4241 | else |
4242 | { | |
13f70342 | 4243 | emit_move_insn (dest, off_r); |
af1e5518 RH |
4244 | emit_insn (gen_adddi3 (dest, src, dest)); |
4245 | } | |
4246 | ||
4247 | src = gen_rtx_MEM (Pmode, dest); | |
4248 | } | |
4249 | } | |
4250 | else | |
4251 | src = gen_rtx_REG (DImode, BR_REG (0)); | |
4252 | ||
4253 | emit_move_insn (dest, src); | |
4254 | } | |
4255 | ||
10c9f189 | 4256 | int |
9c808aad | 4257 | ia64_hard_regno_rename_ok (int from, int to) |
10c9f189 RH |
4258 | { |
4259 | /* Don't clobber any of the registers we reserved for the prologue. */ | |
09639a83 | 4260 | unsigned int r; |
10c9f189 | 4261 | |
6fb5fa3c DB |
4262 | for (r = reg_fp; r <= reg_save_ar_lc; r++) |
4263 | if (to == current_frame_info.r[r] | |
4264 | || from == current_frame_info.r[r] | |
4265 | || to == emitted_frame_related_regs[r] | |
4266 | || from == emitted_frame_related_regs[r]) | |
4267 | return 0; | |
2130b7fb | 4268 | |
10c9f189 RH |
4269 | /* Don't use output registers outside the register frame. */ |
4270 | if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs)) | |
4271 | return 0; | |
4272 | ||
4273 | /* Retain even/oddness on predicate register pairs. */ | |
4274 | if (PR_REGNO_P (from) && PR_REGNO_P (to)) | |
4275 | return (from & 1) == (to & 1); | |
4276 | ||
4277 | return 1; | |
4278 | } | |
4279 | ||
c43f4279 RS |
4280 | /* Implement TARGET_HARD_REGNO_NREGS. |
4281 | ||
4282 | ??? We say that BImode PR values require two registers. This allows us to | |
4283 | easily store the normal and inverted values. We use CCImode to indicate | |
4284 | a single predicate register. */ | |
4285 | ||
4286 | static unsigned int | |
4287 | ia64_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
4288 | { | |
4289 | if (regno == PR_REG (0) && mode == DImode) | |
4290 | return 64; | |
4291 | if (PR_REGNO_P (regno) && (mode) == BImode) | |
4292 | return 2; | |
4293 | if ((PR_REGNO_P (regno) || GR_REGNO_P (regno)) && mode == CCImode) | |
4294 | return 1; | |
4295 | if (FR_REGNO_P (regno) && mode == XFmode) | |
4296 | return 1; | |
4297 | if (FR_REGNO_P (regno) && mode == RFmode) | |
4298 | return 1; | |
4299 | if (FR_REGNO_P (regno) && mode == XCmode) | |
4300 | return 2; | |
4301 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
4302 | } | |
4303 | ||
f939c3e6 RS |
4304 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
4305 | ||
4306 | static bool | |
4307 | ia64_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
4308 | { | |
4309 | if (FR_REGNO_P (regno)) | |
4310 | return (GET_MODE_CLASS (mode) != MODE_CC | |
4311 | && mode != BImode | |
4312 | && mode != TFmode); | |
4313 | ||
4314 | if (PR_REGNO_P (regno)) | |
4315 | return mode == BImode || GET_MODE_CLASS (mode) == MODE_CC; | |
4316 | ||
4317 | if (GR_REGNO_P (regno)) | |
4318 | return mode != XFmode && mode != XCmode && mode != RFmode; | |
4319 | ||
4320 | if (AR_REGNO_P (regno)) | |
4321 | return mode == DImode; | |
4322 | ||
4323 | if (BR_REGNO_P (regno)) | |
4324 | return mode == DImode; | |
4325 | ||
4326 | return false; | |
4327 | } | |
4328 | ||
99e1629f RS |
4329 | /* Implement TARGET_MODES_TIEABLE_P. |
4330 | ||
4331 | Don't tie integer and FP modes, as that causes us to get integer registers | |
4332 | allocated for FP instructions. XFmode only supported in FP registers so | |
4333 | we can't tie it with any other modes. */ | |
4334 | ||
4335 | static bool | |
4336 | ia64_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
4337 | { | |
4338 | return (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2) | |
4339 | && ((mode1 == XFmode || mode1 == XCmode || mode1 == RFmode) | |
4340 | == (mode2 == XFmode || mode2 == XCmode || mode2 == RFmode)) | |
4341 | && (mode1 == BImode) == (mode2 == BImode)); | |
4342 | } | |
4343 | ||
301d03af RS |
4344 | /* Target hook for assembling integer objects. Handle word-sized |
4345 | aligned objects and detect the cases when @fptr is needed. */ | |
4346 | ||
4347 | static bool | |
9c808aad | 4348 | ia64_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 4349 | { |
b6a41a62 | 4350 | if (size == POINTER_SIZE / BITS_PER_UNIT |
301d03af RS |
4351 | && !(TARGET_NO_PIC || TARGET_AUTO_PIC) |
4352 | && GET_CODE (x) == SYMBOL_REF | |
1cdbd630 | 4353 | && SYMBOL_REF_FUNCTION_P (x)) |
301d03af | 4354 | { |
1b79dc38 DM |
4355 | static const char * const directive[2][2] = { |
4356 | /* 64-bit pointer */ /* 32-bit pointer */ | |
4357 | { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */ | |
4358 | { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */ | |
4359 | }; | |
4360 | fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file); | |
301d03af RS |
4361 | output_addr_const (asm_out_file, x); |
4362 | fputs (")\n", asm_out_file); | |
4363 | return true; | |
4364 | } | |
4365 | return default_assemble_integer (x, size, aligned_p); | |
4366 | } | |
4367 | ||
c65ebc55 JW |
4368 | /* Emit the function prologue. */ |
4369 | ||
08c148a8 | 4370 | static void |
42776416 | 4371 | ia64_output_function_prologue (FILE *file) |
c65ebc55 | 4372 | { |
97e242b0 RH |
4373 | int mask, grsave, grsave_prev; |
4374 | ||
4375 | if (current_frame_info.need_regstk) | |
4376 | fprintf (file, "\t.regstk %d, %d, %d, %d\n", | |
4377 | current_frame_info.n_input_regs, | |
4378 | current_frame_info.n_local_regs, | |
4379 | current_frame_info.n_output_regs, | |
4380 | current_frame_info.n_rotate_regs); | |
c65ebc55 | 4381 | |
d5fabb58 | 4382 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0c96007e AM |
4383 | return; |
4384 | ||
97e242b0 | 4385 | /* Emit the .prologue directive. */ |
809d4ef1 | 4386 | |
97e242b0 RH |
4387 | mask = 0; |
4388 | grsave = grsave_prev = 0; | |
6fb5fa3c | 4389 | if (current_frame_info.r[reg_save_b0] != 0) |
0c96007e | 4390 | { |
97e242b0 | 4391 | mask |= 8; |
6fb5fa3c | 4392 | grsave = grsave_prev = current_frame_info.r[reg_save_b0]; |
97e242b0 | 4393 | } |
6fb5fa3c | 4394 | if (current_frame_info.r[reg_save_ar_pfs] != 0 |
97e242b0 | 4395 | && (grsave_prev == 0 |
6fb5fa3c | 4396 | || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1)) |
97e242b0 RH |
4397 | { |
4398 | mask |= 4; | |
4399 | if (grsave_prev == 0) | |
6fb5fa3c DB |
4400 | grsave = current_frame_info.r[reg_save_ar_pfs]; |
4401 | grsave_prev = current_frame_info.r[reg_save_ar_pfs]; | |
0c96007e | 4402 | } |
6fb5fa3c | 4403 | if (current_frame_info.r[reg_fp] != 0 |
97e242b0 | 4404 | && (grsave_prev == 0 |
6fb5fa3c | 4405 | || current_frame_info.r[reg_fp] == grsave_prev + 1)) |
97e242b0 RH |
4406 | { |
4407 | mask |= 2; | |
4408 | if (grsave_prev == 0) | |
4409 | grsave = HARD_FRAME_POINTER_REGNUM; | |
6fb5fa3c | 4410 | grsave_prev = current_frame_info.r[reg_fp]; |
97e242b0 | 4411 | } |
6fb5fa3c | 4412 | if (current_frame_info.r[reg_save_pr] != 0 |
97e242b0 | 4413 | && (grsave_prev == 0 |
6fb5fa3c | 4414 | || current_frame_info.r[reg_save_pr] == grsave_prev + 1)) |
97e242b0 RH |
4415 | { |
4416 | mask |= 1; | |
4417 | if (grsave_prev == 0) | |
6fb5fa3c | 4418 | grsave = current_frame_info.r[reg_save_pr]; |
97e242b0 RH |
4419 | } |
4420 | ||
738e7b39 | 4421 | if (mask && TARGET_GNU_AS) |
97e242b0 RH |
4422 | fprintf (file, "\t.prologue %d, %d\n", mask, |
4423 | ia64_dbx_register_number (grsave)); | |
4424 | else | |
4425 | fputs ("\t.prologue\n", file); | |
4426 | ||
4427 | /* Emit a .spill directive, if necessary, to relocate the base of | |
4428 | the register spill area. */ | |
4429 | if (current_frame_info.spill_cfa_off != -16) | |
4430 | fprintf (file, "\t.spill %ld\n", | |
4431 | (long) (current_frame_info.spill_cfa_off | |
4432 | + current_frame_info.spill_size)); | |
c65ebc55 JW |
4433 | } |
4434 | ||
0186257f JW |
4435 | /* Emit the .body directive at the scheduled end of the prologue. */ |
4436 | ||
b4c25db2 | 4437 | static void |
9c808aad | 4438 | ia64_output_function_end_prologue (FILE *file) |
0186257f | 4439 | { |
d5fabb58 | 4440 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0186257f JW |
4441 | return; |
4442 | ||
4443 | fputs ("\t.body\n", file); | |
4444 | } | |
4445 | ||
c65ebc55 JW |
4446 | /* Emit the function epilogue. */ |
4447 | ||
08c148a8 | 4448 | static void |
42776416 | 4449 | ia64_output_function_epilogue (FILE *) |
c65ebc55 | 4450 | { |
8a959ea5 RH |
4451 | int i; |
4452 | ||
6fb5fa3c | 4453 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4454 | { |
4455 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
4456 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
4457 | = reg_names[current_frame_info.r[reg_fp]]; |
4458 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
4459 | reg_emitted (reg_fp); | |
97e242b0 RH |
4460 | } |
4461 | if (! TARGET_REG_NAMES) | |
4462 | { | |
97e242b0 RH |
4463 | for (i = 0; i < current_frame_info.n_input_regs; i++) |
4464 | reg_names[IN_REG (i)] = ia64_input_reg_names[i]; | |
4465 | for (i = 0; i < current_frame_info.n_local_regs; i++) | |
4466 | reg_names[LOC_REG (i)] = ia64_local_reg_names[i]; | |
4467 | for (i = 0; i < current_frame_info.n_output_regs; i++) | |
4468 | reg_names[OUT_REG (i)] = ia64_output_reg_names[i]; | |
4469 | } | |
8a959ea5 | 4470 | |
97e242b0 RH |
4471 | current_frame_info.initialized = 0; |
4472 | } | |
c65ebc55 JW |
4473 | |
4474 | int | |
9c808aad | 4475 | ia64_dbx_register_number (int regno) |
c65ebc55 | 4476 | { |
97e242b0 RH |
4477 | /* In ia64_expand_prologue we quite literally renamed the frame pointer |
4478 | from its home at loc79 to something inside the register frame. We | |
4479 | must perform the same renumbering here for the debug info. */ | |
6fb5fa3c | 4480 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4481 | { |
4482 | if (regno == HARD_FRAME_POINTER_REGNUM) | |
6fb5fa3c DB |
4483 | regno = current_frame_info.r[reg_fp]; |
4484 | else if (regno == current_frame_info.r[reg_fp]) | |
97e242b0 RH |
4485 | regno = HARD_FRAME_POINTER_REGNUM; |
4486 | } | |
4487 | ||
4488 | if (IN_REGNO_P (regno)) | |
4489 | return 32 + regno - IN_REG (0); | |
4490 | else if (LOC_REGNO_P (regno)) | |
4491 | return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0); | |
4492 | else if (OUT_REGNO_P (regno)) | |
4493 | return (32 + current_frame_info.n_input_regs | |
4494 | + current_frame_info.n_local_regs + regno - OUT_REG (0)); | |
4495 | else | |
4496 | return regno; | |
c65ebc55 JW |
4497 | } |
4498 | ||
2a1211e5 RH |
4499 | /* Implement TARGET_TRAMPOLINE_INIT. |
4500 | ||
4501 | The trampoline should set the static chain pointer to value placed | |
4502 | into the trampoline and should branch to the specified routine. | |
4503 | To make the normal indirect-subroutine calling convention work, | |
4504 | the trampoline must look like a function descriptor; the first | |
4505 | word being the target address and the second being the target's | |
4506 | global pointer. | |
4507 | ||
4508 | We abuse the concept of a global pointer by arranging for it | |
4509 | to point to the data we need to load. The complete trampoline | |
4510 | has the following form: | |
4511 | ||
4512 | +-------------------+ \ | |
4513 | TRAMP: | __ia64_trampoline | | | |
4514 | +-------------------+ > fake function descriptor | |
4515 | | TRAMP+16 | | | |
4516 | +-------------------+ / | |
4517 | | target descriptor | | |
4518 | +-------------------+ | |
4519 | | static link | | |
4520 | +-------------------+ | |
4521 | */ | |
4522 | ||
4523 | static void | |
4524 | ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
97e242b0 | 4525 | { |
2a1211e5 RH |
4526 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
4527 | rtx addr, addr_reg, tramp, eight = GEN_INT (8); | |
97e242b0 | 4528 | |
738e7b39 RK |
4529 | /* The Intel assembler requires that the global __ia64_trampoline symbol |
4530 | be declared explicitly */ | |
4531 | if (!TARGET_GNU_AS) | |
4532 | { | |
4533 | static bool declared_ia64_trampoline = false; | |
4534 | ||
4535 | if (!declared_ia64_trampoline) | |
4536 | { | |
4537 | declared_ia64_trampoline = true; | |
b6a41a62 RK |
4538 | (*targetm.asm_out.globalize_label) (asm_out_file, |
4539 | "__ia64_trampoline"); | |
738e7b39 RK |
4540 | } |
4541 | } | |
4542 | ||
5e89a381 | 4543 | /* Make sure addresses are Pmode even if we are in ILP32 mode. */ |
2a1211e5 | 4544 | addr = convert_memory_address (Pmode, XEXP (m_tramp, 0)); |
5e89a381 SE |
4545 | fnaddr = convert_memory_address (Pmode, fnaddr); |
4546 | static_chain = convert_memory_address (Pmode, static_chain); | |
4547 | ||
97e242b0 | 4548 | /* Load up our iterator. */ |
2a1211e5 RH |
4549 | addr_reg = copy_to_reg (addr); |
4550 | m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0); | |
97e242b0 RH |
4551 | |
4552 | /* The first two words are the fake descriptor: | |
4553 | __ia64_trampoline, ADDR+16. */ | |
f2972bf8 DR |
4554 | tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"); |
4555 | if (TARGET_ABI_OPEN_VMS) | |
4556 | { | |
4557 | /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity | |
4558 | in the Macro-32 compiler) and changed the semantics of the LTOFF22 | |
4559 | relocation against function symbols to make it identical to the | |
4560 | LTOFF_FPTR22 relocation. Emit the latter directly to stay within | |
4561 | strict ELF and dereference to get the bare code address. */ | |
4562 | rtx reg = gen_reg_rtx (Pmode); | |
4563 | SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION; | |
4564 | emit_move_insn (reg, tramp); | |
4565 | emit_move_insn (reg, gen_rtx_MEM (Pmode, reg)); | |
4566 | tramp = reg; | |
4567 | } | |
2a1211e5 | 4568 | emit_move_insn (m_tramp, tramp); |
97e242b0 | 4569 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4570 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 | 4571 | |
0a81f074 | 4572 | emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16))); |
97e242b0 | 4573 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4574 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4575 | |
4576 | /* The third word is the target descriptor. */ | |
2a1211e5 | 4577 | emit_move_insn (m_tramp, force_reg (Pmode, fnaddr)); |
97e242b0 | 4578 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4579 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4580 | |
4581 | /* The fourth word is the static chain. */ | |
2a1211e5 | 4582 | emit_move_insn (m_tramp, static_chain); |
97e242b0 | 4583 | } |
c65ebc55 JW |
4584 | \f |
4585 | /* Do any needed setup for a variadic function. CUM has not been updated | |
e7056ca4 | 4586 | for the last named argument, which is given by ARG. |
97e242b0 RH |
4587 | |
4588 | We generate the actual spill instructions during prologue generation. */ | |
4589 | ||
351a758b | 4590 | static void |
e7056ca4 RS |
4591 | ia64_setup_incoming_varargs (cumulative_args_t cum, |
4592 | const function_arg_info &arg, | |
4593 | int *pretend_size, | |
9c808aad | 4594 | int second_time ATTRIBUTE_UNUSED) |
c65ebc55 | 4595 | { |
d5cc9181 | 4596 | CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum); |
351a758b | 4597 | |
6c535c69 | 4598 | /* Skip the current argument. */ |
6930c98c | 4599 | ia64_function_arg_advance (pack_cumulative_args (&next_cum), arg); |
c65ebc55 | 4600 | |
351a758b | 4601 | if (next_cum.words < MAX_ARGUMENT_SLOTS) |
26a110f5 | 4602 | { |
351a758b | 4603 | int n = MAX_ARGUMENT_SLOTS - next_cum.words; |
26a110f5 RH |
4604 | *pretend_size = n * UNITS_PER_WORD; |
4605 | cfun->machine->n_varargs = n; | |
4606 | } | |
c65ebc55 JW |
4607 | } |
4608 | ||
4609 | /* Check whether TYPE is a homogeneous floating point aggregate. If | |
4610 | it is, return the mode of the floating point type that appears | |
4611 | in all leafs. If it is not, return VOIDmode. | |
4612 | ||
4613 | An aggregate is a homogeneous floating point aggregate is if all | |
4614 | fields/elements in it have the same floating point type (e.g, | |
3d6a9acd RH |
4615 | SFmode). 128-bit quad-precision floats are excluded. |
4616 | ||
4617 | Variable sized aggregates should never arrive here, since we should | |
4618 | have already decided to pass them by reference. Top-level zero-sized | |
4619 | aggregates are excluded because our parallels crash the middle-end. */ | |
c65ebc55 | 4620 | |
ef4bddc2 | 4621 | static machine_mode |
586de218 | 4622 | hfa_element_mode (const_tree type, bool nested) |
c65ebc55 | 4623 | { |
ef4bddc2 RS |
4624 | machine_mode element_mode = VOIDmode; |
4625 | machine_mode mode; | |
c65ebc55 JW |
4626 | enum tree_code code = TREE_CODE (type); |
4627 | int know_element_mode = 0; | |
4628 | tree t; | |
4629 | ||
3d6a9acd RH |
4630 | if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type)))) |
4631 | return VOIDmode; | |
4632 | ||
c65ebc55 JW |
4633 | switch (code) |
4634 | { | |
4635 | case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE: | |
0cc8f5c5 | 4636 | case BOOLEAN_TYPE: case POINTER_TYPE: |
c65ebc55 | 4637 | case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE: |
5662a50d | 4638 | case LANG_TYPE: case FUNCTION_TYPE: |
c65ebc55 JW |
4639 | return VOIDmode; |
4640 | ||
4641 | /* Fortran complex types are supposed to be HFAs, so we need to handle | |
4642 | gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex | |
4643 | types though. */ | |
4644 | case COMPLEX_TYPE: | |
16448fd4 | 4645 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT |
02befdf4 ZW |
4646 | && TYPE_MODE (type) != TCmode) |
4647 | return GET_MODE_INNER (TYPE_MODE (type)); | |
c65ebc55 JW |
4648 | else |
4649 | return VOIDmode; | |
4650 | ||
4651 | case REAL_TYPE: | |
4652 | /* We want to return VOIDmode for raw REAL_TYPEs, but the actual | |
4653 | mode if this is contained within an aggregate. */ | |
02befdf4 | 4654 | if (nested && TYPE_MODE (type) != TFmode) |
c65ebc55 JW |
4655 | return TYPE_MODE (type); |
4656 | else | |
4657 | return VOIDmode; | |
4658 | ||
4659 | case ARRAY_TYPE: | |
46399021 | 4660 | return hfa_element_mode (TREE_TYPE (type), 1); |
c65ebc55 JW |
4661 | |
4662 | case RECORD_TYPE: | |
4663 | case UNION_TYPE: | |
4664 | case QUAL_UNION_TYPE: | |
910ad8de | 4665 | for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t)) |
c65ebc55 JW |
4666 | { |
4667 | if (TREE_CODE (t) != FIELD_DECL) | |
4668 | continue; | |
4669 | ||
4670 | mode = hfa_element_mode (TREE_TYPE (t), 1); | |
4671 | if (know_element_mode) | |
4672 | { | |
4673 | if (mode != element_mode) | |
4674 | return VOIDmode; | |
4675 | } | |
4676 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT) | |
4677 | return VOIDmode; | |
4678 | else | |
4679 | { | |
4680 | know_element_mode = 1; | |
4681 | element_mode = mode; | |
4682 | } | |
4683 | } | |
4684 | return element_mode; | |
4685 | ||
4686 | default: | |
4687 | /* If we reach here, we probably have some front-end specific type | |
4688 | that the backend doesn't know about. This can happen via the | |
4689 | aggregate_value_p call in init_function_start. All we can do is | |
4690 | ignore unknown tree types. */ | |
4691 | return VOIDmode; | |
4692 | } | |
4693 | ||
4694 | return VOIDmode; | |
4695 | } | |
4696 | ||
f57fc998 ZW |
4697 | /* Return the number of words required to hold a quantity of TYPE and MODE |
4698 | when passed as an argument. */ | |
4699 | static int | |
ef4bddc2 | 4700 | ia64_function_arg_words (const_tree type, machine_mode mode) |
f57fc998 ZW |
4701 | { |
4702 | int words; | |
4703 | ||
4704 | if (mode == BLKmode) | |
4705 | words = int_size_in_bytes (type); | |
4706 | else | |
4707 | words = GET_MODE_SIZE (mode); | |
4708 | ||
4709 | return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */ | |
4710 | } | |
4711 | ||
4712 | /* Return the number of registers that should be skipped so the current | |
4713 | argument (described by TYPE and WORDS) will be properly aligned. | |
4714 | ||
4715 | Integer and float arguments larger than 8 bytes start at the next | |
4716 | even boundary. Aggregates larger than 8 bytes start at the next | |
4717 | even boundary if the aggregate has 16 byte alignment. Note that | |
4718 | in the 32-bit ABI, TImode and TFmode have only 8-byte alignment | |
4719 | but are still to be aligned in registers. | |
4720 | ||
4721 | ??? The ABI does not specify how to handle aggregates with | |
4722 | alignment from 9 to 15 bytes, or greater than 16. We handle them | |
4723 | all as if they had 16 byte alignment. Such aggregates can occur | |
4724 | only if gcc extensions are used. */ | |
4725 | static int | |
ffa88471 SE |
4726 | ia64_function_arg_offset (const CUMULATIVE_ARGS *cum, |
4727 | const_tree type, int words) | |
f57fc998 | 4728 | { |
f2972bf8 DR |
4729 | /* No registers are skipped on VMS. */ |
4730 | if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0) | |
f57fc998 ZW |
4731 | return 0; |
4732 | ||
4733 | if (type | |
4734 | && TREE_CODE (type) != INTEGER_TYPE | |
4735 | && TREE_CODE (type) != REAL_TYPE) | |
4736 | return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT; | |
4737 | else | |
4738 | return words > 1; | |
4739 | } | |
4740 | ||
c65ebc55 JW |
4741 | /* Return rtx for register where argument is passed, or zero if it is passed |
4742 | on the stack. */ | |
c65ebc55 JW |
4743 | /* ??? 128-bit quad-precision floats are always passed in general |
4744 | registers. */ | |
4745 | ||
ffa88471 | 4746 | static rtx |
6783fdb7 RS |
4747 | ia64_function_arg_1 (cumulative_args_t cum_v, const function_arg_info &arg, |
4748 | bool incoming) | |
c65ebc55 | 4749 | { |
d5cc9181 JR |
4750 | const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4751 | ||
c65ebc55 | 4752 | int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST); |
6783fdb7 RS |
4753 | int words = ia64_function_arg_words (arg.type, arg.mode); |
4754 | int offset = ia64_function_arg_offset (cum, arg.type, words); | |
ef4bddc2 | 4755 | machine_mode hfa_mode = VOIDmode; |
c65ebc55 | 4756 | |
f2972bf8 DR |
4757 | /* For OPEN VMS, emit the instruction setting up the argument register here, |
4758 | when we know this will be together with the other arguments setup related | |
4759 | insns. This is not the conceptually best place to do this, but this is | |
4760 | the easiest as we have convenient access to cumulative args info. */ | |
4761 | ||
6783fdb7 | 4762 | if (TARGET_ABI_OPEN_VMS && arg.end_marker_p ()) |
f2972bf8 DR |
4763 | { |
4764 | unsigned HOST_WIDE_INT regval = cum->words; | |
4765 | int i; | |
4766 | ||
4767 | for (i = 0; i < 8; i++) | |
4768 | regval |= ((int) cum->atypes[i]) << (i * 3 + 8); | |
4769 | ||
4770 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)), | |
4771 | GEN_INT (regval)); | |
4772 | } | |
4773 | ||
c65ebc55 JW |
4774 | /* If all argument slots are used, then it must go on the stack. */ |
4775 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4776 | return 0; | |
4777 | ||
472b8fdc TG |
4778 | /* On OpenVMS argument is either in Rn or Fn. */ |
4779 | if (TARGET_ABI_OPEN_VMS) | |
4780 | { | |
6783fdb7 RS |
4781 | if (FLOAT_MODE_P (arg.mode)) |
4782 | return gen_rtx_REG (arg.mode, FR_ARG_FIRST + cum->words); | |
472b8fdc | 4783 | else |
6783fdb7 | 4784 | return gen_rtx_REG (arg.mode, basereg + cum->words); |
472b8fdc TG |
4785 | } |
4786 | ||
c65ebc55 | 4787 | /* Check for and handle homogeneous FP aggregates. */ |
6783fdb7 RS |
4788 | if (arg.type) |
4789 | hfa_mode = hfa_element_mode (arg.type, 0); | |
c65ebc55 JW |
4790 | |
4791 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4792 | and unprototyped hfas are passed specially. */ | |
6783fdb7 | 4793 | if (hfa_mode != VOIDmode && (! cum->prototype || arg.named)) |
c65ebc55 JW |
4794 | { |
4795 | rtx loc[16]; | |
4796 | int i = 0; | |
4797 | int fp_regs = cum->fp_regs; | |
4798 | int int_regs = cum->words + offset; | |
4799 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4800 | int byte_size; | |
4801 | int args_byte_size; | |
4802 | ||
4803 | /* If prototyped, pass it in FR regs then GR regs. | |
4804 | If not prototyped, pass it in both FR and GR regs. | |
4805 | ||
4806 | If this is an SFmode aggregate, then it is possible to run out of | |
4807 | FR regs while GR regs are still left. In that case, we pass the | |
4808 | remaining part in the GR regs. */ | |
4809 | ||
4810 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
4811 | of the argument, the last FP register, or the last argument slot. */ | |
4812 | ||
6783fdb7 | 4813 | byte_size = arg.promoted_size_in_bytes (); |
c65ebc55 JW |
4814 | args_byte_size = int_regs * UNITS_PER_WORD; |
4815 | offset = 0; | |
4816 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
4817 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++) | |
4818 | { | |
4819 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4820 | gen_rtx_REG (hfa_mode, (FR_ARG_FIRST | |
4821 | + fp_regs)), | |
4822 | GEN_INT (offset)); | |
c65ebc55 JW |
4823 | offset += hfa_size; |
4824 | args_byte_size += hfa_size; | |
4825 | fp_regs++; | |
4826 | } | |
4827 | ||
4828 | /* If no prototype, then the whole thing must go in GR regs. */ | |
4829 | if (! cum->prototype) | |
4830 | offset = 0; | |
4831 | /* If this is an SFmode aggregate, then we might have some left over | |
4832 | that needs to go in GR regs. */ | |
4833 | else if (byte_size != offset) | |
4834 | int_regs += offset / UNITS_PER_WORD; | |
4835 | ||
4836 | /* Fill in the GR regs. We must use DImode here, not the hfa mode. */ | |
4837 | ||
4838 | for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++) | |
4839 | { | |
ef4bddc2 | 4840 | machine_mode gr_mode = DImode; |
826b47cc | 4841 | unsigned int gr_size; |
c65ebc55 JW |
4842 | |
4843 | /* If we have an odd 4 byte hunk because we ran out of FR regs, | |
4844 | then this goes in a GR reg left adjusted/little endian, right | |
4845 | adjusted/big endian. */ | |
4846 | /* ??? Currently this is handled wrong, because 4-byte hunks are | |
4847 | always right adjusted/little endian. */ | |
4848 | if (offset & 0x4) | |
4849 | gr_mode = SImode; | |
4850 | /* If we have an even 4 byte hunk because the aggregate is a | |
4851 | multiple of 4 bytes in size, then this goes in a GR reg right | |
4852 | adjusted/little endian. */ | |
4853 | else if (byte_size - offset == 4) | |
4854 | gr_mode = SImode; | |
4855 | ||
4856 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4857 | gen_rtx_REG (gr_mode, (basereg | |
4858 | + int_regs)), | |
4859 | GEN_INT (offset)); | |
826b47cc ZW |
4860 | |
4861 | gr_size = GET_MODE_SIZE (gr_mode); | |
4862 | offset += gr_size; | |
4863 | if (gr_size == UNITS_PER_WORD | |
4864 | || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0)) | |
4865 | int_regs++; | |
4866 | else if (gr_size > UNITS_PER_WORD) | |
4867 | int_regs += gr_size / UNITS_PER_WORD; | |
c65ebc55 | 4868 | } |
6783fdb7 | 4869 | return gen_rtx_PARALLEL (arg.mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 4870 | } |
f2972bf8 | 4871 | |
c65ebc55 JW |
4872 | /* Integral and aggregates go in general registers. If we have run out of |
4873 | FR registers, then FP values must also go in general registers. This can | |
4874 | happen when we have a SFmode HFA. */ | |
6783fdb7 RS |
4875 | else if (arg.mode == TFmode || arg.mode == TCmode |
4876 | || !FLOAT_MODE_P (arg.mode) | |
4877 | || cum->fp_regs == MAX_ARGUMENT_SLOTS) | |
3870df96 | 4878 | { |
6783fdb7 | 4879 | int byte_size = arg.promoted_size_in_bytes (); |
3870df96 | 4880 | if (BYTES_BIG_ENDIAN |
6783fdb7 RS |
4881 | && (arg.mode == BLKmode || arg.aggregate_type_p ()) |
4882 | && byte_size < UNITS_PER_WORD | |
4883 | && byte_size > 0) | |
3870df96 SE |
4884 | { |
4885 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
4886 | gen_rtx_REG (DImode, | |
4887 | (basereg + cum->words | |
4888 | + offset)), | |
4889 | const0_rtx); | |
6783fdb7 | 4890 | return gen_rtx_PARALLEL (arg.mode, gen_rtvec (1, gr_reg)); |
3870df96 SE |
4891 | } |
4892 | else | |
6783fdb7 | 4893 | return gen_rtx_REG (arg.mode, basereg + cum->words + offset); |
3870df96 SE |
4894 | |
4895 | } | |
c65ebc55 JW |
4896 | |
4897 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 4898 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
4899 | else if (cum->prototype) |
4900 | { | |
6783fdb7 RS |
4901 | if (arg.named) |
4902 | return gen_rtx_REG (arg.mode, FR_ARG_FIRST + cum->fp_regs); | |
f9c887ac ZW |
4903 | /* In big-endian mode, an anonymous SFmode value must be represented |
4904 | as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force | |
4905 | the value into the high half of the general register. */ | |
6783fdb7 RS |
4906 | else if (BYTES_BIG_ENDIAN && arg.mode == SFmode) |
4907 | return gen_rtx_PARALLEL (arg.mode, | |
f9c887ac ZW |
4908 | gen_rtvec (1, |
4909 | gen_rtx_EXPR_LIST (VOIDmode, | |
4910 | gen_rtx_REG (DImode, basereg + cum->words + offset), | |
4911 | const0_rtx))); | |
4912 | else | |
6783fdb7 | 4913 | return gen_rtx_REG (arg.mode, basereg + cum->words + offset); |
c65ebc55 JW |
4914 | } |
4915 | /* If there is no prototype, then FP values go in both FR and GR | |
4916 | registers. */ | |
4917 | else | |
4918 | { | |
f9c887ac | 4919 | /* See comment above. */ |
ef4bddc2 | 4920 | machine_mode inner_mode = |
6783fdb7 | 4921 | (BYTES_BIG_ENDIAN && arg.mode == SFmode) ? DImode : arg.mode; |
f9c887ac | 4922 | |
c65ebc55 | 4923 | rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode, |
6783fdb7 | 4924 | gen_rtx_REG (arg.mode, (FR_ARG_FIRST |
c65ebc55 JW |
4925 | + cum->fp_regs)), |
4926 | const0_rtx); | |
4927 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
f9c887ac | 4928 | gen_rtx_REG (inner_mode, |
c65ebc55 JW |
4929 | (basereg + cum->words |
4930 | + offset)), | |
4931 | const0_rtx); | |
809d4ef1 | 4932 | |
6783fdb7 | 4933 | return gen_rtx_PARALLEL (arg.mode, gen_rtvec (2, fp_reg, gr_reg)); |
c65ebc55 JW |
4934 | } |
4935 | } | |
4936 | ||
ffa88471 SE |
4937 | /* Implement TARGET_FUNCION_ARG target hook. */ |
4938 | ||
4939 | static rtx | |
6783fdb7 | 4940 | ia64_function_arg (cumulative_args_t cum, const function_arg_info &arg) |
ffa88471 | 4941 | { |
6783fdb7 | 4942 | return ia64_function_arg_1 (cum, arg, false); |
ffa88471 SE |
4943 | } |
4944 | ||
4945 | /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */ | |
4946 | ||
4947 | static rtx | |
d5cc9181 | 4948 | ia64_function_incoming_arg (cumulative_args_t cum, |
6783fdb7 | 4949 | const function_arg_info &arg) |
ffa88471 | 4950 | { |
6783fdb7 | 4951 | return ia64_function_arg_1 (cum, arg, true); |
ffa88471 SE |
4952 | } |
4953 | ||
78a52f11 | 4954 | /* Return number of bytes, at the beginning of the argument, that must be |
c65ebc55 JW |
4955 | put in registers. 0 is the argument is entirely in registers or entirely |
4956 | in memory. */ | |
4957 | ||
78a52f11 | 4958 | static int |
a7c81bc1 | 4959 | ia64_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg) |
c65ebc55 | 4960 | { |
d5cc9181 JR |
4961 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4962 | ||
a7c81bc1 RS |
4963 | int words = ia64_function_arg_words (arg.type, arg.mode); |
4964 | int offset = ia64_function_arg_offset (cum, arg.type, words); | |
c65ebc55 JW |
4965 | |
4966 | /* If all argument slots are used, then it must go on the stack. */ | |
4967 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4968 | return 0; | |
4969 | ||
4970 | /* It doesn't matter whether the argument goes in FR or GR regs. If | |
4971 | it fits within the 8 argument slots, then it goes entirely in | |
4972 | registers. If it extends past the last argument slot, then the rest | |
4973 | goes on the stack. */ | |
4974 | ||
4975 | if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS) | |
4976 | return 0; | |
4977 | ||
78a52f11 | 4978 | return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD; |
c65ebc55 JW |
4979 | } |
4980 | ||
f2972bf8 DR |
4981 | /* Return ivms_arg_type based on machine_mode. */ |
4982 | ||
4983 | static enum ivms_arg_type | |
ef4bddc2 | 4984 | ia64_arg_type (machine_mode mode) |
f2972bf8 DR |
4985 | { |
4986 | switch (mode) | |
4987 | { | |
4e10a5a7 | 4988 | case E_SFmode: |
f2972bf8 | 4989 | return FS; |
4e10a5a7 | 4990 | case E_DFmode: |
f2972bf8 DR |
4991 | return FT; |
4992 | default: | |
4993 | return I64; | |
4994 | } | |
4995 | } | |
4996 | ||
c65ebc55 JW |
4997 | /* Update CUM to point after this argument. This is patterned after |
4998 | ia64_function_arg. */ | |
4999 | ||
ffa88471 | 5000 | static void |
6930c98c RS |
5001 | ia64_function_arg_advance (cumulative_args_t cum_v, |
5002 | const function_arg_info &arg) | |
c65ebc55 | 5003 | { |
d5cc9181 | 5004 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
6930c98c RS |
5005 | int words = ia64_function_arg_words (arg.type, arg.mode); |
5006 | int offset = ia64_function_arg_offset (cum, arg.type, words); | |
ef4bddc2 | 5007 | machine_mode hfa_mode = VOIDmode; |
c65ebc55 JW |
5008 | |
5009 | /* If all arg slots are already full, then there is nothing to do. */ | |
5010 | if (cum->words >= MAX_ARGUMENT_SLOTS) | |
f2972bf8 DR |
5011 | { |
5012 | cum->words += words + offset; | |
5013 | return; | |
5014 | } | |
c65ebc55 | 5015 | |
6930c98c | 5016 | cum->atypes[cum->words] = ia64_arg_type (arg.mode); |
c65ebc55 JW |
5017 | cum->words += words + offset; |
5018 | ||
472b8fdc TG |
5019 | /* On OpenVMS argument is either in Rn or Fn. */ |
5020 | if (TARGET_ABI_OPEN_VMS) | |
5021 | { | |
5022 | cum->int_regs = cum->words; | |
5023 | cum->fp_regs = cum->words; | |
5024 | return; | |
5025 | } | |
5026 | ||
c65ebc55 | 5027 | /* Check for and handle homogeneous FP aggregates. */ |
6930c98c RS |
5028 | if (arg.type) |
5029 | hfa_mode = hfa_element_mode (arg.type, 0); | |
c65ebc55 JW |
5030 | |
5031 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
5032 | and unprototyped hfas are passed specially. */ | |
6930c98c | 5033 | if (hfa_mode != VOIDmode && (! cum->prototype || arg.named)) |
c65ebc55 JW |
5034 | { |
5035 | int fp_regs = cum->fp_regs; | |
5036 | /* This is the original value of cum->words + offset. */ | |
5037 | int int_regs = cum->words - words; | |
5038 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
5039 | int byte_size; | |
5040 | int args_byte_size; | |
5041 | ||
5042 | /* If prototyped, pass it in FR regs then GR regs. | |
5043 | If not prototyped, pass it in both FR and GR regs. | |
5044 | ||
5045 | If this is an SFmode aggregate, then it is possible to run out of | |
5046 | FR regs while GR regs are still left. In that case, we pass the | |
5047 | remaining part in the GR regs. */ | |
5048 | ||
5049 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
5050 | of the argument, the last FP register, or the last argument slot. */ | |
5051 | ||
6930c98c | 5052 | byte_size = arg.promoted_size_in_bytes (); |
c65ebc55 JW |
5053 | args_byte_size = int_regs * UNITS_PER_WORD; |
5054 | offset = 0; | |
5055 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
5056 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));) | |
5057 | { | |
c65ebc55 JW |
5058 | offset += hfa_size; |
5059 | args_byte_size += hfa_size; | |
5060 | fp_regs++; | |
5061 | } | |
5062 | ||
5063 | cum->fp_regs = fp_regs; | |
5064 | } | |
5065 | ||
d13256a3 SE |
5066 | /* Integral and aggregates go in general registers. So do TFmode FP values. |
5067 | If we have run out of FR registers, then other FP values must also go in | |
5068 | general registers. This can happen when we have a SFmode HFA. */ | |
6930c98c RS |
5069 | else if (arg.mode == TFmode || arg.mode == TCmode |
5070 | || !FLOAT_MODE_P (arg.mode) | |
5071 | || cum->fp_regs == MAX_ARGUMENT_SLOTS) | |
648fe28b | 5072 | cum->int_regs = cum->words; |
c65ebc55 JW |
5073 | |
5074 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 5075 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
5076 | else if (cum->prototype) |
5077 | { | |
6930c98c | 5078 | if (! arg.named) |
648fe28b | 5079 | cum->int_regs = cum->words; |
c65ebc55 JW |
5080 | else |
5081 | /* ??? Complex types should not reach here. */ | |
6930c98c RS |
5082 | cum->fp_regs |
5083 | += (GET_MODE_CLASS (arg.mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
c65ebc55 JW |
5084 | } |
5085 | /* If there is no prototype, then FP values go in both FR and GR | |
5086 | registers. */ | |
5087 | else | |
9c808aad | 5088 | { |
648fe28b | 5089 | /* ??? Complex types should not reach here. */ |
6930c98c RS |
5090 | cum->fp_regs |
5091 | += (GET_MODE_CLASS (arg.mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
648fe28b RH |
5092 | cum->int_regs = cum->words; |
5093 | } | |
c65ebc55 | 5094 | } |
51dcde6f | 5095 | |
d13256a3 | 5096 | /* Arguments with alignment larger than 8 bytes start at the next even |
93348822 | 5097 | boundary. On ILP32 HPUX, TFmode arguments start on next even boundary |
d13256a3 SE |
5098 | even though their normal alignment is 8 bytes. See ia64_function_arg. */ |
5099 | ||
c2ed6cf8 | 5100 | static unsigned int |
ef4bddc2 | 5101 | ia64_function_arg_boundary (machine_mode mode, const_tree type) |
d13256a3 | 5102 | { |
d13256a3 SE |
5103 | if (mode == TFmode && TARGET_HPUX && TARGET_ILP32) |
5104 | return PARM_BOUNDARY * 2; | |
5105 | ||
5106 | if (type) | |
5107 | { | |
5108 | if (TYPE_ALIGN (type) > PARM_BOUNDARY) | |
5109 | return PARM_BOUNDARY * 2; | |
5110 | else | |
5111 | return PARM_BOUNDARY; | |
5112 | } | |
5113 | ||
5114 | if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY) | |
5115 | return PARM_BOUNDARY * 2; | |
5116 | else | |
5117 | return PARM_BOUNDARY; | |
5118 | } | |
5119 | ||
599aedd9 RH |
5120 | /* True if it is OK to do sibling call optimization for the specified |
5121 | call expression EXP. DECL will be the called function, or NULL if | |
5122 | this is an indirect call. */ | |
5123 | static bool | |
9c808aad | 5124 | ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
599aedd9 | 5125 | { |
097f3d48 JW |
5126 | /* We can't perform a sibcall if the current function has the syscall_linkage |
5127 | attribute. */ | |
5128 | if (lookup_attribute ("syscall_linkage", | |
5129 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
5130 | return false; | |
5131 | ||
b23ba0b8 | 5132 | /* We must always return with our current GP. This means we can |
c208436c SE |
5133 | only sibcall to functions defined in the current module unless |
5134 | TARGET_CONST_GP is set to true. */ | |
5135 | return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP; | |
599aedd9 | 5136 | } |
c65ebc55 | 5137 | \f |
c65ebc55 JW |
5138 | |
5139 | /* Implement va_arg. */ | |
5140 | ||
23a60a04 | 5141 | static tree |
726a989a RB |
5142 | ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
5143 | gimple_seq *post_p) | |
cd3ce9b4 | 5144 | { |
cd3ce9b4 | 5145 | /* Variable sized types are passed by reference. */ |
fde65a89 | 5146 | if (pass_va_arg_by_reference (type)) |
cd3ce9b4 | 5147 | { |
23a60a04 JM |
5148 | tree ptrtype = build_pointer_type (type); |
5149 | tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p); | |
c2433d7d | 5150 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5151 | } |
5152 | ||
5153 | /* Aggregate arguments with alignment larger than 8 bytes start at | |
5154 | the next even boundary. Integer and floating point arguments | |
5155 | do so if they are larger than 8 bytes, whether or not they are | |
5156 | also aligned larger than 8 bytes. */ | |
5157 | if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE) | |
5158 | ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT) | |
5159 | { | |
5d49b6a7 | 5160 | tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1); |
47a25a46 | 5161 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
5d49b6a7 | 5162 | build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD)); |
726a989a | 5163 | gimplify_assign (unshare_expr (valist), t, pre_p); |
cd3ce9b4 JM |
5164 | } |
5165 | ||
23a60a04 | 5166 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 | 5167 | } |
c65ebc55 JW |
5168 | \f |
5169 | /* Return 1 if function return value returned in memory. Return 0 if it is | |
5170 | in a register. */ | |
5171 | ||
351a758b | 5172 | static bool |
586de218 | 5173 | ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED) |
c65ebc55 | 5174 | { |
ef4bddc2 RS |
5175 | machine_mode mode; |
5176 | machine_mode hfa_mode; | |
487b97e0 | 5177 | HOST_WIDE_INT byte_size; |
c65ebc55 JW |
5178 | |
5179 | mode = TYPE_MODE (valtype); | |
487b97e0 RH |
5180 | byte_size = GET_MODE_SIZE (mode); |
5181 | if (mode == BLKmode) | |
5182 | { | |
5183 | byte_size = int_size_in_bytes (valtype); | |
5184 | if (byte_size < 0) | |
351a758b | 5185 | return true; |
487b97e0 | 5186 | } |
c65ebc55 JW |
5187 | |
5188 | /* Hfa's with up to 8 elements are returned in the FP argument registers. */ | |
5189 | ||
5190 | hfa_mode = hfa_element_mode (valtype, 0); | |
5191 | if (hfa_mode != VOIDmode) | |
5192 | { | |
5193 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
5194 | ||
c65ebc55 | 5195 | if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS) |
351a758b | 5196 | return true; |
c65ebc55 | 5197 | else |
351a758b | 5198 | return false; |
c65ebc55 | 5199 | } |
c65ebc55 | 5200 | else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS) |
351a758b | 5201 | return true; |
c65ebc55 | 5202 | else |
351a758b | 5203 | return false; |
c65ebc55 JW |
5204 | } |
5205 | ||
5206 | /* Return rtx for register that holds the function return value. */ | |
5207 | ||
ba90d838 AS |
5208 | static rtx |
5209 | ia64_function_value (const_tree valtype, | |
5210 | const_tree fn_decl_or_type, | |
5211 | bool outgoing ATTRIBUTE_UNUSED) | |
c65ebc55 | 5212 | { |
ef4bddc2 RS |
5213 | machine_mode mode; |
5214 | machine_mode hfa_mode; | |
f2972bf8 | 5215 | int unsignedp; |
ba90d838 | 5216 | const_tree func = fn_decl_or_type; |
c65ebc55 | 5217 | |
ba90d838 AS |
5218 | if (fn_decl_or_type |
5219 | && !DECL_P (fn_decl_or_type)) | |
5220 | func = NULL; | |
5221 | ||
c65ebc55 JW |
5222 | mode = TYPE_MODE (valtype); |
5223 | hfa_mode = hfa_element_mode (valtype, 0); | |
5224 | ||
5225 | if (hfa_mode != VOIDmode) | |
5226 | { | |
5227 | rtx loc[8]; | |
5228 | int i; | |
5229 | int hfa_size; | |
5230 | int byte_size; | |
5231 | int offset; | |
5232 | ||
5233 | hfa_size = GET_MODE_SIZE (hfa_mode); | |
5234 | byte_size = ((mode == BLKmode) | |
5235 | ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode)); | |
5236 | offset = 0; | |
5237 | for (i = 0; offset < byte_size; i++) | |
5238 | { | |
5239 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5240 | gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i), | |
5241 | GEN_INT (offset)); | |
c65ebc55 JW |
5242 | offset += hfa_size; |
5243 | } | |
9dec91d4 | 5244 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 5245 | } |
f57fc998 | 5246 | else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode) |
c65ebc55 JW |
5247 | return gen_rtx_REG (mode, FR_ARG_FIRST); |
5248 | else | |
3870df96 | 5249 | { |
8c5cacfd RH |
5250 | bool need_parallel = false; |
5251 | ||
5252 | /* In big-endian mode, we need to manage the layout of aggregates | |
5253 | in the registers so that we get the bits properly aligned in | |
5254 | the highpart of the registers. */ | |
3870df96 SE |
5255 | if (BYTES_BIG_ENDIAN |
5256 | && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype)))) | |
8c5cacfd RH |
5257 | need_parallel = true; |
5258 | ||
5259 | /* Something like struct S { long double x; char a[0] } is not an | |
5260 | HFA structure, and therefore doesn't go in fp registers. But | |
5261 | the middle-end will give it XFmode anyway, and XFmode values | |
5262 | don't normally fit in integer registers. So we need to smuggle | |
5263 | the value inside a parallel. */ | |
4de67c26 | 5264 | else if (mode == XFmode || mode == XCmode || mode == RFmode) |
8c5cacfd RH |
5265 | need_parallel = true; |
5266 | ||
5267 | if (need_parallel) | |
3870df96 SE |
5268 | { |
5269 | rtx loc[8]; | |
5270 | int offset; | |
5271 | int bytesize; | |
5272 | int i; | |
5273 | ||
5274 | offset = 0; | |
5275 | bytesize = int_size_in_bytes (valtype); | |
543144ed JM |
5276 | /* An empty PARALLEL is invalid here, but the return value |
5277 | doesn't matter for empty structs. */ | |
5278 | if (bytesize == 0) | |
5279 | return gen_rtx_REG (mode, GR_RET_FIRST); | |
3870df96 SE |
5280 | for (i = 0; offset < bytesize; i++) |
5281 | { | |
5282 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5283 | gen_rtx_REG (DImode, | |
5284 | GR_RET_FIRST + i), | |
5285 | GEN_INT (offset)); | |
5286 | offset += UNITS_PER_WORD; | |
5287 | } | |
5288 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); | |
5289 | } | |
8c5cacfd | 5290 | |
8ee95727 TG |
5291 | mode = promote_function_mode (valtype, mode, &unsignedp, |
5292 | func ? TREE_TYPE (func) : NULL_TREE, | |
5293 | true); | |
f2972bf8 | 5294 | |
8c5cacfd | 5295 | return gen_rtx_REG (mode, GR_RET_FIRST); |
3870df96 | 5296 | } |
c65ebc55 JW |
5297 | } |
5298 | ||
ba90d838 AS |
5299 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
5300 | ||
5301 | static rtx | |
ef4bddc2 | 5302 | ia64_libcall_value (machine_mode mode, |
ba90d838 AS |
5303 | const_rtx fun ATTRIBUTE_UNUSED) |
5304 | { | |
5305 | return gen_rtx_REG (mode, | |
5306 | (((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5307 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5308 | && (mode) != TFmode) | |
5309 | ? FR_RET_FIRST : GR_RET_FIRST)); | |
5310 | } | |
5311 | ||
5312 | /* Worker function for FUNCTION_VALUE_REGNO_P. */ | |
5313 | ||
5314 | static bool | |
5315 | ia64_function_value_regno_p (const unsigned int regno) | |
5316 | { | |
5317 | return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST) | |
5318 | || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST)); | |
5319 | } | |
5320 | ||
fdbe66f2 | 5321 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
5322 | We need to emit DTP-relative relocations. */ |
5323 | ||
fdbe66f2 | 5324 | static void |
9c808aad | 5325 | ia64_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 | 5326 | { |
6f3113ed SE |
5327 | gcc_assert (size == 4 || size == 8); |
5328 | if (size == 4) | |
5329 | fputs ("\tdata4.ua\t@dtprel(", file); | |
5330 | else | |
5331 | fputs ("\tdata8.ua\t@dtprel(", file); | |
6b2300b3 JJ |
5332 | output_addr_const (file, x); |
5333 | fputs (")", file); | |
5334 | } | |
5335 | ||
c65ebc55 JW |
5336 | /* Print a memory address as an operand to reference that memory location. */ |
5337 | ||
5338 | /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps | |
5339 | also call this from ia64_print_operand for memory addresses. */ | |
5340 | ||
5e50b799 | 5341 | static void |
9c808aad | 5342 | ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED, |
cc8ca59e | 5343 | machine_mode /*mode*/, |
9c808aad | 5344 | rtx address ATTRIBUTE_UNUSED) |
c65ebc55 JW |
5345 | { |
5346 | } | |
5347 | ||
3569057d | 5348 | /* Print an operand to an assembler instruction. |
c65ebc55 JW |
5349 | C Swap and print a comparison operator. |
5350 | D Print an FP comparison operator. | |
5351 | E Print 32 - constant, for SImode shifts as extract. | |
66db6b45 | 5352 | e Print 64 - constant, for DImode rotates. |
c65ebc55 JW |
5353 | F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or |
5354 | a floating point register emitted normally. | |
735b94a7 | 5355 | G A floating point constant. |
c65ebc55 | 5356 | I Invert a predicate register by adding 1. |
e5bde68a | 5357 | J Select the proper predicate register for a condition. |
6b6c1201 | 5358 | j Select the inverse predicate register for a condition. |
c65ebc55 JW |
5359 | O Append .acq for volatile load. |
5360 | P Postincrement of a MEM. | |
5361 | Q Append .rel for volatile store. | |
4883241c | 5362 | R Print .s .d or nothing for a single, double or no truncation. |
c65ebc55 JW |
5363 | S Shift amount for shladd instruction. |
5364 | T Print an 8-bit sign extended number (K) as a 32-bit unsigned number | |
5365 | for Intel assembler. | |
5366 | U Print an 8-bit sign extended number (K) as a 64-bit unsigned number | |
5367 | for Intel assembler. | |
a71aef0b | 5368 | X A pair of floating point registers. |
c65ebc55 | 5369 | r Print register name, or constant 0 as r0. HP compatibility for |
f61134e8 RH |
5370 | Linux kernel. |
5371 | v Print vector constant value as an 8-byte integer value. */ | |
5372 | ||
5e50b799 | 5373 | static void |
9c808aad | 5374 | ia64_print_operand (FILE * file, rtx x, int code) |
c65ebc55 | 5375 | { |
e57b9d65 RH |
5376 | const char *str; |
5377 | ||
c65ebc55 JW |
5378 | switch (code) |
5379 | { | |
c65ebc55 JW |
5380 | case 0: |
5381 | /* Handled below. */ | |
5382 | break; | |
809d4ef1 | 5383 | |
c65ebc55 JW |
5384 | case 'C': |
5385 | { | |
5386 | enum rtx_code c = swap_condition (GET_CODE (x)); | |
5387 | fputs (GET_RTX_NAME (c), file); | |
5388 | return; | |
5389 | } | |
5390 | ||
5391 | case 'D': | |
e57b9d65 RH |
5392 | switch (GET_CODE (x)) |
5393 | { | |
5394 | case NE: | |
5395 | str = "neq"; | |
5396 | break; | |
5397 | case UNORDERED: | |
5398 | str = "unord"; | |
5399 | break; | |
5400 | case ORDERED: | |
5401 | str = "ord"; | |
5402 | break; | |
86ad1da0 SE |
5403 | case UNLT: |
5404 | str = "nge"; | |
5405 | break; | |
5406 | case UNLE: | |
5407 | str = "ngt"; | |
5408 | break; | |
5409 | case UNGT: | |
5410 | str = "nle"; | |
5411 | break; | |
5412 | case UNGE: | |
5413 | str = "nlt"; | |
5414 | break; | |
8fc53a5f EB |
5415 | case UNEQ: |
5416 | case LTGT: | |
5417 | gcc_unreachable (); | |
e57b9d65 RH |
5418 | default: |
5419 | str = GET_RTX_NAME (GET_CODE (x)); | |
5420 | break; | |
5421 | } | |
5422 | fputs (str, file); | |
c65ebc55 JW |
5423 | return; |
5424 | ||
5425 | case 'E': | |
5426 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x)); | |
5427 | return; | |
5428 | ||
66db6b45 RH |
5429 | case 'e': |
5430 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x)); | |
5431 | return; | |
5432 | ||
c65ebc55 JW |
5433 | case 'F': |
5434 | if (x == CONST0_RTX (GET_MODE (x))) | |
e57b9d65 | 5435 | str = reg_names [FR_REG (0)]; |
c65ebc55 | 5436 | else if (x == CONST1_RTX (GET_MODE (x))) |
e57b9d65 | 5437 | str = reg_names [FR_REG (1)]; |
c65ebc55 | 5438 | else |
e820471b NS |
5439 | { |
5440 | gcc_assert (GET_CODE (x) == REG); | |
5441 | str = reg_names [REGNO (x)]; | |
5442 | } | |
e57b9d65 | 5443 | fputs (str, file); |
c65ebc55 JW |
5444 | return; |
5445 | ||
735b94a7 SE |
5446 | case 'G': |
5447 | { | |
5448 | long val[4]; | |
34a72c33 | 5449 | real_to_target (val, CONST_DOUBLE_REAL_VALUE (x), GET_MODE (x)); |
735b94a7 SE |
5450 | if (GET_MODE (x) == SFmode) |
5451 | fprintf (file, "0x%08lx", val[0] & 0xffffffff); | |
5452 | else if (GET_MODE (x) == DFmode) | |
5453 | fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1]) | |
5454 | & 0xffffffff, | |
5455 | (WORDS_BIG_ENDIAN ? val[1] : val[0]) | |
5456 | & 0xffffffff); | |
5457 | else | |
5458 | output_operand_lossage ("invalid %%G mode"); | |
5459 | } | |
5460 | return; | |
5461 | ||
c65ebc55 JW |
5462 | case 'I': |
5463 | fputs (reg_names [REGNO (x) + 1], file); | |
5464 | return; | |
5465 | ||
e5bde68a | 5466 | case 'J': |
6b6c1201 RH |
5467 | case 'j': |
5468 | { | |
5469 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5470 | if (GET_CODE (x) == EQ) | |
5471 | regno += 1; | |
5472 | if (code == 'j') | |
5473 | regno ^= 1; | |
5474 | fputs (reg_names [regno], file); | |
5475 | } | |
e5bde68a RH |
5476 | return; |
5477 | ||
c65ebc55 JW |
5478 | case 'O': |
5479 | if (MEM_VOLATILE_P (x)) | |
5480 | fputs(".acq", file); | |
5481 | return; | |
5482 | ||
5483 | case 'P': | |
5484 | { | |
4b983fdc | 5485 | HOST_WIDE_INT value; |
c65ebc55 | 5486 | |
4b983fdc RH |
5487 | switch (GET_CODE (XEXP (x, 0))) |
5488 | { | |
5489 | default: | |
5490 | return; | |
5491 | ||
5492 | case POST_MODIFY: | |
5493 | x = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
5494 | if (GET_CODE (x) == CONST_INT) | |
08012cda | 5495 | value = INTVAL (x); |
e820471b | 5496 | else |
4b983fdc | 5497 | { |
e820471b | 5498 | gcc_assert (GET_CODE (x) == REG); |
08012cda | 5499 | fprintf (file, ", %s", reg_names[REGNO (x)]); |
4b983fdc RH |
5500 | return; |
5501 | } | |
4b983fdc | 5502 | break; |
c65ebc55 | 5503 | |
4b983fdc RH |
5504 | case POST_INC: |
5505 | value = GET_MODE_SIZE (GET_MODE (x)); | |
4b983fdc | 5506 | break; |
c65ebc55 | 5507 | |
4b983fdc | 5508 | case POST_DEC: |
08012cda | 5509 | value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x)); |
4b983fdc RH |
5510 | break; |
5511 | } | |
809d4ef1 | 5512 | |
4a0a75dd | 5513 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value); |
c65ebc55 JW |
5514 | return; |
5515 | } | |
5516 | ||
5517 | case 'Q': | |
5518 | if (MEM_VOLATILE_P (x)) | |
5519 | fputs(".rel", file); | |
5520 | return; | |
5521 | ||
4883241c SE |
5522 | case 'R': |
5523 | if (x == CONST0_RTX (GET_MODE (x))) | |
5524 | fputs(".s", file); | |
5525 | else if (x == CONST1_RTX (GET_MODE (x))) | |
5526 | fputs(".d", file); | |
5527 | else if (x == CONST2_RTX (GET_MODE (x))) | |
5528 | ; | |
5529 | else | |
5530 | output_operand_lossage ("invalid %%R value"); | |
5531 | return; | |
5532 | ||
c65ebc55 | 5533 | case 'S': |
809d4ef1 | 5534 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
c65ebc55 JW |
5535 | return; |
5536 | ||
5537 | case 'T': | |
5538 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5539 | { | |
809d4ef1 | 5540 | fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5541 | return; |
5542 | } | |
5543 | break; | |
5544 | ||
5545 | case 'U': | |
5546 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5547 | { | |
3b572406 | 5548 | const char *prefix = "0x"; |
c65ebc55 JW |
5549 | if (INTVAL (x) & 0x80000000) |
5550 | { | |
5551 | fprintf (file, "0xffffffff"); | |
5552 | prefix = ""; | |
5553 | } | |
809d4ef1 | 5554 | fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5555 | return; |
5556 | } | |
5557 | break; | |
809d4ef1 | 5558 | |
a71aef0b JB |
5559 | case 'X': |
5560 | { | |
5561 | unsigned int regno = REGNO (x); | |
5562 | fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]); | |
5563 | } | |
5564 | return; | |
5565 | ||
c65ebc55 | 5566 | case 'r': |
18a3c539 JW |
5567 | /* If this operand is the constant zero, write it as register zero. |
5568 | Any register, zero, or CONST_INT value is OK here. */ | |
c65ebc55 JW |
5569 | if (GET_CODE (x) == REG) |
5570 | fputs (reg_names[REGNO (x)], file); | |
5571 | else if (x == CONST0_RTX (GET_MODE (x))) | |
5572 | fputs ("r0", file); | |
18a3c539 JW |
5573 | else if (GET_CODE (x) == CONST_INT) |
5574 | output_addr_const (file, x); | |
c65ebc55 JW |
5575 | else |
5576 | output_operand_lossage ("invalid %%r value"); | |
5577 | return; | |
5578 | ||
f61134e8 RH |
5579 | case 'v': |
5580 | gcc_assert (GET_CODE (x) == CONST_VECTOR); | |
5581 | x = simplify_subreg (DImode, x, GET_MODE (x), 0); | |
5582 | break; | |
5583 | ||
85548039 RH |
5584 | case '+': |
5585 | { | |
5586 | const char *which; | |
9c808aad | 5587 | |
85548039 RH |
5588 | /* For conditional branches, returns or calls, substitute |
5589 | sptk, dptk, dpnt, or spnt for %s. */ | |
5590 | x = find_reg_note (current_output_insn, REG_BR_PROB, 0); | |
5591 | if (x) | |
5592 | { | |
5fa396ad JH |
5593 | int pred_val = profile_probability::from_reg_br_prob_note |
5594 | (XINT (x, 0)).to_reg_br_prob_base (); | |
85548039 RH |
5595 | |
5596 | /* Guess top and bottom 10% statically predicted. */ | |
2c9e13f3 JH |
5597 | if (pred_val < REG_BR_PROB_BASE / 50 |
5598 | && br_prob_note_reliable_p (x)) | |
85548039 RH |
5599 | which = ".spnt"; |
5600 | else if (pred_val < REG_BR_PROB_BASE / 2) | |
5601 | which = ".dpnt"; | |
2c9e13f3 JH |
5602 | else if (pred_val < REG_BR_PROB_BASE / 100 * 98 |
5603 | || !br_prob_note_reliable_p (x)) | |
85548039 RH |
5604 | which = ".dptk"; |
5605 | else | |
5606 | which = ".sptk"; | |
5607 | } | |
b64925dc | 5608 | else if (CALL_P (current_output_insn)) |
85548039 RH |
5609 | which = ".sptk"; |
5610 | else | |
5611 | which = ".dptk"; | |
5612 | ||
5613 | fputs (which, file); | |
5614 | return; | |
5615 | } | |
5616 | ||
6f8aa100 RH |
5617 | case ',': |
5618 | x = current_insn_predicate; | |
5619 | if (x) | |
5620 | { | |
5621 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5622 | if (GET_CODE (x) == EQ) | |
5623 | regno += 1; | |
6f8aa100 RH |
5624 | fprintf (file, "(%s) ", reg_names [regno]); |
5625 | } | |
5626 | return; | |
5627 | ||
c65ebc55 JW |
5628 | default: |
5629 | output_operand_lossage ("ia64_print_operand: unknown code"); | |
5630 | return; | |
5631 | } | |
5632 | ||
5633 | switch (GET_CODE (x)) | |
5634 | { | |
5635 | /* This happens for the spill/restore instructions. */ | |
5636 | case POST_INC: | |
4b983fdc RH |
5637 | case POST_DEC: |
5638 | case POST_MODIFY: | |
c65ebc55 | 5639 | x = XEXP (x, 0); |
4c74215c | 5640 | /* fall through */ |
c65ebc55 JW |
5641 | |
5642 | case REG: | |
5643 | fputs (reg_names [REGNO (x)], file); | |
5644 | break; | |
5645 | ||
5646 | case MEM: | |
5647 | { | |
5648 | rtx addr = XEXP (x, 0); | |
ec8e098d | 5649 | if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC) |
c65ebc55 JW |
5650 | addr = XEXP (addr, 0); |
5651 | fprintf (file, "[%s]", reg_names [REGNO (addr)]); | |
5652 | break; | |
5653 | } | |
809d4ef1 | 5654 | |
c65ebc55 JW |
5655 | default: |
5656 | output_addr_const (file, x); | |
5657 | break; | |
5658 | } | |
5659 | ||
5660 | return; | |
5661 | } | |
5e50b799 AS |
5662 | |
5663 | /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ | |
5664 | ||
5665 | static bool | |
5666 | ia64_print_operand_punct_valid_p (unsigned char code) | |
5667 | { | |
5668 | return (code == '+' || code == ','); | |
5669 | } | |
c65ebc55 | 5670 | \f |
3c50106f RH |
5671 | /* Compute a (partial) cost for rtx X. Return true if the complete |
5672 | cost has been computed, and false if subexpressions should be | |
5673 | scanned. In either case, *TOTAL contains the cost result. */ | |
5674 | /* ??? This is incomplete. */ | |
5675 | ||
5676 | static bool | |
e548c9df AM |
5677 | ia64_rtx_costs (rtx x, machine_mode mode, int outer_code, |
5678 | int opno ATTRIBUTE_UNUSED, | |
68f932c4 | 5679 | int *total, bool speed ATTRIBUTE_UNUSED) |
3c50106f | 5680 | { |
e548c9df AM |
5681 | int code = GET_CODE (x); |
5682 | ||
3c50106f RH |
5683 | switch (code) |
5684 | { | |
5685 | case CONST_INT: | |
5686 | switch (outer_code) | |
5687 | { | |
5688 | case SET: | |
13f70342 | 5689 | *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1); |
3c50106f RH |
5690 | return true; |
5691 | case PLUS: | |
13f70342 | 5692 | if (satisfies_constraint_I (x)) |
3c50106f | 5693 | *total = 0; |
13f70342 | 5694 | else if (satisfies_constraint_J (x)) |
3c50106f RH |
5695 | *total = 1; |
5696 | else | |
5697 | *total = COSTS_N_INSNS (1); | |
5698 | return true; | |
5699 | default: | |
13f70342 | 5700 | if (satisfies_constraint_K (x) || satisfies_constraint_L (x)) |
3c50106f RH |
5701 | *total = 0; |
5702 | else | |
5703 | *total = COSTS_N_INSNS (1); | |
5704 | return true; | |
5705 | } | |
5706 | ||
5707 | case CONST_DOUBLE: | |
5708 | *total = COSTS_N_INSNS (1); | |
5709 | return true; | |
5710 | ||
5711 | case CONST: | |
5712 | case SYMBOL_REF: | |
5713 | case LABEL_REF: | |
5714 | *total = COSTS_N_INSNS (3); | |
5715 | return true; | |
5716 | ||
f19f1e5e RH |
5717 | case FMA: |
5718 | *total = COSTS_N_INSNS (4); | |
5719 | return true; | |
5720 | ||
3c50106f RH |
5721 | case MULT: |
5722 | /* For multiplies wider than HImode, we have to go to the FPU, | |
5723 | which normally involves copies. Plus there's the latency | |
5724 | of the multiply itself, and the latency of the instructions to | |
5725 | transfer integer regs to FP regs. */ | |
e548c9df | 5726 | if (FLOAT_MODE_P (mode)) |
f19f1e5e | 5727 | *total = COSTS_N_INSNS (4); |
e548c9df | 5728 | else if (GET_MODE_SIZE (mode) > 2) |
3c50106f RH |
5729 | *total = COSTS_N_INSNS (10); |
5730 | else | |
5731 | *total = COSTS_N_INSNS (2); | |
5732 | return true; | |
5733 | ||
5734 | case PLUS: | |
5735 | case MINUS: | |
e548c9df | 5736 | if (FLOAT_MODE_P (mode)) |
f19f1e5e RH |
5737 | { |
5738 | *total = COSTS_N_INSNS (4); | |
5739 | return true; | |
5740 | } | |
5741 | /* FALLTHRU */ | |
5742 | ||
3c50106f RH |
5743 | case ASHIFT: |
5744 | case ASHIFTRT: | |
5745 | case LSHIFTRT: | |
5746 | *total = COSTS_N_INSNS (1); | |
5747 | return true; | |
5748 | ||
5749 | case DIV: | |
5750 | case UDIV: | |
5751 | case MOD: | |
5752 | case UMOD: | |
5753 | /* We make divide expensive, so that divide-by-constant will be | |
5754 | optimized to a multiply. */ | |
5755 | *total = COSTS_N_INSNS (60); | |
5756 | return true; | |
5757 | ||
5758 | default: | |
5759 | return false; | |
5760 | } | |
5761 | } | |
5762 | ||
9e4f94de | 5763 | /* Calculate the cost of moving data from a register in class FROM to |
7109d286 | 5764 | one in class TO, using MODE. */ |
5527bf14 | 5765 | |
de8f4b07 | 5766 | static int |
ef4bddc2 | 5767 | ia64_register_move_cost (machine_mode mode, reg_class_t from, |
6f76a878 | 5768 | reg_class_t to) |
a87cf97e | 5769 | { |
7109d286 RH |
5770 | /* ADDL_REGS is the same as GR_REGS for movement purposes. */ |
5771 | if (to == ADDL_REGS) | |
5772 | to = GR_REGS; | |
5773 | if (from == ADDL_REGS) | |
5774 | from = GR_REGS; | |
5775 | ||
5776 | /* All costs are symmetric, so reduce cases by putting the | |
5777 | lower number class as the destination. */ | |
5778 | if (from < to) | |
5779 | { | |
6f76a878 | 5780 | reg_class_t tmp = to; |
7109d286 RH |
5781 | to = from, from = tmp; |
5782 | } | |
5783 | ||
02befdf4 | 5784 | /* Moving from FR<->GR in XFmode must be more expensive than 2, |
7109d286 | 5785 | so that we get secondary memory reloads. Between FR_REGS, |
69e18c09 | 5786 | we have to make this at least as expensive as memory_move_cost |
7109d286 | 5787 | to avoid spectacularly poor register class preferencing. */ |
4de67c26 | 5788 | if (mode == XFmode || mode == RFmode) |
7109d286 RH |
5789 | { |
5790 | if (to != GR_REGS || from != GR_REGS) | |
69e18c09 | 5791 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5792 | else |
5793 | return 3; | |
5794 | } | |
5795 | ||
5796 | switch (to) | |
5797 | { | |
5798 | case PR_REGS: | |
5799 | /* Moving between PR registers takes two insns. */ | |
5800 | if (from == PR_REGS) | |
5801 | return 3; | |
5802 | /* Moving between PR and anything but GR is impossible. */ | |
5803 | if (from != GR_REGS) | |
69e18c09 | 5804 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5805 | break; |
5806 | ||
5807 | case BR_REGS: | |
5808 | /* Moving between BR and anything but GR is impossible. */ | |
5809 | if (from != GR_REGS && from != GR_AND_BR_REGS) | |
69e18c09 | 5810 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5811 | break; |
5812 | ||
5813 | case AR_I_REGS: | |
5814 | case AR_M_REGS: | |
5815 | /* Moving between AR and anything but GR is impossible. */ | |
5816 | if (from != GR_REGS) | |
69e18c09 | 5817 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5818 | break; |
5819 | ||
5820 | case GR_REGS: | |
5821 | case FR_REGS: | |
a71aef0b | 5822 | case FP_REGS: |
7109d286 RH |
5823 | case GR_AND_FR_REGS: |
5824 | case GR_AND_BR_REGS: | |
5825 | case ALL_REGS: | |
5826 | break; | |
5827 | ||
5828 | default: | |
e820471b | 5829 | gcc_unreachable (); |
7109d286 | 5830 | } |
3f622353 | 5831 | |
5527bf14 RH |
5832 | return 2; |
5833 | } | |
c65ebc55 | 5834 | |
69e18c09 AS |
5835 | /* Calculate the cost of moving data of MODE from a register to or from |
5836 | memory. */ | |
5837 | ||
5838 | static int | |
ef4bddc2 | 5839 | ia64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
69e18c09 AS |
5840 | reg_class_t rclass, |
5841 | bool in ATTRIBUTE_UNUSED) | |
5842 | { | |
5843 | if (rclass == GENERAL_REGS | |
5844 | || rclass == FR_REGS | |
5845 | || rclass == FP_REGS | |
5846 | || rclass == GR_AND_FR_REGS) | |
5847 | return 4; | |
5848 | else | |
5849 | return 10; | |
5850 | } | |
5851 | ||
ab177ad5 AS |
5852 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions |
5853 | on RCLASS to use when copying X into that class. */ | |
f61134e8 | 5854 | |
ab177ad5 AS |
5855 | static reg_class_t |
5856 | ia64_preferred_reload_class (rtx x, reg_class_t rclass) | |
f61134e8 | 5857 | { |
0a2aaacc | 5858 | switch (rclass) |
f61134e8 RH |
5859 | { |
5860 | case FR_REGS: | |
a71aef0b | 5861 | case FP_REGS: |
f61134e8 RH |
5862 | /* Don't allow volatile mem reloads into floating point registers. |
5863 | This is defined to force reload to choose the r/m case instead | |
5864 | of the f/f case when reloading (set (reg fX) (mem/v)). */ | |
5865 | if (MEM_P (x) && MEM_VOLATILE_P (x)) | |
5866 | return NO_REGS; | |
5867 | ||
5868 | /* Force all unrecognized constants into the constant pool. */ | |
5869 | if (CONSTANT_P (x)) | |
5870 | return NO_REGS; | |
5871 | break; | |
5872 | ||
5873 | case AR_M_REGS: | |
5874 | case AR_I_REGS: | |
5875 | if (!OBJECT_P (x)) | |
5876 | return NO_REGS; | |
5877 | break; | |
5878 | ||
5879 | default: | |
5880 | break; | |
5881 | } | |
5882 | ||
0a2aaacc | 5883 | return rclass; |
f61134e8 RH |
5884 | } |
5885 | ||
c65ebc55 | 5886 | /* This function returns the register class required for a secondary |
0a2aaacc | 5887 | register when copying between one of the registers in RCLASS, and X, |
c65ebc55 JW |
5888 | using MODE. A return value of NO_REGS means that no secondary register |
5889 | is required. */ | |
5890 | ||
5891 | enum reg_class | |
0a2aaacc | 5892 | ia64_secondary_reload_class (enum reg_class rclass, |
ef4bddc2 | 5893 | machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
c65ebc55 JW |
5894 | { |
5895 | int regno = -1; | |
5896 | ||
5897 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
5898 | regno = true_regnum (x); | |
5899 | ||
0a2aaacc | 5900 | switch (rclass) |
97e242b0 RH |
5901 | { |
5902 | case BR_REGS: | |
7109d286 RH |
5903 | case AR_M_REGS: |
5904 | case AR_I_REGS: | |
5905 | /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global | |
5906 | interaction. We end up with two pseudos with overlapping lifetimes | |
5907 | both of which are equiv to the same constant, and both which need | |
5908 | to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end | |
5909 | changes depending on the path length, which means the qty_first_reg | |
5910 | check in make_regs_eqv can give different answers at different times. | |
5911 | At some point I'll probably need a reload_indi pattern to handle | |
5912 | this. | |
5913 | ||
5914 | We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we | |
5915 | wound up with a FP register from GR_AND_FR_REGS. Extend that to all | |
5916 | non-general registers for good measure. */ | |
5917 | if (regno >= 0 && ! GENERAL_REGNO_P (regno)) | |
97e242b0 RH |
5918 | return GR_REGS; |
5919 | ||
5920 | /* This is needed if a pseudo used as a call_operand gets spilled to a | |
5921 | stack slot. */ | |
5922 | if (GET_CODE (x) == MEM) | |
5923 | return GR_REGS; | |
5924 | break; | |
5925 | ||
5926 | case FR_REGS: | |
a71aef0b | 5927 | case FP_REGS: |
c51e6d85 | 5928 | /* Need to go through general registers to get to other class regs. */ |
7109d286 RH |
5929 | if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno))) |
5930 | return GR_REGS; | |
9c808aad | 5931 | |
97e242b0 RH |
5932 | /* This can happen when a paradoxical subreg is an operand to the |
5933 | muldi3 pattern. */ | |
5934 | /* ??? This shouldn't be necessary after instruction scheduling is | |
5935 | enabled, because paradoxical subregs are not accepted by | |
5936 | register_operand when INSN_SCHEDULING is defined. Or alternatively, | |
5937 | stop the paradoxical subreg stupidity in the *_operand functions | |
5938 | in recog.c. */ | |
5939 | if (GET_CODE (x) == MEM | |
5940 | && (GET_MODE (x) == SImode || GET_MODE (x) == HImode | |
5941 | || GET_MODE (x) == QImode)) | |
5942 | return GR_REGS; | |
5943 | ||
5944 | /* This can happen because of the ior/and/etc patterns that accept FP | |
5945 | registers as operands. If the third operand is a constant, then it | |
5946 | needs to be reloaded into a FP register. */ | |
5947 | if (GET_CODE (x) == CONST_INT) | |
5948 | return GR_REGS; | |
5949 | ||
5950 | /* This can happen because of register elimination in a muldi3 insn. | |
5951 | E.g. `26107 * (unsigned long)&u'. */ | |
5952 | if (GET_CODE (x) == PLUS) | |
5953 | return GR_REGS; | |
5954 | break; | |
5955 | ||
5956 | case PR_REGS: | |
f2f90c63 | 5957 | /* ??? This happens if we cse/gcse a BImode value across a call, |
97e242b0 RH |
5958 | and the function has a nonlocal goto. This is because global |
5959 | does not allocate call crossing pseudos to hard registers when | |
e3b5732b | 5960 | crtl->has_nonlocal_goto is true. This is relatively |
97e242b0 RH |
5961 | common for C++ programs that use exceptions. To reproduce, |
5962 | return NO_REGS and compile libstdc++. */ | |
5963 | if (GET_CODE (x) == MEM) | |
5964 | return GR_REGS; | |
f2f90c63 RH |
5965 | |
5966 | /* This can happen when we take a BImode subreg of a DImode value, | |
5967 | and that DImode value winds up in some non-GR register. */ | |
5968 | if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno)) | |
5969 | return GR_REGS; | |
97e242b0 RH |
5970 | break; |
5971 | ||
5972 | default: | |
5973 | break; | |
5974 | } | |
c65ebc55 JW |
5975 | |
5976 | return NO_REGS; | |
5977 | } | |
5978 | ||
215b063c PB |
5979 | \f |
5980 | /* Implement targetm.unspec_may_trap_p hook. */ | |
5981 | static int | |
5982 | ia64_unspec_may_trap_p (const_rtx x, unsigned flags) | |
5983 | { | |
c84a808e EB |
5984 | switch (XINT (x, 1)) |
5985 | { | |
5986 | case UNSPEC_LDA: | |
5987 | case UNSPEC_LDS: | |
5988 | case UNSPEC_LDSA: | |
5989 | case UNSPEC_LDCCLR: | |
5990 | case UNSPEC_CHKACLR: | |
5991 | case UNSPEC_CHKS: | |
5992 | /* These unspecs are just wrappers. */ | |
5993 | return may_trap_p_1 (XVECEXP (x, 0, 0), flags); | |
215b063c PB |
5994 | } |
5995 | ||
5996 | return default_unspec_may_trap_p (x, flags); | |
5997 | } | |
5998 | ||
c65ebc55 JW |
5999 | \f |
6000 | /* Parse the -mfixed-range= option string. */ | |
6001 | ||
6002 | static void | |
9c808aad | 6003 | fix_range (const char *const_str) |
c65ebc55 JW |
6004 | { |
6005 | int i, first, last; | |
3b572406 | 6006 | char *str, *dash, *comma; |
c65ebc55 JW |
6007 | |
6008 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
6009 | REG2 are either register names or register numbers. The effect | |
6010 | of this option is to mark the registers in the range from REG1 to | |
6011 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
6012 | used, e.g., to ensure that kernel mode code doesn't use f32-f127. */ | |
6013 | ||
3b572406 RH |
6014 | i = strlen (const_str); |
6015 | str = (char *) alloca (i + 1); | |
6016 | memcpy (str, const_str, i + 1); | |
6017 | ||
c65ebc55 JW |
6018 | while (1) |
6019 | { | |
6020 | dash = strchr (str, '-'); | |
6021 | if (!dash) | |
6022 | { | |
a3f9f006 | 6023 | warning (0, "value of %<-mfixed-range%> must have form REG1-REG2"); |
c65ebc55 JW |
6024 | return; |
6025 | } | |
6026 | *dash = '\0'; | |
6027 | ||
6028 | comma = strchr (dash + 1, ','); | |
6029 | if (comma) | |
6030 | *comma = '\0'; | |
6031 | ||
6032 | first = decode_reg_name (str); | |
6033 | if (first < 0) | |
6034 | { | |
d4ee4d25 | 6035 | warning (0, "unknown register name: %s", str); |
c65ebc55 JW |
6036 | return; |
6037 | } | |
6038 | ||
6039 | last = decode_reg_name (dash + 1); | |
6040 | if (last < 0) | |
6041 | { | |
d4ee4d25 | 6042 | warning (0, "unknown register name: %s", dash + 1); |
c65ebc55 JW |
6043 | return; |
6044 | } | |
6045 | ||
6046 | *dash = '-'; | |
6047 | ||
6048 | if (first > last) | |
6049 | { | |
d4ee4d25 | 6050 | warning (0, "%s-%s is an empty range", str, dash + 1); |
c65ebc55 JW |
6051 | return; |
6052 | } | |
6053 | ||
6054 | for (i = first; i <= last; ++i) | |
6055 | fixed_regs[i] = call_used_regs[i] = 1; | |
6056 | ||
6057 | if (!comma) | |
6058 | break; | |
6059 | ||
6060 | *comma = ','; | |
6061 | str = comma + 1; | |
6062 | } | |
6063 | } | |
6064 | ||
930572b9 | 6065 | /* Implement TARGET_OPTION_OVERRIDE. */ |
c65ebc55 | 6066 | |
930572b9 AS |
6067 | static void |
6068 | ia64_option_override (void) | |
c65ebc55 | 6069 | { |
e6cc0c98 JM |
6070 | unsigned int i; |
6071 | cl_deferred_option *opt; | |
9771b263 DN |
6072 | vec<cl_deferred_option> *v |
6073 | = (vec<cl_deferred_option> *) ia64_deferred_options; | |
e6cc0c98 | 6074 | |
9771b263 DN |
6075 | if (v) |
6076 | FOR_EACH_VEC_ELT (*v, i, opt) | |
6077 | { | |
6078 | switch (opt->opt_index) | |
6079 | { | |
6080 | case OPT_mfixed_range_: | |
6081 | fix_range (opt->arg); | |
6082 | break; | |
e6cc0c98 | 6083 | |
9771b263 DN |
6084 | default: |
6085 | gcc_unreachable (); | |
6086 | } | |
6087 | } | |
e6cc0c98 | 6088 | |
59da9a7d JW |
6089 | if (TARGET_AUTO_PIC) |
6090 | target_flags |= MASK_CONST_GP; | |
6091 | ||
7e1e7d4c VM |
6092 | /* Numerous experiment shows that IRA based loop pressure |
6093 | calculation works better for RTL loop invariant motion on targets | |
6094 | with enough (>= 32) registers. It is an expensive optimization. | |
6095 | So it is on only for peak performance. */ | |
6096 | if (optimize >= 3) | |
6097 | flag_ira_loop_pressure = 1; | |
6098 | ||
6099 | ||
fa37ed29 JM |
6100 | ia64_section_threshold = (global_options_set.x_g_switch_value |
6101 | ? g_switch_value | |
6102 | : IA64_DEFAULT_GVALUE); | |
2b7e2984 SE |
6103 | |
6104 | init_machine_status = ia64_init_machine_status; | |
6105 | ||
c518c102 ML |
6106 | if (flag_align_functions && !str_align_functions) |
6107 | str_align_functions = "64"; | |
6108 | if (flag_align_loops && !str_align_loops) | |
6109 | str_align_loops = "32"; | |
2b7e2984 SE |
6110 | if (TARGET_ABI_OPEN_VMS) |
6111 | flag_no_common = 1; | |
6112 | ||
6113 | ia64_override_options_after_change(); | |
6114 | } | |
6115 | ||
6116 | /* Implement targetm.override_options_after_change. */ | |
6117 | ||
6118 | static void | |
6119 | ia64_override_options_after_change (void) | |
6120 | { | |
388092d5 | 6121 | if (optimize >= 3 |
d4d24ba4 JM |
6122 | && !global_options_set.x_flag_selective_scheduling |
6123 | && !global_options_set.x_flag_selective_scheduling2) | |
388092d5 AB |
6124 | { |
6125 | flag_selective_scheduling2 = 1; | |
6126 | flag_sel_sched_pipelining = 1; | |
6127 | } | |
6128 | if (mflag_sched_control_spec == 2) | |
6129 | { | |
6130 | /* Control speculation is on by default for the selective scheduler, | |
6131 | but not for the Haifa scheduler. */ | |
6132 | mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0; | |
6133 | } | |
6134 | if (flag_sel_sched_pipelining && flag_auto_inc_dec) | |
6135 | { | |
6136 | /* FIXME: remove this when we'd implement breaking autoinsns as | |
6137 | a transformation. */ | |
6138 | flag_auto_inc_dec = 0; | |
6139 | } | |
c65ebc55 | 6140 | } |
dbdd120f | 6141 | |
6fb5fa3c DB |
6142 | /* Initialize the record of emitted frame related registers. */ |
6143 | ||
6144 | void ia64_init_expanders (void) | |
6145 | { | |
6146 | memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs)); | |
6147 | } | |
6148 | ||
dbdd120f RH |
6149 | static struct machine_function * |
6150 | ia64_init_machine_status (void) | |
6151 | { | |
766090c2 | 6152 | return ggc_cleared_alloc<machine_function> (); |
dbdd120f | 6153 | } |
c65ebc55 | 6154 | \f |
647d790d DM |
6155 | static enum attr_itanium_class ia64_safe_itanium_class (rtx_insn *); |
6156 | static enum attr_type ia64_safe_type (rtx_insn *); | |
2130b7fb | 6157 | |
2130b7fb | 6158 | static enum attr_itanium_class |
647d790d | 6159 | ia64_safe_itanium_class (rtx_insn *insn) |
2130b7fb BS |
6160 | { |
6161 | if (recog_memoized (insn) >= 0) | |
6162 | return get_attr_itanium_class (insn); | |
b5b8b0ac AO |
6163 | else if (DEBUG_INSN_P (insn)) |
6164 | return ITANIUM_CLASS_IGNORE; | |
2130b7fb BS |
6165 | else |
6166 | return ITANIUM_CLASS_UNKNOWN; | |
6167 | } | |
6168 | ||
6169 | static enum attr_type | |
647d790d | 6170 | ia64_safe_type (rtx_insn *insn) |
2130b7fb BS |
6171 | { |
6172 | if (recog_memoized (insn) >= 0) | |
6173 | return get_attr_type (insn); | |
6174 | else | |
6175 | return TYPE_UNKNOWN; | |
6176 | } | |
6177 | \f | |
c65ebc55 JW |
6178 | /* The following collection of routines emit instruction group stop bits as |
6179 | necessary to avoid dependencies. */ | |
6180 | ||
6181 | /* Need to track some additional registers as far as serialization is | |
6182 | concerned so we can properly handle br.call and br.ret. We could | |
6183 | make these registers visible to gcc, but since these registers are | |
6184 | never explicitly used in gcc generated code, it seems wasteful to | |
6185 | do so (plus it would make the call and return patterns needlessly | |
6186 | complex). */ | |
c65ebc55 | 6187 | #define REG_RP (BR_REG (0)) |
c65ebc55 | 6188 | #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1) |
c65ebc55 JW |
6189 | /* This is used for volatile asms which may require a stop bit immediately |
6190 | before and after them. */ | |
5527bf14 | 6191 | #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2) |
870f9ec0 RH |
6192 | #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3) |
6193 | #define NUM_REGS (AR_UNAT_BIT_0 + 64) | |
c65ebc55 | 6194 | |
f2f90c63 RH |
6195 | /* For each register, we keep track of how it has been written in the |
6196 | current instruction group. | |
6197 | ||
6198 | If a register is written unconditionally (no qualifying predicate), | |
6199 | WRITE_COUNT is set to 2 and FIRST_PRED is ignored. | |
6200 | ||
6201 | If a register is written if its qualifying predicate P is true, we | |
6202 | set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register | |
6203 | may be written again by the complement of P (P^1) and when this happens, | |
6204 | WRITE_COUNT gets set to 2. | |
6205 | ||
6206 | The result of this is that whenever an insn attempts to write a register | |
e03f5d43 | 6207 | whose WRITE_COUNT is two, we need to issue an insn group barrier first. |
f2f90c63 RH |
6208 | |
6209 | If a predicate register is written by a floating-point insn, we set | |
6210 | WRITTEN_BY_FP to true. | |
6211 | ||
6212 | If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND | |
6213 | to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */ | |
6214 | ||
444a356a JJ |
6215 | #if GCC_VERSION >= 4000 |
6216 | #define RWS_FIELD_TYPE __extension__ unsigned short | |
6217 | #else | |
6218 | #define RWS_FIELD_TYPE unsigned int | |
6219 | #endif | |
c65ebc55 JW |
6220 | struct reg_write_state |
6221 | { | |
444a356a JJ |
6222 | RWS_FIELD_TYPE write_count : 2; |
6223 | RWS_FIELD_TYPE first_pred : 10; | |
6224 | RWS_FIELD_TYPE written_by_fp : 1; | |
6225 | RWS_FIELD_TYPE written_by_and : 1; | |
6226 | RWS_FIELD_TYPE written_by_or : 1; | |
c65ebc55 JW |
6227 | }; |
6228 | ||
6229 | /* Cumulative info for the current instruction group. */ | |
6230 | struct reg_write_state rws_sum[NUM_REGS]; | |
e28c2052 | 6231 | #if CHECKING_P |
444a356a | 6232 | /* Bitmap whether a register has been written in the current insn. */ |
504279ae RS |
6233 | unsigned HOST_WIDEST_FAST_INT rws_insn |
6234 | [(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) | |
6235 | / HOST_BITS_PER_WIDEST_FAST_INT]; | |
444a356a JJ |
6236 | |
6237 | static inline void | |
504279ae | 6238 | rws_insn_set (unsigned int regno) |
444a356a | 6239 | { |
504279ae RS |
6240 | unsigned int elt = regno / HOST_BITS_PER_WIDEST_FAST_INT; |
6241 | unsigned int bit = regno % HOST_BITS_PER_WIDEST_FAST_INT; | |
6242 | gcc_assert (!((rws_insn[elt] >> bit) & 1)); | |
6243 | rws_insn[elt] |= (unsigned HOST_WIDEST_FAST_INT) 1 << bit; | |
444a356a JJ |
6244 | } |
6245 | ||
6246 | static inline int | |
504279ae | 6247 | rws_insn_test (unsigned int regno) |
444a356a | 6248 | { |
504279ae RS |
6249 | unsigned int elt = regno / HOST_BITS_PER_WIDEST_FAST_INT; |
6250 | unsigned int bit = regno % HOST_BITS_PER_WIDEST_FAST_INT; | |
6251 | return (rws_insn[elt] >> bit) & 1; | |
444a356a JJ |
6252 | } |
6253 | #else | |
6254 | /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */ | |
6255 | unsigned char rws_insn[2]; | |
6256 | ||
6257 | static inline void | |
6258 | rws_insn_set (int regno) | |
6259 | { | |
6260 | if (regno == REG_AR_CFM) | |
6261 | rws_insn[0] = 1; | |
6262 | else if (regno == REG_VOLATILE) | |
6263 | rws_insn[1] = 1; | |
6264 | } | |
6265 | ||
6266 | static inline int | |
6267 | rws_insn_test (int regno) | |
6268 | { | |
6269 | if (regno == REG_AR_CFM) | |
6270 | return rws_insn[0]; | |
6271 | if (regno == REG_VOLATILE) | |
6272 | return rws_insn[1]; | |
6273 | return 0; | |
6274 | } | |
6275 | #endif | |
c65ebc55 | 6276 | |
25250265 | 6277 | /* Indicates whether this is the first instruction after a stop bit, |
e820471b NS |
6278 | in which case we don't need another stop bit. Without this, |
6279 | ia64_variable_issue will die when scheduling an alloc. */ | |
25250265 JW |
6280 | static int first_instruction; |
6281 | ||
c65ebc55 JW |
6282 | /* Misc flags needed to compute RAW/WAW dependencies while we are traversing |
6283 | RTL for one instruction. */ | |
6284 | struct reg_flags | |
6285 | { | |
6286 | unsigned int is_write : 1; /* Is register being written? */ | |
6287 | unsigned int is_fp : 1; /* Is register used as part of an fp op? */ | |
6288 | unsigned int is_branch : 1; /* Is register used as part of a branch? */ | |
f2f90c63 RH |
6289 | unsigned int is_and : 1; /* Is register used as part of and.orcm? */ |
6290 | unsigned int is_or : 1; /* Is register used as part of or.andcm? */ | |
2ed4af6f | 6291 | unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */ |
c65ebc55 JW |
6292 | }; |
6293 | ||
444a356a | 6294 | static void rws_update (int, struct reg_flags, int); |
9c808aad AJ |
6295 | static int rws_access_regno (int, struct reg_flags, int); |
6296 | static int rws_access_reg (rtx, struct reg_flags, int); | |
c1bc6ca8 JW |
6297 | static void update_set_flags (rtx, struct reg_flags *); |
6298 | static int set_src_needs_barrier (rtx, struct reg_flags, int); | |
9c808aad AJ |
6299 | static int rtx_needs_barrier (rtx, struct reg_flags, int); |
6300 | static void init_insn_group_barriers (void); | |
647d790d DM |
6301 | static int group_barrier_needed (rtx_insn *); |
6302 | static int safe_group_barrier_needed (rtx_insn *); | |
444a356a | 6303 | static int in_safe_group_barrier; |
3b572406 | 6304 | |
c65ebc55 JW |
6305 | /* Update *RWS for REGNO, which is being written by the current instruction, |
6306 | with predicate PRED, and associated register flags in FLAGS. */ | |
6307 | ||
6308 | static void | |
444a356a | 6309 | rws_update (int regno, struct reg_flags flags, int pred) |
c65ebc55 | 6310 | { |
3e7c7805 | 6311 | if (pred) |
444a356a | 6312 | rws_sum[regno].write_count++; |
3e7c7805 | 6313 | else |
444a356a JJ |
6314 | rws_sum[regno].write_count = 2; |
6315 | rws_sum[regno].written_by_fp |= flags.is_fp; | |
f2f90c63 | 6316 | /* ??? Not tracking and/or across differing predicates. */ |
444a356a JJ |
6317 | rws_sum[regno].written_by_and = flags.is_and; |
6318 | rws_sum[regno].written_by_or = flags.is_or; | |
6319 | rws_sum[regno].first_pred = pred; | |
c65ebc55 JW |
6320 | } |
6321 | ||
6322 | /* Handle an access to register REGNO of type FLAGS using predicate register | |
444a356a | 6323 | PRED. Update rws_sum array. Return 1 if this access creates |
c65ebc55 JW |
6324 | a dependency with an earlier instruction in the same group. */ |
6325 | ||
6326 | static int | |
9c808aad | 6327 | rws_access_regno (int regno, struct reg_flags flags, int pred) |
c65ebc55 JW |
6328 | { |
6329 | int need_barrier = 0; | |
c65ebc55 | 6330 | |
e820471b | 6331 | gcc_assert (regno < NUM_REGS); |
c65ebc55 | 6332 | |
f2f90c63 RH |
6333 | if (! PR_REGNO_P (regno)) |
6334 | flags.is_and = flags.is_or = 0; | |
6335 | ||
c65ebc55 JW |
6336 | if (flags.is_write) |
6337 | { | |
12c2c7aa JW |
6338 | int write_count; |
6339 | ||
444a356a | 6340 | rws_insn_set (regno); |
12c2c7aa | 6341 | write_count = rws_sum[regno].write_count; |
12c2c7aa JW |
6342 | |
6343 | switch (write_count) | |
c65ebc55 JW |
6344 | { |
6345 | case 0: | |
6346 | /* The register has not been written yet. */ | |
444a356a JJ |
6347 | if (!in_safe_group_barrier) |
6348 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6349 | break; |
6350 | ||
6351 | case 1: | |
89774469 SE |
6352 | /* The register has been written via a predicate. Treat |
6353 | it like a unconditional write and do not try to check | |
6354 | for complementary pred reg in earlier write. */ | |
f2f90c63 | 6355 | if (flags.is_and && rws_sum[regno].written_by_and) |
9c808aad | 6356 | ; |
f2f90c63 RH |
6357 | else if (flags.is_or && rws_sum[regno].written_by_or) |
6358 | ; | |
89774469 | 6359 | else |
c65ebc55 | 6360 | need_barrier = 1; |
444a356a JJ |
6361 | if (!in_safe_group_barrier) |
6362 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6363 | break; |
6364 | ||
6365 | case 2: | |
6366 | /* The register has been unconditionally written already. We | |
6367 | need a barrier. */ | |
f2f90c63 RH |
6368 | if (flags.is_and && rws_sum[regno].written_by_and) |
6369 | ; | |
6370 | else if (flags.is_or && rws_sum[regno].written_by_or) | |
6371 | ; | |
6372 | else | |
6373 | need_barrier = 1; | |
444a356a JJ |
6374 | if (!in_safe_group_barrier) |
6375 | { | |
6376 | rws_sum[regno].written_by_and = flags.is_and; | |
6377 | rws_sum[regno].written_by_or = flags.is_or; | |
6378 | } | |
c65ebc55 JW |
6379 | break; |
6380 | ||
6381 | default: | |
e820471b | 6382 | gcc_unreachable (); |
c65ebc55 JW |
6383 | } |
6384 | } | |
6385 | else | |
6386 | { | |
6387 | if (flags.is_branch) | |
6388 | { | |
6389 | /* Branches have several RAW exceptions that allow to avoid | |
6390 | barriers. */ | |
6391 | ||
5527bf14 | 6392 | if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM) |
c65ebc55 JW |
6393 | /* RAW dependencies on branch regs are permissible as long |
6394 | as the writer is a non-branch instruction. Since we | |
6395 | never generate code that uses a branch register written | |
6396 | by a branch instruction, handling this case is | |
6397 | easy. */ | |
5527bf14 | 6398 | return 0; |
c65ebc55 JW |
6399 | |
6400 | if (REGNO_REG_CLASS (regno) == PR_REGS | |
6401 | && ! rws_sum[regno].written_by_fp) | |
6402 | /* The predicates of a branch are available within the | |
6403 | same insn group as long as the predicate was written by | |
ed168e45 | 6404 | something other than a floating-point instruction. */ |
c65ebc55 JW |
6405 | return 0; |
6406 | } | |
6407 | ||
f2f90c63 RH |
6408 | if (flags.is_and && rws_sum[regno].written_by_and) |
6409 | return 0; | |
6410 | if (flags.is_or && rws_sum[regno].written_by_or) | |
6411 | return 0; | |
6412 | ||
c65ebc55 JW |
6413 | switch (rws_sum[regno].write_count) |
6414 | { | |
6415 | case 0: | |
6416 | /* The register has not been written yet. */ | |
6417 | break; | |
6418 | ||
6419 | case 1: | |
89774469 SE |
6420 | /* The register has been written via a predicate, assume we |
6421 | need a barrier (don't check for complementary regs). */ | |
6422 | need_barrier = 1; | |
c65ebc55 JW |
6423 | break; |
6424 | ||
6425 | case 2: | |
6426 | /* The register has been unconditionally written already. We | |
6427 | need a barrier. */ | |
6428 | need_barrier = 1; | |
6429 | break; | |
6430 | ||
6431 | default: | |
e820471b | 6432 | gcc_unreachable (); |
c65ebc55 JW |
6433 | } |
6434 | } | |
6435 | ||
6436 | return need_barrier; | |
6437 | } | |
6438 | ||
97e242b0 | 6439 | static int |
9c808aad | 6440 | rws_access_reg (rtx reg, struct reg_flags flags, int pred) |
97e242b0 RH |
6441 | { |
6442 | int regno = REGNO (reg); | |
462a99aa | 6443 | int n = REG_NREGS (reg); |
97e242b0 RH |
6444 | |
6445 | if (n == 1) | |
6446 | return rws_access_regno (regno, flags, pred); | |
6447 | else | |
6448 | { | |
6449 | int need_barrier = 0; | |
6450 | while (--n >= 0) | |
6451 | need_barrier |= rws_access_regno (regno + n, flags, pred); | |
6452 | return need_barrier; | |
6453 | } | |
6454 | } | |
6455 | ||
112333d3 BS |
6456 | /* Examine X, which is a SET rtx, and update the flags, the predicate, and |
6457 | the condition, stored in *PFLAGS, *PPRED and *PCOND. */ | |
6458 | ||
6459 | static void | |
c1bc6ca8 | 6460 | update_set_flags (rtx x, struct reg_flags *pflags) |
112333d3 BS |
6461 | { |
6462 | rtx src = SET_SRC (x); | |
6463 | ||
112333d3 BS |
6464 | switch (GET_CODE (src)) |
6465 | { | |
6466 | case CALL: | |
6467 | return; | |
6468 | ||
6469 | case IF_THEN_ELSE: | |
048d0d36 | 6470 | /* There are four cases here: |
c8d3810f RH |
6471 | (1) The destination is (pc), in which case this is a branch, |
6472 | nothing here applies. | |
6473 | (2) The destination is ar.lc, in which case this is a | |
6474 | doloop_end_internal, | |
6475 | (3) The destination is an fp register, in which case this is | |
6476 | an fselect instruction. | |
048d0d36 MK |
6477 | (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case |
6478 | this is a check load. | |
c8d3810f RH |
6479 | In all cases, nothing we do in this function applies. */ |
6480 | return; | |
112333d3 BS |
6481 | |
6482 | default: | |
ec8e098d | 6483 | if (COMPARISON_P (src) |
c8d3810f | 6484 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0)))) |
112333d3 BS |
6485 | /* Set pflags->is_fp to 1 so that we know we're dealing |
6486 | with a floating point comparison when processing the | |
6487 | destination of the SET. */ | |
6488 | pflags->is_fp = 1; | |
6489 | ||
6490 | /* Discover if this is a parallel comparison. We only handle | |
6491 | and.orcm and or.andcm at present, since we must retain a | |
6492 | strict inverse on the predicate pair. */ | |
6493 | else if (GET_CODE (src) == AND) | |
6494 | pflags->is_and = 1; | |
6495 | else if (GET_CODE (src) == IOR) | |
6496 | pflags->is_or = 1; | |
6497 | ||
6498 | break; | |
6499 | } | |
6500 | } | |
6501 | ||
6502 | /* Subroutine of rtx_needs_barrier; this function determines whether the | |
6503 | source of a given SET rtx found in X needs a barrier. FLAGS and PRED | |
6504 | are as in rtx_needs_barrier. COND is an rtx that holds the condition | |
6505 | for this insn. */ | |
9c808aad | 6506 | |
112333d3 | 6507 | static int |
c1bc6ca8 | 6508 | set_src_needs_barrier (rtx x, struct reg_flags flags, int pred) |
112333d3 BS |
6509 | { |
6510 | int need_barrier = 0; | |
6511 | rtx dst; | |
6512 | rtx src = SET_SRC (x); | |
6513 | ||
6514 | if (GET_CODE (src) == CALL) | |
6515 | /* We don't need to worry about the result registers that | |
6516 | get written by subroutine call. */ | |
6517 | return rtx_needs_barrier (src, flags, pred); | |
6518 | else if (SET_DEST (x) == pc_rtx) | |
6519 | { | |
6520 | /* X is a conditional branch. */ | |
6521 | /* ??? This seems redundant, as the caller sets this bit for | |
6522 | all JUMP_INSNs. */ | |
048d0d36 MK |
6523 | if (!ia64_spec_check_src_p (src)) |
6524 | flags.is_branch = 1; | |
112333d3 BS |
6525 | return rtx_needs_barrier (src, flags, pred); |
6526 | } | |
6527 | ||
048d0d36 MK |
6528 | if (ia64_spec_check_src_p (src)) |
6529 | /* Avoid checking one register twice (in condition | |
6530 | and in 'then' section) for ldc pattern. */ | |
6531 | { | |
6532 | gcc_assert (REG_P (XEXP (src, 2))); | |
6533 | need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred); | |
6534 | ||
6535 | /* We process MEM below. */ | |
6536 | src = XEXP (src, 1); | |
6537 | } | |
6538 | ||
6539 | need_barrier |= rtx_needs_barrier (src, flags, pred); | |
112333d3 | 6540 | |
112333d3 BS |
6541 | dst = SET_DEST (x); |
6542 | if (GET_CODE (dst) == ZERO_EXTRACT) | |
6543 | { | |
6544 | need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred); | |
6545 | need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred); | |
112333d3 BS |
6546 | } |
6547 | return need_barrier; | |
6548 | } | |
6549 | ||
b38ba463 ZW |
6550 | /* Handle an access to rtx X of type FLAGS using predicate register |
6551 | PRED. Return 1 if this access creates a dependency with an earlier | |
6552 | instruction in the same group. */ | |
c65ebc55 JW |
6553 | |
6554 | static int | |
9c808aad | 6555 | rtx_needs_barrier (rtx x, struct reg_flags flags, int pred) |
c65ebc55 JW |
6556 | { |
6557 | int i, j; | |
6558 | int is_complemented = 0; | |
6559 | int need_barrier = 0; | |
6560 | const char *format_ptr; | |
6561 | struct reg_flags new_flags; | |
c1bc6ca8 | 6562 | rtx cond; |
c65ebc55 JW |
6563 | |
6564 | if (! x) | |
6565 | return 0; | |
6566 | ||
6567 | new_flags = flags; | |
6568 | ||
6569 | switch (GET_CODE (x)) | |
6570 | { | |
9c808aad | 6571 | case SET: |
c1bc6ca8 JW |
6572 | update_set_flags (x, &new_flags); |
6573 | need_barrier = set_src_needs_barrier (x, new_flags, pred); | |
112333d3 | 6574 | if (GET_CODE (SET_SRC (x)) != CALL) |
c65ebc55 | 6575 | { |
112333d3 BS |
6576 | new_flags.is_write = 1; |
6577 | need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred); | |
c65ebc55 | 6578 | } |
c65ebc55 JW |
6579 | break; |
6580 | ||
6581 | case CALL: | |
6582 | new_flags.is_write = 0; | |
97e242b0 | 6583 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
c65ebc55 JW |
6584 | |
6585 | /* Avoid multiple register writes, in case this is a pattern with | |
e820471b | 6586 | multiple CALL rtx. This avoids a failure in rws_access_reg. */ |
444a356a | 6587 | if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM)) |
c65ebc55 JW |
6588 | { |
6589 | new_flags.is_write = 1; | |
97e242b0 RH |
6590 | need_barrier |= rws_access_regno (REG_RP, new_flags, pred); |
6591 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred); | |
6592 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6593 | } |
6594 | break; | |
6595 | ||
e5bde68a RH |
6596 | case COND_EXEC: |
6597 | /* X is a predicated instruction. */ | |
6598 | ||
6599 | cond = COND_EXEC_TEST (x); | |
e820471b | 6600 | gcc_assert (!pred); |
e5bde68a RH |
6601 | need_barrier = rtx_needs_barrier (cond, flags, 0); |
6602 | ||
6603 | if (GET_CODE (cond) == EQ) | |
6604 | is_complemented = 1; | |
6605 | cond = XEXP (cond, 0); | |
e820471b | 6606 | gcc_assert (GET_CODE (cond) == REG |
c1bc6ca8 | 6607 | && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS); |
e5bde68a RH |
6608 | pred = REGNO (cond); |
6609 | if (is_complemented) | |
6610 | ++pred; | |
6611 | ||
6612 | need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred); | |
6613 | return need_barrier; | |
6614 | ||
c65ebc55 | 6615 | case CLOBBER: |
c65ebc55 | 6616 | case USE: |
c65ebc55 JW |
6617 | /* Clobber & use are for earlier compiler-phases only. */ |
6618 | break; | |
6619 | ||
6620 | case ASM_OPERANDS: | |
6621 | case ASM_INPUT: | |
6622 | /* We always emit stop bits for traditional asms. We emit stop bits | |
6623 | for volatile extended asms if TARGET_VOL_ASM_STOP is true. */ | |
6624 | if (GET_CODE (x) != ASM_OPERANDS | |
6625 | || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP)) | |
6626 | { | |
6627 | /* Avoid writing the register multiple times if we have multiple | |
e820471b | 6628 | asm outputs. This avoids a failure in rws_access_reg. */ |
444a356a | 6629 | if (! rws_insn_test (REG_VOLATILE)) |
c65ebc55 JW |
6630 | { |
6631 | new_flags.is_write = 1; | |
97e242b0 | 6632 | rws_access_regno (REG_VOLATILE, new_flags, pred); |
c65ebc55 JW |
6633 | } |
6634 | return 1; | |
6635 | } | |
6636 | ||
6637 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
1e5f1716 | 6638 | We cannot just fall through here since then we would be confused |
c65ebc55 JW |
6639 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate |
6640 | traditional asms unlike their normal usage. */ | |
6641 | ||
6642 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i) | |
6643 | if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred)) | |
6644 | need_barrier = 1; | |
6645 | break; | |
6646 | ||
6647 | case PARALLEL: | |
6648 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
112333d3 BS |
6649 | { |
6650 | rtx pat = XVECEXP (x, 0, i); | |
051d8245 | 6651 | switch (GET_CODE (pat)) |
112333d3 | 6652 | { |
051d8245 | 6653 | case SET: |
c1bc6ca8 JW |
6654 | update_set_flags (pat, &new_flags); |
6655 | need_barrier |= set_src_needs_barrier (pat, new_flags, pred); | |
051d8245 RH |
6656 | break; |
6657 | ||
6658 | case USE: | |
6659 | case CALL: | |
6660 | case ASM_OPERANDS: | |
93671519 | 6661 | case ASM_INPUT: |
051d8245 RH |
6662 | need_barrier |= rtx_needs_barrier (pat, flags, pred); |
6663 | break; | |
6664 | ||
6665 | case CLOBBER: | |
628162ea JJ |
6666 | if (REG_P (XEXP (pat, 0)) |
6667 | && extract_asm_operands (x) != NULL_RTX | |
6668 | && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM) | |
6669 | { | |
6670 | new_flags.is_write = 1; | |
6671 | need_barrier |= rtx_needs_barrier (XEXP (pat, 0), | |
6672 | new_flags, pred); | |
6673 | new_flags = flags; | |
6674 | } | |
6675 | break; | |
6676 | ||
051d8245 RH |
6677 | case RETURN: |
6678 | break; | |
6679 | ||
6680 | default: | |
6681 | gcc_unreachable (); | |
112333d3 | 6682 | } |
112333d3 BS |
6683 | } |
6684 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
6685 | { | |
6686 | rtx pat = XVECEXP (x, 0, i); | |
6687 | if (GET_CODE (pat) == SET) | |
6688 | { | |
6689 | if (GET_CODE (SET_SRC (pat)) != CALL) | |
6690 | { | |
6691 | new_flags.is_write = 1; | |
6692 | need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags, | |
6693 | pred); | |
6694 | } | |
6695 | } | |
339cb12e | 6696 | else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN) |
112333d3 BS |
6697 | need_barrier |= rtx_needs_barrier (pat, flags, pred); |
6698 | } | |
c65ebc55 JW |
6699 | break; |
6700 | ||
6701 | case SUBREG: | |
077bc924 JM |
6702 | need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred); |
6703 | break; | |
c65ebc55 | 6704 | case REG: |
870f9ec0 RH |
6705 | if (REGNO (x) == AR_UNAT_REGNUM) |
6706 | { | |
6707 | for (i = 0; i < 64; ++i) | |
6708 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred); | |
6709 | } | |
6710 | else | |
6711 | need_barrier = rws_access_reg (x, flags, pred); | |
c65ebc55 JW |
6712 | break; |
6713 | ||
6714 | case MEM: | |
6715 | /* Find the regs used in memory address computation. */ | |
6716 | new_flags.is_write = 0; | |
6717 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6718 | break; | |
6719 | ||
051d8245 | 6720 | case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR: |
c65ebc55 JW |
6721 | case SYMBOL_REF: case LABEL_REF: case CONST: |
6722 | break; | |
6723 | ||
6724 | /* Operators with side-effects. */ | |
6725 | case POST_INC: case POST_DEC: | |
e820471b | 6726 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
c65ebc55 JW |
6727 | |
6728 | new_flags.is_write = 0; | |
97e242b0 | 6729 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 | 6730 | new_flags.is_write = 1; |
97e242b0 | 6731 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6732 | break; |
6733 | ||
6734 | case POST_MODIFY: | |
e820471b | 6735 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
4b983fdc RH |
6736 | |
6737 | new_flags.is_write = 0; | |
97e242b0 | 6738 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6739 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); |
6740 | new_flags.is_write = 1; | |
97e242b0 | 6741 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 JW |
6742 | break; |
6743 | ||
6744 | /* Handle common unary and binary ops for efficiency. */ | |
6745 | case COMPARE: case PLUS: case MINUS: case MULT: case DIV: | |
6746 | case MOD: case UDIV: case UMOD: case AND: case IOR: | |
6747 | case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT: | |
6748 | case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX: | |
6749 | case NE: case EQ: case GE: case GT: case LE: | |
6750 | case LT: case GEU: case GTU: case LEU: case LTU: | |
6751 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6752 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); | |
6753 | break; | |
6754 | ||
6755 | case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND: | |
6756 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: | |
6757 | case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS: | |
c407570a | 6758 | case SQRT: case FFS: case POPCOUNT: |
c65ebc55 JW |
6759 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6760 | break; | |
6761 | ||
051d8245 RH |
6762 | case VEC_SELECT: |
6763 | /* VEC_SELECT's second argument is a PARALLEL with integers that | |
6764 | describe the elements selected. On ia64, those integers are | |
6765 | always constants. Avoid walking the PARALLEL so that we don't | |
e820471b | 6766 | get confused with "normal" parallels and then die. */ |
051d8245 RH |
6767 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6768 | break; | |
6769 | ||
c65ebc55 JW |
6770 | case UNSPEC: |
6771 | switch (XINT (x, 1)) | |
6772 | { | |
7b6e506e RH |
6773 | case UNSPEC_LTOFF_DTPMOD: |
6774 | case UNSPEC_LTOFF_DTPREL: | |
6775 | case UNSPEC_DTPREL: | |
6776 | case UNSPEC_LTOFF_TPREL: | |
6777 | case UNSPEC_TPREL: | |
6778 | case UNSPEC_PRED_REL_MUTEX: | |
6779 | case UNSPEC_PIC_CALL: | |
6780 | case UNSPEC_MF: | |
6781 | case UNSPEC_FETCHADD_ACQ: | |
28875d67 | 6782 | case UNSPEC_FETCHADD_REL: |
7b6e506e RH |
6783 | case UNSPEC_BSP_VALUE: |
6784 | case UNSPEC_FLUSHRS: | |
6785 | case UNSPEC_BUNDLE_SELECTOR: | |
6786 | break; | |
6787 | ||
086c0f96 RH |
6788 | case UNSPEC_GR_SPILL: |
6789 | case UNSPEC_GR_RESTORE: | |
870f9ec0 RH |
6790 | { |
6791 | HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1)); | |
6792 | HOST_WIDE_INT bit = (offset >> 3) & 63; | |
6793 | ||
6794 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
83338d15 | 6795 | new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL); |
870f9ec0 RH |
6796 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit, |
6797 | new_flags, pred); | |
6798 | break; | |
6799 | } | |
9c808aad | 6800 | |
086c0f96 RH |
6801 | case UNSPEC_FR_SPILL: |
6802 | case UNSPEC_FR_RESTORE: | |
c407570a | 6803 | case UNSPEC_GETF_EXP: |
b38ba463 | 6804 | case UNSPEC_SETF_EXP: |
086c0f96 | 6805 | case UNSPEC_ADDP4: |
b38ba463 | 6806 | case UNSPEC_FR_SQRT_RECIP_APPROX: |
07acc7b3 | 6807 | case UNSPEC_FR_SQRT_RECIP_APPROX_RES: |
048d0d36 MK |
6808 | case UNSPEC_LDA: |
6809 | case UNSPEC_LDS: | |
388092d5 | 6810 | case UNSPEC_LDS_A: |
048d0d36 MK |
6811 | case UNSPEC_LDSA: |
6812 | case UNSPEC_CHKACLR: | |
6813 | case UNSPEC_CHKS: | |
6dd12198 SE |
6814 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6815 | break; | |
6816 | ||
086c0f96 | 6817 | case UNSPEC_FR_RECIP_APPROX: |
f526a3c8 | 6818 | case UNSPEC_SHRP: |
046625fa | 6819 | case UNSPEC_COPYSIGN: |
1def9c3f | 6820 | case UNSPEC_FR_RECIP_APPROX_RES: |
655f2eb9 RH |
6821 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6822 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); | |
6823 | break; | |
6824 | ||
086c0f96 | 6825 | case UNSPEC_CMPXCHG_ACQ: |
28875d67 | 6826 | case UNSPEC_CMPXCHG_REL: |
0551c32d RH |
6827 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); |
6828 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred); | |
6829 | break; | |
6830 | ||
c65ebc55 | 6831 | default: |
e820471b | 6832 | gcc_unreachable (); |
c65ebc55 JW |
6833 | } |
6834 | break; | |
6835 | ||
6836 | case UNSPEC_VOLATILE: | |
6837 | switch (XINT (x, 1)) | |
6838 | { | |
086c0f96 | 6839 | case UNSPECV_ALLOC: |
25250265 JW |
6840 | /* Alloc must always be the first instruction of a group. |
6841 | We force this by always returning true. */ | |
6842 | /* ??? We might get better scheduling if we explicitly check for | |
6843 | input/local/output register dependencies, and modify the | |
6844 | scheduler so that alloc is always reordered to the start of | |
6845 | the current group. We could then eliminate all of the | |
6846 | first_instruction code. */ | |
6847 | rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6848 | |
6849 | new_flags.is_write = 1; | |
25250265 JW |
6850 | rws_access_regno (REG_AR_CFM, new_flags, pred); |
6851 | return 1; | |
c65ebc55 | 6852 | |
086c0f96 | 6853 | case UNSPECV_SET_BSP: |
7b84aac0 | 6854 | case UNSPECV_PROBE_STACK_RANGE: |
3b572406 RH |
6855 | need_barrier = 1; |
6856 | break; | |
6857 | ||
086c0f96 RH |
6858 | case UNSPECV_BLOCKAGE: |
6859 | case UNSPECV_INSN_GROUP_BARRIER: | |
6860 | case UNSPECV_BREAK: | |
6861 | case UNSPECV_PSAC_ALL: | |
6862 | case UNSPECV_PSAC_NORMAL: | |
3b572406 | 6863 | return 0; |
0c96007e | 6864 | |
7b84aac0 EB |
6865 | case UNSPECV_PROBE_STACK_ADDRESS: |
6866 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
6867 | break; | |
6868 | ||
c65ebc55 | 6869 | default: |
e820471b | 6870 | gcc_unreachable (); |
c65ebc55 JW |
6871 | } |
6872 | break; | |
6873 | ||
6874 | case RETURN: | |
6875 | new_flags.is_write = 0; | |
97e242b0 RH |
6876 | need_barrier = rws_access_regno (REG_RP, flags, pred); |
6877 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6878 | |
6879 | new_flags.is_write = 1; | |
97e242b0 RH |
6880 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
6881 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6882 | break; |
6883 | ||
6884 | default: | |
6885 | format_ptr = GET_RTX_FORMAT (GET_CODE (x)); | |
6886 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6887 | switch (format_ptr[i]) | |
6888 | { | |
6889 | case '0': /* unused field */ | |
6890 | case 'i': /* integer */ | |
6891 | case 'n': /* note */ | |
6892 | case 'w': /* wide integer */ | |
6893 | case 's': /* pointer to string */ | |
6894 | case 'S': /* optional pointer to string */ | |
6895 | break; | |
6896 | ||
6897 | case 'e': | |
6898 | if (rtx_needs_barrier (XEXP (x, i), flags, pred)) | |
6899 | need_barrier = 1; | |
6900 | break; | |
6901 | ||
6902 | case 'E': | |
6903 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
6904 | if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred)) | |
6905 | need_barrier = 1; | |
6906 | break; | |
6907 | ||
6908 | default: | |
e820471b | 6909 | gcc_unreachable (); |
c65ebc55 | 6910 | } |
2ed4af6f | 6911 | break; |
c65ebc55 JW |
6912 | } |
6913 | return need_barrier; | |
6914 | } | |
6915 | ||
c1bc6ca8 | 6916 | /* Clear out the state for group_barrier_needed at the start of a |
2130b7fb BS |
6917 | sequence of insns. */ |
6918 | ||
6919 | static void | |
9c808aad | 6920 | init_insn_group_barriers (void) |
2130b7fb BS |
6921 | { |
6922 | memset (rws_sum, 0, sizeof (rws_sum)); | |
25250265 | 6923 | first_instruction = 1; |
2130b7fb BS |
6924 | } |
6925 | ||
c1bc6ca8 JW |
6926 | /* Given the current state, determine whether a group barrier (a stop bit) is |
6927 | necessary before INSN. Return nonzero if so. This modifies the state to | |
6928 | include the effects of INSN as a side-effect. */ | |
2130b7fb BS |
6929 | |
6930 | static int | |
647d790d | 6931 | group_barrier_needed (rtx_insn *insn) |
2130b7fb BS |
6932 | { |
6933 | rtx pat; | |
6934 | int need_barrier = 0; | |
6935 | struct reg_flags flags; | |
6936 | ||
6937 | memset (&flags, 0, sizeof (flags)); | |
6938 | switch (GET_CODE (insn)) | |
6939 | { | |
6940 | case NOTE: | |
b5b8b0ac | 6941 | case DEBUG_INSN: |
2130b7fb BS |
6942 | break; |
6943 | ||
6944 | case BARRIER: | |
6945 | /* A barrier doesn't imply an instruction group boundary. */ | |
6946 | break; | |
6947 | ||
6948 | case CODE_LABEL: | |
6949 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6950 | return 1; | |
6951 | ||
6952 | case CALL_INSN: | |
6953 | flags.is_branch = 1; | |
6954 | flags.is_sibcall = SIBLING_CALL_P (insn); | |
6955 | memset (rws_insn, 0, sizeof (rws_insn)); | |
f12f25a7 RH |
6956 | |
6957 | /* Don't bundle a call following another call. */ | |
b64925dc | 6958 | if ((pat = prev_active_insn (insn)) && CALL_P (pat)) |
f12f25a7 RH |
6959 | { |
6960 | need_barrier = 1; | |
6961 | break; | |
6962 | } | |
6963 | ||
2130b7fb BS |
6964 | need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0); |
6965 | break; | |
6966 | ||
6967 | case JUMP_INSN: | |
048d0d36 MK |
6968 | if (!ia64_spec_check_p (insn)) |
6969 | flags.is_branch = 1; | |
f12f25a7 RH |
6970 | |
6971 | /* Don't bundle a jump following a call. */ | |
b64925dc | 6972 | if ((pat = prev_active_insn (insn)) && CALL_P (pat)) |
f12f25a7 RH |
6973 | { |
6974 | need_barrier = 1; | |
6975 | break; | |
6976 | } | |
5efb1046 | 6977 | /* FALLTHRU */ |
2130b7fb BS |
6978 | |
6979 | case INSN: | |
6980 | if (GET_CODE (PATTERN (insn)) == USE | |
6981 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
6982 | /* Don't care about USE and CLOBBER "insns"---those are used to | |
6983 | indicate to the optimizer that it shouldn't get rid of | |
6984 | certain operations. */ | |
6985 | break; | |
6986 | ||
6987 | pat = PATTERN (insn); | |
6988 | ||
6989 | /* Ug. Hack hacks hacked elsewhere. */ | |
6990 | switch (recog_memoized (insn)) | |
6991 | { | |
6992 | /* We play dependency tricks with the epilogue in order | |
6993 | to get proper schedules. Undo this for dv analysis. */ | |
6994 | case CODE_FOR_epilogue_deallocate_stack: | |
bdbe5b8d | 6995 | case CODE_FOR_prologue_allocate_stack: |
2130b7fb BS |
6996 | pat = XVECEXP (pat, 0, 0); |
6997 | break; | |
6998 | ||
6999 | /* The pattern we use for br.cloop confuses the code above. | |
7000 | The second element of the vector is representative. */ | |
7001 | case CODE_FOR_doloop_end_internal: | |
7002 | pat = XVECEXP (pat, 0, 1); | |
7003 | break; | |
7004 | ||
7005 | /* Doesn't generate code. */ | |
7006 | case CODE_FOR_pred_rel_mutex: | |
d0e82870 | 7007 | case CODE_FOR_prologue_use: |
2130b7fb BS |
7008 | return 0; |
7009 | ||
7010 | default: | |
7011 | break; | |
7012 | } | |
7013 | ||
7014 | memset (rws_insn, 0, sizeof (rws_insn)); | |
7015 | need_barrier = rtx_needs_barrier (pat, flags, 0); | |
7016 | ||
7017 | /* Check to see if the previous instruction was a volatile | |
7018 | asm. */ | |
7019 | if (! need_barrier) | |
7020 | need_barrier = rws_access_regno (REG_VOLATILE, flags, 0); | |
388092d5 | 7021 | |
2130b7fb BS |
7022 | break; |
7023 | ||
7024 | default: | |
e820471b | 7025 | gcc_unreachable (); |
2130b7fb | 7026 | } |
25250265 | 7027 | |
7b84aac0 | 7028 | if (first_instruction && important_for_bundling_p (insn)) |
25250265 JW |
7029 | { |
7030 | need_barrier = 0; | |
7031 | first_instruction = 0; | |
7032 | } | |
7033 | ||
2130b7fb BS |
7034 | return need_barrier; |
7035 | } | |
7036 | ||
c1bc6ca8 | 7037 | /* Like group_barrier_needed, but do not clobber the current state. */ |
2130b7fb BS |
7038 | |
7039 | static int | |
647d790d | 7040 | safe_group_barrier_needed (rtx_insn *insn) |
2130b7fb | 7041 | { |
25250265 | 7042 | int saved_first_instruction; |
2130b7fb | 7043 | int t; |
25250265 | 7044 | |
25250265 | 7045 | saved_first_instruction = first_instruction; |
444a356a | 7046 | in_safe_group_barrier = 1; |
25250265 | 7047 | |
c1bc6ca8 | 7048 | t = group_barrier_needed (insn); |
25250265 | 7049 | |
25250265 | 7050 | first_instruction = saved_first_instruction; |
444a356a | 7051 | in_safe_group_barrier = 0; |
25250265 | 7052 | |
2130b7fb BS |
7053 | return t; |
7054 | } | |
7055 | ||
18dbd950 RS |
7056 | /* Scan the current function and insert stop bits as necessary to |
7057 | eliminate dependencies. This function assumes that a final | |
7058 | instruction scheduling pass has been run which has already | |
7059 | inserted most of the necessary stop bits. This function only | |
7060 | inserts new ones at basic block boundaries, since these are | |
7061 | invisible to the scheduler. */ | |
2130b7fb BS |
7062 | |
7063 | static void | |
9c808aad | 7064 | emit_insn_group_barriers (FILE *dump) |
2130b7fb | 7065 | { |
dd3d2b35 DM |
7066 | rtx_insn *insn; |
7067 | rtx_insn *last_label = 0; | |
2130b7fb BS |
7068 | int insns_since_last_label = 0; |
7069 | ||
7070 | init_insn_group_barriers (); | |
7071 | ||
18dbd950 | 7072 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2130b7fb | 7073 | { |
b64925dc | 7074 | if (LABEL_P (insn)) |
2130b7fb BS |
7075 | { |
7076 | if (insns_since_last_label) | |
7077 | last_label = insn; | |
7078 | insns_since_last_label = 0; | |
7079 | } | |
b64925dc | 7080 | else if (NOTE_P (insn) |
a38e7aa5 | 7081 | && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK) |
2130b7fb BS |
7082 | { |
7083 | if (insns_since_last_label) | |
7084 | last_label = insn; | |
7085 | insns_since_last_label = 0; | |
7086 | } | |
b64925dc | 7087 | else if (NONJUMP_INSN_P (insn) |
2130b7fb | 7088 | && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE |
086c0f96 | 7089 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) |
2130b7fb BS |
7090 | { |
7091 | init_insn_group_barriers (); | |
7092 | last_label = 0; | |
7093 | } | |
b5b8b0ac | 7094 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb BS |
7095 | { |
7096 | insns_since_last_label = 1; | |
7097 | ||
c1bc6ca8 | 7098 | if (group_barrier_needed (insn)) |
2130b7fb BS |
7099 | { |
7100 | if (last_label) | |
7101 | { | |
7102 | if (dump) | |
7103 | fprintf (dump, "Emitting stop before label %d\n", | |
7104 | INSN_UID (last_label)); | |
7105 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label); | |
7106 | insn = last_label; | |
112333d3 BS |
7107 | |
7108 | init_insn_group_barriers (); | |
7109 | last_label = 0; | |
2130b7fb | 7110 | } |
2130b7fb BS |
7111 | } |
7112 | } | |
7113 | } | |
7114 | } | |
f4d578da BS |
7115 | |
7116 | /* Like emit_insn_group_barriers, but run if no final scheduling pass was run. | |
7117 | This function has to emit all necessary group barriers. */ | |
7118 | ||
7119 | static void | |
9c808aad | 7120 | emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
f4d578da | 7121 | { |
dd3d2b35 | 7122 | rtx_insn *insn; |
f4d578da BS |
7123 | |
7124 | init_insn_group_barriers (); | |
7125 | ||
18dbd950 | 7126 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f4d578da | 7127 | { |
b64925dc | 7128 | if (BARRIER_P (insn)) |
bd7b9a0f | 7129 | { |
dd3d2b35 | 7130 | rtx_insn *last = prev_active_insn (insn); |
bd7b9a0f RH |
7131 | |
7132 | if (! last) | |
7133 | continue; | |
34f0d87a | 7134 | if (JUMP_TABLE_DATA_P (last)) |
bd7b9a0f RH |
7135 | last = prev_active_insn (last); |
7136 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
7137 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
7138 | ||
7139 | init_insn_group_barriers (); | |
7140 | } | |
b5b8b0ac | 7141 | else if (NONDEBUG_INSN_P (insn)) |
f4d578da | 7142 | { |
bd7b9a0f RH |
7143 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
7144 | init_insn_group_barriers (); | |
c1bc6ca8 | 7145 | else if (group_barrier_needed (insn)) |
f4d578da BS |
7146 | { |
7147 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); | |
7148 | init_insn_group_barriers (); | |
c1bc6ca8 | 7149 | group_barrier_needed (insn); |
f4d578da BS |
7150 | } |
7151 | } | |
7152 | } | |
7153 | } | |
30028c85 | 7154 | |
2130b7fb | 7155 | \f |
2130b7fb | 7156 | |
30028c85 | 7157 | /* Instruction scheduling support. */ |
2130b7fb BS |
7158 | |
7159 | #define NR_BUNDLES 10 | |
7160 | ||
30028c85 | 7161 | /* A list of names of all available bundles. */ |
2130b7fb | 7162 | |
30028c85 | 7163 | static const char *bundle_name [NR_BUNDLES] = |
2130b7fb | 7164 | { |
30028c85 VM |
7165 | ".mii", |
7166 | ".mmi", | |
7167 | ".mfi", | |
7168 | ".mmf", | |
2130b7fb | 7169 | #if NR_BUNDLES == 10 |
30028c85 VM |
7170 | ".bbb", |
7171 | ".mbb", | |
2130b7fb | 7172 | #endif |
30028c85 VM |
7173 | ".mib", |
7174 | ".mmb", | |
7175 | ".mfb", | |
7176 | ".mlx" | |
2130b7fb BS |
7177 | }; |
7178 | ||
30028c85 | 7179 | /* Nonzero if we should insert stop bits into the schedule. */ |
2130b7fb | 7180 | |
30028c85 | 7181 | int ia64_final_schedule = 0; |
2130b7fb | 7182 | |
35fd3193 | 7183 | /* Codes of the corresponding queried units: */ |
2130b7fb | 7184 | |
30028c85 VM |
7185 | static int _0mii_, _0mmi_, _0mfi_, _0mmf_; |
7186 | static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_; | |
2130b7fb | 7187 | |
30028c85 VM |
7188 | static int _1mii_, _1mmi_, _1mfi_, _1mmf_; |
7189 | static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_; | |
2130b7fb | 7190 | |
30028c85 VM |
7191 | static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6; |
7192 | ||
7193 | /* The following variable value is an insn group barrier. */ | |
7194 | ||
dd3d2b35 | 7195 | static rtx_insn *dfa_stop_insn; |
30028c85 VM |
7196 | |
7197 | /* The following variable value is the last issued insn. */ | |
7198 | ||
b32d5189 | 7199 | static rtx_insn *last_scheduled_insn; |
30028c85 | 7200 | |
30028c85 VM |
7201 | /* The following variable value is pointer to a DFA state used as |
7202 | temporary variable. */ | |
7203 | ||
7204 | static state_t temp_dfa_state = NULL; | |
7205 | ||
7206 | /* The following variable value is DFA state after issuing the last | |
7207 | insn. */ | |
7208 | ||
7209 | static state_t prev_cycle_state = NULL; | |
7210 | ||
7211 | /* The following array element values are TRUE if the corresponding | |
9e4f94de | 7212 | insn requires to add stop bits before it. */ |
30028c85 | 7213 | |
048d0d36 MK |
7214 | static char *stops_p = NULL; |
7215 | ||
30028c85 VM |
7216 | /* The following variable is used to set up the mentioned above array. */ |
7217 | ||
7218 | static int stop_before_p = 0; | |
7219 | ||
7220 | /* The following variable value is length of the arrays `clocks' and | |
7221 | `add_cycles'. */ | |
7222 | ||
7223 | static int clocks_length; | |
7224 | ||
048d0d36 MK |
7225 | /* The following variable value is number of data speculations in progress. */ |
7226 | static int pending_data_specs = 0; | |
7227 | ||
388092d5 AB |
7228 | /* Number of memory references on current and three future processor cycles. */ |
7229 | static char mem_ops_in_group[4]; | |
7230 | ||
7231 | /* Number of current processor cycle (from scheduler's point of view). */ | |
7232 | static int current_cycle; | |
7233 | ||
647d790d | 7234 | static rtx ia64_single_set (rtx_insn *); |
017fdefe | 7235 | static void ia64_emit_insn_before (rtx, rtx_insn *); |
2130b7fb BS |
7236 | |
7237 | /* Map a bundle number to its pseudo-op. */ | |
7238 | ||
7239 | const char * | |
9c808aad | 7240 | get_bundle_name (int b) |
2130b7fb | 7241 | { |
30028c85 | 7242 | return bundle_name[b]; |
2130b7fb BS |
7243 | } |
7244 | ||
2130b7fb BS |
7245 | |
7246 | /* Return the maximum number of instructions a cpu can issue. */ | |
7247 | ||
c237e94a | 7248 | static int |
9c808aad | 7249 | ia64_issue_rate (void) |
2130b7fb BS |
7250 | { |
7251 | return 6; | |
7252 | } | |
7253 | ||
7254 | /* Helper function - like single_set, but look inside COND_EXEC. */ | |
7255 | ||
7256 | static rtx | |
647d790d | 7257 | ia64_single_set (rtx_insn *insn) |
2130b7fb | 7258 | { |
30fa7e33 | 7259 | rtx x = PATTERN (insn), ret; |
2130b7fb BS |
7260 | if (GET_CODE (x) == COND_EXEC) |
7261 | x = COND_EXEC_CODE (x); | |
7262 | if (GET_CODE (x) == SET) | |
7263 | return x; | |
bdbe5b8d RH |
7264 | |
7265 | /* Special case here prologue_allocate_stack and epilogue_deallocate_stack. | |
7266 | Although they are not classical single set, the second set is there just | |
7267 | to protect it from moving past FP-relative stack accesses. */ | |
7268 | switch (recog_memoized (insn)) | |
30fa7e33 | 7269 | { |
bdbe5b8d | 7270 | case CODE_FOR_prologue_allocate_stack: |
9eb8c09f | 7271 | case CODE_FOR_prologue_allocate_stack_pr: |
bdbe5b8d | 7272 | case CODE_FOR_epilogue_deallocate_stack: |
9eb8c09f | 7273 | case CODE_FOR_epilogue_deallocate_stack_pr: |
bdbe5b8d RH |
7274 | ret = XVECEXP (x, 0, 0); |
7275 | break; | |
7276 | ||
7277 | default: | |
7278 | ret = single_set_2 (insn, x); | |
7279 | break; | |
30fa7e33 | 7280 | } |
bdbe5b8d | 7281 | |
30fa7e33 | 7282 | return ret; |
2130b7fb BS |
7283 | } |
7284 | ||
388092d5 AB |
7285 | /* Adjust the cost of a scheduling dependency. |
7286 | Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN. | |
7287 | COST is the current cost, DW is dependency weakness. */ | |
c237e94a | 7288 | static int |
b505225b TS |
7289 | ia64_adjust_cost (rtx_insn *insn, int dep_type1, rtx_insn *dep_insn, |
7290 | int cost, dw_t dw) | |
2130b7fb | 7291 | { |
388092d5 | 7292 | enum reg_note dep_type = (enum reg_note) dep_type1; |
2130b7fb BS |
7293 | enum attr_itanium_class dep_class; |
7294 | enum attr_itanium_class insn_class; | |
2130b7fb | 7295 | |
2130b7fb | 7296 | insn_class = ia64_safe_itanium_class (insn); |
30028c85 | 7297 | dep_class = ia64_safe_itanium_class (dep_insn); |
388092d5 AB |
7298 | |
7299 | /* Treat true memory dependencies separately. Ignore apparent true | |
7300 | dependence between store and call (call has a MEM inside a SYMBOL_REF). */ | |
7301 | if (dep_type == REG_DEP_TRUE | |
7302 | && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF) | |
7303 | && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL)) | |
7304 | return 0; | |
7305 | ||
7306 | if (dw == MIN_DEP_WEAK) | |
7307 | /* Store and load are likely to alias, use higher cost to avoid stall. */ | |
7308 | return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST); | |
7309 | else if (dw > MIN_DEP_WEAK) | |
7310 | { | |
7311 | /* Store and load are less likely to alias. */ | |
7312 | if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF) | |
7313 | /* Assume there will be no cache conflict for floating-point data. | |
7314 | For integer data, L1 conflict penalty is huge (17 cycles), so we | |
7315 | never assume it will not cause a conflict. */ | |
7316 | return 0; | |
7317 | else | |
7318 | return cost; | |
7319 | } | |
7320 | ||
7321 | if (dep_type != REG_DEP_OUTPUT) | |
7322 | return cost; | |
7323 | ||
30028c85 VM |
7324 | if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF |
7325 | || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF) | |
2130b7fb BS |
7326 | return 0; |
7327 | ||
2130b7fb BS |
7328 | return cost; |
7329 | } | |
7330 | ||
14d118d6 DM |
7331 | /* Like emit_insn_before, but skip cycle_display notes. |
7332 | ??? When cycle display notes are implemented, update this. */ | |
7333 | ||
7334 | static void | |
d8485bdb | 7335 | ia64_emit_insn_before (rtx insn, rtx_insn *before) |
14d118d6 DM |
7336 | { |
7337 | emit_insn_before (insn, before); | |
7338 | } | |
7339 | ||
30028c85 VM |
7340 | /* The following function marks insns who produce addresses for load |
7341 | and store insns. Such insns will be placed into M slots because it | |
7342 | decrease latency time for Itanium1 (see function | |
7343 | `ia64_produce_address_p' and the DFA descriptions). */ | |
2130b7fb BS |
7344 | |
7345 | static void | |
ce1ce33a | 7346 | ia64_dependencies_evaluation_hook (rtx_insn *head, rtx_insn *tail) |
2130b7fb | 7347 | { |
ce1ce33a | 7348 | rtx_insn *insn, *next, *next_tail; |
9c808aad | 7349 | |
f12b785d RH |
7350 | /* Before reload, which_alternative is not set, which means that |
7351 | ia64_safe_itanium_class will produce wrong results for (at least) | |
7352 | move instructions. */ | |
7353 | if (!reload_completed) | |
7354 | return; | |
7355 | ||
30028c85 VM |
7356 | next_tail = NEXT_INSN (tail); |
7357 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7358 | if (INSN_P (insn)) | |
7359 | insn->call = 0; | |
7360 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7361 | if (INSN_P (insn) | |
7362 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU) | |
7363 | { | |
e2f6ff94 MK |
7364 | sd_iterator_def sd_it; |
7365 | dep_t dep; | |
7366 | bool has_mem_op_consumer_p = false; | |
b198261f | 7367 | |
e2f6ff94 | 7368 | FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) |
30028c85 | 7369 | { |
a71aef0b JB |
7370 | enum attr_itanium_class c; |
7371 | ||
e2f6ff94 | 7372 | if (DEP_TYPE (dep) != REG_DEP_TRUE) |
f12b785d | 7373 | continue; |
b198261f | 7374 | |
e2f6ff94 | 7375 | next = DEP_CON (dep); |
a71aef0b JB |
7376 | c = ia64_safe_itanium_class (next); |
7377 | if ((c == ITANIUM_CLASS_ST | |
7378 | || c == ITANIUM_CLASS_STF) | |
30028c85 | 7379 | && ia64_st_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7380 | { |
7381 | has_mem_op_consumer_p = true; | |
7382 | break; | |
7383 | } | |
a71aef0b JB |
7384 | else if ((c == ITANIUM_CLASS_LD |
7385 | || c == ITANIUM_CLASS_FLD | |
7386 | || c == ITANIUM_CLASS_FLDP) | |
30028c85 | 7387 | && ia64_ld_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7388 | { |
7389 | has_mem_op_consumer_p = true; | |
7390 | break; | |
7391 | } | |
30028c85 | 7392 | } |
e2f6ff94 MK |
7393 | |
7394 | insn->call = has_mem_op_consumer_p; | |
30028c85 VM |
7395 | } |
7396 | } | |
2130b7fb | 7397 | |
30028c85 | 7398 | /* We're beginning a new block. Initialize data structures as necessary. */ |
2130b7fb | 7399 | |
30028c85 | 7400 | static void |
9c808aad AJ |
7401 | ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
7402 | int sched_verbose ATTRIBUTE_UNUSED, | |
7403 | int max_ready ATTRIBUTE_UNUSED) | |
30028c85 | 7404 | { |
e28c2052 MM |
7405 | if (flag_checking && !sel_sched_p () && reload_completed) |
7406 | { | |
7407 | for (rtx_insn *insn = NEXT_INSN (current_sched_info->prev_head); | |
7408 | insn != current_sched_info->next_tail; | |
7409 | insn = NEXT_INSN (insn)) | |
7410 | gcc_assert (!SCHED_GROUP_P (insn)); | |
7411 | } | |
b32d5189 | 7412 | last_scheduled_insn = NULL; |
30028c85 | 7413 | init_insn_group_barriers (); |
388092d5 AB |
7414 | |
7415 | current_cycle = 0; | |
7416 | memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
2130b7fb BS |
7417 | } |
7418 | ||
048d0d36 MK |
7419 | /* We're beginning a scheduling pass. Check assertion. */ |
7420 | ||
7421 | static void | |
7422 | ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, | |
7423 | int sched_verbose ATTRIBUTE_UNUSED, | |
7424 | int max_ready ATTRIBUTE_UNUSED) | |
7425 | { | |
388092d5 | 7426 | gcc_assert (pending_data_specs == 0); |
048d0d36 MK |
7427 | } |
7428 | ||
7429 | /* Scheduling pass is now finished. Free/reset static variable. */ | |
7430 | static void | |
7431 | ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
7432 | int sched_verbose ATTRIBUTE_UNUSED) | |
7433 | { | |
388092d5 AB |
7434 | gcc_assert (pending_data_specs == 0); |
7435 | } | |
7436 | ||
7437 | /* Return TRUE if INSN is a load (either normal or speculative, but not a | |
7438 | speculation check), FALSE otherwise. */ | |
7439 | static bool | |
647d790d | 7440 | is_load_p (rtx_insn *insn) |
388092d5 AB |
7441 | { |
7442 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7443 | ||
7444 | return | |
7445 | ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD) | |
7446 | && get_attr_check_load (insn) == CHECK_LOAD_NO); | |
7447 | } | |
7448 | ||
7449 | /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array | |
7450 | (taking account for 3-cycle cache reference postponing for stores: Intel | |
7451 | Itanium 2 Reference Manual for Software Development and Optimization, | |
7452 | 6.7.3.1). */ | |
7453 | static void | |
647d790d | 7454 | record_memory_reference (rtx_insn *insn) |
388092d5 AB |
7455 | { |
7456 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7457 | ||
7458 | switch (insn_class) { | |
7459 | case ITANIUM_CLASS_FLD: | |
7460 | case ITANIUM_CLASS_LD: | |
7461 | mem_ops_in_group[current_cycle % 4]++; | |
7462 | break; | |
7463 | case ITANIUM_CLASS_STF: | |
7464 | case ITANIUM_CLASS_ST: | |
7465 | mem_ops_in_group[(current_cycle + 3) % 4]++; | |
7466 | break; | |
7467 | default:; | |
7468 | } | |
048d0d36 MK |
7469 | } |
7470 | ||
30028c85 VM |
7471 | /* We are about to being issuing insns for this clock cycle. |
7472 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7473 | |
30028c85 | 7474 | static int |
ce1ce33a | 7475 | ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, |
388092d5 | 7476 | int *pn_ready, int clock_var, |
9c808aad | 7477 | int reorder_type) |
2130b7fb | 7478 | { |
30028c85 VM |
7479 | int n_asms; |
7480 | int n_ready = *pn_ready; | |
ce1ce33a DM |
7481 | rtx_insn **e_ready = ready + n_ready; |
7482 | rtx_insn **insnp; | |
2130b7fb | 7483 | |
30028c85 VM |
7484 | if (sched_verbose) |
7485 | fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type); | |
2130b7fb | 7486 | |
30028c85 | 7487 | if (reorder_type == 0) |
2130b7fb | 7488 | { |
30028c85 VM |
7489 | /* First, move all USEs, CLOBBERs and other crud out of the way. */ |
7490 | n_asms = 0; | |
7491 | for (insnp = ready; insnp < e_ready; insnp++) | |
7492 | if (insnp < e_ready) | |
7493 | { | |
ce1ce33a | 7494 | rtx_insn *insn = *insnp; |
30028c85 VM |
7495 | enum attr_type t = ia64_safe_type (insn); |
7496 | if (t == TYPE_UNKNOWN) | |
7497 | { | |
7498 | if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
7499 | || asm_noperands (PATTERN (insn)) >= 0) | |
7500 | { | |
ce1ce33a | 7501 | rtx_insn *lowest = ready[n_asms]; |
30028c85 VM |
7502 | ready[n_asms] = insn; |
7503 | *insnp = lowest; | |
7504 | n_asms++; | |
7505 | } | |
7506 | else | |
7507 | { | |
ce1ce33a | 7508 | rtx_insn *highest = ready[n_ready - 1]; |
30028c85 VM |
7509 | ready[n_ready - 1] = insn; |
7510 | *insnp = highest; | |
7511 | return 1; | |
7512 | } | |
7513 | } | |
7514 | } | |
98d2b17e | 7515 | |
30028c85 | 7516 | if (n_asms < n_ready) |
98d2b17e | 7517 | { |
30028c85 VM |
7518 | /* Some normal insns to process. Skip the asms. */ |
7519 | ready += n_asms; | |
7520 | n_ready -= n_asms; | |
98d2b17e | 7521 | } |
30028c85 VM |
7522 | else if (n_ready > 0) |
7523 | return 1; | |
2130b7fb BS |
7524 | } |
7525 | ||
30028c85 | 7526 | if (ia64_final_schedule) |
2130b7fb | 7527 | { |
30028c85 VM |
7528 | int deleted = 0; |
7529 | int nr_need_stop = 0; | |
7530 | ||
7531 | for (insnp = ready; insnp < e_ready; insnp++) | |
c1bc6ca8 | 7532 | if (safe_group_barrier_needed (*insnp)) |
30028c85 | 7533 | nr_need_stop++; |
9c808aad | 7534 | |
30028c85 VM |
7535 | if (reorder_type == 1 && n_ready == nr_need_stop) |
7536 | return 0; | |
7537 | if (reorder_type == 0) | |
7538 | return 1; | |
7539 | insnp = e_ready; | |
7540 | /* Move down everything that needs a stop bit, preserving | |
7541 | relative order. */ | |
7542 | while (insnp-- > ready + deleted) | |
7543 | while (insnp >= ready + deleted) | |
7544 | { | |
ce1ce33a | 7545 | rtx_insn *insn = *insnp; |
c1bc6ca8 | 7546 | if (! safe_group_barrier_needed (insn)) |
30028c85 VM |
7547 | break; |
7548 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7549 | *ready = insn; | |
7550 | deleted++; | |
7551 | } | |
7552 | n_ready -= deleted; | |
7553 | ready += deleted; | |
2130b7fb | 7554 | } |
2130b7fb | 7555 | |
388092d5 AB |
7556 | current_cycle = clock_var; |
7557 | if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns) | |
7558 | { | |
7559 | int moved = 0; | |
7560 | ||
7561 | insnp = e_ready; | |
7562 | /* Move down loads/stores, preserving relative order. */ | |
7563 | while (insnp-- > ready + moved) | |
7564 | while (insnp >= ready + moved) | |
7565 | { | |
ce1ce33a | 7566 | rtx_insn *insn = *insnp; |
388092d5 AB |
7567 | if (! is_load_p (insn)) |
7568 | break; | |
7569 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7570 | *ready = insn; | |
7571 | moved++; | |
7572 | } | |
7573 | n_ready -= moved; | |
7574 | ready += moved; | |
7575 | } | |
7576 | ||
30028c85 | 7577 | return 1; |
2130b7fb | 7578 | } |
6b6c1201 | 7579 | |
30028c85 VM |
7580 | /* We are about to being issuing insns for this clock cycle. Override |
7581 | the default sort algorithm to better slot instructions. */ | |
c65ebc55 | 7582 | |
30028c85 | 7583 | static int |
ce1ce33a DM |
7584 | ia64_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, |
7585 | int *pn_ready, int clock_var) | |
2130b7fb | 7586 | { |
30028c85 VM |
7587 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, |
7588 | pn_ready, clock_var, 0); | |
2130b7fb BS |
7589 | } |
7590 | ||
30028c85 VM |
7591 | /* Like ia64_sched_reorder, but called after issuing each insn. |
7592 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7593 | |
30028c85 | 7594 | static int |
9c808aad | 7595 | ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED, |
ce1ce33a | 7596 | int sched_verbose ATTRIBUTE_UNUSED, rtx_insn **ready, |
9c808aad | 7597 | int *pn_ready, int clock_var) |
30028c85 | 7598 | { |
30028c85 VM |
7599 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready, |
7600 | clock_var, 1); | |
2130b7fb BS |
7601 | } |
7602 | ||
30028c85 VM |
7603 | /* We are about to issue INSN. Return the number of insns left on the |
7604 | ready queue that can be issued this cycle. */ | |
2130b7fb | 7605 | |
30028c85 | 7606 | static int |
9c808aad AJ |
7607 | ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED, |
7608 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 7609 | rtx_insn *insn, |
9c808aad | 7610 | int can_issue_more ATTRIBUTE_UNUSED) |
2130b7fb | 7611 | { |
388092d5 | 7612 | if (sched_deps_info->generate_spec_deps && !sel_sched_p ()) |
048d0d36 | 7613 | /* Modulo scheduling does not extend h_i_d when emitting |
388092d5 | 7614 | new instructions. Don't use h_i_d, if we don't have to. */ |
048d0d36 MK |
7615 | { |
7616 | if (DONE_SPEC (insn) & BEGIN_DATA) | |
7617 | pending_data_specs++; | |
7618 | if (CHECK_SPEC (insn) & BEGIN_DATA) | |
7619 | pending_data_specs--; | |
7620 | } | |
7621 | ||
b5b8b0ac AO |
7622 | if (DEBUG_INSN_P (insn)) |
7623 | return 1; | |
7624 | ||
30028c85 VM |
7625 | last_scheduled_insn = insn; |
7626 | memcpy (prev_cycle_state, curr_state, dfa_state_size); | |
7627 | if (reload_completed) | |
2130b7fb | 7628 | { |
c1bc6ca8 | 7629 | int needed = group_barrier_needed (insn); |
e820471b NS |
7630 | |
7631 | gcc_assert (!needed); | |
b64925dc | 7632 | if (CALL_P (insn)) |
30028c85 VM |
7633 | init_insn_group_barriers (); |
7634 | stops_p [INSN_UID (insn)] = stop_before_p; | |
7635 | stop_before_p = 0; | |
388092d5 AB |
7636 | |
7637 | record_memory_reference (insn); | |
2130b7fb | 7638 | } |
30028c85 VM |
7639 | return 1; |
7640 | } | |
c65ebc55 | 7641 | |
4960a0cb | 7642 | /* We are choosing insn from the ready queue. Return zero if INSN |
30028c85 | 7643 | can be chosen. */ |
c65ebc55 | 7644 | |
30028c85 | 7645 | static int |
ac44248e | 7646 | ia64_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *insn, int ready_index) |
30028c85 | 7647 | { |
388092d5 | 7648 | gcc_assert (insn && INSN_P (insn)); |
048d0d36 | 7649 | |
4960a0cb MK |
7650 | /* Size of ALAT is 32. As far as we perform conservative |
7651 | data speculation, we keep ALAT half-empty. */ | |
31815ed7 | 7652 | if (pending_data_specs >= 16 && (TODO_SPEC (insn) & BEGIN_DATA)) |
4960a0cb | 7653 | return ready_index == 0 ? -1 : 1; |
048d0d36 | 7654 | |
4960a0cb MK |
7655 | if (ready_index == 0) |
7656 | return 0; | |
7657 | ||
7658 | if ((!reload_completed | |
7659 | || !safe_group_barrier_needed (insn)) | |
7660 | && (!mflag_sched_mem_insns_hard_limit | |
7661 | || !is_load_p (insn) | |
7662 | || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns)) | |
7663 | return 0; | |
676cad4d MK |
7664 | |
7665 | return 1; | |
2130b7fb BS |
7666 | } |
7667 | ||
30028c85 VM |
7668 | /* The following variable value is pseudo-insn used by the DFA insn |
7669 | scheduler to change the DFA state when the simulated clock is | |
7670 | increased. */ | |
2130b7fb | 7671 | |
dd3d2b35 | 7672 | static rtx_insn *dfa_pre_cycle_insn; |
2130b7fb | 7673 | |
388092d5 AB |
7674 | /* Returns 1 when a meaningful insn was scheduled between the last group |
7675 | barrier and LAST. */ | |
7676 | static int | |
b32d5189 | 7677 | scheduled_good_insn (rtx_insn *last) |
388092d5 AB |
7678 | { |
7679 | if (last && recog_memoized (last) >= 0) | |
7680 | return 1; | |
7681 | ||
7682 | for ( ; | |
7683 | last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last) | |
7684 | && !stops_p[INSN_UID (last)]; | |
7685 | last = PREV_INSN (last)) | |
7686 | /* We could hit a NOTE_INSN_DELETED here which is actually outside | |
7687 | the ebb we're scheduling. */ | |
7688 | if (INSN_P (last) && recog_memoized (last) >= 0) | |
7689 | return 1; | |
7690 | ||
7691 | return 0; | |
7692 | } | |
7693 | ||
1e5f1716 | 7694 | /* We are about to being issuing INSN. Return nonzero if we cannot |
30028c85 VM |
7695 | issue it on given cycle CLOCK and return zero if we should not sort |
7696 | the ready queue on the next clock start. */ | |
2130b7fb BS |
7697 | |
7698 | static int | |
ac44248e | 7699 | ia64_dfa_new_cycle (FILE *dump, int verbose, rtx_insn *insn, int last_clock, |
9c808aad | 7700 | int clock, int *sort_p) |
2130b7fb | 7701 | { |
e820471b | 7702 | gcc_assert (insn && INSN_P (insn)); |
b5b8b0ac AO |
7703 | |
7704 | if (DEBUG_INSN_P (insn)) | |
7705 | return 0; | |
7706 | ||
388092d5 AB |
7707 | /* When a group barrier is needed for insn, last_scheduled_insn |
7708 | should be set. */ | |
7709 | gcc_assert (!(reload_completed && safe_group_barrier_needed (insn)) | |
7710 | || last_scheduled_insn); | |
7711 | ||
7712 | if ((reload_completed | |
7713 | && (safe_group_barrier_needed (insn) | |
7714 | || (mflag_sched_stop_bits_after_every_cycle | |
7715 | && last_clock != clock | |
7716 | && last_scheduled_insn | |
7717 | && scheduled_good_insn (last_scheduled_insn)))) | |
30028c85 | 7718 | || (last_scheduled_insn |
b64925dc | 7719 | && (CALL_P (last_scheduled_insn) |
7b84aac0 | 7720 | || unknown_for_bundling_p (last_scheduled_insn)))) |
2130b7fb | 7721 | { |
30028c85 | 7722 | init_insn_group_barriers (); |
388092d5 | 7723 | |
30028c85 VM |
7724 | if (verbose && dump) |
7725 | fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn), | |
7726 | last_clock == clock ? " + cycle advance" : ""); | |
388092d5 | 7727 | |
30028c85 | 7728 | stop_before_p = 1; |
388092d5 AB |
7729 | current_cycle = clock; |
7730 | mem_ops_in_group[current_cycle % 4] = 0; | |
7731 | ||
30028c85 | 7732 | if (last_clock == clock) |
2130b7fb | 7733 | { |
30028c85 VM |
7734 | state_transition (curr_state, dfa_stop_insn); |
7735 | if (TARGET_EARLY_STOP_BITS) | |
7736 | *sort_p = (last_scheduled_insn == NULL_RTX | |
b64925dc | 7737 | || ! CALL_P (last_scheduled_insn)); |
30028c85 VM |
7738 | else |
7739 | *sort_p = 0; | |
7740 | return 1; | |
7741 | } | |
388092d5 AB |
7742 | |
7743 | if (last_scheduled_insn) | |
25069b42 | 7744 | { |
7b84aac0 | 7745 | if (unknown_for_bundling_p (last_scheduled_insn)) |
388092d5 AB |
7746 | state_reset (curr_state); |
7747 | else | |
7748 | { | |
7749 | memcpy (curr_state, prev_cycle_state, dfa_state_size); | |
7750 | state_transition (curr_state, dfa_stop_insn); | |
7751 | state_transition (curr_state, dfa_pre_cycle_insn); | |
7752 | state_transition (curr_state, NULL); | |
7753 | } | |
25069b42 | 7754 | } |
30028c85 | 7755 | } |
30028c85 | 7756 | return 0; |
2130b7fb BS |
7757 | } |
7758 | ||
048d0d36 MK |
7759 | /* Implement targetm.sched.h_i_d_extended hook. |
7760 | Extend internal data structures. */ | |
7761 | static void | |
7762 | ia64_h_i_d_extended (void) | |
7763 | { | |
048d0d36 MK |
7764 | if (stops_p != NULL) |
7765 | { | |
388092d5 | 7766 | int new_clocks_length = get_max_uid () * 3 / 2; |
5ead67f6 | 7767 | stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1); |
048d0d36 MK |
7768 | clocks_length = new_clocks_length; |
7769 | } | |
7770 | } | |
388092d5 AB |
7771 | \f |
7772 | ||
7773 | /* This structure describes the data used by the backend to guide scheduling. | |
7774 | When the current scheduling point is switched, this data should be saved | |
7775 | and restored later, if the scheduler returns to this point. */ | |
7776 | struct _ia64_sched_context | |
7777 | { | |
7778 | state_t prev_cycle_state; | |
b32d5189 | 7779 | rtx_insn *last_scheduled_insn; |
388092d5 AB |
7780 | struct reg_write_state rws_sum[NUM_REGS]; |
7781 | struct reg_write_state rws_insn[NUM_REGS]; | |
7782 | int first_instruction; | |
7783 | int pending_data_specs; | |
7784 | int current_cycle; | |
7785 | char mem_ops_in_group[4]; | |
7786 | }; | |
7787 | typedef struct _ia64_sched_context *ia64_sched_context_t; | |
7788 | ||
7789 | /* Allocates a scheduling context. */ | |
7790 | static void * | |
7791 | ia64_alloc_sched_context (void) | |
7792 | { | |
7793 | return xmalloc (sizeof (struct _ia64_sched_context)); | |
7794 | } | |
7795 | ||
7796 | /* Initializes the _SC context with clean data, if CLEAN_P, and from | |
7797 | the global context otherwise. */ | |
7798 | static void | |
7799 | ia64_init_sched_context (void *_sc, bool clean_p) | |
7800 | { | |
7801 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7802 | ||
7803 | sc->prev_cycle_state = xmalloc (dfa_state_size); | |
7804 | if (clean_p) | |
7805 | { | |
7806 | state_reset (sc->prev_cycle_state); | |
b32d5189 | 7807 | sc->last_scheduled_insn = NULL; |
388092d5 AB |
7808 | memset (sc->rws_sum, 0, sizeof (rws_sum)); |
7809 | memset (sc->rws_insn, 0, sizeof (rws_insn)); | |
7810 | sc->first_instruction = 1; | |
7811 | sc->pending_data_specs = 0; | |
7812 | sc->current_cycle = 0; | |
7813 | memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
7814 | } | |
7815 | else | |
7816 | { | |
7817 | memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size); | |
7818 | sc->last_scheduled_insn = last_scheduled_insn; | |
7819 | memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum)); | |
7820 | memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn)); | |
7821 | sc->first_instruction = first_instruction; | |
7822 | sc->pending_data_specs = pending_data_specs; | |
7823 | sc->current_cycle = current_cycle; | |
7824 | memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7825 | } | |
7826 | } | |
7827 | ||
7828 | /* Sets the global scheduling context to the one pointed to by _SC. */ | |
7829 | static void | |
7830 | ia64_set_sched_context (void *_sc) | |
7831 | { | |
7832 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7833 | ||
7834 | gcc_assert (sc != NULL); | |
7835 | ||
7836 | memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size); | |
7837 | last_scheduled_insn = sc->last_scheduled_insn; | |
7838 | memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum)); | |
7839 | memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn)); | |
7840 | first_instruction = sc->first_instruction; | |
7841 | pending_data_specs = sc->pending_data_specs; | |
7842 | current_cycle = sc->current_cycle; | |
7843 | memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7844 | } | |
7845 | ||
7846 | /* Clears the data in the _SC scheduling context. */ | |
7847 | static void | |
7848 | ia64_clear_sched_context (void *_sc) | |
7849 | { | |
7850 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7851 | ||
7852 | free (sc->prev_cycle_state); | |
7853 | sc->prev_cycle_state = NULL; | |
7854 | } | |
7855 | ||
7856 | /* Frees the _SC scheduling context. */ | |
7857 | static void | |
7858 | ia64_free_sched_context (void *_sc) | |
7859 | { | |
7860 | gcc_assert (_sc != NULL); | |
7861 | ||
7862 | free (_sc); | |
7863 | } | |
7864 | ||
7865 | typedef rtx (* gen_func_t) (rtx, rtx); | |
7866 | ||
7867 | /* Return a function that will generate a load of mode MODE_NO | |
7868 | with speculation types TS. */ | |
7869 | static gen_func_t | |
7870 | get_spec_load_gen_function (ds_t ts, int mode_no) | |
7871 | { | |
7872 | static gen_func_t gen_ld_[] = { | |
7873 | gen_movbi, | |
7874 | gen_movqi_internal, | |
7875 | gen_movhi_internal, | |
7876 | gen_movsi_internal, | |
7877 | gen_movdi_internal, | |
7878 | gen_movsf_internal, | |
7879 | gen_movdf_internal, | |
7880 | gen_movxf_internal, | |
7881 | gen_movti_internal, | |
7882 | gen_zero_extendqidi2, | |
7883 | gen_zero_extendhidi2, | |
7884 | gen_zero_extendsidi2, | |
7885 | }; | |
7886 | ||
7887 | static gen_func_t gen_ld_a[] = { | |
7888 | gen_movbi_advanced, | |
7889 | gen_movqi_advanced, | |
7890 | gen_movhi_advanced, | |
7891 | gen_movsi_advanced, | |
7892 | gen_movdi_advanced, | |
7893 | gen_movsf_advanced, | |
7894 | gen_movdf_advanced, | |
7895 | gen_movxf_advanced, | |
7896 | gen_movti_advanced, | |
7897 | gen_zero_extendqidi2_advanced, | |
7898 | gen_zero_extendhidi2_advanced, | |
7899 | gen_zero_extendsidi2_advanced, | |
7900 | }; | |
7901 | static gen_func_t gen_ld_s[] = { | |
7902 | gen_movbi_speculative, | |
7903 | gen_movqi_speculative, | |
7904 | gen_movhi_speculative, | |
7905 | gen_movsi_speculative, | |
7906 | gen_movdi_speculative, | |
7907 | gen_movsf_speculative, | |
7908 | gen_movdf_speculative, | |
7909 | gen_movxf_speculative, | |
7910 | gen_movti_speculative, | |
7911 | gen_zero_extendqidi2_speculative, | |
7912 | gen_zero_extendhidi2_speculative, | |
7913 | gen_zero_extendsidi2_speculative, | |
7914 | }; | |
7915 | static gen_func_t gen_ld_sa[] = { | |
7916 | gen_movbi_speculative_advanced, | |
7917 | gen_movqi_speculative_advanced, | |
7918 | gen_movhi_speculative_advanced, | |
7919 | gen_movsi_speculative_advanced, | |
7920 | gen_movdi_speculative_advanced, | |
7921 | gen_movsf_speculative_advanced, | |
7922 | gen_movdf_speculative_advanced, | |
7923 | gen_movxf_speculative_advanced, | |
7924 | gen_movti_speculative_advanced, | |
7925 | gen_zero_extendqidi2_speculative_advanced, | |
7926 | gen_zero_extendhidi2_speculative_advanced, | |
7927 | gen_zero_extendsidi2_speculative_advanced, | |
7928 | }; | |
7929 | static gen_func_t gen_ld_s_a[] = { | |
7930 | gen_movbi_speculative_a, | |
7931 | gen_movqi_speculative_a, | |
7932 | gen_movhi_speculative_a, | |
7933 | gen_movsi_speculative_a, | |
7934 | gen_movdi_speculative_a, | |
7935 | gen_movsf_speculative_a, | |
7936 | gen_movdf_speculative_a, | |
7937 | gen_movxf_speculative_a, | |
7938 | gen_movti_speculative_a, | |
7939 | gen_zero_extendqidi2_speculative_a, | |
7940 | gen_zero_extendhidi2_speculative_a, | |
7941 | gen_zero_extendsidi2_speculative_a, | |
7942 | }; | |
7943 | ||
7944 | gen_func_t *gen_ld; | |
7945 | ||
7946 | if (ts & BEGIN_DATA) | |
7947 | { | |
7948 | if (ts & BEGIN_CONTROL) | |
7949 | gen_ld = gen_ld_sa; | |
7950 | else | |
7951 | gen_ld = gen_ld_a; | |
7952 | } | |
7953 | else if (ts & BEGIN_CONTROL) | |
7954 | { | |
7955 | if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL) | |
7956 | || ia64_needs_block_p (ts)) | |
7957 | gen_ld = gen_ld_s; | |
7958 | else | |
7959 | gen_ld = gen_ld_s_a; | |
7960 | } | |
7961 | else if (ts == 0) | |
7962 | gen_ld = gen_ld_; | |
7963 | else | |
7964 | gcc_unreachable (); | |
7965 | ||
7966 | return gen_ld[mode_no]; | |
7967 | } | |
048d0d36 | 7968 | |
ef4bddc2 | 7969 | /* Constants that help mapping 'machine_mode' to int. */ |
048d0d36 MK |
7970 | enum SPEC_MODES |
7971 | { | |
7972 | SPEC_MODE_INVALID = -1, | |
7973 | SPEC_MODE_FIRST = 0, | |
7974 | SPEC_MODE_FOR_EXTEND_FIRST = 1, | |
7975 | SPEC_MODE_FOR_EXTEND_LAST = 3, | |
7976 | SPEC_MODE_LAST = 8 | |
7977 | }; | |
7978 | ||
388092d5 AB |
7979 | enum |
7980 | { | |
7981 | /* Offset to reach ZERO_EXTEND patterns. */ | |
7982 | SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1 | |
7983 | }; | |
7984 | ||
048d0d36 MK |
7985 | /* Return index of the MODE. */ |
7986 | static int | |
ef4bddc2 | 7987 | ia64_mode_to_int (machine_mode mode) |
048d0d36 MK |
7988 | { |
7989 | switch (mode) | |
7990 | { | |
4e10a5a7 RS |
7991 | case E_BImode: return 0; /* SPEC_MODE_FIRST */ |
7992 | case E_QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */ | |
7993 | case E_HImode: return 2; | |
7994 | case E_SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */ | |
7995 | case E_DImode: return 4; | |
7996 | case E_SFmode: return 5; | |
7997 | case E_DFmode: return 6; | |
7998 | case E_XFmode: return 7; | |
7999 | case E_TImode: | |
048d0d36 MK |
8000 | /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not |
8001 | mentioned in itanium[12].md. Predicate fp_register_operand also | |
8002 | needs to be defined. Bottom line: better disable for now. */ | |
8003 | return SPEC_MODE_INVALID; | |
8004 | default: return SPEC_MODE_INVALID; | |
8005 | } | |
8006 | } | |
8007 | ||
8008 | /* Provide information about speculation capabilities. */ | |
8009 | static void | |
8010 | ia64_set_sched_flags (spec_info_t spec_info) | |
8011 | { | |
8012 | unsigned int *flags = &(current_sched_info->flags); | |
8013 | ||
8014 | if (*flags & SCHED_RGN | |
388092d5 AB |
8015 | || *flags & SCHED_EBB |
8016 | || *flags & SEL_SCHED) | |
048d0d36 MK |
8017 | { |
8018 | int mask = 0; | |
8019 | ||
a57aee2a | 8020 | if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0) |
388092d5 | 8021 | || (mflag_sched_ar_data_spec && reload_completed)) |
048d0d36 MK |
8022 | { |
8023 | mask |= BEGIN_DATA; | |
388092d5 AB |
8024 | |
8025 | if (!sel_sched_p () | |
8026 | && ((mflag_sched_br_in_data_spec && !reload_completed) | |
8027 | || (mflag_sched_ar_in_data_spec && reload_completed))) | |
048d0d36 MK |
8028 | mask |= BE_IN_DATA; |
8029 | } | |
8030 | ||
388092d5 AB |
8031 | if (mflag_sched_control_spec |
8032 | && (!sel_sched_p () | |
8033 | || reload_completed)) | |
048d0d36 MK |
8034 | { |
8035 | mask |= BEGIN_CONTROL; | |
8036 | ||
388092d5 | 8037 | if (!sel_sched_p () && mflag_sched_in_control_spec) |
048d0d36 MK |
8038 | mask |= BE_IN_CONTROL; |
8039 | } | |
8040 | ||
7ab5df48 AB |
8041 | spec_info->mask = mask; |
8042 | ||
048d0d36 MK |
8043 | if (mask) |
8044 | { | |
6fb5fa3c DB |
8045 | *flags |= USE_DEPS_LIST | DO_SPECULATION; |
8046 | ||
8047 | if (mask & BE_IN_SPEC) | |
8048 | *flags |= NEW_BBS; | |
048d0d36 | 8049 | |
048d0d36 MK |
8050 | spec_info->flags = 0; |
8051 | ||
16d83dd6 MK |
8052 | if ((mask & CONTROL_SPEC) |
8053 | && sel_sched_p () && mflag_sel_sched_dont_check_control_spec) | |
8054 | spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL; | |
388092d5 AB |
8055 | |
8056 | if (sched_verbose >= 1) | |
8057 | spec_info->dump = sched_dump; | |
048d0d36 MK |
8058 | else |
8059 | spec_info->dump = 0; | |
8060 | ||
8061 | if (mflag_sched_count_spec_in_critical_path) | |
8062 | spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH; | |
8063 | } | |
8064 | } | |
cd510f15 AM |
8065 | else |
8066 | spec_info->mask = 0; | |
048d0d36 MK |
8067 | } |
8068 | ||
388092d5 AB |
8069 | /* If INSN is an appropriate load return its mode. |
8070 | Return -1 otherwise. */ | |
048d0d36 | 8071 | static int |
647d790d | 8072 | get_mode_no_for_insn (rtx_insn *insn) |
388092d5 AB |
8073 | { |
8074 | rtx reg, mem, mode_rtx; | |
8075 | int mode_no; | |
048d0d36 | 8076 | bool extend_p; |
048d0d36 | 8077 | |
388092d5 | 8078 | extract_insn_cached (insn); |
048d0d36 | 8079 | |
388092d5 AB |
8080 | /* We use WHICH_ALTERNATIVE only after reload. This will |
8081 | guarantee that reload won't touch a speculative insn. */ | |
f6ec1d11 | 8082 | |
388092d5 | 8083 | if (recog_data.n_operands != 2) |
048d0d36 MK |
8084 | return -1; |
8085 | ||
388092d5 AB |
8086 | reg = recog_data.operand[0]; |
8087 | mem = recog_data.operand[1]; | |
f6ec1d11 | 8088 | |
388092d5 AB |
8089 | /* We should use MEM's mode since REG's mode in presence of |
8090 | ZERO_EXTEND will always be DImode. */ | |
8091 | if (get_attr_speculable1 (insn) == SPECULABLE1_YES) | |
8092 | /* Process non-speculative ld. */ | |
8093 | { | |
8094 | if (!reload_completed) | |
8095 | { | |
8096 | /* Do not speculate into regs like ar.lc. */ | |
8097 | if (!REG_P (reg) || AR_REGNO_P (REGNO (reg))) | |
8098 | return -1; | |
8099 | ||
8100 | if (!MEM_P (mem)) | |
8101 | return -1; | |
8102 | ||
8103 | { | |
8104 | rtx mem_reg = XEXP (mem, 0); | |
8105 | ||
8106 | if (!REG_P (mem_reg)) | |
8107 | return -1; | |
8108 | } | |
8109 | ||
8110 | mode_rtx = mem; | |
8111 | } | |
8112 | else if (get_attr_speculable2 (insn) == SPECULABLE2_YES) | |
8113 | { | |
8114 | gcc_assert (REG_P (reg) && MEM_P (mem)); | |
8115 | mode_rtx = mem; | |
8116 | } | |
8117 | else | |
8118 | return -1; | |
8119 | } | |
8120 | else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES | |
8121 | || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES | |
8122 | || get_attr_check_load (insn) == CHECK_LOAD_YES) | |
8123 | /* Process speculative ld or ld.c. */ | |
048d0d36 | 8124 | { |
388092d5 AB |
8125 | gcc_assert (REG_P (reg) && MEM_P (mem)); |
8126 | mode_rtx = mem; | |
048d0d36 MK |
8127 | } |
8128 | else | |
048d0d36 | 8129 | { |
388092d5 | 8130 | enum attr_itanium_class attr_class = get_attr_itanium_class (insn); |
048d0d36 | 8131 | |
388092d5 AB |
8132 | if (attr_class == ITANIUM_CLASS_CHK_A |
8133 | || attr_class == ITANIUM_CLASS_CHK_S_I | |
8134 | || attr_class == ITANIUM_CLASS_CHK_S_F) | |
8135 | /* Process chk. */ | |
8136 | mode_rtx = reg; | |
8137 | else | |
8138 | return -1; | |
048d0d36 | 8139 | } |
f6ec1d11 | 8140 | |
388092d5 | 8141 | mode_no = ia64_mode_to_int (GET_MODE (mode_rtx)); |
f6ec1d11 | 8142 | |
388092d5 | 8143 | if (mode_no == SPEC_MODE_INVALID) |
048d0d36 MK |
8144 | return -1; |
8145 | ||
388092d5 AB |
8146 | extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx)); |
8147 | ||
8148 | if (extend_p) | |
8149 | { | |
8150 | if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no | |
8151 | && mode_no <= SPEC_MODE_FOR_EXTEND_LAST)) | |
8152 | return -1; | |
f6ec1d11 | 8153 | |
388092d5 AB |
8154 | mode_no += SPEC_GEN_EXTEND_OFFSET; |
8155 | } | |
048d0d36 | 8156 | |
388092d5 | 8157 | return mode_no; |
048d0d36 MK |
8158 | } |
8159 | ||
388092d5 AB |
8160 | /* If X is an unspec part of a speculative load, return its code. |
8161 | Return -1 otherwise. */ | |
8162 | static int | |
8163 | get_spec_unspec_code (const_rtx x) | |
8164 | { | |
8165 | if (GET_CODE (x) != UNSPEC) | |
8166 | return -1; | |
048d0d36 | 8167 | |
048d0d36 | 8168 | { |
388092d5 | 8169 | int code; |
048d0d36 | 8170 | |
388092d5 | 8171 | code = XINT (x, 1); |
048d0d36 | 8172 | |
388092d5 AB |
8173 | switch (code) |
8174 | { | |
8175 | case UNSPEC_LDA: | |
8176 | case UNSPEC_LDS: | |
8177 | case UNSPEC_LDS_A: | |
8178 | case UNSPEC_LDSA: | |
8179 | return code; | |
048d0d36 | 8180 | |
388092d5 AB |
8181 | default: |
8182 | return -1; | |
8183 | } | |
8184 | } | |
8185 | } | |
048d0d36 | 8186 | |
388092d5 AB |
8187 | /* Implement skip_rtx_p hook. */ |
8188 | static bool | |
8189 | ia64_skip_rtx_p (const_rtx x) | |
8190 | { | |
8191 | return get_spec_unspec_code (x) != -1; | |
8192 | } | |
048d0d36 | 8193 | |
388092d5 AB |
8194 | /* If INSN is a speculative load, return its UNSPEC code. |
8195 | Return -1 otherwise. */ | |
8196 | static int | |
8197 | get_insn_spec_code (const_rtx insn) | |
8198 | { | |
8199 | rtx pat, reg, mem; | |
048d0d36 | 8200 | |
388092d5 | 8201 | pat = PATTERN (insn); |
048d0d36 | 8202 | |
388092d5 AB |
8203 | if (GET_CODE (pat) == COND_EXEC) |
8204 | pat = COND_EXEC_CODE (pat); | |
048d0d36 | 8205 | |
388092d5 AB |
8206 | if (GET_CODE (pat) != SET) |
8207 | return -1; | |
8208 | ||
8209 | reg = SET_DEST (pat); | |
8210 | if (!REG_P (reg)) | |
8211 | return -1; | |
8212 | ||
8213 | mem = SET_SRC (pat); | |
8214 | if (GET_CODE (mem) == ZERO_EXTEND) | |
8215 | mem = XEXP (mem, 0); | |
8216 | ||
8217 | return get_spec_unspec_code (mem); | |
8218 | } | |
8219 | ||
8220 | /* If INSN is a speculative load, return a ds with the speculation types. | |
8221 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8222 | static ds_t | |
ac44248e | 8223 | ia64_get_insn_spec_ds (rtx_insn *insn) |
388092d5 AB |
8224 | { |
8225 | int code = get_insn_spec_code (insn); | |
8226 | ||
8227 | switch (code) | |
048d0d36 | 8228 | { |
388092d5 AB |
8229 | case UNSPEC_LDA: |
8230 | return BEGIN_DATA; | |
048d0d36 | 8231 | |
388092d5 AB |
8232 | case UNSPEC_LDS: |
8233 | case UNSPEC_LDS_A: | |
8234 | return BEGIN_CONTROL; | |
048d0d36 | 8235 | |
388092d5 AB |
8236 | case UNSPEC_LDSA: |
8237 | return BEGIN_DATA | BEGIN_CONTROL; | |
048d0d36 | 8238 | |
388092d5 AB |
8239 | default: |
8240 | return 0; | |
048d0d36 | 8241 | } |
388092d5 AB |
8242 | } |
8243 | ||
8244 | /* If INSN is a speculative load return a ds with the speculation types that | |
8245 | will be checked. | |
8246 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8247 | static ds_t | |
ac44248e | 8248 | ia64_get_insn_checked_ds (rtx_insn *insn) |
388092d5 AB |
8249 | { |
8250 | int code = get_insn_spec_code (insn); | |
8251 | ||
8252 | switch (code) | |
048d0d36 | 8253 | { |
388092d5 AB |
8254 | case UNSPEC_LDA: |
8255 | return BEGIN_DATA | BEGIN_CONTROL; | |
8256 | ||
8257 | case UNSPEC_LDS: | |
8258 | return BEGIN_CONTROL; | |
8259 | ||
8260 | case UNSPEC_LDS_A: | |
8261 | case UNSPEC_LDSA: | |
8262 | return BEGIN_DATA | BEGIN_CONTROL; | |
8263 | ||
8264 | default: | |
8265 | return 0; | |
048d0d36 | 8266 | } |
388092d5 | 8267 | } |
048d0d36 | 8268 | |
388092d5 AB |
8269 | /* If GEN_P is true, calculate the index of needed speculation check and return |
8270 | speculative pattern for INSN with speculative mode TS, machine mode | |
8271 | MODE_NO and with ZERO_EXTEND (if EXTEND_P is true). | |
8272 | If GEN_P is false, just calculate the index of needed speculation check. */ | |
8273 | static rtx | |
8274 | ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no) | |
8275 | { | |
8276 | rtx pat, new_pat; | |
8277 | gen_func_t gen_load; | |
048d0d36 | 8278 | |
388092d5 | 8279 | gen_load = get_spec_load_gen_function (ts, mode_no); |
048d0d36 | 8280 | |
388092d5 AB |
8281 | new_pat = gen_load (copy_rtx (recog_data.operand[0]), |
8282 | copy_rtx (recog_data.operand[1])); | |
048d0d36 MK |
8283 | |
8284 | pat = PATTERN (insn); | |
8285 | if (GET_CODE (pat) == COND_EXEC) | |
388092d5 AB |
8286 | new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), |
8287 | new_pat); | |
048d0d36 MK |
8288 | |
8289 | return new_pat; | |
8290 | } | |
8291 | ||
048d0d36 | 8292 | static bool |
388092d5 AB |
8293 | insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED, |
8294 | ds_t ds ATTRIBUTE_UNUSED) | |
048d0d36 | 8295 | { |
388092d5 AB |
8296 | return false; |
8297 | } | |
048d0d36 | 8298 | |
388092d5 AB |
8299 | /* Implement targetm.sched.speculate_insn hook. |
8300 | Check if the INSN can be TS speculative. | |
8301 | If 'no' - return -1. | |
8302 | If 'yes' - generate speculative pattern in the NEW_PAT and return 1. | |
8303 | If current pattern of the INSN already provides TS speculation, | |
8304 | return 0. */ | |
8305 | static int | |
ac44248e | 8306 | ia64_speculate_insn (rtx_insn *insn, ds_t ts, rtx *new_pat) |
388092d5 AB |
8307 | { |
8308 | int mode_no; | |
8309 | int res; | |
8310 | ||
8311 | gcc_assert (!(ts & ~SPECULATIVE)); | |
048d0d36 | 8312 | |
388092d5 AB |
8313 | if (ia64_spec_check_p (insn)) |
8314 | return -1; | |
048d0d36 | 8315 | |
388092d5 AB |
8316 | if ((ts & BE_IN_SPEC) |
8317 | && !insn_can_be_in_speculative_p (insn, ts)) | |
8318 | return -1; | |
048d0d36 | 8319 | |
388092d5 | 8320 | mode_no = get_mode_no_for_insn (insn); |
048d0d36 | 8321 | |
388092d5 AB |
8322 | if (mode_no != SPEC_MODE_INVALID) |
8323 | { | |
8324 | if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts)) | |
8325 | res = 0; | |
8326 | else | |
8327 | { | |
8328 | res = 1; | |
8329 | *new_pat = ia64_gen_spec_load (insn, ts, mode_no); | |
8330 | } | |
8331 | } | |
8332 | else | |
8333 | res = -1; | |
048d0d36 | 8334 | |
388092d5 AB |
8335 | return res; |
8336 | } | |
048d0d36 | 8337 | |
388092d5 AB |
8338 | /* Return a function that will generate a check for speculation TS with mode |
8339 | MODE_NO. | |
8340 | If simple check is needed, pass true for SIMPLE_CHECK_P. | |
8341 | If clearing check is needed, pass true for CLEARING_CHECK_P. */ | |
8342 | static gen_func_t | |
8343 | get_spec_check_gen_function (ds_t ts, int mode_no, | |
8344 | bool simple_check_p, bool clearing_check_p) | |
8345 | { | |
8346 | static gen_func_t gen_ld_c_clr[] = { | |
048d0d36 MK |
8347 | gen_movbi_clr, |
8348 | gen_movqi_clr, | |
8349 | gen_movhi_clr, | |
8350 | gen_movsi_clr, | |
8351 | gen_movdi_clr, | |
8352 | gen_movsf_clr, | |
8353 | gen_movdf_clr, | |
8354 | gen_movxf_clr, | |
8355 | gen_movti_clr, | |
8356 | gen_zero_extendqidi2_clr, | |
8357 | gen_zero_extendhidi2_clr, | |
8358 | gen_zero_extendsidi2_clr, | |
388092d5 AB |
8359 | }; |
8360 | static gen_func_t gen_ld_c_nc[] = { | |
8361 | gen_movbi_nc, | |
8362 | gen_movqi_nc, | |
8363 | gen_movhi_nc, | |
8364 | gen_movsi_nc, | |
8365 | gen_movdi_nc, | |
8366 | gen_movsf_nc, | |
8367 | gen_movdf_nc, | |
8368 | gen_movxf_nc, | |
8369 | gen_movti_nc, | |
8370 | gen_zero_extendqidi2_nc, | |
8371 | gen_zero_extendhidi2_nc, | |
8372 | gen_zero_extendsidi2_nc, | |
8373 | }; | |
8374 | static gen_func_t gen_chk_a_clr[] = { | |
048d0d36 MK |
8375 | gen_advanced_load_check_clr_bi, |
8376 | gen_advanced_load_check_clr_qi, | |
8377 | gen_advanced_load_check_clr_hi, | |
8378 | gen_advanced_load_check_clr_si, | |
8379 | gen_advanced_load_check_clr_di, | |
8380 | gen_advanced_load_check_clr_sf, | |
8381 | gen_advanced_load_check_clr_df, | |
8382 | gen_advanced_load_check_clr_xf, | |
8383 | gen_advanced_load_check_clr_ti, | |
8384 | gen_advanced_load_check_clr_di, | |
8385 | gen_advanced_load_check_clr_di, | |
8386 | gen_advanced_load_check_clr_di, | |
388092d5 AB |
8387 | }; |
8388 | static gen_func_t gen_chk_a_nc[] = { | |
8389 | gen_advanced_load_check_nc_bi, | |
8390 | gen_advanced_load_check_nc_qi, | |
8391 | gen_advanced_load_check_nc_hi, | |
8392 | gen_advanced_load_check_nc_si, | |
8393 | gen_advanced_load_check_nc_di, | |
8394 | gen_advanced_load_check_nc_sf, | |
8395 | gen_advanced_load_check_nc_df, | |
8396 | gen_advanced_load_check_nc_xf, | |
8397 | gen_advanced_load_check_nc_ti, | |
8398 | gen_advanced_load_check_nc_di, | |
8399 | gen_advanced_load_check_nc_di, | |
8400 | gen_advanced_load_check_nc_di, | |
8401 | }; | |
8402 | static gen_func_t gen_chk_s[] = { | |
048d0d36 MK |
8403 | gen_speculation_check_bi, |
8404 | gen_speculation_check_qi, | |
8405 | gen_speculation_check_hi, | |
8406 | gen_speculation_check_si, | |
8407 | gen_speculation_check_di, | |
8408 | gen_speculation_check_sf, | |
8409 | gen_speculation_check_df, | |
8410 | gen_speculation_check_xf, | |
8411 | gen_speculation_check_ti, | |
8412 | gen_speculation_check_di, | |
8413 | gen_speculation_check_di, | |
388092d5 | 8414 | gen_speculation_check_di, |
048d0d36 MK |
8415 | }; |
8416 | ||
388092d5 | 8417 | gen_func_t *gen_check; |
048d0d36 | 8418 | |
388092d5 | 8419 | if (ts & BEGIN_DATA) |
048d0d36 | 8420 | { |
388092d5 AB |
8421 | /* We don't need recovery because even if this is ld.sa |
8422 | ALAT entry will be allocated only if NAT bit is set to zero. | |
8423 | So it is enough to use ld.c here. */ | |
8424 | ||
8425 | if (simple_check_p) | |
8426 | { | |
8427 | gcc_assert (mflag_sched_spec_ldc); | |
8428 | ||
8429 | if (clearing_check_p) | |
8430 | gen_check = gen_ld_c_clr; | |
8431 | else | |
8432 | gen_check = gen_ld_c_nc; | |
8433 | } | |
8434 | else | |
8435 | { | |
8436 | if (clearing_check_p) | |
8437 | gen_check = gen_chk_a_clr; | |
8438 | else | |
8439 | gen_check = gen_chk_a_nc; | |
8440 | } | |
048d0d36 | 8441 | } |
388092d5 | 8442 | else if (ts & BEGIN_CONTROL) |
048d0d36 | 8443 | { |
388092d5 AB |
8444 | if (simple_check_p) |
8445 | /* We might want to use ld.sa -> ld.c instead of | |
8446 | ld.s -> chk.s. */ | |
048d0d36 | 8447 | { |
388092d5 | 8448 | gcc_assert (!ia64_needs_block_p (ts)); |
048d0d36 | 8449 | |
388092d5 AB |
8450 | if (clearing_check_p) |
8451 | gen_check = gen_ld_c_clr; | |
8452 | else | |
8453 | gen_check = gen_ld_c_nc; | |
8454 | } | |
8455 | else | |
8456 | { | |
8457 | gen_check = gen_chk_s; | |
048d0d36 | 8458 | } |
388092d5 AB |
8459 | } |
8460 | else | |
8461 | gcc_unreachable (); | |
8462 | ||
8463 | gcc_assert (mode_no >= 0); | |
8464 | return gen_check[mode_no]; | |
8465 | } | |
8466 | ||
8467 | /* Return nonzero, if INSN needs branchy recovery check. */ | |
8468 | static bool | |
8469 | ia64_needs_block_p (ds_t ts) | |
8470 | { | |
8471 | if (ts & BEGIN_DATA) | |
8472 | return !mflag_sched_spec_ldc; | |
8473 | ||
8474 | gcc_assert ((ts & BEGIN_CONTROL) != 0); | |
048d0d36 | 8475 | |
388092d5 AB |
8476 | return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc); |
8477 | } | |
8478 | ||
8e90de43 | 8479 | /* Generate (or regenerate) a recovery check for INSN. */ |
388092d5 | 8480 | static rtx |
ac44248e | 8481 | ia64_gen_spec_check (rtx_insn *insn, rtx_insn *label, ds_t ds) |
388092d5 AB |
8482 | { |
8483 | rtx op1, pat, check_pat; | |
8484 | gen_func_t gen_check; | |
8485 | int mode_no; | |
8486 | ||
8487 | mode_no = get_mode_no_for_insn (insn); | |
8488 | gcc_assert (mode_no >= 0); | |
8489 | ||
8490 | if (label) | |
8491 | op1 = label; | |
8492 | else | |
8493 | { | |
8494 | gcc_assert (!ia64_needs_block_p (ds)); | |
8495 | op1 = copy_rtx (recog_data.operand[1]); | |
048d0d36 | 8496 | } |
388092d5 AB |
8497 | |
8498 | gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX, | |
8499 | true); | |
048d0d36 | 8500 | |
388092d5 | 8501 | check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1); |
048d0d36 MK |
8502 | |
8503 | pat = PATTERN (insn); | |
8504 | if (GET_CODE (pat) == COND_EXEC) | |
8505 | check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), | |
8506 | check_pat); | |
8507 | ||
8508 | return check_pat; | |
8509 | } | |
8510 | ||
8511 | /* Return nonzero, if X is branchy recovery check. */ | |
8512 | static int | |
8513 | ia64_spec_check_p (rtx x) | |
8514 | { | |
8515 | x = PATTERN (x); | |
8516 | if (GET_CODE (x) == COND_EXEC) | |
8517 | x = COND_EXEC_CODE (x); | |
8518 | if (GET_CODE (x) == SET) | |
8519 | return ia64_spec_check_src_p (SET_SRC (x)); | |
8520 | return 0; | |
8521 | } | |
8522 | ||
8523 | /* Return nonzero, if SRC belongs to recovery check. */ | |
8524 | static int | |
8525 | ia64_spec_check_src_p (rtx src) | |
8526 | { | |
8527 | if (GET_CODE (src) == IF_THEN_ELSE) | |
8528 | { | |
8529 | rtx t; | |
8530 | ||
8531 | t = XEXP (src, 0); | |
8532 | if (GET_CODE (t) == NE) | |
8533 | { | |
8534 | t = XEXP (t, 0); | |
8535 | ||
8536 | if (GET_CODE (t) == UNSPEC) | |
8537 | { | |
8538 | int code; | |
8539 | ||
8540 | code = XINT (t, 1); | |
8541 | ||
388092d5 AB |
8542 | if (code == UNSPEC_LDCCLR |
8543 | || code == UNSPEC_LDCNC | |
8544 | || code == UNSPEC_CHKACLR | |
8545 | || code == UNSPEC_CHKANC | |
8546 | || code == UNSPEC_CHKS) | |
048d0d36 MK |
8547 | { |
8548 | gcc_assert (code != 0); | |
8549 | return code; | |
8550 | } | |
8551 | } | |
8552 | } | |
8553 | } | |
8554 | return 0; | |
8555 | } | |
30028c85 | 8556 | \f |
2130b7fb | 8557 | |
30028c85 VM |
8558 | /* The following page contains abstract data `bundle states' which are |
8559 | used for bundling insns (inserting nops and template generation). */ | |
8560 | ||
8561 | /* The following describes state of insn bundling. */ | |
8562 | ||
8563 | struct bundle_state | |
8564 | { | |
8565 | /* Unique bundle state number to identify them in the debugging | |
8566 | output */ | |
8567 | int unique_num; | |
b32d5189 | 8568 | rtx_insn *insn; /* corresponding insn, NULL for the 1st and the last state */ |
30028c85 VM |
8569 | /* number nops before and after the insn */ |
8570 | short before_nops_num, after_nops_num; | |
8571 | int insn_num; /* insn number (0 - for initial state, 1 - for the 1st | |
8572 | insn */ | |
8573 | int cost; /* cost of the state in cycles */ | |
8574 | int accumulated_insns_num; /* number of all previous insns including | |
8575 | nops. L is considered as 2 insns */ | |
8576 | int branch_deviation; /* deviation of previous branches from 3rd slots */ | |
388092d5 | 8577 | int middle_bundle_stops; /* number of stop bits in the middle of bundles */ |
30028c85 VM |
8578 | struct bundle_state *next; /* next state with the same insn_num */ |
8579 | struct bundle_state *originator; /* originator (previous insn state) */ | |
8580 | /* All bundle states are in the following chain. */ | |
8581 | struct bundle_state *allocated_states_chain; | |
8582 | /* The DFA State after issuing the insn and the nops. */ | |
8583 | state_t dfa_state; | |
8584 | }; | |
2130b7fb | 8585 | |
30028c85 | 8586 | /* The following is map insn number to the corresponding bundle state. */ |
2130b7fb | 8587 | |
30028c85 | 8588 | static struct bundle_state **index_to_bundle_states; |
2130b7fb | 8589 | |
30028c85 | 8590 | /* The unique number of next bundle state. */ |
2130b7fb | 8591 | |
30028c85 | 8592 | static int bundle_states_num; |
2130b7fb | 8593 | |
30028c85 | 8594 | /* All allocated bundle states are in the following chain. */ |
2130b7fb | 8595 | |
30028c85 | 8596 | static struct bundle_state *allocated_bundle_states_chain; |
e57b9d65 | 8597 | |
30028c85 VM |
8598 | /* All allocated but not used bundle states are in the following |
8599 | chain. */ | |
870f9ec0 | 8600 | |
30028c85 | 8601 | static struct bundle_state *free_bundle_state_chain; |
2130b7fb | 8602 | |
2130b7fb | 8603 | |
30028c85 | 8604 | /* The following function returns a free bundle state. */ |
2130b7fb | 8605 | |
30028c85 | 8606 | static struct bundle_state * |
9c808aad | 8607 | get_free_bundle_state (void) |
30028c85 VM |
8608 | { |
8609 | struct bundle_state *result; | |
2130b7fb | 8610 | |
30028c85 | 8611 | if (free_bundle_state_chain != NULL) |
2130b7fb | 8612 | { |
30028c85 VM |
8613 | result = free_bundle_state_chain; |
8614 | free_bundle_state_chain = result->next; | |
2130b7fb | 8615 | } |
30028c85 | 8616 | else |
2130b7fb | 8617 | { |
5ead67f6 | 8618 | result = XNEW (struct bundle_state); |
30028c85 VM |
8619 | result->dfa_state = xmalloc (dfa_state_size); |
8620 | result->allocated_states_chain = allocated_bundle_states_chain; | |
8621 | allocated_bundle_states_chain = result; | |
2130b7fb | 8622 | } |
30028c85 VM |
8623 | result->unique_num = bundle_states_num++; |
8624 | return result; | |
9c808aad | 8625 | |
30028c85 | 8626 | } |
2130b7fb | 8627 | |
30028c85 | 8628 | /* The following function frees given bundle state. */ |
2130b7fb | 8629 | |
30028c85 | 8630 | static void |
9c808aad | 8631 | free_bundle_state (struct bundle_state *state) |
30028c85 VM |
8632 | { |
8633 | state->next = free_bundle_state_chain; | |
8634 | free_bundle_state_chain = state; | |
8635 | } | |
2130b7fb | 8636 | |
30028c85 | 8637 | /* Start work with abstract data `bundle states'. */ |
2130b7fb | 8638 | |
30028c85 | 8639 | static void |
9c808aad | 8640 | initiate_bundle_states (void) |
30028c85 VM |
8641 | { |
8642 | bundle_states_num = 0; | |
8643 | free_bundle_state_chain = NULL; | |
8644 | allocated_bundle_states_chain = NULL; | |
2130b7fb BS |
8645 | } |
8646 | ||
30028c85 | 8647 | /* Finish work with abstract data `bundle states'. */ |
2130b7fb BS |
8648 | |
8649 | static void | |
9c808aad | 8650 | finish_bundle_states (void) |
2130b7fb | 8651 | { |
30028c85 VM |
8652 | struct bundle_state *curr_state, *next_state; |
8653 | ||
8654 | for (curr_state = allocated_bundle_states_chain; | |
8655 | curr_state != NULL; | |
8656 | curr_state = next_state) | |
2130b7fb | 8657 | { |
30028c85 VM |
8658 | next_state = curr_state->allocated_states_chain; |
8659 | free (curr_state->dfa_state); | |
8660 | free (curr_state); | |
2130b7fb | 8661 | } |
2130b7fb BS |
8662 | } |
8663 | ||
3a4f280b | 8664 | /* Hashtable helpers. */ |
2130b7fb | 8665 | |
8d67ee55 | 8666 | struct bundle_state_hasher : nofree_ptr_hash <bundle_state> |
3a4f280b | 8667 | { |
67f58944 TS |
8668 | static inline hashval_t hash (const bundle_state *); |
8669 | static inline bool equal (const bundle_state *, const bundle_state *); | |
3a4f280b | 8670 | }; |
2130b7fb | 8671 | |
30028c85 | 8672 | /* The function returns hash of BUNDLE_STATE. */ |
2130b7fb | 8673 | |
3a4f280b | 8674 | inline hashval_t |
67f58944 | 8675 | bundle_state_hasher::hash (const bundle_state *state) |
30028c85 | 8676 | { |
30028c85 | 8677 | unsigned result, i; |
2130b7fb | 8678 | |
30028c85 VM |
8679 | for (result = i = 0; i < dfa_state_size; i++) |
8680 | result += (((unsigned char *) state->dfa_state) [i] | |
8681 | << ((i % CHAR_BIT) * 3 + CHAR_BIT)); | |
8682 | return result + state->insn_num; | |
8683 | } | |
2130b7fb | 8684 | |
30028c85 | 8685 | /* The function returns nonzero if the bundle state keys are equal. */ |
2130b7fb | 8686 | |
3a4f280b | 8687 | inline bool |
67f58944 TS |
8688 | bundle_state_hasher::equal (const bundle_state *state1, |
8689 | const bundle_state *state2) | |
30028c85 | 8690 | { |
30028c85 VM |
8691 | return (state1->insn_num == state2->insn_num |
8692 | && memcmp (state1->dfa_state, state2->dfa_state, | |
8693 | dfa_state_size) == 0); | |
8694 | } | |
2130b7fb | 8695 | |
3a4f280b LC |
8696 | /* Hash table of the bundle states. The key is dfa_state and insn_num |
8697 | of the bundle states. */ | |
8698 | ||
c203e8a7 | 8699 | static hash_table<bundle_state_hasher> *bundle_state_table; |
3a4f280b | 8700 | |
30028c85 VM |
8701 | /* The function inserts the BUNDLE_STATE into the hash table. The |
8702 | function returns nonzero if the bundle has been inserted into the | |
8703 | table. The table contains the best bundle state with given key. */ | |
2130b7fb | 8704 | |
30028c85 | 8705 | static int |
9c808aad | 8706 | insert_bundle_state (struct bundle_state *bundle_state) |
30028c85 | 8707 | { |
3a4f280b | 8708 | struct bundle_state **entry_ptr; |
2130b7fb | 8709 | |
c203e8a7 | 8710 | entry_ptr = bundle_state_table->find_slot (bundle_state, INSERT); |
30028c85 VM |
8711 | if (*entry_ptr == NULL) |
8712 | { | |
8713 | bundle_state->next = index_to_bundle_states [bundle_state->insn_num]; | |
8714 | index_to_bundle_states [bundle_state->insn_num] = bundle_state; | |
3a4f280b | 8715 | *entry_ptr = bundle_state; |
30028c85 | 8716 | return TRUE; |
2130b7fb | 8717 | } |
3a4f280b LC |
8718 | else if (bundle_state->cost < (*entry_ptr)->cost |
8719 | || (bundle_state->cost == (*entry_ptr)->cost | |
8720 | && ((*entry_ptr)->accumulated_insns_num | |
30028c85 | 8721 | > bundle_state->accumulated_insns_num |
3a4f280b | 8722 | || ((*entry_ptr)->accumulated_insns_num |
30028c85 | 8723 | == bundle_state->accumulated_insns_num |
3a4f280b | 8724 | && ((*entry_ptr)->branch_deviation |
388092d5 | 8725 | > bundle_state->branch_deviation |
3a4f280b | 8726 | || ((*entry_ptr)->branch_deviation |
388092d5 | 8727 | == bundle_state->branch_deviation |
3a4f280b | 8728 | && (*entry_ptr)->middle_bundle_stops |
388092d5 | 8729 | > bundle_state->middle_bundle_stops)))))) |
9c808aad | 8730 | |
2130b7fb | 8731 | { |
30028c85 VM |
8732 | struct bundle_state temp; |
8733 | ||
3a4f280b LC |
8734 | temp = **entry_ptr; |
8735 | **entry_ptr = *bundle_state; | |
8736 | (*entry_ptr)->next = temp.next; | |
30028c85 | 8737 | *bundle_state = temp; |
2130b7fb | 8738 | } |
30028c85 VM |
8739 | return FALSE; |
8740 | } | |
2130b7fb | 8741 | |
30028c85 VM |
8742 | /* Start work with the hash table. */ |
8743 | ||
8744 | static void | |
9c808aad | 8745 | initiate_bundle_state_table (void) |
30028c85 | 8746 | { |
c203e8a7 | 8747 | bundle_state_table = new hash_table<bundle_state_hasher> (50); |
2130b7fb BS |
8748 | } |
8749 | ||
30028c85 | 8750 | /* Finish work with the hash table. */ |
e4027dab BS |
8751 | |
8752 | static void | |
9c808aad | 8753 | finish_bundle_state_table (void) |
e4027dab | 8754 | { |
c203e8a7 TS |
8755 | delete bundle_state_table; |
8756 | bundle_state_table = NULL; | |
e4027dab BS |
8757 | } |
8758 | ||
30028c85 | 8759 | \f |
a0a7b566 | 8760 | |
30028c85 VM |
8761 | /* The following variable is a insn `nop' used to check bundle states |
8762 | with different number of inserted nops. */ | |
a0a7b566 | 8763 | |
dd3d2b35 | 8764 | static rtx_insn *ia64_nop; |
a0a7b566 | 8765 | |
30028c85 VM |
8766 | /* The following function tries to issue NOPS_NUM nops for the current |
8767 | state without advancing processor cycle. If it failed, the | |
8768 | function returns FALSE and frees the current state. */ | |
8769 | ||
8770 | static int | |
9c808aad | 8771 | try_issue_nops (struct bundle_state *curr_state, int nops_num) |
a0a7b566 | 8772 | { |
30028c85 | 8773 | int i; |
a0a7b566 | 8774 | |
30028c85 VM |
8775 | for (i = 0; i < nops_num; i++) |
8776 | if (state_transition (curr_state->dfa_state, ia64_nop) >= 0) | |
8777 | { | |
8778 | free_bundle_state (curr_state); | |
8779 | return FALSE; | |
8780 | } | |
8781 | return TRUE; | |
8782 | } | |
a0a7b566 | 8783 | |
30028c85 VM |
8784 | /* The following function tries to issue INSN for the current |
8785 | state without advancing processor cycle. If it failed, the | |
8786 | function returns FALSE and frees the current state. */ | |
a0a7b566 | 8787 | |
30028c85 | 8788 | static int |
9c808aad | 8789 | try_issue_insn (struct bundle_state *curr_state, rtx insn) |
30028c85 VM |
8790 | { |
8791 | if (insn && state_transition (curr_state->dfa_state, insn) >= 0) | |
8792 | { | |
8793 | free_bundle_state (curr_state); | |
8794 | return FALSE; | |
8795 | } | |
8796 | return TRUE; | |
8797 | } | |
a0a7b566 | 8798 | |
30028c85 VM |
8799 | /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN |
8800 | starting with ORIGINATOR without advancing processor cycle. If | |
f32360c7 VM |
8801 | TRY_BUNDLE_END_P is TRUE, the function also/only (if |
8802 | ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle. | |
8803 | If it was successful, the function creates new bundle state and | |
8804 | insert into the hash table and into `index_to_bundle_states'. */ | |
a0a7b566 | 8805 | |
30028c85 | 8806 | static void |
9c808aad | 8807 | issue_nops_and_insn (struct bundle_state *originator, int before_nops_num, |
b32d5189 DM |
8808 | rtx_insn *insn, int try_bundle_end_p, |
8809 | int only_bundle_end_p) | |
30028c85 VM |
8810 | { |
8811 | struct bundle_state *curr_state; | |
8812 | ||
8813 | curr_state = get_free_bundle_state (); | |
8814 | memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size); | |
8815 | curr_state->insn = insn; | |
8816 | curr_state->insn_num = originator->insn_num + 1; | |
8817 | curr_state->cost = originator->cost; | |
8818 | curr_state->originator = originator; | |
8819 | curr_state->before_nops_num = before_nops_num; | |
8820 | curr_state->after_nops_num = 0; | |
8821 | curr_state->accumulated_insns_num | |
8822 | = originator->accumulated_insns_num + before_nops_num; | |
8823 | curr_state->branch_deviation = originator->branch_deviation; | |
388092d5 | 8824 | curr_state->middle_bundle_stops = originator->middle_bundle_stops; |
e820471b NS |
8825 | gcc_assert (insn); |
8826 | if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier) | |
30028c85 | 8827 | { |
e820471b | 8828 | gcc_assert (GET_MODE (insn) != TImode); |
30028c85 VM |
8829 | if (!try_issue_nops (curr_state, before_nops_num)) |
8830 | return; | |
8831 | if (!try_issue_insn (curr_state, insn)) | |
8832 | return; | |
8833 | memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size); | |
388092d5 AB |
8834 | if (curr_state->accumulated_insns_num % 3 != 0) |
8835 | curr_state->middle_bundle_stops++; | |
30028c85 VM |
8836 | if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0 |
8837 | && curr_state->accumulated_insns_num % 3 != 0) | |
a0a7b566 | 8838 | { |
30028c85 VM |
8839 | free_bundle_state (curr_state); |
8840 | return; | |
a0a7b566 | 8841 | } |
a0a7b566 | 8842 | } |
30028c85 | 8843 | else if (GET_MODE (insn) != TImode) |
a0a7b566 | 8844 | { |
30028c85 VM |
8845 | if (!try_issue_nops (curr_state, before_nops_num)) |
8846 | return; | |
8847 | if (!try_issue_insn (curr_state, insn)) | |
8848 | return; | |
f32360c7 | 8849 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8850 | gcc_assert (!unknown_for_bundling_p (insn)); |
e820471b | 8851 | |
30028c85 VM |
8852 | if (ia64_safe_type (insn) == TYPE_L) |
8853 | curr_state->accumulated_insns_num++; | |
8854 | } | |
8855 | else | |
8856 | { | |
68e11b42 JW |
8857 | /* If this is an insn that must be first in a group, then don't allow |
8858 | nops to be emitted before it. Currently, alloc is the only such | |
8859 | supported instruction. */ | |
8860 | /* ??? The bundling automatons should handle this for us, but they do | |
8861 | not yet have support for the first_insn attribute. */ | |
8862 | if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES) | |
8863 | { | |
8864 | free_bundle_state (curr_state); | |
8865 | return; | |
8866 | } | |
8867 | ||
30028c85 VM |
8868 | state_transition (curr_state->dfa_state, dfa_pre_cycle_insn); |
8869 | state_transition (curr_state->dfa_state, NULL); | |
8870 | curr_state->cost++; | |
8871 | if (!try_issue_nops (curr_state, before_nops_num)) | |
8872 | return; | |
8873 | if (!try_issue_insn (curr_state, insn)) | |
8874 | return; | |
f32360c7 | 8875 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8876 | if (unknown_for_bundling_p (insn)) |
f32360c7 VM |
8877 | { |
8878 | /* Finish bundle containing asm insn. */ | |
8879 | curr_state->after_nops_num | |
8880 | = 3 - curr_state->accumulated_insns_num % 3; | |
8881 | curr_state->accumulated_insns_num | |
8882 | += 3 - curr_state->accumulated_insns_num % 3; | |
8883 | } | |
8884 | else if (ia64_safe_type (insn) == TYPE_L) | |
30028c85 VM |
8885 | curr_state->accumulated_insns_num++; |
8886 | } | |
8887 | if (ia64_safe_type (insn) == TYPE_B) | |
8888 | curr_state->branch_deviation | |
8889 | += 2 - (curr_state->accumulated_insns_num - 1) % 3; | |
8890 | if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0) | |
8891 | { | |
f32360c7 | 8892 | if (!only_bundle_end_p && insert_bundle_state (curr_state)) |
a0a7b566 | 8893 | { |
30028c85 VM |
8894 | state_t dfa_state; |
8895 | struct bundle_state *curr_state1; | |
8896 | struct bundle_state *allocated_states_chain; | |
8897 | ||
8898 | curr_state1 = get_free_bundle_state (); | |
8899 | dfa_state = curr_state1->dfa_state; | |
8900 | allocated_states_chain = curr_state1->allocated_states_chain; | |
8901 | *curr_state1 = *curr_state; | |
8902 | curr_state1->dfa_state = dfa_state; | |
8903 | curr_state1->allocated_states_chain = allocated_states_chain; | |
8904 | memcpy (curr_state1->dfa_state, curr_state->dfa_state, | |
8905 | dfa_state_size); | |
8906 | curr_state = curr_state1; | |
a0a7b566 | 8907 | } |
30028c85 VM |
8908 | if (!try_issue_nops (curr_state, |
8909 | 3 - curr_state->accumulated_insns_num % 3)) | |
8910 | return; | |
8911 | curr_state->after_nops_num | |
8912 | = 3 - curr_state->accumulated_insns_num % 3; | |
8913 | curr_state->accumulated_insns_num | |
8914 | += 3 - curr_state->accumulated_insns_num % 3; | |
a0a7b566 | 8915 | } |
30028c85 VM |
8916 | if (!insert_bundle_state (curr_state)) |
8917 | free_bundle_state (curr_state); | |
8918 | return; | |
8919 | } | |
e013f3c7 | 8920 | |
30028c85 VM |
8921 | /* The following function returns position in the two window bundle |
8922 | for given STATE. */ | |
8923 | ||
8924 | static int | |
9c808aad | 8925 | get_max_pos (state_t state) |
30028c85 VM |
8926 | { |
8927 | if (cpu_unit_reservation_p (state, pos_6)) | |
8928 | return 6; | |
8929 | else if (cpu_unit_reservation_p (state, pos_5)) | |
8930 | return 5; | |
8931 | else if (cpu_unit_reservation_p (state, pos_4)) | |
8932 | return 4; | |
8933 | else if (cpu_unit_reservation_p (state, pos_3)) | |
8934 | return 3; | |
8935 | else if (cpu_unit_reservation_p (state, pos_2)) | |
8936 | return 2; | |
8937 | else if (cpu_unit_reservation_p (state, pos_1)) | |
8938 | return 1; | |
8939 | else | |
8940 | return 0; | |
a0a7b566 BS |
8941 | } |
8942 | ||
30028c85 VM |
8943 | /* The function returns code of a possible template for given position |
8944 | and state. The function should be called only with 2 values of | |
96ddf8ef VM |
8945 | position equal to 3 or 6. We avoid generating F NOPs by putting |
8946 | templates containing F insns at the end of the template search | |
8947 | because undocumented anomaly in McKinley derived cores which can | |
8948 | cause stalls if an F-unit insn (including a NOP) is issued within a | |
8949 | six-cycle window after reading certain application registers (such | |
8950 | as ar.bsp). Furthermore, power-considerations also argue against | |
8951 | the use of F-unit instructions unless they're really needed. */ | |
2130b7fb | 8952 | |
c237e94a | 8953 | static int |
9c808aad | 8954 | get_template (state_t state, int pos) |
2130b7fb | 8955 | { |
30028c85 | 8956 | switch (pos) |
2130b7fb | 8957 | { |
30028c85 | 8958 | case 3: |
96ddf8ef | 8959 | if (cpu_unit_reservation_p (state, _0mmi_)) |
30028c85 | 8960 | return 1; |
96ddf8ef VM |
8961 | else if (cpu_unit_reservation_p (state, _0mii_)) |
8962 | return 0; | |
30028c85 VM |
8963 | else if (cpu_unit_reservation_p (state, _0mmb_)) |
8964 | return 7; | |
96ddf8ef VM |
8965 | else if (cpu_unit_reservation_p (state, _0mib_)) |
8966 | return 6; | |
8967 | else if (cpu_unit_reservation_p (state, _0mbb_)) | |
8968 | return 5; | |
8969 | else if (cpu_unit_reservation_p (state, _0bbb_)) | |
8970 | return 4; | |
8971 | else if (cpu_unit_reservation_p (state, _0mmf_)) | |
8972 | return 3; | |
8973 | else if (cpu_unit_reservation_p (state, _0mfi_)) | |
8974 | return 2; | |
30028c85 VM |
8975 | else if (cpu_unit_reservation_p (state, _0mfb_)) |
8976 | return 8; | |
8977 | else if (cpu_unit_reservation_p (state, _0mlx_)) | |
8978 | return 9; | |
8979 | else | |
e820471b | 8980 | gcc_unreachable (); |
30028c85 | 8981 | case 6: |
96ddf8ef | 8982 | if (cpu_unit_reservation_p (state, _1mmi_)) |
30028c85 | 8983 | return 1; |
96ddf8ef VM |
8984 | else if (cpu_unit_reservation_p (state, _1mii_)) |
8985 | return 0; | |
30028c85 VM |
8986 | else if (cpu_unit_reservation_p (state, _1mmb_)) |
8987 | return 7; | |
96ddf8ef VM |
8988 | else if (cpu_unit_reservation_p (state, _1mib_)) |
8989 | return 6; | |
8990 | else if (cpu_unit_reservation_p (state, _1mbb_)) | |
8991 | return 5; | |
8992 | else if (cpu_unit_reservation_p (state, _1bbb_)) | |
8993 | return 4; | |
8994 | else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_)) | |
8995 | return 3; | |
8996 | else if (cpu_unit_reservation_p (state, _1mfi_)) | |
8997 | return 2; | |
30028c85 VM |
8998 | else if (cpu_unit_reservation_p (state, _1mfb_)) |
8999 | return 8; | |
9000 | else if (cpu_unit_reservation_p (state, _1mlx_)) | |
9001 | return 9; | |
9002 | else | |
e820471b | 9003 | gcc_unreachable (); |
30028c85 | 9004 | default: |
e820471b | 9005 | gcc_unreachable (); |
2130b7fb | 9006 | } |
30028c85 | 9007 | } |
2130b7fb | 9008 | |
388092d5 | 9009 | /* True when INSN is important for bundling. */ |
7b84aac0 | 9010 | |
388092d5 | 9011 | static bool |
647d790d | 9012 | important_for_bundling_p (rtx_insn *insn) |
388092d5 AB |
9013 | { |
9014 | return (INSN_P (insn) | |
9015 | && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE | |
9016 | && GET_CODE (PATTERN (insn)) != USE | |
9017 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
9018 | } | |
9019 | ||
30028c85 VM |
9020 | /* The following function returns an insn important for insn bundling |
9021 | followed by INSN and before TAIL. */ | |
a0a7b566 | 9022 | |
b32d5189 DM |
9023 | static rtx_insn * |
9024 | get_next_important_insn (rtx_insn *insn, rtx_insn *tail) | |
30028c85 VM |
9025 | { |
9026 | for (; insn && insn != tail; insn = NEXT_INSN (insn)) | |
388092d5 | 9027 | if (important_for_bundling_p (insn)) |
30028c85 | 9028 | return insn; |
b32d5189 | 9029 | return NULL; |
30028c85 VM |
9030 | } |
9031 | ||
7b84aac0 EB |
9032 | /* True when INSN is unknown, but important, for bundling. */ |
9033 | ||
9034 | static bool | |
647d790d | 9035 | unknown_for_bundling_p (rtx_insn *insn) |
7b84aac0 EB |
9036 | { |
9037 | return (INSN_P (insn) | |
9038 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN | |
9039 | && GET_CODE (PATTERN (insn)) != USE | |
9040 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
9041 | } | |
9042 | ||
4a4cd49c JJ |
9043 | /* Add a bundle selector TEMPLATE0 before INSN. */ |
9044 | ||
9045 | static void | |
b32d5189 | 9046 | ia64_add_bundle_selector_before (int template0, rtx_insn *insn) |
4a4cd49c JJ |
9047 | { |
9048 | rtx b = gen_bundle_selector (GEN_INT (template0)); | |
9049 | ||
9050 | ia64_emit_insn_before (b, insn); | |
9051 | #if NR_BUNDLES == 10 | |
9052 | if ((template0 == 4 || template0 == 5) | |
d5fabb58 | 9053 | && ia64_except_unwind_info (&global_options) == UI_TARGET) |
4a4cd49c JJ |
9054 | { |
9055 | int i; | |
9056 | rtx note = NULL_RTX; | |
9057 | ||
9058 | /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the | |
9059 | first or second slot. If it is and has REG_EH_NOTE set, copy it | |
9060 | to following nops, as br.call sets rp to the address of following | |
9061 | bundle and therefore an EH region end must be on a bundle | |
9062 | boundary. */ | |
9063 | insn = PREV_INSN (insn); | |
9064 | for (i = 0; i < 3; i++) | |
9065 | { | |
9066 | do | |
9067 | insn = next_active_insn (insn); | |
b64925dc | 9068 | while (NONJUMP_INSN_P (insn) |
4a4cd49c | 9069 | && get_attr_empty (insn) == EMPTY_YES); |
b64925dc | 9070 | if (CALL_P (insn)) |
4a4cd49c JJ |
9071 | note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); |
9072 | else if (note) | |
9073 | { | |
9074 | int code; | |
9075 | ||
9076 | gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop | |
9077 | || code == CODE_FOR_nop_b); | |
9078 | if (find_reg_note (insn, REG_EH_REGION, NULL_RTX)) | |
9079 | note = NULL_RTX; | |
9080 | else | |
bbbbb16a | 9081 | add_reg_note (insn, REG_EH_REGION, XEXP (note, 0)); |
4a4cd49c JJ |
9082 | } |
9083 | } | |
9084 | } | |
9085 | #endif | |
9086 | } | |
9087 | ||
c856f536 VM |
9088 | /* The following function does insn bundling. Bundling means |
9089 | inserting templates and nop insns to fit insn groups into permitted | |
9090 | templates. Instruction scheduling uses NDFA (non-deterministic | |
9091 | finite automata) encoding informations about the templates and the | |
9092 | inserted nops. Nondeterminism of the automata permits follows | |
9093 | all possible insn sequences very fast. | |
9094 | ||
9095 | Unfortunately it is not possible to get information about inserting | |
9096 | nop insns and used templates from the automata states. The | |
9097 | automata only says that we can issue an insn possibly inserting | |
9098 | some nops before it and using some template. Therefore insn | |
9099 | bundling in this function is implemented by using DFA | |
048d0d36 | 9100 | (deterministic finite automata). We follow all possible insn |
c856f536 VM |
9101 | sequences by inserting 0-2 nops (that is what the NDFA describe for |
9102 | insn scheduling) before/after each insn being bundled. We know the | |
9103 | start of simulated processor cycle from insn scheduling (insn | |
9104 | starting a new cycle has TImode). | |
9105 | ||
9106 | Simple implementation of insn bundling would create enormous | |
9107 | number of possible insn sequences satisfying information about new | |
9108 | cycle ticks taken from the insn scheduling. To make the algorithm | |
9109 | practical we use dynamic programming. Each decision (about | |
9110 | inserting nops and implicitly about previous decisions) is described | |
9111 | by structure bundle_state (see above). If we generate the same | |
9112 | bundle state (key is automaton state after issuing the insns and | |
9113 | nops for it), we reuse already generated one. As consequence we | |
1e5f1716 | 9114 | reject some decisions which cannot improve the solution and |
c856f536 VM |
9115 | reduce memory for the algorithm. |
9116 | ||
9117 | When we reach the end of EBB (extended basic block), we choose the | |
9118 | best sequence and then, moving back in EBB, insert templates for | |
9119 | the best alternative. The templates are taken from querying | |
9120 | automaton state for each insn in chosen bundle states. | |
9121 | ||
9122 | So the algorithm makes two (forward and backward) passes through | |
7400e46b | 9123 | EBB. */ |
a0a7b566 | 9124 | |
30028c85 | 9125 | static void |
b32d5189 | 9126 | bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) |
30028c85 VM |
9127 | { |
9128 | struct bundle_state *curr_state, *next_state, *best_state; | |
b32d5189 | 9129 | rtx_insn *insn, *next_insn; |
30028c85 | 9130 | int insn_num; |
f32360c7 | 9131 | int i, bundle_end_p, only_bundle_end_p, asm_p; |
74601584 | 9132 | int pos = 0, max_pos, template0, template1; |
b32d5189 | 9133 | rtx_insn *b; |
30028c85 | 9134 | enum attr_type type; |
2d1b811d | 9135 | |
30028c85 | 9136 | insn_num = 0; |
c856f536 | 9137 | /* Count insns in the EBB. */ |
30028c85 VM |
9138 | for (insn = NEXT_INSN (prev_head_insn); |
9139 | insn && insn != tail; | |
9140 | insn = NEXT_INSN (insn)) | |
9141 | if (INSN_P (insn)) | |
9142 | insn_num++; | |
9143 | if (insn_num == 0) | |
9144 | return; | |
9145 | bundling_p = 1; | |
9146 | dfa_clean_insn_cache (); | |
9147 | initiate_bundle_state_table (); | |
5ead67f6 | 9148 | index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2); |
ff482c8d | 9149 | /* First (forward) pass -- generation of bundle states. */ |
30028c85 VM |
9150 | curr_state = get_free_bundle_state (); |
9151 | curr_state->insn = NULL; | |
9152 | curr_state->before_nops_num = 0; | |
9153 | curr_state->after_nops_num = 0; | |
9154 | curr_state->insn_num = 0; | |
9155 | curr_state->cost = 0; | |
9156 | curr_state->accumulated_insns_num = 0; | |
9157 | curr_state->branch_deviation = 0; | |
388092d5 | 9158 | curr_state->middle_bundle_stops = 0; |
30028c85 VM |
9159 | curr_state->next = NULL; |
9160 | curr_state->originator = NULL; | |
9161 | state_reset (curr_state->dfa_state); | |
9162 | index_to_bundle_states [0] = curr_state; | |
9163 | insn_num = 0; | |
c856f536 | 9164 | /* Shift cycle mark if it is put on insn which could be ignored. */ |
30028c85 VM |
9165 | for (insn = NEXT_INSN (prev_head_insn); |
9166 | insn != tail; | |
9167 | insn = NEXT_INSN (insn)) | |
9168 | if (INSN_P (insn) | |
7b84aac0 | 9169 | && !important_for_bundling_p (insn) |
30028c85 | 9170 | && GET_MODE (insn) == TImode) |
2130b7fb | 9171 | { |
30028c85 VM |
9172 | PUT_MODE (insn, VOIDmode); |
9173 | for (next_insn = NEXT_INSN (insn); | |
9174 | next_insn != tail; | |
9175 | next_insn = NEXT_INSN (next_insn)) | |
7b84aac0 | 9176 | if (important_for_bundling_p (next_insn) |
388092d5 | 9177 | && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier) |
30028c85 VM |
9178 | { |
9179 | PUT_MODE (next_insn, TImode); | |
9180 | break; | |
9181 | } | |
2130b7fb | 9182 | } |
048d0d36 | 9183 | /* Forward pass: generation of bundle states. */ |
30028c85 VM |
9184 | for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail); |
9185 | insn != NULL_RTX; | |
9186 | insn = next_insn) | |
1ad72cef | 9187 | { |
7b84aac0 | 9188 | gcc_assert (important_for_bundling_p (insn)); |
f32360c7 | 9189 | type = ia64_safe_type (insn); |
30028c85 VM |
9190 | next_insn = get_next_important_insn (NEXT_INSN (insn), tail); |
9191 | insn_num++; | |
9192 | index_to_bundle_states [insn_num] = NULL; | |
9193 | for (curr_state = index_to_bundle_states [insn_num - 1]; | |
9194 | curr_state != NULL; | |
9195 | curr_state = next_state) | |
f83594c4 | 9196 | { |
30028c85 | 9197 | pos = curr_state->accumulated_insns_num % 3; |
30028c85 | 9198 | next_state = curr_state->next; |
c856f536 VM |
9199 | /* We must fill up the current bundle in order to start a |
9200 | subsequent asm insn in a new bundle. Asm insn is always | |
9201 | placed in a separate bundle. */ | |
f32360c7 VM |
9202 | only_bundle_end_p |
9203 | = (next_insn != NULL_RTX | |
9204 | && INSN_CODE (insn) == CODE_FOR_insn_group_barrier | |
7b84aac0 | 9205 | && unknown_for_bundling_p (next_insn)); |
c856f536 VM |
9206 | /* We may fill up the current bundle if it is the cycle end |
9207 | without a group barrier. */ | |
30028c85 | 9208 | bundle_end_p |
f32360c7 | 9209 | = (only_bundle_end_p || next_insn == NULL_RTX |
30028c85 VM |
9210 | || (GET_MODE (next_insn) == TImode |
9211 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier)); | |
9212 | if (type == TYPE_F || type == TYPE_B || type == TYPE_L | |
7400e46b | 9213 | || type == TYPE_S) |
f32360c7 VM |
9214 | issue_nops_and_insn (curr_state, 2, insn, bundle_end_p, |
9215 | only_bundle_end_p); | |
9216 | issue_nops_and_insn (curr_state, 1, insn, bundle_end_p, | |
9217 | only_bundle_end_p); | |
9218 | issue_nops_and_insn (curr_state, 0, insn, bundle_end_p, | |
9219 | only_bundle_end_p); | |
f83594c4 | 9220 | } |
e820471b | 9221 | gcc_assert (index_to_bundle_states [insn_num]); |
30028c85 VM |
9222 | for (curr_state = index_to_bundle_states [insn_num]; |
9223 | curr_state != NULL; | |
9224 | curr_state = curr_state->next) | |
9225 | if (verbose >= 2 && dump) | |
9226 | { | |
c856f536 VM |
9227 | /* This structure is taken from generated code of the |
9228 | pipeline hazard recognizer (see file insn-attrtab.c). | |
9229 | Please don't forget to change the structure if a new | |
9230 | automaton is added to .md file. */ | |
30028c85 VM |
9231 | struct DFA_chip |
9232 | { | |
9233 | unsigned short one_automaton_state; | |
9234 | unsigned short oneb_automaton_state; | |
9235 | unsigned short two_automaton_state; | |
9236 | unsigned short twob_automaton_state; | |
9237 | }; | |
9c808aad | 9238 | |
30028c85 VM |
9239 | fprintf |
9240 | (dump, | |
388092d5 | 9241 | "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n", |
30028c85 VM |
9242 | curr_state->unique_num, |
9243 | (curr_state->originator == NULL | |
9244 | ? -1 : curr_state->originator->unique_num), | |
9245 | curr_state->cost, | |
9246 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9247 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9248 | curr_state->middle_bundle_stops, |
7400e46b | 9249 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 VM |
9250 | INSN_UID (insn)); |
9251 | } | |
1ad72cef | 9252 | } |
e820471b NS |
9253 | |
9254 | /* We should find a solution because the 2nd insn scheduling has | |
9255 | found one. */ | |
9256 | gcc_assert (index_to_bundle_states [insn_num]); | |
c856f536 | 9257 | /* Find a state corresponding to the best insn sequence. */ |
30028c85 VM |
9258 | best_state = NULL; |
9259 | for (curr_state = index_to_bundle_states [insn_num]; | |
9260 | curr_state != NULL; | |
9261 | curr_state = curr_state->next) | |
c856f536 VM |
9262 | /* We are just looking at the states with fully filled up last |
9263 | bundle. The first we prefer insn sequences with minimal cost | |
9264 | then with minimal inserted nops and finally with branch insns | |
9265 | placed in the 3rd slots. */ | |
30028c85 VM |
9266 | if (curr_state->accumulated_insns_num % 3 == 0 |
9267 | && (best_state == NULL || best_state->cost > curr_state->cost | |
9268 | || (best_state->cost == curr_state->cost | |
9269 | && (curr_state->accumulated_insns_num | |
9270 | < best_state->accumulated_insns_num | |
9271 | || (curr_state->accumulated_insns_num | |
9272 | == best_state->accumulated_insns_num | |
388092d5 AB |
9273 | && (curr_state->branch_deviation |
9274 | < best_state->branch_deviation | |
9275 | || (curr_state->branch_deviation | |
9276 | == best_state->branch_deviation | |
9277 | && curr_state->middle_bundle_stops | |
9278 | < best_state->middle_bundle_stops))))))) | |
30028c85 | 9279 | best_state = curr_state; |
c856f536 | 9280 | /* Second (backward) pass: adding nops and templates. */ |
388092d5 | 9281 | gcc_assert (best_state); |
30028c85 VM |
9282 | insn_num = best_state->before_nops_num; |
9283 | template0 = template1 = -1; | |
9284 | for (curr_state = best_state; | |
9285 | curr_state->originator != NULL; | |
9286 | curr_state = curr_state->originator) | |
9287 | { | |
9288 | insn = curr_state->insn; | |
7b84aac0 | 9289 | asm_p = unknown_for_bundling_p (insn); |
30028c85 VM |
9290 | insn_num++; |
9291 | if (verbose >= 2 && dump) | |
2130b7fb | 9292 | { |
30028c85 VM |
9293 | struct DFA_chip |
9294 | { | |
9295 | unsigned short one_automaton_state; | |
9296 | unsigned short oneb_automaton_state; | |
9297 | unsigned short two_automaton_state; | |
9298 | unsigned short twob_automaton_state; | |
9299 | }; | |
9c808aad | 9300 | |
30028c85 VM |
9301 | fprintf |
9302 | (dump, | |
388092d5 | 9303 | "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n", |
30028c85 VM |
9304 | curr_state->unique_num, |
9305 | (curr_state->originator == NULL | |
9306 | ? -1 : curr_state->originator->unique_num), | |
9307 | curr_state->cost, | |
9308 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9309 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9310 | curr_state->middle_bundle_stops, |
7400e46b | 9311 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 | 9312 | INSN_UID (insn)); |
2130b7fb | 9313 | } |
c856f536 VM |
9314 | /* Find the position in the current bundle window. The window can |
9315 | contain at most two bundles. Two bundle window means that | |
9316 | the processor will make two bundle rotation. */ | |
30028c85 | 9317 | max_pos = get_max_pos (curr_state->dfa_state); |
c856f536 VM |
9318 | if (max_pos == 6 |
9319 | /* The following (negative template number) means that the | |
9320 | processor did one bundle rotation. */ | |
9321 | || (max_pos == 3 && template0 < 0)) | |
2130b7fb | 9322 | { |
c856f536 VM |
9323 | /* We are at the end of the window -- find template(s) for |
9324 | its bundle(s). */ | |
30028c85 VM |
9325 | pos = max_pos; |
9326 | if (max_pos == 3) | |
9327 | template0 = get_template (curr_state->dfa_state, 3); | |
9328 | else | |
9329 | { | |
9330 | template1 = get_template (curr_state->dfa_state, 3); | |
9331 | template0 = get_template (curr_state->dfa_state, 6); | |
9332 | } | |
9333 | } | |
9334 | if (max_pos > 3 && template1 < 0) | |
c856f536 | 9335 | /* It may happen when we have the stop inside a bundle. */ |
30028c85 | 9336 | { |
e820471b | 9337 | gcc_assert (pos <= 3); |
30028c85 VM |
9338 | template1 = get_template (curr_state->dfa_state, 3); |
9339 | pos += 3; | |
9340 | } | |
f32360c7 | 9341 | if (!asm_p) |
c856f536 | 9342 | /* Emit nops after the current insn. */ |
f32360c7 VM |
9343 | for (i = 0; i < curr_state->after_nops_num; i++) |
9344 | { | |
b32d5189 DM |
9345 | rtx nop_pat = gen_nop (); |
9346 | rtx_insn *nop = emit_insn_after (nop_pat, insn); | |
f32360c7 | 9347 | pos--; |
e820471b | 9348 | gcc_assert (pos >= 0); |
f32360c7 VM |
9349 | if (pos % 3 == 0) |
9350 | { | |
c856f536 VM |
9351 | /* We are at the start of a bundle: emit the template |
9352 | (it should be defined). */ | |
e820471b | 9353 | gcc_assert (template0 >= 0); |
4a4cd49c | 9354 | ia64_add_bundle_selector_before (template0, nop); |
c856f536 VM |
9355 | /* If we have two bundle window, we make one bundle |
9356 | rotation. Otherwise template0 will be undefined | |
9357 | (negative value). */ | |
f32360c7 VM |
9358 | template0 = template1; |
9359 | template1 = -1; | |
9360 | } | |
9361 | } | |
c856f536 VM |
9362 | /* Move the position backward in the window. Group barrier has |
9363 | no slot. Asm insn takes all bundle. */ | |
30028c85 | 9364 | if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier |
7b84aac0 | 9365 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9366 | pos--; |
c856f536 | 9367 | /* Long insn takes 2 slots. */ |
30028c85 VM |
9368 | if (ia64_safe_type (insn) == TYPE_L) |
9369 | pos--; | |
e820471b | 9370 | gcc_assert (pos >= 0); |
30028c85 VM |
9371 | if (pos % 3 == 0 |
9372 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier | |
7b84aac0 | 9373 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9374 | { |
c856f536 VM |
9375 | /* The current insn is at the bundle start: emit the |
9376 | template. */ | |
e820471b | 9377 | gcc_assert (template0 >= 0); |
4a4cd49c | 9378 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9379 | b = PREV_INSN (insn); |
9380 | insn = b; | |
68776c43 | 9381 | /* See comment above in analogous place for emitting nops |
c856f536 | 9382 | after the insn. */ |
30028c85 VM |
9383 | template0 = template1; |
9384 | template1 = -1; | |
9385 | } | |
c856f536 | 9386 | /* Emit nops after the current insn. */ |
30028c85 VM |
9387 | for (i = 0; i < curr_state->before_nops_num; i++) |
9388 | { | |
b32d5189 DM |
9389 | rtx nop_pat = gen_nop (); |
9390 | ia64_emit_insn_before (nop_pat, insn); | |
9391 | rtx_insn *nop = PREV_INSN (insn); | |
30028c85 VM |
9392 | insn = nop; |
9393 | pos--; | |
e820471b | 9394 | gcc_assert (pos >= 0); |
30028c85 VM |
9395 | if (pos % 3 == 0) |
9396 | { | |
68776c43 | 9397 | /* See comment above in analogous place for emitting nops |
c856f536 | 9398 | after the insn. */ |
e820471b | 9399 | gcc_assert (template0 >= 0); |
4a4cd49c | 9400 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9401 | b = PREV_INSN (insn); |
9402 | insn = b; | |
9403 | template0 = template1; | |
9404 | template1 = -1; | |
9405 | } | |
2130b7fb BS |
9406 | } |
9407 | } | |
388092d5 | 9408 | |
e28c2052 MM |
9409 | if (flag_checking) |
9410 | { | |
9411 | /* Assert right calculation of middle_bundle_stops. */ | |
9412 | int num = best_state->middle_bundle_stops; | |
9413 | bool start_bundle = true, end_bundle = false; | |
388092d5 | 9414 | |
e28c2052 MM |
9415 | for (insn = NEXT_INSN (prev_head_insn); |
9416 | insn && insn != tail; | |
9417 | insn = NEXT_INSN (insn)) | |
9418 | { | |
9419 | if (!INSN_P (insn)) | |
9420 | continue; | |
9421 | if (recog_memoized (insn) == CODE_FOR_bundle_selector) | |
9422 | start_bundle = true; | |
9423 | else | |
9424 | { | |
9425 | rtx_insn *next_insn; | |
9426 | ||
9427 | for (next_insn = NEXT_INSN (insn); | |
9428 | next_insn && next_insn != tail; | |
9429 | next_insn = NEXT_INSN (next_insn)) | |
9430 | if (INSN_P (next_insn) | |
9431 | && (ia64_safe_itanium_class (next_insn) | |
9432 | != ITANIUM_CLASS_IGNORE | |
9433 | || recog_memoized (next_insn) | |
9434 | == CODE_FOR_bundle_selector) | |
9435 | && GET_CODE (PATTERN (next_insn)) != USE | |
9436 | && GET_CODE (PATTERN (next_insn)) != CLOBBER) | |
9437 | break; | |
9438 | ||
9439 | end_bundle = next_insn == NULL_RTX | |
9440 | || next_insn == tail | |
9441 | || (INSN_P (next_insn) | |
9442 | && recog_memoized (next_insn) == CODE_FOR_bundle_selector); | |
9443 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier | |
9444 | && !start_bundle && !end_bundle | |
9445 | && next_insn | |
9446 | && !unknown_for_bundling_p (next_insn)) | |
9447 | num--; | |
9448 | ||
9449 | start_bundle = false; | |
9450 | } | |
9451 | } | |
388092d5 | 9452 | |
e28c2052 MM |
9453 | gcc_assert (num == 0); |
9454 | } | |
388092d5 | 9455 | |
30028c85 VM |
9456 | free (index_to_bundle_states); |
9457 | finish_bundle_state_table (); | |
9458 | bundling_p = 0; | |
9459 | dfa_clean_insn_cache (); | |
2130b7fb | 9460 | } |
c65ebc55 | 9461 | |
30028c85 VM |
9462 | /* The following function is called at the end of scheduling BB or |
9463 | EBB. After reload, it inserts stop bits and does insn bundling. */ | |
9464 | ||
9465 | static void | |
9c808aad | 9466 | ia64_sched_finish (FILE *dump, int sched_verbose) |
c237e94a | 9467 | { |
30028c85 VM |
9468 | if (sched_verbose) |
9469 | fprintf (dump, "// Finishing schedule.\n"); | |
9470 | if (!reload_completed) | |
9471 | return; | |
9472 | if (reload_completed) | |
9473 | { | |
9474 | final_emit_insn_group_barriers (dump); | |
9475 | bundling (dump, sched_verbose, current_sched_info->prev_head, | |
9476 | current_sched_info->next_tail); | |
9477 | if (sched_verbose && dump) | |
9478 | fprintf (dump, "// finishing %d-%d\n", | |
9479 | INSN_UID (NEXT_INSN (current_sched_info->prev_head)), | |
9480 | INSN_UID (PREV_INSN (current_sched_info->next_tail))); | |
9c808aad | 9481 | |
30028c85 VM |
9482 | return; |
9483 | } | |
c237e94a ZW |
9484 | } |
9485 | ||
30028c85 | 9486 | /* The following function inserts stop bits in scheduled BB or EBB. */ |
2130b7fb | 9487 | |
30028c85 | 9488 | static void |
9c808aad | 9489 | final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
2130b7fb | 9490 | { |
dd3d2b35 | 9491 | rtx_insn *insn; |
30028c85 | 9492 | int need_barrier_p = 0; |
388092d5 | 9493 | int seen_good_insn = 0; |
2130b7fb | 9494 | |
30028c85 | 9495 | init_insn_group_barriers (); |
2130b7fb | 9496 | |
30028c85 VM |
9497 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
9498 | insn != current_sched_info->next_tail; | |
9499 | insn = NEXT_INSN (insn)) | |
9500 | { | |
b64925dc | 9501 | if (BARRIER_P (insn)) |
b395ddbe | 9502 | { |
dd3d2b35 | 9503 | rtx_insn *last = prev_active_insn (insn); |
14d118d6 | 9504 | |
30028c85 | 9505 | if (! last) |
b395ddbe | 9506 | continue; |
34f0d87a | 9507 | if (JUMP_TABLE_DATA_P (last)) |
30028c85 VM |
9508 | last = prev_active_insn (last); |
9509 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9510 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
2130b7fb | 9511 | |
30028c85 | 9512 | init_insn_group_barriers (); |
388092d5 | 9513 | seen_good_insn = 0; |
30028c85 | 9514 | need_barrier_p = 0; |
b395ddbe | 9515 | } |
b5b8b0ac | 9516 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb | 9517 | { |
30028c85 | 9518 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
2130b7fb | 9519 | { |
30028c85 | 9520 | init_insn_group_barriers (); |
388092d5 | 9521 | seen_good_insn = 0; |
30028c85 | 9522 | need_barrier_p = 0; |
c65ebc55 | 9523 | } |
388092d5 AB |
9524 | else if (need_barrier_p || group_barrier_needed (insn) |
9525 | || (mflag_sched_stop_bits_after_every_cycle | |
9526 | && GET_MODE (insn) == TImode | |
9527 | && seen_good_insn)) | |
2130b7fb | 9528 | { |
30028c85 VM |
9529 | if (TARGET_EARLY_STOP_BITS) |
9530 | { | |
dd3d2b35 | 9531 | rtx_insn *last; |
9c808aad | 9532 | |
30028c85 VM |
9533 | for (last = insn; |
9534 | last != current_sched_info->prev_head; | |
9535 | last = PREV_INSN (last)) | |
9536 | if (INSN_P (last) && GET_MODE (last) == TImode | |
9537 | && stops_p [INSN_UID (last)]) | |
9538 | break; | |
9539 | if (last == current_sched_info->prev_head) | |
9540 | last = insn; | |
9541 | last = prev_active_insn (last); | |
9542 | if (last | |
9543 | && recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9544 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), | |
9545 | last); | |
9546 | init_insn_group_barriers (); | |
9547 | for (last = NEXT_INSN (last); | |
9548 | last != insn; | |
9549 | last = NEXT_INSN (last)) | |
9550 | if (INSN_P (last)) | |
388092d5 AB |
9551 | { |
9552 | group_barrier_needed (last); | |
9553 | if (recog_memoized (last) >= 0 | |
9554 | && important_for_bundling_p (last)) | |
9555 | seen_good_insn = 1; | |
9556 | } | |
30028c85 VM |
9557 | } |
9558 | else | |
9559 | { | |
9560 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), | |
9561 | insn); | |
9562 | init_insn_group_barriers (); | |
388092d5 | 9563 | seen_good_insn = 0; |
30028c85 | 9564 | } |
c1bc6ca8 | 9565 | group_barrier_needed (insn); |
388092d5 AB |
9566 | if (recog_memoized (insn) >= 0 |
9567 | && important_for_bundling_p (insn)) | |
9568 | seen_good_insn = 1; | |
2130b7fb | 9569 | } |
388092d5 AB |
9570 | else if (recog_memoized (insn) >= 0 |
9571 | && important_for_bundling_p (insn)) | |
034288ef | 9572 | seen_good_insn = 1; |
b64925dc | 9573 | need_barrier_p = (CALL_P (insn) || unknown_for_bundling_p (insn)); |
c65ebc55 | 9574 | } |
2130b7fb | 9575 | } |
30028c85 | 9576 | } |
2130b7fb | 9577 | |
30028c85 | 9578 | \f |
2130b7fb | 9579 | |
a4d05547 | 9580 | /* If the following function returns TRUE, we will use the DFA |
30028c85 | 9581 | insn scheduler. */ |
2130b7fb | 9582 | |
c237e94a | 9583 | static int |
9c808aad | 9584 | ia64_first_cycle_multipass_dfa_lookahead (void) |
2130b7fb | 9585 | { |
30028c85 VM |
9586 | return (reload_completed ? 6 : 4); |
9587 | } | |
2130b7fb | 9588 | |
30028c85 | 9589 | /* The following function initiates variable `dfa_pre_cycle_insn'. */ |
2130b7fb | 9590 | |
30028c85 | 9591 | static void |
9c808aad | 9592 | ia64_init_dfa_pre_cycle_insn (void) |
30028c85 VM |
9593 | { |
9594 | if (temp_dfa_state == NULL) | |
2130b7fb | 9595 | { |
30028c85 VM |
9596 | dfa_state_size = state_size (); |
9597 | temp_dfa_state = xmalloc (dfa_state_size); | |
9598 | prev_cycle_state = xmalloc (dfa_state_size); | |
2130b7fb | 9599 | } |
30028c85 | 9600 | dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ()); |
0f82e5c9 | 9601 | SET_PREV_INSN (dfa_pre_cycle_insn) = SET_NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX; |
30028c85 VM |
9602 | recog_memoized (dfa_pre_cycle_insn); |
9603 | dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3))); | |
0f82e5c9 | 9604 | SET_PREV_INSN (dfa_stop_insn) = SET_NEXT_INSN (dfa_stop_insn) = NULL_RTX; |
30028c85 VM |
9605 | recog_memoized (dfa_stop_insn); |
9606 | } | |
2130b7fb | 9607 | |
30028c85 VM |
9608 | /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN |
9609 | used by the DFA insn scheduler. */ | |
2130b7fb | 9610 | |
30028c85 | 9611 | static rtx |
9c808aad | 9612 | ia64_dfa_pre_cycle_insn (void) |
30028c85 VM |
9613 | { |
9614 | return dfa_pre_cycle_insn; | |
9615 | } | |
2130b7fb | 9616 | |
30028c85 VM |
9617 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9618 | ld) produces address for CONSUMER (of type st or stf). */ | |
2130b7fb | 9619 | |
30028c85 | 9620 | int |
647d790d | 9621 | ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) |
30028c85 VM |
9622 | { |
9623 | rtx dest, reg, mem; | |
2130b7fb | 9624 | |
e820471b | 9625 | gcc_assert (producer && consumer); |
30028c85 | 9626 | dest = ia64_single_set (producer); |
e820471b NS |
9627 | gcc_assert (dest); |
9628 | reg = SET_DEST (dest); | |
9629 | gcc_assert (reg); | |
30028c85 VM |
9630 | if (GET_CODE (reg) == SUBREG) |
9631 | reg = SUBREG_REG (reg); | |
e820471b NS |
9632 | gcc_assert (GET_CODE (reg) == REG); |
9633 | ||
30028c85 | 9634 | dest = ia64_single_set (consumer); |
e820471b NS |
9635 | gcc_assert (dest); |
9636 | mem = SET_DEST (dest); | |
9637 | gcc_assert (mem && GET_CODE (mem) == MEM); | |
30028c85 | 9638 | return reg_mentioned_p (reg, mem); |
2130b7fb BS |
9639 | } |
9640 | ||
30028c85 VM |
9641 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9642 | ld) produces address for CONSUMER (of type ld or fld). */ | |
2130b7fb | 9643 | |
30028c85 | 9644 | int |
647d790d | 9645 | ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) |
2130b7fb | 9646 | { |
30028c85 VM |
9647 | rtx dest, src, reg, mem; |
9648 | ||
e820471b | 9649 | gcc_assert (producer && consumer); |
30028c85 | 9650 | dest = ia64_single_set (producer); |
e820471b NS |
9651 | gcc_assert (dest); |
9652 | reg = SET_DEST (dest); | |
9653 | gcc_assert (reg); | |
30028c85 VM |
9654 | if (GET_CODE (reg) == SUBREG) |
9655 | reg = SUBREG_REG (reg); | |
e820471b NS |
9656 | gcc_assert (GET_CODE (reg) == REG); |
9657 | ||
30028c85 | 9658 | src = ia64_single_set (consumer); |
e820471b NS |
9659 | gcc_assert (src); |
9660 | mem = SET_SRC (src); | |
9661 | gcc_assert (mem); | |
048d0d36 | 9662 | |
30028c85 VM |
9663 | if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0) |
9664 | mem = XVECEXP (mem, 0, 0); | |
048d0d36 | 9665 | else if (GET_CODE (mem) == IF_THEN_ELSE) |
917f1b7e | 9666 | /* ??? Is this bypass necessary for ld.c? */ |
048d0d36 MK |
9667 | { |
9668 | gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR); | |
9669 | mem = XEXP (mem, 1); | |
9670 | } | |
9671 | ||
30028c85 VM |
9672 | while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND) |
9673 | mem = XEXP (mem, 0); | |
ef1ecf87 | 9674 | |
048d0d36 MK |
9675 | if (GET_CODE (mem) == UNSPEC) |
9676 | { | |
9677 | int c = XINT (mem, 1); | |
9678 | ||
388092d5 AB |
9679 | gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A |
9680 | || c == UNSPEC_LDSA); | |
048d0d36 MK |
9681 | mem = XVECEXP (mem, 0, 0); |
9682 | } | |
9683 | ||
ef1ecf87 | 9684 | /* Note that LO_SUM is used for GOT loads. */ |
e820471b | 9685 | gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM); |
ef1ecf87 | 9686 | |
30028c85 VM |
9687 | return reg_mentioned_p (reg, mem); |
9688 | } | |
9689 | ||
9690 | /* The following function returns TRUE if INSN produces address for a | |
9691 | load/store insn. We will place such insns into M slot because it | |
ff482c8d | 9692 | decreases its latency time. */ |
30028c85 VM |
9693 | |
9694 | int | |
9c808aad | 9695 | ia64_produce_address_p (rtx insn) |
30028c85 VM |
9696 | { |
9697 | return insn->call; | |
2130b7fb | 9698 | } |
30028c85 | 9699 | |
2130b7fb | 9700 | \f |
3b572406 RH |
9701 | /* Emit pseudo-ops for the assembler to describe predicate relations. |
9702 | At present this assumes that we only consider predicate pairs to | |
9703 | be mutex, and that the assembler can deduce proper values from | |
9704 | straight-line code. */ | |
9705 | ||
9706 | static void | |
9c808aad | 9707 | emit_predicate_relation_info (void) |
3b572406 | 9708 | { |
e0082a72 | 9709 | basic_block bb; |
3b572406 | 9710 | |
4f42035e | 9711 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
3b572406 | 9712 | { |
3b572406 | 9713 | int r; |
dd3d2b35 | 9714 | rtx_insn *head = BB_HEAD (bb); |
3b572406 RH |
9715 | |
9716 | /* We only need such notes at code labels. */ | |
b64925dc | 9717 | if (! LABEL_P (head)) |
3b572406 | 9718 | continue; |
740aeb38 | 9719 | if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head))) |
3b572406 RH |
9720 | head = NEXT_INSN (head); |
9721 | ||
9f3b8452 RH |
9722 | /* Skip p0, which may be thought to be live due to (reg:DI p0) |
9723 | grabbing the entire block of predicate registers. */ | |
9724 | for (r = PR_REG (2); r < PR_REG (64); r += 2) | |
6fb5fa3c | 9725 | if (REGNO_REG_SET_P (df_get_live_in (bb), r)) |
3b572406 | 9726 | { |
f2f90c63 | 9727 | rtx p = gen_rtx_REG (BImode, r); |
dd3d2b35 | 9728 | rtx_insn *n = emit_insn_after (gen_pred_rel_mutex (p), head); |
a813c111 | 9729 | if (head == BB_END (bb)) |
1130d5e3 | 9730 | BB_END (bb) = n; |
3b572406 RH |
9731 | head = n; |
9732 | } | |
9733 | } | |
ca3920ad JW |
9734 | |
9735 | /* Look for conditional calls that do not return, and protect predicate | |
9736 | relations around them. Otherwise the assembler will assume the call | |
9737 | returns, and complain about uses of call-clobbered predicates after | |
9738 | the call. */ | |
4f42035e | 9739 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
ca3920ad | 9740 | { |
dd3d2b35 | 9741 | rtx_insn *insn = BB_HEAD (bb); |
9c808aad | 9742 | |
ca3920ad JW |
9743 | while (1) |
9744 | { | |
b64925dc | 9745 | if (CALL_P (insn) |
ca3920ad JW |
9746 | && GET_CODE (PATTERN (insn)) == COND_EXEC |
9747 | && find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
9748 | { | |
dd3d2b35 DM |
9749 | rtx_insn *b = |
9750 | emit_insn_before (gen_safe_across_calls_all (), insn); | |
9751 | rtx_insn *a = emit_insn_after (gen_safe_across_calls_normal (), insn); | |
a813c111 | 9752 | if (BB_HEAD (bb) == insn) |
1130d5e3 | 9753 | BB_HEAD (bb) = b; |
a813c111 | 9754 | if (BB_END (bb) == insn) |
1130d5e3 | 9755 | BB_END (bb) = a; |
ca3920ad | 9756 | } |
9c808aad | 9757 | |
a813c111 | 9758 | if (insn == BB_END (bb)) |
ca3920ad JW |
9759 | break; |
9760 | insn = NEXT_INSN (insn); | |
9761 | } | |
9762 | } | |
3b572406 RH |
9763 | } |
9764 | ||
c65ebc55 JW |
9765 | /* Perform machine dependent operations on the rtl chain INSNS. */ |
9766 | ||
18dbd950 | 9767 | static void |
9c808aad | 9768 | ia64_reorg (void) |
c65ebc55 | 9769 | { |
1e3881c2 JH |
9770 | /* We are freeing block_for_insn in the toplev to keep compatibility |
9771 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
852c6ec7 | 9772 | compute_bb_for_insn (); |
a00fe19f RH |
9773 | |
9774 | /* If optimizing, we'll have split before scheduling. */ | |
9775 | if (optimize == 0) | |
6fb5fa3c | 9776 | split_all_insns (); |
2130b7fb | 9777 | |
2ba42841 | 9778 | if (optimize && flag_schedule_insns_after_reload |
388092d5 | 9779 | && dbg_cnt (ia64_sched2)) |
f4d578da | 9780 | { |
547fdef8 | 9781 | basic_block bb; |
eced69b5 | 9782 | timevar_push (TV_SCHED2); |
f4d578da | 9783 | ia64_final_schedule = 1; |
30028c85 | 9784 | |
547fdef8 BS |
9785 | /* We can't let modulo-sched prevent us from scheduling any bbs, |
9786 | since we need the final schedule to produce bundle information. */ | |
11cd3bed | 9787 | FOR_EACH_BB_FN (bb, cfun) |
547fdef8 BS |
9788 | bb->flags &= ~BB_DISABLE_SCHEDULE; |
9789 | ||
30028c85 VM |
9790 | initiate_bundle_states (); |
9791 | ia64_nop = make_insn_raw (gen_nop ()); | |
0f82e5c9 | 9792 | SET_PREV_INSN (ia64_nop) = SET_NEXT_INSN (ia64_nop) = NULL_RTX; |
30028c85 VM |
9793 | recog_memoized (ia64_nop); |
9794 | clocks_length = get_max_uid () + 1; | |
5ead67f6 | 9795 | stops_p = XCNEWVEC (char, clocks_length); |
7400e46b | 9796 | |
30028c85 VM |
9797 | if (ia64_tune == PROCESSOR_ITANIUM2) |
9798 | { | |
9799 | pos_1 = get_cpu_unit_code ("2_1"); | |
9800 | pos_2 = get_cpu_unit_code ("2_2"); | |
9801 | pos_3 = get_cpu_unit_code ("2_3"); | |
9802 | pos_4 = get_cpu_unit_code ("2_4"); | |
9803 | pos_5 = get_cpu_unit_code ("2_5"); | |
9804 | pos_6 = get_cpu_unit_code ("2_6"); | |
9805 | _0mii_ = get_cpu_unit_code ("2b_0mii."); | |
9806 | _0mmi_ = get_cpu_unit_code ("2b_0mmi."); | |
9807 | _0mfi_ = get_cpu_unit_code ("2b_0mfi."); | |
9808 | _0mmf_ = get_cpu_unit_code ("2b_0mmf."); | |
9809 | _0bbb_ = get_cpu_unit_code ("2b_0bbb."); | |
9810 | _0mbb_ = get_cpu_unit_code ("2b_0mbb."); | |
9811 | _0mib_ = get_cpu_unit_code ("2b_0mib."); | |
9812 | _0mmb_ = get_cpu_unit_code ("2b_0mmb."); | |
9813 | _0mfb_ = get_cpu_unit_code ("2b_0mfb."); | |
9814 | _0mlx_ = get_cpu_unit_code ("2b_0mlx."); | |
9815 | _1mii_ = get_cpu_unit_code ("2b_1mii."); | |
9816 | _1mmi_ = get_cpu_unit_code ("2b_1mmi."); | |
9817 | _1mfi_ = get_cpu_unit_code ("2b_1mfi."); | |
9818 | _1mmf_ = get_cpu_unit_code ("2b_1mmf."); | |
9819 | _1bbb_ = get_cpu_unit_code ("2b_1bbb."); | |
9820 | _1mbb_ = get_cpu_unit_code ("2b_1mbb."); | |
9821 | _1mib_ = get_cpu_unit_code ("2b_1mib."); | |
9822 | _1mmb_ = get_cpu_unit_code ("2b_1mmb."); | |
9823 | _1mfb_ = get_cpu_unit_code ("2b_1mfb."); | |
9824 | _1mlx_ = get_cpu_unit_code ("2b_1mlx."); | |
9825 | } | |
9826 | else | |
9827 | { | |
9828 | pos_1 = get_cpu_unit_code ("1_1"); | |
9829 | pos_2 = get_cpu_unit_code ("1_2"); | |
9830 | pos_3 = get_cpu_unit_code ("1_3"); | |
9831 | pos_4 = get_cpu_unit_code ("1_4"); | |
9832 | pos_5 = get_cpu_unit_code ("1_5"); | |
9833 | pos_6 = get_cpu_unit_code ("1_6"); | |
9834 | _0mii_ = get_cpu_unit_code ("1b_0mii."); | |
9835 | _0mmi_ = get_cpu_unit_code ("1b_0mmi."); | |
9836 | _0mfi_ = get_cpu_unit_code ("1b_0mfi."); | |
9837 | _0mmf_ = get_cpu_unit_code ("1b_0mmf."); | |
9838 | _0bbb_ = get_cpu_unit_code ("1b_0bbb."); | |
9839 | _0mbb_ = get_cpu_unit_code ("1b_0mbb."); | |
9840 | _0mib_ = get_cpu_unit_code ("1b_0mib."); | |
9841 | _0mmb_ = get_cpu_unit_code ("1b_0mmb."); | |
9842 | _0mfb_ = get_cpu_unit_code ("1b_0mfb."); | |
9843 | _0mlx_ = get_cpu_unit_code ("1b_0mlx."); | |
9844 | _1mii_ = get_cpu_unit_code ("1b_1mii."); | |
9845 | _1mmi_ = get_cpu_unit_code ("1b_1mmi."); | |
9846 | _1mfi_ = get_cpu_unit_code ("1b_1mfi."); | |
9847 | _1mmf_ = get_cpu_unit_code ("1b_1mmf."); | |
9848 | _1bbb_ = get_cpu_unit_code ("1b_1bbb."); | |
9849 | _1mbb_ = get_cpu_unit_code ("1b_1mbb."); | |
9850 | _1mib_ = get_cpu_unit_code ("1b_1mib."); | |
9851 | _1mmb_ = get_cpu_unit_code ("1b_1mmb."); | |
9852 | _1mfb_ = get_cpu_unit_code ("1b_1mfb."); | |
9853 | _1mlx_ = get_cpu_unit_code ("1b_1mlx."); | |
9854 | } | |
388092d5 AB |
9855 | |
9856 | if (flag_selective_scheduling2 | |
9857 | && !maybe_skip_selective_scheduling ()) | |
9858 | run_selective_scheduling (); | |
9859 | else | |
9860 | schedule_ebbs (); | |
9861 | ||
9862 | /* Redo alignment computation, as it might gone wrong. */ | |
9863 | compute_alignments (); | |
9864 | ||
6fb5fa3c DB |
9865 | /* We cannot reuse this one because it has been corrupted by the |
9866 | evil glat. */ | |
30028c85 | 9867 | finish_bundle_states (); |
30028c85 | 9868 | free (stops_p); |
048d0d36 | 9869 | stops_p = NULL; |
c263766c | 9870 | emit_insn_group_barriers (dump_file); |
30028c85 | 9871 | |
f4d578da | 9872 | ia64_final_schedule = 0; |
eced69b5 | 9873 | timevar_pop (TV_SCHED2); |
f4d578da BS |
9874 | } |
9875 | else | |
c263766c | 9876 | emit_all_insn_group_barriers (dump_file); |
f2f90c63 | 9877 | |
6fb5fa3c DB |
9878 | df_analyze (); |
9879 | ||
f12f25a7 RH |
9880 | /* A call must not be the last instruction in a function, so that the |
9881 | return address is still within the function, so that unwinding works | |
9882 | properly. Note that IA-64 differs from dwarf2 on this point. */ | |
d5fabb58 | 9883 | if (ia64_except_unwind_info (&global_options) == UI_TARGET) |
f12f25a7 | 9884 | { |
dd3d2b35 | 9885 | rtx_insn *insn; |
f12f25a7 RH |
9886 | int saw_stop = 0; |
9887 | ||
9888 | insn = get_last_insn (); | |
9889 | if (! INSN_P (insn)) | |
9890 | insn = prev_active_insn (insn); | |
2ca57608 | 9891 | if (insn) |
f12f25a7 | 9892 | { |
2ca57608 | 9893 | /* Skip over insns that expand to nothing. */ |
b64925dc | 9894 | while (NONJUMP_INSN_P (insn) |
2ca57608 L |
9895 | && get_attr_empty (insn) == EMPTY_YES) |
9896 | { | |
9897 | if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
9898 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) | |
9899 | saw_stop = 1; | |
9900 | insn = prev_active_insn (insn); | |
9901 | } | |
b64925dc | 9902 | if (CALL_P (insn)) |
2ca57608 L |
9903 | { |
9904 | if (! saw_stop) | |
9905 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9906 | emit_insn (gen_break_f ()); | |
9907 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9908 | } | |
f12f25a7 RH |
9909 | } |
9910 | } | |
9911 | ||
f2f90c63 | 9912 | emit_predicate_relation_info (); |
014a1138 | 9913 | |
2ba42841 | 9914 | if (flag_var_tracking) |
014a1138 JZ |
9915 | { |
9916 | timevar_push (TV_VAR_TRACKING); | |
9917 | variable_tracking_main (); | |
9918 | timevar_pop (TV_VAR_TRACKING); | |
9919 | } | |
0d475361 | 9920 | df_finish_pass (false); |
c65ebc55 JW |
9921 | } |
9922 | \f | |
9923 | /* Return true if REGNO is used by the epilogue. */ | |
9924 | ||
9925 | int | |
9c808aad | 9926 | ia64_epilogue_uses (int regno) |
c65ebc55 | 9927 | { |
6ca3c22f RH |
9928 | switch (regno) |
9929 | { | |
9930 | case R_GR (1): | |
b23ba0b8 RH |
9931 | /* With a call to a function in another module, we will write a new |
9932 | value to "gp". After returning from such a call, we need to make | |
9933 | sure the function restores the original gp-value, even if the | |
9934 | function itself does not use the gp anymore. */ | |
9935 | return !(TARGET_AUTO_PIC || TARGET_NO_PIC); | |
6ca3c22f RH |
9936 | |
9937 | case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3): | |
9938 | case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7): | |
9939 | /* For functions defined with the syscall_linkage attribute, all | |
9940 | input registers are marked as live at all function exits. This | |
9941 | prevents the register allocator from using the input registers, | |
9942 | which in turn makes it possible to restart a system call after | |
9943 | an interrupt without having to save/restore the input registers. | |
9944 | This also prevents kernel data from leaking to application code. */ | |
9945 | return lookup_attribute ("syscall_linkage", | |
9946 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL; | |
9947 | ||
9948 | case R_BR (0): | |
9949 | /* Conditional return patterns can't represent the use of `b0' as | |
9950 | the return address, so we force the value live this way. */ | |
9951 | return 1; | |
6b6c1201 | 9952 | |
6ca3c22f RH |
9953 | case AR_PFS_REGNUM: |
9954 | /* Likewise for ar.pfs, which is used by br.ret. */ | |
9955 | return 1; | |
5527bf14 | 9956 | |
6ca3c22f RH |
9957 | default: |
9958 | return 0; | |
9959 | } | |
c65ebc55 | 9960 | } |
15b5aef3 RH |
9961 | |
9962 | /* Return true if REGNO is used by the frame unwinder. */ | |
9963 | ||
9964 | int | |
9c808aad | 9965 | ia64_eh_uses (int regno) |
15b5aef3 | 9966 | { |
09639a83 | 9967 | unsigned int r; |
6fb5fa3c | 9968 | |
15b5aef3 RH |
9969 | if (! reload_completed) |
9970 | return 0; | |
9971 | ||
6fb5fa3c DB |
9972 | if (regno == 0) |
9973 | return 0; | |
9974 | ||
9975 | for (r = reg_save_b0; r <= reg_save_ar_lc; r++) | |
9976 | if (regno == current_frame_info.r[r] | |
9977 | || regno == emitted_frame_related_regs[r]) | |
9978 | return 1; | |
15b5aef3 RH |
9979 | |
9980 | return 0; | |
9981 | } | |
c65ebc55 | 9982 | \f |
1cdbd630 | 9983 | /* Return true if this goes in small data/bss. */ |
c65ebc55 JW |
9984 | |
9985 | /* ??? We could also support own long data here. Generating movl/add/ld8 | |
9986 | instead of addl,ld8/ld8. This makes the code bigger, but should make the | |
9987 | code faster because there is one less load. This also includes incomplete | |
9988 | types which can't go in sdata/sbss. */ | |
9989 | ||
ae46c4e0 | 9990 | static bool |
3101faab | 9991 | ia64_in_small_data_p (const_tree exp) |
ae46c4e0 RH |
9992 | { |
9993 | if (TARGET_NO_SDATA) | |
9994 | return false; | |
9995 | ||
3907500b RH |
9996 | /* We want to merge strings, so we never consider them small data. */ |
9997 | if (TREE_CODE (exp) == STRING_CST) | |
9998 | return false; | |
9999 | ||
4c494a15 ZW |
10000 | /* Functions are never small data. */ |
10001 | if (TREE_CODE (exp) == FUNCTION_DECL) | |
10002 | return false; | |
10003 | ||
ae46c4e0 RH |
10004 | if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) |
10005 | { | |
f961457f | 10006 | const char *section = DECL_SECTION_NAME (exp); |
826eb7ed | 10007 | |
ae46c4e0 | 10008 | if (strcmp (section, ".sdata") == 0 |
826eb7ed JB |
10009 | || strncmp (section, ".sdata.", 7) == 0 |
10010 | || strncmp (section, ".gnu.linkonce.s.", 16) == 0 | |
10011 | || strcmp (section, ".sbss") == 0 | |
10012 | || strncmp (section, ".sbss.", 6) == 0 | |
10013 | || strncmp (section, ".gnu.linkonce.sb.", 17) == 0) | |
ae46c4e0 RH |
10014 | return true; |
10015 | } | |
10016 | else | |
10017 | { | |
10018 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); | |
10019 | ||
10020 | /* If this is an incomplete type with size 0, then we can't put it | |
10021 | in sdata because it might be too big when completed. */ | |
10022 | if (size > 0 && size <= ia64_section_threshold) | |
10023 | return true; | |
10024 | } | |
10025 | ||
10026 | return false; | |
10027 | } | |
0c96007e | 10028 | \f |
ad0fc698 JW |
10029 | /* Output assembly directives for prologue regions. */ |
10030 | ||
10031 | /* The current basic block number. */ | |
10032 | ||
e0082a72 | 10033 | static bool last_block; |
ad0fc698 JW |
10034 | |
10035 | /* True if we need a copy_state command at the start of the next block. */ | |
10036 | ||
e0082a72 | 10037 | static bool need_copy_state; |
ad0fc698 | 10038 | |
658f32fd AO |
10039 | #ifndef MAX_ARTIFICIAL_LABEL_BYTES |
10040 | # define MAX_ARTIFICIAL_LABEL_BYTES 30 | |
10041 | #endif | |
10042 | ||
ad0fc698 JW |
10043 | /* The function emits unwind directives for the start of an epilogue. */ |
10044 | ||
10045 | static void | |
7d3c6cd8 RH |
10046 | process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED, |
10047 | bool unwind, bool frame ATTRIBUTE_UNUSED) | |
ad0fc698 JW |
10048 | { |
10049 | /* If this isn't the last block of the function, then we need to label the | |
10050 | current state, and copy it back in at the start of the next block. */ | |
10051 | ||
e0082a72 | 10052 | if (!last_block) |
ad0fc698 | 10053 | { |
658f32fd AO |
10054 | if (unwind) |
10055 | fprintf (asm_out_file, "\t.label_state %d\n", | |
10056 | ++cfun->machine->state_num); | |
e0082a72 | 10057 | need_copy_state = true; |
ad0fc698 JW |
10058 | } |
10059 | ||
658f32fd AO |
10060 | if (unwind) |
10061 | fprintf (asm_out_file, "\t.restore sp\n"); | |
ad0fc698 | 10062 | } |
0c96007e | 10063 | |
5c255b57 | 10064 | /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */ |
97e242b0 | 10065 | |
5c255b57 RH |
10066 | static void |
10067 | process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn, | |
10068 | bool unwind, bool frame) | |
0c96007e | 10069 | { |
0c96007e | 10070 | rtx dest = SET_DEST (pat); |
5c255b57 | 10071 | rtx src = SET_SRC (pat); |
0c96007e | 10072 | |
5c255b57 | 10073 | if (dest == stack_pointer_rtx) |
0c96007e AM |
10074 | { |
10075 | if (GET_CODE (src) == PLUS) | |
5c255b57 | 10076 | { |
0c96007e AM |
10077 | rtx op0 = XEXP (src, 0); |
10078 | rtx op1 = XEXP (src, 1); | |
e820471b NS |
10079 | |
10080 | gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT); | |
10081 | ||
10082 | if (INTVAL (op1) < 0) | |
658f32fd AO |
10083 | { |
10084 | gcc_assert (!frame_pointer_needed); | |
10085 | if (unwind) | |
5c255b57 | 10086 | fprintf (asm_out_file, |
16998094 | 10087 | "\t.fframe " HOST_WIDE_INT_PRINT_DEC"\n", |
658f32fd | 10088 | -INTVAL (op1)); |
658f32fd | 10089 | } |
0186257f | 10090 | else |
658f32fd | 10091 | process_epilogue (asm_out_file, insn, unwind, frame); |
0c96007e | 10092 | } |
0186257f | 10093 | else |
e820471b | 10094 | { |
5c255b57 | 10095 | gcc_assert (src == hard_frame_pointer_rtx); |
658f32fd | 10096 | process_epilogue (asm_out_file, insn, unwind, frame); |
e820471b | 10097 | } |
5c255b57 RH |
10098 | } |
10099 | else if (dest == hard_frame_pointer_rtx) | |
10100 | { | |
10101 | gcc_assert (src == stack_pointer_rtx); | |
10102 | gcc_assert (frame_pointer_needed); | |
0186257f | 10103 | |
5c255b57 RH |
10104 | if (unwind) |
10105 | fprintf (asm_out_file, "\t.vframe r%d\n", | |
10106 | ia64_dbx_register_number (REGNO (dest))); | |
0c96007e | 10107 | } |
5c255b57 RH |
10108 | else |
10109 | gcc_unreachable (); | |
10110 | } | |
0c96007e | 10111 | |
5c255b57 | 10112 | /* This function processes a SET pattern for REG_CFA_REGISTER. */ |
97e242b0 | 10113 | |
5c255b57 RH |
10114 | static void |
10115 | process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind) | |
10116 | { | |
10117 | rtx dest = SET_DEST (pat); | |
10118 | rtx src = SET_SRC (pat); | |
5c255b57 | 10119 | int dest_regno = REGNO (dest); |
5f740973 | 10120 | int src_regno; |
97e242b0 | 10121 | |
5f740973 | 10122 | if (src == pc_rtx) |
5c255b57 | 10123 | { |
5c255b57 | 10124 | /* Saving return address pointer. */ |
5c255b57 RH |
10125 | if (unwind) |
10126 | fprintf (asm_out_file, "\t.save rp, r%d\n", | |
10127 | ia64_dbx_register_number (dest_regno)); | |
5f740973 RH |
10128 | return; |
10129 | } | |
10130 | ||
10131 | src_regno = REGNO (src); | |
97e242b0 | 10132 | |
5f740973 RH |
10133 | switch (src_regno) |
10134 | { | |
5c255b57 RH |
10135 | case PR_REG (0): |
10136 | gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]); | |
10137 | if (unwind) | |
10138 | fprintf (asm_out_file, "\t.save pr, r%d\n", | |
10139 | ia64_dbx_register_number (dest_regno)); | |
10140 | break; | |
97e242b0 | 10141 | |
5c255b57 RH |
10142 | case AR_UNAT_REGNUM: |
10143 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]); | |
10144 | if (unwind) | |
10145 | fprintf (asm_out_file, "\t.save ar.unat, r%d\n", | |
10146 | ia64_dbx_register_number (dest_regno)); | |
10147 | break; | |
97e242b0 | 10148 | |
5c255b57 RH |
10149 | case AR_LC_REGNUM: |
10150 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]); | |
10151 | if (unwind) | |
10152 | fprintf (asm_out_file, "\t.save ar.lc, r%d\n", | |
10153 | ia64_dbx_register_number (dest_regno)); | |
10154 | break; | |
10155 | ||
10156 | default: | |
10157 | /* Everything else should indicate being stored to memory. */ | |
10158 | gcc_unreachable (); | |
0c96007e | 10159 | } |
5c255b57 | 10160 | } |
97e242b0 | 10161 | |
5c255b57 | 10162 | /* This function processes a SET pattern for REG_CFA_OFFSET. */ |
97e242b0 | 10163 | |
5c255b57 RH |
10164 | static void |
10165 | process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind) | |
10166 | { | |
10167 | rtx dest = SET_DEST (pat); | |
10168 | rtx src = SET_SRC (pat); | |
10169 | int src_regno = REGNO (src); | |
10170 | const char *saveop; | |
10171 | HOST_WIDE_INT off; | |
10172 | rtx base; | |
0c96007e | 10173 | |
5c255b57 RH |
10174 | gcc_assert (MEM_P (dest)); |
10175 | if (GET_CODE (XEXP (dest, 0)) == REG) | |
10176 | { | |
10177 | base = XEXP (dest, 0); | |
10178 | off = 0; | |
10179 | } | |
10180 | else | |
10181 | { | |
10182 | gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS | |
10183 | && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT); | |
10184 | base = XEXP (XEXP (dest, 0), 0); | |
10185 | off = INTVAL (XEXP (XEXP (dest, 0), 1)); | |
10186 | } | |
97e242b0 | 10187 | |
5c255b57 RH |
10188 | if (base == hard_frame_pointer_rtx) |
10189 | { | |
10190 | saveop = ".savepsp"; | |
10191 | off = - off; | |
10192 | } | |
10193 | else | |
10194 | { | |
10195 | gcc_assert (base == stack_pointer_rtx); | |
10196 | saveop = ".savesp"; | |
10197 | } | |
97e242b0 | 10198 | |
5c255b57 RH |
10199 | src_regno = REGNO (src); |
10200 | switch (src_regno) | |
10201 | { | |
10202 | case BR_REG (0): | |
10203 | gcc_assert (!current_frame_info.r[reg_save_b0]); | |
10204 | if (unwind) | |
10205 | fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10206 | saveop, off); | |
10207 | break; | |
97e242b0 | 10208 | |
5c255b57 RH |
10209 | case PR_REG (0): |
10210 | gcc_assert (!current_frame_info.r[reg_save_pr]); | |
10211 | if (unwind) | |
10212 | fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10213 | saveop, off); | |
10214 | break; | |
97e242b0 | 10215 | |
5c255b57 RH |
10216 | case AR_LC_REGNUM: |
10217 | gcc_assert (!current_frame_info.r[reg_save_ar_lc]); | |
10218 | if (unwind) | |
10219 | fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10220 | saveop, off); | |
10221 | break; | |
97e242b0 | 10222 | |
5c255b57 RH |
10223 | case AR_PFS_REGNUM: |
10224 | gcc_assert (!current_frame_info.r[reg_save_ar_pfs]); | |
10225 | if (unwind) | |
10226 | fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10227 | saveop, off); | |
10228 | break; | |
97e242b0 | 10229 | |
5c255b57 RH |
10230 | case AR_UNAT_REGNUM: |
10231 | gcc_assert (!current_frame_info.r[reg_save_ar_unat]); | |
10232 | if (unwind) | |
10233 | fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10234 | saveop, off); | |
10235 | break; | |
97e242b0 | 10236 | |
5c255b57 RH |
10237 | case GR_REG (4): |
10238 | case GR_REG (5): | |
10239 | case GR_REG (6): | |
10240 | case GR_REG (7): | |
10241 | if (unwind) | |
10242 | fprintf (asm_out_file, "\t.save.g 0x%x\n", | |
10243 | 1 << (src_regno - GR_REG (4))); | |
10244 | break; | |
97e242b0 | 10245 | |
5c255b57 RH |
10246 | case BR_REG (1): |
10247 | case BR_REG (2): | |
10248 | case BR_REG (3): | |
10249 | case BR_REG (4): | |
10250 | case BR_REG (5): | |
10251 | if (unwind) | |
10252 | fprintf (asm_out_file, "\t.save.b 0x%x\n", | |
10253 | 1 << (src_regno - BR_REG (1))); | |
10254 | break; | |
97e242b0 | 10255 | |
5c255b57 RH |
10256 | case FR_REG (2): |
10257 | case FR_REG (3): | |
10258 | case FR_REG (4): | |
10259 | case FR_REG (5): | |
10260 | if (unwind) | |
10261 | fprintf (asm_out_file, "\t.save.f 0x%x\n", | |
10262 | 1 << (src_regno - FR_REG (2))); | |
10263 | break; | |
97e242b0 | 10264 | |
5c255b57 RH |
10265 | case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19): |
10266 | case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23): | |
10267 | case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27): | |
10268 | case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31): | |
10269 | if (unwind) | |
10270 | fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n", | |
10271 | 1 << (src_regno - FR_REG (12))); | |
10272 | break; | |
97e242b0 | 10273 | |
5c255b57 RH |
10274 | default: |
10275 | /* ??? For some reason we mark other general registers, even those | |
10276 | we can't represent in the unwind info. Ignore them. */ | |
10277 | break; | |
10278 | } | |
0c96007e AM |
10279 | } |
10280 | ||
0c96007e AM |
10281 | /* This function looks at a single insn and emits any directives |
10282 | required to unwind this insn. */ | |
5c255b57 | 10283 | |
a68b5e52 | 10284 | static void |
ac44248e | 10285 | ia64_asm_unwind_emit (FILE *asm_out_file, rtx_insn *insn) |
0c96007e | 10286 | { |
d5fabb58 | 10287 | bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET; |
658f32fd | 10288 | bool frame = dwarf2out_do_frame (); |
5c255b57 RH |
10289 | rtx note, pat; |
10290 | bool handled_one; | |
10291 | ||
10292 | if (!unwind && !frame) | |
10293 | return; | |
658f32fd | 10294 | |
5c255b57 | 10295 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
0c96007e | 10296 | { |
fefa31b5 DM |
10297 | last_block = NOTE_BASIC_BLOCK (insn)->next_bb |
10298 | == EXIT_BLOCK_PTR_FOR_FN (cfun); | |
97e242b0 | 10299 | |
5c255b57 RH |
10300 | /* Restore unwind state from immediately before the epilogue. */ |
10301 | if (need_copy_state) | |
ad0fc698 | 10302 | { |
5c255b57 | 10303 | if (unwind) |
ad0fc698 | 10304 | { |
5c255b57 RH |
10305 | fprintf (asm_out_file, "\t.body\n"); |
10306 | fprintf (asm_out_file, "\t.copy_state %d\n", | |
10307 | cfun->machine->state_num); | |
ad0fc698 | 10308 | } |
5c255b57 | 10309 | need_copy_state = false; |
ad0fc698 | 10310 | } |
5c255b57 | 10311 | } |
ad0fc698 | 10312 | |
b64925dc | 10313 | if (NOTE_P (insn) || ! RTX_FRAME_RELATED_P (insn)) |
5c255b57 RH |
10314 | return; |
10315 | ||
10316 | /* Look for the ALLOC insn. */ | |
10317 | if (INSN_CODE (insn) == CODE_FOR_alloc) | |
10318 | { | |
10319 | rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
10320 | int dest_regno = REGNO (dest); | |
ad0fc698 | 10321 | |
5c255b57 RH |
10322 | /* If this is the final destination for ar.pfs, then this must |
10323 | be the alloc in the prologue. */ | |
10324 | if (dest_regno == current_frame_info.r[reg_save_ar_pfs]) | |
10325 | { | |
10326 | if (unwind) | |
10327 | fprintf (asm_out_file, "\t.save ar.pfs, r%d\n", | |
10328 | ia64_dbx_register_number (dest_regno)); | |
10329 | } | |
97e242b0 | 10330 | else |
5c255b57 RH |
10331 | { |
10332 | /* This must be an alloc before a sibcall. We must drop the | |
10333 | old frame info. The easiest way to drop the old frame | |
10334 | info is to ensure we had a ".restore sp" directive | |
10335 | followed by a new prologue. If the procedure doesn't | |
10336 | have a memory-stack frame, we'll issue a dummy ".restore | |
10337 | sp" now. */ | |
10338 | if (current_frame_info.total_size == 0 && !frame_pointer_needed) | |
10339 | /* if haven't done process_epilogue() yet, do it now */ | |
10340 | process_epilogue (asm_out_file, insn, unwind, frame); | |
10341 | if (unwind) | |
10342 | fprintf (asm_out_file, "\t.prologue\n"); | |
10343 | } | |
10344 | return; | |
10345 | } | |
0c96007e | 10346 | |
5c255b57 RH |
10347 | handled_one = false; |
10348 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
10349 | switch (REG_NOTE_KIND (note)) | |
10350 | { | |
10351 | case REG_CFA_ADJUST_CFA: | |
10352 | pat = XEXP (note, 0); | |
10353 | if (pat == NULL) | |
10354 | pat = PATTERN (insn); | |
10355 | process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame); | |
10356 | handled_one = true; | |
10357 | break; | |
809d4ef1 | 10358 | |
5c255b57 RH |
10359 | case REG_CFA_OFFSET: |
10360 | pat = XEXP (note, 0); | |
10361 | if (pat == NULL) | |
10362 | pat = PATTERN (insn); | |
10363 | process_cfa_offset (asm_out_file, pat, unwind); | |
10364 | handled_one = true; | |
10365 | break; | |
809d4ef1 | 10366 | |
5c255b57 RH |
10367 | case REG_CFA_REGISTER: |
10368 | pat = XEXP (note, 0); | |
10369 | if (pat == NULL) | |
10370 | pat = PATTERN (insn); | |
10371 | process_cfa_register (asm_out_file, pat, unwind); | |
10372 | handled_one = true; | |
10373 | break; | |
10374 | ||
10375 | case REG_FRAME_RELATED_EXPR: | |
10376 | case REG_CFA_DEF_CFA: | |
10377 | case REG_CFA_EXPRESSION: | |
10378 | case REG_CFA_RESTORE: | |
10379 | case REG_CFA_SET_VDRAP: | |
10380 | /* Not used in the ia64 port. */ | |
10381 | gcc_unreachable (); | |
10382 | ||
10383 | default: | |
10384 | /* Not a frame-related note. */ | |
10385 | break; | |
10386 | } | |
10387 | ||
10388 | /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the | |
10389 | explicit action to take. No guessing required. */ | |
10390 | gcc_assert (handled_one); | |
0c96007e | 10391 | } |
c65ebc55 | 10392 | |
a68b5e52 RH |
10393 | /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */ |
10394 | ||
10395 | static void | |
10396 | ia64_asm_emit_except_personality (rtx personality) | |
10397 | { | |
10398 | fputs ("\t.personality\t", asm_out_file); | |
10399 | output_addr_const (asm_out_file, personality); | |
10400 | fputc ('\n', asm_out_file); | |
10401 | } | |
10402 | ||
10403 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */ | |
10404 | ||
10405 | static void | |
10406 | ia64_asm_init_sections (void) | |
10407 | { | |
10408 | exception_section = get_unnamed_section (0, output_section_asm_op, | |
10409 | "\t.handlerdata"); | |
10410 | } | |
f0a0390e RH |
10411 | |
10412 | /* Implement TARGET_DEBUG_UNWIND_INFO. */ | |
10413 | ||
10414 | static enum unwind_info_type | |
10415 | ia64_debug_unwind_info (void) | |
10416 | { | |
10417 | return UI_TARGET; | |
10418 | } | |
0551c32d | 10419 | \f |
af795c3c RH |
10420 | enum ia64_builtins |
10421 | { | |
10422 | IA64_BUILTIN_BSP, | |
c252db20 L |
10423 | IA64_BUILTIN_COPYSIGNQ, |
10424 | IA64_BUILTIN_FABSQ, | |
10425 | IA64_BUILTIN_FLUSHRS, | |
fcb82ab0 | 10426 | IA64_BUILTIN_INFQ, |
b14446e2 | 10427 | IA64_BUILTIN_HUGE_VALQ, |
b6ca982f UB |
10428 | IA64_BUILTIN_NANQ, |
10429 | IA64_BUILTIN_NANSQ, | |
b14446e2 | 10430 | IA64_BUILTIN_max |
af795c3c RH |
10431 | }; |
10432 | ||
b14446e2 SE |
10433 | static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max]; |
10434 | ||
c65ebc55 | 10435 | void |
9c808aad | 10436 | ia64_init_builtins (void) |
c65ebc55 | 10437 | { |
9649812a | 10438 | tree fpreg_type; |
bf9ab6b6 | 10439 | tree float80_type; |
b14446e2 | 10440 | tree decl; |
9649812a MM |
10441 | |
10442 | /* The __fpreg type. */ | |
10443 | fpreg_type = make_node (REAL_TYPE); | |
4de67c26 | 10444 | TYPE_PRECISION (fpreg_type) = 82; |
9649812a MM |
10445 | layout_type (fpreg_type); |
10446 | (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg"); | |
10447 | ||
10448 | /* The __float80 type. */ | |
c65699ef JM |
10449 | if (float64x_type_node != NULL_TREE |
10450 | && TYPE_MODE (float64x_type_node) == XFmode) | |
10451 | float80_type = float64x_type_node; | |
10452 | else | |
10453 | { | |
10454 | float80_type = make_node (REAL_TYPE); | |
10455 | TYPE_PRECISION (float80_type) = 80; | |
10456 | layout_type (float80_type); | |
10457 | } | |
bf9ab6b6 | 10458 | (*lang_hooks.types.register_builtin_type) (float80_type, "__float80"); |
9649812a MM |
10459 | |
10460 | /* The __float128 type. */ | |
02befdf4 | 10461 | if (!TARGET_HPUX) |
9649812a | 10462 | { |
b14446e2 | 10463 | tree ftype; |
b6ca982f UB |
10464 | tree const_string_type |
10465 | = build_pointer_type (build_qualified_type | |
10466 | (char_type_node, TYPE_QUAL_CONST)); | |
c252db20 | 10467 | |
c65699ef JM |
10468 | (*lang_hooks.types.register_builtin_type) (float128_type_node, |
10469 | "__float128"); | |
c252db20 L |
10470 | |
10471 | /* TFmode support builtins. */ | |
c65699ef | 10472 | ftype = build_function_type_list (float128_type_node, NULL_TREE); |
b14446e2 SE |
10473 | decl = add_builtin_function ("__builtin_infq", ftype, |
10474 | IA64_BUILTIN_INFQ, BUILT_IN_MD, | |
10475 | NULL, NULL_TREE); | |
10476 | ia64_builtins[IA64_BUILTIN_INFQ] = decl; | |
c252db20 | 10477 | |
b14446e2 SE |
10478 | decl = add_builtin_function ("__builtin_huge_valq", ftype, |
10479 | IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD, | |
10480 | NULL, NULL_TREE); | |
10481 | ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl; | |
fcb82ab0 | 10482 | |
c65699ef | 10483 | ftype = build_function_type_list (float128_type_node, |
b6ca982f UB |
10484 | const_string_type, |
10485 | NULL_TREE); | |
10486 | decl = add_builtin_function ("__builtin_nanq", ftype, | |
10487 | IA64_BUILTIN_NANQ, BUILT_IN_MD, | |
10488 | "nanq", NULL_TREE); | |
10489 | TREE_READONLY (decl) = 1; | |
10490 | ia64_builtins[IA64_BUILTIN_NANQ] = decl; | |
10491 | ||
10492 | decl = add_builtin_function ("__builtin_nansq", ftype, | |
10493 | IA64_BUILTIN_NANSQ, BUILT_IN_MD, | |
10494 | "nansq", NULL_TREE); | |
10495 | TREE_READONLY (decl) = 1; | |
10496 | ia64_builtins[IA64_BUILTIN_NANSQ] = decl; | |
10497 | ||
c65699ef JM |
10498 | ftype = build_function_type_list (float128_type_node, |
10499 | float128_type_node, | |
c252db20 L |
10500 | NULL_TREE); |
10501 | decl = add_builtin_function ("__builtin_fabsq", ftype, | |
10502 | IA64_BUILTIN_FABSQ, BUILT_IN_MD, | |
10503 | "__fabstf2", NULL_TREE); | |
10504 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10505 | ia64_builtins[IA64_BUILTIN_FABSQ] = decl; |
c252db20 | 10506 | |
c65699ef JM |
10507 | ftype = build_function_type_list (float128_type_node, |
10508 | float128_type_node, | |
10509 | float128_type_node, | |
c252db20 L |
10510 | NULL_TREE); |
10511 | decl = add_builtin_function ("__builtin_copysignq", ftype, | |
10512 | IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD, | |
10513 | "__copysigntf3", NULL_TREE); | |
10514 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10515 | ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl; |
9649812a MM |
10516 | } |
10517 | else | |
02befdf4 | 10518 | /* Under HPUX, this is a synonym for "long double". */ |
9649812a MM |
10519 | (*lang_hooks.types.register_builtin_type) (long_double_type_node, |
10520 | "__float128"); | |
10521 | ||
f2972bf8 | 10522 | /* Fwrite on VMS is non-standard. */ |
171da07a RH |
10523 | #if TARGET_ABI_OPEN_VMS |
10524 | vms_patch_builtins (); | |
10525 | #endif | |
f2972bf8 | 10526 | |
6e34d3a3 | 10527 | #define def_builtin(name, type, code) \ |
c79efc4d RÁE |
10528 | add_builtin_function ((name), (type), (code), BUILT_IN_MD, \ |
10529 | NULL, NULL_TREE) | |
0551c32d | 10530 | |
b14446e2 | 10531 | decl = def_builtin ("__builtin_ia64_bsp", |
c0676219 NF |
10532 | build_function_type_list (ptr_type_node, NULL_TREE), |
10533 | IA64_BUILTIN_BSP); | |
b14446e2 | 10534 | ia64_builtins[IA64_BUILTIN_BSP] = decl; |
ce152ef8 | 10535 | |
b14446e2 | 10536 | decl = def_builtin ("__builtin_ia64_flushrs", |
c0676219 NF |
10537 | build_function_type_list (void_type_node, NULL_TREE), |
10538 | IA64_BUILTIN_FLUSHRS); | |
b14446e2 | 10539 | ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl; |
ce152ef8 | 10540 | |
0551c32d | 10541 | #undef def_builtin |
7d522000 SE |
10542 | |
10543 | if (TARGET_HPUX) | |
10544 | { | |
ccea4a27 | 10545 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE) |
e79983f4 | 10546 | set_user_assembler_name (decl, "_Isfinite"); |
ccea4a27 | 10547 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE) |
e79983f4 | 10548 | set_user_assembler_name (decl, "_Isfinitef"); |
ccea4a27 | 10549 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE) |
e79983f4 | 10550 | set_user_assembler_name (decl, "_Isfinitef128"); |
7d522000 | 10551 | } |
c65ebc55 JW |
10552 | } |
10553 | ||
b6ca982f UB |
10554 | static tree |
10555 | ia64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, | |
10556 | tree *args, bool ignore ATTRIBUTE_UNUSED) | |
10557 | { | |
10558 | if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD) | |
10559 | { | |
4d732405 RS |
10560 | enum ia64_builtins fn_code |
10561 | = (enum ia64_builtins) DECL_MD_FUNCTION_CODE (fndecl); | |
b6ca982f UB |
10562 | switch (fn_code) |
10563 | { | |
10564 | case IA64_BUILTIN_NANQ: | |
10565 | case IA64_BUILTIN_NANSQ: | |
10566 | { | |
10567 | tree type = TREE_TYPE (TREE_TYPE (fndecl)); | |
10568 | const char *str = c_getstr (*args); | |
10569 | int quiet = fn_code == IA64_BUILTIN_NANQ; | |
10570 | REAL_VALUE_TYPE real; | |
10571 | ||
10572 | if (str && real_nan (&real, str, quiet, TYPE_MODE (type))) | |
10573 | return build_real (type, real); | |
10574 | return NULL_TREE; | |
10575 | } | |
10576 | ||
10577 | default: | |
10578 | break; | |
10579 | } | |
10580 | } | |
10581 | ||
10582 | #ifdef SUBTARGET_FOLD_BUILTIN | |
10583 | return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore); | |
10584 | #endif | |
10585 | ||
10586 | return NULL_TREE; | |
10587 | } | |
10588 | ||
c65ebc55 | 10589 | rtx |
9c808aad | 10590 | ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
ef4bddc2 | 10591 | machine_mode mode ATTRIBUTE_UNUSED, |
9c808aad | 10592 | int ignore ATTRIBUTE_UNUSED) |
c65ebc55 | 10593 | { |
767fad4c | 10594 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
4d732405 | 10595 | unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl); |
c65ebc55 JW |
10596 | |
10597 | switch (fcode) | |
10598 | { | |
ce152ef8 | 10599 | case IA64_BUILTIN_BSP: |
0551c32d RH |
10600 | if (! target || ! register_operand (target, DImode)) |
10601 | target = gen_reg_rtx (DImode); | |
10602 | emit_insn (gen_bsp_value (target)); | |
8419b675 RK |
10603 | #ifdef POINTERS_EXTEND_UNSIGNED |
10604 | target = convert_memory_address (ptr_mode, target); | |
10605 | #endif | |
0551c32d | 10606 | return target; |
ce152ef8 AM |
10607 | |
10608 | case IA64_BUILTIN_FLUSHRS: | |
3b572406 RH |
10609 | emit_insn (gen_flushrs ()); |
10610 | return const0_rtx; | |
ce152ef8 | 10611 | |
c252db20 | 10612 | case IA64_BUILTIN_INFQ: |
fcb82ab0 | 10613 | case IA64_BUILTIN_HUGE_VALQ: |
c252db20 | 10614 | { |
ef4bddc2 | 10615 | machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp)); |
c252db20 L |
10616 | REAL_VALUE_TYPE inf; |
10617 | rtx tmp; | |
10618 | ||
10619 | real_inf (&inf); | |
555affd7 | 10620 | tmp = const_double_from_real_value (inf, target_mode); |
c252db20 | 10621 | |
6aad068a | 10622 | tmp = validize_mem (force_const_mem (target_mode, tmp)); |
c252db20 L |
10623 | |
10624 | if (target == 0) | |
6aad068a | 10625 | target = gen_reg_rtx (target_mode); |
c252db20 L |
10626 | |
10627 | emit_move_insn (target, tmp); | |
10628 | return target; | |
10629 | } | |
10630 | ||
b6ca982f UB |
10631 | case IA64_BUILTIN_NANQ: |
10632 | case IA64_BUILTIN_NANSQ: | |
c252db20 L |
10633 | case IA64_BUILTIN_FABSQ: |
10634 | case IA64_BUILTIN_COPYSIGNQ: | |
10635 | return expand_call (exp, target, ignore); | |
10636 | ||
c65ebc55 | 10637 | default: |
c252db20 | 10638 | gcc_unreachable (); |
c65ebc55 JW |
10639 | } |
10640 | ||
0551c32d | 10641 | return NULL_RTX; |
c65ebc55 | 10642 | } |
0d7839da | 10643 | |
b14446e2 SE |
10644 | /* Return the ia64 builtin for CODE. */ |
10645 | ||
10646 | static tree | |
10647 | ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
10648 | { | |
10649 | if (code >= IA64_BUILTIN_max) | |
10650 | return error_mark_node; | |
10651 | ||
10652 | return ia64_builtins[code]; | |
10653 | } | |
10654 | ||
76b0cbf8 RS |
10655 | /* Implement TARGET_FUNCTION_ARG_PADDING. |
10656 | ||
10657 | For the HP-UX IA64 aggregate parameters are passed stored in the | |
0d7839da SE |
10658 | most significant bits of the stack slot. */ |
10659 | ||
76b0cbf8 RS |
10660 | static pad_direction |
10661 | ia64_function_arg_padding (machine_mode mode, const_tree type) | |
0d7839da | 10662 | { |
76b0cbf8 RS |
10663 | /* Exception to normal case for structures/unions/etc. */ |
10664 | if (TARGET_HPUX | |
10665 | && type | |
10666 | && AGGREGATE_TYPE_P (type) | |
10667 | && int_size_in_bytes (type) < UNITS_PER_WORD) | |
10668 | return PAD_UPWARD; | |
0d7839da | 10669 | |
76b0cbf8 RS |
10670 | /* Fall back to the default. */ |
10671 | return default_function_arg_padding (mode, type); | |
0d7839da | 10672 | } |
686f3bf0 | 10673 | |
c47c29c8 L |
10674 | /* Emit text to declare externally defined variables and functions, because |
10675 | the Intel assembler does not support undefined externals. */ | |
686f3bf0 | 10676 | |
c47c29c8 L |
10677 | void |
10678 | ia64_asm_output_external (FILE *file, tree decl, const char *name) | |
686f3bf0 | 10679 | { |
c47c29c8 L |
10680 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
10681 | set in order to avoid putting out names that are never really | |
10682 | used. */ | |
10683 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
686f3bf0 | 10684 | { |
c47c29c8 | 10685 | /* maybe_assemble_visibility will return 1 if the assembler |
2e226e66 | 10686 | visibility directive is output. */ |
c47c29c8 L |
10687 | int need_visibility = ((*targetm.binds_local_p) (decl) |
10688 | && maybe_assemble_visibility (decl)); | |
57d4f65c | 10689 | |
c47c29c8 L |
10690 | /* GNU as does not need anything here, but the HP linker does |
10691 | need something for external functions. */ | |
10692 | if ((TARGET_HPUX_LD || !TARGET_GNU_AS) | |
10693 | && TREE_CODE (decl) == FUNCTION_DECL) | |
812b587e | 10694 | (*targetm.asm_out.globalize_decl_name) (file, decl); |
c47c29c8 L |
10695 | else if (need_visibility && !TARGET_GNU_AS) |
10696 | (*targetm.asm_out.globalize_label) (file, name); | |
686f3bf0 SE |
10697 | } |
10698 | } | |
10699 | ||
1f7aa7cd | 10700 | /* Set SImode div/mod functions, init_integral_libfuncs only initializes |
6bc709c1 L |
10701 | modes of word_mode and larger. Rename the TFmode libfuncs using the |
10702 | HPUX conventions. __divtf3 is used for XFmode. We need to keep it for | |
10703 | backward compatibility. */ | |
1f7aa7cd SE |
10704 | |
10705 | static void | |
10706 | ia64_init_libfuncs (void) | |
10707 | { | |
10708 | set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); | |
10709 | set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); | |
10710 | set_optab_libfunc (smod_optab, SImode, "__modsi3"); | |
10711 | set_optab_libfunc (umod_optab, SImode, "__umodsi3"); | |
6bc709c1 L |
10712 | |
10713 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
10714 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
10715 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
10716 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
10717 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
10718 | ||
10719 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); | |
10720 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
10721 | set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad"); | |
10722 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
10723 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
10724 | set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80"); | |
10725 | ||
10726 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl"); | |
10727 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
4a73d865 | 10728 | set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad"); |
6bc709c1 L |
10729 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl"); |
10730 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl"); | |
10731 | ||
10732 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
10733 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
4a73d865 | 10734 | set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad"); |
2a3ebe77 JM |
10735 | /* HP-UX 11.23 libc does not have a function for unsigned |
10736 | SImode-to-TFmode conversion. */ | |
10737 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad"); | |
1f7aa7cd SE |
10738 | } |
10739 | ||
c15c90bb | 10740 | /* Rename all the TFmode libfuncs using the HPUX conventions. */ |
738e7b39 | 10741 | |
c15c90bb ZW |
10742 | static void |
10743 | ia64_hpux_init_libfuncs (void) | |
10744 | { | |
1f7aa7cd SE |
10745 | ia64_init_libfuncs (); |
10746 | ||
bdbba3c2 SE |
10747 | /* The HP SI millicode division and mod functions expect DI arguments. |
10748 | By turning them off completely we avoid using both libgcc and the | |
10749 | non-standard millicode routines and use the HP DI millicode routines | |
10750 | instead. */ | |
10751 | ||
10752 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
10753 | set_optab_libfunc (udiv_optab, SImode, 0); | |
10754 | set_optab_libfunc (smod_optab, SImode, 0); | |
10755 | set_optab_libfunc (umod_optab, SImode, 0); | |
10756 | ||
10757 | set_optab_libfunc (sdiv_optab, DImode, "__milli_divI"); | |
10758 | set_optab_libfunc (udiv_optab, DImode, "__milli_divU"); | |
10759 | set_optab_libfunc (smod_optab, DImode, "__milli_remI"); | |
10760 | set_optab_libfunc (umod_optab, DImode, "__milli_remU"); | |
10761 | ||
10762 | /* HP-UX libc has TF min/max/abs routines in it. */ | |
c15c90bb ZW |
10763 | set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin"); |
10764 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
10765 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
c15c90bb | 10766 | |
24ea7948 ZW |
10767 | /* ia64_expand_compare uses this. */ |
10768 | cmptf_libfunc = init_one_libfunc ("_U_Qfcmp"); | |
10769 | ||
10770 | /* These should never be used. */ | |
10771 | set_optab_libfunc (eq_optab, TFmode, 0); | |
10772 | set_optab_libfunc (ne_optab, TFmode, 0); | |
10773 | set_optab_libfunc (gt_optab, TFmode, 0); | |
10774 | set_optab_libfunc (ge_optab, TFmode, 0); | |
10775 | set_optab_libfunc (lt_optab, TFmode, 0); | |
10776 | set_optab_libfunc (le_optab, TFmode, 0); | |
c15c90bb | 10777 | } |
738e7b39 RK |
10778 | |
10779 | /* Rename the division and modulus functions in VMS. */ | |
10780 | ||
10781 | static void | |
10782 | ia64_vms_init_libfuncs (void) | |
10783 | { | |
10784 | set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I"); | |
10785 | set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L"); | |
10786 | set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI"); | |
10787 | set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL"); | |
10788 | set_optab_libfunc (smod_optab, SImode, "OTS$REM_I"); | |
10789 | set_optab_libfunc (smod_optab, DImode, "OTS$REM_L"); | |
10790 | set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI"); | |
10791 | set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL"); | |
f2972bf8 DR |
10792 | #ifdef MEM_LIBFUNCS_INIT |
10793 | MEM_LIBFUNCS_INIT; | |
10794 | #endif | |
738e7b39 | 10795 | } |
6bc709c1 L |
10796 | |
10797 | /* Rename the TFmode libfuncs available from soft-fp in glibc using | |
10798 | the HPUX conventions. */ | |
10799 | ||
10800 | static void | |
10801 | ia64_sysv4_init_libfuncs (void) | |
10802 | { | |
10803 | ia64_init_libfuncs (); | |
10804 | ||
10805 | /* These functions are not part of the HPUX TFmode interface. We | |
10806 | use them instead of _U_Qfcmp, which doesn't work the way we | |
10807 | expect. */ | |
10808 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); | |
10809 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
10810 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
10811 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
10812 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
10813 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
10814 | ||
10815 | /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in | |
10816 | glibc doesn't have them. */ | |
10817 | } | |
c252db20 L |
10818 | |
10819 | /* Use soft-fp. */ | |
10820 | ||
10821 | static void | |
10822 | ia64_soft_fp_init_libfuncs (void) | |
10823 | { | |
10824 | } | |
f2972bf8 DR |
10825 | |
10826 | static bool | |
095a2d76 | 10827 | ia64_vms_valid_pointer_mode (scalar_int_mode mode) |
f2972bf8 DR |
10828 | { |
10829 | return (mode == SImode || mode == DImode); | |
10830 | } | |
ae46c4e0 | 10831 | \f |
9b580a0b RH |
10832 | /* For HPUX, it is illegal to have relocations in shared segments. */ |
10833 | ||
10834 | static int | |
10835 | ia64_hpux_reloc_rw_mask (void) | |
10836 | { | |
10837 | return 3; | |
10838 | } | |
10839 | ||
10840 | /* For others, relax this so that relocations to local data goes in | |
10841 | read-only segments, but we still cannot allow global relocations | |
10842 | in read-only segments. */ | |
10843 | ||
10844 | static int | |
10845 | ia64_reloc_rw_mask (void) | |
10846 | { | |
10847 | return flag_pic ? 3 : 2; | |
10848 | } | |
10849 | ||
d6b5193b RS |
10850 | /* Return the section to use for X. The only special thing we do here |
10851 | is to honor small data. */ | |
b64a1b53 | 10852 | |
d6b5193b | 10853 | static section * |
ef4bddc2 | 10854 | ia64_select_rtx_section (machine_mode mode, rtx x, |
9c808aad | 10855 | unsigned HOST_WIDE_INT align) |
b64a1b53 RH |
10856 | { |
10857 | if (GET_MODE_SIZE (mode) > 0 | |
1f4a2e84 SE |
10858 | && GET_MODE_SIZE (mode) <= ia64_section_threshold |
10859 | && !TARGET_NO_SDATA) | |
d6b5193b | 10860 | return sdata_section; |
b64a1b53 | 10861 | else |
d6b5193b | 10862 | return default_elf_select_rtx_section (mode, x, align); |
b64a1b53 RH |
10863 | } |
10864 | ||
1e1bd14e | 10865 | static unsigned int |
abb8b19a AM |
10866 | ia64_section_type_flags (tree decl, const char *name, int reloc) |
10867 | { | |
10868 | unsigned int flags = 0; | |
10869 | ||
10870 | if (strcmp (name, ".sdata") == 0 | |
10871 | || strncmp (name, ".sdata.", 7) == 0 | |
10872 | || strncmp (name, ".gnu.linkonce.s.", 16) == 0 | |
10873 | || strncmp (name, ".sdata2.", 8) == 0 | |
10874 | || strncmp (name, ".gnu.linkonce.s2.", 17) == 0 | |
10875 | || strcmp (name, ".sbss") == 0 | |
10876 | || strncmp (name, ".sbss.", 6) == 0 | |
10877 | || strncmp (name, ".gnu.linkonce.sb.", 17) == 0) | |
10878 | flags = SECTION_SMALL; | |
10879 | ||
9b580a0b | 10880 | flags |= default_section_type_flags (decl, name, reloc); |
abb8b19a | 10881 | return flags; |
1e1bd14e RH |
10882 | } |
10883 | ||
57782ad8 MM |
10884 | /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a |
10885 | structure type and that the address of that type should be passed | |
10886 | in out0, rather than in r8. */ | |
10887 | ||
10888 | static bool | |
10889 | ia64_struct_retval_addr_is_first_parm_p (tree fntype) | |
10890 | { | |
10891 | tree ret_type = TREE_TYPE (fntype); | |
10892 | ||
10893 | /* The Itanium C++ ABI requires that out0, rather than r8, be used | |
10894 | as the structure return address parameter, if the return value | |
10895 | type has a non-trivial copy constructor or destructor. It is not | |
10896 | clear if this same convention should be used for other | |
10897 | programming languages. Until G++ 3.4, we incorrectly used r8 for | |
10898 | these return values. */ | |
10899 | return (abi_version_at_least (2) | |
10900 | && ret_type | |
10901 | && TYPE_MODE (ret_type) == BLKmode | |
10902 | && TREE_ADDRESSABLE (ret_type) | |
dcc97066 | 10903 | && lang_GNU_CXX ()); |
57782ad8 | 10904 | } |
1e1bd14e | 10905 | |
5f13cfc6 RH |
10906 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
10907 | declaration for the thunk function itself, FUNCTION is the decl for | |
10908 | the target function. DELTA is an immediate constant offset to be | |
272d0bee | 10909 | added to THIS. If VCALL_OFFSET is nonzero, the word at |
5f13cfc6 RH |
10910 | *(*this + vcall_offset) should be added to THIS. */ |
10911 | ||
c590b625 | 10912 | static void |
9c808aad AJ |
10913 | ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
10914 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
10915 | tree function) | |
483ab821 | 10916 | { |
f7430263 | 10917 | const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); |
dd3d2b35 DM |
10918 | rtx this_rtx, funexp; |
10919 | rtx_insn *insn; | |
57782ad8 MM |
10920 | unsigned int this_parmno; |
10921 | unsigned int this_regno; | |
13f70342 | 10922 | rtx delta_rtx; |
5f13cfc6 | 10923 | |
599aedd9 | 10924 | reload_completed = 1; |
fe3ad572 | 10925 | epilogue_completed = 1; |
599aedd9 | 10926 | |
5f13cfc6 RH |
10927 | /* Set things up as ia64_expand_prologue might. */ |
10928 | last_scratch_gr_reg = 15; | |
10929 | ||
10930 | memset (¤t_frame_info, 0, sizeof (current_frame_info)); | |
10931 | current_frame_info.spill_cfa_off = -16; | |
10932 | current_frame_info.n_input_regs = 1; | |
10933 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
10934 | ||
5f13cfc6 | 10935 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 10936 | emit_note (NOTE_INSN_PROLOGUE_END); |
5f13cfc6 | 10937 | |
57782ad8 MM |
10938 | /* Figure out whether "this" will be the first parameter (the |
10939 | typical case) or the second parameter (as happens when the | |
10940 | virtual function returns certain class objects). */ | |
10941 | this_parmno | |
10942 | = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk)) | |
10943 | ? 1 : 0); | |
10944 | this_regno = IN_REG (this_parmno); | |
10945 | if (!TARGET_REG_NAMES) | |
10946 | reg_names[this_regno] = ia64_reg_numbers[this_parmno]; | |
10947 | ||
0a2aaacc | 10948 | this_rtx = gen_rtx_REG (Pmode, this_regno); |
13f70342 RH |
10949 | |
10950 | /* Apply the constant offset, if required. */ | |
10951 | delta_rtx = GEN_INT (delta); | |
36c216e5 MM |
10952 | if (TARGET_ILP32) |
10953 | { | |
57782ad8 | 10954 | rtx tmp = gen_rtx_REG (ptr_mode, this_regno); |
36c216e5 | 10955 | REG_POINTER (tmp) = 1; |
13f70342 | 10956 | if (delta && satisfies_constraint_I (delta_rtx)) |
36c216e5 | 10957 | { |
0a2aaacc | 10958 | emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx)); |
36c216e5 MM |
10959 | delta = 0; |
10960 | } | |
10961 | else | |
0a2aaacc | 10962 | emit_insn (gen_ptr_extend (this_rtx, tmp)); |
36c216e5 | 10963 | } |
5f13cfc6 RH |
10964 | if (delta) |
10965 | { | |
13f70342 | 10966 | if (!satisfies_constraint_I (delta_rtx)) |
5f13cfc6 RH |
10967 | { |
10968 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10969 | emit_move_insn (tmp, delta_rtx); | |
10970 | delta_rtx = tmp; | |
10971 | } | |
0a2aaacc | 10972 | emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx)); |
5f13cfc6 RH |
10973 | } |
10974 | ||
10975 | /* Apply the offset from the vtable, if required. */ | |
10976 | if (vcall_offset) | |
10977 | { | |
10978 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); | |
10979 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10980 | ||
36c216e5 MM |
10981 | if (TARGET_ILP32) |
10982 | { | |
10983 | rtx t = gen_rtx_REG (ptr_mode, 2); | |
10984 | REG_POINTER (t) = 1; | |
0a2aaacc | 10985 | emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx)); |
13f70342 | 10986 | if (satisfies_constraint_I (vcall_offset_rtx)) |
36c216e5 | 10987 | { |
13f70342 | 10988 | emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx)); |
36c216e5 MM |
10989 | vcall_offset = 0; |
10990 | } | |
10991 | else | |
10992 | emit_insn (gen_ptr_extend (tmp, t)); | |
10993 | } | |
10994 | else | |
0a2aaacc | 10995 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); |
5f13cfc6 | 10996 | |
36c216e5 | 10997 | if (vcall_offset) |
5f13cfc6 | 10998 | { |
13f70342 | 10999 | if (!satisfies_constraint_J (vcall_offset_rtx)) |
36c216e5 MM |
11000 | { |
11001 | rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ()); | |
11002 | emit_move_insn (tmp2, vcall_offset_rtx); | |
11003 | vcall_offset_rtx = tmp2; | |
11004 | } | |
11005 | emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
5f13cfc6 | 11006 | } |
5f13cfc6 | 11007 | |
36c216e5 | 11008 | if (TARGET_ILP32) |
13f70342 | 11009 | emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp))); |
36c216e5 MM |
11010 | else |
11011 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
5f13cfc6 | 11012 | |
0a2aaacc | 11013 | emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp)); |
5f13cfc6 RH |
11014 | } |
11015 | ||
11016 | /* Generate a tail call to the target function. */ | |
11017 | if (! TREE_USED (function)) | |
11018 | { | |
11019 | assemble_external (function); | |
11020 | TREE_USED (function) = 1; | |
11021 | } | |
11022 | funexp = XEXP (DECL_RTL (function), 0); | |
11023 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
11024 | ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1); | |
11025 | insn = get_last_insn (); | |
11026 | SIBLING_CALL_P (insn) = 1; | |
599aedd9 RH |
11027 | |
11028 | /* Code generation for calls relies on splitting. */ | |
11029 | reload_completed = 1; | |
fe3ad572 | 11030 | epilogue_completed = 1; |
599aedd9 RH |
11031 | try_split (PATTERN (insn), insn, 0); |
11032 | ||
5f13cfc6 RH |
11033 | emit_barrier (); |
11034 | ||
11035 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
11036 | There's not really enough bulk here to make other passes such as | |
8b4e7143 | 11037 | instruction scheduling worth while. */ |
599aedd9 | 11038 | |
18dbd950 | 11039 | emit_all_insn_group_barriers (NULL); |
5f13cfc6 | 11040 | insn = get_insns (); |
5f13cfc6 | 11041 | shorten_branches (insn); |
f7430263 | 11042 | assemble_start_function (thunk, fnname); |
5f13cfc6 | 11043 | final_start_function (insn, file, 1); |
c9d691e9 | 11044 | final (insn, file, 1); |
5f13cfc6 | 11045 | final_end_function (); |
f7430263 | 11046 | assemble_end_function (thunk, fnname); |
599aedd9 RH |
11047 | |
11048 | reload_completed = 0; | |
fe3ad572 | 11049 | epilogue_completed = 0; |
483ab821 MM |
11050 | } |
11051 | ||
351a758b KH |
11052 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
11053 | ||
11054 | static rtx | |
57782ad8 | 11055 | ia64_struct_value_rtx (tree fntype, |
351a758b KH |
11056 | int incoming ATTRIBUTE_UNUSED) |
11057 | { | |
f2972bf8 DR |
11058 | if (TARGET_ABI_OPEN_VMS || |
11059 | (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))) | |
57782ad8 | 11060 | return NULL_RTX; |
351a758b KH |
11061 | return gen_rtx_REG (Pmode, GR_REG (8)); |
11062 | } | |
11063 | ||
88ed5ef5 | 11064 | static bool |
18e2a8b8 | 11065 | ia64_scalar_mode_supported_p (scalar_mode mode) |
88ed5ef5 SE |
11066 | { |
11067 | switch (mode) | |
11068 | { | |
4e10a5a7 RS |
11069 | case E_QImode: |
11070 | case E_HImode: | |
11071 | case E_SImode: | |
11072 | case E_DImode: | |
11073 | case E_TImode: | |
88ed5ef5 SE |
11074 | return true; |
11075 | ||
4e10a5a7 RS |
11076 | case E_SFmode: |
11077 | case E_DFmode: | |
11078 | case E_XFmode: | |
11079 | case E_RFmode: | |
88ed5ef5 SE |
11080 | return true; |
11081 | ||
4e10a5a7 | 11082 | case E_TFmode: |
c252db20 | 11083 | return true; |
88ed5ef5 SE |
11084 | |
11085 | default: | |
11086 | return false; | |
11087 | } | |
11088 | } | |
11089 | ||
f61134e8 | 11090 | static bool |
ef4bddc2 | 11091 | ia64_vector_mode_supported_p (machine_mode mode) |
f61134e8 RH |
11092 | { |
11093 | switch (mode) | |
11094 | { | |
4e10a5a7 RS |
11095 | case E_V8QImode: |
11096 | case E_V4HImode: | |
11097 | case E_V2SImode: | |
f61134e8 RH |
11098 | return true; |
11099 | ||
4e10a5a7 | 11100 | case E_V2SFmode: |
f61134e8 RH |
11101 | return true; |
11102 | ||
11103 | default: | |
11104 | return false; | |
11105 | } | |
11106 | } | |
11107 | ||
694a2f6e EB |
11108 | /* Implement the FUNCTION_PROFILER macro. */ |
11109 | ||
2b4f149b RH |
11110 | void |
11111 | ia64_output_function_profiler (FILE *file, int labelno) | |
11112 | { | |
694a2f6e EB |
11113 | bool indirect_call; |
11114 | ||
11115 | /* If the function needs a static chain and the static chain | |
11116 | register is r15, we use an indirect call so as to bypass | |
11117 | the PLT stub in case the executable is dynamically linked, | |
11118 | because the stub clobbers r15 as per 5.3.6 of the psABI. | |
11119 | We don't need to do that in non canonical PIC mode. */ | |
11120 | ||
11121 | if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC) | |
11122 | { | |
11123 | gcc_assert (STATIC_CHAIN_REGNUM == 15); | |
11124 | indirect_call = true; | |
11125 | } | |
11126 | else | |
11127 | indirect_call = false; | |
11128 | ||
2b4f149b RH |
11129 | if (TARGET_GNU_AS) |
11130 | fputs ("\t.prologue 4, r40\n", file); | |
11131 | else | |
11132 | fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file); | |
11133 | fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file); | |
bd8633a3 RH |
11134 | |
11135 | if (NO_PROFILE_COUNTERS) | |
694a2f6e | 11136 | fputs ("\tmov out3 = r0\n", file); |
bd8633a3 RH |
11137 | else |
11138 | { | |
11139 | char buf[20]; | |
11140 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
11141 | ||
11142 | if (TARGET_AUTO_PIC) | |
11143 | fputs ("\tmovl out3 = @gprel(", file); | |
11144 | else | |
11145 | fputs ("\taddl out3 = @ltoff(", file); | |
11146 | assemble_name (file, buf); | |
11147 | if (TARGET_AUTO_PIC) | |
694a2f6e | 11148 | fputs (")\n", file); |
bd8633a3 | 11149 | else |
694a2f6e | 11150 | fputs ("), r1\n", file); |
bd8633a3 RH |
11151 | } |
11152 | ||
694a2f6e EB |
11153 | if (indirect_call) |
11154 | fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file); | |
11155 | fputs ("\t;;\n", file); | |
11156 | ||
2b4f149b | 11157 | fputs ("\t.save rp, r42\n", file); |
bd8633a3 | 11158 | fputs ("\tmov out2 = b0\n", file); |
694a2f6e EB |
11159 | if (indirect_call) |
11160 | fputs ("\tld8 r14 = [r14]\n\t;;\n", file); | |
2b4f149b | 11161 | fputs ("\t.body\n", file); |
2b4f149b | 11162 | fputs ("\tmov out1 = r1\n", file); |
694a2f6e EB |
11163 | if (indirect_call) |
11164 | { | |
11165 | fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file); | |
11166 | fputs ("\tmov b6 = r16\n", file); | |
11167 | fputs ("\tld8 r1 = [r14]\n", file); | |
11168 | fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file); | |
11169 | } | |
11170 | else | |
11171 | fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file); | |
2b4f149b RH |
11172 | } |
11173 | ||
d26afa4f SE |
11174 | static GTY(()) rtx mcount_func_rtx; |
11175 | static rtx | |
11176 | gen_mcount_func_rtx (void) | |
11177 | { | |
11178 | if (!mcount_func_rtx) | |
11179 | mcount_func_rtx = init_one_libfunc ("_mcount"); | |
11180 | return mcount_func_rtx; | |
11181 | } | |
11182 | ||
11183 | void | |
11184 | ia64_profile_hook (int labelno) | |
11185 | { | |
11186 | rtx label, ip; | |
11187 | ||
11188 | if (NO_PROFILE_COUNTERS) | |
11189 | label = const0_rtx; | |
11190 | else | |
11191 | { | |
11192 | char buf[30]; | |
11193 | const char *label_name; | |
11194 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
55504c7c | 11195 | label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf)); |
d26afa4f SE |
11196 | label = gen_rtx_SYMBOL_REF (Pmode, label_name); |
11197 | SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL; | |
11198 | } | |
11199 | ip = gen_reg_rtx (Pmode); | |
11200 | emit_insn (gen_ip_value (ip)); | |
11201 | emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL, | |
db69559b | 11202 | VOIDmode, |
d26afa4f SE |
11203 | gen_rtx_REG (Pmode, BR_REG (0)), Pmode, |
11204 | ip, Pmode, | |
11205 | label, Pmode); | |
11206 | } | |
11207 | ||
cac24f06 JM |
11208 | /* Return the mangling of TYPE if it is an extended fundamental type. */ |
11209 | ||
11210 | static const char * | |
3101faab | 11211 | ia64_mangle_type (const_tree type) |
cac24f06 | 11212 | { |
608063c3 JB |
11213 | type = TYPE_MAIN_VARIANT (type); |
11214 | ||
11215 | if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE | |
11216 | && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) | |
11217 | return NULL; | |
11218 | ||
cac24f06 JM |
11219 | /* On HP-UX, "long double" is mangled as "e" so __float128 is |
11220 | mangled as "e". */ | |
11221 | if (!TARGET_HPUX && TYPE_MODE (type) == TFmode) | |
11222 | return "g"; | |
11223 | /* On HP-UX, "e" is not available as a mangling of __float80 so use | |
11224 | an extended mangling. Elsewhere, "e" is available since long | |
11225 | double is 80 bits. */ | |
11226 | if (TYPE_MODE (type) == XFmode) | |
11227 | return TARGET_HPUX ? "u9__float80" : "e"; | |
4de67c26 JM |
11228 | if (TYPE_MODE (type) == RFmode) |
11229 | return "u7__fpreg"; | |
11230 | return NULL; | |
11231 | } | |
11232 | ||
11233 | /* Return the diagnostic message string if conversion from FROMTYPE to | |
11234 | TOTYPE is not allowed, NULL otherwise. */ | |
11235 | static const char * | |
3101faab | 11236 | ia64_invalid_conversion (const_tree fromtype, const_tree totype) |
4de67c26 JM |
11237 | { |
11238 | /* Reject nontrivial conversion to or from __fpreg. */ | |
11239 | if (TYPE_MODE (fromtype) == RFmode | |
11240 | && TYPE_MODE (totype) != RFmode | |
11241 | && TYPE_MODE (totype) != VOIDmode) | |
11242 | return N_("invalid conversion from %<__fpreg%>"); | |
11243 | if (TYPE_MODE (totype) == RFmode | |
11244 | && TYPE_MODE (fromtype) != RFmode) | |
11245 | return N_("invalid conversion to %<__fpreg%>"); | |
11246 | return NULL; | |
11247 | } | |
11248 | ||
11249 | /* Return the diagnostic message string if the unary operation OP is | |
11250 | not permitted on TYPE, NULL otherwise. */ | |
11251 | static const char * | |
3101faab | 11252 | ia64_invalid_unary_op (int op, const_tree type) |
4de67c26 JM |
11253 | { |
11254 | /* Reject operations on __fpreg other than unary + or &. */ | |
11255 | if (TYPE_MODE (type) == RFmode | |
11256 | && op != CONVERT_EXPR | |
11257 | && op != ADDR_EXPR) | |
11258 | return N_("invalid operation on %<__fpreg%>"); | |
11259 | return NULL; | |
11260 | } | |
11261 | ||
11262 | /* Return the diagnostic message string if the binary operation OP is | |
11263 | not permitted on TYPE1 and TYPE2, NULL otherwise. */ | |
11264 | static const char * | |
3101faab | 11265 | ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2) |
4de67c26 JM |
11266 | { |
11267 | /* Reject operations on __fpreg. */ | |
11268 | if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode) | |
11269 | return N_("invalid operation on %<__fpreg%>"); | |
cac24f06 JM |
11270 | return NULL; |
11271 | } | |
11272 | ||
812b587e SE |
11273 | /* HP-UX version_id attribute. |
11274 | For object foo, if the version_id is set to 1234 put out an alias | |
11275 | of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything | |
11276 | other than an alias statement because it is an illegal symbol name. */ | |
11277 | ||
11278 | static tree | |
11279 | ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED, | |
11280 | tree name ATTRIBUTE_UNUSED, | |
11281 | tree args, | |
11282 | int flags ATTRIBUTE_UNUSED, | |
11283 | bool *no_add_attrs) | |
11284 | { | |
11285 | tree arg = TREE_VALUE (args); | |
11286 | ||
11287 | if (TREE_CODE (arg) != STRING_CST) | |
11288 | { | |
11289 | error("version attribute is not a string"); | |
11290 | *no_add_attrs = true; | |
11291 | return NULL_TREE; | |
11292 | } | |
11293 | return NULL_TREE; | |
11294 | } | |
11295 | ||
a31fa2e0 SE |
11296 | /* Target hook for c_mode_for_suffix. */ |
11297 | ||
ef4bddc2 | 11298 | static machine_mode |
a31fa2e0 SE |
11299 | ia64_c_mode_for_suffix (char suffix) |
11300 | { | |
11301 | if (suffix == 'q') | |
11302 | return TFmode; | |
11303 | if (suffix == 'w') | |
11304 | return XFmode; | |
11305 | ||
11306 | return VOIDmode; | |
11307 | } | |
11308 | ||
f3a83111 SE |
11309 | static GTY(()) rtx ia64_dconst_0_5_rtx; |
11310 | ||
11311 | rtx | |
11312 | ia64_dconst_0_5 (void) | |
11313 | { | |
11314 | if (! ia64_dconst_0_5_rtx) | |
11315 | { | |
11316 | REAL_VALUE_TYPE rv; | |
11317 | real_from_string (&rv, "0.5"); | |
11318 | ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode); | |
11319 | } | |
11320 | return ia64_dconst_0_5_rtx; | |
11321 | } | |
11322 | ||
11323 | static GTY(()) rtx ia64_dconst_0_375_rtx; | |
11324 | ||
11325 | rtx | |
11326 | ia64_dconst_0_375 (void) | |
11327 | { | |
11328 | if (! ia64_dconst_0_375_rtx) | |
11329 | { | |
11330 | REAL_VALUE_TYPE rv; | |
11331 | real_from_string (&rv, "0.375"); | |
11332 | ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode); | |
11333 | } | |
11334 | return ia64_dconst_0_375_rtx; | |
11335 | } | |
11336 | ||
ef1d3b57 | 11337 | static fixed_size_mode |
ffa88471 SE |
11338 | ia64_get_reg_raw_mode (int regno) |
11339 | { | |
11340 | if (FR_REGNO_P (regno)) | |
11341 | return XFmode; | |
11342 | return default_get_reg_raw_mode(regno); | |
11343 | } | |
f3a83111 | 11344 | |
d9886a9e L |
11345 | /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed |
11346 | anymore. */ | |
11347 | ||
11348 | bool | |
ef4bddc2 | 11349 | ia64_member_type_forces_blk (const_tree, machine_mode mode) |
d9886a9e L |
11350 | { |
11351 | return TARGET_HPUX && mode == TFmode; | |
11352 | } | |
11353 | ||
f16d3f39 JH |
11354 | /* Always default to .text section until HP-UX linker is fixed. */ |
11355 | ||
11356 | ATTRIBUTE_UNUSED static section * | |
11357 | ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED, | |
11358 | enum node_frequency freq ATTRIBUTE_UNUSED, | |
11359 | bool startup ATTRIBUTE_UNUSED, | |
11360 | bool exit ATTRIBUTE_UNUSED) | |
11361 | { | |
11362 | return NULL; | |
11363 | } | |
e6431744 RH |
11364 | \f |
11365 | /* Construct (set target (vec_select op0 (parallel perm))) and | |
11366 | return true if that's a valid instruction in the active ISA. */ | |
11367 | ||
11368 | static bool | |
11369 | expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt) | |
11370 | { | |
11371 | rtx rperm[MAX_VECT_LEN], x; | |
11372 | unsigned i; | |
11373 | ||
11374 | for (i = 0; i < nelt; ++i) | |
11375 | rperm[i] = GEN_INT (perm[i]); | |
11376 | ||
11377 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); | |
11378 | x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); | |
f7df4a84 | 11379 | x = gen_rtx_SET (target, x); |
e6431744 | 11380 | |
647d790d DM |
11381 | rtx_insn *insn = emit_insn (x); |
11382 | if (recog_memoized (insn) < 0) | |
e6431744 | 11383 | { |
647d790d | 11384 | remove_insn (insn); |
e6431744 RH |
11385 | return false; |
11386 | } | |
11387 | return true; | |
11388 | } | |
11389 | ||
11390 | /* Similar, but generate a vec_concat from op0 and op1 as well. */ | |
11391 | ||
11392 | static bool | |
11393 | expand_vselect_vconcat (rtx target, rtx op0, rtx op1, | |
11394 | const unsigned char *perm, unsigned nelt) | |
11395 | { | |
ef4bddc2 | 11396 | machine_mode v2mode; |
e6431744 RH |
11397 | rtx x; |
11398 | ||
490d0f6c RS |
11399 | if (!GET_MODE_2XWIDER_MODE (GET_MODE (op0)).exists (&v2mode)) |
11400 | return false; | |
e6431744 RH |
11401 | x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); |
11402 | return expand_vselect (target, x, perm, nelt); | |
11403 | } | |
11404 | ||
11405 | /* Try to expand a no-op permutation. */ | |
11406 | ||
11407 | static bool | |
11408 | expand_vec_perm_identity (struct expand_vec_perm_d *d) | |
11409 | { | |
11410 | unsigned i, nelt = d->nelt; | |
11411 | ||
11412 | for (i = 0; i < nelt; ++i) | |
11413 | if (d->perm[i] != i) | |
11414 | return false; | |
11415 | ||
11416 | if (!d->testing_p) | |
11417 | emit_move_insn (d->target, d->op0); | |
11418 | ||
11419 | return true; | |
11420 | } | |
11421 | ||
11422 | /* Try to expand D via a shrp instruction. */ | |
11423 | ||
11424 | static bool | |
11425 | expand_vec_perm_shrp (struct expand_vec_perm_d *d) | |
11426 | { | |
11427 | unsigned i, nelt = d->nelt, shift, mask; | |
2d130b31 | 11428 | rtx tmp, hi, lo; |
e6431744 RH |
11429 | |
11430 | /* ??? Don't force V2SFmode into the integer registers. */ | |
11431 | if (d->vmode == V2SFmode) | |
11432 | return false; | |
11433 | ||
11434 | mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1); | |
11435 | ||
11436 | shift = d->perm[0]; | |
2d130b31 UB |
11437 | if (BYTES_BIG_ENDIAN && shift > nelt) |
11438 | return false; | |
11439 | ||
e6431744 RH |
11440 | for (i = 1; i < nelt; ++i) |
11441 | if (d->perm[i] != ((shift + i) & mask)) | |
11442 | return false; | |
11443 | ||
11444 | if (d->testing_p) | |
11445 | return true; | |
11446 | ||
2d130b31 UB |
11447 | hi = shift < nelt ? d->op1 : d->op0; |
11448 | lo = shift < nelt ? d->op0 : d->op1; | |
11449 | ||
11450 | shift %= nelt; | |
11451 | ||
e6431744 RH |
11452 | shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT; |
11453 | ||
11454 | /* We've eliminated the shift 0 case via expand_vec_perm_identity. */ | |
11455 | gcc_assert (IN_RANGE (shift, 1, 63)); | |
11456 | ||
11457 | /* Recall that big-endian elements are numbered starting at the top of | |
11458 | the register. Ideally we'd have a shift-left-pair. But since we | |
11459 | don't, convert to a shift the other direction. */ | |
11460 | if (BYTES_BIG_ENDIAN) | |
11461 | shift = 64 - shift; | |
11462 | ||
11463 | tmp = gen_reg_rtx (DImode); | |
2d130b31 UB |
11464 | hi = gen_lowpart (DImode, hi); |
11465 | lo = gen_lowpart (DImode, lo); | |
11466 | emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift))); | |
e6431744 RH |
11467 | |
11468 | emit_move_insn (d->target, gen_lowpart (d->vmode, tmp)); | |
11469 | return true; | |
11470 | } | |
11471 | ||
11472 | /* Try to instantiate D in a single instruction. */ | |
11473 | ||
11474 | static bool | |
11475 | expand_vec_perm_1 (struct expand_vec_perm_d *d) | |
11476 | { | |
11477 | unsigned i, nelt = d->nelt; | |
11478 | unsigned char perm2[MAX_VECT_LEN]; | |
11479 | ||
11480 | /* Try single-operand selections. */ | |
11481 | if (d->one_operand_p) | |
11482 | { | |
11483 | if (expand_vec_perm_identity (d)) | |
11484 | return true; | |
11485 | if (expand_vselect (d->target, d->op0, d->perm, nelt)) | |
11486 | return true; | |
11487 | } | |
11488 | ||
11489 | /* Try two operand selections. */ | |
11490 | if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt)) | |
11491 | return true; | |
11492 | ||
11493 | /* Recognize interleave style patterns with reversed operands. */ | |
11494 | if (!d->one_operand_p) | |
11495 | { | |
11496 | for (i = 0; i < nelt; ++i) | |
11497 | { | |
11498 | unsigned e = d->perm[i]; | |
11499 | if (e >= nelt) | |
11500 | e -= nelt; | |
11501 | else | |
11502 | e += nelt; | |
11503 | perm2[i] = e; | |
11504 | } | |
11505 | ||
11506 | if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) | |
11507 | return true; | |
11508 | } | |
11509 | ||
11510 | if (expand_vec_perm_shrp (d)) | |
11511 | return true; | |
11512 | ||
11513 | /* ??? Look for deposit-like permutations where most of the result | |
11514 | comes from one vector unchanged and the rest comes from a | |
11515 | sequential hunk of the other vector. */ | |
11516 | ||
11517 | return false; | |
11518 | } | |
11519 | ||
11520 | /* Pattern match broadcast permutations. */ | |
11521 | ||
11522 | static bool | |
11523 | expand_vec_perm_broadcast (struct expand_vec_perm_d *d) | |
11524 | { | |
11525 | unsigned i, elt, nelt = d->nelt; | |
11526 | unsigned char perm2[2]; | |
11527 | rtx temp; | |
11528 | bool ok; | |
11529 | ||
11530 | if (!d->one_operand_p) | |
11531 | return false; | |
11532 | ||
11533 | elt = d->perm[0]; | |
11534 | for (i = 1; i < nelt; ++i) | |
11535 | if (d->perm[i] != elt) | |
11536 | return false; | |
11537 | ||
11538 | switch (d->vmode) | |
11539 | { | |
4e10a5a7 RS |
11540 | case E_V2SImode: |
11541 | case E_V2SFmode: | |
e6431744 RH |
11542 | /* Implementable by interleave. */ |
11543 | perm2[0] = elt; | |
11544 | perm2[1] = elt + 2; | |
11545 | ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2); | |
11546 | gcc_assert (ok); | |
11547 | break; | |
11548 | ||
4e10a5a7 | 11549 | case E_V8QImode: |
e6431744 RH |
11550 | /* Implementable by extract + broadcast. */ |
11551 | if (BYTES_BIG_ENDIAN) | |
11552 | elt = 7 - elt; | |
11553 | elt *= BITS_PER_UNIT; | |
11554 | temp = gen_reg_rtx (DImode); | |
11555 | emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0), | |
96fda42c | 11556 | GEN_INT (8), GEN_INT (elt))); |
e6431744 RH |
11557 | emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp))); |
11558 | break; | |
11559 | ||
4e10a5a7 | 11560 | case E_V4HImode: |
e6431744 RH |
11561 | /* Should have been matched directly by vec_select. */ |
11562 | default: | |
11563 | gcc_unreachable (); | |
11564 | } | |
11565 | ||
11566 | return true; | |
11567 | } | |
11568 | ||
11569 | /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a | |
11570 | two vector permutation into a single vector permutation by using | |
11571 | an interleave operation to merge the vectors. */ | |
11572 | ||
11573 | static bool | |
11574 | expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d) | |
11575 | { | |
11576 | struct expand_vec_perm_d dremap, dfinal; | |
11577 | unsigned char remap[2 * MAX_VECT_LEN]; | |
11578 | unsigned contents, i, nelt, nelt2; | |
11579 | unsigned h0, h1, h2, h3; | |
dd3d2b35 | 11580 | rtx_insn *seq; |
e6431744 RH |
11581 | bool ok; |
11582 | ||
11583 | if (d->one_operand_p) | |
11584 | return false; | |
11585 | ||
11586 | nelt = d->nelt; | |
11587 | nelt2 = nelt / 2; | |
11588 | ||
11589 | /* Examine from whence the elements come. */ | |
11590 | contents = 0; | |
11591 | for (i = 0; i < nelt; ++i) | |
11592 | contents |= 1u << d->perm[i]; | |
11593 | ||
11594 | memset (remap, 0xff, sizeof (remap)); | |
11595 | dremap = *d; | |
11596 | ||
11597 | h0 = (1u << nelt2) - 1; | |
11598 | h1 = h0 << nelt2; | |
11599 | h2 = h0 << nelt; | |
11600 | h3 = h0 << (nelt + nelt2); | |
11601 | ||
11602 | if ((contents & (h0 | h2)) == contents) /* punpck even halves */ | |
11603 | { | |
11604 | for (i = 0; i < nelt; ++i) | |
11605 | { | |
11606 | unsigned which = i / 2 + (i & 1 ? nelt : 0); | |
11607 | remap[which] = i; | |
11608 | dremap.perm[i] = which; | |
11609 | } | |
11610 | } | |
11611 | else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */ | |
11612 | { | |
11613 | for (i = 0; i < nelt; ++i) | |
11614 | { | |
11615 | unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0); | |
11616 | remap[which] = i; | |
11617 | dremap.perm[i] = which; | |
11618 | } | |
11619 | } | |
11620 | else if ((contents & 0x5555) == contents) /* mix even elements */ | |
11621 | { | |
11622 | for (i = 0; i < nelt; ++i) | |
11623 | { | |
11624 | unsigned which = (i & ~1) + (i & 1 ? nelt : 0); | |
11625 | remap[which] = i; | |
11626 | dremap.perm[i] = which; | |
11627 | } | |
11628 | } | |
11629 | else if ((contents & 0xaaaa) == contents) /* mix odd elements */ | |
11630 | { | |
11631 | for (i = 0; i < nelt; ++i) | |
11632 | { | |
11633 | unsigned which = (i | 1) + (i & 1 ? nelt : 0); | |
11634 | remap[which] = i; | |
11635 | dremap.perm[i] = which; | |
11636 | } | |
11637 | } | |
11638 | else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */ | |
11639 | { | |
11640 | unsigned shift = ctz_hwi (contents); | |
11641 | for (i = 0; i < nelt; ++i) | |
11642 | { | |
11643 | unsigned which = (i + shift) & (2 * nelt - 1); | |
11644 | remap[which] = i; | |
11645 | dremap.perm[i] = which; | |
11646 | } | |
11647 | } | |
11648 | else | |
11649 | return false; | |
11650 | ||
11651 | /* Use the remapping array set up above to move the elements from their | |
11652 | swizzled locations into their final destinations. */ | |
11653 | dfinal = *d; | |
11654 | for (i = 0; i < nelt; ++i) | |
11655 | { | |
11656 | unsigned e = remap[d->perm[i]]; | |
11657 | gcc_assert (e < nelt); | |
11658 | dfinal.perm[i] = e; | |
11659 | } | |
b4b78e2d EB |
11660 | if (d->testing_p) |
11661 | dfinal.op0 = gen_raw_REG (dfinal.vmode, LAST_VIRTUAL_REGISTER + 1); | |
11662 | else | |
11663 | dfinal.op0 = gen_reg_rtx (dfinal.vmode); | |
e6431744 RH |
11664 | dfinal.op1 = dfinal.op0; |
11665 | dfinal.one_operand_p = true; | |
11666 | dremap.target = dfinal.op0; | |
11667 | ||
11668 | /* Test if the final remap can be done with a single insn. For V4HImode | |
11669 | this *will* succeed. For V8QImode or V2SImode it may not. */ | |
11670 | start_sequence (); | |
11671 | ok = expand_vec_perm_1 (&dfinal); | |
11672 | seq = get_insns (); | |
11673 | end_sequence (); | |
11674 | if (!ok) | |
11675 | return false; | |
11676 | if (d->testing_p) | |
11677 | return true; | |
11678 | ||
11679 | ok = expand_vec_perm_1 (&dremap); | |
11680 | gcc_assert (ok); | |
11681 | ||
11682 | emit_insn (seq); | |
11683 | return true; | |
11684 | } | |
11685 | ||
11686 | /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode | |
11687 | constant permutation via two mux2 and a merge. */ | |
11688 | ||
11689 | static bool | |
11690 | expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d) | |
11691 | { | |
11692 | unsigned char perm2[4]; | |
11693 | rtx rmask[4]; | |
11694 | unsigned i; | |
11695 | rtx t0, t1, mask, x; | |
11696 | bool ok; | |
11697 | ||
11698 | if (d->vmode != V4HImode || d->one_operand_p) | |
11699 | return false; | |
11700 | if (d->testing_p) | |
11701 | return true; | |
11702 | ||
11703 | for (i = 0; i < 4; ++i) | |
11704 | { | |
11705 | perm2[i] = d->perm[i] & 3; | |
11706 | rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx); | |
11707 | } | |
11708 | mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask)); | |
11709 | mask = force_reg (V4HImode, mask); | |
11710 | ||
11711 | t0 = gen_reg_rtx (V4HImode); | |
11712 | t1 = gen_reg_rtx (V4HImode); | |
11713 | ||
11714 | ok = expand_vselect (t0, d->op0, perm2, 4); | |
11715 | gcc_assert (ok); | |
11716 | ok = expand_vselect (t1, d->op1, perm2, 4); | |
11717 | gcc_assert (ok); | |
11718 | ||
11719 | x = gen_rtx_AND (V4HImode, mask, t0); | |
f7df4a84 | 11720 | emit_insn (gen_rtx_SET (t0, x)); |
e6431744 RH |
11721 | |
11722 | x = gen_rtx_NOT (V4HImode, mask); | |
11723 | x = gen_rtx_AND (V4HImode, x, t1); | |
f7df4a84 | 11724 | emit_insn (gen_rtx_SET (t1, x)); |
e6431744 RH |
11725 | |
11726 | x = gen_rtx_IOR (V4HImode, t0, t1); | |
f7df4a84 | 11727 | emit_insn (gen_rtx_SET (d->target, x)); |
e6431744 RH |
11728 | |
11729 | return true; | |
11730 | } | |
11731 | ||
11732 | /* The guts of ia64_expand_vec_perm_const, also used by the ok hook. | |
11733 | With all of the interface bits taken care of, perform the expansion | |
11734 | in D and return true on success. */ | |
11735 | ||
11736 | static bool | |
11737 | ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) | |
11738 | { | |
11739 | if (expand_vec_perm_1 (d)) | |
11740 | return true; | |
11741 | if (expand_vec_perm_broadcast (d)) | |
11742 | return true; | |
11743 | if (expand_vec_perm_interleave_2 (d)) | |
11744 | return true; | |
11745 | if (expand_vec_perm_v4hi_5 (d)) | |
11746 | return true; | |
11747 | return false; | |
11748 | } | |
11749 | ||
f151c9e1 RS |
11750 | /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ |
11751 | ||
11752 | static bool | |
11753 | ia64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, | |
11754 | rtx op1, const vec_perm_indices &sel) | |
e6431744 RH |
11755 | { |
11756 | struct expand_vec_perm_d d; | |
11757 | unsigned char perm[MAX_VECT_LEN]; | |
f151c9e1 | 11758 | unsigned int i, nelt, which; |
e6431744 | 11759 | |
f151c9e1 RS |
11760 | d.target = target; |
11761 | d.op0 = op0; | |
11762 | d.op1 = op1; | |
e6431744 | 11763 | |
f151c9e1 | 11764 | d.vmode = vmode; |
e6431744 RH |
11765 | gcc_assert (VECTOR_MODE_P (d.vmode)); |
11766 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
f151c9e1 | 11767 | d.testing_p = !target; |
e6431744 | 11768 | |
f151c9e1 | 11769 | gcc_assert (sel.length () == nelt); |
e6431744 RH |
11770 | gcc_checking_assert (sizeof (d.perm) == sizeof (perm)); |
11771 | ||
11772 | for (i = which = 0; i < nelt; ++i) | |
11773 | { | |
f151c9e1 | 11774 | unsigned int ei = sel[i] & (2 * nelt - 1); |
e6431744 RH |
11775 | |
11776 | which |= (ei < nelt ? 1 : 2); | |
11777 | d.perm[i] = ei; | |
11778 | perm[i] = ei; | |
11779 | } | |
11780 | ||
11781 | switch (which) | |
11782 | { | |
11783 | default: | |
11784 | gcc_unreachable(); | |
11785 | ||
11786 | case 3: | |
f151c9e1 | 11787 | if (d.testing_p || !rtx_equal_p (d.op0, d.op1)) |
e6431744 RH |
11788 | { |
11789 | d.one_operand_p = false; | |
11790 | break; | |
11791 | } | |
11792 | ||
11793 | /* The elements of PERM do not suggest that only the first operand | |
11794 | is used, but both operands are identical. Allow easier matching | |
11795 | of the permutation by folding the permutation into the single | |
11796 | input vector. */ | |
11797 | for (i = 0; i < nelt; ++i) | |
11798 | if (d.perm[i] >= nelt) | |
11799 | d.perm[i] -= nelt; | |
11800 | /* FALLTHRU */ | |
11801 | ||
11802 | case 1: | |
11803 | d.op1 = d.op0; | |
11804 | d.one_operand_p = true; | |
11805 | break; | |
11806 | ||
11807 | case 2: | |
11808 | for (i = 0; i < nelt; ++i) | |
11809 | d.perm[i] -= nelt; | |
11810 | d.op0 = d.op1; | |
11811 | d.one_operand_p = true; | |
11812 | break; | |
11813 | } | |
11814 | ||
f151c9e1 RS |
11815 | if (d.testing_p) |
11816 | { | |
11817 | /* We have to go through the motions and see if we can | |
11818 | figure out how to generate the requested permutation. */ | |
11819 | d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); | |
11820 | d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); | |
11821 | if (!d.one_operand_p) | |
11822 | d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); | |
11823 | ||
11824 | start_sequence (); | |
11825 | bool ret = ia64_expand_vec_perm_const_1 (&d); | |
11826 | end_sequence (); | |
11827 | ||
11828 | return ret; | |
11829 | } | |
11830 | ||
e6431744 RH |
11831 | if (ia64_expand_vec_perm_const_1 (&d)) |
11832 | return true; | |
11833 | ||
11834 | /* If the mask says both arguments are needed, but they are the same, | |
11835 | the above tried to expand with one_operand_p true. If that didn't | |
11836 | work, retry with one_operand_p false, as that's what we used in _ok. */ | |
11837 | if (which == 3 && d.one_operand_p) | |
11838 | { | |
11839 | memcpy (d.perm, perm, sizeof (perm)); | |
11840 | d.one_operand_p = false; | |
11841 | return ia64_expand_vec_perm_const_1 (&d); | |
11842 | } | |
11843 | ||
11844 | return false; | |
11845 | } | |
11846 | ||
e6431744 RH |
11847 | void |
11848 | ia64_expand_vec_setv2sf (rtx operands[3]) | |
11849 | { | |
11850 | struct expand_vec_perm_d d; | |
11851 | unsigned int which; | |
11852 | bool ok; | |
11853 | ||
11854 | d.target = operands[0]; | |
11855 | d.op0 = operands[0]; | |
11856 | d.op1 = gen_reg_rtx (V2SFmode); | |
11857 | d.vmode = V2SFmode; | |
11858 | d.nelt = 2; | |
11859 | d.one_operand_p = false; | |
11860 | d.testing_p = false; | |
11861 | ||
11862 | which = INTVAL (operands[2]); | |
11863 | gcc_assert (which <= 1); | |
11864 | d.perm[0] = 1 - which; | |
11865 | d.perm[1] = which + 2; | |
11866 | ||
11867 | emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode))); | |
11868 | ||
11869 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11870 | gcc_assert (ok); | |
11871 | } | |
11872 | ||
11873 | void | |
11874 | ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd) | |
11875 | { | |
11876 | struct expand_vec_perm_d d; | |
ef4bddc2 | 11877 | machine_mode vmode = GET_MODE (target); |
e6431744 RH |
11878 | unsigned int i, nelt = GET_MODE_NUNITS (vmode); |
11879 | bool ok; | |
11880 | ||
11881 | d.target = target; | |
11882 | d.op0 = op0; | |
11883 | d.op1 = op1; | |
11884 | d.vmode = vmode; | |
11885 | d.nelt = nelt; | |
11886 | d.one_operand_p = false; | |
11887 | d.testing_p = false; | |
11888 | ||
11889 | for (i = 0; i < nelt; ++i) | |
11890 | d.perm[i] = i * 2 + odd; | |
11891 | ||
11892 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11893 | gcc_assert (ok); | |
11894 | } | |
f16d3f39 | 11895 | |
0d803030 RS |
11896 | /* Implement TARGET_CAN_CHANGE_MODE_CLASS. |
11897 | ||
11898 | In BR regs, we can't change the DImode at all. | |
11899 | In FP regs, we can't change FP values to integer values and vice versa, | |
11900 | but we can change e.g. DImode to SImode, and V2SFmode into DImode. */ | |
11901 | ||
11902 | static bool | |
11903 | ia64_can_change_mode_class (machine_mode from, machine_mode to, | |
11904 | reg_class_t rclass) | |
11905 | { | |
11906 | if (reg_classes_intersect_p (rclass, BR_REGS)) | |
11907 | return from == to; | |
11908 | if (SCALAR_FLOAT_MODE_P (from) != SCALAR_FLOAT_MODE_P (to)) | |
11909 | return !reg_classes_intersect_p (rclass, FR_REGS); | |
11910 | return true; | |
11911 | } | |
11912 | ||
e2500fed | 11913 | #include "gt-ia64.h" |