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385c9217 SC |
1 | /* Definitions of target machine for GNU compiler. |
2 | Motorola 68HC11 and 68HC12. | |
2f83c7d6 | 3 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007 |
577e5d76 | 4 | Free Software Foundation, Inc. |
4caff360 | 5 | Contributed by Stephane Carrez (stcarrez@nerim.fr) |
385c9217 | 6 | |
7ec022b2 | 7 | This file is part of GCC. |
385c9217 | 8 | |
7ec022b2 | 9 | GCC is free software; you can redistribute it and/or modify |
385c9217 | 10 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
385c9217 SC |
12 | any later version. |
13 | ||
7ec022b2 | 14 | GCC is distributed in the hope that it will be useful, |
385c9217 SC |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. | |
385c9217 SC |
22 | |
23 | Note: | |
24 | A first 68HC11 port was made by Otto Lind (otto@coactive.com) | |
25 | on gcc 2.6.3. I have used it as a starting point for this port. | |
26 | However, this new port is a complete re-write. Its internal | |
27 | design is completely different. The generated code is not | |
28 | compatible with the gcc 2.6.3 port. | |
29 | ||
30 | The gcc 2.6.3 port is available at: | |
31 | ||
32 | ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz | |
33 | ||
34 | */ | |
35 | ||
385c9217 SC |
36 | /***************************************************************************** |
37 | ** | |
38 | ** Controlling the Compilation Driver, `gcc' | |
39 | ** | |
40 | *****************************************************************************/ | |
41 | ||
42 | #undef ENDFILE_SPEC | |
43 | ||
44 | /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */ | |
45 | #ifndef ASM_SPEC | |
f077f169 SC |
46 | #define ASM_SPEC \ |
47 | "%{m68hc12:-m68hc12}" \ | |
48 | "%{m68hcs12:-m68hcs12}" \ | |
49 | "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \ | |
50 | "%{mshort:-mshort}%{!mshort:-mlong} " \ | |
51 | "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}" | |
385c9217 SC |
52 | #endif |
53 | ||
54 | /* We need to tell the linker the target elf format. Just pass an | |
5bdc5878 | 55 | emulation option. This can be overridden by -Wl option of gcc. */ |
385c9217 | 56 | #ifndef LINK_SPEC |
f077f169 SC |
57 | #define LINK_SPEC \ |
58 | "%{m68hc12:-m m68hc12elf}" \ | |
59 | "%{m68hcs12:-m m68hc12elf}" \ | |
60 | "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \ | |
61 | "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}" | |
385c9217 SC |
62 | #endif |
63 | ||
64 | #ifndef LIB_SPEC | |
65 | #define LIB_SPEC "" | |
66 | #endif | |
67 | ||
68 | #ifndef CC1_SPEC | |
69 | #define CC1_SPEC "" | |
70 | #endif | |
71 | ||
72 | #ifndef CPP_SPEC | |
73 | #define CPP_SPEC \ | |
676997cf RH |
74 | "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\ |
75 | %{!mshort:-D__INT__=32}\ | |
385c9217 | 76 | %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\ |
f077f169 SC |
77 | %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\ |
78 | %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\ | |
058edcdb SC |
79 | %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\ |
80 | %{mlong-calls:-D__USE_RTC__}" | |
385c9217 SC |
81 | #endif |
82 | ||
83 | #undef STARTFILE_SPEC | |
84 | #define STARTFILE_SPEC "crt1%O%s" | |
85 | ||
86 | /* Names to predefine in the preprocessor for this target machine. */ | |
cc956ba2 NB |
87 | #define TARGET_CPU_CPP_BUILTINS() \ |
88 | do \ | |
89 | { \ | |
90 | builtin_define_std ("mc68hc1x"); \ | |
91 | } \ | |
92 | while (0) | |
385c9217 | 93 | |
0b29309a | 94 | /* As an embedded target, we have no libc. */ |
ff24b820 SC |
95 | #ifndef inhibit_libc |
96 | # define inhibit_libc | |
97 | #endif | |
385c9217 SC |
98 | |
99 | /* Forward type declaration for prototypes definitions. | |
9caea35c | 100 | rtx_ptr is equivalent to rtx. Can't use the same name. */ |
385c9217 SC |
101 | struct rtx_def; |
102 | typedef struct rtx_def *rtx_ptr; | |
103 | ||
104 | union tree_node; | |
105 | typedef union tree_node *tree_ptr; | |
106 | ||
107 | /* We can't declare enum machine_mode forward nor include 'machmode.h' here. | |
108 | Prototypes defined here will use an int instead. It's better than no | |
9caea35c | 109 | prototype at all. */ |
385c9217 | 110 | typedef int enum_machine_mode; |
385c9217 SC |
111 | |
112 | /***************************************************************************** | |
113 | ** | |
114 | ** Run-time Target Specification | |
115 | ** | |
116 | *****************************************************************************/ | |
117 | ||
118 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
119 | ||
385c9217 SC |
120 | extern short *reg_renumber; /* def in local_alloc.c */ |
121 | ||
385c9217 | 122 | #define TARGET_OP_TIME (optimize && optimize_size == 0) |
932657df | 123 | #define TARGET_RELAX (TARGET_NO_DIRECT_MODE) |
385c9217 SC |
124 | |
125 | /* Default target_flags if no switches specified. */ | |
126 | #ifndef TARGET_DEFAULT | |
43849cfa | 127 | # define TARGET_DEFAULT 0 |
385c9217 SC |
128 | #endif |
129 | ||
130 | /* Define this macro as a C expression for the initializer of an | |
131 | array of string to tell the driver program which options are | |
132 | defaults for this target and thus do not need to be handled | |
133 | specially when using `MULTILIB_OPTIONS'. */ | |
134 | #ifndef MULTILIB_DEFAULTS | |
135 | # if TARGET_DEFAULT & MASK_M6811 | |
136 | # define MULTILIB_DEFAULTS { "m68hc11" } | |
137 | # else | |
138 | # define MULTILIB_DEFAULTS { "m68hc12" } | |
139 | # endif | |
140 | #endif | |
141 | ||
385c9217 | 142 | /* Print subsidiary information on the compiler version in use. */ |
f077f169 | 143 | #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)") |
385c9217 SC |
144 | |
145 | /* Sometimes certain combinations of command options do not make | |
146 | sense on a particular target machine. You can define a macro | |
147 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
148 | defined, is executed once just after all the command options have | |
149 | been parsed. | |
150 | ||
151 | Don't use this macro to turn on various extra optimizations for | |
152 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
153 | ||
9e4bd0ea | 154 | #define OVERRIDE_OPTIONS m68hc11_override_options () |
01beec65 SC |
155 | |
156 | \f | |
157 | /* Define cost parameters for a given processor variant. */ | |
158 | struct processor_costs { | |
8b60264b KG |
159 | const int add; /* cost of an add instruction */ |
160 | const int logical; /* cost of a logical instruction */ | |
161 | const int shift_var; | |
162 | const int shiftQI_const[8]; | |
163 | const int shiftHI_const[16]; | |
164 | const int multQI; | |
165 | const int multHI; | |
166 | const int multSI; | |
167 | const int divQI; | |
168 | const int divHI; | |
169 | const int divSI; | |
01beec65 SC |
170 | }; |
171 | ||
172 | /* Costs for the current processor. */ | |
8b60264b | 173 | extern const struct processor_costs *m68hc11_cost; |
385c9217 SC |
174 | \f |
175 | ||
176 | /* target machine storage layout */ | |
177 | ||
178 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
179 | #define BYTES_BIG_ENDIAN 1 | |
180 | ||
181 | /* Define this if most significant bit is lowest numbered | |
9caea35c | 182 | in instructions that operate on numbered bit-fields. */ |
385c9217 SC |
183 | #define BITS_BIG_ENDIAN 0 |
184 | ||
185 | /* Define this if most significant word of a multiword number is numbered. */ | |
186 | #define WORDS_BIG_ENDIAN 1 | |
187 | ||
385c9217 | 188 | /* Width of a word, in units (bytes). */ |
e81dd381 | 189 | #define UNITS_PER_WORD 2 |
385c9217 | 190 | |
385c9217 SC |
191 | /* Definition of size_t. This is really an unsigned short as the |
192 | 68hc11 only handles a 64K address space. */ | |
193 | #define SIZE_TYPE "short unsigned int" | |
194 | ||
195 | /* A C expression for a string describing the name of the data type | |
196 | to use for the result of subtracting two pointers. The typedef | |
197 | name `ptrdiff_t' is defined using the contents of the string. | |
198 | The 68hc11 only has a 64K address space. */ | |
199 | #define PTRDIFF_TYPE "short int" | |
200 | ||
201 | /* Allocation boundary (bits) for storing pointers in memory. */ | |
202 | #define POINTER_BOUNDARY 8 | |
203 | ||
204 | /* Normal alignment required for function parameters on the stack, in bits. | |
205 | This can't be less than BITS_PER_WORD */ | |
206 | #define PARM_BOUNDARY (BITS_PER_WORD) | |
207 | ||
208 | /* Boundary (bits) on which stack pointer should be aligned. */ | |
209 | #define STACK_BOUNDARY 8 | |
210 | ||
211 | /* Allocation boundary (bits) for the code of a function. */ | |
212 | #define FUNCTION_BOUNDARY 8 | |
213 | ||
385c9217 SC |
214 | #define BIGGEST_ALIGNMENT 8 |
215 | ||
216 | /* Alignment of field after `int : 0' in a structure. */ | |
217 | #define EMPTY_FIELD_BOUNDARY 8 | |
218 | ||
219 | /* Every structure's size must be a multiple of this. */ | |
220 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
221 | ||
222 | /* Define this if instructions will fail to work if given data not | |
223 | on the nominal alignment. If instructions will merely go slower | |
224 | in that case, do not define this macro. */ | |
225 | #define STRICT_ALIGNMENT 0 | |
226 | ||
227 | /* An integer expression for the size in bits of the largest integer | |
228 | machine mode that should actually be used. All integer machine modes of | |
229 | this size or smaller can be used for structures and unions with the | |
230 | appropriate sizes. */ | |
231 | #define MAX_FIXED_MODE_SIZE 64 | |
385c9217 SC |
232 | \f |
233 | /* target machine storage layout */ | |
234 | ||
235 | /* Size (bits) of the type "int" on target machine | |
236 | (If undefined, default is BITS_PER_WORD). */ | |
237 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) | |
238 | ||
239 | /* Size (bits) of the type "short" on target machine */ | |
240 | #define SHORT_TYPE_SIZE 16 | |
241 | ||
242 | /* Size (bits) of the type "long" on target machine */ | |
243 | #define LONG_TYPE_SIZE 32 | |
244 | ||
245 | /* Size (bits) of the type "long long" on target machine */ | |
246 | #define LONG_LONG_TYPE_SIZE 64 | |
247 | ||
385c9217 SC |
248 | /* A C expression for the size in bits of the type `float' on the |
249 | target machine. If you don't define this, the default is one word. | |
250 | Don't use default: a word is only 16. */ | |
251 | #define FLOAT_TYPE_SIZE 32 | |
252 | ||
253 | /* A C expression for the size in bits of the type double on the target | |
254 | machine. If you don't define this, the default is two words. | |
255 | Be IEEE compliant. */ | |
256 | #define DOUBLE_TYPE_SIZE 64 | |
257 | ||
258 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
259 | ||
260 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
261 | #define DEFAULT_SIGNED_CHAR 0 | |
262 | ||
263 | /* Define these to avoid dependence on meaning of `int'. | |
264 | Note that WCHAR_TYPE_SIZE is used in cexp.y, | |
265 | where TARGET_SHORT is not available. */ | |
266 | #define WCHAR_TYPE "short int" | |
267 | #define WCHAR_TYPE_SIZE 16 | |
385c9217 SC |
268 | \f |
269 | ||
270 | /* Standard register usage. */ | |
271 | ||
272 | #define HARD_REG_SIZE (UNITS_PER_WORD) | |
273 | ||
274 | /* Assign names to real MC68HC11 registers. | |
275 | A and B registers are not really used (A+B = D) | |
276 | X register is first so that GCC allocates X+D for 32-bit integers and | |
277 | the lowpart of that integer will be D. Having the lower part in D is | |
278 | better for 32<->16bit conversions and for many arithmetic operations. */ | |
279 | #define HARD_X_REGNUM 0 | |
280 | #define HARD_D_REGNUM 1 | |
281 | #define HARD_Y_REGNUM 2 | |
282 | #define HARD_SP_REGNUM 3 | |
283 | #define HARD_PC_REGNUM 4 | |
284 | #define HARD_A_REGNUM 5 | |
285 | #define HARD_B_REGNUM 6 | |
286 | #define HARD_CCR_REGNUM 7 | |
287 | ||
288 | /* The Z register does not really exist in the 68HC11. This a fake register | |
289 | for GCC. It is treated exactly as an index register (X or Y). It is only | |
290 | in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this | |
5b482117 | 291 | register helps the reload pass of GCC. Otherwise, the reload often dies |
385c9217 SC |
292 | with register spill failures. |
293 | ||
294 | The Z register is replaced by either X or Y during the machine specific | |
295 | reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register | |
296 | when this is necessary. | |
297 | ||
298 | It's possible to tell GCC not to use this register with -ffixed-z. */ | |
299 | #define HARD_Z_REGNUM 8 | |
300 | ||
301 | /* The frame pointer is a soft-register. It's treated as such by GCC: | |
302 | it is not and must not be part of the BASE_REG_CLASS. */ | |
303 | #define DEFAULT_HARD_FP_REGNUM (9) | |
304 | #define HARD_FP_REGNUM (9) | |
305 | #define HARD_AP_REGNUM (HARD_FP_REGNUM) | |
306 | ||
307 | /* Temporary soft-register used in some cases when an operand came | |
308 | up into a bad register class (D, X, Y, SP) and gcc failed to | |
309 | recognize this. This register is never allocated by GCC. */ | |
310 | #define SOFT_TMP_REGNUM 10 | |
311 | ||
312 | /* The soft-register which is used to save the Z register | |
313 | (see Z register replacement notes in m68hc11.c). */ | |
314 | #define SOFT_Z_REGNUM 11 | |
315 | ||
9caea35c | 316 | /* The soft-register which is used to save either X or Y. */ |
385c9217 SC |
317 | #define SOFT_SAVED_XY_REGNUM 12 |
318 | ||
319 | /* A fake clobber register for 68HC12 patterns. */ | |
320 | #define FAKE_CLOBBER_REGNUM (13) | |
321 | ||
322 | /* Define 32 soft-registers of 16-bit each. By default, | |
323 | only 12 of them are enabled and can be used by GCC. The | |
324 | -msoft-reg-count=<n> option allows to control the number of valid | |
325 | soft-registers. GCC can put 32-bit values in them | |
326 | by allocating consecutive registers. The first 3 soft-registers | |
327 | are never allocated by GCC. They are used in case the insn template needs | |
328 | a temporary register, or for the Z register replacement. */ | |
329 | ||
330 | #define MAX_SOFT_REG_COUNT (32) | |
331 | #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \ | |
332 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
333 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
334 | 1, 1, 1, 1, 1, 1, 1, 1 | |
335 | #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \ | |
336 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
337 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
338 | 1, 1, 1, 1, 1, 1, 1, 1 | |
339 | #define SOFT_REG_ORDER \ | |
340 | SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\ | |
341 | SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\ | |
342 | SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\ | |
343 | SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\ | |
344 | SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\ | |
345 | SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\ | |
346 | SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\ | |
347 | SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31 | |
348 | ||
349 | #define SOFT_REG_NAMES \ | |
350 | "*_.d1", "*_.d2", "*_.d3", "*_.d4", \ | |
351 | "*_.d5", "*_.d6", "*_.d7", "*_.d8", \ | |
352 | "*_.d9", "*_.d10", "*_.d11", "*_.d12", \ | |
353 | "*_.d13", "*_.d14", "*_.d15", "*_.d16", \ | |
354 | "*_.d17", "*_.d18", "*_.d19", "*_.d20", \ | |
355 | "*_.d21", "*_.d22", "*_.d23", "*_.d24", \ | |
356 | "*_.d25", "*_.d26", "*_.d27", "*_.d28", \ | |
357 | "*_.d29", "*_.d30", "*_.d31", "*_.d32" | |
358 | ||
9caea35c | 359 | /* First available soft-register for GCC. */ |
385c9217 SC |
360 | #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2) |
361 | ||
9caea35c | 362 | /* Last available soft-register for GCC. */ |
385c9217 SC |
363 | #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT) |
364 | #define SOFT_FP_REGNUM (SOFT_REG_LAST) | |
365 | #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1) | |
366 | ||
367 | /* Number of actual hardware registers. The hardware registers are assigned | |
368 | numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. | |
369 | All registers that the compiler knows about must be given numbers, even | |
9caea35c | 370 | those that are not normally considered general registers. */ |
385c9217 SC |
371 | #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2) |
372 | ||
373 | /* 1 for registers that have pervasive standard uses and are not available | |
9caea35c | 374 | for the register allocator. */ |
385c9217 SC |
375 | #define FIXED_REGISTERS \ |
376 | {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1} | |
377 | /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */ | |
378 | ||
379 | /* 1 for registers not available across function calls. For our pseudo | |
380 | registers, all are available. */ | |
381 | #define CALL_USED_REGISTERS \ | |
382 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1} | |
383 | /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */ | |
384 | ||
385 | ||
386 | /* Define this macro to change register usage conditional on target flags. | |
387 | ||
388 | The soft-registers are disabled or enabled according to the | |
9caea35c | 389 | -msoft-reg-count=<n> option. */ |
385c9217 SC |
390 | |
391 | ||
392 | #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ()) | |
393 | ||
394 | /* List the order in which to allocate registers. Each register must be | |
395 | listed once, even those in FIXED_REGISTERS. */ | |
396 | #define REG_ALLOC_ORDER \ | |
397 | { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \ | |
398 | SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \ | |
399 | HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \ | |
400 | HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \ | |
401 | SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM } | |
402 | ||
403 | /* A C expression for the number of consecutive hard registers, | |
404 | starting at register number REGNO, required to hold a value of | |
405 | mode MODE. */ | |
406 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
407 | ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \ | |
408 | ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE)) | |
409 | ||
410 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
85f65093 KH |
411 | - 8-bit values are stored anywhere (except the SP register). |
412 | - 16-bit values can be stored in any register whose mode is 16 | |
413 | - 32-bit values can be stored in D, X registers or in a soft register | |
385c9217 SC |
414 | (except the last one because we need 2 soft registers) |
415 | - Values whose size is > 32 bit are not stored in real hard | |
416 | registers. They may be stored in soft registers if there are | |
417 | enough of them. */ | |
418 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
419 | hard_regno_mode_ok (REGNO,MODE) | |
420 | ||
421 | /* Value is 1 if it is a good idea to tie two pseudo registers when one has | |
422 | mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce | |
423 | different values for MODE1 and MODE2, for any hard reg, then this must be | |
6272bc68 SC |
424 | 0 for correct output. |
425 | ||
426 | All modes are tieable except QImode. */ | |
385c9217 SC |
427 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
428 | (((MODE1) == (MODE2)) \ | |
6272bc68 | 429 | || ((MODE1) != QImode && (MODE2) != QImode)) |
385c9217 SC |
430 | \f |
431 | ||
432 | /* Define the classes of registers for register constraints in the | |
433 | machine description. Also define ranges of constants. | |
434 | ||
435 | One of the classes must always be named ALL_REGS and include all hard regs. | |
436 | If there is more than one class, another class must be named NO_REGS | |
437 | and contain no registers. | |
438 | ||
439 | The name GENERAL_REGS must be the name of a class (or an alias for | |
440 | another name such as ALL_REGS). This is the class of registers | |
441 | that is allowed by "g" or "r" in a register constraint. | |
442 | Also, registers outside this class are allocated only when | |
443 | instructions express preferences for them. | |
444 | ||
445 | The classes must be numbered in nondecreasing order; that is, | |
446 | a larger-numbered class must never be contained completely | |
447 | in a smaller-numbered class. | |
448 | ||
449 | For any two classes, it is very desirable that there be another | |
450 | class that represents their union. */ | |
451 | ||
0fa2e4df | 452 | /* The M68hc11 has so few registers that it's not possible for GCC to |
385c9217 SC |
453 | do any register allocation without breaking. We extend the processor |
454 | registers by having soft registers. These registers are treated as | |
455 | hard registers by GCC but they are located in memory and accessed by page0 | |
456 | accesses (IND mode). */ | |
457 | enum reg_class | |
458 | { | |
459 | NO_REGS, | |
460 | D_REGS, /* 16-bit data register */ | |
461 | X_REGS, /* 16-bit X register */ | |
462 | Y_REGS, /* 16-bit Y register */ | |
85f65093 | 463 | SP_REGS, /* 16-bit stack pointer */ |
9caea35c KH |
464 | DA_REGS, /* 8-bit A reg. */ |
465 | DB_REGS, /* 8-bit B reg. */ | |
385c9217 | 466 | Z_REGS, /* 16-bit fake Z register */ |
9caea35c | 467 | D8_REGS, /* 8-bit A or B reg. */ |
385c9217 SC |
468 | Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */ |
469 | D_OR_X_REGS, /* D or X register */ | |
470 | D_OR_Y_REGS, /* D or Y register */ | |
471 | D_OR_SP_REGS, /* D or SP register */ | |
472 | X_OR_Y_REGS, /* IX or Y register */ | |
473 | A_REGS, /* 16-bit address register (X, Y, Z) */ | |
474 | X_OR_SP_REGS, /* X or SP register */ | |
475 | Y_OR_SP_REGS, /* Y or SP register */ | |
476 | X_OR_Y_OR_D_REGS, /* X, Y or D */ | |
477 | A_OR_D_REGS, /* X, Y, Z or D */ | |
478 | A_OR_SP_REGS, /* X, Y, Z or SP */ | |
479 | H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */ | |
480 | S_REGS, /* 16-bit soft register */ | |
481 | D_OR_S_REGS, /* 16-bit soft register or D register */ | |
482 | X_OR_S_REGS, /* 16-bit soft register or X register */ | |
483 | Y_OR_S_REGS, /* 16-bit soft register or Y register */ | |
96cd9069 | 484 | Z_OR_S_REGS, /* 16-bit soft register or Z register */ |
385c9217 SC |
485 | SP_OR_S_REGS, /* 16-bit soft register or SP register */ |
486 | D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */ | |
487 | D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */ | |
488 | D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */ | |
489 | A_OR_S_REGS, /* 16-bit soft register or X, Y registers */ | |
490 | D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */ | |
85f65093 | 491 | TMP_REGS, /* 16-bit fake scratch register */ |
385c9217 SC |
492 | D_OR_A_OR_TMP_REGS, /* General scratch register */ |
493 | G_REGS, /* 16-bit general register | |
494 | (H_REGS + soft registers) */ | |
495 | ALL_REGS, | |
496 | LIM_REG_CLASSES | |
497 | }; | |
498 | ||
9caea35c | 499 | /* alias GENERAL_REGS to G_REGS. */ |
385c9217 SC |
500 | #define GENERAL_REGS G_REGS |
501 | ||
502 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
503 | ||
9caea35c | 504 | /* Give names of register classes as strings for dump file. */ |
385c9217 SC |
505 | #define REG_CLASS_NAMES \ |
506 | { "NO_REGS", \ | |
507 | "D_REGS", \ | |
508 | "X_REGS", \ | |
509 | "Y_REGS", \ | |
510 | "SP_REGS", \ | |
511 | "DA_REGS", \ | |
512 | "DB_REGS", \ | |
513 | "D8_REGS", \ | |
514 | "Z_REGS", \ | |
515 | "Q_REGS", \ | |
516 | "D_OR_X_REGS", \ | |
517 | "D_OR_Y_REGS", \ | |
518 | "D_OR_SP_REGS", \ | |
519 | "X_OR_Y_REGS", \ | |
520 | "A_REGS", \ | |
521 | "X_OR_SP_REGS", \ | |
522 | "Y_OR_SP_REGS", \ | |
523 | "X_OR_Y_OR_D_REGS", \ | |
524 | "A_OR_D_REGS", \ | |
525 | "A_OR_SP_REGS", \ | |
526 | "H_REGS", \ | |
527 | "S_REGS", \ | |
528 | "D_OR_S_REGS", \ | |
529 | "X_OR_S_REGS", \ | |
530 | "Y_OR_S_REGS", \ | |
96cd9069 | 531 | "Z_OR_S_REGS", \ |
385c9217 SC |
532 | "SP_OR_S_REGS", \ |
533 | "D_OR_X_OR_S_REGS", \ | |
534 | "D_OR_Y_OR_S_REGS", \ | |
535 | "D_OR_SP_OR_S_REGS", \ | |
536 | "A_OR_S_REGS", \ | |
537 | "D_OR_A_OR_S_REGS", \ | |
538 | "TMP_REGS", \ | |
539 | "D_OR_A_OR_TMP_REGS", \ | |
540 | "G_REGS", \ | |
541 | "ALL_REGS" } | |
542 | ||
543 | /* An initializer containing the contents of the register classes, | |
544 | as integers which are bit masks. The Nth integer specifies the | |
545 | contents of class N. The way the integer MASK is interpreted is | |
546 | that register R is in the class if `MASK & (1 << R)' is 1. */ | |
547 | ||
548 | /*-------------------------------------------------------------- | |
549 | X 0x00000001 | |
550 | D 0x00000002 | |
551 | Y 0x00000004 | |
552 | SP 0x00000008 | |
553 | PC 0x00000010 | |
554 | A 0x00000020 | |
555 | B 0x00000040 | |
556 | CCR 0x00000080 | |
557 | Z 0x00000100 | |
558 | FRAME 0x00000200 | |
559 | ZTMP 0x00000400 | |
560 | ZREG 0x00000800 | |
561 | XYREG 0x00001000 | |
562 | FAKE 0x00002000 | |
563 | Di 0xFFFFc000, 0x03FFF | |
564 | SFRAME 0x00000000, 0x04000 | |
565 | AP 0x00000000, 0x08000 | |
566 | ||
567 | D_OR_X_REGS represents D+X. It is used for 32-bits numbers. | |
568 | A_REGS represents a valid base register for indexing. It represents | |
569 | X,Y and the Z register. | |
570 | S_REGS represents the soft-registers. This includes the hard frame | |
571 | and soft frame registers. | |
572 | --------------------------------------------------------------*/ | |
573 | ||
574 | #define REG_CLASS_CONTENTS \ | |
575 | /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \ | |
576 | /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \ | |
577 | /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \ | |
578 | /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \ | |
579 | /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \ | |
580 | /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \ | |
581 | /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \ | |
385c9217 | 582 | /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \ |
6272bc68 | 583 | /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \ |
385c9217 SC |
584 | /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \ |
585 | /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \ | |
586 | /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \ | |
587 | /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \ | |
588 | /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \ | |
589 | /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \ | |
590 | /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \ | |
591 | /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \ | |
592 | /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \ | |
593 | /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \ | |
594 | /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \ | |
595 | /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \ | |
596 | /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \ | |
597 | /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \ | |
598 | /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \ | |
599 | /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \ | |
96cd9069 | 600 | /* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \ |
385c9217 SC |
601 | /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \ |
602 | /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \ | |
603 | /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \ | |
604 | /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \ | |
605 | /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \ | |
606 | /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \ | |
607 | /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \ | |
608 | /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \ | |
609 | /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \ | |
610 | /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }} | |
611 | ||
612 | ||
613 | /* set up a C expression whose value is a register class containing hard | |
614 | register REGNO */ | |
615 | #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \ | |
616 | || (REGNO) == HARD_B_REGNUM) | |
617 | #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X))) | |
618 | ||
619 | #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM) | |
620 | #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) | |
621 | ||
622 | #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM) | |
623 | #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X))) | |
624 | #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM) | |
625 | #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X))) | |
626 | ||
627 | #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM) | |
628 | #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X))) | |
629 | ||
630 | #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM) | |
631 | #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X))) | |
632 | ||
7bdf2c65 SC |
633 | #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) |
634 | #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) | |
635 | ||
385c9217 SC |
636 | #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM) |
637 | #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X))) | |
638 | ||
639 | /* Address register. */ | |
640 | #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \ | |
641 | || (REGNO) == HARD_Y_REGNUM \ | |
642 | || (REGNO) == HARD_Z_REGNUM) | |
643 | #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) | |
644 | ||
645 | /* M68hc11 hard registers. */ | |
646 | #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \ | |
647 | || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO)) | |
648 | #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X))) | |
649 | ||
650 | #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM) | |
651 | #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X))) | |
652 | ||
653 | /* Soft registers (or register emulation for gcc). The temporary register | |
654 | used by insn template must be part of the S_REGS class so that it | |
655 | matches the 'u' constraint. */ | |
656 | #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \ | |
657 | && (REGNO) <= SOFT_REG_LAST \ | |
658 | && (REGNO) != FAKE_CLOBBER_REGNUM) | |
659 | #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) | |
660 | ||
661 | #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) | |
662 | #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) | |
663 | ||
664 | /* General register. */ | |
665 | #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \ | |
666 | || ((REGNO) == HARD_PC_REGNUM) \ | |
667 | || ((REGNO) == HARD_FP_REGNUM) \ | |
668 | || ((REGNO) == SOFT_FP_REGNUM) \ | |
669 | || ((REGNO) == FAKE_CLOBBER_REGNUM) \ | |
670 | || ((REGNO) == SOFT_AP_REGNUM)) | |
671 | ||
672 | #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X))) | |
673 | ||
674 | #define REGNO_REG_CLASS(REGNO) \ | |
675 | (D_REGNO_P (REGNO) ? D_REGS : \ | |
676 | (X_REGNO_P (REGNO) ? X_REGS : \ | |
677 | (Y_REGNO_P (REGNO) ? Y_REGS : \ | |
678 | (SP_REGNO_P (REGNO) ? SP_REGS : \ | |
679 | (Z_REGNO_P (REGNO) ? Z_REGS : \ | |
680 | (H_REGNO_P (REGNO) ? H_REGS : \ | |
681 | (FAKE_REGNO_P (REGNO) ? TMP_REGS : \ | |
682 | (S_REGNO_P (REGNO) ? S_REGS : \ | |
683 | (DA_REGNO_P (REGNO) ? DA_REGS: \ | |
684 | (DB_REGNO_P (REGNO) ? DB_REGS: \ | |
685 | (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))) | |
686 | ||
687 | ||
688 | /* Get reg_class from a letter in the machine description. */ | |
689 | ||
690 | extern enum reg_class m68hc11_tmp_regs_class; | |
691 | #define REG_CLASS_FROM_LETTER(C) \ | |
692 | ((C) == 'a' ? DA_REGS : \ | |
693 | (C) == 'A' ? A_REGS : \ | |
694 | (C) == 'b' ? DB_REGS : \ | |
695 | (C) == 'B' ? X_OR_Y_REGS : \ | |
696 | (C) == 'd' ? D_REGS : \ | |
697 | (C) == 'D' ? D_OR_X_REGS : \ | |
698 | (C) == 'q' ? Q_REGS : \ | |
699 | (C) == 'h' ? H_REGS : \ | |
700 | (C) == 't' ? TMP_REGS : \ | |
701 | (C) == 'u' ? S_REGS : \ | |
702 | (C) == 'v' ? m68hc11_tmp_regs_class : \ | |
703 | (C) == 'w' ? SP_REGS : \ | |
704 | (C) == 'x' ? X_REGS : \ | |
705 | (C) == 'y' ? Y_REGS : \ | |
706 | (C) == 'z' ? Z_REGS : NO_REGS) | |
707 | ||
708 | #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS) | |
709 | ||
385c9217 SC |
710 | #define SMALL_REGISTER_CLASSES 1 |
711 | ||
2d8d15b7 SC |
712 | /* A C expression that is nonzero if hard register number REGNO2 can be |
713 | considered for use as a rename register for REGNO1 */ | |
714 | ||
715 | #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ | |
716 | m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2)) | |
717 | ||
385c9217 SC |
718 | /* A C expression whose value is nonzero if pseudos that have been |
719 | assigned to registers of class CLASS would likely be spilled | |
720 | because registers of CLASS are needed for spill registers. | |
721 | ||
722 | The default value of this macro returns 1 if CLASS has exactly one | |
723 | register and zero otherwise. On most machines, this default | |
724 | should be used. Only define this macro to some other expression | |
725 | if pseudo allocated by `local-alloc.c' end up in memory because | |
726 | their hard registers were needed for spill registers. If this | |
727 | macro returns nonzero for those classes, those pseudos will only | |
728 | be allocated by `global.c', which knows how to reallocate the | |
729 | pseudo to another register. If there would not be another | |
730 | register available for reallocation, you should not change the | |
731 | definition of this macro since the only effect of such a | |
732 | definition would be to slow down register allocation. */ | |
733 | ||
734 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
735 | (((CLASS) == D_REGS) \ | |
736 | || ((CLASS) == X_REGS) \ | |
737 | || ((CLASS) == Y_REGS) \ | |
738 | || ((CLASS) == A_REGS) \ | |
739 | || ((CLASS) == SP_REGS) \ | |
740 | || ((CLASS) == D_OR_X_REGS) \ | |
741 | || ((CLASS) == D_OR_Y_REGS) \ | |
742 | || ((CLASS) == X_OR_SP_REGS) \ | |
743 | || ((CLASS) == Y_OR_SP_REGS) \ | |
744 | || ((CLASS) == D_OR_SP_REGS)) | |
745 | ||
746 | /* Return the maximum number of consecutive registers needed to represent | |
747 | mode MODE in a register of class CLASS. */ | |
748 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
749 | (((CLASS) == DA_REGS || (CLASS) == DB_REGS \ | |
750 | || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \ | |
751 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
752 | ||
753 | /* The letters I, J, K, L and M in a register constraint string | |
754 | can be used to stand for particular ranges of immediate operands. | |
755 | This macro defines what the ranges are. | |
756 | C is the letter, and VALUE is a constant value. | |
757 | Return 1 if VALUE is in the range specified by C. | |
758 | ||
65e6c005 | 759 | `K' is for 0. |
385c9217 SC |
760 | `L' is for range -65536 to 65536 |
761 | `M' is for values whose 16-bit low part is 0 | |
762 | 'N' is for +1 or -1. | |
763 | 'O' is for 16 (for rotate using swap). | |
764 | 'P' is for range -8 to 2 (used by addhi_sp) | |
765 | ||
65e6c005 | 766 | 'I', 'J' are not used. */ |
385c9217 SC |
767 | |
768 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
65e6c005 JJ |
769 | ((C) == 'K' ? (VALUE) == 0 : \ |
770 | (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \ | |
385c9217 | 771 | (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \ |
65e6c005 | 772 | (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \ |
0e01d661 | 773 | (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \ |
385c9217 | 774 | (C) == 'O' ? (VALUE) == 16 : \ |
65e6c005 | 775 | (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0) |
385c9217 SC |
776 | |
777 | /* Similar, but for floating constants, and defining letters G and H. | |
65e6c005 JJ |
778 | |
779 | `G' is for 0.0. */ | |
780 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
781 | ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ | |
782 | && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) | |
385c9217 SC |
783 | |
784 | /* 'U' represents certain kind of memory indexed operand for 68HC12. | |
d5ebbf58 SC |
785 | and any memory operand for 68HC11. |
786 | 'R' represents indexed addressing mode or access to page0 for 68HC11. | |
787 | For 68HC12, it represents any memory operand. */ | |
385c9217 | 788 | #define EXTRA_CONSTRAINT(OP, C) \ |
932657df SC |
789 | ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \ |
790 | : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \ | |
65e6c005 JJ |
791 | : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \ |
792 | : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \ | |
793 | && non_push_operand (OP, GET_MODE (OP))) : 0) | |
385c9217 SC |
794 | |
795 | \f | |
796 | /* Stack layout; function entry, exit and calling. */ | |
797 | ||
798 | /* Define this if pushing a word on the stack | |
799 | makes the stack pointer a smaller address. */ | |
800 | #define STACK_GROWS_DOWNWARD | |
801 | ||
a4d05547 | 802 | /* Define this to nonzero if the nominal address of the stack frame |
385c9217 SC |
803 | is at the high-address end of the local variables; |
804 | that is, each additional local variable allocated | |
805 | goes at a more negative offset in the frame. | |
806 | ||
f62c8a5c | 807 | Define to 0 for 68HC11, the frame pointer is the bottom |
385c9217 | 808 | of local variables. */ |
f62c8a5c | 809 | #define FRAME_GROWS_DOWNWARD 0 |
385c9217 SC |
810 | |
811 | /* Define this if successive arguments to a function occupy decreasing | |
812 | addresses in the stack. */ | |
813 | /* #define ARGS_GROW_DOWNWARD */ | |
814 | ||
815 | /* Offset within stack frame to start allocating local variables at. | |
816 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
817 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
818 | of the first local allocated. */ | |
8dd5d49d | 819 | #define STARTING_FRAME_OFFSET 0 |
385c9217 SC |
820 | |
821 | /* Offset of first parameter from the argument pointer register value. */ | |
822 | ||
823 | #define FIRST_PARM_OFFSET(FNDECL) 2 | |
824 | ||
35f0a736 | 825 | /* After the prologue, RA is at 0(AP) in the current frame. */ |
5becdf11 SC |
826 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
827 | ((COUNT) == 0 \ | |
35f0a736 | 828 | ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ |
5becdf11 SC |
829 | : 0) |
830 | ||
385c9217 SC |
831 | /* Before the prologue, the top of the frame is at 2(sp). */ |
832 | #define INCOMING_FRAME_SP_OFFSET 2 | |
833 | ||
834 | /* Define this if functions should assume that stack space has been | |
835 | allocated for arguments even when their values are passed in | |
836 | registers. | |
837 | ||
838 | The value of this macro is the size, in bytes, of the area reserved for | |
839 | arguments passed in registers. | |
840 | ||
841 | This space can either be allocated by the caller or be a part of the | |
842 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' | |
9caea35c | 843 | says which. */ |
385c9217 SC |
844 | /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */ |
845 | ||
846 | /* Define this macro if REG_PARM_STACK_SPACE is defined but stack | |
847 | parameters don't skip the area specified by REG_PARM_STACK_SPACE. | |
848 | Normally, when a parameter is not passed in registers, it is placed on | |
849 | the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro | |
850 | suppresses this behavior and causes the parameter to be passed on the | |
851 | stack in its natural location. */ | |
852 | /* #define STACK_PARMS_IN_REG_PARM_AREA */ | |
853 | ||
854 | /* Register to use for pushing function arguments. */ | |
855 | #define STACK_POINTER_REGNUM HARD_SP_REGNUM | |
856 | ||
857 | /* Base register for access to local variables of the function. */ | |
858 | #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM | |
859 | ||
860 | #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM | |
861 | ||
862 | /* Base register for access to arguments of the function. */ | |
863 | #define ARG_POINTER_REGNUM SOFT_AP_REGNUM | |
864 | ||
865 | /* Register in which static-chain is passed to a function. */ | |
7bdf2c65 | 866 | #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM |
385c9217 SC |
867 | |
868 | \f | |
869 | /* Definitions for register eliminations. | |
870 | ||
871 | This is an array of structures. Each structure initializes one pair | |
872 | of eliminable registers. The "from" register number is given first, | |
873 | followed by "to". Eliminations of the same "from" register are listed | |
874 | in order of preference. | |
875 | ||
2067c116 | 876 | We have two registers that are eliminated on the 6811. The pseudo arg |
385c9217 | 877 | pointer and pseudo frame pointer registers can always be eliminated; |
9caea35c | 878 | they are replaced with either the stack or the real frame pointer. */ |
385c9217 SC |
879 | |
880 | #define ELIMINABLE_REGS \ | |
881 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
882 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
883 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
884 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
885 | ||
886 | /* Value should be nonzero if functions must have frame pointers. | |
887 | Zero means the frame pointer need not be set up (and parms may be | |
888 | accessed via the stack pointer) in functions that seem suitable. | |
9caea35c | 889 | This is computed in `reload', in reload1.c. */ |
385c9217 SC |
890 | #define FRAME_POINTER_REQUIRED 0 |
891 | ||
892 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
893 | Frame pointer elimination is automatically handled. | |
894 | ||
895 | All other eliminations are valid. */ | |
896 | ||
897 | #define CAN_ELIMINATE(FROM, TO) \ | |
898 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
899 | ? ! frame_pointer_needed \ | |
900 | : 1) | |
901 | ||
902 | ||
903 | /* Define the offset between two registers, one to be eliminated, and the other | |
904 | its replacement, at the start of a routine. */ | |
905 | ||
906 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
907 | { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); } | |
908 | ||
385c9217 SC |
909 | \f |
910 | /* Passing Function Arguments on the Stack. */ | |
911 | ||
385c9217 SC |
912 | /* If we generate an insn to push BYTES bytes, this says how many the |
913 | stack pointer really advances by. No rounding or alignment needed | |
9caea35c | 914 | for MC6811. */ |
385c9217 SC |
915 | #define PUSH_ROUNDING(BYTES) (BYTES) |
916 | ||
917 | /* Value is 1 if returning from a function call automatically pops the | |
918 | arguments described by the number-of-args field in the call. FUNTYPE is | |
919 | the data type of the function (as a tree), or for a library call it is | |
920 | an identifier node for the subroutine name. | |
921 | ||
922 | The standard MC6811 call, with arg count word, includes popping the | |
9caea35c | 923 | args as part of the call template. */ |
385c9217 | 924 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
385c9217 SC |
925 | \f |
926 | /* Passing Arguments in Registers. */ | |
927 | ||
928 | /* Define a data type for recording info about an argument list | |
929 | during the scan of that argument list. This data type should | |
930 | hold all necessary information about the function itself | |
931 | and about the args processed so far, enough to enable macros | |
932 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
933 | ||
934 | typedef struct m68hc11_args | |
935 | { | |
936 | int words; | |
937 | int nregs; | |
938 | } CUMULATIVE_ARGS; | |
939 | ||
385c9217 SC |
940 | /* If defined, a C expression which determines whether, and in which direction, |
941 | to pad out an argument with extra space. The value should be of type | |
942 | `enum direction': either `upward' to pad above the argument, | |
943 | `downward' to pad below, or `none' to inhibit padding. | |
944 | ||
945 | Structures are stored left shifted in their argument slot. */ | |
946 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
947 | m68hc11_function_arg_padding ((MODE), (TYPE)) | |
948 | ||
f2d0440f SC |
949 | #undef PAD_VARARGS_DOWN |
950 | #define PAD_VARARGS_DOWN \ | |
951 | (m68hc11_function_arg_padding (TYPE_MODE (type), type) == downward) | |
952 | ||
385c9217 | 953 | /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a |
9caea35c | 954 | function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ |
0f6937fe | 955 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
385c9217 SC |
956 | (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) |
957 | ||
958 | /* Update the data in CUM to advance over an argument of mode MODE and data | |
959 | type TYPE. (TYPE is null for libcalls where that information may not be | |
960 | available.) */ | |
961 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
962 | (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED)) | |
963 | ||
964 | /* Define where to put the arguments to a function. | |
965 | Value is zero to push the argument on the stack, | |
966 | or a hard register in which to store the argument. | |
967 | ||
968 | MODE is the argument's machine mode. | |
969 | TYPE is the data type of the argument (as a tree). | |
970 | This is null for libcalls where that information may | |
971 | not be available. | |
972 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
973 | the preceding args and about the function being called. | |
974 | NAMED is nonzero if this argument is a named parameter | |
975 | (otherwise it is an extra parameter matching an ellipsis). */ | |
976 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
977 | (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED)) | |
978 | ||
979 | /* Define the profitability of saving registers around calls. | |
980 | ||
981 | Disable this because the saving instructions generated by | |
982 | caller-save need a reload and the way it is implemented, | |
983 | it forbids all spill registers at that point. Enabling | |
984 | caller saving results in spill failure. */ | |
985 | #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 | |
986 | ||
385c9217 SC |
987 | /* 1 if N is a possible register number for function argument passing. |
988 | D is for 16-bit values, X is for 32-bit (X+D). */ | |
989 | #define FUNCTION_ARG_REGNO_P(N) \ | |
990 | (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) | |
991 | ||
992 | /* All return values are in the D or X+D registers: | |
993 | - 8 and 16-bit values are returned in D. | |
994 | BLKmode are passed in D as pointer. | |
995 | - 32-bit values are returned in X + D. | |
996 | The high part is passed in X and the low part in D. | |
997 | For GCC, the register number must be HARD_X_REGNUM. */ | |
998 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
f1c25d3b | 999 | gen_rtx_REG (TYPE_MODE (VALTYPE), \ |
385c9217 SC |
1000 | ((TYPE_MODE (VALTYPE) == BLKmode \ |
1001 | || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \ | |
1002 | ? HARD_D_REGNUM : HARD_X_REGNUM)) | |
1003 | ||
1004 | #define LIBCALL_VALUE(MODE) \ | |
f1c25d3b | 1005 | gen_rtx_REG (MODE, \ |
385c9217 SC |
1006 | (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \ |
1007 | ? HARD_D_REGNUM : HARD_X_REGNUM)) | |
1008 | ||
1009 | /* 1 if N is a possible register number for a function value. */ | |
1010 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
1011 | ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM) | |
1012 | ||
385c9217 SC |
1013 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1014 | the stack pointer does not matter. The value is tested only in functions | |
1015 | that have frame pointers. No definition is equivalent to always zero. */ | |
1016 | #define EXIT_IGNORE_STACK 0 | |
1017 | ||
1018 | \f | |
1019 | /* Generating Code for Profiling. */ | |
1020 | ||
1021 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
1022 | for profiling a function entry. */ | |
1023 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
761c70aa | 1024 | fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO)) |
385c9217 | 1025 | /* Length in units of the trampoline for entering a nested function. */ |
7bdf2c65 | 1026 | #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9) |
385c9217 SC |
1027 | |
1028 | /* A C statement to initialize the variable parts of a trampoline. | |
1029 | ADDR is an RTX for the address of the trampoline; FNADDR is an | |
1030 | RTX for the address of the nested function; STATIC_CHAIN is an | |
1031 | RTX for the static chain value that should be passed to the | |
1032 | function when it is called. */ | |
7bdf2c65 SC |
1033 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1034 | m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
1035 | ||
385c9217 SC |
1036 | \f |
1037 | /* Addressing modes, and classification of registers for them. */ | |
02ee533e SC |
1038 | |
1039 | #define ADDR_STRICT 0x01 /* Accept only registers in class A_REGS */ | |
1040 | #define ADDR_INCDEC 0x02 /* Post/Pre inc/dec */ | |
1041 | #define ADDR_INDEXED 0x04 /* D-reg index */ | |
1042 | #define ADDR_OFFSET 0x08 | |
1043 | #define ADDR_INDIRECT 0x10 /* Accept (mem (mem ...)) for [n,X] */ | |
1044 | #define ADDR_CONST 0x20 /* Accept const and symbol_ref */ | |
385c9217 SC |
1045 | |
1046 | /* The 68HC12 has all the post/pre increment/decrement modes. */ | |
1047 | #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1048 | #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1049 | #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1050 | #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) | |
1051 | ||
1052 | /* The class value for base registers. This depends on the target: | |
1053 | A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value | |
1054 | is stored at init time. */ | |
1055 | extern enum reg_class m68hc11_base_reg_class; | |
1056 | #define BASE_REG_CLASS m68hc11_base_reg_class | |
1057 | ||
1058 | /* The class value for index registers. This is NO_REGS for 68HC11. */ | |
1059 | ||
1060 | extern enum reg_class m68hc11_index_reg_class; | |
1061 | #define INDEX_REG_CLASS m68hc11_index_reg_class | |
1062 | ||
1063 | /* These assume that REGNO is a hard or pseudo reg number. They give nonzero | |
1064 | only if REGNO is a hard reg of the suitable class or a pseudo reg currently | |
1065 | allocated to a suitable hard reg. Since they use reg_renumber, they are | |
1066 | safe only once reg_renumber has been allocated, which happens in | |
1067 | local-alloc.c. */ | |
1068 | ||
1069 | ||
1070 | /* Internal macro, return 1 if REGNO is a valid base register. */ | |
a63569e1 | 1071 | #define REG_VALID_P(REGNO) ((REGNO) >= 0) |
385c9217 SC |
1072 | |
1073 | extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER]; | |
1074 | #define REG_VALID_FOR_BASE_P(REGNO) \ | |
1075 | (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \ | |
1076 | && m68hc11_reg_valid_for_base[REGNO]) | |
1077 | ||
1078 | /* Internal macro, return 1 if REGNO is a valid index register. */ | |
1079 | extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER]; | |
1080 | #define REG_VALID_FOR_INDEX_P(REGNO) \ | |
1081 | (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \ | |
1082 | && m68hc11_reg_valid_for_index[REGNO]) | |
1083 | ||
1084 | /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */ | |
1085 | #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ | |
1086 | ((REGNO) >= FIRST_PSEUDO_REGISTER \ | |
1087 | || REG_VALID_FOR_BASE_P (REGNO) \ | |
1088 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
1089 | || (REGNO) == HARD_FRAME_POINTER_REGNUM \ | |
1090 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1091 | || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) | |
1092 | ||
1093 | /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */ | |
1094 | #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ | |
1095 | (TARGET_M6812 \ | |
1096 | && ((REGNO) >= FIRST_PSEUDO_REGISTER \ | |
1097 | || REG_VALID_FOR_INDEX_P (REGNO) \ | |
1098 | || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) | |
1099 | ||
1100 | /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */ | |
1101 | #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \ | |
1102 | ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \ | |
1103 | : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) | |
1104 | ||
1105 | /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */ | |
1106 | #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \ | |
1107 | (TARGET_M6812 \ | |
1108 | && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \ | |
1109 | : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) | |
1110 | ||
1111 | #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \ | |
1112 | ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \ | |
1113 | : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO))) | |
1114 | ||
1115 | #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \ | |
1116 | ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \ | |
1117 | : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO))) | |
1118 | ||
1119 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO) | |
1120 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO) | |
1121 | ||
1122 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X)) | |
1123 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X)) | |
1124 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X)) | |
1125 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X)) | |
1126 | ||
1127 | /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */ | |
1128 | #define IS_STACK_PUSH(operand) \ | |
1129 | ((GET_CODE (operand) == MEM) \ | |
1130 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \ | |
1131 | && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) | |
1132 | ||
1133 | #define IS_STACK_POP(operand) \ | |
1134 | ((GET_CODE (operand) == MEM) \ | |
1135 | && (GET_CODE (XEXP (operand, 0)) == POST_INC) \ | |
1136 | && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) | |
1137 | ||
1138 | /* 1 if X is an rtx for a constant that is a valid address. */ | |
1139 | #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) | |
1140 | ||
1141 | /* Maximum number of registers that can appear in a valid memory address */ | |
1142 | #define MAX_REGS_PER_ADDRESS 2 | |
1143 | ||
1144 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a | |
1145 | valid memory address for an instruction. The MODE argument is the | |
1146 | machine mode for the MEM expression that wants to use this address. */ | |
1147 | ||
1148 | /*-------------------------------------------------------------- | |
1149 | Valid addresses are either direct or indirect (MEM) versions | |
1150 | of the following forms: | |
1151 | constant N | |
1152 | register ,X | |
1153 | indexed N,X | |
1154 | --------------------------------------------------------------*/ | |
1155 | ||
9caea35c | 1156 | /* The range of index that is allowed by indirect addressing. */ |
385c9217 SC |
1157 | |
1158 | #define VALID_MIN_OFFSET m68hc11_min_offset | |
1159 | #define VALID_MAX_OFFSET m68hc11_max_offset | |
1160 | ||
1161 | /* The offset values which are allowed by the n,x and n,y addressing modes. | |
1162 | Take into account the size of the mode because we may have to add | |
1163 | a mode offset to access the lowest part of the data. | |
1164 | (For example, for an SImode, the last valid offset is 252.) */ | |
1165 | #define VALID_CONSTANT_OFFSET_P(X,MODE) \ | |
fdffea1a SC |
1166 | (((GET_CODE (X) == CONST_INT) && \ |
1167 | ((INTVAL (X) >= VALID_MIN_OFFSET) \ | |
1168 | && ((INTVAL (X) <= VALID_MAX_OFFSET \ | |
1169 | - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \ | |
1170 | || (TARGET_M6812 \ | |
1171 | && ((GET_CODE (X) == SYMBOL_REF) \ | |
1172 | || GET_CODE (X) == LABEL_REF \ | |
1173 | || GET_CODE (X) == CONST))) | |
385c9217 SC |
1174 | |
1175 | /* This is included to allow stack push/pop operations. Special hacks in the | |
1176 | md and m6811.c files exist to support this. */ | |
1177 | #define PUSH_POP_ADDRESS_P(X) \ | |
1178 | (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \ | |
1179 | && SP_REG_P (XEXP (X, 0))) | |
1180 | ||
9caea35c | 1181 | /* Go to ADDR if X is a valid address. */ |
385c9217 SC |
1182 | #ifndef REG_OK_STRICT |
1183 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1184 | { \ | |
1185 | if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \ | |
1186 | } | |
1187 | #else | |
1188 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1189 | { \ | |
1190 | if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \ | |
1191 | } | |
1192 | #endif | |
1193 | ||
1194 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its | |
1195 | validity for a certain class. We have two alternate definitions for each | |
1196 | of them. The usual definition accepts all pseudo regs; the other rejects | |
1197 | them unless they have been allocated suitable hard regs. The symbol | |
1198 | REG_OK_STRICT causes the latter definition to be used. | |
1199 | ||
1200 | Most source files want to accept pseudo regs in the hope that they will | |
1201 | get allocated to the class that the insn wants them to be in. Source files | |
1202 | for reload pass need to be strict. After reload, it makes no difference, | |
1203 | since pseudo regs have been eliminated by then. */ | |
1204 | ||
1205 | #ifndef REG_OK_STRICT | |
1206 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1207 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
1208 | ||
1209 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1210 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
1211 | #else | |
1212 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
1213 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
1214 | #endif | |
1215 | ||
1216 | ||
1217 | /* Try machine-dependent ways of modifying an illegitimate address | |
1218 | to be legitimate. If we find one, return the new, valid address. | |
1219 | This macro is used in only one place: `memory_address' in explow.c. | |
1220 | ||
1221 | OLDX is the address as it was before break_out_memory_refs was called. | |
1222 | In some cases it is useful to look at this to decide what needs to be done. | |
1223 | ||
1224 | MODE and WIN are passed so that this macro can use | |
1225 | GO_IF_LEGITIMATE_ADDRESS. | |
1226 | ||
1227 | It is always safe for this macro to do nothing. | |
1228 | It exists to recognize opportunities to optimize the output. */ | |
1229 | ||
1230 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1231 | { rtx operand = (X); \ | |
1232 | if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \ | |
1233 | { \ | |
1234 | (X) = operand; \ | |
1235 | GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \ | |
1236 | } \ | |
1237 | } | |
1238 | ||
1239 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1240 | has an effect that depends on the machine mode it is used for. */ | |
b9a76028 | 1241 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) |
385c9217 SC |
1242 | |
1243 | /* Nonzero if the constant value X is a legitimate general operand. | |
1244 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1245 | ||
1246 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1247 | ||
1248 | \f | |
1249 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1250 | ||
1251 | #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
1252 | m68hc11_notice_update_cc ((EXP), (INSN)) | |
1253 | ||
385c9217 | 1254 | /* Move costs between classes of registers */ |
cf011243 | 1255 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
a0ccf503 | 1256 | (m68hc11_register_move_cost (MODE, CLASS1, CLASS2)) |
385c9217 SC |
1257 | |
1258 | /* Move cost between register and memory. | |
1259 | - Move to a 16-bit register is reasonable, | |
1260 | - Move to a soft register can be expensive. */ | |
1261 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
1262 | m68hc11_memory_move_cost ((MODE),(CLASS),(IN)) | |
1263 | ||
1264 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1265 | is the default; other values are interpreted relative to that. | |
1266 | ||
1267 | Pretend branches are cheap because GCC generates sub-optimal code | |
1268 | for the default value. */ | |
1269 | #define BRANCH_COST 0 | |
1270 | ||
1271 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1272 | #define SLOW_BYTE_ACCESS 0 | |
1273 | ||
1274 | /* It is as good to call a constant function address as to call an address | |
1275 | kept in a register. */ | |
1276 | #define NO_FUNCTION_CSE | |
1277 | ||
1278 | /* Try a machine-dependent way of reloading an illegitimate address | |
1279 | operand. If we find one, push the reload and jump to WIN. This | |
1280 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1281 | ||
1282 | For M68HC11, we handle large displacements of a base register | |
839a4992 | 1283 | by splitting the addend across an addhi3 insn. |
385c9217 SC |
1284 | |
1285 | For M68HC12, the 64K offset range is available. | |
1286 | */ | |
1287 | ||
1288 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1289 | do { \ | |
1290 | /* We must recognize output that we have already generated ourselves. */ \ | |
1291 | if (GET_CODE (X) == PLUS \ | |
1292 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1293 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1294 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1295 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1296 | { \ | |
df4ae160 | 1297 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
385c9217 SC |
1298 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1299 | OPNUM, TYPE); \ | |
1300 | goto WIN; \ | |
1301 | } \ | |
1302 | if (GET_CODE (X) == PLUS \ | |
1303 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1304 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1305 | && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \ | |
1306 | { \ | |
1307 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1308 | HOST_WIDE_INT low, high; \ | |
1309 | high = val & (~0x0FF); \ | |
1310 | low = val & 0x00FF; \ | |
1311 | if (low >= 256-15) { high += 16; low -= 16; } \ | |
1312 | /* Reload the high part into a base reg; leave the low part \ | |
1313 | in the mem directly. */ \ | |
1314 | \ | |
1315 | X = gen_rtx_PLUS (Pmode, \ | |
1316 | gen_rtx_PLUS (Pmode, XEXP (X, 0), \ | |
1317 | GEN_INT (high)), \ | |
1318 | GEN_INT (low)); \ | |
1319 | \ | |
df4ae160 | 1320 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
385c9217 SC |
1321 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1322 | OPNUM, TYPE); \ | |
1323 | goto WIN; \ | |
1324 | } \ | |
1325 | } while (0) | |
1326 | ||
1327 | \f | |
1328 | /* Defining the Output Assembler Language. */ | |
1329 | ||
1330 | /* A default list of other sections which we might be "in" at any given | |
1331 | time. For targets that use additional sections (e.g. .tdesc) you | |
1332 | should override this definition in the target-specific file which | |
1333 | includes this file. */ | |
1334 | ||
1335 | /* Output before read-only data. */ | |
1336 | #define TEXT_SECTION_ASM_OP ("\t.sect\t.text") | |
1337 | ||
1338 | /* Output before writable data. */ | |
1339 | #define DATA_SECTION_ASM_OP ("\t.sect\t.data") | |
1340 | ||
1341 | /* Output before uninitialized data. */ | |
1342 | #define BSS_SECTION_ASM_OP ("\t.sect\t.bss") | |
1343 | ||
70a5787e SC |
1344 | /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. |
1345 | ||
1346 | Same as config/elfos.h but don't mark these section SHF_WRITE since | |
1347 | there is no shared library problem. */ | |
1348 | #undef CTORS_SECTION_ASM_OP | |
1349 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
1350 | ||
1351 | #undef DTORS_SECTION_ASM_OP | |
1352 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
1353 | ||
2cc07db4 RH |
1354 | #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor |
1355 | #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor | |
70a5787e | 1356 | |
385c9217 SC |
1357 | /* Comment character */ |
1358 | #define ASM_COMMENT_START ";" | |
1359 | ||
1360 | /* Output to assembler file text saying following lines | |
1361 | may contain character constants, extra white space, comments, etc. */ | |
1362 | #define ASM_APP_ON "; Begin inline assembler code\n#APP\n" | |
1363 | ||
1364 | /* Output to assembler file text saying following lines | |
1365 | no longer contain unusual constructs. */ | |
1366 | #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n" | |
1367 | ||
058edcdb SC |
1368 | /* Write the extra assembler code needed to declare a function properly. |
1369 | Some svr4 assemblers need to also have something extra said about the | |
1370 | function's return value. We allow for that here. | |
1371 | ||
1372 | For 68HC12 we mark functions that return with 'rtc'. The linker | |
1373 | will ensure that a 'call' is really made (instead of 'jsr'). | |
1374 | The debugger needs this information to correctly compute the stack frame. | |
1375 | ||
1376 | For 68HC11/68HC12 we also mark interrupt handlers for gdb to | |
1377 | compute the correct stack frame. */ | |
1378 | ||
1379 | #undef ASM_DECLARE_FUNCTION_NAME | |
1380 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ | |
1381 | do \ | |
1382 | { \ | |
1383 | fprintf (FILE, "%s", TYPE_ASM_OP); \ | |
1384 | assemble_name (FILE, NAME); \ | |
1385 | putc (',', FILE); \ | |
1386 | fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ | |
1387 | putc ('\n', FILE); \ | |
1388 | \ | |
dbcedbc4 | 1389 | if (current_function_far) \ |
058edcdb SC |
1390 | { \ |
1391 | fprintf (FILE, "\t.far\t"); \ | |
1392 | assemble_name (FILE, NAME); \ | |
1393 | putc ('\n', FILE); \ | |
1394 | } \ | |
1395 | else if (current_function_interrupt \ | |
1396 | || current_function_trap) \ | |
1397 | { \ | |
1398 | fprintf (FILE, "\t.interrupt\t"); \ | |
1399 | assemble_name (FILE, NAME); \ | |
639a8102 | 1400 | putc ('\n', FILE); \ |
058edcdb SC |
1401 | } \ |
1402 | ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
1403 | ASM_OUTPUT_LABEL(FILE, NAME); \ | |
1404 | } \ | |
1405 | while (0) | |
1406 | ||
385c9217 SC |
1407 | /* Output #ident as a .ident. */ |
1408 | ||
385c9217 | 1409 | /* output external reference */ |
586de218 | 1410 | #undef ASM_OUTPUT_EXTERNAL |
385c9217 SC |
1411 | #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ |
1412 | {fputs ("\t; extern\t", FILE); \ | |
1413 | assemble_name (FILE, NAME); \ | |
1414 | fputs ("\n", FILE);} | |
1415 | ||
385c9217 SC |
1416 | /* How to refer to registers in assembler output. This sequence is indexed |
1417 | by compiler's hard-register-number (see above). */ | |
1418 | #define REGISTER_NAMES \ | |
1419 | { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \ | |
1420 | "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \ | |
1421 | SOFT_REG_NAMES, "*sframe", "*ap"} | |
1422 | ||
385c9217 SC |
1423 | /* Print an instruction operand X on file FILE. CODE is the code from the |
1424 | %-spec for printing this operand. If `%z3' was used to print operand | |
1425 | 3, then CODE is 'z'. */ | |
1426 | ||
1427 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1428 | print_operand (FILE, X, CODE) | |
1429 | ||
9caea35c | 1430 | /* Print a memory operand whose address is X, on file FILE. */ |
385c9217 SC |
1431 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
1432 | print_operand_address (FILE, ADDR) | |
1433 | ||
1434 | /* This is how to output an insn to push/pop a register on the stack. | |
1435 | It need not be very fast code. | |
1436 | ||
1437 | Don't define because we don't know how to handle that with | |
1438 | the STATIC_CHAIN_REGNUM (soft register). Saving the static | |
1439 | chain must be made inside FUNCTION_PROFILER. */ | |
1440 | ||
1441 | #undef ASM_OUTPUT_REG_PUSH | |
1442 | #undef ASM_OUTPUT_REG_POP | |
1443 | ||
9caea35c | 1444 | /* This is how to output an element of a case-vector that is relative. */ |
385c9217 SC |
1445 | |
1446 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
761c70aa | 1447 | fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL) |
385c9217 | 1448 | |
9caea35c | 1449 | /* This is how to output an element of a case-vector that is absolute. */ |
385c9217 | 1450 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
761c70aa | 1451 | fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE) |
385c9217 SC |
1452 | |
1453 | /* This is how to output an assembler line that says to advance the | |
1454 | location counter to a multiple of 2**LOG bytes. */ | |
1455 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1456 | do { \ | |
1457 | if ((LOG) > 1) \ | |
761c70aa | 1458 | fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \ |
385c9217 SC |
1459 | } while (0) |
1460 | ||
1461 | \f | |
1462 | /* Assembler Commands for Exception Regions. */ | |
1463 | ||
dab66575 | 1464 | /* Default values provided by GCC should be ok. Assuming that DWARF-2 |
9caea35c | 1465 | frame unwind info is ok for this platform. */ |
385c9217 | 1466 | |
385c9217 SC |
1467 | #undef PREFERRED_DEBUGGING_TYPE |
1468 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1469 | ||
dbcedbc4 SC |
1470 | /* For the support of memory banks we need addresses that indicate |
1471 | the page number. */ | |
1472 | #define DWARF2_ADDR_SIZE 4 | |
1473 | ||
f6423302 SC |
1474 | /* SCz 2003-07-08: Don't use as dwarf2 .file/.loc directives because |
1475 | the linker is doing relaxation and it does not adjust the debug_line | |
1476 | sections when it shrinks the code. This results in invalid addresses | |
1477 | when debugging. This does not bless too much the HC11/HC12 as most | |
1478 | applications are embedded and small, hence a reasonable debug info. | |
71cc389b | 1479 | This problem is known for binutils 2.13, 2.14 and mainline. */ |
f6423302 SC |
1480 | #undef HAVE_AS_DWARF2_DEBUG_LINE |
1481 | ||
385c9217 SC |
1482 | /* The prefix for local labels. You should be able to define this as |
1483 | an empty string, or any arbitrary string (such as ".", ".L%", etc) | |
1484 | without having to make any other changes to account for the specific | |
1485 | definition. Note it is a string literal, not interpreted by printf | |
9caea35c | 1486 | and friends. */ |
385c9217 SC |
1487 | #define LOCAL_LABEL_PREFIX "." |
1488 | ||
1489 | /* The prefix for immediate operands. */ | |
1490 | #define IMMEDIATE_PREFIX "#" | |
6e7b07a7 | 1491 | #define GLOBAL_ASM_OP "\t.globl\t" |
385c9217 SC |
1492 | |
1493 | \f | |
1494 | /* Miscellaneous Parameters. */ | |
1495 | ||
385c9217 SC |
1496 | /* Specify the machine mode that this machine uses |
1497 | for the index in the tablejump instruction. */ | |
1498 | #define CASE_VECTOR_MODE Pmode | |
1499 | ||
385c9217 SC |
1500 | /* This flag, if defined, says the same insns that convert to a signed fixnum |
1501 | also convert validly to an unsigned one. */ | |
1502 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
1503 | ||
385c9217 SC |
1504 | /* Max number of bytes we can move from memory to memory in one |
1505 | reasonably fast instruction. */ | |
1506 | #define MOVE_MAX 2 | |
1507 | ||
1508 | /* MOVE_RATIO is the number of move instructions that is better than a | |
1509 | block move. Make this small on 6811, since the code size grows very | |
1510 | large with each move. */ | |
1511 | #define MOVE_RATIO 3 | |
1512 | ||
1513 | /* Define if shifts truncate the shift count which implies one can omit | |
1514 | a sign-extension or zero-extension of a shift count. */ | |
1515 | #define SHIFT_COUNT_TRUNCATED 1 | |
1516 | ||
1517 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1518 | is done just by pretending it is already truncated. */ | |
1519 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1520 | ||
1521 | /* Specify the machine mode that pointers have. After generation of rtl, the | |
1522 | compiler makes no further distinction between pointers and any other | |
1523 | objects of this machine mode. */ | |
1524 | #define Pmode HImode | |
1525 | ||
1526 | /* A function address in a call instruction is a byte address (for indexing | |
1527 | purposes) so give the MEM rtx a byte's mode. */ | |
1528 | #define FUNCTION_MODE QImode | |
1529 | ||
385c9217 SC |
1530 | extern int debug_m6811; |
1531 | extern int z_replacement_completed; | |
1532 | extern int current_function_interrupt; | |
1533 | extern int current_function_trap; | |
058edcdb | 1534 | extern int current_function_far; |
e9f13564 SC |
1535 | |
1536 | extern GTY(()) rtx m68hc11_compare_op0; | |
1537 | extern GTY(()) rtx m68hc11_compare_op1; | |
1538 | extern GTY(()) rtx m68hc11_soft_tmp_reg; | |
1539 | extern GTY(()) rtx ix_reg; | |
1540 | extern GTY(()) rtx iy_reg; | |
1541 | extern GTY(()) rtx d_reg; |