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Commit | Line | Data |
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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
6fb5fa3c DB |
2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
3 | 2005, 2006, 2007 Free Software Foundation, Inc. | |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
7ec022b2 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
11bb1f11 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
11bb1f11 JL |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
11bb1f11 JL |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 | 21 | |
11bb1f11 | 22 | #include "config.h" |
c5c76735 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
11bb1f11 | 26 | #include "rtl.h" |
bf6bb899 | 27 | #include "tree.h" |
11bb1f11 JL |
28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
11bb1f11 JL |
33 | #include "output.h" |
34 | #include "insn-attr.h" | |
35 | #include "flags.h" | |
36 | #include "recog.h" | |
37 | #include "expr.h" | |
e78d8e51 | 38 | #include "optabs.h" |
bf6bb899 | 39 | #include "function.h" |
11bb1f11 | 40 | #include "obstack.h" |
69bc71fa KG |
41 | #include "toplev.h" |
42 | #include "tm_p.h" | |
672a6f42 NB |
43 | #include "target.h" |
44 | #include "target-def.h" | |
11bb1f11 | 45 | |
d1776069 AO |
46 | /* This is used by GOTaddr2picreg to uniquely identify |
47 | UNSPEC_INT_LABELs. */ | |
48 | int mn10300_unspec_int_label_counter; | |
49 | ||
2beef00e AO |
50 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
51 | names are not prefixed by underscores, to tell whether to prefix a | |
52 | label with a plus sign or not, so that the assembler can tell | |
53 | symbol names from register names. */ | |
54 | int mn10300_protect_label; | |
55 | ||
13dd556c RS |
56 | /* The selected processor. */ |
57 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
58 | ||
4d1a91c2 JL |
59 | /* The size of the callee register save area. Right now we save everything |
60 | on entry since it costs us nothing in code size. It does cost us from a | |
61 | speed standpoint, so we want to optimize this sooner or later. */ | |
6fb5fa3c DB |
62 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
63 | + 4 * df_regs_ever_live_p (3) \ | |
64 | + 4 * df_regs_ever_live_p (6) \ | |
65 | + 4 * df_regs_ever_live_p (7) \ | |
66 | + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \ | |
67 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17))) | |
3c50106f RH |
68 | |
69 | ||
13dd556c | 70 | static bool mn10300_handle_option (size_t, const char *, int); |
7f682641 SB |
71 | static int mn10300_address_cost_1 (rtx, int *); |
72 | static int mn10300_address_cost (rtx); | |
73 | static bool mn10300_rtx_costs (rtx, int, int, int *); | |
74 | static void mn10300_file_start (void); | |
586de218 | 75 | static bool mn10300_return_in_memory (const_tree, const_tree); |
9024ea92 | 76 | static rtx mn10300_builtin_saveregs (void); |
8cd5a4e0 | 77 | static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
586de218 | 78 | const_tree, bool); |
78a52f11 RH |
79 | static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
80 | tree, bool); | |
672a6f42 NB |
81 | \f |
82 | /* Initialize the GCC target structure. */ | |
301d03af RS |
83 | #undef TARGET_ASM_ALIGNED_HI_OP |
84 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
4d1a91c2 | 85 | |
3c50106f RH |
86 | #undef TARGET_RTX_COSTS |
87 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
dcefdf67 RH |
88 | #undef TARGET_ADDRESS_COST |
89 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
3c50106f | 90 | |
1bc7c5b6 ZW |
91 | #undef TARGET_ASM_FILE_START |
92 | #define TARGET_ASM_FILE_START mn10300_file_start | |
93 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
94 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
95 | ||
13dd556c | 96 | #undef TARGET_DEFAULT_TARGET_FLAGS |
b1eb8119 | 97 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 |
13dd556c RS |
98 | #undef TARGET_HANDLE_OPTION |
99 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
100 | ||
d1776069 AO |
101 | #undef TARGET_ENCODE_SECTION_INFO |
102 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
103 | ||
9024ea92 | 104 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 105 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
9024ea92 KH |
106 | #undef TARGET_RETURN_IN_MEMORY |
107 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
8cd5a4e0 RH |
108 | #undef TARGET_PASS_BY_REFERENCE |
109 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
6cdd5672 RH |
110 | #undef TARGET_CALLEE_COPIES |
111 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
78a52f11 RH |
112 | #undef TARGET_ARG_PARTIAL_BYTES |
113 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
9024ea92 KH |
114 | |
115 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
116 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
117 | ||
d1776069 | 118 | static void mn10300_encode_section_info (tree, rtx, int); |
f6897b10 | 119 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 120 | \f |
13dd556c RS |
121 | /* Implement TARGET_HANDLE_OPTION. */ |
122 | ||
123 | static bool | |
124 | mn10300_handle_option (size_t code, | |
125 | const char *arg ATTRIBUTE_UNUSED, | |
126 | int value) | |
127 | { | |
128 | switch (code) | |
129 | { | |
130 | case OPT_mam33: | |
131 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
132 | return true; | |
133 | case OPT_mam33_2: | |
134 | mn10300_processor = (value | |
135 | ? PROCESSOR_AM33_2 | |
136 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
137 | return true; | |
138 | default: | |
139 | return true; | |
140 | } | |
141 | } | |
142 | ||
143 | /* Implement OVERRIDE_OPTIONS. */ | |
144 | ||
145 | void | |
146 | mn10300_override_options (void) | |
147 | { | |
148 | if (TARGET_AM33) | |
149 | target_flags &= ~MASK_MULT_BUG; | |
150 | } | |
151 | ||
1bc7c5b6 | 152 | static void |
f1777882 | 153 | mn10300_file_start (void) |
11bb1f11 | 154 | { |
1bc7c5b6 | 155 | default_file_start (); |
705ac34f | 156 | |
18e9d2f9 AO |
157 | if (TARGET_AM33_2) |
158 | fprintf (asm_out_file, "\t.am33_2\n"); | |
159 | else if (TARGET_AM33) | |
1bc7c5b6 | 160 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
161 | } |
162 | \f | |
163 | ||
11bb1f11 JL |
164 | /* Print operand X using operand code CODE to assembly language output file |
165 | FILE. */ | |
166 | ||
167 | void | |
f1777882 | 168 | print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
169 | { |
170 | switch (code) | |
171 | { | |
172 | case 'b': | |
173 | case 'B': | |
18e9d2f9 AO |
174 | if (cc_status.mdep.fpCC) |
175 | { | |
176 | switch (code == 'b' ? GET_CODE (x) | |
177 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
178 | { | |
179 | case NE: | |
180 | fprintf (file, "ne"); | |
181 | break; | |
182 | case EQ: | |
183 | fprintf (file, "eq"); | |
184 | break; | |
185 | case GE: | |
186 | fprintf (file, "ge"); | |
187 | break; | |
188 | case GT: | |
189 | fprintf (file, "gt"); | |
190 | break; | |
191 | case LE: | |
192 | fprintf (file, "le"); | |
193 | break; | |
194 | case LT: | |
195 | fprintf (file, "lt"); | |
196 | break; | |
197 | case ORDERED: | |
198 | fprintf (file, "lge"); | |
199 | break; | |
200 | case UNORDERED: | |
201 | fprintf (file, "uo"); | |
202 | break; | |
203 | case LTGT: | |
204 | fprintf (file, "lg"); | |
205 | break; | |
206 | case UNEQ: | |
207 | fprintf (file, "ue"); | |
208 | break; | |
209 | case UNGE: | |
210 | fprintf (file, "uge"); | |
211 | break; | |
212 | case UNGT: | |
213 | fprintf (file, "ug"); | |
214 | break; | |
215 | case UNLE: | |
216 | fprintf (file, "ule"); | |
217 | break; | |
218 | case UNLT: | |
219 | fprintf (file, "ul"); | |
220 | break; | |
221 | default: | |
dc759020 | 222 | gcc_unreachable (); |
18e9d2f9 AO |
223 | } |
224 | break; | |
225 | } | |
11bb1f11 JL |
226 | /* These are normal and reversed branches. */ |
227 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
228 | { | |
229 | case NE: | |
230 | fprintf (file, "ne"); | |
231 | break; | |
232 | case EQ: | |
233 | fprintf (file, "eq"); | |
234 | break; | |
235 | case GE: | |
236 | fprintf (file, "ge"); | |
237 | break; | |
238 | case GT: | |
239 | fprintf (file, "gt"); | |
240 | break; | |
241 | case LE: | |
242 | fprintf (file, "le"); | |
243 | break; | |
244 | case LT: | |
245 | fprintf (file, "lt"); | |
246 | break; | |
247 | case GEU: | |
248 | fprintf (file, "cc"); | |
249 | break; | |
250 | case GTU: | |
251 | fprintf (file, "hi"); | |
252 | break; | |
253 | case LEU: | |
254 | fprintf (file, "ls"); | |
255 | break; | |
256 | case LTU: | |
257 | fprintf (file, "cs"); | |
258 | break; | |
259 | default: | |
dc759020 | 260 | gcc_unreachable (); |
11bb1f11 JL |
261 | } |
262 | break; | |
263 | case 'C': | |
264 | /* This is used for the operand to a call instruction; | |
265 | if it's a REG, enclose it in parens, else output | |
266 | the operand normally. */ | |
267 | if (GET_CODE (x) == REG) | |
268 | { | |
269 | fputc ('(', file); | |
270 | print_operand (file, x, 0); | |
271 | fputc (')', file); | |
272 | } | |
273 | else | |
274 | print_operand (file, x, 0); | |
275 | break; | |
5abc5de9 | 276 | |
18e9d2f9 AO |
277 | case 'D': |
278 | switch (GET_CODE (x)) | |
279 | { | |
280 | case MEM: | |
281 | fputc ('(', file); | |
282 | output_address (XEXP (x, 0)); | |
283 | fputc (')', file); | |
284 | break; | |
285 | ||
286 | case REG: | |
287 | fprintf (file, "fd%d", REGNO (x) - 18); | |
288 | break; | |
289 | ||
290 | default: | |
dc759020 | 291 | gcc_unreachable (); |
18e9d2f9 AO |
292 | } |
293 | break; | |
294 | ||
38c37a0e JL |
295 | /* These are the least significant word in a 64bit value. */ |
296 | case 'L': | |
297 | switch (GET_CODE (x)) | |
298 | { | |
299 | case MEM: | |
300 | fputc ('(', file); | |
301 | output_address (XEXP (x, 0)); | |
302 | fputc (')', file); | |
303 | break; | |
304 | ||
305 | case REG: | |
306 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
307 | break; | |
308 | ||
309 | case SUBREG: | |
ddef6bc7 | 310 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
311 | break; |
312 | ||
313 | case CONST_DOUBLE: | |
314 | { | |
315 | long val[2]; | |
316 | REAL_VALUE_TYPE rv; | |
317 | ||
318 | switch (GET_MODE (x)) | |
319 | { | |
320 | case DFmode: | |
321 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
322 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 323 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
324 | break;; |
325 | case SFmode: | |
326 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
327 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 328 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
329 | break;; |
330 | case VOIDmode: | |
331 | case DImode: | |
332 | print_operand_address (file, | |
333 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
334 | break; | |
69bc71fa KG |
335 | default: |
336 | break; | |
38c37a0e JL |
337 | } |
338 | break; | |
339 | } | |
340 | ||
341 | case CONST_INT: | |
212bc5fa AO |
342 | { |
343 | rtx low, high; | |
344 | split_double (x, &low, &high); | |
345 | fprintf (file, "%ld", (long)INTVAL (low)); | |
346 | break; | |
347 | } | |
38c37a0e JL |
348 | |
349 | default: | |
dc759020 | 350 | gcc_unreachable (); |
38c37a0e JL |
351 | } |
352 | break; | |
353 | ||
354 | /* Similarly, but for the most significant word. */ | |
355 | case 'H': | |
356 | switch (GET_CODE (x)) | |
357 | { | |
358 | case MEM: | |
359 | fputc ('(', file); | |
b72f00af | 360 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
361 | output_address (XEXP (x, 0)); |
362 | fputc (')', file); | |
363 | break; | |
364 | ||
365 | case REG: | |
366 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
367 | break; | |
368 | ||
369 | case SUBREG: | |
ddef6bc7 | 370 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
371 | break; |
372 | ||
373 | case CONST_DOUBLE: | |
374 | { | |
375 | long val[2]; | |
376 | REAL_VALUE_TYPE rv; | |
377 | ||
378 | switch (GET_MODE (x)) | |
379 | { | |
380 | case DFmode: | |
381 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
382 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 383 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
384 | break;; |
385 | case SFmode: | |
dc759020 | 386 | gcc_unreachable (); |
38c37a0e JL |
387 | case VOIDmode: |
388 | case DImode: | |
5abc5de9 | 389 | print_operand_address (file, |
38c37a0e JL |
390 | GEN_INT (CONST_DOUBLE_HIGH (x))); |
391 | break; | |
69bc71fa KG |
392 | default: |
393 | break; | |
38c37a0e JL |
394 | } |
395 | break; | |
396 | } | |
397 | ||
398 | case CONST_INT: | |
212bc5fa AO |
399 | { |
400 | rtx low, high; | |
401 | split_double (x, &low, &high); | |
402 | fprintf (file, "%ld", (long)INTVAL (high)); | |
403 | break; | |
404 | } | |
405 | ||
38c37a0e | 406 | default: |
dc759020 | 407 | gcc_unreachable (); |
38c37a0e JL |
408 | } |
409 | break; | |
410 | ||
411 | case 'A': | |
412 | fputc ('(', file); | |
413 | if (GET_CODE (XEXP (x, 0)) == REG) | |
a556fd39 | 414 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
38c37a0e JL |
415 | else |
416 | output_address (XEXP (x, 0)); | |
417 | fputc (')', file); | |
418 | break; | |
419 | ||
6fafc523 | 420 | case 'N': |
dc759020 | 421 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 AO |
422 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
423 | break; | |
424 | ||
425 | case 'U': | |
dc759020 | 426 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 | 427 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
6fafc523 JL |
428 | break; |
429 | ||
576e5acc JL |
430 | /* For shift counts. The hardware ignores the upper bits of |
431 | any immediate, but the assembler will flag an out of range | |
432 | shift count as an error. So we mask off the high bits | |
433 | of the immediate here. */ | |
434 | case 'S': | |
435 | if (GET_CODE (x) == CONST_INT) | |
436 | { | |
a58be199 | 437 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
438 | break; |
439 | } | |
440 | /* FALL THROUGH */ | |
441 | ||
11bb1f11 JL |
442 | default: |
443 | switch (GET_CODE (x)) | |
444 | { | |
445 | case MEM: | |
446 | fputc ('(', file); | |
447 | output_address (XEXP (x, 0)); | |
448 | fputc (')', file); | |
449 | break; | |
450 | ||
38c37a0e JL |
451 | case PLUS: |
452 | output_address (x); | |
453 | break; | |
454 | ||
11bb1f11 JL |
455 | case REG: |
456 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
457 | break; | |
458 | ||
459 | case SUBREG: | |
ddef6bc7 | 460 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
461 | break; |
462 | ||
38c37a0e JL |
463 | /* This will only be single precision.... */ |
464 | case CONST_DOUBLE: | |
465 | { | |
466 | unsigned long val; | |
467 | REAL_VALUE_TYPE rv; | |
468 | ||
469 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
470 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 471 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
472 | break; |
473 | } | |
474 | ||
11bb1f11 JL |
475 | case CONST_INT: |
476 | case SYMBOL_REF: | |
477 | case CONST: | |
478 | case LABEL_REF: | |
479 | case CODE_LABEL: | |
d1776069 | 480 | case UNSPEC: |
11bb1f11 JL |
481 | print_operand_address (file, x); |
482 | break; | |
483 | default: | |
dc759020 | 484 | gcc_unreachable (); |
11bb1f11 JL |
485 | } |
486 | break; | |
487 | } | |
488 | } | |
489 | ||
490 | /* Output assembly language output for the address ADDR to FILE. */ | |
491 | ||
492 | void | |
f1777882 | 493 | print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
494 | { |
495 | switch (GET_CODE (addr)) | |
496 | { | |
705ac34f JL |
497 | case POST_INC: |
498 | print_operand_address (file, XEXP (addr, 0)); | |
499 | fputc ('+', file); | |
500 | break; | |
11bb1f11 | 501 | case REG: |
79e4122c | 502 | print_operand (file, addr, 0); |
11bb1f11 JL |
503 | break; |
504 | case PLUS: | |
505 | { | |
506 | rtx base, index; | |
507 | if (REG_P (XEXP (addr, 0)) | |
508 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
509 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
510 | else if (REG_P (XEXP (addr, 1)) | |
511 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
512 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
513 | else | |
dc759020 | 514 | gcc_unreachable (); |
11bb1f11 JL |
515 | print_operand (file, index, 0); |
516 | fputc (',', file); | |
517 | print_operand (file, base, 0);; | |
518 | break; | |
519 | } | |
520 | case SYMBOL_REF: | |
521 | output_addr_const (file, addr); | |
522 | break; | |
523 | default: | |
524 | output_addr_const (file, addr); | |
525 | break; | |
526 | } | |
527 | } | |
528 | ||
18e9d2f9 AO |
529 | /* Count the number of FP registers that have to be saved. */ |
530 | static int | |
f1777882 | 531 | fp_regs_to_save (void) |
18e9d2f9 AO |
532 | { |
533 | int i, n = 0; | |
534 | ||
535 | if (! TARGET_AM33_2) | |
536 | return 0; | |
537 | ||
538 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
6fb5fa3c | 539 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
18e9d2f9 AO |
540 | ++n; |
541 | ||
542 | return n; | |
543 | } | |
544 | ||
f6cd7c62 RS |
545 | /* Print a set of registers in the format required by "movm" and "ret". |
546 | Register K is saved if bit K of MASK is set. The data and address | |
547 | registers can be stored individually, but the extended registers cannot. | |
9f5ed61a | 548 | We assume that the mask already takes that into account. For instance, |
8596d0a1 | 549 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
550 | |
551 | void | |
f1777882 | 552 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
553 | { |
554 | int need_comma; | |
555 | int i; | |
556 | ||
557 | need_comma = 0; | |
558 | fputc ('[', file); | |
559 | ||
560 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
561 | if ((mask & (1 << i)) != 0) | |
562 | { | |
563 | if (need_comma) | |
564 | fputc (',', file); | |
565 | fputs (reg_names [i], file); | |
566 | need_comma = 1; | |
567 | } | |
568 | ||
569 | if ((mask & 0x3c000) != 0) | |
570 | { | |
dc759020 | 571 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
f6cd7c62 RS |
572 | if (need_comma) |
573 | fputc (',', file); | |
574 | fputs ("exreg1", file); | |
575 | need_comma = 1; | |
576 | } | |
577 | ||
578 | fputc (']', file); | |
579 | } | |
580 | ||
38c37a0e | 581 | int |
f1777882 | 582 | can_use_return_insn (void) |
38c37a0e | 583 | { |
460f4b9d JL |
584 | /* size includes the fixed stack space needed for function calls. */ |
585 | int size = get_frame_size () + current_function_outgoing_args_size; | |
586 | ||
587 | /* And space for the return pointer. */ | |
588 | size += current_function_outgoing_args_size ? 4 : 0; | |
38c37a0e JL |
589 | |
590 | return (reload_completed | |
591 | && size == 0 | |
6fb5fa3c DB |
592 | && !df_regs_ever_live_p (2) |
593 | && !df_regs_ever_live_p (3) | |
594 | && !df_regs_ever_live_p (6) | |
595 | && !df_regs_ever_live_p (7) | |
596 | && !df_regs_ever_live_p (14) | |
597 | && !df_regs_ever_live_p (15) | |
598 | && !df_regs_ever_live_p (16) | |
599 | && !df_regs_ever_live_p (17) | |
18e9d2f9 | 600 | && fp_regs_to_save () == 0 |
38c37a0e JL |
601 | && !frame_pointer_needed); |
602 | } | |
603 | ||
f6cd7c62 RS |
604 | /* Returns the set of live, callee-saved registers as a bitmask. The |
605 | callee-saved extended registers cannot be stored individually, so | |
8596d0a1 | 606 | all of them will be included in the mask if any one of them is used. */ |
f6cd7c62 RS |
607 | |
608 | int | |
f1777882 | 609 | mn10300_get_live_callee_saved_regs (void) |
f6cd7c62 RS |
610 | { |
611 | int mask; | |
612 | int i; | |
613 | ||
614 | mask = 0; | |
18e9d2f9 | 615 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
6fb5fa3c | 616 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
f6cd7c62 RS |
617 | mask |= (1 << i); |
618 | if ((mask & 0x3c000) != 0) | |
619 | mask |= 0x3c000; | |
620 | ||
621 | return mask; | |
622 | } | |
623 | ||
624 | /* Generate an instruction that pushes several registers onto the stack. | |
625 | Register K will be saved if bit K in MASK is set. The function does | |
626 | nothing if MASK is zero. | |
627 | ||
628 | To be compatible with the "movm" instruction, the lowest-numbered | |
629 | register must be stored in the lowest slot. If MASK is the set | |
630 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
631 | instruction will have the form: | |
632 | ||
633 | (parallel | |
634 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
635 | (set (mem:SI (plus:SI (reg:SI 9) | |
636 | (const_int -1*4))) | |
637 | (reg:SI RN)) | |
638 | ... | |
639 | (set (mem:SI (plus:SI (reg:SI 9) | |
640 | (const_int -N*4))) | |
641 | (reg:SI R1))) */ | |
642 | ||
643 | void | |
f1777882 | 644 | mn10300_gen_multiple_store (int mask) |
f6cd7c62 RS |
645 | { |
646 | if (mask != 0) | |
647 | { | |
648 | int i; | |
649 | int count; | |
650 | rtx par; | |
651 | int pari; | |
652 | ||
8596d0a1 | 653 | /* Count how many registers need to be saved. */ |
f6cd7c62 | 654 | count = 0; |
18e9d2f9 | 655 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
f6cd7c62 RS |
656 | if ((mask & (1 << i)) != 0) |
657 | count += 1; | |
658 | ||
659 | /* We need one PARALLEL element to update the stack pointer and | |
8596d0a1 | 660 | an additional element for each register that is stored. */ |
f6cd7c62 RS |
661 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
662 | ||
8596d0a1 | 663 | /* Create the instruction that updates the stack pointer. */ |
f6cd7c62 RS |
664 | XVECEXP (par, 0, 0) |
665 | = gen_rtx_SET (SImode, | |
666 | stack_pointer_rtx, | |
667 | gen_rtx_PLUS (SImode, | |
668 | stack_pointer_rtx, | |
669 | GEN_INT (-count * 4))); | |
670 | ||
8596d0a1 | 671 | /* Create each store. */ |
f6cd7c62 | 672 | pari = 1; |
18e9d2f9 | 673 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
f6cd7c62 RS |
674 | if ((mask & (1 << i)) != 0) |
675 | { | |
676 | rtx address = gen_rtx_PLUS (SImode, | |
677 | stack_pointer_rtx, | |
678 | GEN_INT (-pari * 4)); | |
679 | XVECEXP(par, 0, pari) | |
680 | = gen_rtx_SET (VOIDmode, | |
681 | gen_rtx_MEM (SImode, address), | |
682 | gen_rtx_REG (SImode, i)); | |
683 | pari += 1; | |
684 | } | |
685 | ||
686 | par = emit_insn (par); | |
687 | RTX_FRAME_RELATED_P (par) = 1; | |
688 | } | |
689 | } | |
690 | ||
11bb1f11 | 691 | void |
f1777882 | 692 | expand_prologue (void) |
11bb1f11 | 693 | { |
036182e7 | 694 | HOST_WIDE_INT size; |
3dbc43d1 | 695 | |
3dbc43d1 | 696 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
697 | size = get_frame_size () + current_function_outgoing_args_size; |
698 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 699 | |
8596d0a1 | 700 | /* If we use any of the callee-saved registers, save them now. */ |
f6cd7c62 | 701 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
777fbf09 | 702 | |
18e9d2f9 AO |
703 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
704 | { | |
705 | int num_regs_to_save = fp_regs_to_save (), i; | |
706 | HOST_WIDE_INT xsize; | |
707 | enum { save_sp_merge, | |
708 | save_sp_no_merge, | |
709 | save_sp_partial_merge, | |
710 | save_a0_merge, | |
711 | save_a0_no_merge } strategy; | |
712 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
713 | rtx reg; | |
714 | rtx insn; | |
715 | ||
716 | /* We have several different strategies to save FP registers. | |
717 | We can store them using SP offsets, which is beneficial if | |
718 | there are just a few registers to save, or we can use `a0' in | |
719 | post-increment mode (`a0' is the only call-clobbered address | |
720 | register that is never used to pass information to a | |
721 | function). Furthermore, if we don't need a frame pointer, we | |
722 | can merge the two SP adds into a single one, but this isn't | |
723 | always beneficial; sometimes we can just split the two adds | |
724 | so that we don't exceed a 16-bit constant size. The code | |
725 | below will select which strategy to use, so as to generate | |
726 | smallest code. Ties are broken in favor or shorter sequences | |
727 | (in terms of number of instructions). */ | |
728 | ||
729 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
730 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
731 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
732 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
733 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
734 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
735 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
736 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
737 | : (ELSE)) | |
738 | #define SIZE_FMOV_SP_(S,N) \ | |
739 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
740 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
741 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
742 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
743 | ||
744 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 745 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
746 | if (! frame_pointer_needed && size) |
747 | { | |
748 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
749 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
750 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
751 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
752 | ||
753 | if (this_strategy_size < strategy_size) | |
754 | { | |
755 | strategy = save_sp_merge; | |
756 | strategy_size = this_strategy_size; | |
757 | } | |
758 | } | |
759 | ||
760 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
761 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
762 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
763 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
764 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
765 | if (size) | |
766 | { | |
767 | /* Insn: add -size, sp. */ | |
768 | this_strategy_size += SIZE_ADD_SP (-size); | |
769 | } | |
770 | ||
771 | if (this_strategy_size < strategy_size) | |
772 | { | |
773 | strategy = save_sp_no_merge; | |
774 | strategy_size = this_strategy_size; | |
775 | } | |
776 | ||
777 | /* Consider alternative save_sp_partial_merge only if we don't | |
778 | need a frame pointer and size is reasonably large. */ | |
779 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
780 | { | |
781 | /* Insn: add -128, sp. */ | |
782 | this_strategy_size = SIZE_ADD_SP (-128); | |
783 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
784 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
785 | num_regs_to_save); | |
786 | if (size) | |
787 | { | |
788 | /* Insn: add 128-size, sp. */ | |
789 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
790 | } | |
791 | ||
792 | if (this_strategy_size < strategy_size) | |
793 | { | |
794 | strategy = save_sp_partial_merge; | |
795 | strategy_size = this_strategy_size; | |
796 | } | |
797 | } | |
798 | ||
799 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 800 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
801 | changed the calling conventions of a0. */ |
802 | if (! frame_pointer_needed && size | |
803 | && call_used_regs[FIRST_ADDRESS_REGNUM] | |
804 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
805 | { | |
806 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
807 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
808 | /* Insn: mov sp, a0. */ | |
809 | this_strategy_size++; | |
810 | if (size) | |
811 | { | |
812 | /* Insn: add size, a0. */ | |
813 | this_strategy_size += SIZE_ADD_AX (size); | |
814 | } | |
815 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
816 | this_strategy_size += 3 * num_regs_to_save; | |
817 | ||
818 | if (this_strategy_size < strategy_size) | |
819 | { | |
820 | strategy = save_a0_merge; | |
821 | strategy_size = this_strategy_size; | |
822 | } | |
823 | } | |
824 | ||
825 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 826 | changed the calling conventions of a0. */ |
18e9d2f9 AO |
827 | if (call_used_regs[FIRST_ADDRESS_REGNUM] |
828 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
829 | { | |
830 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
831 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
832 | /* Insn: mov sp, a0. */ | |
833 | this_strategy_size++; | |
834 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
835 | this_strategy_size += 3 * num_regs_to_save; | |
836 | if (size) | |
837 | { | |
838 | /* Insn: add -size, sp. */ | |
839 | this_strategy_size += SIZE_ADD_SP (-size); | |
840 | } | |
841 | ||
842 | if (this_strategy_size < strategy_size) | |
843 | { | |
844 | strategy = save_a0_no_merge; | |
845 | strategy_size = this_strategy_size; | |
846 | } | |
847 | } | |
848 | ||
849 | /* Emit the initial SP add, common to all strategies. */ | |
850 | switch (strategy) | |
851 | { | |
852 | case save_sp_no_merge: | |
853 | case save_a0_no_merge: | |
854 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
855 | stack_pointer_rtx, | |
856 | GEN_INT (-4 * num_regs_to_save))); | |
857 | xsize = 0; | |
858 | break; | |
859 | ||
860 | case save_sp_partial_merge: | |
861 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
862 | stack_pointer_rtx, | |
863 | GEN_INT (-128))); | |
864 | xsize = 128 - 4 * num_regs_to_save; | |
865 | size -= xsize; | |
866 | break; | |
867 | ||
868 | case save_sp_merge: | |
869 | case save_a0_merge: | |
870 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
871 | stack_pointer_rtx, | |
872 | GEN_INT (-(size + 4 * num_regs_to_save)))); | |
873 | /* We'll have to adjust FP register saves according to the | |
8596d0a1 | 874 | frame size. */ |
18e9d2f9 AO |
875 | xsize = size; |
876 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 877 | again at the end of the function. */ |
18e9d2f9 AO |
878 | size = 0; |
879 | break; | |
880 | ||
881 | default: | |
dc759020 | 882 | gcc_unreachable (); |
18e9d2f9 | 883 | } |
5abc5de9 | 884 | |
18e9d2f9 AO |
885 | /* Now prepare register a0, if we have decided to use it. */ |
886 | switch (strategy) | |
887 | { | |
888 | case save_sp_merge: | |
889 | case save_sp_no_merge: | |
890 | case save_sp_partial_merge: | |
891 | reg = 0; | |
892 | break; | |
893 | ||
894 | case save_a0_merge: | |
895 | case save_a0_no_merge: | |
896 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
897 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
898 | if (xsize) | |
899 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); | |
900 | reg = gen_rtx_POST_INC (SImode, reg); | |
901 | break; | |
5abc5de9 | 902 | |
18e9d2f9 | 903 | default: |
dc759020 | 904 | gcc_unreachable (); |
18e9d2f9 | 905 | } |
5abc5de9 | 906 | |
18e9d2f9 AO |
907 | /* Now actually save the FP registers. */ |
908 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
6fb5fa3c | 909 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
18e9d2f9 AO |
910 | { |
911 | rtx addr; | |
912 | ||
913 | if (reg) | |
914 | addr = reg; | |
915 | else | |
916 | { | |
917 | /* If we aren't using `a0', use an SP offset. */ | |
918 | if (xsize) | |
919 | { | |
920 | addr = gen_rtx_PLUS (SImode, | |
921 | stack_pointer_rtx, | |
922 | GEN_INT (xsize)); | |
923 | } | |
924 | else | |
925 | addr = stack_pointer_rtx; | |
5abc5de9 | 926 | |
18e9d2f9 AO |
927 | xsize += 4; |
928 | } | |
929 | ||
930 | insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), | |
931 | gen_rtx_REG (SImode, i))); | |
932 | ||
933 | RTX_FRAME_RELATED_P (insn) = 1; | |
934 | } | |
935 | } | |
936 | ||
777fbf09 | 937 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 938 | if (frame_pointer_needed) |
6e86170d | 939 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
11bb1f11 | 940 | |
777fbf09 | 941 | /* Allocate stack for this frame. */ |
11bb1f11 JL |
942 | if (size) |
943 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
944 | stack_pointer_rtx, | |
945 | GEN_INT (-size))); | |
6fb5fa3c DB |
946 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
947 | emit_insn (gen_GOTaddr2picreg ()); | |
11bb1f11 JL |
948 | } |
949 | ||
950 | void | |
f1777882 | 951 | expand_epilogue (void) |
11bb1f11 | 952 | { |
036182e7 | 953 | HOST_WIDE_INT size; |
3dbc43d1 | 954 | |
3dbc43d1 | 955 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
956 | size = get_frame_size () + current_function_outgoing_args_size; |
957 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 958 | |
18e9d2f9 AO |
959 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
960 | { | |
961 | int num_regs_to_save = fp_regs_to_save (), i; | |
962 | rtx reg = 0; | |
963 | ||
964 | /* We have several options to restore FP registers. We could | |
965 | load them from SP offsets, but, if there are enough FP | |
966 | registers to restore, we win if we use a post-increment | |
967 | addressing mode. */ | |
968 | ||
969 | /* If we have a frame pointer, it's the best option, because we | |
970 | already know it has the value we want. */ | |
971 | if (frame_pointer_needed) | |
972 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
973 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
974 | it's never used for return values. But only do so if it's | |
975 | smaller than using SP offsets. */ | |
976 | else | |
977 | { | |
978 | enum { restore_sp_post_adjust, | |
979 | restore_sp_pre_adjust, | |
980 | restore_sp_partial_adjust, | |
981 | restore_a1 } strategy; | |
982 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
983 | ||
984 | /* Consider using sp offsets before adjusting sp. */ | |
985 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
986 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
987 | /* If size is too large, we'll have to adjust SP with an | |
988 | add. */ | |
989 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
990 | { | |
991 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
992 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
993 | } | |
994 | /* If we don't have to restore any non-FP registers, | |
995 | we'll be able to save one byte by using rets. */ | |
996 | if (! REG_SAVE_BYTES) | |
997 | this_strategy_size--; | |
998 | ||
999 | if (this_strategy_size < strategy_size) | |
1000 | { | |
1001 | strategy = restore_sp_post_adjust; | |
1002 | strategy_size = this_strategy_size; | |
1003 | } | |
1004 | ||
1005 | /* Consider using sp offsets after adjusting sp. */ | |
1006 | /* Insn: add size, sp. */ | |
1007 | this_strategy_size = SIZE_ADD_SP (size); | |
1008 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1009 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1010 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1011 | save area, so, no savings. */ |
18e9d2f9 AO |
1012 | |
1013 | if (this_strategy_size < strategy_size) | |
1014 | { | |
1015 | strategy = restore_sp_pre_adjust; | |
1016 | strategy_size = this_strategy_size; | |
1017 | } | |
1018 | ||
1019 | /* Consider using sp offsets after partially adjusting sp. | |
1020 | When size is close to 32Kb, we may be able to adjust SP | |
1021 | with an imm16 add instruction while still using fmov | |
1022 | (d8,sp). */ | |
1023 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1024 | { | |
1025 | /* Insn: add size + 4 * num_regs_to_save | |
1026 | + REG_SAVE_BYTES - 252,sp. */ | |
1027 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1028 | + REG_SAVE_BYTES - 252); | |
1029 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1030 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1031 | - 4 * num_regs_to_save, | |
1032 | num_regs_to_save); | |
1033 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1034 | save area, so, no savings. */ |
18e9d2f9 AO |
1035 | |
1036 | if (this_strategy_size < strategy_size) | |
1037 | { | |
1038 | strategy = restore_sp_partial_adjust; | |
1039 | strategy_size = this_strategy_size; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* Consider using a1 in post-increment mode, as long as the | |
1044 | user hasn't changed the calling conventions of a1. */ | |
1045 | if (call_used_regs[FIRST_ADDRESS_REGNUM+1] | |
1046 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) | |
1047 | { | |
1048 | /* Insn: mov sp,a1. */ | |
1049 | this_strategy_size = 1; | |
1050 | if (size) | |
1051 | { | |
1052 | /* Insn: add size,a1. */ | |
1053 | this_strategy_size += SIZE_ADD_AX (size); | |
1054 | } | |
1055 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1056 | this_strategy_size += 3 * num_regs_to_save; | |
1057 | /* If size is large enough, we may be able to save a | |
1058 | couple of bytes. */ | |
1059 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1060 | { | |
1061 | /* Insn: mov a1,sp. */ | |
1062 | this_strategy_size += 2; | |
1063 | } | |
1064 | /* If we don't have to restore any non-FP registers, | |
1065 | we'll be able to save one byte by using rets. */ | |
1066 | if (! REG_SAVE_BYTES) | |
1067 | this_strategy_size--; | |
1068 | ||
1069 | if (this_strategy_size < strategy_size) | |
1070 | { | |
1071 | strategy = restore_a1; | |
1072 | strategy_size = this_strategy_size; | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | switch (strategy) | |
1077 | { | |
1078 | case restore_sp_post_adjust: | |
1079 | break; | |
1080 | ||
1081 | case restore_sp_pre_adjust: | |
1082 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1083 | stack_pointer_rtx, | |
1084 | GEN_INT (size))); | |
1085 | size = 0; | |
1086 | break; | |
1087 | ||
1088 | case restore_sp_partial_adjust: | |
1089 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1090 | stack_pointer_rtx, | |
1091 | GEN_INT (size + 4 * num_regs_to_save | |
1092 | + REG_SAVE_BYTES - 252))); | |
1093 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1094 | break; | |
5abc5de9 | 1095 | |
18e9d2f9 AO |
1096 | case restore_a1: |
1097 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1098 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1099 | if (size) | |
1100 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1101 | break; | |
1102 | ||
1103 | default: | |
dc759020 | 1104 | gcc_unreachable (); |
18e9d2f9 AO |
1105 | } |
1106 | } | |
1107 | ||
1108 | /* Adjust the selected register, if any, for post-increment. */ | |
1109 | if (reg) | |
1110 | reg = gen_rtx_POST_INC (SImode, reg); | |
1111 | ||
1112 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
6fb5fa3c | 1113 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
18e9d2f9 AO |
1114 | { |
1115 | rtx addr; | |
5abc5de9 | 1116 | |
18e9d2f9 AO |
1117 | if (reg) |
1118 | addr = reg; | |
1119 | else if (size) | |
1120 | { | |
1121 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1122 | SP offset. */ |
18e9d2f9 AO |
1123 | addr = gen_rtx_PLUS (SImode, |
1124 | stack_pointer_rtx, | |
1125 | GEN_INT (size)); | |
1126 | } | |
1127 | else | |
1128 | addr = stack_pointer_rtx; | |
1129 | ||
1130 | size += 4; | |
1131 | ||
1132 | emit_insn (gen_movsi (gen_rtx_REG (SImode, i), | |
1133 | gen_rtx_MEM (SImode, addr))); | |
1134 | } | |
1135 | ||
1136 | /* If we were using the restore_a1 strategy and the number of | |
1137 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1138 | to `sp', to avoid having to use `add' to adjust it. */ | |
1139 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1140 | { | |
1141 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1142 | size = 0; | |
1143 | } | |
1144 | } | |
1145 | ||
5d29a95f JL |
1146 | /* Maybe cut back the stack, except for the register save area. |
1147 | ||
1148 | If the frame pointer exists, then use the frame pointer to | |
1149 | cut back the stack. | |
1150 | ||
1151 | If the stack size + register save area is more than 255 bytes, | |
1152 | then the stack must be cut back here since the size + register | |
5abc5de9 | 1153 | save size is too big for a ret/retf instruction. |
5d29a95f JL |
1154 | |
1155 | Else leave it alone, it will be cut back as part of the | |
1156 | ret/retf instruction, or there wasn't any stack to begin with. | |
1157 | ||
dab66575 | 1158 | Under no circumstances should the register save area be |
5d29a95f JL |
1159 | deallocated here, that would leave a window where an interrupt |
1160 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1161 | if (frame_pointer_needed) |
1162 | { | |
11bb1f11 | 1163 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1164 | size = 0; |
1165 | } | |
ed6089d6 | 1166 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
1167 | { |
1168 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1169 | stack_pointer_rtx, | |
1170 | GEN_INT (size))); | |
1171 | size = 0; | |
11bb1f11 | 1172 | } |
11bb1f11 | 1173 | |
ed6089d6 | 1174 | /* Adjust the stack and restore callee-saved registers, if any. */ |
6fb5fa3c DB |
1175 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1176 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1177 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1178 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
777fbf09 | 1179 | || frame_pointer_needed) |
ed6089d6 AO |
1180 | emit_jump_insn (gen_return_internal_regs |
1181 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 1182 | else |
ed6089d6 | 1183 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
1184 | } |
1185 | ||
1186 | /* Update the condition code from the insn. */ | |
1187 | ||
1188 | void | |
f1777882 | 1189 | notice_update_cc (rtx body, rtx insn) |
11bb1f11 | 1190 | { |
11bb1f11 JL |
1191 | switch (get_attr_cc (insn)) |
1192 | { | |
1193 | case CC_NONE: | |
1194 | /* Insn does not affect CC at all. */ | |
1195 | break; | |
1196 | ||
1197 | case CC_NONE_0HIT: | |
1198 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1199 | if (cc_status.value1 != 0 | |
1ccbefce | 1200 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
1201 | cc_status.value1 = 0; |
1202 | break; | |
1203 | ||
d116300b | 1204 | case CC_SET_ZN: |
1ccbefce | 1205 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 1206 | V,C are unusable. */ |
11bb1f11 | 1207 | CC_STATUS_INIT; |
d116300b | 1208 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 1209 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
1210 | break; |
1211 | ||
d116300b | 1212 | case CC_SET_ZNV: |
1ccbefce | 1213 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 1214 | C is unusable. */ |
82c6faa8 | 1215 | CC_STATUS_INIT; |
d116300b | 1216 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 1217 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
1218 | break; |
1219 | ||
11bb1f11 JL |
1220 | case CC_COMPARE: |
1221 | /* The insn is a compare instruction. */ | |
1222 | CC_STATUS_INIT; | |
1223 | cc_status.value1 = SET_SRC (body); | |
18e9d2f9 AO |
1224 | if (GET_CODE (cc_status.value1) == COMPARE |
1225 | && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) | |
1226 | cc_status.mdep.fpCC = 1; | |
11bb1f11 JL |
1227 | break; |
1228 | ||
1229 | case CC_CLOBBER: | |
1230 | /* Insn doesn't leave CC in a usable state. */ | |
1231 | CC_STATUS_INIT; | |
1232 | break; | |
82c6faa8 JL |
1233 | |
1234 | default: | |
dc759020 | 1235 | gcc_unreachable (); |
11bb1f11 | 1236 | } |
11bb1f11 JL |
1237 | } |
1238 | ||
05713b80 | 1239 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1240 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1241 | parallel. If OP is a multiple store, return a mask indicating which | |
1242 | registers it saves. Return 0 otherwise. */ | |
1243 | ||
1244 | int | |
f1777882 | 1245 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
f6cd7c62 RS |
1246 | { |
1247 | int count; | |
1248 | int mask; | |
1249 | int i; | |
1250 | unsigned int last; | |
1251 | rtx elt; | |
1252 | ||
1253 | count = XVECLEN (op, 0); | |
1254 | if (count < 2) | |
1255 | return 0; | |
1256 | ||
1257 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1258 | elt = XVECEXP (op, 0, 0); | |
1259 | if (GET_CODE (elt) != SET | |
1260 | || GET_CODE (SET_DEST (elt)) != REG | |
1261 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1262 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1263 | return 0; | |
1264 | ||
1265 | /* Check that A is the stack pointer and B is the expected stack size. | |
1266 | For OP to match, each subsequent instruction should push a word onto | |
1267 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1268 | COUNT-1 stack slots. */ |
f6cd7c62 RS |
1269 | elt = SET_SRC (elt); |
1270 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1271 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1272 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1273 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1274 | return 0; | |
1275 | ||
1276 | /* Now go through the rest of the vector elements. They must be | |
1277 | ordered so that the first instruction stores the highest-numbered | |
1278 | register to the highest stack slot and that subsequent instructions | |
1279 | store a lower-numbered register to the slot below. | |
1280 | ||
1281 | LAST keeps track of the smallest-numbered register stored so far. | |
8596d0a1 | 1282 | MASK is the set of stored registers. */ |
18e9d2f9 | 1283 | last = LAST_EXTENDED_REGNUM + 1; |
f6cd7c62 RS |
1284 | mask = 0; |
1285 | for (i = 1; i < count; i++) | |
1286 | { | |
8596d0a1 | 1287 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
f6cd7c62 RS |
1288 | elt = XVECEXP (op, 0, i); |
1289 | if (GET_CODE (elt) != SET | |
1290 | || GET_CODE (SET_DEST (elt)) != MEM | |
1291 | || GET_CODE (SET_SRC (elt)) != REG | |
1292 | || REGNO (SET_SRC (elt)) >= last) | |
1293 | return 0; | |
1294 | ||
1295 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
8596d0a1 | 1296 | case if the rest of the instruction has a flaw. */ |
f6cd7c62 RS |
1297 | last = REGNO (SET_SRC (elt)); |
1298 | mask |= (1 << last); | |
1299 | ||
1300 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1301 | elt = XEXP (SET_DEST (elt), 0); | |
1302 | if (GET_CODE (elt) != PLUS | |
1303 | || GET_CODE (XEXP (elt, 0)) != REG | |
1304 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1305 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1306 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1307 | return 0; | |
1308 | } | |
1309 | ||
8596d0a1 | 1310 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1311 | if ((mask & 0x3c000) != 0 |
1312 | && (mask & 0x3c000) != 0x3c000) | |
1313 | return 0; | |
1314 | ||
1315 | return mask; | |
1316 | } | |
1317 | ||
11bb1f11 | 1318 | /* What (if any) secondary registers are needed to move IN with mode |
5abc5de9 | 1319 | MODE into a register in register class CLASS. |
11bb1f11 JL |
1320 | |
1321 | We might be able to simplify this. */ | |
1322 | enum reg_class | |
3c4774e0 R |
1323 | mn10300_secondary_reload_class (enum reg_class class, enum machine_mode mode, |
1324 | rtx in) | |
11bb1f11 | 1325 | { |
11bb1f11 JL |
1326 | /* Memory loads less than a full word wide can't have an |
1327 | address or stack pointer destination. They must use | |
1328 | a data register as an intermediate register. */ | |
15c09738 AH |
1329 | if ((GET_CODE (in) == MEM |
1330 | || (GET_CODE (in) == REG | |
1331 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
1332 | || (GET_CODE (in) == SUBREG | |
1333 | && GET_CODE (SUBREG_REG (in)) == REG | |
1334 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
11bb1f11 | 1335 | && (mode == QImode || mode == HImode) |
15c09738 | 1336 | && (class == ADDRESS_REGS || class == SP_REGS |
842a0788 | 1337 | || class == SP_OR_ADDRESS_REGS)) |
4d1a91c2 | 1338 | { |
705ac34f JL |
1339 | if (TARGET_AM33) |
1340 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1341 | return DATA_REGS; |
1342 | } | |
11bb1f11 JL |
1343 | |
1344 | /* We can't directly load sp + const_int into a data register; | |
1345 | we must use an address register as an intermediate. */ | |
777fbf09 JL |
1346 | if (class != SP_REGS |
1347 | && class != ADDRESS_REGS | |
1348 | && class != SP_OR_ADDRESS_REGS | |
705ac34f JL |
1349 | && class != SP_OR_EXTENDED_REGS |
1350 | && class != ADDRESS_OR_EXTENDED_REGS | |
1351 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
1352 | && (in == stack_pointer_rtx |
1353 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
1354 | && (XEXP (in, 0) == stack_pointer_rtx |
1355 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
1356 | return ADDRESS_REGS; |
1357 | ||
4c742813 JL |
1358 | if (GET_CODE (in) == PLUS |
1359 | && (XEXP (in, 0) == stack_pointer_rtx | |
1360 | || XEXP (in, 1) == stack_pointer_rtx)) | |
4d1a91c2 | 1361 | { |
705ac34f JL |
1362 | if (TARGET_AM33) |
1363 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1364 | return DATA_REGS; |
1365 | } | |
5abc5de9 | 1366 | |
18e9d2f9 | 1367 | if (TARGET_AM33_2 && class == FP_REGS |
5abc5de9 EC |
1368 | && GET_CODE (in) == MEM |
1369 | && ! (GET_CODE (in) == MEM && !CONSTANT_ADDRESS_P (XEXP (in, 0)))) | |
18e9d2f9 AO |
1370 | { |
1371 | if (TARGET_AM33) | |
1372 | return DATA_OR_EXTENDED_REGS; | |
1373 | return DATA_REGS; | |
1374 | } | |
1375 | ||
777fbf09 JL |
1376 | /* Otherwise assume no secondary reloads are needed. */ |
1377 | return NO_REGS; | |
1378 | } | |
1379 | ||
1380 | int | |
f1777882 | 1381 | initial_offset (int from, int to) |
777fbf09 | 1382 | { |
3dbc43d1 JL |
1383 | /* The difference between the argument pointer and the frame pointer |
1384 | is the size of the callee register save area. */ | |
777fbf09 | 1385 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 1386 | { |
6fb5fa3c DB |
1387 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1388 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1389 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1390 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1391 | || fp_regs_to_save () |
777fbf09 | 1392 | || frame_pointer_needed) |
18e9d2f9 AO |
1393 | return REG_SAVE_BYTES |
1394 | + 4 * fp_regs_to_save (); | |
777fbf09 | 1395 | else |
22ef4e9b | 1396 | return 0; |
11bb1f11 JL |
1397 | } |
1398 | ||
3dbc43d1 JL |
1399 | /* The difference between the argument pointer and the stack pointer is |
1400 | the sum of the size of this function's frame, the callee register save | |
1401 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
1402 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1403 | { | |
6fb5fa3c DB |
1404 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1405 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1406 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1407 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1408 | || fp_regs_to_save () |
777fbf09 | 1409 | || frame_pointer_needed) |
4d1a91c2 | 1410 | return (get_frame_size () + REG_SAVE_BYTES |
18e9d2f9 | 1411 | + 4 * fp_regs_to_save () |
460f4b9d | 1412 | + (current_function_outgoing_args_size |
5abc5de9 | 1413 | ? current_function_outgoing_args_size + 4 : 0)); |
777fbf09 | 1414 | else |
460f4b9d JL |
1415 | return (get_frame_size () |
1416 | + (current_function_outgoing_args_size | |
5abc5de9 | 1417 | ? current_function_outgoing_args_size + 4 : 0)); |
777fbf09 | 1418 | } |
11bb1f11 | 1419 | |
3dbc43d1 JL |
1420 | /* The difference between the frame pointer and stack pointer is the sum |
1421 | of the size of this function's frame and the fixed stack space needed | |
1422 | for function calls (if any). */ | |
777fbf09 | 1423 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d JL |
1424 | return (get_frame_size () |
1425 | + (current_function_outgoing_args_size | |
5abc5de9 | 1426 | ? current_function_outgoing_args_size + 4 : 0)); |
777fbf09 | 1427 | |
dc759020 | 1428 | gcc_unreachable (); |
11bb1f11 | 1429 | } |
22ef4e9b | 1430 | |
bd5bd7ac KH |
1431 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1432 | ||
9024ea92 | 1433 | static bool |
586de218 | 1434 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9024ea92 KH |
1435 | { |
1436 | /* Return values > 8 bytes in length in memory. */ | |
b1eb8119 DD |
1437 | return (int_size_in_bytes (type) > 8 |
1438 | || int_size_in_bytes (type) == 0 | |
1439 | || TYPE_MODE (type) == BLKmode); | |
9024ea92 KH |
1440 | } |
1441 | ||
22ef4e9b JL |
1442 | /* Flush the argument registers to the stack for a stdarg function; |
1443 | return the new argument pointer. */ | |
9024ea92 | 1444 | static rtx |
f1777882 | 1445 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1446 | { |
fc2acc87 | 1447 | rtx offset, mem; |
22ef4e9b JL |
1448 | tree fntype = TREE_TYPE (current_function_decl); |
1449 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
1450 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
1451 | != void_type_node))) | |
1452 | ? UNITS_PER_WORD : 0); | |
4862826d | 1453 | alias_set_type set = get_varargs_alias_set (); |
22ef4e9b JL |
1454 | |
1455 | if (argadj) | |
1456 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
1457 | else | |
1458 | offset = current_function_arg_offset_rtx; | |
1459 | ||
fc2acc87 | 1460 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ba4828e0 | 1461 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1462 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1463 | ||
1464 | mem = gen_rtx_MEM (SImode, | |
1465 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ba4828e0 | 1466 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1467 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1468 | ||
22ef4e9b JL |
1469 | return copy_to_reg (expand_binop (Pmode, add_optab, |
1470 | current_function_internal_arg_pointer, | |
1471 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
1472 | } | |
1473 | ||
fc2acc87 | 1474 | void |
f1777882 | 1475 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1476 | { |
6c535c69 | 1477 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1478 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1479 | } |
1480 | ||
8cd5a4e0 RH |
1481 | /* Return true when a parameter should be passed by reference. */ |
1482 | ||
1483 | static bool | |
1484 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
586de218 | 1485 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
1486 | bool named ATTRIBUTE_UNUSED) |
1487 | { | |
1488 | unsigned HOST_WIDE_INT size; | |
1489 | ||
1490 | if (type) | |
1491 | size = int_size_in_bytes (type); | |
1492 | else | |
1493 | size = GET_MODE_SIZE (mode); | |
1494 | ||
b1eb8119 | 1495 | return (size > 8 || size == 0); |
8cd5a4e0 RH |
1496 | } |
1497 | ||
22ef4e9b JL |
1498 | /* Return an RTX to represent where a value with mode MODE will be returned |
1499 | from a function. If the result is 0, the argument is pushed. */ | |
1500 | ||
1501 | rtx | |
f1777882 KH |
1502 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1503 | tree type, int named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1504 | { |
1505 | rtx result = 0; | |
1506 | int size, align; | |
1507 | ||
1508 | /* We only support using 2 data registers as argument registers. */ | |
1509 | int nregs = 2; | |
1510 | ||
1511 | /* Figure out the size of the object to be passed. */ | |
1512 | if (mode == BLKmode) | |
1513 | size = int_size_in_bytes (type); | |
1514 | else | |
1515 | size = GET_MODE_SIZE (mode); | |
1516 | ||
1517 | /* Figure out the alignment of the object to be passed. */ | |
1518 | align = size; | |
1519 | ||
1520 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1521 | ||
1522 | /* Don't pass this arg via a register if all the argument registers | |
1523 | are used up. */ | |
1524 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1525 | return 0; | |
1526 | ||
1527 | /* Don't pass this arg via a register if it would be split between | |
1528 | registers and memory. */ | |
1529 | if (type == NULL_TREE | |
1530 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1531 | return 0; | |
1532 | ||
1533 | switch (cum->nbytes / UNITS_PER_WORD) | |
1534 | { | |
1535 | case 0: | |
c5c76735 | 1536 | result = gen_rtx_REG (mode, 0); |
22ef4e9b JL |
1537 | break; |
1538 | case 1: | |
c5c76735 | 1539 | result = gen_rtx_REG (mode, 1); |
22ef4e9b JL |
1540 | break; |
1541 | default: | |
1542 | result = 0; | |
1543 | } | |
1544 | ||
1545 | return result; | |
1546 | } | |
1547 | ||
78a52f11 RH |
1548 | /* Return the number of bytes of registers to use for an argument passed |
1549 | partially in registers and partially in memory. */ | |
22ef4e9b | 1550 | |
78a52f11 RH |
1551 | static int |
1552 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1553 | tree type, bool named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1554 | { |
1555 | int size, align; | |
1556 | ||
1557 | /* We only support using 2 data registers as argument registers. */ | |
1558 | int nregs = 2; | |
1559 | ||
1560 | /* Figure out the size of the object to be passed. */ | |
1561 | if (mode == BLKmode) | |
1562 | size = int_size_in_bytes (type); | |
1563 | else | |
1564 | size = GET_MODE_SIZE (mode); | |
1565 | ||
1566 | /* Figure out the alignment of the object to be passed. */ | |
1567 | align = size; | |
1568 | ||
1569 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1570 | ||
1571 | /* Don't pass this arg via a register if all the argument registers | |
1572 | are used up. */ | |
1573 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1574 | return 0; | |
1575 | ||
1576 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1577 | return 0; | |
1578 | ||
1579 | /* Don't pass this arg via a register if it would be split between | |
1580 | registers and memory. */ | |
1581 | if (type == NULL_TREE | |
1582 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1583 | return 0; | |
1584 | ||
78a52f11 | 1585 | return nregs * UNITS_PER_WORD - cum->nbytes; |
22ef4e9b JL |
1586 | } |
1587 | ||
b1eb8119 DD |
1588 | /* Return the location of the function's value. This will be either |
1589 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1590 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1591 | we only return the PARALLEL for outgoing values; we do not want | |
1592 | callers relying on this extra copy. */ | |
1593 | ||
1594 | rtx | |
586de218 | 1595 | mn10300_function_value (const_tree valtype, const_tree func, int outgoing) |
b1eb8119 DD |
1596 | { |
1597 | rtx rv; | |
1598 | enum machine_mode mode = TYPE_MODE (valtype); | |
1599 | ||
1600 | if (! POINTER_TYPE_P (valtype)) | |
1601 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1602 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
1603 | || current_function_returns_struct) | |
1604 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); | |
1605 | ||
1606 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1607 | XVECEXP (rv, 0, 0) | |
1608 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1609 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1610 | GEN_INT (0)); | |
5abc5de9 | 1611 | |
b1eb8119 DD |
1612 | XVECEXP (rv, 0, 1) |
1613 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1614 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1615 | GEN_INT (0)); | |
1616 | return rv; | |
1617 | } | |
1618 | ||
22ef4e9b | 1619 | /* Output a tst insn. */ |
1943c2c1 | 1620 | const char * |
f1777882 | 1621 | output_tst (rtx operand, rtx insn) |
22ef4e9b | 1622 | { |
22ef4e9b JL |
1623 | rtx temp; |
1624 | int past_call = 0; | |
1625 | ||
1626 | /* We can save a byte if we can find a register which has the value | |
1627 | zero in it. */ | |
1628 | temp = PREV_INSN (insn); | |
74452ac3 | 1629 | while (optimize && temp) |
22ef4e9b JL |
1630 | { |
1631 | rtx set; | |
1632 | ||
1633 | /* We allow the search to go through call insns. We record | |
1634 | the fact that we've past a CALL_INSN and reject matches which | |
1635 | use call clobbered registers. */ | |
1636 | if (GET_CODE (temp) == CODE_LABEL | |
1637 | || GET_CODE (temp) == JUMP_INSN | |
1638 | || GET_CODE (temp) == BARRIER) | |
1639 | break; | |
1640 | ||
1641 | if (GET_CODE (temp) == CALL_INSN) | |
1642 | past_call = 1; | |
1643 | ||
1644 | if (GET_CODE (temp) == NOTE) | |
1645 | { | |
1646 | temp = PREV_INSN (temp); | |
1647 | continue; | |
1648 | } | |
1649 | ||
8596d0a1 | 1650 | /* It must be an insn, see if it is a simple set. */ |
22ef4e9b JL |
1651 | set = single_set (temp); |
1652 | if (!set) | |
1653 | { | |
1654 | temp = PREV_INSN (temp); | |
1655 | continue; | |
1656 | } | |
1657 | ||
1658 | /* Are we setting a data register to zero (this does not win for | |
5abc5de9 | 1659 | address registers)? |
22ef4e9b JL |
1660 | |
1661 | If it's a call clobbered register, have we past a call? | |
1662 | ||
1663 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1664 | the mn10300 can't encode that. |
1665 | ||
1666 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1667 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1668 | if (REG_P (SET_DEST (set)) |
1669 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1670 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1671 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1672 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1673 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1674 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
5abc5de9 | 1675 | && (!past_call |
705ac34f JL |
1676 | || !call_used_regs[REGNO (SET_DEST (set))])) |
1677 | { | |
1678 | rtx xoperands[2]; | |
1679 | xoperands[0] = operand; | |
1680 | xoperands[1] = SET_DEST (set); | |
1681 | ||
1682 | output_asm_insn ("cmp %1,%0", xoperands); | |
1683 | return ""; | |
1684 | } | |
1685 | ||
1686 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1687 | && REG_P (SET_DEST (set)) | |
1688 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1689 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1690 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1691 | != REGNO_REG_CLASS (REGNO (operand))) | |
1692 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b | 1693 | && REGNO (SET_DEST (set)) != REGNO (operand) |
5abc5de9 | 1694 | && (!past_call |
22ef4e9b JL |
1695 | || !call_used_regs[REGNO (SET_DEST (set))])) |
1696 | { | |
1697 | rtx xoperands[2]; | |
1698 | xoperands[0] = operand; | |
1699 | xoperands[1] = SET_DEST (set); | |
1700 | ||
1701 | output_asm_insn ("cmp %1,%0", xoperands); | |
1702 | return ""; | |
1703 | } | |
1704 | temp = PREV_INSN (temp); | |
1705 | } | |
1706 | return "cmp 0,%0"; | |
1707 | } | |
460f4b9d JL |
1708 | |
1709 | int | |
f1777882 | 1710 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
460f4b9d | 1711 | { |
460f4b9d JL |
1712 | if (GET_CODE (op) != PLUS) |
1713 | return 0; | |
1714 | ||
4c742813 JL |
1715 | if (XEXP (op, 0) == stack_pointer_rtx |
1716 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
1717 | return 1; |
1718 | ||
460f4b9d JL |
1719 | return 0; |
1720 | } | |
e9ad4573 | 1721 | |
f8912297 JL |
1722 | /* Similarly, but when using a zero_extract pattern for a btst where |
1723 | the source operand might end up in memory. */ | |
1724 | int | |
f1777882 | 1725 | mask_ok_for_mem_btst (int len, int bit) |
f8912297 | 1726 | { |
4977bab6 | 1727 | unsigned int mask = 0; |
f8912297 JL |
1728 | |
1729 | while (len > 0) | |
1730 | { | |
1731 | mask |= (1 << bit); | |
1732 | bit++; | |
1733 | len--; | |
1734 | } | |
1735 | ||
1736 | /* MASK must bit into an 8bit value. */ | |
1737 | return (((mask & 0xff) == mask) | |
1738 | || ((mask & 0xff00) == mask) | |
1739 | || ((mask & 0xff0000) == mask) | |
1740 | || ((mask & 0xff000000) == mask)); | |
1741 | } | |
1742 | ||
e9ad4573 JL |
1743 | /* Return 1 if X contains a symbolic expression. We know these |
1744 | expressions will have one of a few well defined forms, so | |
1745 | we need only check those forms. */ | |
1746 | int | |
f1777882 | 1747 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e9ad4573 JL |
1748 | { |
1749 | switch (GET_CODE (op)) | |
1750 | { | |
1751 | case SYMBOL_REF: | |
1752 | case LABEL_REF: | |
1753 | return 1; | |
1754 | case CONST: | |
1755 | op = XEXP (op, 0); | |
1756 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1757 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1758 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1759 | default: | |
1760 | return 0; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | /* Try machine dependent ways of modifying an illegitimate address | |
1765 | to be legitimate. If we find one, return the new valid address. | |
1766 | This macro is used in only one place: `memory_address' in explow.c. | |
1767 | ||
1768 | OLDX is the address as it was before break_out_memory_refs was called. | |
1769 | In some cases it is useful to look at this to decide what needs to be done. | |
1770 | ||
1771 | MODE and WIN are passed so that this macro can use | |
1772 | GO_IF_LEGITIMATE_ADDRESS. | |
1773 | ||
1774 | Normally it is always safe for this macro to do nothing. It exists to | |
1775 | recognize opportunities to optimize the output. | |
1776 | ||
1777 | But on a few ports with segmented architectures and indexed addressing | |
1778 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1779 | rtx | |
f1777882 KH |
1780 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1781 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1782 | { |
d1776069 AO |
1783 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1784 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1785 | ||
e9ad4573 JL |
1786 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1787 | special handling to avoid creating an indexed memory address | |
1788 | with x-100000 as the base. */ | |
1789 | if (GET_CODE (x) == PLUS | |
1790 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1791 | { | |
1792 | /* Ugly. We modify things here so that the address offset specified | |
1793 | by the index expression is computed first, then added to x to form | |
1794 | the entire address. */ | |
1795 | ||
69bc71fa | 1796 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1797 | |
1798 | /* Strip off any CONST. */ | |
1799 | y = XEXP (x, 1); | |
1800 | if (GET_CODE (y) == CONST) | |
1801 | y = XEXP (y, 0); | |
1802 | ||
bf4219f0 JL |
1803 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1804 | { | |
1805 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1806 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1807 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1808 | regx1 = force_reg (Pmode, | |
1c563bed | 1809 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2)); |
c5c76735 | 1810 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1811 | } |
e9ad4573 | 1812 | } |
371036e0 | 1813 | return x; |
e9ad4573 | 1814 | } |
460ad325 | 1815 | |
d1776069 | 1816 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1817 | @GOTOFF in `reg'. */ |
d1776069 | 1818 | rtx |
f1777882 | 1819 | legitimize_pic_address (rtx orig, rtx reg) |
d1776069 AO |
1820 | { |
1821 | if (GET_CODE (orig) == LABEL_REF | |
1822 | || (GET_CODE (orig) == SYMBOL_REF | |
1823 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1824 | || ! MN10300_GLOBAL_P (orig)))) | |
1825 | { | |
1826 | if (reg == 0) | |
1827 | reg = gen_reg_rtx (Pmode); | |
1828 | ||
1829 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1830 | return reg; | |
1831 | } | |
1832 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1833 | { | |
1834 | if (reg == 0) | |
1835 | reg = gen_reg_rtx (Pmode); | |
1836 | ||
1837 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1838 | return reg; | |
1839 | } | |
1840 | return orig; | |
1841 | } | |
1842 | ||
1843 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1844 | isn't protected by a PIC unspec; nonzero otherwise. */ |
d1776069 | 1845 | int |
f1777882 | 1846 | legitimate_pic_operand_p (rtx x) |
d1776069 AO |
1847 | { |
1848 | register const char *fmt; | |
1849 | register int i; | |
1850 | ||
1851 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1852 | return 0; | |
1853 | ||
1854 | if (GET_CODE (x) == UNSPEC | |
1855 | && (XINT (x, 1) == UNSPEC_PIC | |
1856 | || XINT (x, 1) == UNSPEC_GOT | |
1857 | || XINT (x, 1) == UNSPEC_GOTOFF | |
1858 | || XINT (x, 1) == UNSPEC_PLT)) | |
1859 | return 1; | |
1860 | ||
d1776069 AO |
1861 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1862 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1863 | { | |
1864 | if (fmt[i] == 'E') | |
1865 | { | |
1866 | register int j; | |
1867 | ||
1868 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1869 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1870 | return 0; | |
1871 | } | |
1872 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | return 1; | |
1877 | } | |
1878 | ||
e733134f AO |
1879 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
1880 | legitimate, and FALSE otherwise. */ | |
1881 | bool | |
1882 | legitimate_address_p (enum machine_mode mode, rtx x, int strict) | |
1883 | { | |
1884 | if (CONSTANT_ADDRESS_P (x) | |
1885 | && (! flag_pic || legitimate_pic_operand_p (x))) | |
1886 | return TRUE; | |
1887 | ||
1888 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1889 | return TRUE; | |
1890 | ||
1891 | if (TARGET_AM33 | |
1892 | && GET_CODE (x) == POST_INC | |
1893 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1894 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1895 | return TRUE; | |
1896 | ||
1897 | if (GET_CODE (x) == PLUS) | |
1898 | { | |
1899 | rtx base = 0, index = 0; | |
1900 | ||
1901 | if (REG_P (XEXP (x, 0)) | |
1902 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1903 | { | |
1904 | base = XEXP (x, 0); | |
1905 | index = XEXP (x, 1); | |
1906 | } | |
1907 | ||
1908 | if (REG_P (XEXP (x, 1)) | |
1909 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1910 | { | |
1911 | base = XEXP (x, 1); | |
1912 | index = XEXP (x, 0); | |
1913 | } | |
1914 | ||
1915 | if (base != 0 && index != 0) | |
1916 | { | |
1917 | if (GET_CODE (index) == CONST_INT) | |
1918 | return TRUE; | |
1919 | if (GET_CODE (index) == CONST | |
5542b23d | 1920 | && GET_CODE (XEXP (index, 0)) != PLUS |
e733134f AO |
1921 | && (! flag_pic |
1922 | || legitimate_pic_operand_p (index))) | |
1923 | return TRUE; | |
1924 | } | |
1925 | } | |
1926 | ||
1927 | return FALSE; | |
1928 | } | |
1929 | ||
dcefdf67 | 1930 | static int |
f1777882 | 1931 | mn10300_address_cost_1 (rtx x, int *unsig) |
460ad325 | 1932 | { |
460ad325 AO |
1933 | switch (GET_CODE (x)) |
1934 | { | |
1935 | case REG: | |
1936 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1937 | { | |
1938 | case SP_REGS: | |
1939 | *unsig = 1; | |
1940 | return 0; | |
1941 | ||
1942 | case ADDRESS_REGS: | |
1943 | return 1; | |
1944 | ||
1945 | case DATA_REGS: | |
1946 | case EXTENDED_REGS: | |
18e9d2f9 | 1947 | case FP_REGS: |
460ad325 AO |
1948 | return 3; |
1949 | ||
1950 | case NO_REGS: | |
1951 | return 5; | |
1952 | ||
1953 | default: | |
dc759020 | 1954 | gcc_unreachable (); |
460ad325 AO |
1955 | } |
1956 | ||
1957 | case PLUS: | |
1958 | case MINUS: | |
d82704fb AO |
1959 | case ASHIFT: |
1960 | case AND: | |
460ad325 | 1961 | case IOR: |
dcefdf67 RH |
1962 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1963 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
460ad325 AO |
1964 | |
1965 | case EXPR_LIST: | |
1966 | case SUBREG: | |
1967 | case MEM: | |
dcefdf67 | 1968 | return mn10300_address_cost (XEXP (x, 0)); |
460ad325 AO |
1969 | |
1970 | case ZERO_EXTEND: | |
1971 | *unsig = 1; | |
dcefdf67 | 1972 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
460ad325 AO |
1973 | |
1974 | case CONST_INT: | |
1975 | if (INTVAL (x) == 0) | |
1976 | return 0; | |
1977 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1978 | return 1; | |
1979 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1980 | return 3; | |
1981 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1982 | return 5; | |
1983 | return 7; | |
1984 | ||
1985 | case CONST: | |
1986 | case SYMBOL_REF: | |
d82704fb | 1987 | case LABEL_REF: |
460ad325 AO |
1988 | return 8; |
1989 | ||
460ad325 | 1990 | default: |
dc759020 | 1991 | gcc_unreachable (); |
460ad325 AO |
1992 | |
1993 | } | |
1994 | } | |
3c50106f | 1995 | |
dcefdf67 | 1996 | static int |
f1777882 | 1997 | mn10300_address_cost (rtx x) |
dcefdf67 RH |
1998 | { |
1999 | int s = 0; | |
2000 | return mn10300_address_cost_1 (x, &s); | |
2001 | } | |
2002 | ||
3c50106f | 2003 | static bool |
f1777882 | 2004 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
2005 | { |
2006 | switch (code) | |
2007 | { | |
2008 | case CONST_INT: | |
2009 | /* Zeros are extremely cheap. */ | |
2010 | if (INTVAL (x) == 0 && outer_code == SET) | |
2011 | *total = 0; | |
2012 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
2013 | else if (INT_8_BITS (INTVAL (x))) | |
2014 | *total = 1; | |
2015 | /* This is the "base" cost, includes constants where either the | |
2016 | upper or lower 16bits are all zeros. */ | |
2017 | else if (INT_16_BITS (INTVAL (x)) | |
2018 | || (INTVAL (x) & 0xffff) == 0 | |
2019 | || (INTVAL (x) & 0xffff0000) == 0) | |
2020 | *total = 2; | |
2021 | else | |
2022 | *total = 4; | |
2023 | return true; | |
2024 | ||
2025 | case CONST: | |
2026 | case LABEL_REF: | |
2027 | case SYMBOL_REF: | |
2028 | /* These are more costly than a CONST_INT, but we can relax them, | |
2029 | so they're less costly than a CONST_DOUBLE. */ | |
2030 | *total = 6; | |
2031 | return true; | |
2032 | ||
2033 | case CONST_DOUBLE: | |
2034 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2035 | so their cost is very high. */ | |
2036 | *total = 8; | |
2037 | return true; | |
2038 | ||
2039 | /* ??? This probably needs more work. */ | |
2040 | case MOD: | |
2041 | case DIV: | |
2042 | case MULT: | |
2043 | *total = 8; | |
2044 | return true; | |
2045 | ||
2046 | default: | |
2047 | return false; | |
2048 | } | |
2049 | } | |
fe7496dd AO |
2050 | |
2051 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2052 | use a clr instruction. The code here must be kept in sync with | |
2053 | movdf and movdi. */ | |
2054 | ||
2055 | bool | |
f1777882 | 2056 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
fe7496dd AO |
2057 | { |
2058 | long val[2]; | |
2059 | ||
2060 | if (GET_CODE (operands[0]) != REG | |
2061 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
2062 | return false; | |
2063 | ||
2064 | switch (GET_CODE (operands[1])) | |
2065 | { | |
2066 | case CONST_INT: | |
2067 | { | |
2068 | rtx low, high; | |
2069 | split_double (operands[1], &low, &high); | |
2070 | val[0] = INTVAL (low); | |
2071 | val[1] = INTVAL (high); | |
2072 | } | |
2073 | break; | |
5abc5de9 | 2074 | |
fe7496dd AO |
2075 | case CONST_DOUBLE: |
2076 | if (GET_MODE (operands[1]) == DFmode) | |
2077 | { | |
2078 | REAL_VALUE_TYPE rv; | |
2079 | ||
2080 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2081 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2082 | } | |
2083 | else if (GET_MODE (operands[1]) == VOIDmode | |
2084 | || GET_MODE (operands[1]) == DImode) | |
2085 | { | |
2086 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2087 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2088 | } | |
2089 | break; | |
5abc5de9 | 2090 | |
fe7496dd AO |
2091 | default: |
2092 | return false; | |
2093 | } | |
2094 | ||
2095 | return val[0] == 0 || val[1] == 0; | |
2096 | } | |
d1776069 AO |
2097 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2098 | may access it using GOTOFF instead of GOT. */ | |
2099 | ||
2100 | static void | |
3bc5e4ef | 2101 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
d1776069 AO |
2102 | { |
2103 | rtx symbol; | |
2104 | ||
2105 | if (GET_CODE (rtl) != MEM) | |
2106 | return; | |
2107 | symbol = XEXP (rtl, 0); | |
2108 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2109 | return; | |
2110 | ||
2111 | if (flag_pic) | |
2112 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2113 | } |