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d79df659 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
aad93da1 | 2 | Copyright (C) 1992-2017 Free Software Foundation, Inc. |
7e2cdc14 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
d79df659 | 4 | |
3a5a28e2 | 5 | This file is part of GCC. |
d79df659 | 6 | |
3a5a28e2 | 7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
038d1e19 | 9 | by the Free Software Foundation; either version 3, or (at your |
3a5a28e2 | 10 | option) any later version. |
d79df659 | 11 | |
3a5a28e2 | 12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
d79df659 | 16 | |
6bc9506f | 17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
038d1e19 | 24 | <http://www.gnu.org/licenses/>. */ |
d79df659 | 25 | |
26 | /* Note that some other tm.h files include this one and then override | |
bbd21807 | 27 | many of the definitions. */ |
d79df659 | 28 | |
755fa783 | 29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
bbd21807 | 33 | /* Definitions for the object file format. These are set at |
34 | compile-time. */ | |
d79df659 | 35 | |
bbd21807 | 36 | #define OBJECT_XCOFF 1 |
37 | #define OBJECT_ELF 2 | |
38 | #define OBJECT_PEF 3 | |
80d725d7 | 39 | #define OBJECT_MACHO 4 |
d79df659 | 40 | |
bbd21807 | 41 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
8eaf2dd1 | 42 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
bbd21807 | 43 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
80d725d7 | 44 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
d79df659 | 45 | |
8eaf2dd1 | 46 | #ifndef TARGET_AIX |
47 | #define TARGET_AIX 0 | |
48 | #endif | |
49 | ||
904080f9 | 50 | #ifndef TARGET_AIX_OS |
51 | #define TARGET_AIX_OS 0 | |
52 | #endif | |
53 | ||
66ebfa67 | 54 | /* Control whether function entry points use a "dot" symbol when |
55 | ABI_AIX. */ | |
56 | #define DOT_SYMBOLS 1 | |
57 | ||
2c3f5685 | 58 | /* Default string to use for cpu if not specified. */ |
59 | #ifndef TARGET_CPU_DEFAULT | |
60 | #define TARGET_CPU_DEFAULT ((char *)0) | |
61 | #endif | |
62 | ||
44cb69ff | 63 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
e2fcf81b | 64 | #ifdef CONFIG_PPC405CR |
44cb69ff | 65 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
66 | #else | |
67 | #define PPC405_ERRATUM77 0 | |
68 | #endif | |
69 | ||
a9de045e | 70 | #ifndef TARGET_PAIRED_FLOAT |
71 | #define TARGET_PAIRED_FLOAT 0 | |
72 | #endif | |
73 | ||
b30c4a87 | 74 | #ifdef HAVE_AS_POPCNTB |
75 | #define ASM_CPU_POWER5_SPEC "-mpower5" | |
76 | #else | |
77 | #define ASM_CPU_POWER5_SPEC "-mpower4" | |
78 | #endif | |
79 | ||
80 | #ifdef HAVE_AS_DFP | |
81 | #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
82 | #else | |
83 | #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
84 | #endif | |
85 | ||
9c878e1b | 86 | #ifdef HAVE_AS_POPCNTD |
94f7a54b | 87 | #define ASM_CPU_POWER7_SPEC "-mpower7" |
88 | #else | |
89 | #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
90 | #endif | |
91 | ||
721599fd | 92 | #ifdef HAVE_AS_POWER8 |
93 | #define ASM_CPU_POWER8_SPEC "-mpower8" | |
94 | #else | |
81f0e7d0 | 95 | #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC |
721599fd | 96 | #endif |
97 | ||
a875ad2e | 98 | #ifdef HAVE_AS_POWER9 |
99 | #define ASM_CPU_POWER9_SPEC "-mpower9" | |
100 | #else | |
101 | #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC | |
102 | #endif | |
103 | ||
ed08558a | 104 | #ifdef HAVE_AS_DCI |
105 | #define ASM_CPU_476_SPEC "-m476" | |
106 | #else | |
107 | #define ASM_CPU_476_SPEC "-mpower4" | |
108 | #endif | |
109 | ||
9c878e1b | 110 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
111 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to | |
112 | provide the default assembler options if the user uses -mcpu=native, so if | |
113 | you make changes here, make them also there. */ | |
6beea24d | 114 | #define ASM_CPU_SPEC \ |
115 | "%{!mcpu*: \ | |
8e69e3da | 116 | %{mpowerpc64*: -mppc64} \ |
34c34d94 | 117 | %{!mpowerpc64*: %(asm_default)}} \ |
9c878e1b | 118 | %{mcpu=native: %(asm_cpu_native)} \ |
cd21f4e0 | 119 | %{mcpu=cell: -mcell} \ |
8e69e3da | 120 | %{mcpu=power3: -mppc64} \ |
42d6c9f5 | 121 | %{mcpu=power4: -mpower4} \ |
b30c4a87 | 122 | %{mcpu=power5: %(asm_cpu_power5)} \ |
123 | %{mcpu=power5+: %(asm_cpu_power5)} \ | |
124 | %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
125 | %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
94f7a54b | 126 | %{mcpu=power7: %(asm_cpu_power7)} \ |
721599fd | 127 | %{mcpu=power8: %(asm_cpu_power8)} \ |
a875ad2e | 128 | %{mcpu=power9: %(asm_cpu_power9)} \ |
80c8ed02 | 129 | %{mcpu=a2: -ma2} \ |
6beea24d | 130 | %{mcpu=powerpc: -mppc} \ |
08f4e8e8 | 131 | %{mcpu=powerpc64le: %(asm_cpu_power8)} \ |
8e69e3da | 132 | %{mcpu=rs64a: -mppc64} \ |
6beea24d | 133 | %{mcpu=401: -mppc} \ |
f9557322 | 134 | %{mcpu=403: -m403} \ |
135 | %{mcpu=405: -m405} \ | |
d147888d | 136 | %{mcpu=405fp: -m405} \ |
137 | %{mcpu=440: -m440} \ | |
138 | %{mcpu=440fp: -m440} \ | |
257bc844 | 139 | %{mcpu=464: -m440} \ |
140 | %{mcpu=464fp: -m440} \ | |
ed08558a | 141 | %{mcpu=476: %(asm_cpu_476)} \ |
142 | %{mcpu=476fp: %(asm_cpu_476)} \ | |
6beea24d | 143 | %{mcpu=505: -mppc} \ |
144 | %{mcpu=601: -m601} \ | |
145 | %{mcpu=602: -mppc} \ | |
146 | %{mcpu=603: -mppc} \ | |
147 | %{mcpu=603e: -mppc} \ | |
148 | %{mcpu=ec603e: -mppc} \ | |
149 | %{mcpu=604: -mppc} \ | |
150 | %{mcpu=604e: -mppc} \ | |
8e69e3da | 151 | %{mcpu=620: -mppc64} \ |
152 | %{mcpu=630: -mppc64} \ | |
6beea24d | 153 | %{mcpu=740: -mppc} \ |
154 | %{mcpu=750: -mppc} \ | |
2cbae4d7 | 155 | %{mcpu=G3: -mppc} \ |
8e69e3da | 156 | %{mcpu=7400: -mppc -maltivec} \ |
157 | %{mcpu=7450: -mppc -maltivec} \ | |
158 | %{mcpu=G4: -mppc -maltivec} \ | |
6beea24d | 159 | %{mcpu=801: -mppc} \ |
160 | %{mcpu=821: -mppc} \ | |
161 | %{mcpu=823: -mppc} \ | |
77c46d92 | 162 | %{mcpu=860: -mppc} \ |
8e69e3da | 163 | %{mcpu=970: -mpower4 -maltivec} \ |
164 | %{mcpu=G5: -mpower4 -maltivec} \ | |
f19493d5 | 165 | %{mcpu=8540: -me500} \ |
1dd6dd88 | 166 | %{mcpu=8548: -me500} \ |
73edc44b | 167 | %{mcpu=e300c2: -me300} \ |
168 | %{mcpu=e300c3: -me300} \ | |
2b3ae3ef | 169 | %{mcpu=e500mc: -me500mc} \ |
20d6e0e0 | 170 | %{mcpu=e500mc64: -me500mc64} \ |
b770074c | 171 | %{mcpu=e5500: -me5500} \ |
172 | %{mcpu=e6500: -me6500} \ | |
8e69e3da | 173 | %{maltivec: -maltivec} \ |
587d8e9f | 174 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
5088e479 | 175 | %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ |
8e69e3da | 176 | -many" |
6beea24d | 177 | |
178 | #define CPP_DEFAULT_SPEC "" | |
179 | ||
180 | #define ASM_DEFAULT_SPEC "" | |
181 | ||
8b351d3c | 182 | /* This macro defines names of additional specifications to put in the specs |
183 | that can be used in various specifications like CC1_SPEC. Its definition | |
184 | is an initializer with a subgrouping for each command option. | |
185 | ||
186 | Each subgrouping contains a string constant, that defines the | |
3a5a28e2 | 187 | specification name, and a string constant that used by the GCC driver |
8b351d3c | 188 | program. |
189 | ||
190 | Do not define this macro if it does not need to do anything. */ | |
191 | ||
7a2fc9d6 | 192 | #define SUBTARGET_EXTRA_SPECS |
7a2fc9d6 | 193 | |
a91f63e4 | 194 | #define EXTRA_SPECS \ |
a91f63e4 | 195 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
a91f63e4 | 196 | { "asm_cpu", ASM_CPU_SPEC }, \ |
9c878e1b | 197 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
a91f63e4 | 198 | { "asm_default", ASM_DEFAULT_SPEC }, \ |
7cfb6ab6 | 199 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
b30c4a87 | 200 | { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ |
201 | { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
94f7a54b | 202 | { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ |
721599fd | 203 | { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ |
a875ad2e | 204 | { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \ |
ed08558a | 205 | { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
7a2fc9d6 | 206 | SUBTARGET_EXTRA_SPECS |
207 | ||
7cfb6ab6 | 208 | /* -mcpu=native handling only makes sense with compiler running on |
209 | an PowerPC chip. If changing this condition, also change | |
210 | the condition in driver-rs6000.c. */ | |
211 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
212 | /* In driver-rs6000.c. */ | |
213 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
214 | #define EXTRA_SPEC_FUNCTIONS \ | |
215 | { "local_cpu_detect", host_detect_local_cpu }, | |
216 | #define HAVE_LOCAL_CPU_DETECT | |
9c878e1b | 217 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
218 | ||
219 | #else | |
220 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
7cfb6ab6 | 221 | #endif |
222 | ||
26ac30e1 | 223 | #ifndef CC1_CPU_SPEC |
224 | #ifdef HAVE_LOCAL_CPU_DETECT | |
7cfb6ab6 | 225 | #define CC1_CPU_SPEC \ |
226 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
227 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
26ac30e1 | 228 | #else |
229 | #define CC1_CPU_SPEC "" | |
230 | #endif | |
7cfb6ab6 | 231 | #endif |
232 | ||
7e1099c3 | 233 | /* Architecture type. */ |
d79df659 | 234 | |
6414dd4c | 235 | /* Define TARGET_MFCRF if the target assembler does not support the |
16ac04e7 | 236 | optional field operand for mfcr. */ |
7e1099c3 | 237 | |
16ac04e7 | 238 | #ifndef HAVE_AS_MFCRF |
a8bb341c | 239 | #undef TARGET_MFCRF |
876ae45a | 240 | #define TARGET_MFCRF 0 |
241 | #endif | |
242 | ||
442e3cb9 | 243 | /* Define TARGET_POPCNTB if the target assembler does not support the |
a8bb341c | 244 | popcount byte instruction. */ |
245 | ||
246 | #ifndef HAVE_AS_POPCNTB | |
247 | #undef TARGET_POPCNTB | |
248 | #define TARGET_POPCNTB 0 | |
249 | #endif | |
250 | ||
a6018579 | 251 | /* Define TARGET_FPRND if the target assembler does not support the |
252 | fp rounding instructions. */ | |
253 | ||
254 | #ifndef HAVE_AS_FPRND | |
255 | #undef TARGET_FPRND | |
256 | #define TARGET_FPRND 0 | |
257 | #endif | |
258 | ||
3230b740 | 259 | /* Define TARGET_CMPB if the target assembler does not support the |
260 | cmpb instruction. */ | |
261 | ||
262 | #ifndef HAVE_AS_CMPB | |
263 | #undef TARGET_CMPB | |
264 | #define TARGET_CMPB 0 | |
265 | #endif | |
266 | ||
c15fcd1f | 267 | /* Define TARGET_MFPGPR if the target assembler does not support the |
268 | mffpr and mftgpr instructions. */ | |
269 | ||
270 | #ifndef HAVE_AS_MFPGPR | |
271 | #undef TARGET_MFPGPR | |
272 | #define TARGET_MFPGPR 0 | |
273 | #endif | |
274 | ||
3230b740 | 275 | /* Define TARGET_DFP if the target assembler does not support decimal |
276 | floating point instructions. */ | |
277 | #ifndef HAVE_AS_DFP | |
278 | #undef TARGET_DFP | |
279 | #define TARGET_DFP 0 | |
280 | #endif | |
281 | ||
9c878e1b | 282 | /* Define TARGET_POPCNTD if the target assembler does not support the |
283 | popcount word and double word instructions. */ | |
284 | ||
285 | #ifndef HAVE_AS_POPCNTD | |
286 | #undef TARGET_POPCNTD | |
287 | #define TARGET_POPCNTD 0 | |
288 | #endif | |
289 | ||
81f0e7d0 | 290 | /* Define the ISA 2.07 flags as 0 if the target assembler does not support the |
291 | waitasecond instruction. Allow -mpower8-fusion, since it does not add new | |
292 | instructions. */ | |
293 | ||
294 | #ifndef HAVE_AS_POWER8 | |
295 | #undef TARGET_DIRECT_MOVE | |
296 | #undef TARGET_CRYPTO | |
5088e479 | 297 | #undef TARGET_HTM |
81f0e7d0 | 298 | #undef TARGET_P8_VECTOR |
299 | #define TARGET_DIRECT_MOVE 0 | |
300 | #define TARGET_CRYPTO 0 | |
5088e479 | 301 | #define TARGET_HTM 0 |
81f0e7d0 | 302 | #define TARGET_P8_VECTOR 0 |
303 | #endif | |
304 | ||
a6f93fc2 | 305 | /* Define the ISA 3.0 flags as 0 if the target assembler does not support |
306 | Power9 instructions. Allow -mpower9-fusion, since it does not add new | |
307 | instructions. Allow -misel, since it predates ISA 3.0 and does | |
308 | not require any Power9 features. */ | |
309 | ||
310 | #ifndef HAVE_AS_POWER9 | |
311 | #undef TARGET_FLOAT128_HW | |
312 | #undef TARGET_MODULO | |
313 | #undef TARGET_P9_VECTOR | |
314 | #undef TARGET_P9_MINMAX | |
17c32c4a | 315 | #undef TARGET_P9_MISC |
a6f93fc2 | 316 | #define TARGET_FLOAT128_HW 0 |
317 | #define TARGET_MODULO 0 | |
318 | #define TARGET_P9_VECTOR 0 | |
319 | #define TARGET_P9_MINMAX 0 | |
17c32c4a | 320 | #define TARGET_P9_MISC 0 |
a6f93fc2 | 321 | #endif |
322 | ||
9c878e1b | 323 | /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If |
324 | not, generate the lwsync code as an integer constant. */ | |
325 | #ifdef HAVE_AS_LWSYNC | |
326 | #define TARGET_LWSYNC_INSTRUCTION 1 | |
327 | #else | |
328 | #define TARGET_LWSYNC_INSTRUCTION 0 | |
329 | #endif | |
330 | ||
d46ea878 | 331 | /* Define TARGET_TLS_MARKERS if the target assembler does not support |
332 | arg markers for __tls_get_addr calls. */ | |
333 | #ifndef HAVE_AS_TLS_MARKERS | |
334 | #undef TARGET_TLS_MARKERS | |
335 | #define TARGET_TLS_MARKERS 0 | |
336 | #else | |
337 | #define TARGET_TLS_MARKERS tls_markers | |
338 | #endif | |
339 | ||
197f58fa | 340 | #ifndef TARGET_SECURE_PLT |
341 | #define TARGET_SECURE_PLT 0 | |
342 | #endif | |
343 | ||
72350d7b | 344 | #ifndef TARGET_CMODEL |
345 | #define TARGET_CMODEL CMODEL_SMALL | |
346 | #endif | |
347 | ||
4086c37e | 348 | #define TARGET_32BIT (! TARGET_64BIT) |
4ba5d6c4 | 349 | |
9b552c45 | 350 | #ifndef HAVE_AS_TLS |
351 | #define HAVE_AS_TLS 0 | |
352 | #endif | |
353 | ||
fef79628 | 354 | #ifndef TARGET_LINK_STACK |
355 | #define TARGET_LINK_STACK 0 | |
356 | #endif | |
357 | ||
358 | #ifndef SET_TARGET_LINK_STACK | |
359 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
360 | #endif | |
361 | ||
7d29bba9 | 362 | #ifndef TARGET_FLOAT128_ENABLE_TYPE |
363 | #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
364 | #endif | |
365 | ||
91141d39 | 366 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
367 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
368 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
369 | ||
cf378360 | 370 | #ifdef IN_LIBGCC2 |
371 | /* For libgcc2 we make sure this is a compile time constant */ | |
23e97733 | 372 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
16ac04e7 | 373 | #undef TARGET_POWERPC64 |
cf378360 | 374 | #define TARGET_POWERPC64 1 |
375 | #else | |
16ac04e7 | 376 | #undef TARGET_POWERPC64 |
cf378360 | 377 | #define TARGET_POWERPC64 0 |
378 | #endif | |
6b02f2a5 | 379 | #else |
16ac04e7 | 380 | /* The option machinery will define this. */ |
6b02f2a5 | 381 | #endif |
382 | ||
55920223 | 383 | #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) |
bbd21807 | 384 | |
3f5debcf | 385 | /* FPU operations supported. |
386 | Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
387 | also test TARGET_HARD_FLOAT. */ | |
388 | #define TARGET_SINGLE_FLOAT 1 | |
389 | #define TARGET_DOUBLE_FLOAT 1 | |
390 | #define TARGET_SINGLE_FPU 0 | |
391 | #define TARGET_SIMPLE_FPU 0 | |
303906c1 | 392 | #define TARGET_XILINX_FPU 0 |
3f5debcf | 393 | |
7e1099c3 | 394 | /* Recast the processor type to the cpu attribute. */ |
395 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
396 | ||
e1c37a86 | 397 | /* Define generic processor types based upon current deployment. */ |
91452706 | 398 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
91452706 | 399 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
400 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
e81f42fe | 401 | |
7e1099c3 | 402 | /* Define the default processor. This is overridden by other tm.h files. */ |
01eb32e7 | 403 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
91452706 | 404 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
7e1099c3 | 405 | |
18163dd8 | 406 | /* Specify the dialect of assembler to use. Only new mnemonics are supported |
407 | starting with GCC 4.8, i.e. just one dialect, but for backwards | |
408 | compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
409 | defined. */ | |
410 | #define ASSEMBLER_DIALECT 1 | |
411 | ||
bda6fa4d | 412 | /* Debug support */ |
755fa783 | 413 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
414 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
415 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
416 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
417 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
418 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
0375b229 | 419 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
755fa783 | 420 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
421 | | MASK_DEBUG_ARG \ | |
422 | | MASK_DEBUG_REG \ | |
423 | | MASK_DEBUG_ADDR \ | |
424 | | MASK_DEBUG_COST \ | |
0375b229 | 425 | | MASK_DEBUG_TARGET \ |
426 | | MASK_DEBUG_BUILTIN) | |
755fa783 | 427 | |
428 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
429 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
430 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
431 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
432 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
433 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
0375b229 | 434 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
9c878e1b | 435 | |
8b2f7251 | 436 | /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM |
437 | long double format that uses a pair of doubles, or IEEE 128-bit floating | |
438 | point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
439 | even if the default for long double is the IBM long double format. | |
440 | Similarly IFmode is the IBM long double format even if the default is IEEE | |
ba1e3b8f | 441 | 128-bit. Don't allow IFmode if -msoft-float. */ |
8b2f7251 | 442 | #define FLOAT128_IEEE_P(MODE) \ |
3c62cae0 | 443 | ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ |
444 | || ((MODE) == KFmode) || ((MODE) == KCmode)) | |
8b2f7251 | 445 | |
446 | #define FLOAT128_IBM_P(MODE) \ | |
3c62cae0 | 447 | ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ |
df8015ff | 448 | || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) |
8b2f7251 | 449 | |
450 | /* Helper macros to say whether a 128-bit floating point type can go in a | |
451 | single vector register, or whether it needs paired scalar values. */ | |
7d29bba9 | 452 | #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) |
8b2f7251 | 453 | |
454 | #define FLOAT128_2REG_P(MODE) \ | |
455 | (FLOAT128_IBM_P (MODE) \ | |
456 | || ((MODE) == TDmode) \ | |
7d29bba9 | 457 | || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) |
8b2f7251 | 458 | |
459 | /* Return true for floating point that does not use a vector register. */ | |
460 | #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
461 | (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
462 | ||
81f0e7d0 | 463 | /* Describe the vector unit used for arithmetic operations. */ |
9c878e1b | 464 | extern enum rs6000_vector rs6000_vector_unit[]; |
465 | ||
466 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
467 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
468 | ||
469 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
470 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
471 | ||
81f0e7d0 | 472 | #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
473 | (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
474 | ||
9c878e1b | 475 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
476 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
477 | ||
81f0e7d0 | 478 | #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
479 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
480 | (int)VECTOR_VSX, \ | |
481 | (int)VECTOR_P8_VECTOR)) | |
482 | ||
483 | /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
484 | altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
485 | compatible, so allow it as well, rather than changing all of the uses of the | |
486 | macro. */ | |
9c878e1b | 487 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
81f0e7d0 | 488 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
489 | (int)VECTOR_ALTIVEC, \ | |
490 | (int)VECTOR_P8_VECTOR)) | |
9c878e1b | 491 | |
492 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
493 | same unit as the vector unit we are using, but we may want to migrate to | |
494 | using VSX style loads even for types handled by altivec. */ | |
495 | extern enum rs6000_vector rs6000_vector_mem[]; | |
496 | ||
497 | #define VECTOR_MEM_NONE_P(MODE) \ | |
498 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
499 | ||
500 | #define VECTOR_MEM_VSX_P(MODE) \ | |
501 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
502 | ||
81f0e7d0 | 503 | #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
504 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
505 | ||
9c878e1b | 506 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
507 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
508 | ||
81f0e7d0 | 509 | #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
510 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
511 | (int)VECTOR_VSX, \ | |
512 | (int)VECTOR_P8_VECTOR)) | |
513 | ||
9c878e1b | 514 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
81f0e7d0 | 515 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
516 | (int)VECTOR_ALTIVEC, \ | |
517 | (int)VECTOR_P8_VECTOR)) | |
9c878e1b | 518 | |
519 | /* Return the alignment of a given vector type, which is set based on the | |
520 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
521 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
522 | extern int rs6000_vector_align[]; | |
523 | ||
524 | #define VECTOR_ALIGN(MODE) \ | |
525 | ((rs6000_vector_align[(MODE)] != 0) \ | |
526 | ? rs6000_vector_align[(MODE)] \ | |
527 | : (int)GET_MODE_BITSIZE ((MODE))) | |
528 | ||
b5236700 | 529 | /* Determine the element order to use for vector instructions. By |
530 | default we use big-endian element order when targeting big-endian, | |
531 | and little-endian element order when targeting little-endian. For | |
532 | programs being ported from BE Power to LE Power, it can sometimes | |
533 | be useful to use big-endian element order when targeting little-endian. | |
534 | This is set via -maltivec=be, for example. */ | |
535 | #define VECTOR_ELT_ORDER_BIG \ | |
536 | (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) | |
537 | ||
a1546352 | 538 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
539 | with scalar instructions. */ | |
540 | #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
541 | ||
7ee13677 | 542 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
543 | with the ISA 3.0 MFVSRLD instructions. */ | |
544 | #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
545 | ||
d9231aca | 546 | /* Alignment options for fields in structures for sub-targets following |
547 | AIX-like ABI. | |
548 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
549 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
550 | ||
551 | Override the macro definitions when compiling libobjc to avoid undefined | |
552 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
553 | macros which use the macros below. */ | |
9e7454d0 | 554 | |
d9231aca | 555 | #ifndef IN_TARGET_LIBS |
556 | #define MASK_ALIGN_POWER 0x00000000 | |
557 | #define MASK_ALIGN_NATURAL 0x00000001 | |
558 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
559 | #else | |
560 | #define TARGET_ALIGN_NATURAL 0 | |
561 | #endif | |
5b53fefa | 562 | |
563 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
baad77c2 | 564 | #define TARGET_IEEEQUAD rs6000_ieeequad |
5b53fefa | 565 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
9c878e1b | 566 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
5b53fefa | 567 | |
9c878e1b | 568 | #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) |
f19493d5 | 569 | |
776f5702 | 570 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
571 | Enable 32-bit fcfid's on any of the switches for newer ISA machines or | |
572 | XILINX. */ | |
203e95f6 | 573 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
574 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
575 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
576 | || TARGET_CMPB /* ISA 2.05 */ \ | |
577 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
776f5702 | 578 | || TARGET_XILINX_FPU) |
579 | ||
580 | #define TARGET_FCTIDZ TARGET_FCFID | |
581 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
582 | #define TARGET_LFIWAX TARGET_CMPB | |
583 | #define TARGET_LFIWZX TARGET_POPCNTD | |
584 | #define TARGET_FCFIDS TARGET_POPCNTD | |
585 | #define TARGET_FCFIDU TARGET_POPCNTD | |
586 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
587 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
588 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
efa01e7c | 589 | #define TARGET_CTZ TARGET_MODULO |
590 | #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
7ee13677 | 591 | #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) |
776f5702 | 592 | |
81f0e7d0 | 593 | #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) |
594 | #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
ae61c502 | 595 | #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) |
7ee13677 | 596 | #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
597 | && TARGET_POWERPC64) | |
63abcf45 | 598 | #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
92891f84 | 599 | && TARGET_POWERPC64) |
522d385d | 600 | |
522d385d | 601 | /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ |
602 | #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
603 | #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
604 | ||
ef86dfca | 605 | /* This wants to be set for p8 and newer. On p7, overlapping unaligned |
606 | loads are slow. */ | |
607 | #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX | |
81f0e7d0 | 608 | |
609 | /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
610 | in power7, so conditionalize them on p8 features. TImode syncs need quad | |
611 | memory support. */ | |
1c09f133 | 612 | #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ |
613 | || TARGET_QUAD_MEMORY_ATOMIC \ | |
614 | || TARGET_DIRECT_MOVE) | |
615 | ||
616 | #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
81f0e7d0 | 617 | |
33a2d887 | 618 | /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need |
619 | to allocate the SDmode stack slot to get the value into the proper location | |
620 | in the register. */ | |
621 | #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
622 | ||
2e196ca8 | 623 | /* ISA 3.0 has new min/max functions that don't need fast math that are being |
624 | phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
625 | answers if the arguments are not in the normal range. */ | |
626 | #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ | |
627 | && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
628 | ||
629 | #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \ | |
630 | && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
631 | ||
62b54165 | 632 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
633 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
634 | OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
635 | #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
636 | #define MASK_CMPB OPTION_MASK_CMPB | |
81f0e7d0 | 637 | #define MASK_CRYPTO OPTION_MASK_CRYPTO |
62b54165 | 638 | #define MASK_DFP OPTION_MASK_DFP |
81f0e7d0 | 639 | #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE |
62b54165 | 640 | #define MASK_DLMZB OPTION_MASK_DLMZB |
641 | #define MASK_EABI OPTION_MASK_EABI | |
7d29bba9 | 642 | #define MASK_FLOAT128_TYPE OPTION_MASK_FLOAT128_TYPE |
62b54165 | 643 | #define MASK_FPRND OPTION_MASK_FPRND |
81f0e7d0 | 644 | #define MASK_P8_FUSION OPTION_MASK_P8_FUSION |
62b54165 | 645 | #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT |
5088e479 | 646 | #define MASK_HTM OPTION_MASK_HTM |
62b54165 | 647 | #define MASK_ISEL OPTION_MASK_ISEL |
648 | #define MASK_MFCRF OPTION_MASK_MFCRF | |
649 | #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
650 | #define MASK_MULHW OPTION_MASK_MULHW | |
651 | #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
652 | #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
81f0e7d0 | 653 | #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR |
d94e6223 | 654 | #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR |
17c32c4a | 655 | #define MASK_P9_MISC OPTION_MASK_P9_MISC |
62b54165 | 656 | #define MASK_POPCNTB OPTION_MASK_POPCNTB |
657 | #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
658 | #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
659 | #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
660 | #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
661 | #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
662 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
663 | #define MASK_STRING OPTION_MASK_STRING | |
664 | #define MASK_UPDATE OPTION_MASK_UPDATE | |
665 | #define MASK_VSX OPTION_MASK_VSX | |
666 | ||
667 | #ifndef IN_LIBGCC2 | |
668 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
669 | #endif | |
670 | ||
671 | #ifdef TARGET_64BIT | |
672 | #define MASK_64BIT OPTION_MASK_64BIT | |
673 | #endif | |
674 | ||
62b54165 | 675 | #ifdef TARGET_LITTLE_ENDIAN |
676 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
677 | #endif | |
678 | ||
62b54165 | 679 | #ifdef TARGET_REGNAMES |
680 | #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
681 | #endif | |
682 | ||
683 | #ifdef TARGET_PROTOTYPE | |
684 | #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
685 | #endif | |
686 | ||
26a51591 | 687 | #ifdef TARGET_MODULO |
688 | #define RS6000_BTM_MODULO OPTION_MASK_MODULO | |
689 | #endif | |
690 | ||
691 | ||
0375b229 | 692 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
693 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
694 | of #pragma GCC target or the target attribute to change the code level for a | |
0a35be0f | 695 | given system. The Paired builtins are only enabled if you configure the |
696 | compiler for those builtins, and those machines don't support altivec or | |
0375b229 | 697 | VSX. */ |
698 | ||
9d20c62c | 699 | #define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ |
0375b229 | 700 | && ((TARGET_POWERPC64 \ |
203e95f6 | 701 | || TARGET_PPC_GPOPT /* 970/power4 */ \ |
0375b229 | 702 | || TARGET_POPCNTB /* ISA 2.02 */ \ |
703 | || TARGET_CMPB /* ISA 2.05 */ \ | |
704 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
705 | || TARGET_ALTIVEC \ | |
d44f2f7c | 706 | || TARGET_VSX \ |
707 | || TARGET_HARD_FLOAT))) | |
0375b229 | 708 | |
76303083 | 709 | /* E500 cores only support plain "sync", not lwsync. */ |
710 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
711 | || rs6000_cpu == PROCESSOR_PPC8548) | |
0375b229 | 712 | |
713 | ||
47ae02b7 | 714 | /* Whether SF/DF operations are supported by the normal floating point unit |
0b16079d | 715 | (or the vector/scalar unit). */ |
df8015ff | 716 | #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT) |
717 | #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) | |
0b16079d | 718 | |
719 | /* Whether SF/DF operations are supported by any hardware. */ | |
df8015ff | 720 | #define TARGET_SF_INSN TARGET_SF_FPR |
721 | #define TARGET_DF_INSN TARGET_DF_FPR | |
0b16079d | 722 | |
0eac26de | 723 | /* Which machine supports the various reciprocal estimate instructions. */ |
724 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ | |
df8015ff | 725 | && TARGET_SINGLE_FLOAT) |
0eac26de | 726 | |
df8015ff | 727 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ |
0eac26de | 728 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
729 | ||
730 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
df8015ff | 731 | && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) |
0eac26de | 732 | |
df8015ff | 733 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ |
0eac26de | 734 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) |
735 | ||
efa01e7c | 736 | /* Conditions to allow TOC fusion for loading/storing integers. */ |
737 | #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \ | |
738 | && TARGET_TOC_FUSION \ | |
739 | && (TARGET_CMODEL != CMODEL_SMALL) \ | |
740 | && TARGET_POWERPC64) | |
741 | ||
742 | /* Conditions to allow TOC fusion for loading/storing floating point. */ | |
743 | #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \ | |
744 | && TARGET_TOC_FUSION \ | |
745 | && (TARGET_CMODEL != CMODEL_SMALL) \ | |
746 | && TARGET_POWERPC64 \ | |
747 | && TARGET_HARD_FLOAT \ | |
efa01e7c | 748 | && TARGET_SINGLE_FLOAT \ |
749 | && TARGET_DOUBLE_FLOAT) | |
750 | ||
ff055c48 | 751 | /* Macro to say whether we can do optimizations where we need to do parts of |
752 | the calculation in 64-bit GPRs and then is transfered to the vector | |
753 | registers. Do not allow -maltivec=be for these optimizations, because it | |
754 | adds to the complexity of the code. */ | |
a52bb7a0 | 755 | #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ |
756 | && TARGET_P8_VECTOR \ | |
757 | && TARGET_POWERPC64 \ | |
ff055c48 | 758 | && (rs6000_altivec_element_order != 2)) |
a52bb7a0 | 759 | |
0eac26de | 760 | /* Whether the various reciprocal divide/square root estimate instructions |
761 | exist, and whether we should automatically generate code for the instruction | |
762 | by default. */ | |
763 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
764 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
765 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
766 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
767 | ||
768 | extern unsigned char rs6000_recip_bits[]; | |
769 | ||
770 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
771 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
772 | ||
773 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
774 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
775 | ||
776 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
777 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
778 | ||
779 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
780 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
781 | ||
4c834714 | 782 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
783 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
d79df659 | 784 | |
edd2f2ae | 785 | /* Target pragma. */ |
eb180587 | 786 | #define REGISTER_TARGET_PRAGMAS() do { \ |
787 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
755fa783 | 788 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
02e6a8e1 | 789 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
0375b229 | 790 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
edd2f2ae | 791 | } while (0) |
792 | ||
b2d381e8 | 793 | /* Target #defines. */ |
794 | #define TARGET_CPU_CPP_BUILTINS() \ | |
795 | rs6000_cpu_cpp_builtins (pfile) | |
a429a994 | 796 | |
797 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
798 | we're compiling for. Some configurations may need to override it. */ | |
799 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
800 | do \ | |
801 | { \ | |
802 | if (BYTES_BIG_ENDIAN) \ | |
803 | { \ | |
804 | builtin_define ("__BIG_ENDIAN__"); \ | |
805 | builtin_define ("_BIG_ENDIAN"); \ | |
806 | builtin_assert ("machine=bigendian"); \ | |
807 | } \ | |
808 | else \ | |
809 | { \ | |
810 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
811 | builtin_define ("_LITTLE_ENDIAN"); \ | |
812 | builtin_assert ("machine=littleendian"); \ | |
813 | } \ | |
814 | } \ | |
815 | while (0) | |
d79df659 | 816 | \f |
b2d381e8 | 817 | /* Target machine storage layout. */ |
d79df659 | 818 | |
064d9c8f | 819 | /* Define this macro if it is advisable to hold scalars in registers |
a91f63e4 | 820 | in a wider mode than that declared by the program. In such cases, |
60fe810e | 821 | the value is constrained to be within the bounds of the declared |
822 | type, but kept valid in the wider mode. The signedness of the | |
823 | extension may differ from that of the type. */ | |
824 | ||
3469a3e2 | 825 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
826 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
2f4fe32e | 827 | && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
4cccb4b2 | 828 | (MODE) = TARGET_32BIT ? SImode : DImode; |
3469a3e2 | 829 | |
d79df659 | 830 | /* Define this if most significant bit is lowest numbered |
7c721ad4 | 831 | in instructions that operate on numbered bit-fields. */ |
832 | /* That is true on RS/6000. */ | |
d79df659 | 833 | #define BITS_BIG_ENDIAN 1 |
834 | ||
835 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
836 | /* That is true on RS/6000. */ | |
837 | #define BYTES_BIG_ENDIAN 1 | |
838 | ||
839 | /* Define this if most significant word of a multiword number is lowest | |
a91f63e4 | 840 | numbered. |
d79df659 | 841 | |
842 | For RS/6000 we can decide arbitrarily since there are no machine | |
7c721ad4 | 843 | instructions for them. Might as well be consistent with bits and bytes. */ |
d79df659 | 844 | #define WORDS_BIG_ENDIAN 1 |
845 | ||
74a1167a | 846 | /* This says that for the IBM long double the larger magnitude double |
847 | comes first. It's really a two element double array, and arrays | |
848 | don't index differently between little- and big-endian. */ | |
849 | #define LONG_DOUBLE_LARGE_FIRST 1 | |
850 | ||
5bc3a2d4 | 851 | #define MAX_BITS_PER_WORD 64 |
d79df659 | 852 | |
853 | /* Width of a word, in units (bytes). */ | |
05ee0562 | 854 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
227c963b | 855 | #ifdef IN_LIBGCC2 |
856 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
857 | #else | |
65748b1b | 858 | #define MIN_UNITS_PER_WORD 4 |
227c963b | 859 | #endif |
5bc3a2d4 | 860 | #define UNITS_PER_FP_WORD 8 |
500c7157 | 861 | #define UNITS_PER_ALTIVEC_WORD 16 |
9c878e1b | 862 | #define UNITS_PER_VSX_WORD 16 |
a9de045e | 863 | #define UNITS_PER_PAIRED_WORD 8 |
d79df659 | 864 | |
d2d45541 | 865 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
866 | #define PTRDIFF_TYPE "int" | |
867 | ||
b37aff25 | 868 | /* Type used for size_t, as a string used in a declaration. */ |
869 | #define SIZE_TYPE "long unsigned int" | |
870 | ||
d79df659 | 871 | /* Type used for wchar_t, as a string used in a declaration. */ |
872 | #define WCHAR_TYPE "short unsigned int" | |
873 | ||
874 | /* Width of wchar_t in bits. */ | |
875 | #define WCHAR_TYPE_SIZE 16 | |
876 | ||
02094643 | 877 | /* A C expression for the size in bits of the type `short' on the |
878 | target machine. If you don't define this, the default is half a | |
879 | word. (If this would be less than one storage unit, it is | |
880 | rounded up to one unit.) */ | |
881 | #define SHORT_TYPE_SIZE 16 | |
882 | ||
883 | /* A C expression for the size in bits of the type `int' on the | |
884 | target machine. If you don't define this, the default is one | |
885 | word. */ | |
66455505 | 886 | #define INT_TYPE_SIZE 32 |
02094643 | 887 | |
888 | /* A C expression for the size in bits of the type `long' on the | |
889 | target machine. If you don't define this, the default is one | |
890 | word. */ | |
4086c37e | 891 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
02094643 | 892 | |
893 | /* A C expression for the size in bits of the type `long long' on the | |
894 | target machine. If you don't define this, the default is two | |
895 | words. */ | |
896 | #define LONG_LONG_TYPE_SIZE 64 | |
897 | ||
02094643 | 898 | /* A C expression for the size in bits of the type `float' on the |
899 | target machine. If you don't define this, the default is one | |
900 | word. */ | |
901 | #define FLOAT_TYPE_SIZE 32 | |
902 | ||
903 | /* A C expression for the size in bits of the type `double' on the | |
904 | target machine. If you don't define this, the default is two | |
905 | words. */ | |
906 | #define DOUBLE_TYPE_SIZE 64 | |
907 | ||
908 | /* A C expression for the size in bits of the type `long double' on | |
909 | the target machine. If you don't define this, the default is two | |
910 | words. */ | |
5b53fefa | 911 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
5c0586b9 | 912 | |
4dba9f7a | 913 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
914 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
915 | ||
d79df659 | 916 | /* Width in bits of a pointer. |
917 | See also the macro `Pmode' defined below. */ | |
9c878e1b | 918 | extern unsigned rs6000_pointer_size; |
919 | #define POINTER_SIZE rs6000_pointer_size | |
d79df659 | 920 | |
921 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
4086c37e | 922 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
d79df659 | 923 | |
924 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9c878e1b | 925 | #define STACK_BOUNDARY \ |
926 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
927 | ? 64 : 128) | |
d79df659 | 928 | |
929 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
930 | #define FUNCTION_BOUNDARY 32 | |
931 | ||
932 | /* No data type wants to be aligned rounder than this. */ | |
500c7157 | 933 | #define BIGGEST_ALIGNMENT 128 |
934 | ||
d79df659 | 935 | /* Alignment of field after `int : 0' in a structure. */ |
936 | #define EMPTY_FIELD_BOUNDARY 32 | |
937 | ||
938 | /* Every structure's size must be a multiple of this. */ | |
939 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
940 | ||
ceb2fe0f | 941 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
d79df659 | 942 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
943 | ||
efb66c8d | 944 | enum data_align { align_abi, align_opt, align_both }; |
945 | ||
946 | /* A C expression to compute the alignment for a variables in the | |
947 | local store. TYPE is the data type, and ALIGN is the alignment | |
948 | that the object would ordinarily have. */ | |
949 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
950 | rs6000_data_alignment (TYPE, ALIGN, align_both) | |
951 | ||
952 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
886cfd4f | 953 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
954 | (TREE_CODE (EXP) == STRING_CST \ | |
070270ea | 955 | && (STRICT_ALIGNMENT || !optimize_size) \ |
886cfd4f | 956 | && (ALIGN) < BITS_PER_WORD \ |
957 | ? BITS_PER_WORD \ | |
958 | : (ALIGN)) | |
d79df659 | 959 | |
efb66c8d | 960 | /* Make arrays of chars word-aligned for the same reasons. */ |
961 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
962 | rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
963 | ||
9d20c62c | 964 | /* Align vectors to 128 bits. */ |
efb66c8d | 965 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ |
966 | rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
d79df659 | 967 | |
e911aedf | 968 | /* Nonzero if move instructions will actually fail to work |
d79df659 | 969 | when given unaligned data. */ |
397cd47b | 970 | #define STRICT_ALIGNMENT 0 |
9439ebf7 | 971 | |
972 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
973 | many times greater than aligned accesses, for example if they are | |
974 | emulated in a trap handler. */ | |
9d20c62c | 975 | /* Altivec vector memory instructions simply ignore the low bits; VSX memory |
976 | instructions are aligned to 4 or 8 bytes. */ | |
36198b23 | 977 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
978 | (STRICT_ALIGNMENT \ | |
b1b27d3b | 979 | || (!TARGET_EFFICIENT_UNALIGNED_VSX \ |
980 | && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) && (ALIGN) < 32) \ | |
981 | || ((VECTOR_MODE_P (MODE) || FLOAT128_VECTOR_P (MODE)) \ | |
982 | && (int) (ALIGN) < VECTOR_ALIGN (MODE))))) | |
9c878e1b | 983 | |
d79df659 | 984 | \f |
985 | /* Standard register usage. */ | |
986 | ||
987 | /* Number of actual hardware registers. | |
988 | The hardware registers are assigned numbers for the compiler | |
989 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
990 | All registers that the compiler knows about must be given numbers, | |
991 | even those that are not normally considered general registers. | |
992 | ||
993 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
ca1ad495 | 994 | a count register, a link register, and 8 condition register fields, |
995 | which we view here as separate registers. AltiVec adds 32 vector | |
996 | registers and a VRsave register. | |
d79df659 | 997 | |
998 | In addition, the difference between the frame and argument pointers is | |
999 | a function of the number of registers saved, so we need to have a | |
1000 | register for AP that will later be eliminated in favor of SP or FP. | |
359e408d | 1001 | This is a normal register, but it is fixed. |
d79df659 | 1002 | |
359e408d | 1003 | We also create a pseudo register for float/int conversions, that will |
1004 | really represent the memory location used. It is represented here as | |
1005 | a register, in order to work around problems in allocating stack storage | |
0d6c02bf | 1006 | in inline functions. |
359e408d | 1007 | |
0d6c02bf | 1008 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
8e5b1909 | 1009 | pointer, which is eventually eliminated in favor of SP or FP. |
1010 | ||
1011 | The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ | |
0d6c02bf | 1012 | |
e77e5402 | 1013 | #define FIRST_PSEUDO_REGISTER 115 |
d79df659 | 1014 | |
cb0ccc1e | 1015 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
0ef398b0 | 1016 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
043c3f91 | 1017 | |
9d20c62c | 1018 | /* The sfp register and 3 HTM registers |
3fa2798a | 1019 | aren't included in DWARF_FRAME_REGISTERS. */ |
1020 | #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) | |
d838c8e7 | 1021 | |
bc5c9982 | 1022 | /* Use standard DWARF numbering for DWARF debugging information. */ |
fc222f44 | 1023 | #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
bc5c9982 | 1024 | |
0e841d50 | 1025 | /* Use gcc hard register numbering for eh_frame. */ |
fc222f44 | 1026 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) |
e92aec9e | 1027 | |
bc5c9982 | 1028 | /* Map register numbers held in the call frame info that gcc has |
1029 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
fc222f44 | 1030 | .debug_frame and .eh_frame. */ |
1031 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
1032 | rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) | |
bc5c9982 | 1033 | |
d79df659 | 1034 | /* 1 for registers that have pervasive standard uses |
1035 | and are not available for the register allocator. | |
1036 | ||
646b2fe6 | 1037 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
1038 | as a local register; for all other OS's r2 is the TOC pointer. | |
d79df659 | 1039 | |
38bde2e6 | 1040 | On System V implementations, r13 is fixed and not available for use. */ |
1041 | ||
d79df659 | 1042 | #define FIXED_REGISTERS \ |
646b2fe6 | 1043 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
d79df659 | 1044 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1045 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1046 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
72dc204f | 1047 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
500c7157 | 1048 | /* AltiVec registers. */ \ |
1049 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1050 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
3a1f8574 | 1051 | 1, 1 \ |
e77e5402 | 1052 | , 1, 1, 1, 1 \ |
500c7157 | 1053 | } |
d79df659 | 1054 | |
1055 | /* 1 for registers not available across function calls. | |
1056 | These must include the FIXED_REGISTERS and also any | |
1057 | registers that can be used without being saved. | |
1058 | The latter must include the registers where values are returned | |
1059 | and the register where structure-value addresses are passed. | |
1060 | Aside from that, you can include as many other registers as you like. */ | |
1061 | ||
1062 | #define CALL_USED_REGISTERS \ | |
38bde2e6 | 1063 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
d79df659 | 1064 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1065 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
1066 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
500c7157 | 1067 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
1068 | /* AltiVec registers. */ \ | |
1069 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1070 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
3a1f8574 | 1071 | 1, 1 \ |
e77e5402 | 1072 | , 1, 1, 1, 1 \ |
500c7157 | 1073 | } |
1074 | ||
d79ffb55 | 1075 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
1076 | the entire set of `FIXED_REGISTERS' be included. | |
1077 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
1078 | This macro is optional. If not specified, it defaults to the value | |
1079 | of `CALL_USED_REGISTERS'. */ | |
9e7454d0 | 1080 | |
d79ffb55 | 1081 | #define CALL_REALLY_USED_REGISTERS \ |
1082 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
1083 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1084 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
1085 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
d462568f | 1086 | 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
d79ffb55 | 1087 | /* AltiVec registers. */ \ |
1088 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1089 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
3a1f8574 | 1090 | 0, 0 \ |
e77e5402 | 1091 | , 0, 0, 0, 0 \ |
d79ffb55 | 1092 | } |
d79df659 | 1093 | |
1daf4caa | 1094 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
bbd21807 | 1095 | |
b3a89f06 | 1096 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
cef20746 | 1097 | #define FIRST_SAVED_FP_REGNO (14+32) |
1098 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
b3a89f06 | 1099 | |
d79df659 | 1100 | /* List the order in which to allocate registers. Each register must be |
1101 | listed once, even those in FIXED_REGISTERS. | |
1102 | ||
1103 | We allocate in the following order: | |
1104 | fp0 (not saved or used for anything) | |
1105 | fp13 - fp2 (not saved; incoming fp arg registers) | |
1106 | fp1 (not saved; return value) | |
51ce1864 | 1107 | fp31 - fp14 (saved; order given to save least number) |
72dc204f | 1108 | cr7, cr5 (not saved or special) |
1109 | cr6 (not saved, but used for vector operations) | |
879c6e0a | 1110 | cr1 (not saved, but used for FP operations) |
d79df659 | 1111 | cr0 (not saved, but used for arithmetic operations) |
879c6e0a | 1112 | cr4, cr3, cr2 (saved) |
d79df659 | 1113 | r9 (not saved; best for TImode) |
e0ec8173 | 1114 | r10, r8-r4 (not saved; highest first for less conflict with params) |
51ce1864 | 1115 | r3 (not saved; return value register) |
e0ec8173 | 1116 | r11 (not saved; later alloc to help shrink-wrap) |
1117 | r0 (not saved; cannot be base reg) | |
d79df659 | 1118 | r31 - r13 (saved; order given to save least number) |
1119 | r12 (not saved; if used for DImode or DFmode would use r13) | |
d79df659 | 1120 | ctr (not saved; when we have the choice ctr is better) |
1121 | lr (saved) | |
72dc204f | 1122 | r1, r2, ap, ca (fixed) |
51ce1864 | 1123 | v0 - v1 (not saved or used for anything) |
1124 | v13 - v3 (not saved; incoming vector arg registers) | |
1125 | v2 (not saved; incoming vector arg reg; return value) | |
1126 | v19 - v14 (not saved or used for anything) | |
1127 | v31 - v20 (saved; order given to save least number) | |
1128 | vrsave, vscr (fixed) | |
0d6c02bf | 1129 | sfp (fixed) |
5088e479 | 1130 | tfhar (fixed) |
1131 | tfiar (fixed) | |
1132 | texasr (fixed) | |
500c7157 | 1133 | */ |
9e7454d0 | 1134 | |
fd235bd7 | 1135 | #if FIXED_R2 == 1 |
1136 | #define MAYBE_R2_AVAILABLE | |
1137 | #define MAYBE_R2_FIXED 2, | |
1138 | #else | |
1139 | #define MAYBE_R2_AVAILABLE 2, | |
1140 | #define MAYBE_R2_FIXED | |
1141 | #endif | |
d79df659 | 1142 | |
e0ec8173 | 1143 | #if FIXED_R13 == 1 |
1144 | #define EARLY_R12 12, | |
1145 | #define LATE_R12 | |
1146 | #else | |
1147 | #define EARLY_R12 | |
1148 | #define LATE_R12 12, | |
1149 | #endif | |
1150 | ||
51ce1864 | 1151 | #define REG_ALLOC_ORDER \ |
1152 | {32, \ | |
81f0e7d0 | 1153 | /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
1154 | /* not use fr14 which is a saved register. */ \ | |
1155 | 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
51ce1864 | 1156 | 33, \ |
1157 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
1158 | 50, 49, 48, 47, 46, \ | |
72dc204f | 1159 | 75, 73, 74, 69, 68, 72, 71, 70, \ |
e0ec8173 | 1160 | MAYBE_R2_AVAILABLE \ |
1161 | 9, 10, 8, 7, 6, 5, 4, \ | |
1162 | 3, EARLY_R12 11, 0, \ | |
51ce1864 | 1163 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
e0ec8173 | 1164 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
ca1ad495 | 1165 | 66, 65, \ |
72dc204f | 1166 | 1, MAYBE_R2_FIXED 67, 76, \ |
51ce1864 | 1167 | /* AltiVec registers. */ \ |
1168 | 77, 78, \ | |
1169 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
1170 | 79, \ | |
1171 | 96, 95, 94, 93, 92, 91, \ | |
1172 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
1173 | 109, 110, \ | |
e77e5402 | 1174 | 111, 112, 113, 114 \ |
500c7157 | 1175 | } |
d79df659 | 1176 | |
1177 | /* True if register is floating-point. */ | |
1178 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1179 | ||
1180 | /* True if register is a condition register. */ | |
e18e5bf1 | 1181 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
d79df659 | 1182 | |
9aba4661 | 1183 | /* True if register is a condition register, but not cr0. */ |
e18e5bf1 | 1184 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
9aba4661 | 1185 | |
d79df659 | 1186 | /* True if register is an integer register. */ |
0d6c02bf | 1187 | #define INT_REGNO_P(N) \ |
1188 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
d79df659 | 1189 | |
a9de045e | 1190 | /* PAIRED SIMD registers are just the FPRs. */ |
1191 | #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1192 | ||
ce81d1c2 | 1193 | /* True if register is the CA register. */ |
1194 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
359e408d | 1195 | |
500c7157 | 1196 | /* True if register is an AltiVec register. */ |
1197 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
1198 | ||
9c878e1b | 1199 | /* True if register is a VSX register. */ |
1200 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
1201 | ||
1202 | /* Alternate name for any vector register supporting floating point, no matter | |
1203 | which instruction set(s) are available. */ | |
1204 | #define VFLOAT_REGNO_P(N) \ | |
1205 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
1206 | ||
1207 | /* Alternate name for any vector register supporting integer, no matter which | |
1208 | instruction set(s) are available. */ | |
1209 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
1210 | ||
1211 | /* Alternate name for any vector register supporting logical operations, no | |
91bf8773 | 1212 | matter which instruction set(s) are available. Allow GPRs as well as the |
1213 | vector registers. */ | |
81f0e7d0 | 1214 | #define VLOGICAL_REGNO_P(N) \ |
91bf8773 | 1215 | (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ |
1216 | || (TARGET_VSX && FP_REGNO_P (N))) \ | |
9c878e1b | 1217 | |
d79df659 | 1218 | /* Return number of consecutive hard regs needed starting at reg REGNO |
2859c78f | 1219 | to hold something of mode MODE. */ |
1220 | ||
9c878e1b | 1221 | #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] |
e4707539 | 1222 | |
d9350d7a | 1223 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
21e5dc01 | 1224 | enough space to account for vectors in FP regs. However, TFmode/TDmode |
1225 | should not use VSX instructions to do a caller save. */ | |
2cf72ba5 | 1226 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
506d6baf | 1227 | ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ |
1228 | ? (MODE) \ | |
1229 | : TARGET_VSX \ | |
1230 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
1231 | && FP_REGNO_P (REGNO) \ | |
21e5dc01 | 1232 | ? V2DFmode \ |
94da43a5 | 1233 | : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ |
21e5dc01 | 1234 | ? DFmode \ |
94da43a5 | 1235 | : (MODE) == TDmode && FP_REGNO_P (REGNO) \ |
21e5dc01 | 1236 | ? DImode \ |
d9350d7a | 1237 | : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
1238 | ||
9c878e1b | 1239 | #define VSX_VECTOR_MODE(MODE) \ |
1240 | ((MODE) == V4SFmode \ | |
1241 | || (MODE) == V2DFmode) \ | |
1242 | ||
3f2bdc95 | 1243 | /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
1244 | really a vector, but we want to treat it as a vector for moves, and | |
1245 | such. */ | |
1246 | ||
1247 | #define ALTIVEC_VECTOR_MODE(MODE) \ | |
1248 | ((MODE) == V16QImode \ | |
1249 | || (MODE) == V8HImode \ | |
1250 | || (MODE) == V4SFmode \ | |
1251 | || (MODE) == V4SImode \ | |
1252 | || FLOAT128_VECTOR_P (MODE)) | |
500c7157 | 1253 | |
2cf72ba5 | 1254 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1255 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
ae61c502 | 1256 | || (MODE) == V2DImode || (MODE) == V1TImode) |
2cf72ba5 | 1257 | |
a9de045e | 1258 | #define PAIRED_VECTOR_MODE(MODE) \ |
1259 | ((MODE) == V2SFmode) | |
1260 | ||
1aad6057 | 1261 | /* Value is TRUE if hard register REGNO can hold a value of |
1262 | machine-mode MODE. */ | |
1263 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1264 | rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] | |
d79df659 | 1265 | |
1266 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1267 | when one has mode MODE1 and one has mode MODE2. | |
1268 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
53ee13c3 | 1269 | for any hard reg, then this must be 0 for correct output. |
1270 | ||
1271 | PTImode cannot tie with other modes because PTImode is restricted to even | |
1272 | GPR registers, and TImode can go in any GPR as well as VSX registers (PR | |
3f2bdc95 | 1273 | 57744). |
1274 | ||
1275 | Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE | |
1276 | 128-bit floating point on VSX systems ties with other vectors. */ | |
81f0e7d0 | 1277 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
53ee13c3 | 1278 | ((MODE1) == PTImode \ |
1279 | ? (MODE2) == PTImode \ | |
1280 | : (MODE2) == PTImode \ | |
1281 | ? 0 \ | |
3f2bdc95 | 1282 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ |
1283 | ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1284 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1285 | ? 0 \ | |
53ee13c3 | 1286 | : SCALAR_FLOAT_MODE_P (MODE1) \ |
e284b8fb | 1287 | ? SCALAR_FLOAT_MODE_P (MODE2) \ |
1288 | : SCALAR_FLOAT_MODE_P (MODE2) \ | |
53ee13c3 | 1289 | ? 0 \ |
d79df659 | 1290 | : GET_MODE_CLASS (MODE1) == MODE_CC \ |
1291 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1292 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
53ee13c3 | 1293 | ? 0 \ |
9d20c62c | 1294 | : PAIRED_VECTOR_MODE (MODE1) \ |
1295 | ? PAIRED_VECTOR_MODE (MODE2) \ | |
1296 | : PAIRED_VECTOR_MODE (MODE2) \ | |
53ee13c3 | 1297 | ? 0 \ |
d79df659 | 1298 | : 1) |
1299 | ||
0e3a9960 | 1300 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1301 | emitted the vrsave mask. */ | |
1302 | ||
1303 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
3072d30e | 1304 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
0e3a9960 | 1305 | |
d79df659 | 1306 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1307 | should be added to avoid a branch. | |
1308 | ||
60fe810e | 1309 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
d79df659 | 1310 | unscheduled conditional branch. */ |
1311 | ||
4a9d7ef7 | 1312 | #define BRANCH_COST(speed_p, predictable_p) 3 |
d79df659 | 1313 | |
cf451ad8 | 1314 | /* Override BRANCH_COST heuristic which empirically produces worse |
17529f98 | 1315 | performance for removing short circuiting from the logical ops. */ |
cf451ad8 | 1316 | |
17529f98 | 1317 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
f19493d5 | 1318 | |
d79df659 | 1319 | /* Specify the registers used for certain standard purposes. |
1320 | The values of these macros are register numbers. */ | |
1321 | ||
1322 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1323 | /* #define PC_REGNUM */ | |
1324 | ||
1325 | /* Register to use for pushing function arguments. */ | |
1326 | #define STACK_POINTER_REGNUM 1 | |
1327 | ||
1328 | /* Base register for access to local variables of the function. */ | |
0d6c02bf | 1329 | #define HARD_FRAME_POINTER_REGNUM 31 |
1330 | ||
1331 | /* Base register for access to local variables of the function. */ | |
e77e5402 | 1332 | #define FRAME_POINTER_REGNUM 111 |
d79df659 | 1333 | |
d79df659 | 1334 | /* Base register for access to arguments of the function. */ |
1335 | #define ARG_POINTER_REGNUM 67 | |
1336 | ||
1337 | /* Place to put static chain when calling a function that requires it. */ | |
1338 | #define STATIC_CHAIN_REGNUM 11 | |
1339 | ||
62752e71 | 1340 | /* Base register for access to thread local storage variables. */ |
1341 | #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
1342 | ||
d79df659 | 1343 | \f |
1344 | /* Define the classes of registers for register constraints in the | |
1345 | machine description. Also define ranges of constants. | |
1346 | ||
1347 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1348 | If there is more than one class, another class must be named NO_REGS | |
1349 | and contain no registers. | |
1350 | ||
1351 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1352 | another name such as ALL_REGS). This is the class of registers | |
1353 | that is allowed by "g" or "r" in a register constraint. | |
1354 | Also, registers outside this class are allocated only when | |
1355 | instructions express preferences for them. | |
1356 | ||
1357 | The classes must be numbered in nondecreasing order; that is, | |
1358 | a larger-numbered class must never be contained completely | |
1359 | in a smaller-numbered class. | |
1360 | ||
1361 | For any two classes, it is very desirable that there be another | |
1362 | class that represents their union. */ | |
a91f63e4 | 1363 | |
9c878e1b | 1364 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
ca1ad495 | 1365 | condition registers, plus three special registers, CTR, and the link |
9c878e1b | 1366 | register. AltiVec adds a vector register class. VSX registers overlap the |
1367 | FPR registers and the Altivec registers. | |
d79df659 | 1368 | |
1369 | However, r0 is special in that it cannot be used as a base register. | |
1370 | So make a class for registers valid as base registers. | |
1371 | ||
1372 | Also, cr0 is the only condition code register that can be used in | |
93d09736 | 1373 | arithmetic insns, so make a separate class for it. */ |
d79df659 | 1374 | |
6131c8b5 | 1375 | enum reg_class |
1376 | { | |
1377 | NO_REGS, | |
6131c8b5 | 1378 | BASE_REGS, |
1379 | GENERAL_REGS, | |
1380 | FLOAT_REGS, | |
500c7157 | 1381 | ALTIVEC_REGS, |
6ff33500 | 1382 | VSX_REGS, |
500c7157 | 1383 | VRSAVE_REGS, |
3a1f8574 | 1384 | VSCR_REGS, |
5088e479 | 1385 | SPR_REGS, |
6131c8b5 | 1386 | NON_SPECIAL_REGS, |
6131c8b5 | 1387 | LINK_REGS, |
1388 | CTR_REGS, | |
1389 | LINK_OR_CTR_REGS, | |
1390 | SPECIAL_REGS, | |
1391 | SPEC_OR_GEN_REGS, | |
1392 | CR0_REGS, | |
6131c8b5 | 1393 | CR_REGS, |
1394 | NON_FLOAT_REGS, | |
ce81d1c2 | 1395 | CA_REGS, |
6131c8b5 | 1396 | ALL_REGS, |
1397 | LIM_REG_CLASSES | |
1398 | }; | |
d79df659 | 1399 | |
1400 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1401 | ||
7c721ad4 | 1402 | /* Give names of register classes as strings for dump file. */ |
d79df659 | 1403 | |
6131c8b5 | 1404 | #define REG_CLASS_NAMES \ |
1405 | { \ | |
1406 | "NO_REGS", \ | |
6131c8b5 | 1407 | "BASE_REGS", \ |
1408 | "GENERAL_REGS", \ | |
1409 | "FLOAT_REGS", \ | |
500c7157 | 1410 | "ALTIVEC_REGS", \ |
6ff33500 | 1411 | "VSX_REGS", \ |
500c7157 | 1412 | "VRSAVE_REGS", \ |
3a1f8574 | 1413 | "VSCR_REGS", \ |
5088e479 | 1414 | "SPR_REGS", \ |
6131c8b5 | 1415 | "NON_SPECIAL_REGS", \ |
6131c8b5 | 1416 | "LINK_REGS", \ |
1417 | "CTR_REGS", \ | |
1418 | "LINK_OR_CTR_REGS", \ | |
1419 | "SPECIAL_REGS", \ | |
1420 | "SPEC_OR_GEN_REGS", \ | |
1421 | "CR0_REGS", \ | |
6131c8b5 | 1422 | "CR_REGS", \ |
1423 | "NON_FLOAT_REGS", \ | |
ce81d1c2 | 1424 | "CA_REGS", \ |
6131c8b5 | 1425 | "ALL_REGS" \ |
1426 | } | |
d79df659 | 1427 | |
1428 | /* Define which registers fit in which classes. | |
1429 | This is an initializer for a vector of HARD_REG_SET | |
1430 | of length N_REG_CLASSES. */ | |
1431 | ||
3fa2798a | 1432 | #define REG_CLASS_CONTENTS \ |
1433 | { \ | |
1434 | /* NO_REGS. */ \ | |
bc550266 | 1435 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
3fa2798a | 1436 | /* BASE_REGS. */ \ |
e77e5402 | 1437 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \ |
3fa2798a | 1438 | /* GENERAL_REGS. */ \ |
e77e5402 | 1439 | { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \ |
3fa2798a | 1440 | /* FLOAT_REGS. */ \ |
bc550266 | 1441 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ |
3fa2798a | 1442 | /* ALTIVEC_REGS. */ \ |
bc550266 | 1443 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \ |
3fa2798a | 1444 | /* VSX_REGS. */ \ |
bc550266 | 1445 | { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \ |
3fa2798a | 1446 | /* VRSAVE_REGS. */ \ |
bc550266 | 1447 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ |
3fa2798a | 1448 | /* VSCR_REGS. */ \ |
bc550266 | 1449 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \ |
3fa2798a | 1450 | /* SPR_REGS. */ \ |
e77e5402 | 1451 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \ |
3fa2798a | 1452 | /* NON_SPECIAL_REGS. */ \ |
e77e5402 | 1453 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \ |
3fa2798a | 1454 | /* LINK_REGS. */ \ |
bc550266 | 1455 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \ |
3fa2798a | 1456 | /* CTR_REGS. */ \ |
bc550266 | 1457 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \ |
3fa2798a | 1458 | /* LINK_OR_CTR_REGS. */ \ |
bc550266 | 1459 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \ |
3fa2798a | 1460 | /* SPECIAL_REGS. */ \ |
bc550266 | 1461 | { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \ |
3fa2798a | 1462 | /* SPEC_OR_GEN_REGS. */ \ |
e77e5402 | 1463 | { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \ |
3fa2798a | 1464 | /* CR0_REGS. */ \ |
bc550266 | 1465 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \ |
3fa2798a | 1466 | /* CR_REGS. */ \ |
bc550266 | 1467 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \ |
3fa2798a | 1468 | /* NON_FLOAT_REGS. */ \ |
e77e5402 | 1469 | { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \ |
3fa2798a | 1470 | /* CA_REGS. */ \ |
bc550266 | 1471 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \ |
3fa2798a | 1472 | /* ALL_REGS. */ \ |
e77e5402 | 1473 | { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \ |
6131c8b5 | 1474 | } |
d79df659 | 1475 | |
1476 | /* The same information, inverted: | |
1477 | Return the class number of the smallest class containing | |
1478 | reg number REGNO. This could be a conditional expression | |
1479 | or could index an array. */ | |
1480 | ||
9c878e1b | 1481 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1482 | ||
9c878e1b | 1483 | #define REGNO_REG_CLASS(REGNO) \ |
1d674b45 | 1484 | (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
9c878e1b | 1485 | rs6000_regno_regclass[(REGNO)]) |
1486 | ||
702c5d85 | 1487 | /* Register classes for various constraints that are based on the target |
1488 | switches. */ | |
1489 | enum r6000_reg_class_enum { | |
1490 | RS6000_CONSTRAINT_d, /* fpr registers for double values */ | |
1491 | RS6000_CONSTRAINT_f, /* fpr registers for single values */ | |
1492 | RS6000_CONSTRAINT_v, /* Altivec registers */ | |
1493 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
64dc3674 | 1494 | RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ |
702c5d85 | 1495 | RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
7ee13677 | 1496 | RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
702c5d85 | 1497 | RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
fbacd2bf | 1498 | RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
2a92da31 | 1499 | RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ |
1500 | RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ | |
1501 | RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ | |
1502 | RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ | |
33a2d887 | 1503 | RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ |
81f0e7d0 | 1504 | RS6000_CONSTRAINT_wm, /* VSX register for direct move */ |
8427dff3 | 1505 | RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ |
97d09b30 | 1506 | RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ |
1507 | RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ | |
81f0e7d0 | 1508 | RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ |
702c5d85 | 1509 | RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
33a2d887 | 1510 | RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
fbacd2bf | 1511 | RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ |
1512 | RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ | |
1513 | RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ | |
33a2d887 | 1514 | RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ |
fbacd2bf | 1515 | RS6000_CONSTRAINT_wy, /* VSX register for SF */ |
33a2d887 | 1516 | RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ |
e5cdce14 | 1517 | RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ |
d59ca9c8 | 1518 | RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ |
1519 | RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ | |
1520 | RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ | |
1521 | RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ | |
702c5d85 | 1522 | RS6000_CONSTRAINT_MAX |
1523 | }; | |
1524 | ||
1525 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
d79df659 | 1526 | |
1527 | /* The class value for index registers, and the one for base regs. */ | |
1528 | #define INDEX_REG_CLASS GENERAL_REGS | |
1529 | #define BASE_REG_CLASS BASE_REGS | |
1530 | ||
9c878e1b | 1531 | /* Return whether a given register class can hold VSX objects. */ |
1532 | #define VSX_REG_CLASS_P(CLASS) \ | |
1533 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1534 | ||
2a92da31 | 1535 | /* Return whether a given register class targets general purpose registers. */ |
1536 | #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
1537 | ||
d79df659 | 1538 | /* Given an rtx X being reloaded into a reg required to be |
1539 | in class CLASS, return the class of reg to actually use. | |
1540 | In general this is just CLASS; but on some machines | |
a91f63e4 | 1541 | in some cases it is preferable to use a more restrictive class. |
d79df659 | 1542 | |
1543 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
9e7454d0 | 1544 | floating-point CONST_DOUBLE to force it to be copied to memory. |
a99459e4 | 1545 | |
1546 | We also don't want to reload integer values into floating-point | |
1547 | registers if we can at all help it. In fact, this can | |
5b949046 | 1548 | cause reload to die, if it tries to generate a reload of CTR |
a99459e4 | 1549 | into a FP register and discovers it doesn't have the memory location |
1550 | required. | |
1551 | ||
1552 | ??? Would it be a good idea to have reload do the converse, that is | |
1553 | try to reload floating modes into FP registers if possible? | |
1554 | */ | |
d79df659 | 1555 | |
359e408d | 1556 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
6ff33500 | 1557 | rs6000_preferred_reload_class_ptr (X, CLASS) |
a91f63e4 | 1558 | |
d79df659 | 1559 | /* Return the register class of a scratch register needed to copy IN into |
1560 | or out of a register in CLASS in MODE. If it can be done directly, | |
1561 | NO_REGS is returned. */ | |
1562 | ||
1563 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
6ff33500 | 1564 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
d79df659 | 1565 | |
500c7157 | 1566 | /* If we are copying between FP or AltiVec registers and anything |
c15fcd1f | 1567 | else, we need a memory location. The exception is when we are |
1568 | targeting ppc64 and the move to/from fpr to gpr instructions | |
1569 | are available.*/ | |
1570 | ||
1571 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
6ff33500 | 1572 | rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) |
bcae75c7 | 1573 | |
bcdf945c | 1574 | /* Specify the mode to be used for memory when a secondary memory |
1575 | location is needed. For cpus that cannot load/store SDmode values | |
1576 | from the 64-bit FP registers without using a full 64-bit | |
1577 | load/store, we need a wider mode. */ | |
1578 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1579 | rs6000_secondary_memory_needed_mode (MODE) | |
1580 | ||
d79df659 | 1581 | /* Return the maximum number of consecutive registers |
1582 | needed to represent mode MODE in a register of class CLASS. | |
1583 | ||
9c878e1b | 1584 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1585 | a single reg is enough for two words, unless we have VSX, where the FP | |
1586 | registers can hold 128 bits. */ | |
1587 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
1ffc56fe | 1588 | |
14ee7385 | 1589 | /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ |
1590 | ||
1591 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
6ff33500 | 1592 | rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) |
c5af420e | 1593 | |
d79df659 | 1594 | /* Stack layout; function entry, exit and calling. */ |
1595 | ||
1596 | /* Define this if pushing a word on the stack | |
1597 | makes the stack pointer a smaller address. */ | |
2b785411 | 1598 | #define STACK_GROWS_DOWNWARD 1 |
d79df659 | 1599 | |
20ebc48f | 1600 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1601 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1602 | ||
3ce7ff97 | 1603 | /* Define this to nonzero if the nominal address of the stack frame |
d79df659 | 1604 | is at the high-address end of the local variables; |
1605 | that is, each additional local variable allocated | |
1606 | goes at a more negative offset in the frame. | |
1607 | ||
1608 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1609 | arguments. */ | |
9e46467d | 1610 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
1611 | || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
d79df659 | 1612 | |
a3bbc303 | 1613 | /* Size of the fixed area on the stack */ |
bbd21807 | 1614 | #define RS6000_SAVE_AREA \ |
238f342d | 1615 | ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
bbd21807 | 1616 | << (TARGET_64BIT ? 1 : 0)) |
a3bbc303 | 1617 | |
238f342d | 1618 | /* Stack offset for toc save slot. */ |
1619 | #define RS6000_TOC_SAVE_SLOT \ | |
1620 | ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
6b02f2a5 | 1621 | |
a3bbc303 | 1622 | /* Align an address */ |
74d63f1e | 1623 | #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
a3bbc303 | 1624 | |
d79df659 | 1625 | /* Offset within stack frame to start allocating local variables at. |
1626 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1627 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
a91f63e4 | 1628 | of the first local allocated. |
d79df659 | 1629 | |
1630 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1631 | except for dynamic allocations. So we start after the fixed area and | |
37ea1410 | 1632 | outgoing parameter area. |
1633 | ||
1634 | If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
1635 | space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
1636 | sizes of the fixed area and the parameter area must be a multiple of | |
1637 | STACK_BOUNDARY. */ | |
d79df659 | 1638 | |
359e408d | 1639 | #define STARTING_FRAME_OFFSET \ |
0d6c02bf | 1640 | (FRAME_GROWS_DOWNWARD \ |
1641 | ? 0 \ | |
37ea1410 | 1642 | : (cfun->calls_alloca \ |
1643 | ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
1644 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
1645 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ | |
1646 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
1647 | + RS6000_SAVE_AREA))) | |
359e408d | 1648 | |
1649 | /* Offset from the stack pointer register to an item dynamically | |
1650 | allocated on the stack, e.g., by `alloca'. | |
1651 | ||
1652 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1653 | length of the outgoing arguments. The default is correct for most | |
37ea1410 | 1654 | machines. See `function.c' for details. |
1655 | ||
1656 | This value must be a multiple of STACK_BOUNDARY (hard coded in | |
1657 | `emit-rtl.c'). */ | |
359e408d | 1658 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
37ea1410 | 1659 | RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \ |
1660 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) | |
d79df659 | 1661 | |
1662 | /* If we generate an insn to push BYTES bytes, | |
1663 | this says how many the stack pointer really advances by. | |
1664 | On RS/6000, don't define this because there are no push insns. */ | |
1665 | /* #define PUSH_ROUNDING(BYTES) */ | |
1666 | ||
1667 | /* Offset of first parameter from the argument pointer register value. | |
1668 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1669 | area. */ | |
a3bbc303 | 1670 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
d79df659 | 1671 | |
043c3f91 | 1672 | /* Offset from the argument pointer register value to the top of |
1673 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1674 | register save area. */ | |
1675 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1676 | ||
d79df659 | 1677 | /* Define this if stack space is still allocated for a parameter passed |
1678 | in a register. The value is the number of bytes allocated to this | |
1679 | area. */ | |
02114c95 | 1680 | #define REG_PARM_STACK_SPACE(FNDECL) \ |
1681 | rs6000_reg_parm_stack_space ((FNDECL), false) | |
1682 | ||
1683 | /* Define this macro if space guaranteed when compiling a function body | |
1684 | is different to space required when making a call, a situation that | |
1685 | can arise with K&R style function definitions. */ | |
1686 | #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
1687 | rs6000_reg_parm_stack_space ((FNDECL), true) | |
d79df659 | 1688 | |
1689 | /* Define this if the above stack space is to be considered part of the | |
1690 | space allocated by the caller. */ | |
22c61100 | 1691 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
d79df659 | 1692 | |
1693 | /* This is the difference between the logical top of stack and the actual sp. | |
1694 | ||
7c721ad4 | 1695 | For the RS/6000, sp points past the fixed area. */ |
a3bbc303 | 1696 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
d79df659 | 1697 | |
1698 | /* Define this if the maximum size of all the outgoing args is to be | |
1699 | accumulated and pushed during the prologue. The amount can be | |
abe32cce | 1700 | found in the variable crtl->outgoing_args_size. */ |
4448f543 | 1701 | #define ACCUMULATE_OUTGOING_ARGS 1 |
d79df659 | 1702 | |
d79df659 | 1703 | /* Define how to find the value returned by a library function |
1704 | assuming the value has mode MODE. */ | |
1705 | ||
915e81b8 | 1706 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
d79df659 | 1707 | |
5b53fefa | 1708 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1709 | #define DRAFT_V4_STRUCT_RET 0 | |
e7ce8542 | 1710 | |
6644435d | 1711 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
e7ce8542 | 1712 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
d79df659 | 1713 | |
8cda90b9 | 1714 | /* Mode of stack savearea. |
13c06a53 | 1715 | FUNCTION is VOIDmode because calling convention maintains SP. |
1716 | BLOCK needs Pmode for SP. | |
8cda90b9 | 1717 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1718 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
13c06a53 | 1719 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
33a2d887 | 1720 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
8cda90b9 | 1721 | |
a3bbc303 | 1722 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1723 | #define GP_ARG_MIN_REG 3 | |
1724 | #define GP_ARG_MAX_REG 10 | |
1725 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1726 | ||
1727 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1728 | #define FP_ARG_MIN_REG 33 | |
7a2fc9d6 | 1729 | #define FP_ARG_AIX_MAX_REG 45 |
1730 | #define FP_ARG_V4_MAX_REG 40 | |
231e9287 | 1731 | #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
1732 | ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
a3bbc303 | 1733 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1734 | ||
500c7157 | 1735 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1736 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1737 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1738 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1739 | ||
238f342d | 1740 | /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
1741 | #define AGGR_ARG_NUM_REG 8 | |
1742 | ||
a3bbc303 | 1743 | /* Return registers */ |
1744 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1745 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
500c7157 | 1746 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
238f342d | 1747 | #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
1748 | : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
3c62cae0 | 1749 | #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ |
1750 | ? (ALTIVEC_ARG_RETURN \ | |
7d29bba9 | 1751 | + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ |
238f342d | 1752 | : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) |
a3bbc303 | 1753 | |
7a2fc9d6 | 1754 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
fed06885 | 1755 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
bbd21807 | 1756 | /* Bits in 0x00000001 are unused. */ |
fed06885 | 1757 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1758 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1759 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
ce2aceca | 1760 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7a2fc9d6 | 1761 | |
133acd7c | 1762 | /* We don't have prologue and epilogue functions to save/restore |
1763 | everything for most ABIs. */ | |
1764 | #define WORLD_SAVE_P(INFO) 0 | |
1765 | ||
d79df659 | 1766 | /* 1 if N is a possible register number for a function value |
1767 | as seen by the caller. | |
1768 | ||
500c7157 | 1769 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
37f2c115 | 1770 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1771 | ((N) == GP_ARG_RETURN \ | |
0eb7cd3d | 1772 | || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
df8015ff | 1773 | && TARGET_HARD_FLOAT) \ |
0eb7cd3d | 1774 | || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ |
238f342d | 1775 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
d79df659 | 1776 | |
1777 | /* 1 if N is a possible register number for function argument passing. | |
500c7157 | 1778 | On RS/6000, these are r3-r10 and fp1-fp13. |
1779 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
a3bbc303 | 1780 | #define FUNCTION_ARG_REGNO_P(N) \ |
0eb7cd3d | 1781 | (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
1782 | || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
40bed498 | 1783 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
0eb7cd3d | 1784 | || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
df8015ff | 1785 | && TARGET_HARD_FLOAT)) |
d79df659 | 1786 | \f |
1787 | /* Define a data type for recording info about an argument list | |
1788 | during the scan of that argument list. This data type should | |
1789 | hold all necessary information about the function itself | |
1790 | and about the args processed so far, enough to enable macros | |
1791 | such as FUNCTION_ARG to determine where the next arg should go. | |
1792 | ||
1793 | On the RS/6000, this is a structure. The first element is the number of | |
1794 | total argument words, the second is used to store the next | |
1795 | floating-point register number, and the third says how many more args we | |
a3bbc303 | 1796 | have prototype types for. |
1797 | ||
036c1d46 | 1798 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
6ed6b935 | 1799 | the next available GP register, `fregno' is the next available FP |
036c1d46 | 1800 | register, and `words' is the number of words used on the stack. |
1801 | ||
b5c77702 | 1802 | The varargs/stdarg support requires that this structure's size |
036c1d46 | 1803 | be a multiple of sizeof(int). */ |
a3bbc303 | 1804 | |
1805 | typedef struct rs6000_args | |
1806 | { | |
036c1d46 | 1807 | int words; /* # words used for passing GP registers */ |
fed06885 | 1808 | int fregno; /* next available FP register */ |
500c7157 | 1809 | int vregno; /* next available AltiVec register */ |
fed06885 | 1810 | int nargs_prototype; /* # args left in the current prototype */ |
fed06885 | 1811 | int prototype; /* Whether a prototype was defined */ |
03cd7f2e | 1812 | int stdarg; /* Whether function is a stdarg function. */ |
fed06885 | 1813 | int call_cookie; /* Do special things for this call */ |
036c1d46 | 1814 | int sysv_gregno; /* next available GP register */ |
64c822a6 | 1815 | int intoffset; /* running offset in struct (darwin64) */ |
1816 | int use_stack; /* any part of struct on stack (darwin64) */ | |
b8831040 | 1817 | int floats_in_gpr; /* count of SFmode floats taking up |
1818 | GPR space (darwin64) */ | |
64c822a6 | 1819 | int named; /* false for varargs params */ |
7a2d6ba2 | 1820 | int escapes; /* if function visible outside tu */ |
3f2bdc95 | 1821 | int libcall; /* If this is a compiler generated call. */ |
a3bbc303 | 1822 | } CUMULATIVE_ARGS; |
d79df659 | 1823 | |
d79df659 | 1824 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1825 | for a call to a function whose data type is FNTYPE. | |
1826 | For a library call, FNTYPE is 0. */ | |
1827 | ||
7a2d6ba2 | 1828 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1829 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1830 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
d79df659 | 1831 | |
1832 | /* Similar, but when scanning the definition of a procedure. We always | |
1833 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1834 | ||
30c70355 | 1835 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
7a2d6ba2 | 1836 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1837 | 1000, current_function_decl, VOIDmode) | |
ce2aceca | 1838 | |
1839 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1840 | ||
1841 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
7a2d6ba2 | 1842 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1843 | 0, NULL_TREE, MODE) | |
d79df659 | 1844 | |
030a4821 | 1845 | /* If defined, a C expression which determines whether, and in which |
1846 | direction, to pad out an argument with extra space. The value | |
1847 | should be of type `enum direction': either `upward' to pad above | |
1848 | the argument, `downward' to pad below, or `none' to inhibit | |
1849 | padding. */ | |
1850 | ||
bbd21807 | 1851 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
030a4821 | 1852 | |
5f4cd670 | 1853 | #define PAD_VARARGS_DOWN \ |
1854 | (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
04c6ce8b | 1855 | |
d79df659 | 1856 | /* Output assembler code to FILE to increment profiler label # LABELNO |
4bf5c38d | 1857 | for profiling a function entry. */ |
d79df659 | 1858 | |
1859 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
4bf5c38d | 1860 | output_function_profiler ((FILE), (LABELNO)); |
d79df659 | 1861 | |
1862 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1863 | the stack pointer does not matter. No definition is equivalent to | |
1864 | always zero. | |
1865 | ||
e911aedf | 1866 | On the RS/6000, this is nonzero because we can restore the stack from |
d79df659 | 1867 | its backpointer, which we maintain. */ |
1868 | #define EXIT_IGNORE_STACK 1 | |
1869 | ||
e07cc119 | 1870 | /* Define this macro as a C expression that is nonzero for registers |
1871 | that are used by the epilogue or the return' pattern. The stack | |
1872 | and frame pointer registers are already be assumed to be used as | |
1873 | needed. */ | |
1874 | ||
4ce33b7f | 1875 | #define EPILOGUE_USES(REGNO) \ |
e18e5bf1 | 1876 | ((reload_completed && (REGNO) == LR_REGNO) \ |
6007cde0 | 1877 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
9c878e1b | 1878 | || (crtl->calls_eh_return \ |
454d5a5f | 1879 | && TARGET_AIX \ |
71ac14cb | 1880 | && (REGNO) == 2)) |
8eaf2dd1 | 1881 | |
d79df659 | 1882 | \f |
d79df659 | 1883 | /* Length in units of the trampoline for entering a nested function. */ |
1884 | ||
6b02f2a5 | 1885 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
d79df659 | 1886 | \f |
666bf402 | 1887 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
a61b7cd7 | 1888 | __builtin_return_address (0) should give link register (LR_REGNO), enable |
7c721ad4 | 1889 | this. */ |
666bf402 | 1890 | /* This should be uncommented, so that the link register is used, but |
1891 | currently this would result in unmatched insns and spilling fixed | |
1892 | registers so we'll leave it for another day. When these problems are | |
1893 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1894 | (mrs) */ | |
1895 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
e3718019 | 1896 | |
6b02f2a5 | 1897 | /* Number of bytes into the frame return addresses can be found. See |
1898 | rs6000_stack_info in rs6000.c for more information on how the different | |
1899 | abi's store the return address. */ | |
231e9287 | 1900 | #define RETURN_ADDRESS_OFFSET \ |
1901 | ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
e3718019 | 1902 | |
666bf402 | 1903 | /* The current return address is in link register (65). The return address |
1904 | of anything farther back is accessed normally at an offset of 8 from the | |
1905 | frame pointer. */ | |
8f474918 | 1906 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1907 | (rs6000_return_addr (COUNT, FRAME)) | |
1908 | ||
666bf402 | 1909 | \f |
d79df659 | 1910 | /* Definitions for register eliminations. |
1911 | ||
1912 | We have two registers that can be eliminated on the RS/6000. First, the | |
1913 | frame pointer register can often be eliminated in favor of the stack | |
1914 | pointer register. Secondly, the argument pointer register can always be | |
a65b4c3f | 1915 | eliminated; it is replaced with either the stack or frame pointer. |
1916 | ||
1917 | In addition, we use the elimination mechanism to see if r30 is needed | |
1918 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1919 | by making it an eliminable register. We replace it with itself so that | |
1920 | if it isn't needed, then existing uses won't be modified. */ | |
d79df659 | 1921 | |
1922 | /* This is an array of structures. Each structure initializes one pair | |
1923 | of eliminable registers. The "from" register number is given first, | |
1924 | followed by "to". Eliminations of the same "from" register are listed | |
1925 | in order of preference. */ | |
0d6c02bf | 1926 | #define ELIMINABLE_REGS \ |
1927 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1928 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1929 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1930 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1931 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
fc3feebd | 1932 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
d79df659 | 1933 | |
d79df659 | 1934 | /* Define the offset between two registers, one to be eliminated, and the other |
1935 | its replacement, at the start of a routine. */ | |
549fb3f0 | 1936 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1937 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
d79df659 | 1938 | \f |
1939 | /* Addressing modes, and classification of registers for them. */ | |
1940 | ||
e4e498cf | 1941 | #define HAVE_PRE_DECREMENT 1 |
1942 | #define HAVE_PRE_INCREMENT 1 | |
3072d30e | 1943 | #define HAVE_PRE_MODIFY_DISP 1 |
1944 | #define HAVE_PRE_MODIFY_REG 1 | |
d79df659 | 1945 | |
1946 | /* Macros to check register numbers against specific register classes. */ | |
1947 | ||
1948 | /* These assume that REGNO is a hard or pseudo reg number. | |
1949 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1950 | or a pseudo reg currently allocated to a suitable hard reg. | |
1951 | Since they use reg_renumber, they are safe only once reg_renumber | |
957b2bdc | 1952 | has been allocated, which happens in reginfo.c during register |
1953 | allocation. */ | |
d79df659 | 1954 | |
1955 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1956 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1957 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
0d6c02bf | 1958 | || (REGNO) == FRAME_POINTER_REGNUM \ |
d79df659 | 1959 | : (reg_renumber[REGNO] >= 0 \ |
0d6c02bf | 1960 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1961 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
d79df659 | 1962 | |
1963 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1964 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1965 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
0d6c02bf | 1966 | || (REGNO) == FRAME_POINTER_REGNUM \ |
d79df659 | 1967 | : (reg_renumber[REGNO] > 0 \ |
0d6c02bf | 1968 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1969 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
fd50b071 | 1970 | |
1971 | /* Nonzero if X is a hard reg that can be used as an index | |
1972 | or if it is a pseudo reg in the non-strict case. */ | |
1973 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1974 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1975 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
1976 | ||
1977 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1978 | or if it is a pseudo reg in the non-strict case. */ | |
1979 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1980 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1981 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1982 | ||
d79df659 | 1983 | \f |
1984 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1985 | ||
1986 | #define MAX_REGS_PER_ADDRESS 2 | |
1987 | ||
1988 | /* Recognize any constant value that is a valid address. */ | |
1989 | ||
145ccd50 | 1990 | #define CONSTANT_ADDRESS_P(X) \ |
1991 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1992 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1993 | || GET_CODE (X) == HIGH) | |
d79df659 | 1994 | |
91141d39 | 1995 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
2dbdd8d6 | 1996 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
8631d1da | 1997 | && EASY_VECTOR_15((n) >> 1) \ |
1998 | && ((n) & 1) == 0) | |
91141d39 | 1999 | |
32374e3c | 2000 | #define EASY_VECTOR_MSB(n,mode) \ |
fce02392 | 2001 | ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
32374e3c | 2002 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
2003 | ||
d79df659 | 2004 | \f |
8cda90b9 | 2005 | /* Try a machine-dependent way of reloading an illegitimate address |
2006 | operand. If we find one, push the reload and jump to WIN. This | |
2007 | macro is used in only one place: `find_reloads_address' in reload.c. | |
2008 | ||
9e7454d0 | 2009 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
e3374f82 | 2010 | Note that (X) is evaluated twice; this is safe in current usage. */ |
9e7454d0 | 2011 | |
e2f08fad | 2012 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
2013 | do { \ | |
e3374f82 | 2014 | int win; \ |
6ff33500 | 2015 | (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
e3374f82 | 2016 | (int)(TYPE), (IND_LEVELS), &win); \ |
2017 | if ( win ) \ | |
2018 | goto WIN; \ | |
8cda90b9 | 2019 | } while (0) |
2020 | ||
27e16789 | 2021 | #define FIND_BASE_TERM rs6000_find_base_term |
ea6394e7 | 2022 | \f |
2023 | /* The register number of the register used to address a table of | |
2024 | static data addresses in memory. In some cases this register is | |
2025 | defined by a processor's "application binary interface" (ABI). | |
2026 | When this macro is defined, RTL is generated for this register | |
2027 | once, as with the stack pointer and frame pointer registers. If | |
2028 | this macro is not defined, it is up to the machine-dependent files | |
2029 | to allocate such a register (if necessary). */ | |
2030 | ||
479d644a | 2031 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
92132445 | 2032 | #define PIC_OFFSET_TABLE_REGNUM \ |
2033 | (TARGET_TOC ? TOC_REGISTER \ | |
2034 | : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
2035 | : INVALID_REGNUM) | |
ea6394e7 | 2036 | |
fc3feebd | 2037 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
bbd21807 | 2038 | |
ea6394e7 | 2039 | /* Define this macro if the register defined by |
2040 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
64d9c5f7 | 2041 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
ea6394e7 | 2042 | |
2043 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
2044 | ||
ea6394e7 | 2045 | /* A C expression that is nonzero if X is a legitimate immediate |
2046 | operand on the target machine when generating position independent | |
2047 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
2048 | not check this. You can also assume FLAG_PIC is true, so you need | |
2049 | not check it either. You need not define this macro if all | |
2050 | constants (including `SYMBOL_REF') can be immediate operands when | |
2051 | generating position independent code. */ | |
2052 | ||
2053 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
d79df659 | 2054 | \f |
d79df659 | 2055 | /* Specify the machine mode that this machine uses |
2056 | for the index in the tablejump instruction. */ | |
9439ebf7 | 2057 | #define CASE_VECTOR_MODE SImode |
d79df659 | 2058 | |
25d1d1e9 | 2059 | /* Define as C expression which evaluates to nonzero if the tablejump |
2060 | instruction expects the table to contain offsets from the address of the | |
2061 | table. | |
7c721ad4 | 2062 | Do not define this if the table should contain absolute addresses. */ |
25d1d1e9 | 2063 | #define CASE_VECTOR_PC_RELATIVE 1 |
d79df659 | 2064 | |
d79df659 | 2065 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2066 | #define DEFAULT_SIGNED_CHAR 0 | |
2067 | ||
e84a95ef | 2068 | /* An integer expression for the size in bits of the largest integer machine |
2069 | mode that should actually be used. */ | |
2070 | ||
2071 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
2072 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
2073 | ||
d79df659 | 2074 | /* Max number of bytes we can move from memory to memory |
2075 | in one reasonably fast instruction. */ | |
4086c37e | 2076 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
70309a38 | 2077 | #define MAX_MOVE_MAX 8 |
d79df659 | 2078 | |
2079 | /* Nonzero if access to memory by bytes is no faster than for words. | |
e911aedf | 2080 | Also nonzero if doing byte operations (specifically shifts) in registers |
d79df659 | 2081 | is undesirable. */ |
2082 | #define SLOW_BYTE_ACCESS 1 | |
2083 | ||
29701bb8 | 2084 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD |
2085 | will either zero-extend or sign-extend. The value of this macro should | |
2086 | be the code that says which one of the two operations is implicitly | |
21f1e711 | 2087 | done, UNKNOWN if none. */ |
29701bb8 | 2088 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
e5f1946a | 2089 | |
2090 | /* Define if loading short immediate values into registers sign extends. */ | |
d0b99710 | 2091 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
397cd47b | 2092 | \f |
d79df659 | 2093 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
2094 | is done just by pretending it is already truncated. */ | |
2095 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2096 | ||
d23c4355 | 2097 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
0b6d1b79 | 2098 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
824e9f2e | 2099 | ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
0b6d1b79 | 2100 | |
efa01e7c | 2101 | /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of |
824e9f2e | 2102 | zero. The hardware instructions added in Power9 and the sequences using |
2103 | popcount return 32 or 64. */ | |
efa01e7c | 2104 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
824e9f2e | 2105 | (TARGET_CTZ || TARGET_POPCNTD \ |
2106 | ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
2107 | : ((VALUE) = -1, 2)) | |
d23c4355 | 2108 | |
d79df659 | 2109 | /* Specify the machine mode that pointers have. |
2110 | After generation of rtl, the compiler makes no further distinction | |
2111 | between pointers and any other objects of this machine mode. */ | |
af8303fa | 2112 | extern scalar_int_mode rs6000_pmode; |
2113 | #define Pmode rs6000_pmode | |
d79df659 | 2114 | |
1a4e6801 | 2115 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
29f1acb1 | 2116 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
2117 | ||
d79df659 | 2118 | /* Mode of a function address in a call instruction (for indexing purposes). |
d79df659 | 2119 | Doesn't matter on RS/6000. */ |
aec6ed91 | 2120 | #define FUNCTION_MODE SImode |
d79df659 | 2121 | |
2122 | /* Define this if addresses of constant functions | |
2123 | shouldn't be put through pseudo regs where they can be cse'd. | |
2124 | Desirable on machines where ordinary constants are expensive | |
2125 | but a CALL with constant address is cheap. */ | |
93516111 | 2126 | #define NO_FUNCTION_CSE 1 |
d79df659 | 2127 | |
d78882c8 | 2128 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
2a33b158 | 2129 | few bits. |
2130 | ||
2131 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2132 | have been dropped from the PowerPC architecture. */ | |
55920223 | 2133 | #define SHIFT_COUNT_TRUNCATED 0 |
d79df659 | 2134 | |
d79df659 | 2135 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
2136 | should be adjusted to reflect any required changes. This macro is used when | |
2137 | there is some systematic length adjustment required that would be difficult | |
2138 | to express in the length attribute. */ | |
2139 | ||
2140 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2141 | ||
ac313e39 | 2142 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2143 | COMPARE, return the mode to be used for the comparison. For | |
2144 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2145 | for unsigned comparisons. CCEQmode should be used when we are | |
2146 | doing an inequality comparison on the result of a | |
2147 | comparison. CCmode should be used in all other cases. */ | |
3b82fbed | 2148 | |
fda4fc2e | 2149 | #define SELECT_CC_MODE(OP,X,Y) \ |
e284b8fb | 2150 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
3b82fbed | 2151 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
6720e96c | 2152 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
3b82fbed | 2153 | ? CCEQmode : CCmode)) |
d79df659 | 2154 | |
0c51108c | 2155 | /* Can the condition code MODE be safely reversed? This is safe in |
2156 | all cases on this port, because at present it doesn't use the | |
2157 | trapping FP comparisons (fcmpo). */ | |
2158 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2159 | ||
2160 | /* Given a condition code and a mode, return the inverse condition. */ | |
2161 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
2162 | ||
d79df659 | 2163 | \f |
2164 | /* Control the assembler format that we output. */ | |
2165 | ||
cb30236b | 2166 | /* A C string constant describing how to begin a comment in the target |
2167 | assembler language. The compiler assumes that the comment will end at | |
2168 | the end of the line. */ | |
2169 | #define ASM_COMMENT_START " #" | |
6f5f357f | 2170 | |
bda6fa4d | 2171 | /* Flag to say the TOC is initialized */ |
2172 | extern int toc_initialized; | |
2173 | ||
d79df659 | 2174 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2175 | it. Otherwise, it is written the usual way. | |
2176 | ||
2177 | On the RS/6000, toc entries are handled this way. */ | |
2178 | ||
e2f08fad | 2179 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2180 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2181 | { \ | |
2182 | output_toc (FILE, X, LABELNO, MODE); \ | |
2183 | goto WIN; \ | |
2184 | } \ | |
d79df659 | 2185 | } |
2186 | ||
a60dd68f | 2187 | #ifdef HAVE_GAS_WEAK |
2188 | #define RS6000_WEAK 1 | |
2189 | #else | |
2190 | #define RS6000_WEAK 0 | |
2191 | #endif | |
84fb9e97 | 2192 | |
ee0125fb | 2193 | #if RS6000_WEAK |
2194 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
3b118414 | 2195 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
2196 | rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
ee0125fb | 2197 | #endif |
2198 | ||
b0988db1 | 2199 | #if HAVE_GAS_WEAKREF |
2200 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
2201 | do \ | |
2202 | { \ | |
2203 | fputs ("\t.weakref\t", (FILE)); \ | |
2204 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2205 | fputs (", ", (FILE)); \ | |
2206 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2207 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2208 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2209 | { \ | |
2210 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
2211 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2212 | fputs (", .", (FILE)); \ | |
2213 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2214 | } \ | |
2215 | fputc ('\n', (FILE)); \ | |
2216 | } while (0) | |
2217 | #endif | |
2218 | ||
ee0125fb | 2219 | /* This implements the `alias' attribute. */ |
2220 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2221 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2222 | do \ | |
2223 | { \ | |
2224 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2225 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2226 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
66ebfa67 | 2227 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
ee0125fb | 2228 | { \ |
2229 | if (TREE_PUBLIC (DECL)) \ | |
2230 | { \ | |
2231 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2232 | { \ | |
2233 | fputs ("\t.globl\t.", FILE); \ | |
17fb2af4 | 2234 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
ee0125fb | 2235 | putc ('\n', FILE); \ |
2236 | } \ | |
2237 | } \ | |
2238 | else if (TARGET_XCOFF) \ | |
2239 | { \ | |
f8918696 | 2240 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
2241 | { \ | |
2242 | fputs ("\t.lglobl\t.", FILE); \ | |
2243 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2244 | putc ('\n', FILE); \ | |
2245 | fputs ("\t.lglobl\t", FILE); \ | |
2246 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2247 | putc ('\n', FILE); \ | |
2248 | } \ | |
ee0125fb | 2249 | } \ |
2250 | fputs ("\t.set\t.", FILE); \ | |
17fb2af4 | 2251 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
ee0125fb | 2252 | fputs (",.", FILE); \ |
17fb2af4 | 2253 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
ee0125fb | 2254 | fputc ('\n', FILE); \ |
2255 | } \ | |
2256 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2257 | } \ | |
2258 | while (0) | |
84fb9e97 | 2259 | |
92c473b8 | 2260 | #define TARGET_ASM_FILE_START rs6000_file_start |
2261 | ||
d79df659 | 2262 | /* Output to assembler file text saying following lines |
2263 | may contain character constants, extra white space, comments, etc. */ | |
2264 | ||
2265 | #define ASM_APP_ON "" | |
2266 | ||
2267 | /* Output to assembler file text saying following lines | |
2268 | no longer contain unusual constructs. */ | |
2269 | ||
2270 | #define ASM_APP_OFF "" | |
2271 | ||
d79df659 | 2272 | /* How to refer to registers in assembler output. |
2273 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2274 | ||
7c721ad4 | 2275 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
a91f63e4 | 2276 | |
2277 | #define REGISTER_NAMES \ | |
2278 | { \ | |
2279 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2280 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2281 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2282 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2283 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2284 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2285 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2286 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2287 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2288 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2289 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2290 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2291 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2292 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2293 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2294 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2295 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2296 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2297 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2298 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2299 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2300 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2301 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2302 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2303 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2304 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2305 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2306 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2307 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2308 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2309 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2310 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2311 | \ | |
2312 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2313 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2314 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2315 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2316 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2317 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2318 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2319 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2320 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2321 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2322 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2323 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2324 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2325 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2326 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2327 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2328 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2329 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2330 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2331 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2332 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2333 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2334 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2335 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2336 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2337 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2338 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2339 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2340 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2341 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2342 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2343 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2344 | \ | |
ca1ad495 | 2345 | &rs6000_reg_names[64][0], /* was mq */ \ |
a91f63e4 | 2346 | &rs6000_reg_names[65][0], /* lr */ \ |
2347 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2348 | &rs6000_reg_names[67][0], /* ap */ \ | |
2349 | \ | |
2350 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2351 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2352 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2353 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2354 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2355 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2356 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2357 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
359e408d | 2358 | \ |
ce81d1c2 | 2359 | &rs6000_reg_names[76][0], /* ca */ \ |
500c7157 | 2360 | \ |
2361 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2362 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2363 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2364 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2365 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2366 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2367 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2368 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2369 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2370 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2371 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2372 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2373 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2374 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2375 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2376 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2377 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2378 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2379 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2380 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2381 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2382 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2383 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2384 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2385 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2386 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2387 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2388 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2389 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2390 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2391 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2392 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2393 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
3a1f8574 | 2394 | &rs6000_reg_names[110][0], /* vscr */ \ |
e77e5402 | 2395 | &rs6000_reg_names[111][0], /* sfp */ \ |
2396 | &rs6000_reg_names[112][0], /* tfhar */ \ | |
2397 | &rs6000_reg_names[113][0], /* tfiar */ \ | |
2398 | &rs6000_reg_names[114][0], /* texasr */ \ | |
a91f63e4 | 2399 | } |
2400 | ||
d79df659 | 2401 | /* Table of additional register names to use in user input. */ |
2402 | ||
2403 | #define ADDITIONAL_REGISTER_NAMES \ | |
a665c153 | 2404 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2405 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2406 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2407 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2408 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2409 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2410 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2411 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2412 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2413 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2414 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2415 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2416 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2417 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2418 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2419 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
500c7157 | 2420 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2421 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2422 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2423 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2424 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2425 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2426 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2427 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
3a1f8574 | 2428 | {"vrsave", 109}, {"vscr", 110}, \ |
ca1ad495 | 2429 | /* no additional names for: lr, ctr, ap */ \ |
a665c153 | 2430 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
2431 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
9c878e1b | 2432 | {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
ce81d1c2 | 2433 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
2434 | {"xer", 76}, \ | |
9c878e1b | 2435 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2436 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2437 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2438 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2439 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2440 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2441 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2442 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2443 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
2444 | {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ | |
2445 | {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ | |
2446 | {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ | |
2447 | {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ | |
2448 | {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ | |
2449 | {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ | |
2450 | {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ | |
5088e479 | 2451 | {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ |
2452 | /* Transactional Memory Facility (HTM) Registers. */ \ | |
e77e5402 | 2453 | {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \ |
3fa2798a | 2454 | } |
d79df659 | 2455 | |
d79df659 | 2456 | /* This is how to output an element of a case-vector that is relative. */ |
2457 | ||
9439ebf7 | 2458 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
8f84ead8 | 2459 | do { char buf[100]; \ |
9439ebf7 | 2460 | fputs ("\t.long ", FILE); \ |
8f84ead8 | 2461 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2462 | assemble_name (FILE, buf); \ | |
66455505 | 2463 | putc ('-', FILE); \ |
8f84ead8 | 2464 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2465 | assemble_name (FILE, buf); \ | |
66455505 | 2466 | putc ('\n', FILE); \ |
8f84ead8 | 2467 | } while (0) |
d79df659 | 2468 | |
2469 | /* This is how to output an assembler line | |
2470 | that says to advance the location counter | |
2471 | to a multiple of 2**LOG bytes. */ | |
2472 | ||
2473 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2474 | if ((LOG) != 0) \ | |
2475 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2476 | ||
0683140a | 2477 | /* How to align the given loop. */ |
2478 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2479 | ||
ed11924e | 2480 | /* Alignment guaranteed by __builtin_malloc. */ |
2481 | /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
2482 | However, specifying the stronger guarantee currently leads to | |
2483 | a regression in SPEC CPU2006 437.leslie3d. The stronger | |
2484 | guarantee should be implemented here once that's fixed. */ | |
2485 | #define MALLOC_ABI_ALIGNMENT (64) | |
2486 | ||
bbd21807 | 2487 | /* Pick up the return address upon entry to a procedure. Used for |
2488 | dwarf2 unwind information. This also enables the table driven | |
2489 | mechanism. */ | |
2490 | ||
e18e5bf1 | 2491 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2492 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
bbd21807 | 2493 | |
4ce33b7f | 2494 | /* Describe how we implement __builtin_eh_return. */ |
2495 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2496 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2497 | ||
d79df659 | 2498 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2499 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2500 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2501 | ||
2502 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2503 | ||
2504 | /* Define which CODE values are valid. */ | |
2505 | ||
f28fe1ac | 2506 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
d79df659 | 2507 | |
2508 | /* Print a memory address as an operand to reference that memory location. */ | |
2509 | ||
2510 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2511 | ||
3257ccd1 | 2512 | /* For switching between functions with different target attributes. */ |
2513 | #define SWITCHABLE_TARGET 1 | |
2514 | ||
6b02f2a5 | 2515 | /* uncomment for disabling the corresponding default options */ |
2516 | /* #define MACHINE_no_sched_interblock */ | |
2517 | /* #define MACHINE_no_sched_speculative */ | |
2518 | /* #define MACHINE_no_sched_speculative_load */ | |
2519 | ||
ea6394e7 | 2520 | /* General flags. */ |
33e46abb | 2521 | extern int frame_pointer_needed; |
500c7157 | 2522 | |
0375b229 | 2523 | /* Classification of the builtin functions as to which switches enable the |
2524 | builtin, and what attributes it should have. We used to use the target | |
2525 | flags macros, but we've run out of bits, so we now map the options into new | |
2526 | settings used here. */ | |
2527 | ||
2528 | /* Builtin attributes. */ | |
2529 | #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
2530 | #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
2531 | #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
2532 | #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
2533 | #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
2534 | #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
0375b229 | 2535 | #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ |
2536 | #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
2537 | ||
2538 | #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
f9debd38 | 2539 | #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor |
2540 | modifies global state. */ | |
26a51591 | 2541 | #define RS6000_BTC_PURE 0x00000200 /* reads global |
2542 | state/mem and does | |
2543 | not modify global state. */ | |
0375b229 | 2544 | #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ |
2545 | #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
2546 | ||
2547 | /* Miscellaneous information. */ | |
5088e479 | 2548 | #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ |
2549 | #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
cb2c281a | 2550 | #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ |
2551 | #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
5088e479 | 2552 | #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ |
605afdd6 | 2553 | |
2554 | /* Convenience macros to document the instruction type. */ | |
0375b229 | 2555 | #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
2556 | #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
2557 | ||
2558 | /* Builtin targets. For now, we reuse the masks for those options that are in | |
9d20c62c | 2559 | target flags, and pick two random bits for paired and ldbl128, which |
1d2fa40a | 2560 | aren't in target_flags. */ |
1144b872 | 2561 | #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
0375b229 | 2562 | #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ |
9534dff5 | 2563 | #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ |
0375b229 | 2564 | #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ |
81f0e7d0 | 2565 | #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ |
d94e6223 | 2566 | #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ |
17c32c4a | 2567 | #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ |
81f0e7d0 | 2568 | #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ |
5088e479 | 2569 | #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ |
0375b229 | 2570 | #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ |
2571 | #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
2572 | #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
2573 | #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
2574 | #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
2575 | #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
0375b229 | 2576 | #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ |
ac0adecc | 2577 | #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ |
d44f2f7c | 2578 | #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ |
1d2fa40a | 2579 | #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ |
26a51591 | 2580 | #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ |
7d29bba9 | 2581 | #define RS6000_BTM_FLOAT128 MASK_FLOAT128_TYPE /* IEEE 128-bit float. */ |
0375b229 | 2582 | |
2583 | #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
2584 | | RS6000_BTM_VSX \ | |
81f0e7d0 | 2585 | | RS6000_BTM_P8_VECTOR \ |
d94e6223 | 2586 | | RS6000_BTM_P9_VECTOR \ |
17c32c4a | 2587 | | RS6000_BTM_P9_MISC \ |
ec15042a | 2588 | | RS6000_BTM_MODULO \ |
81f0e7d0 | 2589 | | RS6000_BTM_CRYPTO \ |
0375b229 | 2590 | | RS6000_BTM_FRE \ |
2591 | | RS6000_BTM_FRES \ | |
2592 | | RS6000_BTM_FRSQRTE \ | |
2593 | | RS6000_BTM_FRSQRTES \ | |
5088e479 | 2594 | | RS6000_BTM_HTM \ |
0375b229 | 2595 | | RS6000_BTM_POPCNTD \ |
ac0adecc | 2596 | | RS6000_BTM_CELL \ |
d44f2f7c | 2597 | | RS6000_BTM_DFP \ |
1d2fa40a | 2598 | | RS6000_BTM_HARD_FLOAT \ |
2275a11d | 2599 | | RS6000_BTM_LDBL128 \ |
2600 | | RS6000_BTM_FLOAT128) | |
0375b229 | 2601 | |
2602 | /* Define builtin enum index. */ | |
2603 | ||
26a51591 | 2604 | #undef RS6000_BUILTIN_0 |
0375b229 | 2605 | #undef RS6000_BUILTIN_1 |
2606 | #undef RS6000_BUILTIN_2 | |
2607 | #undef RS6000_BUILTIN_3 | |
2608 | #undef RS6000_BUILTIN_A | |
2609 | #undef RS6000_BUILTIN_D | |
5088e479 | 2610 | #undef RS6000_BUILTIN_H |
0375b229 | 2611 | #undef RS6000_BUILTIN_P |
2612 | #undef RS6000_BUILTIN_Q | |
0375b229 | 2613 | #undef RS6000_BUILTIN_X |
2614 | ||
26a51591 | 2615 | #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
0375b229 | 2616 | #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
2617 | #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2618 | #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2619 | #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2620 | #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
5088e479 | 2621 | #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
0375b229 | 2622 | #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
2623 | #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
0375b229 | 2624 | #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
605afdd6 | 2625 | |
500c7157 | 2626 | enum rs6000_builtins |
2627 | { | |
605afdd6 | 2628 | #include "rs6000-builtin.def" |
702c5d85 | 2629 | |
65441f6f | 2630 | RS6000_BUILTIN_COUNT |
2631 | }; | |
2632 | ||
26a51591 | 2633 | #undef RS6000_BUILTIN_0 |
0375b229 | 2634 | #undef RS6000_BUILTIN_1 |
2635 | #undef RS6000_BUILTIN_2 | |
2636 | #undef RS6000_BUILTIN_3 | |
2637 | #undef RS6000_BUILTIN_A | |
2638 | #undef RS6000_BUILTIN_D | |
5088e479 | 2639 | #undef RS6000_BUILTIN_H |
0375b229 | 2640 | #undef RS6000_BUILTIN_P |
2641 | #undef RS6000_BUILTIN_Q | |
0375b229 | 2642 | #undef RS6000_BUILTIN_X |
605afdd6 | 2643 | |
65441f6f | 2644 | enum rs6000_builtin_type_index |
2645 | { | |
2646 | RS6000_BTI_NOT_OPAQUE, | |
2647 | RS6000_BTI_opaque_V2SI, | |
2648 | RS6000_BTI_opaque_V2SF, | |
2649 | RS6000_BTI_opaque_p_V2SI, | |
2650 | RS6000_BTI_opaque_V4SI, | |
2651 | RS6000_BTI_V16QI, | |
ae61c502 | 2652 | RS6000_BTI_V1TI, |
65441f6f | 2653 | RS6000_BTI_V2SI, |
2654 | RS6000_BTI_V2SF, | |
702c5d85 | 2655 | RS6000_BTI_V2DI, |
2656 | RS6000_BTI_V2DF, | |
65441f6f | 2657 | RS6000_BTI_V4HI, |
2658 | RS6000_BTI_V4SI, | |
2659 | RS6000_BTI_V4SF, | |
2660 | RS6000_BTI_V8HI, | |
2661 | RS6000_BTI_unsigned_V16QI, | |
ae61c502 | 2662 | RS6000_BTI_unsigned_V1TI, |
65441f6f | 2663 | RS6000_BTI_unsigned_V8HI, |
2664 | RS6000_BTI_unsigned_V4SI, | |
702c5d85 | 2665 | RS6000_BTI_unsigned_V2DI, |
65441f6f | 2666 | RS6000_BTI_bool_char, /* __bool char */ |
2667 | RS6000_BTI_bool_short, /* __bool short */ | |
2668 | RS6000_BTI_bool_int, /* __bool int */ | |
702c5d85 | 2669 | RS6000_BTI_bool_long, /* __bool long */ |
65441f6f | 2670 | RS6000_BTI_pixel, /* __pixel */ |
2671 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
2672 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2673 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
702c5d85 | 2674 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
65441f6f | 2675 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2676 | RS6000_BTI_long, /* long_integer_type_node */ | |
2677 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
a501acda | 2678 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2679 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
65441f6f | 2680 | RS6000_BTI_INTQI, /* intQI_type_node */ |
2681 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
2682 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2683 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
2684 | RS6000_BTI_INTSI, /* intSI_type_node */ | |
2685 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
702c5d85 | 2686 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2687 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
ae61c502 | 2688 | RS6000_BTI_INTTI, /* intTI_type_node */ |
2689 | RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
65441f6f | 2690 | RS6000_BTI_float, /* float_type_node */ |
702c5d85 | 2691 | RS6000_BTI_double, /* double_type_node */ |
ac0adecc | 2692 | RS6000_BTI_long_double, /* long_double_type_node */ |
2693 | RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
2694 | RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
65441f6f | 2695 | RS6000_BTI_void, /* void_type_node */ |
94f623e1 | 2696 | RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
2697 | RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
2275a11d | 2698 | RS6000_BTI_const_str, /* pointer to const char * */ |
65441f6f | 2699 | RS6000_BTI_MAX |
500c7157 | 2700 | }; |
65441f6f | 2701 | |
2702 | ||
2703 | #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
2704 | #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
2705 | #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
2706 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
2707 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
ae61c502 | 2708 | #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
702c5d85 | 2709 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2710 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
65441f6f | 2711 | #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
2712 | #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
2713 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
2714 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2715 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2716 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2717 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
ae61c502 | 2718 | #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
65441f6f | 2719 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
2720 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
702c5d85 | 2721 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
65441f6f | 2722 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2723 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2724 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
702c5d85 | 2725 | #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
65441f6f | 2726 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2727 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2728 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2729 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
702c5d85 | 2730 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
65441f6f | 2731 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2732 | ||
a501acda | 2733 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2734 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
65441f6f | 2735 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2736 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2737 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2738 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2739 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2740 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2741 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2742 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
702c5d85 | 2743 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2744 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
ae61c502 | 2745 | #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
2746 | #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
65441f6f | 2747 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
702c5d85 | 2748 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
ac0adecc | 2749 | #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
2750 | #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
2751 | #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
65441f6f | 2752 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
94f623e1 | 2753 | #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
2754 | #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
2275a11d | 2755 | #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) |
65441f6f | 2756 | |
2757 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2758 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2759 | ||
219f3246 | 2760 | #define TARGET_SUPPORTS_WIDE_INT 1 |
7d29bba9 | 2761 | |
2762 | #if (GCC_VERSION >= 3000) | |
2763 | #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
2764 | #endif |