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4673c1a0 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
aad93da1 | 2 | Copyright (C) 1999-2017 Free Software Foundation, Inc. |
4673c1a0 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
0c0a8ea5 | 4 | Ulrich Weigand (uweigand@de.ibm.com). |
e68d6a13 | 5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) |
4673c1a0 | 6 | |
1e98c8f3 | 7 | This file is part of GCC. |
4673c1a0 | 8 | |
1e98c8f3 | 9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
038d1e19 | 11 | Software Foundation; either version 3, or (at your option) any later |
1e98c8f3 | 12 | version. |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
4673c1a0 | 18 | |
19 | You should have received a copy of the GNU General Public License | |
038d1e19 | 20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
4673c1a0 | 22 | |
23 | #ifndef _S390_H | |
24 | #define _S390_H | |
25 | ||
b8c0043c | 26 | /* Optional architectural facilities supported by the processor. */ |
27 | ||
28 | enum processor_flags | |
29 | { | |
30 | PF_IEEE_FLOAT = 1, | |
31 | PF_ZARCH = 2, | |
163277cf | 32 | PF_LONG_DISPLACEMENT = 4, |
0c2edaa7 | 33 | PF_EXTIMM = 8, |
a850370e | 34 | PF_DFP = 16, |
33d033da | 35 | PF_Z10 = 32, |
81769881 | 36 | PF_Z196 = 64, |
5ada7a14 | 37 | PF_ZEC12 = 128, |
cc79fcc9 | 38 | PF_TX = 256, |
39 | PF_Z13 = 512, | |
c9213ca0 | 40 | PF_VX = 1024, |
41 | PF_ARCH12 = 2048, | |
42 | PF_VXE = 4096 | |
b8c0043c | 43 | }; |
44 | ||
23911610 | 45 | /* This is necessary to avoid a warning about comparing different enum |
46 | types. */ | |
c9213ca0 | 47 | #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_2964_Z13 ? PROCESSOR_2964_Z13 : s390_tune )) |
23911610 | 48 | |
e68d6a13 | 49 | /* These flags indicate that the generated code should run on a cpu |
50 | providing the respective hardware facility regardless of the | |
51 | current cpu mode (ESA or z/Architecture). */ | |
52 | ||
b8c0043c | 53 | #define TARGET_CPU_IEEE_FLOAT \ |
54 | (s390_arch_flags & PF_IEEE_FLOAT) | |
7a0cee35 | 55 | #define TARGET_CPU_IEEE_FLOAT_P(opts) \ |
56 | (opts->x_s390_arch_flags & PF_IEEE_FLOAT) | |
b8c0043c | 57 | #define TARGET_CPU_ZARCH \ |
58 | (s390_arch_flags & PF_ZARCH) | |
7a0cee35 | 59 | #define TARGET_CPU_ZARCH_P(opts) \ |
60 | (opts->x_s390_arch_flags & PF_ZARCH) | |
b8c0043c | 61 | #define TARGET_CPU_LONG_DISPLACEMENT \ |
62 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
7a0cee35 | 63 | #define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \ |
64 | (opts->x_s390_arch_flags & PF_LONG_DISPLACEMENT) | |
163277cf | 65 | #define TARGET_CPU_EXTIMM \ |
7a0cee35 | 66 | (s390_arch_flags & PF_EXTIMM) |
67 | #define TARGET_CPU_EXTIMM_P(opts) \ | |
68 | (opts->x_s390_arch_flags & PF_EXTIMM) | |
0c2edaa7 | 69 | #define TARGET_CPU_DFP \ |
7a0cee35 | 70 | (s390_arch_flags & PF_DFP) |
71 | #define TARGET_CPU_DFP_P(opts) \ | |
72 | (opts->x_s390_arch_flags & PF_DFP) | |
a850370e | 73 | #define TARGET_CPU_Z10 \ |
7a0cee35 | 74 | (s390_arch_flags & PF_Z10) |
75 | #define TARGET_CPU_Z10_P(opts) \ | |
76 | (opts->x_s390_arch_flags & PF_Z10) | |
33d033da | 77 | #define TARGET_CPU_Z196 \ |
7a0cee35 | 78 | (s390_arch_flags & PF_Z196) |
79 | #define TARGET_CPU_Z196_P(opts) \ | |
80 | (opts->x_s390_arch_flags & PF_Z196) | |
81769881 | 81 | #define TARGET_CPU_ZEC12 \ |
7a0cee35 | 82 | (s390_arch_flags & PF_ZEC12) |
83 | #define TARGET_CPU_ZEC12_P(opts) \ | |
84 | (opts->x_s390_arch_flags & PF_ZEC12) | |
5ada7a14 | 85 | #define TARGET_CPU_HTM \ |
7a0cee35 | 86 | (s390_arch_flags & PF_TX) |
87 | #define TARGET_CPU_HTM_P(opts) \ | |
88 | (opts->x_s390_arch_flags & PF_TX) | |
cc79fcc9 | 89 | #define TARGET_CPU_Z13 \ |
7a0cee35 | 90 | (s390_arch_flags & PF_Z13) |
91 | #define TARGET_CPU_Z13_P(opts) \ | |
c9213ca0 | 92 | (opts->x_s390_arch_flags & PF_Z13) |
cc79fcc9 | 93 | #define TARGET_CPU_VX \ |
c9213ca0 | 94 | (s390_arch_flags & PF_VX) |
7a0cee35 | 95 | #define TARGET_CPU_VX_P(opts) \ |
96 | (opts->x_s390_arch_flags & PF_VX) | |
c9213ca0 | 97 | #define TARGET_CPU_ARCH12 \ |
98 | (s390_arch_flags & PF_ARCH12) | |
99 | #define TARGET_CPU_ARCH12_P(opts) \ | |
100 | (opts->x_s390_arch_flags & PF_ARCH12) | |
101 | #define TARGET_CPU_VXE \ | |
102 | (s390_arch_flags & PF_VXE) | |
103 | #define TARGET_CPU_VXE_P(opts) \ | |
104 | (opts->x_s390_arch_flags & PF_VXE) | |
7a0cee35 | 105 | |
106 | #define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts)) | |
b8c0043c | 107 | |
e68d6a13 | 108 | /* These flags indicate that the generated code should run on a cpu |
109 | providing the respective hardware facility when run in | |
110 | z/Architecture mode. */ | |
111 | ||
b8c0043c | 112 | #define TARGET_LONG_DISPLACEMENT \ |
7a0cee35 | 113 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) |
114 | #define TARGET_LONG_DISPLACEMENT_P(opts) \ | |
115 | (TARGET_ZARCH_P (opts->x_target_flags) \ | |
116 | && TARGET_CPU_LONG_DISPLACEMENT_P (opts)) | |
163277cf | 117 | #define TARGET_EXTIMM \ |
7a0cee35 | 118 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) |
119 | #define TARGET_EXTIMM_P(opts) \ | |
120 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts)) | |
0c2edaa7 | 121 | #define TARGET_DFP \ |
7a0cee35 | 122 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
123 | #define TARGET_DFP_P(opts) \ | |
124 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \ | |
125 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
a850370e | 126 | #define TARGET_Z10 \ |
7a0cee35 | 127 | (TARGET_ZARCH && TARGET_CPU_Z10) |
128 | #define TARGET_Z10_P(opts) \ | |
129 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts)) | |
33d033da | 130 | #define TARGET_Z196 \ |
7a0cee35 | 131 | (TARGET_ZARCH && TARGET_CPU_Z196) |
132 | #define TARGET_Z196_P(opts) \ | |
133 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts)) | |
81769881 | 134 | #define TARGET_ZEC12 \ |
7a0cee35 | 135 | (TARGET_ZARCH && TARGET_CPU_ZEC12) |
136 | #define TARGET_ZEC12_P(opts) \ | |
137 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts)) | |
ee2dbc39 | 138 | #define TARGET_HTM (TARGET_OPT_HTM) |
7a0cee35 | 139 | #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags)) |
cc79fcc9 | 140 | #define TARGET_Z13 \ |
7a0cee35 | 141 | (TARGET_ZARCH && TARGET_CPU_Z13) |
142 | #define TARGET_Z13_P(opts) \ | |
143 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts)) | |
cc79fcc9 | 144 | #define TARGET_VX \ |
7a0cee35 | 145 | (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) |
146 | #define TARGET_VX_P(opts) \ | |
147 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \ | |
148 | && TARGET_OPT_VX_P (opts->x_target_flags) \ | |
149 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
c9213ca0 | 150 | #define TARGET_ARCH12 (TARGET_ZARCH && TARGET_CPU_ARCH12) |
151 | #define TARGET_ARCH12_P(opts) \ | |
152 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ARCH12_P (opts)) | |
153 | #define TARGET_VXE \ | |
154 | (TARGET_VX && TARGET_CPU_VXE) | |
155 | #define TARGET_VXE_P(opts) \ | |
156 | (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) | |
7a0cee35 | 157 | |
158 | #ifdef HAVE_AS_MACHINE_MACHINEMODE | |
159 | #define S390_USE_TARGET_ATTRIBUTE 1 | |
160 | #else | |
161 | #define S390_USE_TARGET_ATTRIBUTE 0 | |
162 | #endif | |
163 | ||
164 | #ifdef HAVE_AS_ARCHITECTURE_MODIFIERS | |
165 | #define S390_USE_ARCHITECTURE_MODIFIERS 1 | |
166 | #else | |
167 | #define S390_USE_ARCHITECTURE_MODIFIERS 0 | |
168 | #endif | |
169 | ||
170 | #if S390_USE_TARGET_ATTRIBUTE | |
171 | /* For switching between functions with different target attributes. */ | |
172 | #define SWITCHABLE_TARGET 1 | |
173 | #endif | |
33d033da | 174 | |
ba0e61d6 | 175 | #define TARGET_SUPPORTS_WIDE_INT 1 |
176 | ||
cc79fcc9 | 177 | /* Use the ABI introduced with IBM z13: |
178 | - pass vector arguments <= 16 bytes in VRs | |
179 | - align *all* vector types to 8 bytes */ | |
180 | #define TARGET_VX_ABI TARGET_VX | |
33d033da | 181 | |
182 | #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) | |
6c3a2301 | 183 | |
7718b866 | 184 | /* Run-time target specification. */ |
4673c1a0 | 185 | |
d2351d8b | 186 | /* Defaults for option flags defined only on some subtargets. */ |
187 | #ifndef TARGET_TPF_PROFILING | |
188 | #define TARGET_TPF_PROFILING 0 | |
189 | #endif | |
190 | ||
b33c41a1 | 191 | /* This will be overridden by OS headers. */ |
192 | #define TARGET_TPF 0 | |
193 | ||
7718b866 | 194 | /* Target CPU builtins. */ |
07f32359 | 195 | #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) |
4673c1a0 | 196 | |
d50213e6 | 197 | #ifdef DEFAULT_TARGET_64BIT |
cc79fcc9 | 198 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ |
199 | | MASK_OPT_HTM | MASK_OPT_VX) | |
d50213e6 | 200 | #else |
0c2edaa7 | 201 | #define TARGET_DEFAULT 0 |
d50213e6 | 202 | #endif |
203 | ||
b8c0043c | 204 | /* Support for configure-time defaults. */ |
205 | #define OPTION_DEFAULT_SPECS \ | |
206 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
207 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
208 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
209 | ||
058194ac | 210 | #ifdef __s390__ |
db249f37 | 211 | extern const char *s390_host_detect_local_cpu (int argc, const char **argv); |
212 | # define EXTRA_SPEC_FUNCTIONS \ | |
213 | { "local_cpu_detect", s390_host_detect_local_cpu }, | |
214 | ||
f369dcc9 | 215 | #define MARCH_MTUNE_NATIVE_SPECS \ |
216 | "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \ | |
217 | "%{march=native:%<march=native" \ | |
218 | " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}" | |
058194ac | 219 | #else |
220 | # define MARCH_MTUNE_NATIVE_SPECS "" | |
221 | #endif | |
db249f37 | 222 | |
b8c0043c | 223 | #ifdef DEFAULT_TARGET_64BIT |
f369dcc9 | 224 | #define S390_TARGET_BITS_STRING "64" |
b8c0043c | 225 | #else |
f369dcc9 | 226 | #define S390_TARGET_BITS_STRING "31" |
227 | #endif | |
228 | ||
229 | /* Defaulting rules. */ | |
b8c0043c | 230 | #define DRIVER_SELF_SPECS \ |
f369dcc9 | 231 | MARCH_MTUNE_NATIVE_SPECS, \ |
232 | "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ | |
b8c0043c | 233 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ |
3bd8520f | 234 | "%{!march=*:-march=z900}" |
b8c0043c | 235 | |
27784c70 | 236 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
d1191819 | 237 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
238 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
239 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
240 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
241 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
242 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
243 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
244 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
245 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
246 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
247 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
248 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
249 | ||
250 | /* The following values are different for DFP. */ | |
251 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
252 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
253 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
254 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
255 | ||
ffead1ca | 256 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
93f564d6 | 257 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
d1191819 | 258 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
259 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
93f564d6 | 260 | | S390_TDC_NEGATIVE_INFINITY \ |
261 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
262 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) | |
263 | ||
27784c70 | 264 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
265 | | S390_TDC_NEGATIVE_INFINITY ) | |
4673c1a0 | 266 | |
267 | /* Target machine storage layout. */ | |
268 | ||
7718b866 | 269 | /* Everything is big-endian. */ |
4673c1a0 | 270 | #define BITS_BIG_ENDIAN 1 |
4673c1a0 | 271 | #define BYTES_BIG_ENDIAN 1 |
4673c1a0 | 272 | #define WORDS_BIG_ENDIAN 1 |
273 | ||
b5fdc416 | 274 | #define STACK_SIZE_MODE (Pmode) |
275 | ||
76a4c804 | 276 | /* Vector arguments are left-justified when placed on the stack during |
277 | parameter passing. */ | |
278 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
279 | (s390_function_arg_vector ((MODE), (TYPE)) \ | |
280 | ? upward \ | |
281 | : DEFAULT_FUNCTION_ARG_PADDING ((MODE), (TYPE))) | |
282 | ||
f553e2d1 | 283 | #ifndef IN_LIBGCC2 |
b5fdc416 | 284 | |
285 | /* Width of a word, in units (bytes). */ | |
286 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
287 | ||
288 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
289 | ABI-relevant contexts. This always matches | |
290 | GET_MODE_SIZE (Pmode). */ | |
291 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
292 | #define MIN_UNITS_PER_WORD 4 | |
293 | #define MAX_BITS_PER_WORD 64 | |
294 | #else | |
295 | ||
296 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
297 | the library should export TImode functions or not. Thus, we have | |
298 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
299 | #ifdef __s390x__ | |
300 | #define UNITS_PER_WORD 8 | |
301 | #else | |
302 | #define UNITS_PER_WORD 4 | |
303 | #endif | |
f553e2d1 | 304 | #endif |
b5fdc416 | 305 | |
306 | /* Width of a pointer, in bits. */ | |
307 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
4673c1a0 | 308 | |
4673c1a0 | 309 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
4673c1a0 | 310 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
311 | ||
312 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
4673c1a0 | 313 | #define STACK_BOUNDARY 64 |
314 | ||
315 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
77bc9912 | 316 | #define FUNCTION_BOUNDARY 64 |
4673c1a0 | 317 | |
318 | /* There is no point aligning anything to a rounder boundary than this. */ | |
4673c1a0 | 319 | #define BIGGEST_ALIGNMENT 64 |
320 | ||
321 | /* Alignment of field after `int : 0' in a structure. */ | |
4673c1a0 | 322 | #define EMPTY_FIELD_BOUNDARY 32 |
323 | ||
8ef587dc | 324 | /* Alignment on even addresses for LARL instruction. */ |
4673c1a0 | 325 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
a16734cd | 326 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
4673c1a0 | 327 | |
7718b866 | 328 | /* Alignment is not required by the hardware. */ |
4673c1a0 | 329 | #define STRICT_ALIGNMENT 0 |
330 | ||
7718b866 | 331 | /* Mode of stack savearea. |
332 | FUNCTION is VOIDmode because calling convention maintains SP. | |
333 | BLOCK needs Pmode for SP. | |
334 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
55673549 | 335 | #define STACK_SAVEAREA_MODE(LEVEL) \ |
336 | ((LEVEL) == SAVE_FUNCTION ? VOIDmode \ | |
337 | : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) | |
7718b866 | 338 | |
4673c1a0 | 339 | |
7718b866 | 340 | /* Type layout. */ |
4673c1a0 | 341 | |
7718b866 | 342 | /* Sizes in bits of the source language data types. */ |
343 | #define SHORT_TYPE_SIZE 16 | |
344 | #define INT_TYPE_SIZE 32 | |
345 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
7718b866 | 346 | #define LONG_LONG_TYPE_SIZE 64 |
347 | #define FLOAT_TYPE_SIZE 32 | |
348 | #define DOUBLE_TYPE_SIZE 64 | |
429f9fdb | 349 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
350 | ||
429f9fdb | 351 | /* Work around target_flags dependency in ada/targtyps.c. */ |
352 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
7718b866 | 353 | |
354 | /* We use "unsigned char" as default. */ | |
355 | #define DEFAULT_SIGNED_CHAR 0 | |
356 | ||
357 | ||
358 | /* Register usage. */ | |
359 | ||
360 | /* We have 16 general purpose registers (registers 0-15), | |
361 | and 16 floating point registers (registers 16-31). | |
362 | (On non-IEEE machines, we have only 4 fp registers.) | |
f81e845f | 363 | |
7718b866 | 364 | Amongst the general purpose registers, some are used |
365 | for specific purposes: | |
366 | GPR 11: Hard frame pointer (if needed) | |
367 | GPR 12: Global offset table pointer (if needed) | |
368 | GPR 13: Literal pool base register | |
369 | GPR 14: Return address register | |
370 | GPR 15: Stack pointer | |
f81e845f | 371 | |
923cf36d | 372 | Registers 32-35 are 'fake' hard registers that do not |
7718b866 | 373 | correspond to actual hardware: |
374 | Reg 32: Argument pointer | |
375 | Reg 33: Condition code | |
ffead1ca | 376 | Reg 34: Frame pointer |
923cf36d | 377 | Reg 35: Return address pointer |
7718b866 | 378 | |
ffead1ca | 379 | Registers 36 and 37 are mapped to access registers |
76a4c804 | 380 | 0 and 1, used to implement thread-local storage. |
381 | ||
382 | Reg 38-53: Vector registers v16-v31 */ | |
923cf36d | 383 | |
76a4c804 | 384 | #define FIRST_PSEUDO_REGISTER 54 |
7718b866 | 385 | |
386 | /* Standard register usage. */ | |
25da9e9f | 387 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
388 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
095798e3 | 389 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
25da9e9f | 390 | #define CC_REGNO_P(N) ((N) == 33) |
7cbfc974 | 391 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
923cf36d | 392 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
76a4c804 | 393 | #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53) |
394 | #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N)) | |
25da9e9f | 395 | |
396 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
397 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
398 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
399 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
ec3b9583 | 400 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
923cf36d | 401 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
76a4c804 | 402 | #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X))) |
403 | #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X))) | |
4673c1a0 | 404 | |
7718b866 | 405 | /* Set up fixed registers and calling convention: |
4673c1a0 | 406 | |
7718b866 | 407 | GPRs 0-5 are always call-clobbered, |
408 | GPRs 6-15 are always call-saved. | |
409 | GPR 12 is fixed if used as GOT pointer. | |
410 | GPR 13 is always fixed (as literal pool pointer). | |
5fe74ca1 | 411 | GPR 14 is always fixed on S/390 machines (as return address). |
7718b866 | 412 | GPR 15 is always fixed (as stack pointer). |
413 | The 'fake' hard registers are call-clobbered and fixed. | |
923cf36d | 414 | The access registers are call-saved and fixed. |
4673c1a0 | 415 | |
7718b866 | 416 | On 31-bit, FPRs 18-19 are call-clobbered; |
417 | on 64-bit, FPRs 24-31 are call-clobbered. | |
76a4c804 | 418 | The remaining FPRs are call-saved. |
419 | ||
420 | All non-FP vector registers are call-clobbered v16-v31. */ | |
4673c1a0 | 421 | |
422 | #define FIXED_REGISTERS \ | |
423 | { 0, 0, 0, 0, \ | |
424 | 0, 0, 0, 0, \ | |
425 | 0, 0, 0, 0, \ | |
426 | 0, 1, 1, 1, \ | |
427 | 0, 0, 0, 0, \ | |
428 | 0, 0, 0, 0, \ | |
429 | 0, 0, 0, 0, \ | |
430 | 0, 0, 0, 0, \ | |
923cf36d | 431 | 1, 1, 1, 1, \ |
76a4c804 | 432 | 1, 1, \ |
433 | 0, 0, 0, 0, \ | |
434 | 0, 0, 0, 0, \ | |
435 | 0, 0, 0, 0, \ | |
436 | 0, 0, 0, 0 } | |
4673c1a0 | 437 | |
4673c1a0 | 438 | #define CALL_USED_REGISTERS \ |
439 | { 1, 1, 1, 1, \ | |
440 | 1, 1, 0, 0, \ | |
441 | 0, 0, 0, 0, \ | |
442 | 0, 1, 1, 1, \ | |
8b4a4127 | 443 | 1, 1, 1, 1, \ |
444 | 1, 1, 1, 1, \ | |
445 | 1, 1, 1, 1, \ | |
446 | 1, 1, 1, 1, \ | |
923cf36d | 447 | 1, 1, 1, 1, \ |
76a4c804 | 448 | 1, 1, \ |
449 | 1, 1, 1, 1, \ | |
450 | 1, 1, 1, 1, \ | |
451 | 1, 1, 1, 1, \ | |
452 | 1, 1, 1, 1 } | |
8b4a4127 | 453 | |
8b4a4127 | 454 | #define CALL_REALLY_USED_REGISTERS \ |
76a4c804 | 455 | { 1, 1, 1, 1, /* r0 - r15 */ \ |
4673c1a0 | 456 | 1, 1, 0, 0, \ |
8b4a4127 | 457 | 0, 0, 0, 0, \ |
458 | 0, 0, 0, 0, \ | |
76a4c804 | 459 | 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \ |
4673c1a0 | 460 | 1, 1, 1, 1, \ |
461 | 1, 1, 1, 1, \ | |
462 | 1, 1, 1, 1, \ | |
76a4c804 | 463 | 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \ |
464 | 0, 0, /* a0 (36), a1 (37) */ \ | |
465 | 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \ | |
923cf36d | 466 | 1, 1, 1, 1, \ |
76a4c804 | 467 | 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \ |
468 | 1, 1, 1, 1 } | |
4673c1a0 | 469 | |
7718b866 | 470 | /* Preferred register allocation order. */ |
76a4c804 | 471 | #define REG_ALLOC_ORDER \ |
472 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ | |
473 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
474 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
475 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ | |
476 | 15, 32, 33, 34, 35, 36, 37 } | |
4673c1a0 | 477 | |
4673c1a0 | 478 | |
7718b866 | 479 | /* Fitting values into registers. */ |
f81e845f | 480 | |
7718b866 | 481 | /* Integer modes <= word size fit into any GPR. |
482 | Integer modes > word size fit into successive GPRs, starting with | |
483 | an even-numbered register. | |
484 | SImode and DImode fit into FPRs as well. | |
f81e845f | 485 | |
7718b866 | 486 | Floating point modes <= word size fit into any FPR or GPR. |
487 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
488 | into any FPR, or an even-odd GPR pair. | |
429f9fdb | 489 | TFmode fits only into an even-odd FPR pair. |
f81e845f | 490 | |
7718b866 | 491 | Complex floating point modes fit either into two FPRs, or into |
492 | successive GPRs (again starting with an even number). | |
429f9fdb | 493 | TCmode fits only into two successive even-odd FPR pairs. |
f81e845f | 494 | |
7718b866 | 495 | Condition code modes fit only into the CC register. */ |
4673c1a0 | 496 | |
8f1128bb | 497 | /* Because all registers in a class have the same size HARD_REGNO_NREGS |
498 | is equivalent to CLASS_MAX_NREGS. */ | |
4673c1a0 | 499 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
8f1128bb | 500 | s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) |
501 | ||
502 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
503 | s390_hard_regno_mode_ok ((REGNO), (MODE)) | |
504 | ||
505 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ | |
55673549 | 506 | s390_hard_regno_rename_ok ((FROM), (TO)) |
d1a5573e | 507 | |
4673c1a0 | 508 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
509 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
510 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
511 | ||
7718b866 | 512 | /* Maximum number of registers to represent a value of mode MODE |
513 | in a register of class CLASS. */ | |
514 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
8f1128bb | 515 | s390_class_max_nregs ((CLASS), (MODE)) |
8b4a4127 | 516 | |
429f9fdb | 517 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
76a4c804 | 518 | s390_cannot_change_mode_class ((FROM), (TO), (CLASS)) |
4673c1a0 | 519 | |
e17ed6ec | 520 | /* We can reverse a CC mode safely if we know whether it comes from a |
521 | floating point compare or not. With the vector modes it is encoded | |
522 | as part of the mode. | |
523 | FIXME: It might make sense to do this for other cc modes as well. */ | |
524 | #define REVERSIBLE_CC_MODE(MODE) \ | |
525 | ((MODE) == CCVIALLmode || (MODE) == CCVIANYmode \ | |
526 | || (MODE) == CCVFALLmode || (MODE) == CCVFANYmode) | |
527 | ||
528 | /* Given a condition code and a mode, return the inverse condition. */ | |
529 | #define REVERSE_CONDITION(CODE, MODE) s390_reverse_condition (MODE, CODE) | |
530 | ||
531 | ||
7718b866 | 532 | /* Register classes. */ |
f81e845f | 533 | |
7718b866 | 534 | /* We use the following register classes: |
535 | GENERAL_REGS All general purpose registers | |
536 | ADDR_REGS All general purpose registers except %r0 | |
537 | (These registers can be used in address generation) | |
538 | FP_REGS All floating point registers | |
923cf36d | 539 | CC_REGS The condition code register |
540 | ACCESS_REGS The access registers | |
f81e845f | 541 | |
7718b866 | 542 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
543 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
923cf36d | 544 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
545 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
f81e845f | 546 | |
7718b866 | 547 | NO_REGS No registers |
548 | ALL_REGS All registers | |
f81e845f | 549 | |
7718b866 | 550 | Note that the 'fake' frame pointer and argument pointer registers |
923cf36d | 551 | are included amongst the address registers here. */ |
4673c1a0 | 552 | |
553 | enum reg_class | |
554 | { | |
923cf36d | 555 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
ffead1ca | 556 | ADDR_CC_REGS, GENERAL_CC_REGS, |
8b4a4127 | 557 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
76a4c804 | 558 | VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS, |
8b4a4127 | 559 | ALL_REGS, LIM_REG_CLASSES |
4673c1a0 | 560 | }; |
4673c1a0 | 561 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
562 | ||
923cf36d | 563 | #define REG_CLASS_NAMES \ |
564 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
565 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
76a4c804 | 566 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \ |
567 | "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \ | |
568 | "ALL_REGS" } | |
4673c1a0 | 569 | |
7718b866 | 570 | /* Class -> register mapping. */ |
76a4c804 | 571 | #define REG_CLASS_CONTENTS \ |
572 | { \ | |
4673c1a0 | 573 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
bcbf02a5 | 574 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
7cbfc974 | 575 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
576 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
923cf36d | 577 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
bcbf02a5 | 578 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
579 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
4673c1a0 | 580 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
7cbfc974 | 581 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
582 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
76a4c804 | 583 | { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \ |
584 | { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \ | |
585 | { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \ | |
586 | { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \ | |
4673c1a0 | 587 | } |
588 | ||
47dd2e78 | 589 | /* In some case register allocation order is not enough for IRA to |
590 | generate a good code. The following macro (if defined) increases | |
591 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
592 | multiplied by the macro value. | |
593 | ||
594 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
595 | reload can decide not to use the hard register because some | |
596 | constant was forced to be in memory. */ | |
597 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
55673549 | 598 | ((regno) != BASE_REGNUM ? 0.0 : 0.5) |
47dd2e78 | 599 | |
7718b866 | 600 | /* Register -> class mapping. */ |
601 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
602 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
4673c1a0 | 603 | |
7718b866 | 604 | /* ADDR_REGS can be used as base or index register. */ |
605 | #define INDEX_REG_CLASS ADDR_REGS | |
606 | #define BASE_REG_CLASS ADDR_REGS | |
4673c1a0 | 607 | |
7718b866 | 608 | /* Check whether REGNO is a hard register of the suitable class |
609 | or a pseudo register currently allocated to one such. */ | |
610 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
611 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1e280623 | 612 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ |
613 | || ADDR_REGNO_P (reg_renumber[REGNO])) | |
7718b866 | 614 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
4673c1a0 | 615 | |
4673c1a0 | 616 | |
76a4c804 | 617 | /* We need secondary memory to move data between GPRs and FPRs. |
618 | ||
619 | - With DFP the ldgr lgdr instructions are available. Due to the | |
620 | different alignment we cannot use them for SFmode. For 31 bit a | |
621 | 64 bit value in GPR would be a register pair so here we still | |
622 | need to go via memory. | |
623 | ||
624 | - With z13 we can do the SF/SImode moves with vlgvf. Due to the | |
625 | overlapping of FPRs and VRs we still disallow TF/TD modes to be | |
626 | in full VRs so as before also on z13 we do these moves via | |
627 | memory. | |
628 | ||
629 | FIXME: Should we try splitting it into two vlgvg's/vlvg's instead? */ | |
630 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
55673549 | 631 | (((reg_classes_intersect_p ((CLASS1), VEC_REGS) \ |
632 | && reg_classes_intersect_p ((CLASS2), GENERAL_REGS)) \ | |
633 | || (reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ | |
634 | && reg_classes_intersect_p ((CLASS2), VEC_REGS))) \ | |
76a4c804 | 635 | && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8) \ |
636 | && (!TARGET_VX || (SCALAR_FLOAT_MODE_P (MODE) \ | |
637 | && GET_MODE_SIZE (MODE) > 8))) | |
7718b866 | 638 | |
639 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
640 | because the movsi and movsf patterns don't handle r/f moves. */ | |
641 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
642 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
643 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
55673549 | 644 | : (MODE)) |
7718b866 | 645 | |
646 | ||
7718b866 | 647 | /* Stack layout and calling conventions. */ |
f81e845f | 648 | |
7718b866 | 649 | /* Our stack grows from higher to lower addresses. However, local variables |
650 | are accessed by positive offsets, and function arguments are stored at | |
651 | increasing addresses. */ | |
2b785411 | 652 | #define STACK_GROWS_DOWNWARD 1 |
119114cb | 653 | #define FRAME_GROWS_DOWNWARD 1 |
7718b866 | 654 | /* #undef ARGS_GROW_DOWNWARD */ |
4673c1a0 | 655 | |
7718b866 | 656 | /* The basic stack layout looks like this: the stack pointer points |
657 | to the register save area for called functions. Above that area | |
658 | is the location to place outgoing arguments. Above those follow | |
659 | dynamic allocations (alloca), and finally the local variables. */ | |
4673c1a0 | 660 | |
7718b866 | 661 | /* Offset from stack-pointer to first location of outgoing args. */ |
662 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
4673c1a0 | 663 | |
7718b866 | 664 | /* Offset within stack frame to start allocating local variables at. */ |
119114cb | 665 | #define STARTING_FRAME_OFFSET 0 |
4673c1a0 | 666 | |
7718b866 | 667 | /* Offset from the stack pointer register to an item dynamically |
668 | allocated on the stack, e.g., by `alloca'. */ | |
119114cb | 669 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
abe32cce | 670 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
4673c1a0 | 671 | |
7718b866 | 672 | /* Offset of first parameter from the argument pointer register value. |
673 | We have a fake argument pointer register that points directly to | |
674 | the argument area. */ | |
675 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
4673c1a0 | 676 | |
ffead1ca | 677 | /* Defining this macro makes __builtin_frame_address(0) and |
869d0ef0 | 678 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
679 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
29c05e22 | 680 | (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
869d0ef0 | 681 | |
f81e845f | 682 | /* The return address of the current frame is retrieved |
8b4a4127 | 683 | from the initial value of register RETURN_REGNUM. |
684 | For frames farther back, we use the stack slot where | |
685 | the corresponding RETURN_REGNUM register was saved. */ | |
869d0ef0 | 686 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
687 | (TARGET_PACKED_STACK ? \ | |
29c05e22 | 688 | plus_constant (Pmode, (FRAME), \ |
689 | STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) | |
8b4a4127 | 690 | |
4f091f59 | 691 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
692 | builtin_frame_address. Otherwise arg pointer - | |
693 | STACK_POINTER_OFFSET would be returned for | |
694 | __builtin_frame_address(0) what might result in an address pointing | |
695 | somewhere into the middle of the local variables since the packed | |
696 | stack layout generally does not need all the bytes in the register | |
697 | save area. */ | |
698 | #define FRAME_ADDR_RTX(FRAME) \ | |
699 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
700 | ||
869d0ef0 | 701 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
abd8f04d | 702 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
4673c1a0 | 703 | |
7718b866 | 704 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
bcd9bd66 | 705 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
4673c1a0 | 706 | |
8b4a4127 | 707 | |
7718b866 | 708 | /* Exception handling. */ |
f81e845f | 709 | |
7718b866 | 710 | /* Describe calling conventions for DWARF-2 exception handling. */ |
711 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
8b4a4127 | 712 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
4673c1a0 | 713 | #define DWARF_FRAME_RETURN_COLUMN 14 |
714 | ||
715 | /* Describe how we implement __builtin_eh_return. */ | |
716 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
7cbfc974 | 717 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
ffead1ca | 718 | |
e3a04290 | 719 | /* Select a format to encode pointers in exception handling data. */ |
720 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
721 | (flag_pic \ | |
722 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
723 | : DW_EH_PE_absptr) | |
724 | ||
b5fdc416 | 725 | /* Register save slot alignment. */ |
726 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
727 | ||
a22cd2a7 | 728 | /* Let the assembler generate debug line info. */ |
729 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
730 | ||
76a4c804 | 731 | /* Define the dwarf register mapping. |
732 | v16-v31 -> 68-83 | |
733 | rX -> X otherwise */ | |
55673549 | 734 | #define DBX_REGISTER_NUMBER(regno) \ |
735 | (((regno) >= 38 && (regno) <= 53) ? (regno) + 30 : (regno)) | |
4673c1a0 | 736 | |
7718b866 | 737 | /* Frame registers. */ |
4673c1a0 | 738 | |
7718b866 | 739 | #define STACK_POINTER_REGNUM 15 |
740 | #define FRAME_POINTER_REGNUM 34 | |
741 | #define HARD_FRAME_POINTER_REGNUM 11 | |
742 | #define ARG_POINTER_REGNUM 32 | |
7cbfc974 | 743 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
4673c1a0 | 744 | |
f81e845f | 745 | /* The static chain must be call-clobbered, but not used for |
746 | function argument passing. As register 1 is clobbered by | |
7718b866 | 747 | the trampoline code, we only have one option. */ |
748 | #define STATIC_CHAIN_REGNUM 0 | |
4673c1a0 | 749 | |
7718b866 | 750 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
751 | To avoid ABI incompatibility, this number must not change even as | |
752 | 'fake' hard registers are added or removed. */ | |
753 | #define DWARF_FRAME_REGISTERS 34 | |
4673c1a0 | 754 | |
4673c1a0 | 755 | |
7718b866 | 756 | /* Frame pointer and argument pointer elimination. */ |
4673c1a0 | 757 | |
d1a5573e | 758 | #define ELIMINABLE_REGS \ |
759 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
760 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
761 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
762 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
763 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
764 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
765 | { BASE_REGNUM, BASE_REGNUM }} | |
4673c1a0 | 766 | |
4fed3f99 | 767 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
768 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
4673c1a0 | 769 | |
4673c1a0 | 770 | |
7718b866 | 771 | /* Stack arguments. */ |
f81e845f | 772 | |
7718b866 | 773 | /* We need current_function_outgoing_args to be valid. */ |
774 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
4673c1a0 | 775 | |
4673c1a0 | 776 | |
7718b866 | 777 | /* Register arguments. */ |
f81e845f | 778 | |
4673c1a0 | 779 | typedef struct s390_arg_structure |
780 | { | |
781 | int gprs; /* gpr so far */ | |
782 | int fprs; /* fpr so far */ | |
76a4c804 | 783 | int vrs; /* vr so far */ |
4673c1a0 | 784 | } |
785 | CUMULATIVE_ARGS; | |
786 | ||
34f27375 | 787 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
76a4c804 | 788 | ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0) |
789 | ||
790 | #define FIRST_VEC_ARG_REGNO 46 | |
791 | #define LAST_VEC_ARG_REGNO 53 | |
4673c1a0 | 792 | |
8364148d | 793 | /* Arguments can be placed in general registers 2 to 6, or in floating |
794 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
795 | bit. */ | |
76a4c804 | 796 | #define FUNCTION_ARG_REGNO_P(N) \ |
797 | (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ | |
798 | || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ | |
799 | || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) | |
4673c1a0 | 800 | |
4673c1a0 | 801 | |
76a4c804 | 802 | /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */ |
803 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
804 | ((N) == 2 || (N) == 16 \ | |
805 | || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO)) | |
4673c1a0 | 806 | |
4673c1a0 | 807 | |
7718b866 | 808 | /* Function entry and exit. */ |
f81e845f | 809 | |
7718b866 | 810 | /* When returning from a function, the stack pointer does not matter. */ |
811 | #define EXIT_IGNORE_STACK 1 | |
4673c1a0 | 812 | |
4673c1a0 | 813 | |
7718b866 | 814 | /* Profiling. */ |
4673c1a0 | 815 | |
816 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
7718b866 | 817 | s390_function_profiler ((FILE), ((LABELNO))) |
4673c1a0 | 818 | |
ecfe03ce | 819 | #define PROFILE_BEFORE_PROLOGUE 1 |
4673c1a0 | 820 | |
4673c1a0 | 821 | |
7718b866 | 822 | /* Trampolines for nested functions. */ |
4673c1a0 | 823 | |
4d946732 | 824 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
825 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
4673c1a0 | 826 | |
7718b866 | 827 | /* Addressing modes, and classification of registers for them. */ |
4673c1a0 | 828 | |
7718b866 | 829 | /* Recognize any constant value that is a valid address. */ |
830 | #define CONSTANT_ADDRESS_P(X) 0 | |
4673c1a0 | 831 | |
7718b866 | 832 | /* Maximum number of registers that can appear in a valid memory address. */ |
833 | #define MAX_REGS_PER_ADDRESS 2 | |
4673c1a0 | 834 | |
e68d6a13 | 835 | /* This definition replaces the formerly used 'm' constraint with a |
fd50b071 | 836 | different constraint letter in order to avoid changing semantics of |
837 | the 'm' constraint when accepting new address formats in | |
838 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
839 | must not be used in insn definitions or inline assemblies. */ | |
e68d6a13 | 840 | #define TARGET_MEM_CONSTRAINT 'e' |
841 | ||
e4542435 | 842 | /* Try a machine-dependent way of reloading an illegitimate address |
843 | operand. If we find one, push the reload and jump to WIN. This | |
844 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
845 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
55673549 | 846 | do { \ |
847 | rtx new_rtx = legitimize_reload_address ((AD), (MODE), \ | |
848 | (OPNUM), (int)(TYPE)); \ | |
849 | if (new_rtx) \ | |
850 | { \ | |
851 | (AD) = new_rtx; \ | |
852 | goto WIN; \ | |
853 | } \ | |
854 | } while (0) | |
e4542435 | 855 | |
7718b866 | 856 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
55673549 | 857 | #define SYMBOLIC_CONST(X) \ |
858 | (GET_CODE (X) == SYMBOL_REF \ | |
859 | || GET_CODE (X) == LABEL_REF \ | |
860 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
4673c1a0 | 861 | |
55673549 | 862 | #define TLS_SYMBOLIC_CONST(X) \ |
863 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
864 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
be00aaa8 | 865 | |
4673c1a0 | 866 | |
7718b866 | 867 | /* Condition codes. */ |
4673c1a0 | 868 | |
7718b866 | 869 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
870 | return the mode to be used for the comparison. */ | |
871 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
f81e845f | 872 | |
7718b866 | 873 | /* Relative costs of operations. */ |
4673c1a0 | 874 | |
4673c1a0 | 875 | /* A C expression for the cost of a branch instruction. A value of 1 |
876 | is the default; other values are interpreted relative to that. */ | |
abb9bd4b | 877 | #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost |
4673c1a0 | 878 | |
7718b866 | 879 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
880 | #define SLOW_BYTE_ACCESS 1 | |
881 | ||
363f612f | 882 | /* An integer expression for the size in bits of the largest integer machine |
ffead1ca | 883 | mode that should actually be used. We allow pairs of registers. */ |
363f612f | 884 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
885 | ||
7718b866 | 886 | /* The maximum number of bytes that a single instruction can move quickly |
1d60d981 | 887 | between memory and registers or between two memory locations. */ |
b5fdc416 | 888 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
889 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
7718b866 | 890 | #define MAX_MOVE_MAX 16 |
4673c1a0 | 891 | |
7718b866 | 892 | /* Don't perform CSE on function addresses. */ |
93516111 | 893 | #define NO_FUNCTION_CSE 1 |
7718b866 | 894 | |
6cb659b1 | 895 | /* This value is used in tree-sra to decide whether it might benefical |
896 | to split a struct move into several word-size moves. For S/390 | |
897 | only small values make sense here since struct moves are relatively | |
9d75589a | 898 | cheap thanks to mvc so the small default value chosen for archs |
6cb659b1 | 899 | with memmove patterns should be ok. But this value is multiplied |
900 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
901 | here to compensate for that factor since mvc costs exactly the same | |
902 | on 31 and 64 bit. */ | |
f5733e7c | 903 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
6cb659b1 | 904 | |
7718b866 | 905 | |
906 | /* Sections. */ | |
907 | ||
908 | /* Output before read-only data. */ | |
909 | #define TEXT_SECTION_ASM_OP ".text" | |
910 | ||
911 | /* Output before writable (initialized) data. */ | |
912 | #define DATA_SECTION_ASM_OP ".data" | |
913 | ||
914 | /* Output before writable (uninitialized) data. */ | |
915 | #define BSS_SECTION_ASM_OP ".bss" | |
916 | ||
917 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
918 | in where code resides. We have to write it as asm code. */ | |
919 | #ifndef __s390x__ | |
920 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
921 | asm (SECTION_OP "\n\ | |
922 | bras\t%r2,1f\n\ | |
923 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
924 | 1: l\t%r3,0(%r2)\n\ | |
925 | bas\t%r14,0(%r3,%r2)\n\ | |
926 | .previous"); | |
927 | #endif | |
a983c6d2 | 928 | |
7718b866 | 929 | |
930 | /* Position independent code. */ | |
931 | ||
7718b866 | 932 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
933 | ||
934 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
a983c6d2 | 935 | |
9852c8ae | 936 | #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE |
937 | #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 | |
938 | #endif | |
939 | ||
a983c6d2 | 940 | |
941 | /* Assembler file format. */ | |
942 | ||
943 | /* Character to start a comment. */ | |
944 | #define ASM_COMMENT_START "#" | |
945 | ||
946 | /* Declare an uninitialized external linkage data object. */ | |
55673549 | 947 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
948 | asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) | |
a983c6d2 | 949 | |
950 | /* Globalizing directive for a label. */ | |
951 | #define GLOBAL_ASM_OP ".globl " | |
952 | ||
953 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
954 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
955 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
956 | ||
957 | /* Advance the location counter by SIZE bytes. */ | |
958 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
f03df321 | 959 | fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
a983c6d2 | 960 | |
a983c6d2 | 961 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
962 | #define LOCAL_LABEL_PREFIX "." | |
4673c1a0 | 963 | |
6d0afa28 | 964 | #define LABEL_ALIGN(LABEL) \ |
55673549 | 965 | s390_label_align ((LABEL)) |
6d0afa28 | 966 | |
4673c1a0 | 967 | /* How to refer to registers in assembler output. This sequence is |
968 | indexed by compiler's hard-register-number (see above). */ | |
4673c1a0 | 969 | #define REGISTER_NAMES \ |
76a4c804 | 970 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ |
971 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
972 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ | |
973 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ | |
974 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \ | |
975 | "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \ | |
976 | "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \ | |
977 | } | |
978 | ||
979 | #define ADDITIONAL_REGISTER_NAMES \ | |
980 | { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \ | |
981 | { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \ | |
982 | { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \ | |
983 | { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } }; | |
4673c1a0 | 984 | |
a983c6d2 | 985 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
55673549 | 986 | #define PRINT_OPERAND(FILE, X, CODE) print_operand ((FILE), (X), (CODE)) |
987 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address ((FILE), (ADDR)) | |
4673c1a0 | 988 | |
a983c6d2 | 989 | /* Output an element of a case-vector that is absolute. */ |
990 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
991 | do { \ | |
992 | char buf[32]; \ | |
b5fdc416 | 993 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
a983c6d2 | 994 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
995 | assemble_name ((FILE), buf); \ | |
996 | fputc ('\n', (FILE)); \ | |
997 | } while (0) | |
998 | ||
999 | /* Output an element of a case-vector that is relative. */ | |
1000 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1001 | do { \ | |
1002 | char buf[32]; \ | |
b5fdc416 | 1003 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
a983c6d2 | 1004 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
1005 | assemble_name ((FILE), buf); \ | |
1006 | fputc ('-', (FILE)); \ | |
1007 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
1008 | assemble_name ((FILE), buf); \ | |
1009 | fputc ('\n', (FILE)); \ | |
1010 | } while (0) | |
1011 | ||
7a64c761 | 1012 | /* Mark the return register as used by the epilogue so that we can |
1013 | use it in unadorned (return) and (simple_return) instructions. */ | |
1014 | #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) | |
1015 | ||
77bc9912 | 1016 | #undef ASM_OUTPUT_FUNCTION_LABEL |
55673549 | 1017 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ |
1018 | s390_asm_output_function_label ((FILE), (NAME), (DECL)) | |
4673c1a0 | 1019 | |
7a0cee35 | 1020 | #if S390_USE_TARGET_ATTRIBUTE |
1021 | /* Hook to output .machine and .machinemode at start of function. */ | |
1022 | #undef ASM_OUTPUT_FUNCTION_PREFIX | |
1023 | #define ASM_OUTPUT_FUNCTION_PREFIX s390_asm_output_function_prefix | |
1024 | ||
1025 | /* Hook to output .machine and .machinemode at end of function. */ | |
1026 | #undef ASM_DECLARE_FUNCTION_SIZE | |
1027 | #define ASM_DECLARE_FUNCTION_SIZE s390_asm_declare_function_size | |
1028 | #endif | |
1029 | ||
7718b866 | 1030 | /* Miscellaneous parameters. */ |
1031 | ||
7718b866 | 1032 | /* Specify the machine mode that this machine uses for the index in the |
1033 | tablejump instruction. */ | |
1034 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
1035 | ||
7718b866 | 1036 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1037 | is done just by pretending it is already truncated. */ | |
1038 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1039 | ||
1040 | /* Specify the machine mode that pointers have. | |
1041 | After generation of rtl, the compiler makes no further distinction | |
1042 | between pointers and any other objects of this machine mode. */ | |
af8303fa | 1043 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
7718b866 | 1044 | |
f81e845f | 1045 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
1046 | #define POINTERS_EXTEND_UNSIGNED -1 | |
1047 | ||
7718b866 | 1048 | /* A function address in a call instruction is a byte address (for |
1049 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
1050 | #define FUNCTION_MODE QImode | |
1051 | ||
163277cf | 1052 | /* Specify the value which is used when clz operand is zero. */ |
1053 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
1054 | ||
8cc5de33 | 1055 | /* Machine-specific symbol_ref flags. */ |
78affa36 | 1056 | #define SYMBOL_FLAG_ALIGN_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT |
1057 | #define SYMBOL_FLAG_ALIGN_MASK \ | |
1058 | ((SYMBOL_FLAG_MACH_DEP << 0) | (SYMBOL_FLAG_MACH_DEP << 1)) | |
1059 | ||
1060 | #define SYMBOL_FLAG_SET_ALIGN(X, A) \ | |
1061 | (SYMBOL_REF_FLAGS (X) = (SYMBOL_REF_FLAGS (X) & ~SYMBOL_FLAG_ALIGN_MASK) \ | |
1062 | | (A << SYMBOL_FLAG_ALIGN_SHIFT)) | |
1063 | ||
1064 | #define SYMBOL_FLAG_GET_ALIGN(X) \ | |
1065 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN_MASK) >> SYMBOL_FLAG_ALIGN_SHIFT) | |
1066 | ||
1067 | /* Helpers to access symbol_ref flags. They are used in | |
1068 | check_symref_alignment() and larl_operand to detect if the | |
1069 | available alignment matches the required one. We do not use | |
1070 | a positive check like _ALIGN2 because in that case we would have | |
1071 | to annotate every symbol_ref. However, we only want to touch | |
1072 | the symbol_refs that can be misaligned and assume that the others | |
1073 | are correctly aligned. Hence, if a symbol_ref does not have | |
1074 | a _NOTALIGN flag it is supposed to be correctly aligned. */ | |
55673549 | 1075 | #define SYMBOL_FLAG_SET_NOTALIGN2(X) SYMBOL_FLAG_SET_ALIGN((X), 1) |
1076 | #define SYMBOL_FLAG_SET_NOTALIGN4(X) SYMBOL_FLAG_SET_ALIGN((X), 2) | |
1077 | #define SYMBOL_FLAG_SET_NOTALIGN8(X) SYMBOL_FLAG_SET_ALIGN((X), 3) | |
78affa36 | 1078 | |
1079 | #define SYMBOL_FLAG_NOTALIGN2_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 1) | |
55673549 | 1080 | #define SYMBOL_FLAG_NOTALIGN4_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 2 \ |
78affa36 | 1081 | || SYMBOL_FLAG_GET_ALIGN(X) == 1) |
55673549 | 1082 | #define SYMBOL_FLAG_NOTALIGN8_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 3 \ |
1083 | || SYMBOL_FLAG_GET_ALIGN(X) == 2 \ | |
78affa36 | 1084 | || SYMBOL_FLAG_GET_ALIGN(X) == 1) |
8cc5de33 | 1085 | |
76a4c804 | 1086 | /* Check whether integer displacement is in range for a short displacement. */ |
1087 | #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095) | |
1088 | ||
8cc5de33 | 1089 | /* Check whether integer displacement is in range. */ |
55673549 | 1090 | #define DISP_IN_RANGE(d) \ |
1091 | (TARGET_LONG_DISPLACEMENT \ | |
1092 | ? ((d) >= -524288 && (d) <= 524287) \ | |
1093 | : SHORT_DISP_IN_RANGE(d)) | |
8cc5de33 | 1094 | |
d80deb0a | 1095 | /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ |
1096 | #define READ_CAN_USE_WRITE_PREFETCH 1 | |
218e3e4e | 1097 | |
1098 | extern const int processor_flags_table[]; | |
76a4c804 | 1099 | |
1100 | /* The truth element value for vector comparisons. Our instructions | |
1101 | always generate -1 in that case. */ | |
1102 | #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) | |
1103 | ||
07f32359 | 1104 | /* Target pragma. */ |
1105 | ||
1106 | /* resolve_overloaded_builtin can not be defined the normal way since | |
1107 | it is defined in code which technically belongs to the | |
1108 | front-end. */ | |
1109 | #define REGISTER_TARGET_PRAGMAS() \ | |
1110 | do { \ | |
1111 | s390_register_target_pragmas (); \ | |
1112 | } while (0) | |
1113 | ||
76a4c804 | 1114 | #endif /* S390_H */ |