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[thirdparty/gcc.git] / gcc / config / sparc / sparc.c
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c3427c7d 1/* Subroutines for insn-output.c for SPARC.
4592bdcb 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4900aa61 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
62de55f7 4 Free Software Foundation, Inc.
ab835497 5 Contributed by Michael Tiemann (tiemann@cygnus.com)
c3427c7d 6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
61a55e8b 7 at Cygnus Support.
ab835497 8
4d8af13f 9This file is part of GCC.
ab835497 10
4d8af13f 11GCC is free software; you can redistribute it and/or modify
ab835497 12it under the terms of the GNU General Public License as published by
2f83c7d6 13the Free Software Foundation; either version 3, or (at your option)
ab835497
RK		 14any later version.
15
4d8af13f 16GCC is distributed in the hope that it will be useful,
ab835497
RK		 17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
2f83c7d6
NC		 22along with GCC; see the file COPYING3. If not see
23<http://www.gnu.org/licenses/>. */
ab835497 24
ab835497 25#include "config.h"
284d86e9 26#include "system.h"
4977bab6
ZW		 27#include "coretypes.h"
28#include "tm.h"
210aa14a 29#include "tree.h"
ab835497
RK		 30#include "rtl.h"
31#include "regs.h"
32#include "hard-reg-set.h"
33#include "real.h"
34#include "insn-config.h"
16f59241 35#include "insn-codes.h"
ab835497 36#include "conditions.h"
ab835497
RK		 37#include "output.h"
38#include "insn-attr.h"
39#include "flags.h"
49ad7cfa 40#include "function.h"
ab835497 41#include "expr.h"
e78d8e51 42#include "optabs.h"
ab835497 43#include "recog.h"
487a6e06 44#include "toplev.h"
d07d525a 45#include "ggc.h"
b1474bb7 46#include "tm_p.h"
e78d8e51 47#include "debug.h"
672a6f42
NB		 48#include "target.h"
49#include "target-def.h"
117dca74 50#include "cfglayout.h"
726a989a 51#include "gimple.h"
16f59241 52#include "langhooks.h"
47eb5b32 53#include "params.h"
6fb5fa3c 54#include "df.h"
9fd52c6c 55#include "dwarf2out.h"
ab835497 56
18df6de9
DM		 57/* Processor costs */
58static const
59struct processor_costs cypress_costs = {
ffe384ff
DM		 60 COSTS_N_INSNS (2), /* int load */
61 COSTS_N_INSNS (2), /* int signed load */
62 COSTS_N_INSNS (2), /* int zeroed load */
63 COSTS_N_INSNS (2), /* float load */
64 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
65 COSTS_N_INSNS (5), /* fadd, fsub */
66 COSTS_N_INSNS (1), /* fcmp */
67 COSTS_N_INSNS (1), /* fmov, fmovr */
68 COSTS_N_INSNS (7), /* fmul */
69 COSTS_N_INSNS (37), /* fdivs */
70 COSTS_N_INSNS (37), /* fdivd */
71 COSTS_N_INSNS (63), /* fsqrts */
72 COSTS_N_INSNS (63), /* fsqrtd */
73 COSTS_N_INSNS (1), /* imul */
74 COSTS_N_INSNS (1), /* imulX */
18df6de9 75 0, /* imul bit factor */
ffe384ff
DM		 76 COSTS_N_INSNS (1), /* idiv */
77 COSTS_N_INSNS (1), /* idivX */
78 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 79 0, /* shift penalty */
80};
81
82static const
83struct processor_costs supersparc_costs = {
ffe384ff
DM		 84 COSTS_N_INSNS (1), /* int load */
85 COSTS_N_INSNS (1), /* int signed load */
86 COSTS_N_INSNS (1), /* int zeroed load */
87 COSTS_N_INSNS (0), /* float load */
88 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
89 COSTS_N_INSNS (3), /* fadd, fsub */
90 COSTS_N_INSNS (3), /* fcmp */
91 COSTS_N_INSNS (1), /* fmov, fmovr */
92 COSTS_N_INSNS (3), /* fmul */
93 COSTS_N_INSNS (6), /* fdivs */
94 COSTS_N_INSNS (9), /* fdivd */
95 COSTS_N_INSNS (12), /* fsqrts */
96 COSTS_N_INSNS (12), /* fsqrtd */
97 COSTS_N_INSNS (4), /* imul */
98 COSTS_N_INSNS (4), /* imulX */
18df6de9 99 0, /* imul bit factor */
ffe384ff
DM		 100 COSTS_N_INSNS (4), /* idiv */
101 COSTS_N_INSNS (4), /* idivX */
102 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 103 1, /* shift penalty */
104};
105
106static const
107struct processor_costs hypersparc_costs = {
ffe384ff
DM		 108 COSTS_N_INSNS (1), /* int load */
109 COSTS_N_INSNS (1), /* int signed load */
110 COSTS_N_INSNS (1), /* int zeroed load */
111 COSTS_N_INSNS (1), /* float load */
112 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
113 COSTS_N_INSNS (1), /* fadd, fsub */
114 COSTS_N_INSNS (1), /* fcmp */
115 COSTS_N_INSNS (1), /* fmov, fmovr */
116 COSTS_N_INSNS (1), /* fmul */
117 COSTS_N_INSNS (8), /* fdivs */
118 COSTS_N_INSNS (12), /* fdivd */
119 COSTS_N_INSNS (17), /* fsqrts */
120 COSTS_N_INSNS (17), /* fsqrtd */
121 COSTS_N_INSNS (17), /* imul */
122 COSTS_N_INSNS (17), /* imulX */
18df6de9 123 0, /* imul bit factor */
ffe384ff
DM		 124 COSTS_N_INSNS (17), /* idiv */
125 COSTS_N_INSNS (17), /* idivX */
126 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 127 0, /* shift penalty */
128};
129
130static const
131struct processor_costs sparclet_costs = {
ffe384ff
DM		 132 COSTS_N_INSNS (3), /* int load */
133 COSTS_N_INSNS (3), /* int signed load */
134 COSTS_N_INSNS (1), /* int zeroed load */
135 COSTS_N_INSNS (1), /* float load */
136 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
137 COSTS_N_INSNS (1), /* fadd, fsub */
138 COSTS_N_INSNS (1), /* fcmp */
139 COSTS_N_INSNS (1), /* fmov, fmovr */
140 COSTS_N_INSNS (1), /* fmul */
141 COSTS_N_INSNS (1), /* fdivs */
142 COSTS_N_INSNS (1), /* fdivd */
143 COSTS_N_INSNS (1), /* fsqrts */
144 COSTS_N_INSNS (1), /* fsqrtd */
145 COSTS_N_INSNS (5), /* imul */
146 COSTS_N_INSNS (5), /* imulX */
18df6de9 147 0, /* imul bit factor */
ffe384ff
DM		 148 COSTS_N_INSNS (5), /* idiv */
149 COSTS_N_INSNS (5), /* idivX */
150 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 151 0, /* shift penalty */
152};
153
154static const
155struct processor_costs ultrasparc_costs = {
ffe384ff
DM		 156 COSTS_N_INSNS (2), /* int load */
157 COSTS_N_INSNS (3), /* int signed load */
158 COSTS_N_INSNS (2), /* int zeroed load */
159 COSTS_N_INSNS (2), /* float load */
160 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
161 COSTS_N_INSNS (4), /* fadd, fsub */
162 COSTS_N_INSNS (1), /* fcmp */
163 COSTS_N_INSNS (2), /* fmov, fmovr */
164 COSTS_N_INSNS (4), /* fmul */
165 COSTS_N_INSNS (13), /* fdivs */
166 COSTS_N_INSNS (23), /* fdivd */
167 COSTS_N_INSNS (13), /* fsqrts */
168 COSTS_N_INSNS (23), /* fsqrtd */
169 COSTS_N_INSNS (4), /* imul */
170 COSTS_N_INSNS (4), /* imulX */
18df6de9 171 2, /* imul bit factor */
ffe384ff
DM		 172 COSTS_N_INSNS (37), /* idiv */
173 COSTS_N_INSNS (68), /* idivX */
174 COSTS_N_INSNS (2), /* movcc/movr */
18df6de9
DM		 175 2, /* shift penalty */
176};
177
178static const
179struct processor_costs ultrasparc3_costs = {
ffe384ff
DM		 180 COSTS_N_INSNS (2), /* int load */
181 COSTS_N_INSNS (3), /* int signed load */
182 COSTS_N_INSNS (3), /* int zeroed load */
183 COSTS_N_INSNS (2), /* float load */
184 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
185 COSTS_N_INSNS (4), /* fadd, fsub */
186 COSTS_N_INSNS (5), /* fcmp */
187 COSTS_N_INSNS (3), /* fmov, fmovr */
188 COSTS_N_INSNS (4), /* fmul */
189 COSTS_N_INSNS (17), /* fdivs */
190 COSTS_N_INSNS (20), /* fdivd */
191 COSTS_N_INSNS (20), /* fsqrts */
192 COSTS_N_INSNS (29), /* fsqrtd */
193 COSTS_N_INSNS (6), /* imul */
194 COSTS_N_INSNS (6), /* imulX */
18df6de9 195 0, /* imul bit factor */
ffe384ff
DM		 196 COSTS_N_INSNS (40), /* idiv */
197 COSTS_N_INSNS (71), /* idivX */
198 COSTS_N_INSNS (2), /* movcc/movr */
18df6de9
DM		 199 0, /* shift penalty */
200};
201
4c837a1e
DM		 202static const
203struct processor_costs niagara_costs = {
204 COSTS_N_INSNS (3), /* int load */
205 COSTS_N_INSNS (3), /* int signed load */
206 COSTS_N_INSNS (3), /* int zeroed load */
207 COSTS_N_INSNS (9), /* float load */
208 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
209 COSTS_N_INSNS (8), /* fadd, fsub */
210 COSTS_N_INSNS (26), /* fcmp */
211 COSTS_N_INSNS (8), /* fmov, fmovr */
212 COSTS_N_INSNS (29), /* fmul */
213 COSTS_N_INSNS (54), /* fdivs */
214 COSTS_N_INSNS (83), /* fdivd */
215 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
216 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
217 COSTS_N_INSNS (11), /* imul */
218 COSTS_N_INSNS (11), /* imulX */
219 0, /* imul bit factor */
220 COSTS_N_INSNS (72), /* idiv */
221 COSTS_N_INSNS (72), /* idivX */
222 COSTS_N_INSNS (1), /* movcc/movr */
223 0, /* shift penalty */
224};
225
9eeaed6e
DM		 226static const
227struct processor_costs niagara2_costs = {
228 COSTS_N_INSNS (3), /* int load */
229 COSTS_N_INSNS (3), /* int signed load */
230 COSTS_N_INSNS (3), /* int zeroed load */
231 COSTS_N_INSNS (3), /* float load */
232 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
233 COSTS_N_INSNS (6), /* fadd, fsub */
234 COSTS_N_INSNS (6), /* fcmp */
235 COSTS_N_INSNS (6), /* fmov, fmovr */
236 COSTS_N_INSNS (6), /* fmul */
237 COSTS_N_INSNS (19), /* fdivs */
238 COSTS_N_INSNS (33), /* fdivd */
239 COSTS_N_INSNS (19), /* fsqrts */
240 COSTS_N_INSNS (33), /* fsqrtd */
241 COSTS_N_INSNS (5), /* imul */
242 COSTS_N_INSNS (5), /* imulX */
243 0, /* imul bit factor */
244 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
245 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
246 COSTS_N_INSNS (1), /* movcc/movr */
247 0, /* shift penalty */
248};
249
18df6de9
DM		 250const struct processor_costs *sparc_costs = &cypress_costs;
251
9ac617d4
EB		 252#ifdef HAVE_AS_RELAX_OPTION
253/* If 'as' and 'ld' are relaxing tail call insns into branch always, use
254 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
255 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
256 somebody does not branch between the sethi and jmp. */
6244b14e 257#define LEAF_SIBCALL_SLOT_RESERVED_P 1
9ac617d4 258#else
6244b14e
EB		 259#define LEAF_SIBCALL_SLOT_RESERVED_P \
260 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
9ac617d4
EB		 261#endif
262
ab835497
RK		 263/* Global variables for machine-dependent things. */
264
61a55e8b 265/* Size of frame. Need to know this to emit return insns from leaf procedures.
9ac617d4
EB		 266 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
267 reload pass. This is important as the value is later used for scheduling
268 (to see what can go in a delay slot).
61a55e8b
DE		 269 APPARENT_FSIZE is the size of the stack less the register save area and less
270 the outgoing argument area. It is used when saving call preserved regs. */
6a151f87
EB		 271static HOST_WIDE_INT apparent_fsize;
272static HOST_WIDE_INT actual_fsize;
61a55e8b 273
33074e5f
RH		 274/* Number of live general or floating point registers needed to be
275 saved (as 4-byte quantities). */
e48addee
JJ		 276static int num_gfregs;
277
9ac617d4 278/* The alias set for prologue/epilogue register save/restore. */
4862826d 279static GTY(()) alias_set_type sparc_sr_alias_set;
9ac617d4 280
1da4c3a7 281/* The alias set for the structure return value. */
4862826d 282static GTY(()) alias_set_type struct_value_alias_set;
1da4c3a7 283
563c12b0
RH		 284/* Vector to say how input registers are mapped to output registers.
285 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
286 eliminate it. You must use -fomit-frame-pointer to get that. */
d70e94ec 287char leaf_reg_remap[] =
ab835497
RK		 288{ 0, 1, 2, 3, 4, 5, 6, 7,
289 -1, -1, -1, -1, -1, -1, 14, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 8, 9, 10, 11, 12, 13, -1, 15,
292
293 32, 33, 34, 35, 36, 37, 38, 39,
294 40, 41, 42, 43, 44, 45, 46, 47,
295 48, 49, 50, 51, 52, 53, 54, 55,
61a55e8b
DE		 296 56, 57, 58, 59, 60, 61, 62, 63,
297 64, 65, 66, 67, 68, 69, 70, 71,
298 72, 73, 74, 75, 76, 77, 78, 79,
299 80, 81, 82, 83, 84, 85, 86, 87,
300 88, 89, 90, 91, 92, 93, 94, 95,
c4ce6853 301 96, 97, 98, 99, 100};
ab835497 302
7d167afd
JJ		 303/* Vector, indexed by hard register number, which contains 1
304 for a register that is allowable in a candidate for leaf
305 function treatment. */
306char sparc_leaf_regs[] =
307{ 1, 1, 1, 1, 1, 1, 1, 1,
308 0, 0, 0, 0, 0, 0, 1, 0,
309 0, 0, 0, 0, 0, 0, 0, 0,
310 1, 1, 1, 1, 1, 1, 0, 1,
311 1, 1, 1, 1, 1, 1, 1, 1,
312 1, 1, 1, 1, 1, 1, 1, 1,
313 1, 1, 1, 1, 1, 1, 1, 1,
314 1, 1, 1, 1, 1, 1, 1, 1,
315 1, 1, 1, 1, 1, 1, 1, 1,
316 1, 1, 1, 1, 1, 1, 1, 1,
317 1, 1, 1, 1, 1, 1, 1, 1,
318 1, 1, 1, 1, 1, 1, 1, 1,
319 1, 1, 1, 1, 1};
320
d1b38208 321struct GTY(()) machine_function
5751a10b
JJ		 322{
323 /* Some local-dynamic TLS symbol name. */
324 const char *some_ld_name;
5be9b7a1
EB		 325
326 /* True if the current function is leaf and uses only leaf regs,
327 so that the SPARC leaf function optimization can be applied.
328 Private version of current_function_uses_only_leaf_regs, see
329 sparc_expand_prologue for the rationale. */
330 int leaf_function_p;
331
332 /* True if the data calculated by sparc_expand_prologue are valid. */
333 bool prologue_data_valid_p;
5751a10b
JJ		 334};
335
5be9b7a1
EB		 336#define sparc_leaf_function_p cfun->machine->leaf_function_p
337#define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
338
9ac617d4
EB		 339/* Register we pretend to think the frame pointer is allocated to.
340 Normally, this is %fp, but if we are in a leaf procedure, this
341 is %sp+"something". We record "something" separately as it may
342 be too big for reg+constant addressing. */
9ac617d4 343static rtx frame_base_reg;
6a151f87 344static HOST_WIDE_INT frame_base_offset;
ab835497 345
4e5b002b
EB		 346/* 1 if the next opcode is to be specially indented. */
347int sparc_indent_opcode = 0;
348
fe609b0f 349static bool sparc_handle_option (size_t, const char *, int);
e80d5f80 350static void sparc_init_modes (void);
5c4f4b18 351static void scan_record_type (tree, int *, int *, int *);
e80d5f80
KG		 352static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
353 tree, int, int, int *, int *);
354
355static int supersparc_adjust_cost (rtx, rtx, rtx, int);
356static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
357
358static void sparc_output_addr_vec (rtx);
359static void sparc_output_addr_diff_vec (rtx);
360static void sparc_output_deferred_case_vectors (void);
c6c3dba9 361static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
3e2cc1d1 362static rtx sparc_builtin_saveregs (void);
e80d5f80
KG		 363static int epilogue_renumber (rtx *, int);
364static bool sparc_assemble_integer (rtx, unsigned int, int);
365static int set_extends (rtx);
9fd52c6c 366static void load_pic_register (void);
9ac617d4 367static int save_or_restore_regs (int, int, rtx, int, int);
f8ece000 368static void emit_save_or_restore_regs (int);
9ac617d4
EB		 369static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
370static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
d1ced155
EB		 371static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
372 tree) ATTRIBUTE_UNUSED;
e80d5f80
KG		 373static int sparc_adjust_cost (rtx, rtx, rtx, int);
374static int sparc_issue_rate (void);
375static void sparc_sched_init (FILE *, int, int);
e80d5f80
KG		 376static int sparc_use_sched_lookahead (void);
377
378static void emit_soft_tfmode_libcall (const char *, int, rtx *);
379static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
380static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
381static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
382static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
383
384static bool sparc_function_ok_for_sibcall (tree, tree);
c15c90bb 385static void sparc_init_libfuncs (void);
16f59241
JM		 386static void sparc_init_builtins (void);
387static void sparc_vis_init_builtins (void);
388static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
f311c3b4 389static tree sparc_fold_builtin (tree, int, tree *, bool);
8b0096b4
JM		 390static int sparc_vis_mul8x16 (int, int);
391static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
e80d5f80
KG		 392static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
393 HOST_WIDE_INT, tree);
3101faab
KG		 394static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
395 HOST_WIDE_INT, const_tree);
5751a10b
JJ		 396static struct machine_function * sparc_init_machine_status (void);
397static bool sparc_cannot_force_const_mem (rtx);
398static rtx sparc_tls_get_addr (void);
399static rtx sparc_tls_got (void);
400static const char *get_some_local_dynamic_name (void);
401static int get_some_local_dynamic_name_1 (rtx *, void *);
f40751dd 402static bool sparc_rtx_costs (rtx, int, int, int *, bool);
586de218 403static bool sparc_promote_prototypes (const_tree);
3e2cc1d1 404static rtx sparc_struct_value_rtx (tree, int);
cde0f3fd
PB		 405static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
406 int *, const_tree, int);
586de218 407static bool sparc_return_in_memory (const_tree, const_tree);
3e2cc1d1 408static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
d7bd8aeb 409static void sparc_va_start (tree, rtx);
726a989a 410static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
c75d6010 411static bool sparc_vector_mode_supported_p (enum machine_mode);
208384fd
EB		 412static bool sparc_tls_referenced_p (rtx);
413static rtx legitimize_tls_address (rtx);
414static rtx legitimize_pic_address (rtx, rtx);
506d7b68 415static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
8cd5a4e0 416static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
586de218 417 enum machine_mode, const_tree, bool);
78a52f11
RH		 418static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *,
419 enum machine_mode, tree, bool);
e54c7471 420static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
fdbe66f2 421static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5e77eb53 422static void sparc_file_end (void);
b52b1749 423static bool sparc_frame_pointer_required (void);
7b5cbb57 424static bool sparc_can_eliminate (const int, const int);
7269aee7 425#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
3101faab 426static const char *sparc_mangle_type (const_tree);
7269aee7 427#endif
809e78cc 428static void sparc_trampoline_init (rtx, tree, rtx);
5a82ecd9 429\f
07a43492 430#ifdef SUBTARGET_ATTRIBUTE_TABLE
5a82ecd9
ILT		 431/* Table of valid machine attributes. */
432static const struct attribute_spec sparc_attribute_table[] =
433{
434 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
435 SUBTARGET_ATTRIBUTE_TABLE,
436 { NULL, 0, 0, false, false, false, NULL }
437};
07a43492 438#endif
61a55e8b
DE		 439\f
440/* Option handling. */
441
a0a301fc
DE		 442/* Parsed value. */
443enum cmodel sparc_cmodel;
444
1cb36a98
RH		 445char sparc_hard_reg_printed[8];
446
16956f6e
DE		 447struct sparc_cpu_select sparc_select[] =
448{
449 /* switch name, tune arch */
450 { (char *)0, "default", 1, 1 },
451 { (char *)0, "-mcpu=", 1, 1 },
452 { (char *)0, "-mtune=", 1, 0 },
db3d4438 453 { 0, 0, 0, 0 }
16956f6e 454};
733f53f5 455
16956f6e
DE		 456/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
457enum processor_type sparc_cpu;
fe609b0f
EB		 458
459/* Whether\fan FPU option was specified. */
460static bool fpu_option_set = false;
461
672a6f42 462/* Initialize the GCC target structure. */
301d03af 463
d1ced155 464/* The default is to use .half rather than .short for aligned HI objects. */
301d03af
RS		 465#undef TARGET_ASM_ALIGNED_HI_OP
466#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
301d03af
RS		 467
468#undef TARGET_ASM_UNALIGNED_HI_OP
469#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
470#undef TARGET_ASM_UNALIGNED_SI_OP
471#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
472#undef TARGET_ASM_UNALIGNED_DI_OP
473#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
474
475/* The target hook has to handle DI-mode values. */
476#undef TARGET_ASM_INTEGER
477#define TARGET_ASM_INTEGER sparc_assemble_integer
478
08c148a8 479#undef TARGET_ASM_FUNCTION_PROLOGUE
9ac617d4 480#define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
08c148a8 481#undef TARGET_ASM_FUNCTION_EPILOGUE
9ac617d4 482#define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
733f53f5 483
c237e94a
ZW		 484#undef TARGET_SCHED_ADJUST_COST
485#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
486#undef TARGET_SCHED_ISSUE_RATE
487#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
c237e94a
ZW		 488#undef TARGET_SCHED_INIT
489#define TARGET_SCHED_INIT sparc_sched_init
fae15c93
VM		 490#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
491#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
c237e94a 492
4977bab6
ZW		 493#undef TARGET_FUNCTION_OK_FOR_SIBCALL
494#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
495
c15c90bb
ZW		 496#undef TARGET_INIT_LIBFUNCS
497#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
16f59241
JM		 498#undef TARGET_INIT_BUILTINS
499#define TARGET_INIT_BUILTINS sparc_init_builtins
500
506d7b68
PB		 501#undef TARGET_LEGITIMIZE_ADDRESS
502#define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
503
16f59241
JM		 504#undef TARGET_EXPAND_BUILTIN
505#define TARGET_EXPAND_BUILTIN sparc_expand_builtin
8b0096b4
JM		 506#undef TARGET_FOLD_BUILTIN
507#define TARGET_FOLD_BUILTIN sparc_fold_builtin
c15c90bb 508
fdbe66f2 509#if TARGET_TLS
5751a10b
JJ		 510#undef TARGET_HAVE_TLS
511#define TARGET_HAVE_TLS true
512#endif
fdbe66f2 513
5751a10b
JJ		 514#undef TARGET_CANNOT_FORCE_CONST_MEM
515#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
516
c590b625
RH		 517#undef TARGET_ASM_OUTPUT_MI_THUNK
518#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
3961e8fe 519#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
b9bf58e5 520#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
c590b625 521
3c50106f
RH		 522#undef TARGET_RTX_COSTS
523#define TARGET_RTX_COSTS sparc_rtx_costs
dcefdf67 524#undef TARGET_ADDRESS_COST
f40751dd 525#define TARGET_ADDRESS_COST hook_int_rtx_bool_0
3c50106f 526
cde0f3fd
PB		 527#undef TARGET_PROMOTE_FUNCTION_MODE
528#define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
3e2cc1d1
KH		 529
530#undef TARGET_PROMOTE_PROTOTYPES
531#define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
532
533#undef TARGET_STRUCT_VALUE_RTX
534#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
535#undef TARGET_RETURN_IN_MEMORY
536#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
fe984136
RH		 537#undef TARGET_MUST_PASS_IN_STACK
538#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
8cd5a4e0
RH		 539#undef TARGET_PASS_BY_REFERENCE
540#define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
78a52f11
RH		 541#undef TARGET_ARG_PARTIAL_BYTES
542#define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
3e2cc1d1
KH		 543
544#undef TARGET_EXPAND_BUILTIN_SAVEREGS
545#define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
546#undef TARGET_STRICT_ARGUMENT_NAMING
547#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
548
d7bd8aeb
JJ		 549#undef TARGET_EXPAND_BUILTIN_VA_START
550#define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
5f393b25
JM		 551#undef TARGET_GIMPLIFY_VA_ARG_EXPR
552#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
553
c75d6010
JM		 554#undef TARGET_VECTOR_MODE_SUPPORTED_P
555#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
556
e54c7471
EB		 557#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
558#define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
559
07a43492
DJ		 560#ifdef SUBTARGET_INSERT_ATTRIBUTES
561#undef TARGET_INSERT_ATTRIBUTES
562#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
563#endif
564
565#ifdef SUBTARGET_ATTRIBUTE_TABLE
566#undef TARGET_ATTRIBUTE_TABLE
567#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
568#endif
569
0e4e8dab 570#undef TARGET_RELAXED_ORDERING
548a6c4f 571#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
445cf5eb 572
fe609b0f
EB		 573#undef TARGET_DEFAULT_TARGET_FLAGS
574#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
575#undef TARGET_HANDLE_OPTION
576#define TARGET_HANDLE_OPTION sparc_handle_option
577
f06fb22b 578#if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
fdbe66f2
EB		 579#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
580#define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
581#endif
582
c81739f7 583#undef TARGET_ASM_FILE_END
5e77eb53
EB		 584#define TARGET_ASM_FILE_END sparc_file_end
585
b52b1749
AS		 586#undef TARGET_FRAME_POINTER_REQUIRED
587#define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
588
7b5cbb57
AS		 589#undef TARGET_CAN_ELIMINATE
590#define TARGET_CAN_ELIMINATE sparc_can_eliminate
591
7269aee7 592#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3
JB		 593#undef TARGET_MANGLE_TYPE
594#define TARGET_MANGLE_TYPE sparc_mangle_type
7269aee7
AH		 595#endif
596
c6c3dba9
PB		 597#undef TARGET_LEGITIMATE_ADDRESS_P
598#define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
599
809e78cc
RH		 600#undef TARGET_TRAMPOLINE_INIT
601#define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
602
f6897b10 603struct gcc_target targetm = TARGET_INITIALIZER;
fe609b0f
EB		 604
605/* Implement TARGET_HANDLE_OPTION. */
606
607static bool
608sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
609{
610 switch (code)
611 {
612 case OPT_mfpu:
613 case OPT_mhard_float:
614 case OPT_msoft_float:
615 fpu_option_set = true;
616 break;
617
618 case OPT_mcpu_:
619 sparc_select[1].string = arg;
620 break;
621
622 case OPT_mtune_:
623 sparc_select[2].string = arg;
624 break;
fe609b0f
EB		 625 }
626
627 return true;
628}
629
61a55e8b
DE		 630/* Validate and override various options, and do some machine dependent
631 initialization. */
632
633void
fc27d102 634sparc_override_options (void)
61a55e8b 635{
a0a301fc 636 static struct code_model {
8b60264b 637 const char *const name;
32e8bb8e 638 const enum cmodel value;
8b60264b 639 } const cmodels[] = {
a0a301fc
DE		 640 { "32", CM_32 },
641 { "medlow", CM_MEDLOW },
642 { "medmid", CM_MEDMID },
643 { "medany", CM_MEDANY },
644 { "embmedany", CM_EMBMEDANY },
32e8bb8e 645 { NULL, (enum cmodel) 0 }
a0a301fc 646 };
8b60264b 647 const struct code_model *cmodel;
16956f6e 648 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
733f53f5 649 static struct cpu_default {
8b60264b
KG		 650 const int cpu;
651 const char *const name;
652 } const cpu_default[] = {
a0a301fc 653 /* There must be one entry here for each TARGET_CPU value. */
16956f6e 654 { TARGET_CPU_sparc, "cypress" },
3592ea0d 655 { TARGET_CPU_sparclet, "tsc701" },
16956f6e 656 { TARGET_CPU_sparclite, "f930" },
a0a301fc 657 { TARGET_CPU_v8, "v8" },
8947065c
RH		 658 { TARGET_CPU_hypersparc, "hypersparc" },
659 { TARGET_CPU_sparclite86x, "sparclite86x" },
a0a301fc
DE		 660 { TARGET_CPU_supersparc, "supersparc" },
661 { TARGET_CPU_v9, "v9" },
ba542005 662 { TARGET_CPU_ultrasparc, "ultrasparc" },
fae15c93 663 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
4c837a1e 664 { TARGET_CPU_niagara, "niagara" },
9eeaed6e 665 { TARGET_CPU_niagara2, "niagara2" },
db3d4438 666 { 0, 0 }
733f53f5 667 };
8b60264b 668 const struct cpu_default *def;
16956f6e 669 /* Table of values for -m{cpu,tune}=. */
733f53f5 670 static struct cpu_table {
8b60264b
KG		 671 const char *const name;
672 const enum processor_type processor;
673 const int disable;
674 const int enable;
675 } const cpu_table[] = {
16956f6e
DE		 676 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
677 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
678 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
733f53f5 679 /* TI TMS390Z55 supersparc */
16956f6e
DE		 680 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
681 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
733f53f5
DE		 682 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
683 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
16956f6e
DE		 684 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
685 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
8947065c 686 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
d3ec6b06
VM		 687 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
688 MASK_SPARCLITE },
16956f6e 689 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
733f53f5 690 /* TEMIC sparclet */
3592ea0d 691 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
16956f6e 692 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
5cb01b65
JJ		 693 /* TI ultrasparc I, II, IIi */
694 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
695 /* Although insns using %y are deprecated, it is a clear win on current
80ffc95e 696 ultrasparcs. */
3276910d 697 |MASK_DEPRECATED_V8_INSNS},
fae15c93
VM		 698 /* TI ultrasparc III */
699 /* ??? Check if %y issue still holds true in ultra3. */
700 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
4c837a1e
DM		 701 /* UltraSPARC T1 */
702 { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
9eeaed6e 703 { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
81f40b79 704 { 0, (enum processor_type) 0, 0, 0 }
733f53f5 705 };
8b60264b
KG		 706 const struct cpu_table *cpu;
707 const struct sparc_cpu_select *sel;
a0a301fc 708 int fpu;
4900aa61 709
a0a301fc
DE		 710#ifndef SPARC_BI_ARCH
711 /* Check for unsupported architecture size. */
712 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
3276910d
RK		 713 error ("%s is not supported by this configuration",
714 DEFAULT_ARCH32_P ? "-m64" : "-m32");
a0a301fc
DE		 715#endif
716
4710d3eb
JJ		 717 /* We force all 64bit archs to use 128 bit long double */
718 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
719 {
720 error ("-mlong-double-64 not allowed with -m64");
721 target_flags |= MASK_LONG_DOUBLE_128;
722 }
723
a0a301fc
DE		 724 /* Code model selection. */
725 sparc_cmodel = SPARC_DEFAULT_CMODEL;
4900aa61 726
345a6161
DM		 727#ifdef SPARC_BI_ARCH
728 if (TARGET_ARCH32)
729 sparc_cmodel = CM_32;
730#endif
731
a0a301fc
DE		 732 if (sparc_cmodel_string != NULL)
733 {
734 if (TARGET_ARCH64)
735 {
736 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
737 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
738 break;
739 if (cmodel->name == NULL)
740 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
741 else
742 sparc_cmodel = cmodel->value;
743 }
744 else
745 error ("-mcmodel= is not supported on 32 bit systems");
746 }
16956f6e 747
06063fa2 748 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1f1406b4 749
a0a301fc 750 /* Set the default CPU. */
16956f6e
DE		 751 for (def = &cpu_default[0]; def->name; ++def)
752 if (def->cpu == TARGET_CPU_DEFAULT)
753 break;
f5f7d171 754 gcc_assert (def->name);
16956f6e
DE		 755 sparc_select[0].string = def->name;
756
757 for (sel = &sparc_select[0]; sel->name; ++sel)
61a55e8b 758 {
16956f6e 759 if (sel->string)
733f53f5 760 {
16956f6e
DE		 761 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
762 if (! strcmp (sel->string, cpu->name))
763 {
764 if (sel->set_tune_p)
765 sparc_cpu = cpu->processor;
766
767 if (sel->set_arch_p)
768 {
769 target_flags &= ~cpu->disable;
770 target_flags |= cpu->enable;
771 }
772 break;
773 }
774
775 if (! cpu->name)
776 error ("bad value (%s) for %s switch", sel->string, sel->name);
733f53f5 777 }
61a55e8b 778 }
97da85b7 779
1f1406b4 780 /* If -mfpu or -mno-fpu was explicitly used, don't override with
fe609b0f
EB		 781 the processor default. */
782 if (fpu_option_set)
783 target_flags = (target_flags & ~MASK_FPU) | fpu;
1f1406b4 784
a5774a7d
JJ		 785 /* Don't allow -mvis if FPU is disabled. */
786 if (! TARGET_FPU)
787 target_flags &= ~MASK_VIS;
788
789 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
790 are available.
791 -m64 also implies v9. */
792 if (TARGET_VIS || TARGET_ARCH64)
c4031a04
JJ		 793 {
794 target_flags |= MASK_V9;
795 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
796 }
a5774a7d 797
16956f6e
DE		 798 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
799 if (TARGET_V9 && TARGET_ARCH32)
733f53f5 800 target_flags |= MASK_DEPRECATED_V8_INSNS;
61a55e8b 801
345a6161
DM		 802 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
803 if (! TARGET_V9 || TARGET_ARCH64)
284d86e9
JC		 804 target_flags &= ~MASK_V8PLUS;
805
82d6b402
RH		 806 /* Don't use stack biasing in 32 bit mode. */
807 if (TARGET_ARCH32)
808 target_flags &= ~MASK_STACK_BIAS;
4900aa61 809
efa3896a 810 /* Supply a default value for align_functions. */
fae15c93
VM		 811 if (align_functions == 0
812 && (sparc_cpu == PROCESSOR_ULTRASPARC
4c837a1e 813 || sparc_cpu == PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 814 || sparc_cpu == PROCESSOR_NIAGARA
815 || sparc_cpu == PROCESSOR_NIAGARA2))
efa3896a 816 align_functions = 32;
bf62bbf1 817
82d6b402
RH		 818 /* Validate PCC_STRUCT_RETURN. */
819 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
820 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
821
301d03af
RS		 822 /* Only use .uaxword when compiling for a 64-bit target. */
823 if (!TARGET_ARCH64)
824 targetm.asm_out.unaligned_op.di = NULL;
825
61a55e8b
DE		 826 /* Do various machine dependent initializations. */
827 sparc_init_modes ();
5751a10b 828
1da4c3a7 829 /* Acquire unique alias sets for our private stuff. */
9ac617d4 830 sparc_sr_alias_set = new_alias_set ();
1da4c3a7 831 struct_value_alias_set = new_alias_set ();
9ac617d4 832
5751a10b
JJ		 833 /* Set up function hooks. */
834 init_machine_status = sparc_init_machine_status;
18df6de9
DM		 835
836 switch (sparc_cpu)
837 {
838 case PROCESSOR_V7:
839 case PROCESSOR_CYPRESS:
840 sparc_costs = &cypress_costs;
841 break;
842 case PROCESSOR_V8:
843 case PROCESSOR_SPARCLITE:
844 case PROCESSOR_SUPERSPARC:
845 sparc_costs = &supersparc_costs;
846 break;
847 case PROCESSOR_F930:
848 case PROCESSOR_F934:
849 case PROCESSOR_HYPERSPARC:
850 case PROCESSOR_SPARCLITE86X:
851 sparc_costs = &hypersparc_costs;
852 break;
853 case PROCESSOR_SPARCLET:
854 case PROCESSOR_TSC701:
855 sparc_costs = &sparclet_costs;
856 break;
857 case PROCESSOR_V9:
858 case PROCESSOR_ULTRASPARC:
859 sparc_costs = &ultrasparc_costs;
860 break;
861 case PROCESSOR_ULTRASPARC3:
862 sparc_costs = &ultrasparc3_costs;
863 break;
4c837a1e
DM		 864 case PROCESSOR_NIAGARA:
865 sparc_costs = &niagara_costs;
866 break;
9eeaed6e
DM		 867 case PROCESSOR_NIAGARA2:
868 sparc_costs = &niagara2_costs;
869 break;
18df6de9 870 };
ed965309
JJ		 871
872#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
873 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
874 target_flags |= MASK_LONG_DOUBLE_128;
875#endif
47eb5b32
ZD		 876
877 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
878 set_param_value ("simultaneous-prefetches",
879 ((sparc_cpu == PROCESSOR_ULTRASPARC
9eeaed6e
DM		 880 || sparc_cpu == PROCESSOR_NIAGARA
881 || sparc_cpu == PROCESSOR_NIAGARA2)
47eb5b32
ZD		 882 ? 2
883 : (sparc_cpu == PROCESSOR_ULTRASPARC3
884 ? 8 : 3)));
885 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
4900aa61 886 set_param_value ("l1-cache-line-size",
47eb5b32
ZD		 887 ((sparc_cpu == PROCESSOR_ULTRASPARC
888 || sparc_cpu == PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 889 || sparc_cpu == PROCESSOR_NIAGARA
890 || sparc_cpu == PROCESSOR_NIAGARA2)
47eb5b32 891 ? 64 : 32));
61a55e8b
DE		 892}
893\f
cd5fb1ee
DE		 894/* Miscellaneous utilities. */
895
896/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
897 or branch on register contents instructions. */
898
899int
fc27d102 900v9_regcmp_p (enum rtx_code code)
cd5fb1ee
DE		 901{
902 return (code == EQ || code == NE || code == GE || code == LT
903 || code == LE || code == GT);
904}
bfd6bc60 905
62190128
DM		 906/* Nonzero if OP is a floating point constant which can
907 be loaded into an integer register using a single
908 sethi instruction. */
909
910int
fc27d102 911fp_sethi_p (rtx op)
62190128
DM		 912{
913 if (GET_CODE (op) == CONST_DOUBLE)
914 {
915 REAL_VALUE_TYPE r;
916 long i;
917
918 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 919 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 920 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
62190128
DM		 921 }
922
923 return 0;
924}
925
926/* Nonzero if OP is a floating point constant which can
927 be loaded into an integer register using a single
928 mov instruction. */
929
930int
fc27d102 931fp_mov_p (rtx op)
62190128
DM		 932{
933 if (GET_CODE (op) == CONST_DOUBLE)
934 {
935 REAL_VALUE_TYPE r;
936 long i;
937
938 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 939 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 940 return SPARC_SIMM13_P (i);
62190128
DM		 941 }
942
943 return 0;
944}
945
946/* Nonzero if OP is a floating point constant which can
947 be loaded into an integer register using a high/losum
948 instruction sequence. */
949
950int
fc27d102 951fp_high_losum_p (rtx op)
62190128
DM		 952{
953 /* The constraints calling this should only be in
954 SFmode move insns, so any constant which cannot
955 be moved using a single insn will do. */
956 if (GET_CODE (op) == CONST_DOUBLE)
957 {
958 REAL_VALUE_TYPE r;
959 long i;
960
961 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 962 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 963 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
62190128
DM		 964 }
965
966 return 0;
967}
968
bea5071f
EB		 969/* Expand a move instruction. Return true if all work is done. */
970
971bool
972sparc_expand_move (enum machine_mode mode, rtx *operands)
973{
974 /* Handle sets of MEM first. */
975 if (GET_CODE (operands[0]) == MEM)
976 {
977 /* 0 is a register (or a pair of registers) on SPARC. */
978 if (register_or_zero_operand (operands[1], mode))
979 return false;
980
981 if (!reload_in_progress)
982 {
983 operands[0] = validize_mem (operands[0]);
984 operands[1] = force_reg (mode, operands[1]);
985 }
986 }
987
988 /* Fixup TLS cases. */
38fc66ba
EB		 989 if (TARGET_HAVE_TLS
990 && CONSTANT_P (operands[1])
38fc66ba
EB		 991 && sparc_tls_referenced_p (operands [1]))
992 {
208384fd
EB		 993 operands[1] = legitimize_tls_address (operands[1]);
994 return false;
38fc66ba 995 }
4900aa61 996
bea5071f
EB		 997 /* Fixup PIC cases. */
998 if (flag_pic && CONSTANT_P (operands[1]))
999 {
1000 if (pic_address_needs_scratch (operands[1]))
208384fd 1001 operands[1] = legitimize_pic_address (operands[1], NULL_RTX);
bea5071f 1002
1910440e
RS		 1003 /* VxWorks does not impose a fixed gap between segments; the run-time
1004 gap can be different from the object-file gap. We therefore can't
1005 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1006 are absolutely sure that X is in the same segment as the GOT.
1007 Unfortunately, the flexibility of linker scripts means that we
1008 can't be sure of that in general, so assume that _G_O_T_-relative
1009 accesses are never valid on VxWorks. */
1010 if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP)
bea5071f 1011 {
1910440e
RS		 1012 if (mode == SImode)
1013 {
1014 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1015 return true;
1016 }
bea5071f 1017
1910440e
RS		 1018 if (mode == DImode)
1019 {
1020 gcc_assert (TARGET_ARCH64);
1021 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1022 return true;
1023 }
bea5071f
EB		 1024 }
1025
1026 if (symbolic_operand (operands[1], mode))
1027 {
1028 operands[1] = legitimize_pic_address (operands[1],
208384fd
EB		 1029 reload_in_progress
1030 ? operands[0] : NULL_RTX);
bea5071f
EB		 1031 return false;
1032 }
1033 }
1034
1035 /* If we are trying to toss an integer constant into FP registers,
1036 or loading a FP or vector constant, force it into memory. */
1037 if (CONSTANT_P (operands[1])
1038 && REG_P (operands[0])
1039 && (SPARC_FP_REG_P (REGNO (operands[0]))
1040 || SCALAR_FLOAT_MODE_P (mode)
1041 || VECTOR_MODE_P (mode)))
1042 {
1043 /* emit_group_store will send such bogosity to us when it is
1044 not storing directly into memory. So fix this up to avoid
1045 crashes in output_constant_pool. */
1046 if (operands [1] == const0_rtx)
1047 operands[1] = CONST0_RTX (mode);
1048
1049 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1050 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1051 && const_zero_operand (operands[1], mode))
1052 return false;
1053
1054 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1055 /* We are able to build any SF constant in integer registers
1056 with at most 2 instructions. */
1057 && (mode == SFmode
1058 /* And any DF constant in integer registers. */
1059 || (mode == DFmode
1060 && (reload_completed || reload_in_progress))))
1061 return false;
1062
1063 operands[1] = force_const_mem (mode, operands[1]);
1064 if (!reload_in_progress)
1065 operands[1] = validize_mem (operands[1]);
1066 return false;
1067 }
1068
1069 /* Accept non-constants and valid constants unmodified. */
1070 if (!CONSTANT_P (operands[1])
1071 || GET_CODE (operands[1]) == HIGH
1072 || input_operand (operands[1], mode))
1073 return false;
1074
1075 switch (mode)
1076 {
1077 case QImode:
1078 /* All QImode constants require only one insn, so proceed. */
1079 break;
1080
1081 case HImode:
1082 case SImode:
1083 sparc_emit_set_const32 (operands[0], operands[1]);
1084 return true;
1085
1086 case DImode:
1087 /* input_operand should have filtered out 32-bit mode. */
1088 sparc_emit_set_const64 (operands[0], operands[1]);
1089 return true;
4900aa61 1090
bea5071f
EB		 1091 default:
1092 gcc_unreachable ();
1093 }
1094
1095 return false;
1096}
1097
1098/* Load OP1, a 32-bit constant, into OP0, a register.
1099 We know it can't be done in one insn when we get
1100 here, the move expander guarantees this. */
1101
e0d80184 1102void
fc27d102 1103sparc_emit_set_const32 (rtx op0, rtx op1)
e0d80184
DM		 1104{
1105 enum machine_mode mode = GET_MODE (op0);
1106 rtx temp;
1107
e0d80184
DM		 1108 if (reload_in_progress || reload_completed)
1109 temp = op0;
284d86e9 1110 else
e0d80184
DM		 1111 temp = gen_reg_rtx (mode);
1112
71648202
DM		 1113 if (GET_CODE (op1) == CONST_INT)
1114 {
0e5d569c
EB		 1115 gcc_assert (!small_int_operand (op1, mode)
1116 && !const_high_operand (op1, mode));
1117
71648202
DM		 1118 /* Emit them as real moves instead of a HIGH/LO_SUM,
1119 this way CSE can see everything and reuse intermediate
1120 values if it wants. */
0e5d569c
EB		 1121 emit_insn (gen_rtx_SET (VOIDmode, temp,
1122 GEN_INT (INTVAL (op1)
1123 & ~(HOST_WIDE_INT)0x3ff)));
f2827474 1124
71648202
DM		 1125 emit_insn (gen_rtx_SET (VOIDmode,
1126 op0,
f2827474 1127 gen_rtx_IOR (mode, temp,
71648202
DM		 1128 GEN_INT (INTVAL (op1) & 0x3ff))));
1129 }
1130 else
1131 {
1132 /* A symbol, emit in the traditional way. */
f2827474
RK		 1133 emit_insn (gen_rtx_SET (VOIDmode, temp,
1134 gen_rtx_HIGH (mode, op1)));
71648202 1135 emit_insn (gen_rtx_SET (VOIDmode,
f2827474 1136 op0, gen_rtx_LO_SUM (mode, temp, op1)));
71648202 1137 }
e0d80184
DM		 1138}
1139
1d511ed5 1140/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
0e40b5f2 1141 If TEMP is nonzero, we are forbidden to use any other scratch
1d511ed5
EB		 1142 registers. Otherwise, we are allowed to generate them as needed.
1143
1144 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1145 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
bea5071f 1146
e0d80184 1147void
1d511ed5 1148sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
e0d80184 1149{
1d511ed5
EB		 1150 rtx temp1, temp2, temp3, temp4, temp5;
1151 rtx ti_temp = 0;
3968de80 1152
1d511ed5 1153 if (temp && GET_MODE (temp) == TImode)
3968de80 1154 {
1d511ed5
EB		 1155 ti_temp = temp;
1156 temp = gen_rtx_REG (DImode, REGNO (temp));
3968de80
DD		 1157 }
1158
1d511ed5 1159 /* SPARC-V9 code-model support. */
e0d80184 1160 switch (sparc_cmodel)
284d86e9 1161 {
e0d80184
DM		 1162 case CM_MEDLOW:
1163 /* The range spanned by all instructions in the object is less
1164 than 2^31 bytes (2GB) and the distance from any instruction
1165 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1166 than 2^31 bytes (2GB).
ab835497 1167
e0d80184
DM		 1168 The executable must be in the low 4TB of the virtual address
1169 space.
61a55e8b 1170
1d511ed5
EB		 1171 sethi %hi(symbol), %temp1
1172 or %temp1, %lo(symbol), %reg */
1173 if (temp)
1174 temp1 = temp; /* op0 is allowed. */
1175 else
1176 temp1 = gen_reg_rtx (DImode);
1177
9208e4b2
DM		 1178 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1179 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
e0d80184 1180 break;
61a55e8b 1181
e0d80184
DM		 1182 case CM_MEDMID:
1183 /* The range spanned by all instructions in the object is less
1184 than 2^31 bytes (2GB) and the distance from any instruction
1185 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1186 than 2^31 bytes (2GB).
1187
1188 The executable must be in the low 16TB of the virtual address
1189 space.
1190
1191 sethi %h44(symbol), %temp1
1192 or %temp1, %m44(symbol), %temp2
1193 sllx %temp2, 12, %temp3
1194 or %temp3, %l44(symbol), %reg */
1d511ed5
EB		 1195 if (temp)
1196 {
1197 temp1 = op0;
1198 temp2 = op0;
1199 temp3 = temp; /* op0 is allowed. */
1200 }
1201 else
1202 {
1203 temp1 = gen_reg_rtx (DImode);
1204 temp2 = gen_reg_rtx (DImode);
1205 temp3 = gen_reg_rtx (DImode);
1206 }
1207
1208 emit_insn (gen_seth44 (temp1, op1));
1209 emit_insn (gen_setm44 (temp2, temp1, op1));
1210 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1211 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1212 emit_insn (gen_setl44 (op0, temp3, op1));
e0d80184 1213 break;
61a55e8b 1214
e0d80184
DM		 1215 case CM_MEDANY:
1216 /* The range spanned by all instructions in the object is less
1217 than 2^31 bytes (2GB) and the distance from any instruction
1218 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1219 than 2^31 bytes (2GB).
1220
1221 The executable can be placed anywhere in the virtual address
1222 space.
1223
1224 sethi %hh(symbol), %temp1
1225 sethi %lm(symbol), %temp2
1226 or %temp1, %hm(symbol), %temp3
1d511ed5
EB		 1227 sllx %temp3, 32, %temp4
1228 or %temp4, %temp2, %temp5
1229 or %temp5, %lo(symbol), %reg */
1230 if (temp)
3968de80 1231 {
1d511ed5
EB		 1232 /* It is possible that one of the registers we got for operands[2]
1233 might coincide with that of operands[0] (which is why we made
1234 it TImode). Pick the other one to use as our scratch. */
1235 if (rtx_equal_p (temp, op0))
1236 {
f5f7d171
JM		 1237 gcc_assert (ti_temp);
1238 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1d511ed5
EB		 1239 }
1240 temp1 = op0;
1241 temp2 = temp; /* op0 is _not_ allowed, see above. */
1242 temp3 = op0;
1243 temp4 = op0;
1244 temp5 = op0;
1245 }
1246 else
1247 {
1248 temp1 = gen_reg_rtx (DImode);
1249 temp2 = gen_reg_rtx (DImode);
1250 temp3 = gen_reg_rtx (DImode);
1251 temp4 = gen_reg_rtx (DImode);
1252 temp5 = gen_reg_rtx (DImode);
3968de80 1253 }
61a55e8b 1254
1d511ed5
EB		 1255 emit_insn (gen_sethh (temp1, op1));
1256 emit_insn (gen_setlm (temp2, op1));
1257 emit_insn (gen_sethm (temp3, temp1, op1));
1258 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1259 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1260 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1261 gen_rtx_PLUS (DImode, temp4, temp2)));
1262 emit_insn (gen_setlo (op0, temp5, op1));
e0d80184 1263 break;
61a55e8b 1264
e0d80184
DM		 1265 case CM_EMBMEDANY:
1266 /* Old old old backwards compatibility kruft here.
1267 Essentially it is MEDLOW with a fixed 64-bit
1268 virtual base added to all data segment addresses.
1269 Text-segment stuff is computed like MEDANY, we can't
1270 reuse the code above because the relocation knobs
1271 look different.
1272
1273 Data segment: sethi %hi(symbol), %temp1
1d511ed5
EB		 1274 add %temp1, EMBMEDANY_BASE_REG, %temp2
1275 or %temp2, %lo(symbol), %reg */
e0d80184
DM		 1276 if (data_segment_operand (op1, GET_MODE (op1)))
1277 {
1d511ed5
EB		 1278 if (temp)
1279 {
1280 temp1 = temp; /* op0 is allowed. */
1281 temp2 = op0;
1282 }
1283 else
1284 {
1285 temp1 = gen_reg_rtx (DImode);
1286 temp2 = gen_reg_rtx (DImode);
1287 }
1288
e0d80184 1289 emit_insn (gen_embmedany_sethi (temp1, op1));
1d511ed5
EB		 1290 emit_insn (gen_embmedany_brsum (temp2, temp1));
1291 emit_insn (gen_embmedany_losum (op0, temp2, op1));
e0d80184 1292 }
1d511ed5
EB		 1293
1294 /* Text segment: sethi %uhi(symbol), %temp1
1295 sethi %hi(symbol), %temp2
1296 or %temp1, %ulo(symbol), %temp3
1297 sllx %temp3, 32, %temp4
1298 or %temp4, %temp2, %temp5
1299 or %temp5, %lo(symbol), %reg */
e0d80184
DM		 1300 else
1301 {
1d511ed5 1302 if (temp)
3968de80 1303 {
1d511ed5
EB		 1304 /* It is possible that one of the registers we got for operands[2]
1305 might coincide with that of operands[0] (which is why we made
1306 it TImode). Pick the other one to use as our scratch. */
1307 if (rtx_equal_p (temp, op0))
1308 {
f5f7d171
JM		 1309 gcc_assert (ti_temp);
1310 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1d511ed5
EB		 1311 }
1312 temp1 = op0;
1313 temp2 = temp; /* op0 is _not_ allowed, see above. */
1314 temp3 = op0;
1315 temp4 = op0;
1316 temp5 = op0;
1317 }
1318 else
1319 {
1320 temp1 = gen_reg_rtx (DImode);
1321 temp2 = gen_reg_rtx (DImode);
1322 temp3 = gen_reg_rtx (DImode);
1323 temp4 = gen_reg_rtx (DImode);
1324 temp5 = gen_reg_rtx (DImode);
3968de80 1325 }
61a55e8b 1326
1d511ed5
EB		 1327 emit_insn (gen_embmedany_textuhi (temp1, op1));
1328 emit_insn (gen_embmedany_texthi (temp2, op1));
1329 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1330 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1331 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1332 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1333 gen_rtx_PLUS (DImode, temp4, temp2)));
1334 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
e0d80184
DM		 1335 }
1336 break;
1337
1338 default:
f5f7d171 1339 gcc_unreachable ();
e0d80184
DM		 1340 }
1341}
1342
0e5d569c
EB		 1343#if HOST_BITS_PER_WIDE_INT == 32
1344void
1345sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1346{
1347 gcc_unreachable ();
1348}
1349#else
9208e4b2
DM		 1350/* These avoid problems when cross compiling. If we do not
1351 go through all this hair then the optimizer will see
1352 invalid REG_EQUAL notes or in some cases none at all. */
9bb3323d 1353static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
e80d5f80
KG		 1354static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1355static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1356static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
9208e4b2 1357
9208e4b2
DM		 1358/* The optimizer is not to assume anything about exactly
1359 which bits are set for a HIGH, they are unspecified.
1360 Unfortunately this leads to many missed optimizations
1361 during CSE. We mask out the non-HIGH bits, and matches
1362 a plain movdi, to alleviate this problem. */
9bb3323d
EB		 1363static rtx
1364gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
9208e4b2 1365{
9bb3323d 1366 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
9208e4b2 1367}
2a01c939 1368
e0d80184 1369static rtx
fc27d102 1370gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
61a55e8b 1371{
0e5d569c 1372 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
9208e4b2
DM		 1373}
1374
1375static rtx
fc27d102 1376gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
9208e4b2 1377{
0e5d569c 1378 return gen_rtx_IOR (DImode, src, GEN_INT (val));
9208e4b2
DM		 1379}
1380
1381static rtx
fc27d102 1382gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
9208e4b2 1383{
0e5d569c 1384 return gen_rtx_XOR (DImode, src, GEN_INT (val));
e0d80184 1385}
61a55e8b 1386
e0d80184
DM		 1387/* Worker routines for 64-bit constant formation on arch64.
1388 One of the key things to be doing in these emissions is
1389 to create as many temp REGs as possible. This makes it
1390 possible for half-built constants to be used later when
1391 such values are similar to something required later on.
1392 Without doing this, the optimizer cannot see such
1393 opportunities. */
2a01c939 1394
e80d5f80
KG		 1395static void sparc_emit_set_const64_quick1 (rtx, rtx,
1396 unsigned HOST_WIDE_INT, int);
2a01c939 1397
e0d80184 1398static void
fc27d102
KG		 1399sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1400 unsigned HOST_WIDE_INT low_bits, int is_neg)
e0d80184 1401{
2a01c939 1402 unsigned HOST_WIDE_INT high_bits;
a9e27770 1403
e0d80184 1404 if (is_neg)
2a01c939 1405 high_bits = (~low_bits) & 0xffffffff;
31bc9eba 1406 else
e0d80184 1407 high_bits = low_bits;
31bc9eba 1408
9bb3323d 1409 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1410 if (!is_neg)
5108f3e5
DM		 1411 {
1412 emit_insn (gen_rtx_SET (VOIDmode, op0,
1413 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1414 }
e0d80184 1415 else
5108f3e5
DM		 1416 {
1417 /* If we are XOR'ing with -1, then we should emit a one's complement
1418 instead. This way the combiner will notice logical operations
1419 such as ANDN later on and substitute. */
1420 if ((low_bits & 0x3ff) == 0x3ff)
1421 {
1422 emit_insn (gen_rtx_SET (VOIDmode, op0,
1423 gen_rtx_NOT (DImode, temp)));
1424 }
1425 else
1426 {
1427 emit_insn (gen_rtx_SET (VOIDmode, op0,
1428 gen_safe_XOR64 (temp,
9e0625a3
AO		 1429 (-(HOST_WIDE_INT)0x400
1430 | (low_bits & 0x3ff)))));
5108f3e5
DM		 1431 }
1432 }
e0d80184 1433}
61a55e8b 1434
e80d5f80
KG		 1435static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1436 unsigned HOST_WIDE_INT, int);
2a01c939 1437
e0d80184 1438static void
fc27d102
KG		 1439sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1440 unsigned HOST_WIDE_INT high_bits,
1441 unsigned HOST_WIDE_INT low_immediate,
1442 int shift_count)
e0d80184
DM		 1443{
1444 rtx temp2 = op0;
61a55e8b 1445
e0d80184
DM		 1446 if ((high_bits & 0xfffffc00) != 0)
1447 {
9bb3323d 1448 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1449 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2
DM		 1450 emit_insn (gen_rtx_SET (VOIDmode, op0,
1451 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
61a55e8b 1452 else
e0d80184 1453 temp2 = temp;
61a55e8b
DE		 1454 }
1455 else
1456 {
f710f868 1457 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184
DM		 1458 temp2 = temp;
1459 }
61a55e8b 1460
80ffc95e 1461 /* Now shift it up into place. */
9208e4b2 1462 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1463 gen_rtx_ASHIFT (DImode, temp2,
1464 GEN_INT (shift_count))));
61a55e8b 1465
e0d80184
DM		 1466 /* If there is a low immediate part piece, finish up by
1467 putting that in as well. */
1468 if (low_immediate != 0)
9208e4b2
DM		 1469 emit_insn (gen_rtx_SET (VOIDmode, op0,
1470 gen_safe_OR64 (op0, low_immediate)));
ab835497
RK		 1471}
1472
e80d5f80
KG		 1473static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1474 unsigned HOST_WIDE_INT);
2a01c939 1475
e0d80184
DM		 1476/* Full 64-bit constant decomposition. Even though this is the
1477 'worst' case, we still optimize a few things away. */
1478static void
fc27d102
KG		 1479sparc_emit_set_const64_longway (rtx op0, rtx temp,
1480 unsigned HOST_WIDE_INT high_bits,
1481 unsigned HOST_WIDE_INT low_bits)
ab835497 1482{
e0d80184 1483 rtx sub_temp;
4bf7135b 1484
e0d80184
DM		 1485 if (reload_in_progress || reload_completed)
1486 sub_temp = op0;
1487 else
1488 sub_temp = gen_reg_rtx (DImode);
1489
1490 if ((high_bits & 0xfffffc00) != 0)
1491 {
9bb3323d 1492 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1493 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2 1494 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1495 sub_temp,
9208e4b2 1496 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
e0d80184
DM		 1497 else
1498 sub_temp = temp;
1499 }
1500 else
ab835497 1501 {
f710f868 1502 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184 1503 sub_temp = temp;
ab835497 1504 }
4bf7135b 1505
e0d80184 1506 if (!reload_in_progress && !reload_completed)
284d86e9 1507 {
e0d80184
DM		 1508 rtx temp2 = gen_reg_rtx (DImode);
1509 rtx temp3 = gen_reg_rtx (DImode);
1510 rtx temp4 = gen_reg_rtx (DImode);
284d86e9 1511
9208e4b2 1512 emit_insn (gen_rtx_SET (VOIDmode, temp4,
e0d80184
DM		 1513 gen_rtx_ASHIFT (DImode, sub_temp,
1514 GEN_INT (32))));
4bf7135b 1515
9bb3323d 1516 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
e0d80184 1517 if ((low_bits & ~0xfffffc00) != 0)
f710f868
DM		 1518 {
1519 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1520 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1521 emit_insn (gen_rtx_SET (VOIDmode, op0,
1522 gen_rtx_PLUS (DImode, temp4, temp3)));
1523 }
1524 else
1525 {
1526 emit_insn (gen_rtx_SET (VOIDmode, op0,
1527 gen_rtx_PLUS (DImode, temp4, temp2)));
1528 }
284d86e9 1529 }
e0d80184
DM		 1530 else
1531 {
9208e4b2
DM		 1532 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1533 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1534 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
e0d80184 1535 int to_shift = 12;
284d86e9 1536
e0d80184
DM		 1537 /* We are in the middle of reload, so this is really
1538 painful. However we do still make an attempt to
5108f3e5 1539 avoid emitting truly stupid code. */
e0d80184
DM		 1540 if (low1 != const0_rtx)
1541 {
9208e4b2 1542 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1543 gen_rtx_ASHIFT (DImode, sub_temp,
2a01c939 1544 GEN_INT (to_shift))));
9208e4b2 1545 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1546 gen_rtx_IOR (DImode, op0, low1)));
1547 sub_temp = op0;
1548 to_shift = 12;
1549 }
1550 else
1551 {
1552 to_shift += 12;
1553 }
1554 if (low2 != const0_rtx)
1555 {
9208e4b2 1556 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1557 gen_rtx_ASHIFT (DImode, sub_temp,
1558 GEN_INT (to_shift))));
9208e4b2 1559 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1560 gen_rtx_IOR (DImode, op0, low2)));
1561 sub_temp = op0;
1562 to_shift = 8;
1563 }
1564 else
1565 {
1566 to_shift += 8;
1567 }
9208e4b2 1568 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1569 gen_rtx_ASHIFT (DImode, sub_temp,
1570 GEN_INT (to_shift))));
1571 if (low3 != const0_rtx)
9208e4b2 1572 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1573 gen_rtx_IOR (DImode, op0, low3)));
80ffc95e 1574 /* phew... */
e0d80184 1575 }
284d86e9
JC		 1576}
1577
80ffc95e 1578/* Analyze a 64-bit constant for certain properties. */
e80d5f80
KG		 1579static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1580 unsigned HOST_WIDE_INT,
1581 int *, int *, int *);
2a01c939 1582
e0d80184 1583static void
fc27d102
KG		 1584analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1585 unsigned HOST_WIDE_INT low_bits,
1586 int *hbsp, int *lbsp, int *abbasp)
ab835497 1587{
e0d80184
DM		 1588 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1589 int i;
ab835497 1590
e0d80184
DM		 1591 lowest_bit_set = highest_bit_set = -1;
1592 i = 0;
1593 do
ab835497 1594 {
e0d80184
DM		 1595 if ((lowest_bit_set == -1)
1596 && ((low_bits >> i) & 1))
1597 lowest_bit_set = i;
1598 if ((highest_bit_set == -1)
1599 && ((high_bits >> (32 - i - 1)) & 1))
1600 highest_bit_set = (64 - i - 1);
1601 }
1602 while (++i < 32
1603 && ((highest_bit_set == -1)
1604 || (lowest_bit_set == -1)));
1605 if (i == 32)
1606 {
1607 i = 0;
1608 do
ab835497 1609 {
e0d80184
DM		 1610 if ((lowest_bit_set == -1)
1611 && ((high_bits >> i) & 1))
1612 lowest_bit_set = i + 32;
1613 if ((highest_bit_set == -1)
1614 && ((low_bits >> (32 - i - 1)) & 1))
1615 highest_bit_set = 32 - i - 1;
ab835497 1616 }
e0d80184
DM		 1617 while (++i < 32
1618 && ((highest_bit_set == -1)
1619 || (lowest_bit_set == -1)));
1620 }
1621 /* If there are no bits set this should have gone out
1622 as one instruction! */
f5f7d171 1623 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
e0d80184
DM		 1624 all_bits_between_are_set = 1;
1625 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1626 {
1627 if (i < 32)
1628 {
1629 if ((low_bits & (1 << i)) != 0)
1630 continue;
1631 }
1632 else
1633 {
1634 if ((high_bits & (1 << (i - 32))) != 0)
1635 continue;
1636 }
1637 all_bits_between_are_set = 0;
1638 break;
ab835497 1639 }
e0d80184
DM		 1640 *hbsp = highest_bit_set;
1641 *lbsp = lowest_bit_set;
1642 *abbasp = all_bits_between_are_set;
ab835497 1643}
6a4bb1fa 1644
e80d5f80 1645static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2a01c939 1646
e0d80184 1647static int
fc27d102
KG		 1648const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1649 unsigned HOST_WIDE_INT low_bits)
e0d80184
DM		 1650{
1651 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
284d86e9 1652
e0d80184 1653 if (high_bits == 0
f451b552 1654 || high_bits == 0xffffffff)
e0d80184 1655 return 1;
6a4bb1fa 1656
e0d80184
DM		 1657 analyze_64bit_constant (high_bits, low_bits,
1658 &highest_bit_set, &lowest_bit_set,
1659 &all_bits_between_are_set);
6a4bb1fa 1660
f710f868
DM		 1661 if ((highest_bit_set == 63
1662 || lowest_bit_set == 0)
e0d80184
DM		 1663 && all_bits_between_are_set != 0)
1664 return 1;
6a4bb1fa 1665
9208e4b2
DM		 1666 if ((highest_bit_set - lowest_bit_set) < 21)
1667 return 1;
1668
6a4bb1fa
DE		 1669 return 0;
1670}
1671
e80d5f80
KG		 1672static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1673 unsigned HOST_WIDE_INT,
1674 int, int);
2a01c939
DM		 1675
1676static unsigned HOST_WIDE_INT
fc27d102
KG		 1677create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1678 unsigned HOST_WIDE_INT low_bits,
1679 int lowest_bit_set, int shift)
ab835497 1680{
f710f868 1681 HOST_WIDE_INT hi, lo;
ab835497 1682
e0d80184
DM		 1683 if (lowest_bit_set < 32)
1684 {
1685 lo = (low_bits >> lowest_bit_set) << shift;
1686 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1687 }
1688 else
1689 {
1690 lo = 0;
1691 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1692 }
f5f7d171 1693 gcc_assert (! (hi & lo));
e0d80184
DM		 1694 return (hi | lo);
1695}
ab835497 1696
e0d80184
DM		 1697/* Here we are sure to be arch64 and this is an integer constant
1698 being loaded into a register. Emit the most efficient
1699 insn sequence possible. Detection of all the 1-insn cases
1700 has been done already. */
1701void
fc27d102 1702sparc_emit_set_const64 (rtx op0, rtx op1)
e0d80184 1703{
2a01c939 1704 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1705 int lowest_bit_set, highest_bit_set;
1706 int all_bits_between_are_set;
1d511ed5 1707 rtx temp = 0;
ab835497 1708
e0d80184 1709 /* Sanity check that we know what we are working with. */
bea5071f
EB		 1710 gcc_assert (TARGET_ARCH64
1711 && (GET_CODE (op0) == SUBREG
1712 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
380f6ad3 1713
f710f868
DM		 1714 if (reload_in_progress || reload_completed)
1715 temp = op0;
f710f868 1716
0e5d569c 1717 if (GET_CODE (op1) != CONST_INT)
e0d80184 1718 {
5f78aa30
JC		 1719 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1720 return;
e0d80184 1721 }
ab835497 1722
1d511ed5
EB		 1723 if (! temp)
1724 temp = gen_reg_rtx (DImode);
1725
0e5d569c
EB		 1726 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1727 low_bits = (INTVAL (op1) & 0xffffffff);
ab835497 1728
e0d80184
DM		 1729 /* low_bits bits 0 --> 31
1730 high_bits bits 32 --> 63 */
ab835497 1731
e0d80184
DM		 1732 analyze_64bit_constant (high_bits, low_bits,
1733 &highest_bit_set, &lowest_bit_set,
1734 &all_bits_between_are_set);
1735
1736 /* First try for a 2-insn sequence. */
1737
1738 /* These situations are preferred because the optimizer can
1739 * do more things with them:
1740 * 1) mov -1, %reg
1741 * sllx %reg, shift, %reg
1742 * 2) mov -1, %reg
1743 * srlx %reg, shift, %reg
1744 * 3) mov some_small_const, %reg
1745 * sllx %reg, shift, %reg
1746 */
1747 if (((highest_bit_set == 63
1748 || lowest_bit_set == 0)
1749 && all_bits_between_are_set != 0)
2a01c939 1750 || ((highest_bit_set - lowest_bit_set) < 12))
e0d80184 1751 {
9208e4b2 1752 HOST_WIDE_INT the_const = -1;
e0d80184
DM		 1753 int shift = lowest_bit_set;
1754
f710f868
DM		 1755 if ((highest_bit_set != 63
1756 && lowest_bit_set != 0)
1757 || all_bits_between_are_set == 0)
ab835497 1758 {
e0d80184 1759 the_const =
9208e4b2 1760 create_simple_focus_bits (high_bits, low_bits,
9208e4b2 1761 lowest_bit_set, 0);
ab835497 1762 }
e0d80184 1763 else if (lowest_bit_set == 0)
9208e4b2 1764 shift = -(63 - highest_bit_set);
e0d80184 1765
f5f7d171
JM		 1766 gcc_assert (SPARC_SIMM13_P (the_const));
1767 gcc_assert (shift != 0);
f710f868 1768
9208e4b2 1769 emit_insn (gen_safe_SET64 (temp, the_const));
e0d80184 1770 if (shift > 0)
9208e4b2 1771 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1772 op0,
1773 gen_rtx_ASHIFT (DImode,
1774 temp,
1775 GEN_INT (shift))));
1776 else if (shift < 0)
9208e4b2 1777 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1778 op0,
9208e4b2 1779 gen_rtx_LSHIFTRT (DImode,
e0d80184
DM		 1780 temp,
1781 GEN_INT (-shift))));
e0d80184
DM		 1782 return;
1783 }
ab835497 1784
e0d80184
DM		 1785 /* Now a range of 22 or less bits set somewhere.
1786 * 1) sethi %hi(focus_bits), %reg
1787 * sllx %reg, shift, %reg
1788 * 2) sethi %hi(focus_bits), %reg
1789 * srlx %reg, shift, %reg
1790 */
2a01c939 1791 if ((highest_bit_set - lowest_bit_set) < 21)
e0d80184 1792 {
2a01c939 1793 unsigned HOST_WIDE_INT focus_bits =
e0d80184 1794 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1795 lowest_bit_set, 10);
f710f868 1796
f5f7d171
JM		 1797 gcc_assert (SPARC_SETHI_P (focus_bits));
1798 gcc_assert (lowest_bit_set != 10);
f710f868 1799
9bb3323d 1800 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
e0d80184 1801
9208e4b2 1802 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
e0d80184 1803 if (lowest_bit_set < 10)
9208e4b2 1804 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1805 op0,
9208e4b2 1806 gen_rtx_LSHIFTRT (DImode, temp,
e0d80184 1807 GEN_INT (10 - lowest_bit_set))));
9208e4b2
DM		 1808 else if (lowest_bit_set > 10)
1809 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1810 op0,
1811 gen_rtx_ASHIFT (DImode, temp,
1812 GEN_INT (lowest_bit_set - 10))));
e0d80184
DM		 1813 return;
1814 }
1815
1816 /* 1) sethi %hi(low_bits), %reg
1817 * or %reg, %lo(low_bits), %reg
1818 * 2) sethi %hi(~low_bits), %reg
1819 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1820 */
1821 if (high_bits == 0
2a01c939 1822 || high_bits == 0xffffffff)
5f78aa30
JC		 1823 {
1824 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1825 (high_bits == 0xffffffff));
1826 return;
1827 }
e0d80184 1828
f710f868
DM		 1829 /* Now, try 3-insn sequences. */
1830
e0d80184
DM		 1831 /* 1) sethi %hi(high_bits), %reg
1832 * or %reg, %lo(high_bits), %reg
1833 * sllx %reg, 32, %reg
1834 */
f710f868 1835 if (low_bits == 0)
5f78aa30 1836 {
f710f868 1837 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
5f78aa30
JC		 1838 return;
1839 }
e0d80184 1840
f710f868
DM		 1841 /* We may be able to do something quick
1842 when the constant is negated, so try that. */
e0d80184
DM		 1843 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1844 (~low_bits) & 0xfffffc00))
1845 {
5108f3e5
DM		 1846 /* NOTE: The trailing bits get XOR'd so we need the
1847 non-negated bits, not the negated ones. */
1848 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
e0d80184
DM		 1849
1850 if ((((~high_bits) & 0xffffffff) == 0
1851 && ((~low_bits) & 0x80000000) == 0)
1852 || (((~high_bits) & 0xffffffff) == 0xffffffff
1853 && ((~low_bits) & 0x80000000) != 0))
ab835497 1854 {
0e5d569c 1855 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
e0d80184 1856
5108f3e5
DM		 1857 if ((SPARC_SETHI_P (fast_int)
1858 && (~high_bits & 0xffffffff) == 0)
1859 || SPARC_SIMM13_P (fast_int))
9208e4b2 1860 emit_insn (gen_safe_SET64 (temp, fast_int));
ab835497 1861 else
0e5d569c 1862 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
ab835497 1863 }
e0d80184
DM		 1864 else
1865 {
1866 rtx negated_const;
e0d80184
DM		 1867 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1868 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
e0d80184
DM		 1869 sparc_emit_set_const64 (temp, negated_const);
1870 }
5108f3e5
DM		 1871
1872 /* If we are XOR'ing with -1, then we should emit a one's complement
1873 instead. This way the combiner will notice logical operations
1874 such as ANDN later on and substitute. */
1875 if (trailing_bits == 0x3ff)
1876 {
1877 emit_insn (gen_rtx_SET (VOIDmode, op0,
1878 gen_rtx_NOT (DImode, temp)));
1879 }
1880 else
1881 {
1882 emit_insn (gen_rtx_SET (VOIDmode,
1883 op0,
1884 gen_safe_XOR64 (temp,
1885 (-0x400 | trailing_bits))));
1886 }
e0d80184 1887 return;
ab835497 1888 }
ab835497 1889
e0d80184
DM		 1890 /* 1) sethi %hi(xxx), %reg
1891 * or %reg, %lo(xxx), %reg
1892 * sllx %reg, yyy, %reg
f710f868
DM		 1893 *
1894 * ??? This is just a generalized version of the low_bits==0
1895 * thing above, FIXME...
e0d80184
DM		 1896 */
1897 if ((highest_bit_set - lowest_bit_set) < 32)
1898 {
f710f868
DM		 1899 unsigned HOST_WIDE_INT focus_bits =
1900 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1901 lowest_bit_set, 0);
ab835497 1902
e0d80184 1903 /* We can't get here in this state. */
f5f7d171 1904 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
95726648 1905
e0d80184
DM		 1906 /* So what we know is that the set bits straddle the
1907 middle of the 64-bit word. */
5f78aa30
JC		 1908 sparc_emit_set_const64_quick2 (op0, temp,
1909 focus_bits, 0,
1910 lowest_bit_set);
1911 return;
e0d80184 1912 }
c85f7c16 1913
f710f868
DM		 1914 /* 1) sethi %hi(high_bits), %reg
1915 * or %reg, %lo(high_bits), %reg
1916 * sllx %reg, 32, %reg
1917 * or %reg, low_bits, %reg
1918 */
1919 if (SPARC_SIMM13_P(low_bits)
1920 && ((int)low_bits > 0))
1921 {
1922 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1923 return;
1924 }
1925
80ffc95e 1926 /* The easiest way when all else fails, is full decomposition. */
e0d80184
DM		 1927#if 0
1928 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1929 high_bits, low_bits, ~high_bits, ~low_bits);
1930#endif
1931 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
c85f7c16 1932}
0e5d569c 1933#endif /* HOST_BITS_PER_WIDE_INT == 32 */
c85f7c16 1934
e267e177
RH		 1935/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1936 return the mode to be used for the comparison. For floating-point,
1937 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1938 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1939 processing is needed. */
1940
1941enum machine_mode
fc27d102 1942select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
e267e177
RH		 1943{
1944 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1945 {
1946 switch (op)
1947 {
1948 case EQ:
1949 case NE:
1950 case UNORDERED:
1951 case ORDERED:
1952 case UNLT:
1953 case UNLE:
1954 case UNGT:
1955 case UNGE:
1956 case UNEQ:
7913f3d0 1957 case LTGT:
e267e177
RH		 1958 return CCFPmode;
1959
1960 case LT:
1961 case LE:
1962 case GT:
1963 case GE:
1964 return CCFPEmode;
1965
1966 default:
f5f7d171 1967 gcc_unreachable ();
e267e177
RH		 1968 }
1969 }
1970 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
1971 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
1972 {
1973 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1974 return CCX_NOOVmode;
1975 else
1976 return CC_NOOVmode;
1977 }
1978 else
1979 {
1980 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1981 return CCXmode;
1982 else
1983 return CCmode;
1984 }
1985}
1986
f90b7a5a
PB		 1987/* Emit the compare insn and return the CC reg for a CODE comparison
1988 with operands X and Y. */
c85f7c16 1989
f90b7a5a
PB		 1990static rtx
1991gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
c85f7c16 1992{
65c5ae8b 1993 enum machine_mode mode;
f90b7a5a 1994 rtx cc_reg;
c85f7c16 1995
f90b7a5a
PB		 1996 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
1997 return x;
65c5ae8b 1998
65c5ae8b 1999 mode = SELECT_CC_MODE (code, x, y);
8ec11fe9 2000
e0d80184
DM		 2001 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2002 fcc regs (cse can't tell they're really call clobbered regs and will
2003 remove a duplicate comparison even if there is an intervening function
2004 call - it will then try to reload the cc reg via an int reg which is why
2005 we need the movcc patterns). It is possible to provide the movcc
2006 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2007 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2008 to tell cse that CCFPE mode registers (even pseudos) are call
2009 clobbered. */
c85f7c16 2010
e0d80184
DM		 2011 /* ??? This is an experiment. Rather than making changes to cse which may
2012 or may not be easy/clean, we do our own cse. This is possible because
2013 we will generate hard registers. Cse knows they're call clobbered (it
2014 doesn't know the same thing about pseudos). If we guess wrong, no big
2015 deal, but if we win, great! */
c85f7c16 2016
e0d80184
DM		 2017 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2018#if 1 /* experiment */
284d86e9 2019 {
e0d80184
DM		 2020 int reg;
2021 /* We cycle through the registers to ensure they're all exercised. */
2022 static int next_fcc_reg = 0;
2023 /* Previous x,y for each fcc reg. */
2024 static rtx prev_args[4][2];
284d86e9 2025
e0d80184
DM		 2026 /* Scan prev_args for x,y. */
2027 for (reg = 0; reg < 4; reg++)
2028 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2029 break;
2030 if (reg == 4)
2031 {
2032 reg = next_fcc_reg;
2033 prev_args[reg][0] = x;
2034 prev_args[reg][1] = y;
2035 next_fcc_reg = (next_fcc_reg + 1) & 3;
2036 }
2037 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
284d86e9 2038 }
e0d80184
DM		 2039#else
2040 cc_reg = gen_reg_rtx (mode);
2041#endif /* ! experiment */
2042 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2043 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2044 else
2045 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
284d86e9 2046
19047e4a
EB		 2047 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2048 will only result in an unrecognizable insn so no point in asserting. */
2049 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
c85f7c16 2050
e0d80184
DM		 2051 return cc_reg;
2052}
c85f7c16 2053
f90b7a5a
PB		 2054
2055/* Emit the compare insn and return the CC reg for the comparison in CMP. */
19047e4a
EB		 2056
2057rtx
f90b7a5a 2058gen_compare_reg (rtx cmp)
19047e4a 2059{
f90b7a5a 2060 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
19047e4a
EB		 2061}
2062
e0d80184 2063/* This function is used for v9 only.
f90b7a5a 2064 DEST is the target of the Scc insn.
e0d80184 2065 CODE is the code for an Scc's comparison.
f90b7a5a 2066 X and Y are the values we compare.
c85f7c16 2067
e0d80184 2068 This function is needed to turn
ab835497 2069
e0d80184
DM		 2070 (set (reg:SI 110)
2071 (gt (reg:CCX 100 %icc)
2072 (const_int 0)))
2073 into
2074 (set (reg:SI 110)
2075 (gt:DI (reg:CCX 100 %icc)
2076 (const_int 0)))
2077
2078 IE: The instruction recognizer needs to see the mode of the comparison to
2079 find the right instruction. We could use "gt:DI" right in the
f90b7a5a 2080 define_expand, but leaving it out allows us to handle DI, SI, etc. */
ab835497 2081
f90b7a5a
PB		 2082static int
2083gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
ab835497 2084{
e0d80184 2085 if (! TARGET_ARCH64
f90b7a5a
PB		 2086 && (GET_MODE (x) == DImode
2087 || GET_MODE (dest) == DImode))
e0d80184 2088 return 0;
7e2feebf 2089
e0d80184
DM		 2090 /* Try to use the movrCC insns. */
2091 if (TARGET_ARCH64
f90b7a5a
PB		 2092 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2093 && y == const0_rtx
e0d80184 2094 && v9_regcmp_p (compare_code))
ab835497 2095 {
f90b7a5a 2096 rtx op0 = x;
7e04157d
DM		 2097 rtx temp;
2098
e0d80184 2099 /* Special case for op0 != 0. This can be done with one instruction if
f90b7a5a 2100 dest == x. */
e0d80184
DM		 2101
2102 if (compare_code == NE
f90b7a5a
PB		 2103 && GET_MODE (dest) == DImode
2104 && rtx_equal_p (op0, dest))
ab835497 2105 {
f90b7a5a 2106 emit_insn (gen_rtx_SET (VOIDmode, dest,
e0d80184
DM		 2107 gen_rtx_IF_THEN_ELSE (DImode,
2108 gen_rtx_fmt_ee (compare_code, DImode,
2109 op0, const0_rtx),
2110 const1_rtx,
f90b7a5a 2111 dest)));
ab835497
RK		 2112 return 1;
2113 }
e0d80184 2114
f90b7a5a 2115 if (reg_overlap_mentioned_p (dest, op0))
a42519be 2116 {
f90b7a5a 2117 /* Handle the case where dest == x.
a42519be 2118 We "early clobber" the result. */
f90b7a5a
PB		 2119 op0 = gen_reg_rtx (GET_MODE (x));
2120 emit_move_insn (op0, x);
a42519be
JJ		 2121 }
2122
f90b7a5a 2123 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
e0d80184 2124 if (GET_MODE (op0) != DImode)
ab835497 2125 {
e0d80184
DM		 2126 temp = gen_reg_rtx (DImode);
2127 convert_move (temp, op0, 0);
ab835497 2128 }
e0d80184
DM		 2129 else
2130 temp = op0;
f90b7a5a
PB		 2131 emit_insn (gen_rtx_SET (VOIDmode, dest,
2132 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
e0d80184
DM		 2133 gen_rtx_fmt_ee (compare_code, DImode,
2134 temp, const0_rtx),
2135 const1_rtx,
f90b7a5a 2136 dest)));
95726648
DE		 2137 return 1;
2138 }
e0d80184 2139 else
ab835497 2140 {
f90b7a5a
PB		 2141 x = gen_compare_reg_1 (compare_code, x, y);
2142 y = const0_rtx;
ab835497 2143
f90b7a5a
PB		 2144 gcc_assert (GET_MODE (x) != CC_NOOVmode
2145 && GET_MODE (x) != CCX_NOOVmode);
2146
2147 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2148 emit_insn (gen_rtx_SET (VOIDmode, dest,
2149 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
e0d80184 2150 gen_rtx_fmt_ee (compare_code,
f90b7a5a
PB		 2151 GET_MODE (x), x, y),
2152 const1_rtx, dest)));
e0d80184 2153 return 1;
ab835497 2154 }
ab835497 2155}
4fb4e4b8 2156
f90b7a5a
PB		 2157
2158/* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2159 without jumps using the addx/subx instructions. */
2160
2161bool
2162emit_scc_insn (rtx operands[])
2163{
2164 rtx tem;
2165 rtx x;
2166 rtx y;
2167 enum rtx_code code;
2168
2169 /* The quad-word fp compare library routines all return nonzero to indicate
2170 true, which is different from the equivalent libgcc routines, so we must
2171 handle them specially here. */
2172 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2173 {
2174 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2175 GET_CODE (operands[1]));
2176 operands[2] = XEXP (operands[1], 0);
2177 operands[3] = XEXP (operands[1], 1);
2178 }
2179
2180 code = GET_CODE (operands[1]);
2181 x = operands[2];
2182 y = operands[3];
2183
2184 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2185 more applications). The exception to this is "reg != 0" which can
2186 be done in one instruction on v9 (so we do it). */
2187 if (code == EQ)
2188 {
2189 if (GET_MODE (x) == SImode)
2190 {
2191 rtx pat = gen_seqsi_special (operands[0], x, y);
2192 emit_insn (pat);
2193 return true;
2194 }
2195 else if (GET_MODE (x) == DImode)
2196 {
2197 rtx pat = gen_seqdi_special (operands[0], x, y);
2198 emit_insn (pat);
2199 return true;
2200 }
2201 }
2202
2203 if (code == NE)
2204 {
2205 if (GET_MODE (x) == SImode)
2206 {
2207 rtx pat = gen_snesi_special (operands[0], x, y);
2208 emit_insn (pat);
2209 return true;
2210 }
2211 else if (GET_MODE (x) == DImode)
2212 {
2213 rtx pat = gen_snedi_special (operands[0], x, y);
2214 emit_insn (pat);
2215 return true;
2216 }
2217 }
2218
2219 /* For the rest, on v9 we can use conditional moves. */
2220
2221 if (TARGET_V9)
2222 {
2223 if (gen_v9_scc (operands[0], code, x, y))
2224 return true;
2225 }
2226
2227 /* We can do LTU and GEU using the addx/subx instructions too. And
2228 for GTU/LEU, if both operands are registers swap them and fall
2229 back to the easy case. */
2230 if (code == GTU || code == LEU)
2231 {
2232 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2233 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2234 {
2235 tem = x;
2236 x = y;
2237 y = tem;
2238 code = swap_condition (code);
2239 }
2240 }
2241
2242 if (code == LTU || code == GEU)
2243 {
2244 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4900aa61 2245 gen_rtx_fmt_ee (code, SImode,
f90b7a5a
PB		 2246 gen_compare_reg_1 (code, x, y),
2247 const0_rtx)));
2248 return true;
2249 }
2250
2251 /* Nope, do branches. */
2252 return false;
2253}
2254
e0d80184
DM		 2255/* Emit a conditional jump insn for the v9 architecture using comparison code
2256 CODE and jump target LABEL.
2257 This function exists to take advantage of the v9 brxx insns. */
ab835497 2258
f90b7a5a 2259static void
fc27d102 2260emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
ab835497 2261{
e0d80184
DM		 2262 emit_jump_insn (gen_rtx_SET (VOIDmode,
2263 pc_rtx,
2264 gen_rtx_IF_THEN_ELSE (VOIDmode,
2265 gen_rtx_fmt_ee (code, GET_MODE (op0),
2266 op0, const0_rtx),
2267 gen_rtx_LABEL_REF (VOIDmode, label),
2268 pc_rtx)));
2269}
7b1ac798 2270
f90b7a5a
PB		 2271void
2272emit_conditional_branch_insn (rtx operands[])
2273{
2274 /* The quad-word fp compare library routines all return nonzero to indicate
2275 true, which is different from the equivalent libgcc routines, so we must
2276 handle them specially here. */
2277 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2278 {
2279 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2280 GET_CODE (operands[0]));
2281 operands[1] = XEXP (operands[0], 0);
2282 operands[2] = XEXP (operands[0], 1);
2283 }
2284
2285 if (TARGET_ARCH64 && operands[2] == const0_rtx
2286 && GET_CODE (operands[1]) == REG
2287 && GET_MODE (operands[1]) == DImode)
2288 {
2289 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2290 return;
2291 }
2292
2293 operands[1] = gen_compare_reg (operands[0]);
2294 operands[2] = const0_rtx;
2295 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2296 operands[1], operands[2]);
2297 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2298 operands[3]));
2299}
2300
2301
7b1ac798
JJ		 2302/* Generate a DFmode part of a hard TFmode register.
2303 REG is the TFmode hard register, LOW is 1 for the
2304 low 64bit of the register and 0 otherwise.
2305 */
2306rtx
fc27d102 2307gen_df_reg (rtx reg, int low)
7b1ac798
JJ		 2308{
2309 int regno = REGNO (reg);
2310
2311 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2aac41d6 2312 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
7b1ac798
JJ		 2313 return gen_rtx_REG (DFmode, regno);
2314}
e0d80184 2315\f
73985940
RH		 2316/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2317 Unlike normal calls, TFmode operands are passed by reference. It is
2318 assumed that no more than 3 operands are required. */
2319
2320static void
fc27d102 2321emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
73985940
RH		 2322{
2323 rtx ret_slot = NULL, arg[3], func_sym;
4e7d5d27 2324 int i;
73985940
RH		 2325
2326 /* We only expect to be called for conversions, unary, and binary ops. */
f5f7d171 2327 gcc_assert (nargs == 2 || nargs == 3);
73985940
RH		 2328
2329 for (i = 0; i < nargs; ++i)
2330 {
2331 rtx this_arg = operands[i];
2332 rtx this_slot;
2333
2334 /* TFmode arguments and return values are passed by reference. */
2335 if (GET_MODE (this_arg) == TFmode)
2336 {
4e7d5d27
DM		 2337 int force_stack_temp;
2338
2339 force_stack_temp = 0;
2340 if (TARGET_BUGGY_QP_LIB && i == 0)
2341 force_stack_temp = 1;
2342
2343 if (GET_CODE (this_arg) == MEM
2344 && ! force_stack_temp)
2345 this_arg = XEXP (this_arg, 0);
2346 else if (CONSTANT_P (this_arg)
2347 && ! force_stack_temp)
73985940
RH		 2348 {
2349 this_slot = force_const_mem (TFmode, this_arg);
2350 this_arg = XEXP (this_slot, 0);
2351 }
2352 else
2353 {
2354 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2355
2356 /* Operand 0 is the return value. We'll copy it out later. */
2357 if (i > 0)
2358 emit_move_insn (this_slot, this_arg);
2359 else
2360 ret_slot = this_slot;
2361
2362 this_arg = XEXP (this_slot, 0);
2363 }
2364 }
2365
2366 arg[i] = this_arg;
2367 }
2368
2369 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2370
2371 if (GET_MODE (operands[0]) == TFmode)
2372 {
2373 if (nargs == 2)
2374 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2375 arg[0], GET_MODE (arg[0]),
2376 arg[1], GET_MODE (arg[1]));
2377 else
2378 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2379 arg[0], GET_MODE (arg[0]),
2380 arg[1], GET_MODE (arg[1]),
2381 arg[2], GET_MODE (arg[2]));
2382
2383 if (ret_slot)
2384 emit_move_insn (operands[0], ret_slot);
2385 }
2386 else
2387 {
2388 rtx ret;
2389
f5f7d171 2390 gcc_assert (nargs == 2);
73985940
RH		 2391
2392 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2393 GET_MODE (operands[0]), 1,
2394 arg[1], GET_MODE (arg[1]));
2395
2396 if (ret != operands[0])
2397 emit_move_insn (operands[0], ret);
2398 }
2399}
2400
2401/* Expand soft-float TFmode calls to sparc abi routines. */
2402
2403static void
fc27d102 2404emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
73985940
RH		 2405{
2406 const char *func;
2407
2408 switch (code)
2409 {
2410 case PLUS:
2411 func = "_Qp_add";
2412 break;
2413 case MINUS:
2414 func = "_Qp_sub";
2415 break;
2416 case MULT:
2417 func = "_Qp_mul";
2418 break;
2419 case DIV:
2420 func = "_Qp_div";
2421 break;
2422 default:
f5f7d171 2423 gcc_unreachable ();
73985940
RH		 2424 }
2425
2426 emit_soft_tfmode_libcall (func, 3, operands);
2427}
2428
2429static void
fc27d102 2430emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
73985940
RH		 2431{
2432 const char *func;
2433
f5f7d171
JM		 2434 gcc_assert (code == SQRT);
2435 func = "_Qp_sqrt";
73985940
RH		 2436
2437 emit_soft_tfmode_libcall (func, 2, operands);
2438}
2439
2440static void
fc27d102 2441emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
73985940
RH		 2442{
2443 const char *func;
2444
2445 switch (code)
2446 {
2447 case FLOAT_EXTEND:
2448 switch (GET_MODE (operands[1]))
2449 {
2450 case SFmode:
2451 func = "_Qp_stoq";
2452 break;
2453 case DFmode:
2454 func = "_Qp_dtoq";
2455 break;
2456 default:
f5f7d171 2457 gcc_unreachable ();
73985940
RH		 2458 }
2459 break;
2460
2461 case FLOAT_TRUNCATE:
2462 switch (GET_MODE (operands[0]))
2463 {
2464 case SFmode:
2465 func = "_Qp_qtos";
2466 break;
2467 case DFmode:
2468 func = "_Qp_qtod";
2469 break;
2470 default:
f5f7d171 2471 gcc_unreachable ();
73985940
RH		 2472 }
2473 break;
2474
2475 case FLOAT:
2476 switch (GET_MODE (operands[1]))
2477 {
2478 case SImode:
2479 func = "_Qp_itoq";
92693034
JM		 2480 if (TARGET_ARCH64)
2481 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
73985940
RH		 2482 break;
2483 case DImode:
2484 func = "_Qp_xtoq";
2485 break;
2486 default:
f5f7d171 2487 gcc_unreachable ();
73985940
RH		 2488 }
2489 break;
2490
2491 case UNSIGNED_FLOAT:
2492 switch (GET_MODE (operands[1]))
2493 {
2494 case SImode:
2495 func = "_Qp_uitoq";
92693034
JM		 2496 if (TARGET_ARCH64)
2497 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
73985940
RH		 2498 break;
2499 case DImode:
2500 func = "_Qp_uxtoq";
2501 break;
2502 default:
f5f7d171 2503 gcc_unreachable ();
73985940
RH		 2504 }
2505 break;
2506
2507 case FIX:
2508 switch (GET_MODE (operands[0]))
2509 {
2510 case SImode:
2511 func = "_Qp_qtoi";
2512 break;
2513 case DImode:
2514 func = "_Qp_qtox";
2515 break;
2516 default:
f5f7d171 2517 gcc_unreachable ();
73985940
RH		 2518 }
2519 break;
2520
2521 case UNSIGNED_FIX:
2522 switch (GET_MODE (operands[0]))
2523 {
2524 case SImode:
2525 func = "_Qp_qtoui";
2526 break;
2527 case DImode:
2528 func = "_Qp_qtoux";
2529 break;
2530 default:
f5f7d171 2531 gcc_unreachable ();
73985940
RH		 2532 }
2533 break;
2534
2535 default:
f5f7d171 2536 gcc_unreachable ();
73985940
RH		 2537 }
2538
2539 emit_soft_tfmode_libcall (func, 2, operands);
2540}
2541
2542/* Expand a hard-float tfmode operation. All arguments must be in
2543 registers. */
2544
2545static void
fc27d102 2546emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
73985940
RH		 2547{
2548 rtx op, dest;
2549
ec8e098d 2550 if (GET_RTX_CLASS (code) == RTX_UNARY)
73985940
RH		 2551 {
2552 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2553 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2554 }
2555 else
2556 {
2557 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2558 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2559 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2560 operands[1], operands[2]);
2561 }
2562
2563 if (register_operand (operands[0], VOIDmode))
2564 dest = operands[0];
2565 else
2566 dest = gen_reg_rtx (GET_MODE (operands[0]));
2567
2568 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2569
2570 if (dest != operands[0])
2571 emit_move_insn (operands[0], dest);
2572}
2573
2574void
fc27d102 2575emit_tfmode_binop (enum rtx_code code, rtx *operands)
73985940
RH		 2576{
2577 if (TARGET_HARD_QUAD)
2578 emit_hard_tfmode_operation (code, operands);
2579 else
2580 emit_soft_tfmode_binop (code, operands);
2581}
2582
2583void
fc27d102 2584emit_tfmode_unop (enum rtx_code code, rtx *operands)
73985940
RH		 2585{
2586 if (TARGET_HARD_QUAD)
2587 emit_hard_tfmode_operation (code, operands);
2588 else
2589 emit_soft_tfmode_unop (code, operands);
2590}
2591
2592void
fc27d102 2593emit_tfmode_cvt (enum rtx_code code, rtx *operands)
73985940
RH		 2594{
2595 if (TARGET_HARD_QUAD)
2596 emit_hard_tfmode_operation (code, operands);
2597 else
2598 emit_soft_tfmode_cvt (code, operands);
2599}
2600\f
f17f9332
JJ		 2601/* Return nonzero if a branch/jump/call instruction will be emitting
2602 nop into its delay slot. */
2603
2604int
fc27d102 2605empty_delay_slot (rtx insn)
f17f9332
JJ		 2606{
2607 rtx seq;
2608
2609 /* If no previous instruction (should not happen), return true. */
2610 if (PREV_INSN (insn) == NULL)
2611 return 1;
2612
2613 seq = NEXT_INSN (PREV_INSN (insn));
2614 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2615 return 0;
2616
2617 return 1;
2618}
2619
9ac617d4 2620/* Return nonzero if TRIAL can go into the call delay slot. */
ab835497 2621
e0d80184 2622int
9ac617d4 2623tls_call_delay (rtx trial)
e0d80184 2624{
e10fbf96 2625 rtx pat;
1150a841 2626
9ac617d4 2627 /* Binutils allows
e10fbf96
EB		 2628 call __tls_get_addr, %tgd_call (foo)
2629 add %l7, %o0, %o0, %tgd_add (foo)
9ac617d4
EB		 2630 while Sun as/ld does not. */
2631 if (TARGET_GNU_TLS || !TARGET_TLS)
2632 return 1;
4fb4e4b8 2633
e0d80184 2634 pat = PATTERN (trial);
795068a4 2635
e10fbf96
EB		 2636 /* We must reject tgd_add{32|64}, i.e.
2637 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2638 and tldm_add{32|64}, i.e.
2639 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2640 for Sun as/ld. */
2641 if (GET_CODE (pat) == SET
2642 && GET_CODE (SET_SRC (pat)) == PLUS)
2643 {
2644 rtx unspec = XEXP (SET_SRC (pat), 1);
795068a4 2645
e10fbf96
EB		 2646 if (GET_CODE (unspec) == UNSPEC
2647 && (XINT (unspec, 1) == UNSPEC_TLSGD
2648 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2649 return 0;
2650 }
2651
2652 return 1;
9ac617d4
EB		 2653}
2654
2655/* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2656 instruction. RETURN_P is true if the v9 variant 'return' is to be
2657 considered in the test too.
c137830f 2658
9ac617d4
EB		 2659 TRIAL must be a SET whose destination is a REG appropriate for the
2660 'restore' instruction or, if RETURN_P is true, for the 'return'
2661 instruction. */
795068a4 2662
9ac617d4
EB		 2663static int
2664eligible_for_restore_insn (rtx trial, bool return_p)
2665{
2666 rtx pat = PATTERN (trial);
2667 rtx src = SET_SRC (pat);
795068a4 2668
9ac617d4 2669 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3ec6f1a9
RK		 2670 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2671 && arith_operand (src, GET_MODE (src)))
3c6088d2
JJ		 2672 {
2673 if (TARGET_ARCH64)
2674 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2675 else
2676 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2677 }
e48addee 2678
9ac617d4 2679 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3ec6f1a9
RK		 2680 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2681 && arith_double_operand (src, GET_MODE (src)))
e0d80184 2682 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
795068a4 2683
9ac617d4
EB		 2684 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2685 else if (! TARGET_FPU && register_operand (src, SFmode))
2686 return 1;
2687
2688 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2689 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
e0d80184 2690 return 1;
f5da225e 2691
9ac617d4 2692 /* If we have the 'return' instruction, anything that does not use
e48addee 2693 local or output registers and can go into a delay slot wins. */
9ac617d4
EB		 2694 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
2695 && (get_attr_in_uncond_branch_delay (trial)
2696 == IN_UNCOND_BRANCH_DELAY_TRUE))
e48addee
JJ		 2697 return 1;
2698
9ac617d4 2699 /* The 'restore src1,src2,dest' pattern for SImode. */
e0d80184 2700 else if (GET_CODE (src) == PLUS
9ac617d4
EB		 2701 && register_operand (XEXP (src, 0), SImode)
2702 && arith_operand (XEXP (src, 1), SImode))
e0d80184
DM		 2703 return 1;
2704
9ac617d4 2705 /* The 'restore src1,src2,dest' pattern for DImode. */
e0d80184 2706 else if (GET_CODE (src) == PLUS
9ac617d4
EB		 2707 && register_operand (XEXP (src, 0), DImode)
2708 && arith_double_operand (XEXP (src, 1), DImode))
795068a4 2709 return 1;
795068a4 2710
9ac617d4 2711 /* The 'restore src1,%lo(src2),dest' pattern. */
e48addee
JJ		 2712 else if (GET_CODE (src) == LO_SUM
2713 && ! TARGET_CM_MEDMID
2714 && ((register_operand (XEXP (src, 0), SImode)
2715 && immediate_operand (XEXP (src, 1), SImode))
2716 || (TARGET_ARCH64
2717 && register_operand (XEXP (src, 0), DImode)
2718 && immediate_operand (XEXP (src, 1), DImode))))
2719 return 1;
2720
9ac617d4 2721 /* The 'restore src,src,dest' pattern. */
e48addee
JJ		 2722 else if (GET_CODE (src) == ASHIFT
2723 && (register_operand (XEXP (src, 0), SImode)
2724 || register_operand (XEXP (src, 0), DImode))
2725 && XEXP (src, 1) == const1_rtx)
2726 return 1;
2727
795068a4
JW		 2728 return 0;
2729}
2730
9ac617d4
EB		 2731/* Return nonzero if TRIAL can go into the function return's
2732 delay slot. */
2733
5751a10b 2734int
9ac617d4 2735eligible_for_return_delay (rtx trial)
5751a10b 2736{
9ac617d4 2737 rtx pat;
5751a10b 2738
9ac617d4
EB		 2739 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2740 return 0;
2741
2742 if (get_attr_length (trial) != 1)
2743 return 0;
2744
2745 /* If there are any call-saved registers, we should scan TRIAL if it
2746 does not reference them. For now just make it easy. */
2747 if (num_gfregs)
2748 return 0;
2749
2750 /* If the function uses __builtin_eh_return, the eh_return machinery
2751 occupies the delay slot. */
e3b5732b 2752 if (crtl->calls_eh_return)
9ac617d4
EB		 2753 return 0;
2754
2755 /* In the case of a true leaf function, anything can go into the slot. */
5be9b7a1 2756 if (sparc_leaf_function_p)
9ac617d4
EB		 2757 return get_attr_in_uncond_branch_delay (trial)
2758 == IN_UNCOND_BRANCH_DELAY_TRUE;
5751a10b
JJ		 2759
2760 pat = PATTERN (trial);
5751a10b 2761
9ac617d4
EB		 2762 /* Otherwise, only operations which can be done in tandem with
2763 a `restore' or `return' insn can go into the delay slot. */
2764 if (GET_CODE (SET_DEST (pat)) != REG
2765 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2766 return 0;
5751a10b 2767
9ac617d4
EB		 2768 /* If this instruction sets up floating point register and we have a return
2769 instruction, it can probably go in. But restore will not work
2770 with FP_REGS. */
2771 if (REGNO (SET_DEST (pat)) >= 32)
2772 return (TARGET_V9
2773 && ! epilogue_renumber (&pat, 1)
2774 && (get_attr_in_uncond_branch_delay (trial)
2775 == IN_UNCOND_BRANCH_DELAY_TRUE));
2776
2777 return eligible_for_restore_insn (trial, true);
5751a10b
JJ		 2778}
2779
9ac617d4 2780/* Return nonzero if TRIAL can go into the sibling call's
7d167afd
JJ		 2781 delay slot. */
2782
2783int
fc27d102 2784eligible_for_sibcall_delay (rtx trial)
7d167afd 2785{
9ac617d4 2786 rtx pat;
7d167afd
JJ		 2787
2788 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2789 return 0;
2790
8456b95a 2791 if (get_attr_length (trial) != 1)
7d167afd
JJ		 2792 return 0;
2793
2794 pat = PATTERN (trial);
2795
5be9b7a1 2796 if (sparc_leaf_function_p)
7d167afd
JJ		 2797 {
2798 /* If the tail call is done using the call instruction,
2799 we have to restore %o7 in the delay slot. */
6244b14e 2800 if (LEAF_SIBCALL_SLOT_RESERVED_P)
7d167afd
JJ		 2801 return 0;
2802
2803 /* %g1 is used to build the function address */
2804 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2805 return 0;
2806
2807 return 1;
2808 }
2809
2810 /* Otherwise, only operations which can be done in tandem with
2811 a `restore' insn can go into the delay slot. */
2812 if (GET_CODE (SET_DEST (pat)) != REG
9ac617d4 2813 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
7d167afd
JJ		 2814 || REGNO (SET_DEST (pat)) >= 32)
2815 return 0;
2816
2817 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2818 in most cases. */
2819 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2820 return 0;
2821
9ac617d4 2822 return eligible_for_restore_insn (trial, false);
e0d80184 2823}
ab835497 2824
e0d80184 2825int
fc27d102 2826short_branch (int uid1, int uid2)
e0d80184 2827{
9d98a694 2828 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
77b91512
RK		 2829
2830 /* Leave a few words of "slop". */
2831 if (delta >= -1023 && delta <= 1022)
e0d80184 2832 return 1;
77b91512 2833
e0d80184
DM		 2834 return 0;
2835}
ab835497 2836
5e7a8ee0 2837/* Return nonzero if REG is not used after INSN.
e0d80184
DM		 2838 We assume REG is a reload reg, and therefore does
2839 not live past labels or calls or jumps. */
2840int
fc27d102 2841reg_unused_after (rtx reg, rtx insn)
e0d80184
DM		 2842{
2843 enum rtx_code code, prev_code = UNKNOWN;
ab835497 2844
e0d80184 2845 while ((insn = NEXT_INSN (insn)))
61a55e8b 2846 {
e0d80184
DM		 2847 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2848 return 1;
ab835497 2849
e0d80184
DM		 2850 code = GET_CODE (insn);
2851 if (GET_CODE (insn) == CODE_LABEL)
2852 return 1;
bc961ed7 2853
ec8e098d 2854 if (INSN_P (insn))
61a55e8b 2855 {
e0d80184
DM		 2856 rtx set = single_set (insn);
2857 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2858 if (set && in_src)
2859 return 0;
2860 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2861 return 1;
2862 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2863 return 0;
61a55e8b 2864 }
e0d80184 2865 prev_code = code;
61a55e8b 2866 }
e0d80184
DM		 2867 return 1;
2868}
2869\f
5751a10b
JJ		 2870/* Determine if it's legal to put X into the constant pool. This
2871 is not possible if X contains the address of a symbol that is
2872 not constant (TLS) or not known at final link time (PIC). */
2873
2874static bool
2875sparc_cannot_force_const_mem (rtx x)
2876{
2877 switch (GET_CODE (x))
2878 {
2879 case CONST_INT:
2880 case CONST_DOUBLE:
c75d6010 2881 case CONST_VECTOR:
5751a10b
JJ		 2882 /* Accept all non-symbolic constants. */
2883 return false;
2884
2885 case LABEL_REF:
2886 /* Labels are OK iff we are non-PIC. */
2887 return flag_pic != 0;
2888
2889 case SYMBOL_REF:
2890 /* 'Naked' TLS symbol references are never OK,
2891 non-TLS symbols are OK iff we are non-PIC. */
2892 if (SYMBOL_REF_TLS_MODEL (x))
2893 return true;
2894 else
2895 return flag_pic != 0;
2896
2897 case CONST:
2898 return sparc_cannot_force_const_mem (XEXP (x, 0));
2899 case PLUS:
2900 case MINUS:
2901 return sparc_cannot_force_const_mem (XEXP (x, 0))
2902 || sparc_cannot_force_const_mem (XEXP (x, 1));
2903 case UNSPEC:
2904 return true;
2905 default:
f5f7d171 2906 gcc_unreachable ();
5751a10b
JJ		 2907 }
2908}
2909\f
5e77eb53 2910/* PIC support. */
9fd52c6c 2911static GTY(()) bool pic_helper_needed = false;
5e77eb53 2912static GTY(()) rtx pic_helper_symbol;
e2500fed 2913static GTY(()) rtx global_offset_table;
bc961ed7 2914
e0d80184 2915/* Ensure that we are not using patterns that are not OK with PIC. */
795068a4 2916
e0d80184 2917int
fc27d102 2918check_pic (int i)
e0d80184
DM		 2919{
2920 switch (flag_pic)
ab835497 2921 {
e0d80184 2922 case 1:
f5f7d171
JM		 2923 gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
2924 && (GET_CODE (recog_data.operand[i]) != CONST
2925 || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2926 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2927 == global_offset_table)
2928 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2929 == CONST))));
e0d80184
DM		 2930 case 2:
2931 default:
2932 return 1;
ab835497 2933 }
ab835497 2934}
795068a4 2935
4900aa61 2936/* Return true if X is an address which needs a temporary register when
e0d80184 2937 reloaded while generating PIC code. */
795068a4 2938
e0d80184 2939int
fc27d102 2940pic_address_needs_scratch (rtx x)
795068a4 2941{
e0d80184
DM		 2942 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2943 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2944 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2945 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2946 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2947 return 1;
795068a4 2948
e0d80184
DM		 2949 return 0;
2950}
795068a4 2951
5751a10b
JJ		 2952/* Determine if a given RTX is a valid constant. We already know this
2953 satisfies CONSTANT_P. */
2954
2955bool
2956legitimate_constant_p (rtx x)
2957{
5751a10b
JJ		 2958 switch (GET_CODE (x))
2959 {
5751a10b 2960 case CONST:
208384fd
EB		 2961 case SYMBOL_REF:
2962 if (sparc_tls_referenced_p (x))
5751a10b
JJ		 2963 return false;
2964 break;
2965
2966 case CONST_DOUBLE:
2967 if (GET_MODE (x) == VOIDmode)
2968 return true;
2969
2970 /* Floating point constants are generally not ok.
2971 The only exception is 0.0 in VIS. */
2972 if (TARGET_VIS
bea5071f
EB		 2973 && SCALAR_FLOAT_MODE_P (GET_MODE (x))
2974 && const_zero_operand (x, GET_MODE (x)))
2975 return true;
2976
2977 return false;
2978
2979 case CONST_VECTOR:
2980 /* Vector constants are generally not ok.
2981 The only exception is 0 in VIS. */
2982 if (TARGET_VIS
0e5d569c 2983 && const_zero_operand (x, GET_MODE (x)))
5751a10b
JJ		 2984 return true;
2985
2986 return false;
2987
2988 default:
2989 break;
2990 }
2991
2992 return true;
2993}
2994
2995/* Determine if a given RTX is a valid constant address. */
2996
2997bool
2998constant_address_p (rtx x)
2999{
3000 switch (GET_CODE (x))
3001 {
3002 case LABEL_REF:
3003 case CONST_INT:
3004 case HIGH:
3005 return true;
3006
3007 case CONST:
3008 if (flag_pic && pic_address_needs_scratch (x))
3009 return false;
3010 return legitimate_constant_p (x);
3011
3012 case SYMBOL_REF:
3013 return !flag_pic && legitimate_constant_p (x);
3014
3015 default:
3016 return false;
3017 }
3018}
3019
3020/* Nonzero if the constant value X is a legitimate general operand
3021 when generating PIC code. It is given that flag_pic is on and
3022 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3023
3024bool
3025legitimate_pic_operand_p (rtx x)
3026{
3027 if (pic_address_needs_scratch (x))
3028 return false;
208384fd 3029 if (sparc_tls_referenced_p (x))
5751a10b
JJ		 3030 return false;
3031 return true;
3032}
3033
3034/* Return nonzero if ADDR is a valid memory address.
3035 STRICT specifies whether strict register checking applies. */
4900aa61 3036
c6c3dba9
PB		 3037static bool
3038sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
5751a10b 3039{
f1b259d5 3040 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
5751a10b
JJ		 3041
3042 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3043 rs1 = addr;
3044 else if (GET_CODE (addr) == PLUS)
3045 {
3046 rs1 = XEXP (addr, 0);
3047 rs2 = XEXP (addr, 1);
3048
3049 /* Canonicalize. REG comes first, if there are no regs,
3050 LO_SUM comes first. */
3051 if (!REG_P (rs1)
3052 && GET_CODE (rs1) != SUBREG
3053 && (REG_P (rs2)
3054 || GET_CODE (rs2) == SUBREG
3055 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3056 {
3057 rs1 = XEXP (addr, 1);
3058 rs2 = XEXP (addr, 0);
3059 }
3060
3061 if ((flag_pic == 1
3062 && rs1 == pic_offset_table_rtx
3063 && !REG_P (rs2)
3064 && GET_CODE (rs2) != SUBREG
3065 && GET_CODE (rs2) != LO_SUM
3066 && GET_CODE (rs2) != MEM
208384fd 3067 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
5751a10b
JJ		 3068 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3069 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3070 || ((REG_P (rs1)
3071 || GET_CODE (rs1) == SUBREG)
3072 && RTX_OK_FOR_OFFSET_P (rs2)))
3073 {
3074 imm1 = rs2;
3075 rs2 = NULL;
3076 }
3077 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3078 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3079 {
39ba2f92
EB		 3080 /* We prohibit REG + REG for TFmode when there are no quad move insns
3081 and we consequently need to split. We do this because REG+REG
3082 is not an offsettable address. If we get the situation in reload
5751a10b
JJ		 3083 where source and destination of a movtf pattern are both MEMs with
3084 REG+REG address, then only one of them gets converted to an
39ba2f92 3085 offsettable address. */
5751a10b 3086 if (mode == TFmode
39ba2f92 3087 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
5751a10b
JJ		 3088 return 0;
3089
3090 /* We prohibit REG + REG on ARCH32 if not optimizing for
3091 DFmode/DImode because then mem_min_alignment is likely to be zero
3092 after reload and the forced split would lack a matching splitter
3093 pattern. */
3094 if (TARGET_ARCH32 && !optimize
3095 && (mode == DFmode || mode == DImode))
3096 return 0;
3097 }
3098 else if (USE_AS_OFFSETABLE_LO10
3099 && GET_CODE (rs1) == LO_SUM
3100 && TARGET_ARCH64
3101 && ! TARGET_CM_MEDMID
3102 && RTX_OK_FOR_OLO10_P (rs2))
3103 {
5751a10b
JJ		 3104 rs2 = NULL;
3105 imm1 = XEXP (rs1, 1);
3106 rs1 = XEXP (rs1, 0);
208384fd
EB		 3107 if (!CONSTANT_P (imm1)
3108 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
5751a10b
JJ		 3109 return 0;
3110 }
3111 }
3112 else if (GET_CODE (addr) == LO_SUM)
3113 {
3114 rs1 = XEXP (addr, 0);
3115 imm1 = XEXP (addr, 1);
3116
208384fd
EB		 3117 if (!CONSTANT_P (imm1)
3118 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
5751a10b
JJ		 3119 return 0;
3120
f1b259d5
EB		 3121 /* We can't allow TFmode in 32-bit mode, because an offset greater
3122 than the alignment (8) may cause the LO_SUM to overflow. */
d24088cc 3123 if (mode == TFmode && TARGET_ARCH32)
f1b259d5 3124 return 0;
5751a10b
JJ		 3125 }
3126 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3127 return 1;
3128 else
3129 return 0;
3130
3131 if (GET_CODE (rs1) == SUBREG)
3132 rs1 = SUBREG_REG (rs1);
3133 if (!REG_P (rs1))
3134 return 0;
3135
3136 if (rs2)
3137 {
3138 if (GET_CODE (rs2) == SUBREG)
3139 rs2 = SUBREG_REG (rs2);
3140 if (!REG_P (rs2))
3141 return 0;
3142 }
3143
3144 if (strict)
3145 {
3146 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3147 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3148 return 0;
3149 }
3150 else
3151 {
3152 if ((REGNO (rs1) >= 32
3153 && REGNO (rs1) != FRAME_POINTER_REGNUM
3154 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3155 || (rs2
3156 && (REGNO (rs2) >= 32
3157 && REGNO (rs2) != FRAME_POINTER_REGNUM
3158 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3159 return 0;
3160 }
3161 return 1;
3162}
3163
3164/* Construct the SYMBOL_REF for the tls_get_offset function. */
3165
3166static GTY(()) rtx sparc_tls_symbol;
38fc66ba 3167
5751a10b
JJ		 3168static rtx
3169sparc_tls_get_addr (void)
3170{
3171 if (!sparc_tls_symbol)
3172 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3173
3174 return sparc_tls_symbol;
3175}
3176
3177static rtx
3178sparc_tls_got (void)
3179{
3180 rtx temp;
3181 if (flag_pic)
3182 {
e3b5732b 3183 crtl->uses_pic_offset_table = 1;
5751a10b
JJ		 3184 return pic_offset_table_rtx;
3185 }
3186
3187 if (!global_offset_table)
3188 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3189 temp = gen_reg_rtx (Pmode);
3190 emit_move_insn (temp, global_offset_table);
3191 return temp;
3192}
3193
208384fd 3194/* Return true if X contains a thread-local symbol. */
38fc66ba 3195
208384fd 3196static bool
38fc66ba
EB		 3197sparc_tls_referenced_p (rtx x)
3198{
3199 if (!TARGET_HAVE_TLS)
3200 return false;
3201
208384fd
EB		 3202 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3203 x = XEXP (XEXP (x, 0), 0);
3204
3205 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3206 return true;
3207
3208 /* That's all we handle in legitimize_tls_address for now. */
3209 return false;
38fc66ba 3210}
5751a10b
JJ		 3211
3212/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3213 this (thread-local) address. */
3214
208384fd 3215static rtx
5751a10b
JJ		 3216legitimize_tls_address (rtx addr)
3217{
3218 rtx temp1, temp2, temp3, ret, o0, got, insn;
3219
b3a13419 3220 gcc_assert (can_create_pseudo_p ());
5751a10b
JJ		 3221
3222 if (GET_CODE (addr) == SYMBOL_REF)
3223 switch (SYMBOL_REF_TLS_MODEL (addr))
3224 {
3225 case TLS_MODEL_GLOBAL_DYNAMIC:
3226 start_sequence ();
3227 temp1 = gen_reg_rtx (SImode);
3228 temp2 = gen_reg_rtx (SImode);
3229 ret = gen_reg_rtx (Pmode);
3230 o0 = gen_rtx_REG (Pmode, 8);
3231 got = sparc_tls_got ();
3232 emit_insn (gen_tgd_hi22 (temp1, addr));
3233 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3234 if (TARGET_ARCH32)
3235 {
3236 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3237 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3238 addr, const1_rtx));
3239 }
3240 else
3241 {
3242 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3243 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3244 addr, const1_rtx));
3245 }
3246 CALL_INSN_FUNCTION_USAGE (insn)
3247 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3248 CALL_INSN_FUNCTION_USAGE (insn));
3249 insn = get_insns ();
3250 end_sequence ();
3251 emit_libcall_block (insn, ret, o0, addr);
3252 break;
3253
3254 case TLS_MODEL_LOCAL_DYNAMIC:
3255 start_sequence ();
3256 temp1 = gen_reg_rtx (SImode);
3257 temp2 = gen_reg_rtx (SImode);
3258 temp3 = gen_reg_rtx (Pmode);
3259 ret = gen_reg_rtx (Pmode);
3260 o0 = gen_rtx_REG (Pmode, 8);
3261 got = sparc_tls_got ();
3262 emit_insn (gen_tldm_hi22 (temp1));
3263 emit_insn (gen_tldm_lo10 (temp2, temp1));
3264 if (TARGET_ARCH32)
3265 {
3266 emit_insn (gen_tldm_add32 (o0, got, temp2));
3267 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3268 const1_rtx));
3269 }
3270 else
3271 {
3272 emit_insn (gen_tldm_add64 (o0, got, temp2));
3273 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3274 const1_rtx));
3275 }
3276 CALL_INSN_FUNCTION_USAGE (insn)
3277 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3278 CALL_INSN_FUNCTION_USAGE (insn));
3279 insn = get_insns ();
3280 end_sequence ();
3281 emit_libcall_block (insn, temp3, o0,
3282 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3283 UNSPEC_TLSLD_BASE));
3284 temp1 = gen_reg_rtx (SImode);
3285 temp2 = gen_reg_rtx (SImode);
3286 emit_insn (gen_tldo_hix22 (temp1, addr));
3287 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3288 if (TARGET_ARCH32)
3289 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3290 else
3291 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3292 break;
3293
3294 case TLS_MODEL_INITIAL_EXEC:
3295 temp1 = gen_reg_rtx (SImode);
3296 temp2 = gen_reg_rtx (SImode);
3297 temp3 = gen_reg_rtx (Pmode);
3298 got = sparc_tls_got ();
3299 emit_insn (gen_tie_hi22 (temp1, addr));
3300 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3301 if (TARGET_ARCH32)
3302 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3303 else
3304 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3305 if (TARGET_SUN_TLS)
3306 {
3307 ret = gen_reg_rtx (Pmode);
3308 if (TARGET_ARCH32)
3309 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3310 temp3, addr));
3311 else
3312 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3313 temp3, addr));
3314 }
3315 else
3316 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3317 break;
3318
3319 case TLS_MODEL_LOCAL_EXEC:
3320 temp1 = gen_reg_rtx (Pmode);
3321 temp2 = gen_reg_rtx (Pmode);
3322 if (TARGET_ARCH32)
3323 {
3324 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3325 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3326 }
3327 else
3328 {
3329 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3330 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3331 }
3332 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3333 break;
3334
3335 default:
f5f7d171 3336 gcc_unreachable ();
5751a10b
JJ		 3337 }
3338
208384fd
EB		 3339 else if (GET_CODE (addr) == CONST)
3340 {
3341 rtx base, offset;
3342
3343 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3344
3345 base = legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
3346 offset = XEXP (XEXP (addr, 0), 1);
3347
3348 base = force_operand (base, NULL_RTX);
3349 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3350 offset = force_reg (Pmode, offset);
3351 ret = gen_rtx_PLUS (Pmode, base, offset);
3352 }
3353
5751a10b 3354 else
f5f7d171 3355 gcc_unreachable (); /* for now ... */
5751a10b
JJ		 3356
3357 return ret;
3358}
3359
e0d80184
DM		 3360/* Legitimize PIC addresses. If the address is already position-independent,
3361 we return ORIG. Newly generated position-independent addresses go into a
88cad84b 3362 reg. This is REG if nonzero, otherwise we allocate register(s) as
e0d80184 3363 necessary. */
795068a4 3364
208384fd
EB		 3365static rtx
3366legitimize_pic_address (rtx orig, rtx reg)
e0d80184 3367{
878ee0ab
DM		 3368 bool gotdata_op = false;
3369
1910440e
RS		 3370 if (GET_CODE (orig) == SYMBOL_REF
3371 /* See the comment in sparc_expand_move. */
3372 || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF))
82d6b402 3373 {
e0d80184
DM		 3374 rtx pic_ref, address;
3375 rtx insn;
82d6b402 3376
e0d80184 3377 if (reg == 0)
82d6b402 3378 {
f5f7d171
JM		 3379 gcc_assert (! reload_in_progress && ! reload_completed);
3380 reg = gen_reg_rtx (Pmode);
82d6b402 3381 }
795068a4 3382
e0d80184 3383 if (flag_pic == 2)
4fb4e4b8 3384 {
e0d80184
DM		 3385 /* If not during reload, allocate another temp reg here for loading
3386 in the address, so that these instructions can be optimized
3387 properly. */
3388 rtx temp_reg = ((reload_in_progress || reload_completed)
3389 ? reg : gen_reg_rtx (Pmode));
3390
3391 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3392 won't get confused into thinking that these two instructions
3393 are loading in the true address of the symbol. If in the
3394 future a PIC rtx exists, that should be used instead. */
bea5071f 3395 if (TARGET_ARCH64)
be3f1ff5 3396 {
bea5071f
EB		 3397 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3398 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
be3f1ff5
DM		 3399 }
3400 else
3401 {
bea5071f
EB		 3402 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3403 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
be3f1ff5 3404 }
e0d80184 3405 address = temp_reg;
878ee0ab 3406 gotdata_op = true;
4fb4e4b8
DE		 3407 }
3408 else
e0d80184
DM		 3409 address = orig;
3410
e3b5732b 3411 crtl->uses_pic_offset_table = 1;
878ee0ab
DM		 3412 if (gotdata_op)
3413 {
3414 if (TARGET_ARCH64)
3415 insn = emit_insn (gen_movdi_pic_gotdata_op (reg, pic_offset_table_rtx,
3416 address, orig));
3417 else
3418 insn = emit_insn (gen_movsi_pic_gotdata_op (reg, pic_offset_table_rtx,
3419 address, orig));
3420 }
3421 else
3422 {
3423 pic_ref = gen_const_mem (Pmode,
3424 gen_rtx_PLUS (Pmode,
3425 pic_offset_table_rtx, address));
3426 insn = emit_move_insn (reg, pic_ref);
3427 }
e0d80184
DM		 3428 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3429 by loop. */
bd94cb6e 3430 set_unique_reg_note (insn, REG_EQUAL, orig);
e0d80184 3431 return reg;
795068a4 3432 }
e0d80184 3433 else if (GET_CODE (orig) == CONST)
795068a4 3434 {
e0d80184 3435 rtx base, offset;
795068a4 3436
e0d80184
DM		 3437 if (GET_CODE (XEXP (orig, 0)) == PLUS
3438 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3439 return orig;
82d6b402 3440
e0d80184 3441 if (reg == 0)
4fb4e4b8 3442 {
f5f7d171
JM		 3443 gcc_assert (! reload_in_progress && ! reload_completed);
3444 reg = gen_reg_rtx (Pmode);
4fb4e4b8 3445 }
e0d80184 3446
f5f7d171 3447 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
208384fd
EB		 3448 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3449 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3450 base == reg ? NULL_RTX : reg);
61a66555 3451
e0d80184
DM		 3452 if (GET_CODE (offset) == CONST_INT)
3453 {
3454 if (SMALL_INT (offset))
ed8908e7 3455 return plus_constant (base, INTVAL (offset));
e0d80184
DM		 3456 else if (! reload_in_progress && ! reload_completed)
3457 offset = force_reg (Pmode, offset);
3458 else
3459 /* If we reach here, then something is seriously wrong. */
f5f7d171 3460 gcc_unreachable ();
e0d80184
DM		 3461 }
3462 return gen_rtx_PLUS (Pmode, base, offset);
795068a4 3463 }
e0d80184
DM		 3464 else if (GET_CODE (orig) == LABEL_REF)
3465 /* ??? Why do we do this? */
3466 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3467 the register is live instead, in case it is eliminated. */
e3b5732b 3468 crtl->uses_pic_offset_table = 1;
795068a4 3469
e0d80184
DM		 3470 return orig;
3471}
795068a4 3472
5751a10b
JJ		 3473/* Try machine-dependent ways of modifying an illegitimate address X
3474 to be legitimate. If we find one, return the new, valid address.
3475
3476 OLDX is the address as it was before break_out_memory_refs was called.
3477 In some cases it is useful to look at this to decide what needs to be done.
3478
506d7b68
PB		 3479 MODE is the mode of the operand pointed to by X.
3480
3481 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
5751a10b 3482
208384fd 3483static rtx
506d7b68
PB		 3484sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3485 enum machine_mode mode)
5751a10b
JJ		 3486{
3487 rtx orig_x = x;
3488
3489 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3490 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3491 force_operand (XEXP (x, 0), NULL_RTX));
3492 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3493 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3494 force_operand (XEXP (x, 1), NULL_RTX));
3495 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3496 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3497 XEXP (x, 1));
3498 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3499 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3500 force_operand (XEXP (x, 1), NULL_RTX));
3501
c6c3dba9 3502 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
5751a10b
JJ		 3503 return x;
3504
208384fd 3505 if (sparc_tls_referenced_p (x))
5751a10b
JJ		 3506 x = legitimize_tls_address (x);
3507 else if (flag_pic)
208384fd 3508 x = legitimize_pic_address (x, NULL_RTX);
5751a10b
JJ		 3509 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3510 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3511 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3512 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3513 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3514 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3515 else if (GET_CODE (x) == SYMBOL_REF
3516 || GET_CODE (x) == CONST
208384fd 3517 || GET_CODE (x) == LABEL_REF)
5751a10b 3518 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
208384fd 3519
5751a10b
JJ		 3520 return x;
3521}
3522
9fd52c6c
DM		 3523#ifdef HAVE_GAS_HIDDEN
3524# define USE_HIDDEN_LINKONCE 1
3525#else
3526# define USE_HIDDEN_LINKONCE 0
3527#endif
795068a4 3528
9ac617d4 3529static void
9fd52c6c 3530get_pc_thunk_name (char name[32], unsigned int regno)
e0d80184 3531{
9fd52c6c 3532 const char *pic_name = reg_names[regno];
4fb4e4b8 3533
9fd52c6c
DM		 3534 /* Skip the leading '%' as that cannot be used in a
3535 symbol name. */
3536 pic_name += 1;
82d6b402 3537
9fd52c6c
DM		 3538 if (USE_HIDDEN_LINKONCE)
3539 sprintf (name, "__sparc_get_pc_thunk.%s", pic_name);
5e77eb53 3540 else
9fd52c6c 3541 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
5e77eb53
EB		 3542}
3543
3544/* Emit code to load the PIC register. */
3545
3546static void
9fd52c6c 3547load_pic_register (void)
5e77eb53
EB		 3548{
3549 int orig_flag_pic = flag_pic;
3550
1910440e
RS		 3551 if (TARGET_VXWORKS_RTP)
3552 {
3553 emit_insn (gen_vxworks_load_got ());
c41c1387 3554 emit_use (pic_offset_table_rtx);
1910440e
RS		 3555 return;
3556 }
3557
5e77eb53 3558 /* If we haven't initialized the special PIC symbols, do so now. */
9fd52c6c 3559 if (!pic_helper_needed)
5e77eb53 3560 {
9fd52c6c
DM		 3561 char name[32];
3562
3563 pic_helper_needed = true;
3564
3565 get_pc_thunk_name (name, REGNO (pic_offset_table_rtx));
3566 pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
3567
5e77eb53 3568 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
e0d80184 3569 }
82d6b402 3570
ef573211 3571 flag_pic = 0;
eb7a7903
EB		 3572 if (TARGET_ARCH64)
3573 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
5e77eb53 3574 pic_helper_symbol));
eb7a7903
EB		 3575 else
3576 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
5e77eb53 3577 pic_helper_symbol));
e0d80184 3578 flag_pic = orig_flag_pic;
82d6b402 3579
e0d80184
DM		 3580 /* Need to emit this whether or not we obey regdecls,
3581 since setjmp/longjmp can cause life info to screw up.
3582 ??? In the case where we don't obey regdecls, this is not sufficient
3583 since we may not fall out the bottom. */
c41c1387 3584 emit_use (pic_offset_table_rtx);
795068a4 3585}
1910440e
RS		 3586
3587/* Emit a call instruction with the pattern given by PAT. ADDR is the
3588 address of the call target. */
3589
3590void
3591sparc_emit_call_insn (rtx pat, rtx addr)
3592{
3593 rtx insn;
3594
3595 insn = emit_call_insn (pat);
3596
3597 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3598 if (TARGET_VXWORKS_RTP
3599 && flag_pic
3600 && GET_CODE (addr) == SYMBOL_REF
3601 && (SYMBOL_REF_DECL (addr)
3602 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
3603 : !SYMBOL_REF_LOCAL_P (addr)))
3604 {
3605 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
e3b5732b 3606 crtl->uses_pic_offset_table = 1;
1910440e
RS		 3607 }
3608}
ab835497 3609\f
e0d80184 3610/* Return 1 if RTX is a MEM which is known to be aligned to at
7a31a340 3611 least a DESIRED byte boundary. */
a3ee5899 3612
e0d80184 3613int
fc27d102 3614mem_min_alignment (rtx mem, int desired)
ab835497 3615{
e0d80184
DM		 3616 rtx addr, base, offset;
3617
3618 /* If it's not a MEM we can't accept it. */
3619 if (GET_CODE (mem) != MEM)
3620 return 0;
3621
167a1354 3622 /* Obviously... */
0f95e914
EB		 3623 if (!TARGET_UNALIGNED_DOUBLES
3624 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
167a1354
EB		 3625 return 1;
3626
3627 /* ??? The rest of the function predates MEM_ALIGN so
3628 there is probably a bit of redundancy. */
e0d80184
DM		 3629 addr = XEXP (mem, 0);
3630 base = offset = NULL_RTX;
3631 if (GET_CODE (addr) == PLUS)
ab835497 3632 {
e0d80184 3633 if (GET_CODE (XEXP (addr, 0)) == REG)
61a55e8b 3634 {
e0d80184
DM		 3635 base = XEXP (addr, 0);
3636
3637 /* What we are saying here is that if the base
3638 REG is aligned properly, the compiler will make
3639 sure any REG based index upon it will be so
3640 as well. */
3641 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3642 offset = XEXP (addr, 1);
61a55e8b 3643 else
e0d80184 3644 offset = const0_rtx;
61a55e8b 3645 }
ab835497 3646 }
e0d80184 3647 else if (GET_CODE (addr) == REG)
ab835497 3648 {
e0d80184
DM		 3649 base = addr;
3650 offset = const0_rtx;
ab835497 3651 }
82d6b402 3652
e0d80184 3653 if (base != NULL_RTX)
795068a4 3654 {
e0d80184
DM		 3655 int regno = REGNO (base);
3656
563c12b0 3657 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
61a55e8b 3658 {
e0d80184
DM		 3659 /* Check if the compiler has recorded some information
3660 about the alignment of the base REG. If reload has
021e2ecc
JJ		 3661 completed, we already matched with proper alignments.
3662 If not running global_alloc, reload might give us
3663 unaligned pointer to local stack though. */
bdb429a5
RK		 3664 if (((cfun != 0
3665 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
021e2ecc 3666 || (optimize && reload_completed))
bdb429a5 3667 && (INTVAL (offset) & (desired - 1)) == 0)
e0d80184 3668 return 1;
61a55e8b 3669 }
795068a4 3670 else
e0d80184
DM		 3671 {
3672 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3673 return 1;
3674 }
795068a4 3675 }
e0d80184
DM		 3676 else if (! TARGET_UNALIGNED_DOUBLES
3677 || CONSTANT_P (addr)
3678 || GET_CODE (addr) == LO_SUM)
795068a4 3679 {
e0d80184
DM		 3680 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3681 is true, in which case we can only assume that an access is aligned if
3682 it is to a constant address, or the address involves a LO_SUM. */
3683 return 1;
795068a4 3684 }
4900aa61 3685
e0d80184
DM		 3686 /* An obviously unaligned address. */
3687 return 0;
795068a4 3688}
e0d80184 3689
ab835497 3690\f
61a55e8b 3691/* Vectors to keep interesting information about registers where it can easily
01d3224a 3692 be got. We used to use the actual mode value as the bit number, but there
61a55e8b
DE		 3693 are more than 32 modes now. Instead we use two tables: one indexed by
3694 hard register number, and one indexed by mode. */
3695
3696/* The purpose of sparc_mode_class is to shrink the range of modes so that
a7b376ee 3697 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
61a55e8b
DE		 3698 mapped into one sparc_mode_class mode. */
3699
3700enum sparc_mode_class {
61a55e8b 3701 S_MODE, D_MODE, T_MODE, O_MODE,
c4ce6853
DE		 3702 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3703 CC_MODE, CCFP_MODE
61a55e8b 3704};
ab835497 3705
61a55e8b
DE		 3706/* Modes for single-word and smaller quantities. */
3707#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3708
3709/* Modes for double-word and smaller quantities. */
3710#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3711
3712/* Modes for quad-word and smaller quantities. */
3713#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
ab835497 3714
d0cee9ba
JJ		 3715/* Modes for 8-word and smaller quantities. */
3716#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3717
1e4eb8d1
JW		 3718/* Modes for single-float quantities. We must allow any single word or
3719 smaller quantity. This is because the fix/float conversion instructions
3720 take integer inputs/outputs from the float registers. */
3721#define SF_MODES (S_MODES)
ab835497 3722
61a55e8b 3723/* Modes for double-float and smaller quantities. */
948bf106 3724#define DF_MODES (D_MODES)
61a55e8b
DE		 3725
3726/* Modes for quad-float and smaller quantities. */
948bf106 3727#define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
61a55e8b 3728
948bf106
EB		 3729/* Modes for quad-float pairs and smaller quantities. */
3730#define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
d0cee9ba 3731
948bf106
EB		 3732/* Modes for double-float only quantities. */
3733#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
d0cee9ba 3734
948bf106
EB		 3735/* Modes for quad-float and double-float only quantities. */
3736#define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
d0cee9ba 3737
948bf106
EB		 3738/* Modes for quad-float pairs and double-float only quantities. */
3739#define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
ab835497 3740
c4ce6853
DE		 3741/* Modes for condition codes. */
3742#define CC_MODES (1 << (int) CC_MODE)
3743#define CCFP_MODES (1 << (int) CCFP_MODE)
3744
ab835497
RK		 3745/* Value is 1 if register/mode pair is acceptable on sparc.
3746 The funny mixture of D and T modes is because integer operations
3747 do not specially operate on tetra quantities, so non-quad-aligned
3748 registers can hold quadword quantities (except %o4 and %i4 because
c4ce6853 3749 they cross fixed registers). */
ab835497 3750
61a55e8b 3751/* This points to either the 32 bit or the 64 bit version. */
0b5826ac 3752const int *hard_regno_mode_classes;
61a55e8b 3753
0b5826ac 3754static const int hard_32bit_mode_classes[] = {
c4ce6853 3755 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
ab835497
RK		 3756 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3757 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3758 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3759
d0cee9ba
JJ		 3760 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3761 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3762 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3763 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
a9e27770
DE		 3764
3765 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3766 and none can hold SFmode/SImode values. */
d0cee9ba
JJ		 3767 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3768 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3769 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3770 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
a9e27770
DE		 3771
3772 /* %fcc[0123] */
c4ce6853
DE		 3773 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3774
3775 /* %icc */
3776 CC_MODES
61a55e8b
DE		 3777};
3778
0b5826ac 3779static const int hard_64bit_mode_classes[] = {
c4ce6853 3780 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
d0cee9ba 3781 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b 3782 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
d0cee9ba 3783 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b 3784
d0cee9ba
JJ		 3785 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3786 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3787 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3788 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
61a55e8b 3789
a9e27770 3790 /* FP regs f32 to f63. Only the even numbered registers actually exist,
61a55e8b 3791 and none can hold SFmode/SImode values. */
d0cee9ba
JJ		 3792 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3793 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3794 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3795 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
61a55e8b
DE		 3796
3797 /* %fcc[0123] */
c4ce6853
DE		 3798 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3799
3800 /* %icc */
3801 CC_MODES
61a55e8b
DE		 3802};
3803
3804int sparc_mode_class [NUM_MACHINE_MODES];
3805
c4ce6853
DE		 3806enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3807
61a55e8b 3808static void
fc27d102 3809sparc_init_modes (void)
61a55e8b
DE		 3810{
3811 int i;
3812
61a55e8b
DE		 3813 for (i = 0; i < NUM_MACHINE_MODES; i++)
3814 {
3815 switch (GET_MODE_CLASS (i))
3816 {
3817 case MODE_INT:
3818 case MODE_PARTIAL_INT:
3819 case MODE_COMPLEX_INT:
3820 if (GET_MODE_SIZE (i) <= 4)
3821 sparc_mode_class[i] = 1 << (int) S_MODE;
3822 else if (GET_MODE_SIZE (i) == 8)
3823 sparc_mode_class[i] = 1 << (int) D_MODE;
3824 else if (GET_MODE_SIZE (i) == 16)
3825 sparc_mode_class[i] = 1 << (int) T_MODE;
3826 else if (GET_MODE_SIZE (i) == 32)
3827 sparc_mode_class[i] = 1 << (int) O_MODE;
4900aa61 3828 else
61a55e8b
DE		 3829 sparc_mode_class[i] = 0;
3830 break;
c75d6010
JM		 3831 case MODE_VECTOR_INT:
3832 if (GET_MODE_SIZE (i) <= 4)
3833 sparc_mode_class[i] = 1 << (int)SF_MODE;
3834 else if (GET_MODE_SIZE (i) == 8)
3835 sparc_mode_class[i] = 1 << (int)DF_MODE;
3836 break;
61a55e8b
DE		 3837 case MODE_FLOAT:
3838 case MODE_COMPLEX_FLOAT:
3839 if (GET_MODE_SIZE (i) <= 4)
3840 sparc_mode_class[i] = 1 << (int) SF_MODE;
3841 else if (GET_MODE_SIZE (i) == 8)
3842 sparc_mode_class[i] = 1 << (int) DF_MODE;
3843 else if (GET_MODE_SIZE (i) == 16)
3844 sparc_mode_class[i] = 1 << (int) TF_MODE;
3845 else if (GET_MODE_SIZE (i) == 32)
3846 sparc_mode_class[i] = 1 << (int) OF_MODE;
4900aa61 3847 else
61a55e8b
DE		 3848 sparc_mode_class[i] = 0;
3849 break;
3850 case MODE_CC:
61a55e8b
DE		 3851 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3852 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
61a55e8b 3853 else
94134f42
ZW		 3854 sparc_mode_class[i] = 1 << (int) CC_MODE;
3855 break;
3856 default:
3857 sparc_mode_class[i] = 0;
61a55e8b
DE		 3858 break;
3859 }
3860 }
3861
a9e27770 3862 if (TARGET_ARCH64)
61a55e8b
DE		 3863 hard_regno_mode_classes = hard_64bit_mode_classes;
3864 else
3865 hard_regno_mode_classes = hard_32bit_mode_classes;
c4ce6853
DE		 3866
3867 /* Initialize the array used by REGNO_REG_CLASS. */
3868 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3869 {
284d86e9
JC		 3870 if (i < 16 && TARGET_V8PLUS)
3871 sparc_regno_reg_class[i] = I64_REGS;
563c12b0 3872 else if (i < 32 || i == FRAME_POINTER_REGNUM)
c4ce6853
DE		 3873 sparc_regno_reg_class[i] = GENERAL_REGS;
3874 else if (i < 64)
3875 sparc_regno_reg_class[i] = FP_REGS;
3876 else if (i < 96)
3877 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3878 else if (i < 100)
3879 sparc_regno_reg_class[i] = FPCC_REGS;
3880 else
3881 sparc_regno_reg_class[i] = NO_REGS;
3882 }
61a55e8b 3883}
ab835497 3884\f
61a55e8b 3885/* Compute the frame size required by the function. This function is called
9ac617d4 3886 during the reload pass and also by sparc_expand_prologue. */
ab835497 3887
6a151f87 3888HOST_WIDE_INT
9ac617d4 3889sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
ab835497 3890{
38173d38 3891 int outgoing_args_size = (crtl->outgoing_args_size
4fb4e4b8 3892 + REG_PARM_STACK_SPACE (current_function_decl));
9ac617d4
EB		 3893 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3894 int i;
61a55e8b 3895
33074e5f
RH		 3896 if (TARGET_ARCH64)
3897 {
3898 for (i = 0; i < 8; i++)
6fb5fa3c 3899 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
33074e5f
RH		 3900 n_regs += 2;
3901 }
3902 else
3903 {
3904 for (i = 0; i < 8; i += 2)
6fb5fa3c
DB		 3905 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
3906 || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]))
61a55e8b 3907 n_regs += 2;
ab835497
RK		 3908 }
3909
33074e5f 3910 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
6fb5fa3c
DB		 3911 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
3912 || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]))
33074e5f
RH		 3913 n_regs += 2;
3914
9ac617d4 3915 /* Set up values for use in prologue and epilogue. */
61a55e8b 3916 num_gfregs = n_regs;
ab835497 3917
9ac617d4
EB		 3918 if (leaf_function_p
3919 && n_regs == 0
3920 && size == 0
38173d38 3921 && crtl->outgoing_args_size == 0)
9ac617d4 3922 actual_fsize = apparent_fsize = 0;
61a55e8b
DE		 3923 else
3924 {
225909c3
JS		 3925 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3926 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
61a55e8b
DE		 3927 apparent_fsize += n_regs * 4;
3928 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3929 }
ab835497
RK		 3930
3931 /* Make sure nothing can clobber our register windows.
3932 If a SAVE must be done, or there is a stack-local variable,
f8ece000 3933 the register window area must be allocated. */
9ac617d4 3934 if (! leaf_function_p || size > 0)
f8ece000 3935 actual_fsize += FIRST_PARM_OFFSET (current_function_decl);
ab835497 3936
61a55e8b
DE		 3937 return SPARC_STACK_ALIGN (actual_fsize);
3938}
3939
9ac617d4 3940/* Output any necessary .register pseudo-ops. */
61a55e8b 3941
9ac617d4
EB		 3942void
3943sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
61a55e8b 3944{
9ac617d4
EB		 3945#ifdef HAVE_AS_REGISTER_PSEUDO_OP
3946 int i;
6a151f87 3947
9ac617d4
EB		 3948 if (TARGET_ARCH32)
3949 return;
3950
3951 /* Check if %g[2367] were used without
3952 .register being printed for them already. */
3953 for (i = 2; i < 8; i++)
61a55e8b 3954 {
6fb5fa3c 3955 if (df_regs_ever_live_p (i)
9ac617d4
EB		 3956 && ! sparc_hard_reg_printed [i])
3957 {
3958 sparc_hard_reg_printed [i] = 1;
392e5756
JJ		 3959 /* %g7 is used as TLS base register, use #ignore
3960 for it instead of #scratch. */
3961 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
3962 i == 7 ? "ignore" : "scratch");
9ac617d4
EB		 3963 }
3964 if (i == 3) i = 5;
61a55e8b 3965 }
6a151f87 3966#endif
9ac617d4 3967}
6a151f87 3968
9ac617d4
EB		 3969/* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
3970 as needed. LOW should be double-word aligned for 32-bit registers.
3971 Return the new OFFSET. */
6a151f87 3972
9ac617d4
EB		 3973#define SORR_SAVE 0
3974#define SORR_RESTORE 1
3975
3976static int
3977save_or_restore_regs (int low, int high, rtx base, int offset, int action)
3978{
3979 rtx mem, insn;
3980 int i;
3981
3982 if (TARGET_ARCH64 && high <= 32)
3983 {
3984 for (i = low; i < high; i++)
6a151f87 3985 {
6fb5fa3c 3986 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
9ac617d4
EB		 3987 {
3988 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
3989 set_mem_alias_set (mem, sparc_sr_alias_set);
3990 if (action == SORR_SAVE)
3991 {
3992 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
3993 RTX_FRAME_RELATED_P (insn) = 1;
3994 }
3995 else /* action == SORR_RESTORE */
3996 emit_move_insn (gen_rtx_REG (DImode, i), mem);
3997 offset += 8;
3998 }
6a151f87 3999 }
9ac617d4
EB		 4000 }
4001 else
4002 {
4003 for (i = low; i < high; i += 2)
6a151f87 4004 {
6fb5fa3c
DB		 4005 bool reg0 = df_regs_ever_live_p (i) && ! call_used_regs[i];
4006 bool reg1 = df_regs_ever_live_p (i+1) && ! call_used_regs[i+1];
9ac617d4
EB		 4007 enum machine_mode mode;
4008 int regno;
4009
4010 if (reg0 && reg1)
4011 {
4012 mode = i < 32 ? DImode : DFmode;
4013 regno = i;
4014 }
4015 else if (reg0)
4016 {
4017 mode = i < 32 ? SImode : SFmode;
4018 regno = i;
4019 }
4020 else if (reg1)
4021 {
4022 mode = i < 32 ? SImode : SFmode;
4023 regno = i + 1;
4024 offset += 4;
4025 }
4026 else
4027 continue;
4028
4029 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4030 set_mem_alias_set (mem, sparc_sr_alias_set);
4031 if (action == SORR_SAVE)
4032 {
4033 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4034 RTX_FRAME_RELATED_P (insn) = 1;
4035 }
4036 else /* action == SORR_RESTORE */
4037 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4038
4039 /* Always preserve double-word alignment. */
4040 offset = (offset + 7) & -8;
6a151f87 4041 }
6a151f87 4042 }
9ac617d4
EB		 4043
4044 return offset;
ab835497
RK		 4045}
4046
9ac617d4
EB		 4047/* Emit code to save call-saved registers. */
4048
4049static void
f8ece000 4050emit_save_or_restore_regs (int action)
1cb36a98 4051{
9ac617d4
EB		 4052 HOST_WIDE_INT offset;
4053 rtx base;
1cb36a98 4054
9ac617d4 4055 offset = frame_base_offset - apparent_fsize;
1cb36a98 4056
f8ece000 4057 if (offset < -4096 || offset + num_gfregs * 4 > 4095)
1cb36a98 4058 {
9ac617d4
EB		 4059 /* ??? This might be optimized a little as %g1 might already have a
4060 value close enough that a single add insn will do. */
4061 /* ??? Although, all of this is probably only a temporary fix
4062 because if %g1 can hold a function result, then
4063 sparc_expand_epilogue will lose (the result will be
4064 clobbered). */
4065 base = gen_rtx_REG (Pmode, 1);
4066 emit_move_insn (base, GEN_INT (offset));
4067 emit_insn (gen_rtx_SET (VOIDmode,
4068 base,
4069 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4070 offset = 0;
1cb36a98 4071 }
9ac617d4
EB		 4072 else
4073 base = frame_base_reg;
4074
f8ece000
EB		 4075 offset = save_or_restore_regs (0, 8, base, offset, action);
4076 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, action);
9ac617d4 4077}
08c148a8 4078
e54c7471 4079/* Generate a save_register_window insn. */
08c148a8 4080
e54c7471
EB		 4081static rtx
4082gen_save_register_window (rtx increment)
08c148a8 4083{
9ac617d4 4084 if (TARGET_ARCH64)
e54c7471 4085 return gen_save_register_windowdi (increment);
9ac617d4 4086 else
e54c7471 4087 return gen_save_register_windowsi (increment);
08c148a8
NB		 4088}
4089
e54c7471 4090/* Generate an increment for the stack pointer. */
915f619f 4091
e54c7471
EB		 4092static rtx
4093gen_stack_pointer_inc (rtx increment)
ab835497 4094{
6deb0339
EB		 4095 return gen_rtx_SET (VOIDmode,
4096 stack_pointer_rtx,
4097 gen_rtx_PLUS (Pmode,
4098 stack_pointer_rtx,
4099 increment));
e54c7471
EB		 4100}
4101
4102/* Generate a decrement for the stack pointer. */
4103
4104static rtx
4105gen_stack_pointer_dec (rtx decrement)
4106{
6deb0339
EB		 4107 return gen_rtx_SET (VOIDmode,
4108 stack_pointer_rtx,
4109 gen_rtx_MINUS (Pmode,
4110 stack_pointer_rtx,
4111 decrement));
9ac617d4
EB		 4112}
4113
4114/* Expand the function prologue. The prologue is responsible for reserving
4115 storage for the frame, saving the call-saved registers and loading the
4116 PIC register if needed. */
4117
4118void
4119sparc_expand_prologue (void)
4120{
e54c7471
EB		 4121 rtx insn;
4122 int i;
4123
5be9b7a1
EB		 4124 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4125 on the final value of the flag means deferring the prologue/epilogue
4126 expansion until just before the second scheduling pass, which is too
4127 late to emit multiple epilogues or return insns.
4128
4129 Of course we are making the assumption that the value of the flag
4130 will not change between now and its final value. Of the three parts
4131 of the formula, only the last one can reasonably vary. Let's take a
4132 closer look, after assuming that the first two ones are set to true
4133 (otherwise the last value is effectively silenced).
4134
4135 If only_leaf_regs_used returns false, the global predicate will also
4136 be false so the actual frame size calculated below will be positive.
4137 As a consequence, the save_register_window insn will be emitted in
4138 the instruction stream; now this insn explicitly references %fp
4139 which is not a leaf register so only_leaf_regs_used will always
4140 return false subsequently.
4141
4142 If only_leaf_regs_used returns true, we hope that the subsequent
4143 optimization passes won't cause non-leaf registers to pop up. For
4144 example, the regrename pass has special provisions to not rename to
4145 non-leaf registers in a leaf function. */
4146 sparc_leaf_function_p
4147 = optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
1cb36a98 4148
915f619f
JW		 4149 /* Need to use actual_fsize, since we are also allocating
4150 space for our callee (and our own register save area). */
5be9b7a1
EB		 4151 actual_fsize
4152 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4153
4154 /* Advertise that the data calculated just above are now valid. */
4155 sparc_prologue_data_valid_p = true;
ab835497 4156
5be9b7a1 4157 if (sparc_leaf_function_p)
61a55e8b 4158 {
9ac617d4 4159 frame_base_reg = stack_pointer_rtx;
61a55e8b
DE		 4160 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4161 }
4162 else
4163 {
9ac617d4 4164 frame_base_reg = hard_frame_pointer_rtx;
61a55e8b
DE		 4165 frame_base_offset = SPARC_STACK_BIAS;
4166 }
4167
915f619f
JW		 4168 if (actual_fsize == 0)
4169 /* do nothing. */ ;
5be9b7a1 4170 else if (sparc_leaf_function_p)
ab835497 4171 {
3592ea0d 4172 if (actual_fsize <= 4096)
e54c7471 4173 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
3592ea0d 4174 else if (actual_fsize <= 8192)
915f619f 4175 {
e54c7471
EB		 4176 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4177 /* %sp is still the CFA register. */
4178 RTX_FRAME_RELATED_P (insn) = 1;
4179 insn
4180 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
915f619f
JW		 4181 }
4182 else
4183 {
9ac617d4
EB		 4184 rtx reg = gen_rtx_REG (Pmode, 1);
4185 emit_move_insn (reg, GEN_INT (-actual_fsize));
e54c7471 4186 insn = emit_insn (gen_stack_pointer_inc (reg));
bbbbb16a
ILT		 4187 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4188 gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
915f619f 4189 }
e54c7471
EB		 4190
4191 RTX_FRAME_RELATED_P (insn) = 1;
ab835497 4192 }
9ac617d4 4193 else
5f4241d5 4194 {
3592ea0d 4195 if (actual_fsize <= 4096)
e54c7471 4196 insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
3592ea0d
DE		 4197 else if (actual_fsize <= 8192)
4198 {
e54c7471
EB		 4199 insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
4200 /* %sp is not the CFA register anymore. */
4201 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
3592ea0d 4202 }
915f619f 4203 else
3592ea0d 4204 {
9ac617d4
EB		 4205 rtx reg = gen_rtx_REG (Pmode, 1);
4206 emit_move_insn (reg, GEN_INT (-actual_fsize));
e54c7471 4207 insn = emit_insn (gen_save_register_window (reg));
3592ea0d 4208 }
e54c7471
EB		 4209
4210 RTX_FRAME_RELATED_P (insn) = 1;
4211 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4212 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
ab835497
RK		 4213 }
4214
9ac617d4 4215 if (num_gfregs)
f8ece000 4216 emit_save_or_restore_regs (SORR_SAVE);
9ac617d4
EB		 4217
4218 /* Load the PIC register if needed. */
e3b5732b 4219 if (flag_pic && crtl->uses_pic_offset_table)
9fd52c6c 4220 load_pic_register ();
9ac617d4 4221}
4900aa61 4222
9ac617d4 4223/* This function generates the assembly code for function entry, which boils
f8ece000 4224 down to emitting the necessary .register directives. */
9ac617d4
EB		 4225
4226static void
4227sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4228{
5be9b7a1 4229 /* Check that the assumption we made in sparc_expand_prologue is valid. */
f5f7d171 4230 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
9ac617d4
EB		 4231
4232 sparc_output_scratch_registers (file);
9ac617d4
EB		 4233}
4234
4235/* Expand the function epilogue, either normal or part of a sibcall.
4236 We emit all the instructions except the return or the call. */
c53aa195 4237
9ac617d4
EB		 4238void
4239sparc_expand_epilogue (void)
4240{
61a55e8b 4241 if (num_gfregs)
f8ece000 4242 emit_save_or_restore_regs (SORR_RESTORE);
ab835497 4243
9ac617d4
EB		 4244 if (actual_fsize == 0)
4245 /* do nothing. */ ;
5be9b7a1 4246 else if (sparc_leaf_function_p)
9ac617d4
EB		 4247 {
4248 if (actual_fsize <= 4096)
e54c7471 4249 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize)));
9ac617d4 4250 else if (actual_fsize <= 8192)
61a55e8b 4251 {
e54c7471
EB		 4252 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4253 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize)));
61a55e8b 4254 }
ab835497 4255 else
61a55e8b 4256 {
9ac617d4
EB		 4257 rtx reg = gen_rtx_REG (Pmode, 1);
4258 emit_move_insn (reg, GEN_INT (-actual_fsize));
e54c7471 4259 emit_insn (gen_stack_pointer_dec (reg));
61a55e8b 4260 }
ab835497
RK		 4261 }
4262}
5be9b7a1
EB		 4263
4264/* Return true if it is appropriate to emit `return' instructions in the
4265 body of a function. */
4266
4267bool
4268sparc_can_use_return_insn_p (void)
4269{
4270 return sparc_prologue_data_valid_p
4271 && (actual_fsize == 0 || !sparc_leaf_function_p);
4272}
4900aa61 4273
9ac617d4 4274/* This function generates the assembly code for function exit. */
4900aa61 4275
9ac617d4
EB		 4276static void
4277sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4278{
4279 /* If code does not drop into the epilogue, we have to still output
4280 a dummy nop for the sake of sane backtraces. Otherwise, if the
4281 last two instructions of a function were "call foo; dslot;" this
19525b57 4282 can make the return PC of foo (i.e. address of call instruction
9ac617d4 4283 plus 8) point to the first instruction in the next function. */
ab835497 4284
9ac617d4 4285 rtx insn, last_real_insn;
7d167afd 4286
9ac617d4
EB		 4287 insn = get_last_insn ();
4288
4289 last_real_insn = prev_real_insn (insn);
4290 if (last_real_insn
4291 && GET_CODE (last_real_insn) == INSN
4292 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4293 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4294
4295 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4296 fputs("\tnop\n", file);
4297
4298 sparc_output_deferred_case_vectors ();
4299}
4900aa61 4300
9ac617d4 4301/* Output a 'restore' instruction. */
4900aa61 4302
7d167afd 4303static void
6244b14e 4304output_restore (rtx pat)
7d167afd 4305{
6244b14e 4306 rtx operands[3];
7d167afd 4307
6244b14e 4308 if (! pat)
7d167afd 4309 {
9ac617d4
EB		 4310 fputs ("\t restore\n", asm_out_file);
4311 return;
7d167afd
JJ		 4312 }
4313
f5f7d171 4314 gcc_assert (GET_CODE (pat) == SET);
08c148a8 4315
9ac617d4
EB		 4316 operands[0] = SET_DEST (pat);
4317 pat = SET_SRC (pat);
08c148a8 4318
9ac617d4
EB		 4319 switch (GET_CODE (pat))
4320 {
4321 case PLUS:
4322 operands[1] = XEXP (pat, 0);
4323 operands[2] = XEXP (pat, 1);
4324 output_asm_insn (" restore %r1, %2, %Y0", operands);
4325 break;
4326 case LO_SUM:
4327 operands[1] = XEXP (pat, 0);
4328 operands[2] = XEXP (pat, 1);
4329 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4330 break;
4331 case ASHIFT:
4332 operands[1] = XEXP (pat, 0);
f5f7d171 4333 gcc_assert (XEXP (pat, 1) == const1_rtx);
9ac617d4
EB		 4334 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4335 break;
4336 default:
4337 operands[1] = pat;
4338 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4339 break;
4340 }
08c148a8 4341}
4900aa61 4342
9ac617d4 4343/* Output a return. */
08c148a8 4344
9ac617d4
EB		 4345const char *
4346output_return (rtx insn)
ab835497 4347{
5be9b7a1 4348 if (sparc_leaf_function_p)
e48addee 4349 {
9ac617d4
EB		 4350 /* This is a leaf function so we don't have to bother restoring the
4351 register window, which frees us from dealing with the convoluted
4352 semantics of restore/return. We simply output the jump to the
4e5b002b 4353 return address and the insn in the delay slot (if any). */
7a31a340 4354
e3b5732b 4355 gcc_assert (! crtl->calls_eh_return);
ac59ed37 4356
4e5b002b 4357 return "jmp\t%%o7+%)%#";
bfd6bc60 4358 }
ab835497 4359 else
ab835497 4360 {
9ac617d4
EB		 4361 /* This is a regular function so we have to restore the register window.
4362 We may have a pending insn for the delay slot, which will be either
4363 combined with the 'restore' instruction or put in the delay slot of
4364 the 'return' instruction. */
4365
e3b5732b 4366 if (crtl->calls_eh_return)
33074e5f 4367 {
9ac617d4
EB		 4368 /* If the function uses __builtin_eh_return, the eh_return
4369 machinery occupies the delay slot. */
f5f7d171 4370 gcc_assert (! final_sequence);
ab835497 4371
951661a1
EB		 4372 if (! flag_delayed_branch)
4373 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4374
9ac617d4
EB		 4375 if (TARGET_V9)
4376 fputs ("\treturn\t%i7+8\n", asm_out_file);
4377 else
4378 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4379
951661a1
EB		 4380 if (flag_delayed_branch)
4381 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4382 else
4383 fputs ("\t nop\n", asm_out_file);
33074e5f 4384 }
4e5b002b 4385 else if (final_sequence)
ef8200df 4386 {
9ac617d4
EB		 4387 rtx delay, pat;
4388
4389 delay = NEXT_INSN (insn);
f5f7d171 4390 gcc_assert (delay);
1150a841 4391
9ac617d4
EB		 4392 pat = PATTERN (delay);
4393
4394 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
33074e5f 4395 {
9ac617d4 4396 epilogue_renumber (&pat, 0);
4e5b002b 4397 return "return\t%%i7+%)%#";
1150a841 4398 }
33074e5f 4399 else
ab835497 4400 {
4e5b002b 4401 output_asm_insn ("jmp\t%%i7+%)", NULL);
6244b14e 4402 output_restore (pat);
4e5b002b
EB		 4403 PATTERN (delay) = gen_blockage ();
4404 INSN_CODE (delay) = -1;
ab835497 4405 }
ef8200df 4406 }
33074e5f 4407 else
9ac617d4
EB		 4408 {
4409 /* The delay slot is empty. */
4410 if (TARGET_V9)
4e5b002b 4411 return "return\t%%i7+%)\n\t nop";
951661a1 4412 else if (flag_delayed_branch)
4e5b002b 4413 return "jmp\t%%i7+%)\n\t restore";
951661a1 4414 else
4e5b002b 4415 return "restore\n\tjmp\t%%o7+%)\n\t nop";
9ac617d4 4416 }
6a151f87 4417 }
e0d80184 4418
9ac617d4 4419 return "";
ab835497 4420}
7d167afd
JJ		 4421
4422/* Output a sibling call. */
4423
4424const char *
fc27d102 4425output_sibcall (rtx insn, rtx call_operand)
7d167afd 4426{
9ac617d4 4427 rtx operands[1];
7d167afd 4428
f5f7d171 4429 gcc_assert (flag_delayed_branch);
951661a1 4430
7d167afd
JJ		 4431 operands[0] = call_operand;
4432
5be9b7a1 4433 if (sparc_leaf_function_p)
7d167afd 4434 {
9ac617d4
EB		 4435 /* This is a leaf function so we don't have to bother restoring the
4436 register window. We simply output the jump to the function and
4437 the insn in the delay slot (if any). */
7d167afd 4438
f5f7d171 4439 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
9ac617d4 4440
4e5b002b
EB		 4441 if (final_sequence)
4442 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4443 operands);
7d167afd 4444 else
4e5b002b
EB		 4445 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4446 it into branch if possible. */
4447 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4448 operands);
7d167afd 4449 }
9ac617d4 4450 else
7d167afd 4451 {
9ac617d4
EB		 4452 /* This is a regular function so we have to restore the register window.
4453 We may have a pending insn for the delay slot, which will be combined
4454 with the 'restore' instruction. */
7d167afd 4455
9ac617d4 4456 output_asm_insn ("call\t%a0, 0", operands);
7d167afd 4457
4e5b002b 4458 if (final_sequence)
7d167afd 4459 {
9ac617d4 4460 rtx delay = NEXT_INSN (insn);
f5f7d171 4461 gcc_assert (delay);
9ac617d4 4462
6244b14e 4463 output_restore (PATTERN (delay));
9ac617d4
EB		 4464
4465 PATTERN (delay) = gen_blockage ();
4466 INSN_CODE (delay) = -1;
7d167afd 4467 }
9ac617d4 4468 else
6244b14e 4469 output_restore (NULL_RTX);
7d167afd 4470 }
9ac617d4 4471
7d167afd
JJ		 4472 return "";
4473}
4fb4e4b8
DE		 4474\f
4475/* Functions for handling argument passing.
4476
1b5963f7 4477 For 32-bit, the first 6 args are normally in registers and the rest are
4fb4e4b8
DE		 4478 pushed. Any arg that starts within the first 6 words is at least
4479 partially passed in a register unless its data type forbids.
4480
1b5963f7 4481 For 64-bit, the argument registers are laid out as an array of 16 elements
4fb4e4b8
DE		 4482 and arguments are added sequentially. The first 6 int args and up to the
4483 first 16 fp args (depending on size) are passed in regs.
4484
4485 Slot Stack Integral Float Float in structure Double Long Double
4486 ---- ----- -------- ----- ------------------ ------ -----------
4487 15 [SP+248] %f31 %f30,%f31 %d30
4488 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4489 13 [SP+232] %f27 %f26,%f27 %d26
4490 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4491 11 [SP+216] %f23 %f22,%f23 %d22
4492 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4493 9 [SP+200] %f19 %f18,%f19 %d18
4494 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4495 7 [SP+184] %f15 %f14,%f15 %d14
4496 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4497 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4498 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4499 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4500 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4501 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4502 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4503
4504 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4505
1b5963f7 4506 Integral arguments are always passed as 64-bit quantities appropriately
4fb4e4b8
DE		 4507 extended.
4508
4509 Passing of floating point values is handled as follows.
4510 If a prototype is in scope:
4511 If the value is in a named argument (i.e. not a stdarg function or a
4512 value not part of the `...') then the value is passed in the appropriate
4513 fp reg.
4514 If the value is part of the `...' and is passed in one of the first 6
4515 slots then the value is passed in the appropriate int reg.
4516 If the value is part of the `...' and is not passed in one of the first 6
4517 slots then the value is passed in memory.
4518 If a prototype is not in scope:
4519 If the value is one of the first 6 arguments the value is passed in the
4520 appropriate integer reg and the appropriate fp reg.
4521 If the value is not one of the first 6 arguments the value is passed in
4522 the appropriate fp reg and in memory.
1b5963f7
EB		 4523
4524
4900aa61 4525 Summary of the calling conventions implemented by GCC on the SPARC:
1b5963f7
EB		 4526
4527 32-bit ABI:
4528 size argument return value
4529
4530 small integer <4 int. reg. int. reg.
4531 word 4 int. reg. int. reg.
4532 double word 8 int. reg. int. reg.
4533
4534 _Complex small integer <8 int. reg. int. reg.
4535 _Complex word 8 int. reg. int. reg.
4536 _Complex double word 16 memory int. reg.
4537
4538 vector integer <=8 int. reg. FP reg.
4539 vector integer >8 memory memory
4540
4541 float 4 int. reg. FP reg.
4542 double 8 int. reg. FP reg.
4543 long double 16 memory memory
4544
4545 _Complex float 8 memory FP reg.
4546 _Complex double 16 memory FP reg.
4547 _Complex long double 32 memory FP reg.
4548
45261626 4549 vector float any memory memory
1b5963f7
EB		 4550
4551 aggregate any memory memory
4552
4553
4554
4555 64-bit ABI:
4556 size argument return value
4557
4558 small integer <8 int. reg. int. reg.
4559 word 8 int. reg. int. reg.
4560 double word 16 int. reg. int. reg.
4561
4562 _Complex small integer <16 int. reg. int. reg.
4563 _Complex word 16 int. reg. int. reg.
4564 _Complex double word 32 memory int. reg.
4565
4566 vector integer <=16 FP reg. FP reg.
4567 vector integer 16<s<=32 memory FP reg.
4568 vector integer >32 memory memory
4569
4570 float 4 FP reg. FP reg.
4571 double 8 FP reg. FP reg.
4572 long double 16 FP reg. FP reg.
4573
4574 _Complex float 8 FP reg. FP reg.
4575 _Complex double 16 FP reg. FP reg.
4576 _Complex long double 32 memory FP reg.
4577
4578 vector float <=16 FP reg. FP reg.
4579 vector float 16<s<=32 memory FP reg.
4580 vector float >32 memory memory
4581
4582 aggregate <=16 reg. reg.
4583 aggregate 16<s<=32 memory reg.
4584 aggregate >32 memory memory
4585
4586
4587
4588Note #1: complex floating-point types follow the extended SPARC ABIs as
4589implemented by the Sun compiler.
4590
4591Note #2: integral vector types follow the scalar floating-point types
4592conventions to match what is implemented by the Sun VIS SDK.
4593
4900aa61 4594Note #3: floating-point vector types follow the aggregate types
45261626 4595conventions. */
1b5963f7 4596
4fb4e4b8
DE		 4597
4598/* Maximum number of int regs for args. */
4599#define SPARC_INT_ARG_MAX 6
4600/* Maximum number of fp regs for args. */
4601#define SPARC_FP_ARG_MAX 16
4602
4603#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4604
4605/* Handle the INIT_CUMULATIVE_ARGS macro.
4606 Initialize a variable CUM of type CUMULATIVE_ARGS
4607 for a call to a function whose data type is FNTYPE.
4608 For a library call, FNTYPE is 0. */
3ea1fdd3 4609
4fb4e4b8 4610void
fc27d102
KG		 4611init_cumulative_args (struct sparc_args *cum, tree fntype,
4612 rtx libname ATTRIBUTE_UNUSED,
4613 tree fndecl ATTRIBUTE_UNUSED)
4fb4e4b8
DE		 4614{
4615 cum->words = 0;
4616 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4617 cum->libcall_p = fntype == 0;
4618}
61a55e8b 4619
bd5bd7ac 4620/* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
3e2cc1d1
KH		 4621 When a prototype says `char' or `short', really pass an `int'. */
4622
4623static bool
586de218 4624sparc_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED)
3e2cc1d1
KH		 4625{
4626 return TARGET_ARCH32 ? true : false;
4627}
4628
cde0f3fd
PB		 4629/* Handle promotion of pointer and integer arguments. */
4630
4631static enum machine_mode
4632sparc_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
4633 enum machine_mode mode,
4634 int *punsignedp ATTRIBUTE_UNUSED,
4635 const_tree fntype ATTRIBUTE_UNUSED,
4636 int for_return ATTRIBUTE_UNUSED)
4637{
4638 if (POINTER_TYPE_P (type))
4639 {
4640 *punsignedp = POINTERS_EXTEND_UNSIGNED;
4641 return Pmode;
4642 }
4643
4644 /* For TARGET_ARCH64 we need this, as we don't have instructions
4645 for arithmetic operations which do zero/sign extension at the same time,
4646 so without this we end up with a srl/sra after every assignment to an
4647 user variable, which means very very bad code. */
cde0f3fd
PB		 4648 if (TARGET_ARCH64
4649 && GET_MODE_CLASS (mode) == MODE_INT
4650 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4651 return word_mode;
4652
4653 return mode;
4654}
4655
bd5bd7ac 4656/* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
3e2cc1d1
KH		 4657
4658static bool
4659sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4660{
1b5963f7 4661 return TARGET_ARCH64 ? true : false;
3e2cc1d1
KH		 4662}
4663
5c4f4b18
EB		 4664/* Scan the record type TYPE and return the following predicates:
4665 - INTREGS_P: the record contains at least one field or sub-field
4666 that is eligible for promotion in integer registers.
4667 - FP_REGS_P: the record contains at least one field or sub-field
4668 that is eligible for promotion in floating-point registers.
4669 - PACKED_P: the record contains at least one field that is packed.
4670
4671 Sub-fields are not taken into account for the PACKED_P predicate. */
4672
4673static void
a7bba6ca 4674scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5c4f4b18
EB		 4675{
4676 tree field;
4677
4678 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4679 {
4680 if (TREE_CODE (field) == FIELD_DECL)
4681 {
4682 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4683 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
45261626
EB		 4684 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4685 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
4686 && TARGET_FPU)
5c4f4b18
EB		 4687 *fpregs_p = 1;
4688 else
4689 *intregs_p = 1;
4690
4691 if (packed_p && DECL_PACKED (field))
4692 *packed_p = 1;
4693 }
4694 }
4695}
4696
4fb4e4b8 4697/* Compute the slot number to pass an argument in.
5c4f4b18 4698 Return the slot number or -1 if passing on the stack.
4fb4e4b8
DE		 4699
4700 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4701 the preceding args and about the function being called.
4702 MODE is the argument's machine mode.
4703 TYPE is the data type of the argument (as a tree).
4704 This is null for libcalls where that information may
4705 not be available.
4706 NAMED is nonzero if this argument is a named parameter
4707 (otherwise it is an extra parameter matching an ellipsis).
4708 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4709 *PREGNO records the register number to use if scalar type.
4710 *PPADDING records the amount of padding needed in words. */
4711
4712static int
fc27d102
KG		 4713function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4714 tree type, int named, int incoming_p,
4715 int *pregno, int *ppadding)
4fb4e4b8
DE		 4716{
4717 int regbase = (incoming_p
4718 ? SPARC_INCOMING_INT_ARG_FIRST
4719 : SPARC_OUTGOING_INT_ARG_FIRST);
4720 int slotno = cum->words;
45261626 4721 enum mode_class mclass;
4fb4e4b8
DE		 4722 int regno;
4723
4724 *ppadding = 0;
4725
1b5963f7 4726 if (type && TREE_ADDRESSABLE (type))
4fb4e4b8 4727 return -1;
1b5963f7 4728
4fb4e4b8 4729 if (TARGET_ARCH32
1b5963f7
EB		 4730 && mode == BLKmode
4731 && type
4fb4e4b8
DE		 4732 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4733 return -1;
4734
1b5963f7
EB		 4735 /* For SPARC64, objects requiring 16-byte alignment get it. */
4736 if (TARGET_ARCH64
7617ec02 4737 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
1b5963f7
EB		 4738 && (slotno & 1) != 0)
4739 slotno++, *ppadding = 1;
4fb4e4b8 4740
45261626
EB		 4741 mclass = GET_MODE_CLASS (mode);
4742 if (type && TREE_CODE (type) == VECTOR_TYPE)
4743 {
4744 /* Vector types deserve special treatment because they are
4745 polymorphic wrt their mode, depending upon whether VIS
4746 instructions are enabled. */
4747 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4748 {
4749 /* The SPARC port defines no floating-point vector modes. */
f5f7d171 4750 gcc_assert (mode == BLKmode);
45261626
EB		 4751 }
4752 else
4753 {
4754 /* Integral vector types should either have a vector
4755 mode or an integral mode, because we are guaranteed
4756 by pass_by_reference that their size is not greater
4757 than 16 bytes and TImode is 16-byte wide. */
f5f7d171 4758 gcc_assert (mode != BLKmode);
45261626
EB		 4759
4760 /* Vector integers are handled like floats according to
4761 the Sun VIS SDK. */
4762 mclass = MODE_FLOAT;
4763 }
4764 }
4765
4766 switch (mclass)
1b5963f7
EB		 4767 {
4768 case MODE_FLOAT:
4769 case MODE_COMPLEX_FLOAT:
0dd8c9bc 4770 case MODE_VECTOR_INT:
1b5963f7
EB		 4771 if (TARGET_ARCH64 && TARGET_FPU && named)
4772 {
4773 if (slotno >= SPARC_FP_ARG_MAX)
4774 return -1;
4775 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4776 /* Arguments filling only one single FP register are
4777 right-justified in the outer double FP register. */
4778 if (GET_MODE_SIZE (mode) <= 4)
4779 regno++;
4780 break;
4781 }
d560b0aa
EB		 4782 /* fallthrough */
4783
1b5963f7
EB		 4784 case MODE_INT:
4785 case MODE_COMPLEX_INT:
4fb4e4b8
DE		 4786 if (slotno >= SPARC_INT_ARG_MAX)
4787 return -1;
4788 regno = regbase + slotno;
4789 break;
4790
1b5963f7
EB		 4791 case MODE_RANDOM:
4792 if (mode == VOIDmode)
4793 /* MODE is VOIDmode when generating the actual call. */
4794 return -1;
d560b0aa 4795
f5f7d171 4796 gcc_assert (mode == BLKmode);
4fb4e4b8 4797
ef6843ed
EB		 4798 if (TARGET_ARCH32
4799 || !type
4800 || (TREE_CODE (type) != VECTOR_TYPE
4801 && TREE_CODE (type) != RECORD_TYPE))
4fb4e4b8
DE		 4802 {
4803 if (slotno >= SPARC_INT_ARG_MAX)
4804 return -1;
4805 regno = regbase + slotno;
4806 }
45261626 4807 else /* TARGET_ARCH64 && type */
4fb4e4b8 4808 {
5c4f4b18
EB		 4809 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
4810
4811 /* First see what kinds of registers we would need. */
45261626
EB		 4812 if (TREE_CODE (type) == VECTOR_TYPE)
4813 fpregs_p = 1;
4814 else
4815 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5c4f4b18
EB		 4816
4817 /* The ABI obviously doesn't specify how packed structures
4818 are passed. These are defined to be passed in int regs
4819 if possible, otherwise memory. */
4fb4e4b8
DE		 4820 if (packed_p || !named)
4821 fpregs_p = 0, intregs_p = 1;
4822
4823 /* If all arg slots are filled, then must pass on stack. */
4824 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4825 return -1;
1b5963f7 4826
4fb4e4b8
DE		 4827 /* If there are only int args and all int arg slots are filled,
4828 then must pass on stack. */
4829 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4830 return -1;
1b5963f7 4831
4fb4e4b8
DE		 4832 /* Note that even if all int arg slots are filled, fp members may
4833 still be passed in regs if such regs are available.
4834 *PREGNO isn't set because there may be more than one, it's up
4835 to the caller to compute them. */
4836 return slotno;
4837 }
4838 break;
4839
4840 default :
f5f7d171 4841 gcc_unreachable ();
4fb4e4b8
DE		 4842 }
4843
4844 *pregno = regno;
4845 return slotno;
4846}
4847
82d6b402
RH		 4848/* Handle recursive register counting for structure field layout. */
4849
4850struct function_arg_record_value_parms
4851{
48028e21
EB		 4852 rtx ret; /* return expression being built. */
4853 int slotno; /* slot number of the argument. */
4854 int named; /* whether the argument is named. */
4855 int regbase; /* regno of the base register. */
4856 int stack; /* 1 if part of the argument is on the stack. */
1fd05073 4857 int intoffset; /* offset of the first pending integer field. */
48028e21 4858 unsigned int nregs; /* number of words passed in registers. */
82d6b402
RH		 4859};
4860
2a01c939 4861static void function_arg_record_value_3
e80d5f80 4862 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
2a01c939 4863static void function_arg_record_value_2
586de218 4864 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
b1474bb7 4865static void function_arg_record_value_1
586de218
KG		 4866 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4867static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
22d8d627 4868static rtx function_arg_union_value (int, enum machine_mode, int, int);
2a01c939 4869
0020b823 4870/* A subroutine of function_arg_record_value. Traverse the structure
fae778eb 4871 recursively and determine how many registers will be required. */
0020b823 4872
82d6b402 4873static void
586de218 4874function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
cde85594
EB		 4875 struct function_arg_record_value_parms *parms,
4876 bool packed_p)
82d6b402
RH		 4877{
4878 tree field;
4879
82d6b402
RH		 4880 /* We need to compute how many registers are needed so we can
4881 allocate the PARALLEL but before we can do that we need to know
cde85594
EB		 4882 whether there are any packed fields. The ABI obviously doesn't
4883 specify how structures are passed in this case, so they are
4884 defined to be passed in int regs if possible, otherwise memory,
4885 regardless of whether there are fp values present. */
4886
4887 if (! packed_p)
4888 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4889 {
4890 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4891 {
4892 packed_p = true;
4893 break;
4894 }
4895 }
82d6b402
RH		 4896
4897 /* Compute how many registers we need. */
4898 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4899 {
4900 if (TREE_CODE (field) == FIELD_DECL)
4901 {
75131237
RK		 4902 HOST_WIDE_INT bitpos = startbitpos;
4903
bb05e341
EB		 4904 if (DECL_SIZE (field) != 0)
4905 {
4906 if (integer_zerop (DECL_SIZE (field)))
4907 continue;
4908
4909 if (host_integerp (bit_position (field), 1))
4910 bitpos += int_bit_position (field);
4911 }
75131237 4912
82d6b402
RH		 4913 /* ??? FIXME: else assume zero offset. */
4914
4915 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
cde85594
EB		 4916 function_arg_record_value_1 (TREE_TYPE (field),
4917 bitpos,
4918 parms,
4919 packed_p);
1b5963f7
EB		 4920 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4921 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8a98812c
EB		 4922 && TARGET_FPU
4923 && parms->named
4924 && ! packed_p)
82d6b402
RH		 4925 {
4926 if (parms->intoffset != -1)
4927 {
b2f24c85 4928 unsigned int startbit, endbit;
82d6b402
RH		 4929 int intslots, this_slotno;
4930
b2f24c85
EB		 4931 startbit = parms->intoffset & -BITS_PER_WORD;
4932 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4933
4934 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 4935 this_slotno = parms->slotno + parms->intoffset
4936 / BITS_PER_WORD;
4937
48028e21
EB		 4938 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4939 {
4940 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4941 /* We need to pass this field on the stack. */
4942 parms->stack = 1;
4943 }
4944
82d6b402
RH		 4945 parms->nregs += intslots;
4946 parms->intoffset = -1;
4947 }
4948
4949 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4950 If it wasn't true we wouldn't be here. */
45261626
EB		 4951 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
4952 && DECL_MODE (field) == BLKmode)
4953 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
4954 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4955 parms->nregs += 2;
4956 else
105b2084 4957 parms->nregs += 1;
82d6b402
RH		 4958 }
4959 else
4960 {
4961 if (parms->intoffset == -1)
4962 parms->intoffset = bitpos;
4963 }
4964 }
4965 }
4966}
4967
0020b823
RH		 4968/* A subroutine of function_arg_record_value. Assign the bits of the
4969 structure between parms->intoffset and bitpos to integer registers. */
82d6b402 4970
4900aa61 4971static void
fc27d102
KG		 4972function_arg_record_value_3 (HOST_WIDE_INT bitpos,
4973 struct function_arg_record_value_parms *parms)
82d6b402
RH		 4974{
4975 enum machine_mode mode;
75131237 4976 unsigned int regno;
0020b823 4977 unsigned int startbit, endbit;
75131237 4978 int this_slotno, intslots, intoffset;
82d6b402
RH		 4979 rtx reg;
4980
4981 if (parms->intoffset == -1)
4982 return;
75131237 4983
82d6b402
RH		 4984 intoffset = parms->intoffset;
4985 parms->intoffset = -1;
4986
0020b823
RH		 4987 startbit = intoffset & -BITS_PER_WORD;
4988 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4989 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 4990 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4991
4992 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4993 if (intslots <= 0)
4994 return;
4995
4996 /* If this is the trailing part of a word, only load that much into
4997 the register. Otherwise load the whole register. Note that in
4998 the latter case we may pick up unwanted bits. It's not a problem
4999 at the moment but may wish to revisit. */
5000
5001 if (intoffset % BITS_PER_WORD != 0)
bb05e341
EB		 5002 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5003 MODE_INT);
82d6b402
RH		 5004 else
5005 mode = word_mode;
5006
5007 intoffset /= BITS_PER_UNIT;
5008 do
5009 {
5010 regno = parms->regbase + this_slotno;
254110c2 5011 reg = gen_rtx_REG (mode, regno);
48028e21 5012 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
254110c2 5013 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
82d6b402
RH		 5014
5015 this_slotno += 1;
5016 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
1fd05073 5017 mode = word_mode;
82d6b402
RH		 5018 parms->nregs += 1;
5019 intslots -= 1;
5020 }
5021 while (intslots > 0);
5022}
5023
0020b823
RH		 5024/* A subroutine of function_arg_record_value. Traverse the structure
5025 recursively and assign bits to floating point registers. Track which
5026 bits in between need integer registers; invoke function_arg_record_value_3
5027 to make that happen. */
5028
82d6b402 5029static void
586de218 5030function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
cde85594
EB		 5031 struct function_arg_record_value_parms *parms,
5032 bool packed_p)
82d6b402
RH		 5033{
5034 tree field;
82d6b402 5035
cde85594
EB		 5036 if (! packed_p)
5037 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5038 {
5039 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5040 {
5041 packed_p = true;
5042 break;
5043 }
5044 }
82d6b402
RH		 5045
5046 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5047 {
5048 if (TREE_CODE (field) == FIELD_DECL)
5049 {
75131237
RK		 5050 HOST_WIDE_INT bitpos = startbitpos;
5051
bb05e341
EB		 5052 if (DECL_SIZE (field) != 0)
5053 {
5054 if (integer_zerop (DECL_SIZE (field)))
5055 continue;
5056
5057 if (host_integerp (bit_position (field), 1))
5058 bitpos += int_bit_position (field);
5059 }
75131237 5060
82d6b402
RH		 5061 /* ??? FIXME: else assume zero offset. */
5062
5063 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
cde85594
EB		 5064 function_arg_record_value_2 (TREE_TYPE (field),
5065 bitpos,
5066 parms,
5067 packed_p);
1b5963f7
EB		 5068 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5069 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8a98812c
EB		 5070 && TARGET_FPU
5071 && parms->named
5072 && ! packed_p)
82d6b402
RH		 5073 {
5074 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
45261626 5075 int regno, nregs, pos;
105b2084 5076 enum machine_mode mode = DECL_MODE (field);
82d6b402
RH		 5077 rtx reg;
5078
5079 function_arg_record_value_3 (bitpos, parms);
45261626
EB		 5080
5081 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5082 && mode == BLKmode)
5083 {
5084 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5085 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
105b2084 5086 }
45261626
EB		 5087 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5088 {
5089 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5090 nregs = 2;
5091 }
5092 else
5093 nregs = 1;
5094
1b5963f7
EB		 5095 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5096 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5097 regno++;
105b2084 5098 reg = gen_rtx_REG (mode, regno);
45261626 5099 pos = bitpos / BITS_PER_UNIT;
48028e21 5100 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
45261626 5101 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
82d6b402 5102 parms->nregs += 1;
45261626 5103 while (--nregs > 0)
105b2084
JJ		 5104 {
5105 regno += GET_MODE_SIZE (mode) / 4;
5106 reg = gen_rtx_REG (mode, regno);
45261626 5107 pos += GET_MODE_SIZE (mode);
48028e21 5108 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
45261626 5109 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
105b2084
JJ		 5110 parms->nregs += 1;
5111 }
82d6b402
RH		 5112 }
5113 else
5114 {
5115 if (parms->intoffset == -1)
5116 parms->intoffset = bitpos;
5117 }
5118 }
5119 }
5120}
5121
0020b823 5122/* Used by function_arg and function_value to implement the complex
48028e21
EB		 5123 conventions of the 64-bit ABI for passing and returning structures.
5124 Return an expression valid as a return value for the two macros
5125 FUNCTION_ARG and FUNCTION_VALUE.
0020b823 5126
48028e21
EB		 5127 TYPE is the data type of the argument (as a tree).
5128 This is null for libcalls where that information may
5129 not be available.
5130 MODE is the argument's machine mode.
5131 SLOTNO is the index number of the argument's slot in the parameter array.
5132 NAMED is nonzero if this argument is a named parameter
5133 (otherwise it is an extra parameter matching an ellipsis).
5134 REGBASE is the regno of the base register for the parameter array. */
4900aa61 5135
82d6b402 5136static rtx
586de218 5137function_arg_record_value (const_tree type, enum machine_mode mode,
fc27d102 5138 int slotno, int named, int regbase)
82d6b402
RH		 5139{
5140 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5141 struct function_arg_record_value_parms parms;
75131237 5142 unsigned int nregs;
82d6b402
RH		 5143
5144 parms.ret = NULL_RTX;
5145 parms.slotno = slotno;
5146 parms.named = named;
5147 parms.regbase = regbase;
48028e21 5148 parms.stack = 0;
82d6b402
RH		 5149
5150 /* Compute how many registers we need. */
5151 parms.nregs = 0;
5152 parms.intoffset = 0;
cde85594 5153 function_arg_record_value_1 (type, 0, &parms, false);
82d6b402 5154
1fd05073 5155 /* Take into account pending integer fields. */
82d6b402
RH		 5156 if (parms.intoffset != -1)
5157 {
0020b823 5158 unsigned int startbit, endbit;
82d6b402
RH		 5159 int intslots, this_slotno;
5160
0020b823
RH		 5161 startbit = parms.intoffset & -BITS_PER_WORD;
5162 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5163 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 5164 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5165
48028e21
EB		 5166 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5167 {
5168 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5169 /* We need to pass this field on the stack. */
5170 parms.stack = 1;
5171 }
82d6b402
RH		 5172
5173 parms.nregs += intslots;
5174 }
5175 nregs = parms.nregs;
5176
5177 /* Allocate the vector and handle some annoying special cases. */
5178 if (nregs == 0)
5179 {
5180 /* ??? Empty structure has no value? Duh? */
5181 if (typesize <= 0)
5182 {
5183 /* Though there's nothing really to store, return a word register
5184 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5185 leads to breakage due to the fact that there are zero bytes to
5186 load. */
1eac9f59 5187 return gen_rtx_REG (mode, regbase);
82d6b402
RH		 5188 }
5189 else
5190 {
5191 /* ??? C++ has structures with no fields, and yet a size. Give up
5192 for now and pass everything back in integer registers. */
5193 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5194 }
5195 if (nregs + slotno > SPARC_INT_ARG_MAX)
5196 nregs = SPARC_INT_ARG_MAX - slotno;
5197 }
f5f7d171 5198 gcc_assert (nregs != 0);
82d6b402 5199
48028e21
EB		 5200 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5201
5202 /* If at least one field must be passed on the stack, generate
5203 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5204 also be passed on the stack. We can't do much better because the
78a52f11 5205 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
48028e21
EB		 5206 of structures for which the fields passed exclusively in registers
5207 are not at the beginning of the structure. */
5208 if (parms.stack)
5209 XVECEXP (parms.ret, 0, 0)
5210 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
82d6b402
RH		 5211
5212 /* Fill in the entries. */
5213 parms.nregs = 0;
5214 parms.intoffset = 0;
cde85594 5215 function_arg_record_value_2 (type, 0, &parms, false);
82d6b402
RH		 5216 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5217
f5f7d171 5218 gcc_assert (parms.nregs == nregs);
82d6b402
RH		 5219
5220 return parms.ret;
5221}
5222
a7bba6ca
EB		 5223/* Used by function_arg and function_value to implement the conventions
5224 of the 64-bit ABI for passing and returning unions.
5225 Return an expression valid as a return value for the two macros
5226 FUNCTION_ARG and FUNCTION_VALUE.
5227
5228 SIZE is the size in bytes of the union.
85bbb21f 5229 MODE is the argument's machine mode.
a7bba6ca
EB		 5230 REGNO is the hard register the union will be passed in. */
5231
5232static rtx
22d8d627
EB		 5233function_arg_union_value (int size, enum machine_mode mode, int slotno,
5234 int regno)
a7bba6ca 5235{
85bbb21f
EB		 5236 int nwords = ROUND_ADVANCE (size), i;
5237 rtx regs;
a7bba6ca 5238
bb05e341
EB		 5239 /* See comment in previous function for empty structures. */
5240 if (nwords == 0)
5241 return gen_rtx_REG (mode, regno);
5242
22d8d627
EB		 5243 if (slotno == SPARC_INT_ARG_MAX - 1)
5244 nwords = 1;
5245
85bbb21f 5246 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
a7bba6ca 5247
85bbb21f 5248 for (i = 0; i < nwords; i++)
45261626
EB		 5249 {
5250 /* Unions are passed left-justified. */
5251 XVECEXP (regs, 0, i)
5252 = gen_rtx_EXPR_LIST (VOIDmode,
5253 gen_rtx_REG (word_mode, regno),
5254 GEN_INT (UNITS_PER_WORD * i));
5255 regno++;
5256 }
5257
5258 return regs;
5259}
5260
5261/* Used by function_arg and function_value to implement the conventions
5262 for passing and returning large (BLKmode) vectors.
5263 Return an expression valid as a return value for the two macros
5264 FUNCTION_ARG and FUNCTION_VALUE.
5265
26237a50 5266 SIZE is the size in bytes of the vector (at least 8 bytes).
45261626
EB		 5267 REGNO is the FP hard register the vector will be passed in. */
5268
5269static rtx
26237a50 5270function_arg_vector_value (int size, int regno)
45261626 5271{
26237a50 5272 int i, nregs = size / 8;
45261626
EB		 5273 rtx regs;
5274
5275 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
5276
5277 for (i = 0; i < nregs; i++)
5278 {
5279 XVECEXP (regs, 0, i)
5280 = gen_rtx_EXPR_LIST (VOIDmode,
26237a50
EB		 5281 gen_rtx_REG (DImode, regno + 2*i),
5282 GEN_INT (i*8));
45261626 5283 }
a7bba6ca 5284
85bbb21f 5285 return regs;
a7bba6ca
EB		 5286}
5287
4fb4e4b8
DE		 5288/* Handle the FUNCTION_ARG macro.
5289 Determine where to put an argument to a function.
5290 Value is zero to push the argument on the stack,
5291 or a hard register in which to store the argument.
5292
5293 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5294 the preceding args and about the function being called.
5295 MODE is the argument's machine mode.
5296 TYPE is the data type of the argument (as a tree).
5297 This is null for libcalls where that information may
5298 not be available.
5299 NAMED is nonzero if this argument is a named parameter
5300 (otherwise it is an extra parameter matching an ellipsis).
5301 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
61a55e8b
DE		 5302
5303rtx
fc27d102
KG		 5304function_arg (const struct sparc_args *cum, enum machine_mode mode,
5305 tree type, int named, int incoming_p)
61a55e8b 5306{
4fb4e4b8
DE		 5307 int regbase = (incoming_p
5308 ? SPARC_INCOMING_INT_ARG_FIRST
5309 : SPARC_OUTGOING_INT_ARG_FIRST);
5310 int slotno, regno, padding;
45261626 5311 enum mode_class mclass = GET_MODE_CLASS (mode);
4fb4e4b8
DE		 5312
5313 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5314 &regno, &padding);
4fb4e4b8
DE		 5315 if (slotno == -1)
5316 return 0;
5317
ef6843ed
EB		 5318 /* Vector types deserve special treatment because they are polymorphic wrt
5319 their mode, depending upon whether VIS instructions are enabled. */
5320 if (type && TREE_CODE (type) == VECTOR_TYPE)
4fb4e4b8 5321 {
ef6843ed
EB		 5322 HOST_WIDE_INT size = int_size_in_bytes (type);
5323 gcc_assert ((TARGET_ARCH32 && size <= 8)
5324 || (TARGET_ARCH64 && size <= 16));
5325
5326 if (mode == BLKmode)
5327 return function_arg_vector_value (size,
ef6843ed
EB		 5328 SPARC_FP_ARG_FIRST + 2*slotno);
5329 else
5330 mclass = MODE_FLOAT;
4fb4e4b8 5331 }
4043d6fb 5332
ef6843ed
EB		 5333 if (TARGET_ARCH32)
5334 return gen_rtx_REG (mode, regno);
4043d6fb 5335
ef6843ed
EB		 5336 /* Structures up to 16 bytes in size are passed in arg slots on the stack
5337 and are promoted to registers if possible. */
5338 if (type && TREE_CODE (type) == RECORD_TYPE)
4043d6fb 5339 {
a7bba6ca 5340 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 5341 gcc_assert (size <= 16);
4fb4e4b8 5342
ef6843ed 5343 return function_arg_record_value (type, mode, slotno, named, regbase);
4043d6fb 5344 }
ef6843ed
EB		 5345
5346 /* Unions up to 16 bytes in size are passed in integer registers. */
5347 else if (type && TREE_CODE (type) == UNION_TYPE)
45261626 5348 {
45261626 5349 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 5350 gcc_assert (size <= 16);
45261626 5351
ef6843ed 5352 return function_arg_union_value (size, mode, slotno, regno);
45261626
EB		 5353 }
5354
4fb4e4b8
DE		 5355 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5356 but also have the slot allocated for them.
5357 If no prototype is in scope fp values in register slots get passed
5358 in two places, either fp regs and int regs or fp regs and memory. */
ef6843ed
EB		 5359 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5360 && SPARC_FP_REG_P (regno))
4fb4e4b8 5361 {
ef6843ed 5362 rtx reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 5363 if (cum->prototype_p || cum->libcall_p)
5364 {
5365 /* "* 2" because fp reg numbers are recorded in 4 byte
5366 quantities. */
82d6b402 5367#if 0
4fb4e4b8
DE		 5368 /* ??? This will cause the value to be passed in the fp reg and
5369 in the stack. When a prototype exists we want to pass the
5370 value in the reg but reserve space on the stack. That's an
956d6950 5371 optimization, and is deferred [for a bit]. */
4fb4e4b8 5372 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
254110c2 5373 return gen_rtx_PARALLEL (mode,
4fb4e4b8 5374 gen_rtvec (2,
254110c2 5375 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8 5376 NULL_RTX, const0_rtx),
254110c2 5377 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8
DE		 5378 reg, const0_rtx)));
5379 else
82d6b402
RH		 5380#else
5381 /* ??? It seems that passing back a register even when past
5382 the area declared by REG_PARM_STACK_SPACE will allocate
5383 space appropriately, and will not copy the data onto the
5384 stack, exactly as we desire.
5385
5386 This is due to locate_and_pad_parm being called in
5387 expand_call whenever reg_parm_stack_space > 0, which
fae778eb 5388 while beneficial to our example here, would seem to be
82d6b402
RH		 5389 in error from what had been intended. Ho hum... -- r~ */
5390#endif
4fb4e4b8
DE		 5391 return reg;
5392 }
5393 else
5394 {
82d6b402
RH		 5395 rtx v0, v1;
5396
4fb4e4b8
DE		 5397 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5398 {
82d6b402
RH		 5399 int intreg;
5400
5401 /* On incoming, we don't need to know that the value
5402 is passed in %f0 and %i0, and it confuses other parts
5403 causing needless spillage even on the simplest cases. */
5404 if (incoming_p)
5405 return reg;
5406
5407 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5408 + (regno - SPARC_FP_ARG_FIRST) / 2);
5409
5410 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5411 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5412 const0_rtx);
5413 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4fb4e4b8
DE		 5414 }
5415 else
82d6b402
RH		 5416 {
5417 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5418 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5419 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5420 }
4fb4e4b8
DE		 5421 }
5422 }
ef6843ed
EB		 5423
5424 /* All other aggregate types are passed in an integer register in a mode
5425 corresponding to the size of the type. */
5426 else if (type && AGGREGATE_TYPE_P (type))
4fb4e4b8 5427 {
ef6843ed
EB		 5428 HOST_WIDE_INT size = int_size_in_bytes (type);
5429 gcc_assert (size <= 16);
5430
5431 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4fb4e4b8
DE		 5432 }
5433
ef6843ed 5434 return gen_rtx_REG (mode, regno);
4fb4e4b8 5435}
a7acd911 5436
78a52f11
RH		 5437/* For an arg passed partly in registers and partly in memory,
5438 this is the number of bytes of registers used.
4fb4e4b8 5439 For args passed entirely in registers or entirely in memory, zero.
61a55e8b 5440
4fb4e4b8
DE		 5441 Any arg that starts in the first 6 regs but won't entirely fit in them
5442 needs partial registers on v8. On v9, structures with integer
5443 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5444 values that begin in the last fp reg [where "last fp reg" varies with the
5445 mode] will be split between that reg and memory. */
61a55e8b 5446
78a52f11
RH		 5447static int
5448sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5449 tree type, bool named)
4fb4e4b8
DE		 5450{
5451 int slotno, regno, padding;
61a55e8b 5452
4fb4e4b8
DE		 5453 /* We pass 0 for incoming_p here, it doesn't matter. */
5454 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5455
5456 if (slotno == -1)
5457 return 0;
5458
5459 if (TARGET_ARCH32)
bf62bbf1 5460 {
4fb4e4b8
DE		 5461 if ((slotno + (mode == BLKmode
5462 ? ROUND_ADVANCE (int_size_in_bytes (type))
5463 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
1b5963f7 5464 > SPARC_INT_ARG_MAX)
78a52f11 5465 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
4fb4e4b8
DE		 5466 }
5467 else
5468 {
8cd5a4e0 5469 /* We are guaranteed by pass_by_reference that the size of the
78a52f11
RH		 5470 argument is not greater than 16 bytes, so we only need to return
5471 one word if the argument is partially passed in registers. */
1b5963f7 5472
4fb4e4b8
DE		 5473 if (type && AGGREGATE_TYPE_P (type))
5474 {
5475 int size = int_size_in_bytes (type);
bf62bbf1 5476
1b5963f7 5477 if (size > UNITS_PER_WORD
4fb4e4b8 5478 && slotno == SPARC_INT_ARG_MAX - 1)
78a52f11 5479 return UNITS_PER_WORD;
4fb4e4b8 5480 }
0a9e65f9 5481 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4fb4e4b8 5482 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
c3427c7d 5483 && ! (TARGET_FPU && named)))
4fb4e4b8 5484 {
0a9e65f9 5485 /* The complex types are passed as packed types. */
1b5963f7
EB		 5486 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5487 && slotno == SPARC_INT_ARG_MAX - 1)
78a52f11 5488 return UNITS_PER_WORD;
4fb4e4b8
DE		 5489 }
5490 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5491 {
4fb4e4b8
DE		 5492 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5493 > SPARC_FP_ARG_MAX)
78a52f11 5494 return UNITS_PER_WORD;
4fb4e4b8 5495 }
bf62bbf1 5496 }
1b5963f7
EB		 5497
5498 return 0;
4fb4e4b8 5499}
61a55e8b 5500
45261626
EB		 5501/* Handle the TARGET_PASS_BY_REFERENCE target hook.
5502 Specify whether to pass the argument by reference. */
4fb4e4b8 5503
8cd5a4e0
RH		 5504static bool
5505sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
586de218 5506 enum machine_mode mode, const_tree type,
8cd5a4e0 5507 bool named ATTRIBUTE_UNUSED)
4fb4e4b8
DE		 5508{
5509 if (TARGET_ARCH32)
45261626
EB		 5510 /* Original SPARC 32-bit ABI says that structures and unions,
5511 and quad-precision floats are passed by reference. For Pascal,
5512 also pass arrays by reference. All other base types are passed
5513 in registers.
5514
5515 Extended ABI (as implemented by the Sun compiler) says that all
5516 complex floats are passed by reference. Pass complex integers
5517 in registers up to 8 bytes. More generally, enforce the 2-word
5518 cap for passing arguments in registers.
5519
5520 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5521 integers are passed like floats of the same size, that is in
5522 registers up to 8 bytes. Pass all vector floats by reference
5523 like structure and unions. */
ef6843ed
EB		 5524 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
5525 || mode == SCmode
5526 /* Catch CDImode, TFmode, DCmode and TCmode. */
5527 || GET_MODE_SIZE (mode) > 8
5528 || (type
5529 && TREE_CODE (type) == VECTOR_TYPE
5530 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
4fb4e4b8 5531 else
45261626
EB		 5532 /* Original SPARC 64-bit ABI says that structures and unions
5533 smaller than 16 bytes are passed in registers, as well as
ef6843ed 5534 all other base types.
4900aa61 5535
45261626
EB		 5536 Extended ABI (as implemented by the Sun compiler) says that
5537 complex floats are passed in registers up to 16 bytes. Pass
5538 all complex integers in registers up to 16 bytes. More generally,
5539 enforce the 2-word cap for passing arguments in registers.
5540
5541 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5542 integers are passed like floats of the same size, that is in
5543 registers (up to 16 bytes). Pass all vector floats like structure
5544 and unions. */
ef6843ed
EB		 5545 return ((type
5546 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
5547 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5548 /* Catch CTImode and TCmode. */
5549 || GET_MODE_SIZE (mode) > 16);
4fb4e4b8
DE		 5550}
5551
5552/* Handle the FUNCTION_ARG_ADVANCE macro.
5553 Update the data in CUM to advance over an argument
5554 of mode MODE and data type TYPE.
5555 TYPE is null for libcalls where that information may not be available. */
5556
5557void
fc27d102
KG		 5558function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5559 tree type, int named)
4fb4e4b8
DE		 5560{
5561 int slotno, regno, padding;
5562
5563 /* We pass 0 for incoming_p here, it doesn't matter. */
5564 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5565
5566 /* If register required leading padding, add it. */
5567 if (slotno != -1)
5568 cum->words += padding;
eadceb59 5569
4fb4e4b8
DE		 5570 if (TARGET_ARCH32)
5571 {
5572 cum->words += (mode != BLKmode
5573 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5574 : ROUND_ADVANCE (int_size_in_bytes (type)));
5575 }
5576 else
5577 {
5578 if (type && AGGREGATE_TYPE_P (type))
5579 {
5580 int size = int_size_in_bytes (type);
5581
5582 if (size <= 8)
5583 ++cum->words;
5584 else if (size <= 16)
5585 cum->words += 2;
5586 else /* passed by reference */
5587 ++cum->words;
5588 }
4fb4e4b8
DE		 5589 else
5590 {
5591 cum->words += (mode != BLKmode
5592 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5593 : ROUND_ADVANCE (int_size_in_bytes (type)));
5594 }
eadceb59 5595 }
4fb4e4b8 5596}
eadceb59 5597
4fb4e4b8
DE		 5598/* Handle the FUNCTION_ARG_PADDING macro.
5599 For the 64 bit ABI structs are always stored left shifted in their
5600 argument slot. */
5601
5602enum direction
586de218 5603function_arg_padding (enum machine_mode mode, const_tree type)
4fb4e4b8 5604{
c85f7c16
JL		 5605 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5606 return upward;
61a55e8b 5607
d3704c46
KH		 5608 /* Fall back to the default. */
5609 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
61a55e8b 5610}
82d6b402 5611
1b5963f7
EB		 5612/* Handle the TARGET_RETURN_IN_MEMORY target hook.
5613 Specify whether to return the return value in memory. */
5614
5615static bool
586de218 5616sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1b5963f7
EB		 5617{
5618 if (TARGET_ARCH32)
45261626
EB		 5619 /* Original SPARC 32-bit ABI says that structures and unions,
5620 and quad-precision floats are returned in memory. All other
5621 base types are returned in registers.
5622
5623 Extended ABI (as implemented by the Sun compiler) says that
5624 all complex floats are returned in registers (8 FP registers
5625 at most for '_Complex long double'). Return all complex integers
5626 in registers (4 at most for '_Complex long long').
5627
5628 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5629 integers are returned like floats of the same size, that is in
5630 registers up to 8 bytes and in memory otherwise. Return all
5631 vector floats in memory like structure and unions; note that
5632 they always have BLKmode like the latter. */
1b5963f7
EB		 5633 return (TYPE_MODE (type) == BLKmode
5634 || TYPE_MODE (type) == TFmode
45261626
EB		 5635 || (TREE_CODE (type) == VECTOR_TYPE
5636 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
1b5963f7
EB		 5637 else
5638 /* Original SPARC 64-bit ABI says that structures and unions
45261626
EB		 5639 smaller than 32 bytes are returned in registers, as well as
5640 all other base types.
4900aa61 5641
45261626
EB		 5642 Extended ABI (as implemented by the Sun compiler) says that all
5643 complex floats are returned in registers (8 FP registers at most
5644 for '_Complex long double'). Return all complex integers in
5645 registers (4 at most for '_Complex TItype').
5646
5647 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5648 integers are returned like floats of the same size, that is in
5649 registers. Return all vector floats like structure and unions;
5650 note that they always have BLKmode like the latter. */
1b5963f7 5651 return ((TYPE_MODE (type) == BLKmode
45261626 5652 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32));
1b5963f7
EB		 5653}
5654
5655/* Handle the TARGET_STRUCT_VALUE target hook.
5656 Return where to find the structure return value address. */
5657
5658static rtx
2225b57c 5659sparc_struct_value_rtx (tree fndecl, int incoming)
1b5963f7
EB		 5660{
5661 if (TARGET_ARCH64)
5662 return 0;
5663 else
5664 {
1da4c3a7
EB		 5665 rtx mem;
5666
1b5963f7 5667 if (incoming)
1da4c3a7
EB		 5668 mem = gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5669 STRUCT_VALUE_OFFSET));
1b5963f7 5670 else
1da4c3a7
EB		 5671 mem = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5672 STRUCT_VALUE_OFFSET));
5673
4900aa61
EB		 5674 /* Only follow the SPARC ABI for fixed-size structure returns.
5675 Variable size structure returns are handled per the normal
2225b57c 5676 procedures in GCC. This is enabled by -mstd-struct-return */
4900aa61 5677 if (incoming == 2
2225b57c
CD		 5678 && sparc_std_struct_return
5679 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
5680 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
5681 {
5682 /* We must check and adjust the return address, as it is
5683 optional as to whether the return object is really
5684 provided. */
5685 rtx ret_rtx = gen_rtx_REG (Pmode, 31);
5686 rtx scratch = gen_reg_rtx (SImode);
4900aa61 5687 rtx endlab = gen_label_rtx ();
2225b57c
CD		 5688
5689 /* Calculate the return object size */
5690 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
5691 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
5692 /* Construct a temporary return value */
5693 rtx temp_val = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
5694
5695 /* Implement SPARC 32-bit psABI callee returns struck checking
4900aa61
EB		 5696 requirements:
5697
2225b57c
CD		 5698 Fetch the instruction where we will return to and see if
5699 it's an unimp instruction (the most significant 10 bits
5700 will be zero). */
5701 emit_move_insn (scratch, gen_rtx_MEM (SImode,
5702 plus_constant (ret_rtx, 8)));
5703 /* Assume the size is valid and pre-adjust */
5704 emit_insn (gen_add3_insn (ret_rtx, ret_rtx, GEN_INT (4)));
5705 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode, 0, endlab);
5706 emit_insn (gen_sub3_insn (ret_rtx, ret_rtx, GEN_INT (4)));
4900aa61 5707 /* Assign stack temp:
2225b57c
CD		 5708 Write the address of the memory pointed to by temp_val into
5709 the memory pointed to by mem */
5710 emit_move_insn (mem, XEXP (temp_val, 0));
5711 emit_label (endlab);
5712 }
5713
1da4c3a7
EB		 5714 set_mem_alias_set (mem, struct_value_alias_set);
5715 return mem;
1b5963f7
EB		 5716 }
5717}
5718
82d6b402
RH		 5719/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5720 For v9, function return values are subject to the same rules as arguments,
1b5963f7 5721 except that up to 32 bytes may be returned in registers. */
82d6b402
RH		 5722
5723rtx
586de218 5724function_value (const_tree type, enum machine_mode mode, int incoming_p)
82d6b402 5725{
1b5963f7
EB		 5726 /* Beware that the two values are swapped here wrt function_arg. */
5727 int regbase = (incoming_p
5728 ? SPARC_OUTGOING_INT_ARG_FIRST
5729 : SPARC_INCOMING_INT_ARG_FIRST);
45261626 5730 enum mode_class mclass = GET_MODE_CLASS (mode);
82d6b402 5731 int regno;
82d6b402 5732
ef6843ed
EB		 5733 /* Vector types deserve special treatment because they are polymorphic wrt
5734 their mode, depending upon whether VIS instructions are enabled. */
45261626
EB		 5735 if (type && TREE_CODE (type) == VECTOR_TYPE)
5736 {
45261626 5737 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171
JM		 5738 gcc_assert ((TARGET_ARCH32 && size <= 8)
5739 || (TARGET_ARCH64 && size <= 32));
45261626
EB		 5740
5741 if (mode == BLKmode)
5742 return function_arg_vector_value (size,
45261626
EB		 5743 SPARC_FP_ARG_FIRST);
5744 else
5745 mclass = MODE_FLOAT;
5746 }
ef6843ed
EB		 5747
5748 if (TARGET_ARCH64 && type)
82d6b402 5749 {
ef6843ed 5750 /* Structures up to 32 bytes in size are returned in registers. */
82d6b402
RH		 5751 if (TREE_CODE (type) == RECORD_TYPE)
5752 {
ef6843ed
EB		 5753 HOST_WIDE_INT size = int_size_in_bytes (type);
5754 gcc_assert (size <= 32);
82d6b402 5755
1eac9f59 5756 return function_arg_record_value (type, mode, 0, 1, regbase);
82d6b402 5757 }
ef6843ed
EB		 5758
5759 /* Unions up to 32 bytes in size are returned in integer registers. */
a7bba6ca
EB		 5760 else if (TREE_CODE (type) == UNION_TYPE)
5761 {
5762 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 5763 gcc_assert (size <= 32);
a7bba6ca 5764
22d8d627 5765 return function_arg_union_value (size, mode, 0, regbase);
a7bba6ca 5766 }
ef6843ed
EB		 5767
5768 /* Objects that require it are returned in FP registers. */
5769 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5770 ;
5771
5772 /* All other aggregate types are returned in an integer register in a
5773 mode corresponding to the size of the type. */
8a7199ad 5774 else if (AGGREGATE_TYPE_P (type))
82d6b402 5775 {
8a7199ad
RK		 5776 /* All other aggregate types are passed in an integer register
5777 in a mode corresponding to the size of the type. */
ef6843ed
EB		 5778 HOST_WIDE_INT size = int_size_in_bytes (type);
5779 gcc_assert (size <= 32);
82d6b402 5780
ef6843ed 5781 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
c74fd3f1
EB		 5782
5783 /* ??? We probably should have made the same ABI change in
5784 3.4.0 as the one we made for unions. The latter was
5785 required by the SCD though, while the former is not
5786 specified, so we favored compatibility and efficiency.
5787
5788 Now we're stuck for aggregates larger than 16 bytes,
5789 because OImode vanished in the meantime. Let's not
5790 try to be unduly clever, and simply follow the ABI
5791 for unions in that case. */
5792 if (mode == BLKmode)
ef6843ed 5793 return function_arg_union_value (size, mode, 0, regbase);
45261626
EB		 5794 else
5795 mclass = MODE_INT;
82d6b402 5796 }
ef6843ed 5797
cde0f3fd
PB		 5798 /* This must match sparc_promote_function_mode.
5799 ??? Maybe 32-bit pointers should actually remain in Pmode? */
ef6843ed 5800 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
a7bba6ca 5801 mode = word_mode;
82d6b402
RH		 5802 }
5803
ef6843ed 5804 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
1b5963f7 5805 regno = SPARC_FP_ARG_FIRST;
82d6b402 5806 else
1b5963f7 5807 regno = regbase;
82d6b402 5808
254110c2 5809 return gen_rtx_REG (mode, regno);
82d6b402
RH		 5810}
5811
648d2ffc
RH		 5812/* Do what is necessary for `va_start'. We look at the current function
5813 to determine if stdarg or varargs is used and return the address of
5814 the first unnamed parameter. */
3ea1fdd3 5815
3e2cc1d1 5816static rtx
fc27d102 5817sparc_builtin_saveregs (void)
3ea1fdd3 5818{
38173d38 5819 int first_reg = crtl->args.info.words;
3ea1fdd3
JW		 5820 rtx address;
5821 int regno;
5822
1b5963f7 5823 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
254110c2 5824 emit_move_insn (gen_rtx_MEM (word_mode,
8ac61af7
RK		 5825 gen_rtx_PLUS (Pmode,
5826 frame_pointer_rtx,
563c12b0 5827 GEN_INT (FIRST_PARM_OFFSET (0)
8ac61af7
RK		 5828 + (UNITS_PER_WORD
5829 * regno)))),
254110c2 5830 gen_rtx_REG (word_mode,
1b5963f7 5831 SPARC_INCOMING_INT_ARG_FIRST + regno));
3ea1fdd3 5832
254110c2 5833 address = gen_rtx_PLUS (Pmode,
8ac61af7 5834 frame_pointer_rtx,
563c12b0 5835 GEN_INT (FIRST_PARM_OFFSET (0)
8ac61af7 5836 + UNITS_PER_WORD * first_reg));
3ea1fdd3
JW		 5837
5838 return address;
5839}
a8b2c8a1 5840
1b5963f7 5841/* Implement `va_start' for stdarg. */
a8b2c8a1 5842
d7bd8aeb 5843static void
fc27d102 5844sparc_va_start (tree valist, rtx nextarg)
a8b2c8a1
RH		 5845{
5846 nextarg = expand_builtin_saveregs ();
e5faf155 5847 std_expand_builtin_va_start (valist, nextarg);
a8b2c8a1
RH		 5848}
5849
1b5963f7 5850/* Implement `va_arg' for stdarg. */
a8b2c8a1 5851
35652573 5852static tree
726a989a
RB		 5853sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
5854 gimple_seq *post_p)
5f393b25
JM		 5855{
5856 HOST_WIDE_INT size, rsize, align;
5857 tree addr, incr;
5858 bool indirect;
5859 tree ptrtype = build_pointer_type (type);
5860
22d66adf 5861 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5f393b25
JM		 5862 {
5863 indirect = true;
5864 size = rsize = UNITS_PER_WORD;
5865 align = 0;
5866 }
5867 else
5868 {
5869 indirect = false;
5870 size = int_size_in_bytes (type);
5871 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5872 align = 0;
3764d512 5873
5f393b25
JM		 5874 if (TARGET_ARCH64)
5875 {
5876 /* For SPARC64, objects requiring 16-byte alignment get it. */
5877 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5878 align = 2 * UNITS_PER_WORD;
5879
5880 /* SPARC-V9 ABI states that structures up to 16 bytes in size
22d66adf 5881 are left-justified in their slots. */
5f393b25
JM		 5882 if (AGGREGATE_TYPE_P (type))
5883 {
5884 if (size == 0)
5885 size = rsize = UNITS_PER_WORD;
5886 else
5887 size = rsize;
5888 }
5889 }
5890 }
5891
5892 incr = valist;
5893 if (align)
5894 {
5be014d5
AP		 5895 incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
5896 size_int (align - 1));
5897 incr = fold_convert (sizetype, incr);
5898 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
5899 size_int (-align));
5900 incr = fold_convert (ptr_type_node, incr);
5f393b25
JM		 5901 }
5902
5903 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
5904 addr = incr;
5905
5906 if (BYTES_BIG_ENDIAN && size < rsize)
5be014d5
AP		 5907 addr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
5908 size_int (rsize - size));
5f393b25
JM		 5909
5910 if (indirect)
5911 {
5912 addr = fold_convert (build_pointer_type (ptrtype), addr);
22d66adf 5913 addr = build_va_arg_indirect_ref (addr);
5f393b25 5914 }
3764d512
EB		 5915
5916 /* If the address isn't aligned properly for the type, we need a temporary.
5917 FIXME: This is inefficient, usually we can do this in registers. */
5918 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
5f393b25
JM		 5919 {
5920 tree tmp = create_tmp_var (type, "va_arg_tmp");
5921 tree dest_addr = build_fold_addr_expr (tmp);
3764d512
EB		 5922 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
5923 3, dest_addr, addr, size_int (rsize));
5924 TREE_ADDRESSABLE (tmp) = 1;
5f393b25
JM		 5925 gimplify_and_add (copy, pre_p);
5926 addr = dest_addr;
5927 }
3764d512 5928
5f393b25
JM		 5929 else
5930 addr = fold_convert (ptrtype, addr);
5931
3764d512
EB		 5932 incr
5933 = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, size_int (rsize));
726a989a 5934 gimplify_assign (valist, incr, post_p);
5f393b25 5935
22d66adf 5936 return build_va_arg_indirect_ref (addr);
5f393b25 5937}
ab835497 5938\f
c75d6010
JM		 5939/* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
5940 Specify whether the vector mode is supported by the hardware. */
5941
5942static bool
5943sparc_vector_mode_supported_p (enum machine_mode mode)
5944{
5945 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
5946}
5947\f
1b3c2c2d
EB		 5948/* Return the string to output an unconditional branch to LABEL, which is
5949 the operand number of the label.
5950
5951 DEST is the destination insn (i.e. the label), INSN is the source. */
5952
5953const char *
5954output_ubranch (rtx dest, int label, rtx insn)
5955{
5956 static char string[64];
4e5b002b 5957 bool v9_form = false;
1b3c2c2d
EB		 5958 char *p;
5959
4e5b002b 5960 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
1b3c2c2d 5961 {
4e5b002b
EB		 5962 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5963 - INSN_ADDRESSES (INSN_UID (insn)));
5964 /* Leave some instructions for "slop". */
5965 if (delta >= -260000 && delta < 260000)
5966 v9_form = true;
1b3c2c2d 5967 }
1b3c2c2d 5968
4e5b002b
EB		 5969 if (v9_form)
5970 strcpy (string, "ba%*,pt\t%%xcc, ");
5971 else
5972 strcpy (string, "b%*\t");
1b3c2c2d
EB		 5973
5974 p = strchr (string, '\0');
5975 *p++ = '%';
5976 *p++ = 'l';
5977 *p++ = '0' + label;
5978 *p++ = '%';
4e5b002b 5979 *p++ = '(';
1b3c2c2d
EB		 5980 *p = '\0';
5981
5982 return string;
5983}
5984
ab835497 5985/* Return the string to output a conditional branch to LABEL, which is
c4ce6853
DE		 5986 the operand number of the label. OP is the conditional expression.
5987 XEXP (OP, 0) is assumed to be a condition code register (integer or
5988 floating point) and its mode specifies what kind of comparison we made.
61a55e8b 5989
1b3c2c2d
EB		 5990 DEST is the destination insn (i.e. the label), INSN is the source.
5991
5e7a8ee0 5992 REVERSED is nonzero if we should reverse the sense of the comparison.
ab835497 5993
4e5b002b 5994 ANNUL is nonzero if we should generate an annulling branch. */
ab835497 5995
a6163c22 5996const char *
fc27d102 5997output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
4e5b002b 5998 rtx insn)
ab835497 5999{
a6163c22 6000 static char string[64];
ab835497 6001 enum rtx_code code = GET_CODE (op);
c4ce6853
DE		 6002 rtx cc_reg = XEXP (op, 0);
6003 enum machine_mode mode = GET_MODE (cc_reg);
0b82d204
JJ		 6004 const char *labelno, *branch;
6005 int spaces = 8, far;
6006 char *p;
6007
6008 /* v9 branches are limited to +-1MB. If it is too far away,
6009 change
6010
6011 bne,pt %xcc, .LC30
6012
6013 to
6014
6015 be,pn %xcc, .+12
a6163c22 6016 nop
0b82d204
JJ		 6017 ba .LC30
6018
6019 and
6020
6021 fbne,a,pn %fcc2, .LC29
61a55e8b 6022
0b82d204
JJ		 6023 to
6024
6025 fbe,pt %fcc2, .+16
a6163c22 6026 nop
0b82d204
JJ		 6027 ba .LC29 */
6028
883d9e0c 6029 far = TARGET_V9 && (get_attr_length (insn) >= 3);
0b82d204 6030 if (reversed ^ far)
ab835497 6031 {
e267e177
RH		 6032 /* Reversal of FP compares takes care -- an ordered compare
6033 becomes an unordered compare and vice versa. */
4d449554 6034 if (mode == CCFPmode || mode == CCFPEmode)
7913f3d0 6035 code = reverse_condition_maybe_unordered (code);
ab835497 6036 else
e267e177 6037 code = reverse_condition (code);
ab835497
RK		 6038 }
6039
e267e177
RH		 6040 /* Start by writing the branch condition. */
6041 if (mode == CCFPmode || mode == CCFPEmode)
5850dc00
RH		 6042 {
6043 switch (code)
6044 {
6045 case NE:
6046 branch = "fbne";
6047 break;
6048 case EQ:
6049 branch = "fbe";
6050 break;
6051 case GE:
6052 branch = "fbge";
6053 break;
6054 case GT:
6055 branch = "fbg";
6056 break;
6057 case LE:
6058 branch = "fble";
6059 break;
6060 case LT:
6061 branch = "fbl";
6062 break;
6063 case UNORDERED:
6064 branch = "fbu";
6065 break;
6066 case ORDERED:
6067 branch = "fbo";
6068 break;
6069 case UNGT:
6070 branch = "fbug";
6071 break;
6072 case UNLT:
6073 branch = "fbul";
6074 break;
6075 case UNEQ:
6076 branch = "fbue";
6077 break;
6078 case UNGE:
6079 branch = "fbuge";
6080 break;
6081 case UNLE:
6082 branch = "fbule";
6083 break;
6084 case LTGT:
6085 branch = "fblg";
6086 break;
6087
6088 default:
f5f7d171 6089 gcc_unreachable ();
5850dc00
RH		 6090 }
6091
6092 /* ??? !v9: FP branches cannot be preceded by another floating point
6093 insn. Because there is currently no concept of pre-delay slots,
6094 we can fix this only by always emitting a nop before a floating
6095 point branch. */
6096
6097 string[0] = '\0';
6098 if (! TARGET_V9)
6099 strcpy (string, "nop\n\t");
6100 strcat (string, branch);
6101 }
e267e177 6102 else
5850dc00
RH		 6103 {
6104 switch (code)
6105 {
6106 case NE:
6107 branch = "bne";
6108 break;
6109 case EQ:
6110 branch = "be";
6111 break;
6112 case GE:
0b82d204 6113 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5850dc00
RH		 6114 branch = "bpos";
6115 else
6116 branch = "bge";
6117 break;
6118 case GT:
6119 branch = "bg";
6120 break;
6121 case LE:
6122 branch = "ble";
6123 break;
6124 case LT:
0b82d204 6125 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5850dc00
RH		 6126 branch = "bneg";
6127 else
6128 branch = "bl";
6129 break;
6130 case GEU:
6131 branch = "bgeu";
6132 break;
6133 case GTU:
6134 branch = "bgu";
6135 break;
6136 case LEU:
6137 branch = "bleu";
6138 break;
6139 case LTU:
6140 branch = "blu";
6141 break;
6142
6143 default:
f5f7d171 6144 gcc_unreachable ();
5850dc00
RH		 6145 }
6146 strcpy (string, branch);
6147 }
e267e177 6148 spaces -= strlen (branch);
0b82d204 6149 p = strchr (string, '\0');
e267e177 6150
ab835497 6151 /* Now add the annulling, the label, and a possible noop. */
0b82d204 6152 if (annul && ! far)
e0d80184 6153 {
0b82d204
JJ		 6154 strcpy (p, ",a");
6155 p += 2;
e0d80184
DM		 6156 spaces -= 2;
6157 }
ab835497 6158
883d9e0c 6159 if (TARGET_V9)
61a55e8b 6160 {
c6b0465b 6161 rtx note;
0b82d204 6162 int v8 = 0;
c6b0465b 6163
0b82d204 6164 if (! far && insn && INSN_ADDRESSES_SET_P ())
e0d80184 6165 {
0b82d204
JJ		 6166 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6167 - INSN_ADDRESSES (INSN_UID (insn)));
6168 /* Leave some instructions for "slop". */
6169 if (delta < -260000 || delta >= 260000)
6170 v8 = 1;
e0d80184 6171 }
c6b0465b 6172
61a55e8b
DE		 6173 if (mode == CCFPmode || mode == CCFPEmode)
6174 {
0b82d204 6175 static char v9_fcc_labelno[] = "%%fccX, ";
61a55e8b 6176 /* Set the char indicating the number of the fcc reg to use. */
0b82d204
JJ		 6177 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6178 labelno = v9_fcc_labelno;
6179 if (v8)
6180 {
f5f7d171
JM		 6181 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
6182 labelno = "";
0b82d204 6183 }
61a55e8b
DE		 6184 }
6185 else if (mode == CCXmode || mode == CCX_NOOVmode)
0b82d204
JJ		 6186 {
6187 labelno = "%%xcc, ";
f5f7d171 6188 gcc_assert (! v8);
0b82d204 6189 }
61a55e8b 6190 else
0b82d204
JJ		 6191 {
6192 labelno = "%%icc, ";
6193 if (v8)
6194 labelno = "";
6195 }
6196
4f31cce8 6197 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
0b82d204
JJ		 6198 {
6199 strcpy (p,
4f31cce8 6200 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
0b82d204
JJ		 6201 ? ",pt" : ",pn");
6202 p += 3;
6203 spaces -= 3;
6204 }
61a55e8b 6205 }
883d9e0c
EB		 6206 else
6207 labelno = "";
6208
e0d80184 6209 if (spaces > 0)
0b82d204 6210 *p++ = '\t';
e0d80184 6211 else
0b82d204
JJ		 6212 *p++ = ' ';
6213 strcpy (p, labelno);
6214 p = strchr (p, '\0');
6215 if (far)
6216 {
a6163c22 6217 strcpy (p, ".+12\n\t nop\n\tb\t");
4e5b002b
EB		 6218 /* Skip the next insn if requested or
6219 if we know that it will be a nop. */
6220 if (annul || ! final_sequence)
0b82d204 6221 p[3] = '6';
a6163c22 6222 p += 14;
0b82d204
JJ		 6223 }
6224 *p++ = '%';
6225 *p++ = 'l';
0b82d204 6226 *p++ = label + '0';
4e5b002b
EB		 6227 *p++ = '%';
6228 *p++ = '#';
0b82d204 6229 *p = '\0';
61a55e8b
DE		 6230
6231 return string;
6232}
6233
47ac041c 6234/* Emit a library call comparison between floating point X and Y.
19047e4a
EB		 6235 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
6236 Return the new operator to be used in the comparison sequence.
6237
47ac041c
JJ		 6238 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6239 values as arguments instead of the TFmode registers themselves,
6240 that's why we cannot call emit_float_lib_cmp. */
19047e4a 6241
f90b7a5a 6242rtx
fc27d102 6243sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
47ac041c 6244{
e77d72cb 6245 const char *qpfunc;
390b17c2 6246 rtx slot0, slot1, result, tem, tem2, libfunc;
5c5c34a4 6247 enum machine_mode mode;
19047e4a 6248 enum rtx_code new_comparison;
47ac041c
JJ		 6249
6250 switch (comparison)
6251 {
6252 case EQ:
19047e4a 6253 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
47ac041c
JJ		 6254 break;
6255
6256 case NE:
19047e4a 6257 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
47ac041c
JJ		 6258 break;
6259
6260 case GT:
19047e4a 6261 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
47ac041c
JJ		 6262 break;
6263
6264 case GE:
19047e4a 6265 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
47ac041c
JJ		 6266 break;
6267
6268 case LT:
19047e4a 6269 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
47ac041c
JJ		 6270 break;
6271
6272 case LE:
19047e4a 6273 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
5c5c34a4
JJ		 6274 break;
6275
6276 case ORDERED:
6277 case UNORDERED:
6278 case UNGT:
6279 case UNLT:
6280 case UNEQ:
6281 case UNGE:
6282 case UNLE:
6283 case LTGT:
19047e4a 6284 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
47ac041c
JJ		 6285 break;
6286
6287 default:
f5f7d171 6288 gcc_unreachable ();
47ac041c
JJ		 6289 }
6290
5c5c34a4 6291 if (TARGET_ARCH64)
47ac041c 6292 {
19047e4a
EB		 6293 if (MEM_P (x))
6294 slot0 = x;
6295 else
5c5c34a4
JJ		 6296 {
6297 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
c5d74498 6298 emit_move_insn (slot0, x);
5c5c34a4 6299 }
5c5c34a4 6300
19047e4a
EB		 6301 if (MEM_P (y))
6302 slot1 = y;
6303 else
5c5c34a4
JJ		 6304 {
6305 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
c5d74498 6306 emit_move_insn (slot1, y);
5c5c34a4 6307 }
47ac041c 6308
390b17c2
RE		 6309 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
6310 emit_library_call (libfunc, LCT_NORMAL,
5c5c34a4
JJ		 6311 DImode, 2,
6312 XEXP (slot0, 0), Pmode,
6313 XEXP (slot1, 0), Pmode);
5c5c34a4
JJ		 6314 mode = DImode;
6315 }
6316 else
47ac041c 6317 {
390b17c2
RE		 6318 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
6319 emit_library_call (libfunc, LCT_NORMAL,
5c5c34a4
JJ		 6320 SImode, 2,
6321 x, TFmode, y, TFmode);
5c5c34a4 6322 mode = SImode;
47ac041c
JJ		 6323 }
6324
47ac041c
JJ		 6325
6326 /* Immediately move the result of the libcall into a pseudo
6327 register so reload doesn't clobber the value if it needs
6328 the return register for a spill reg. */
5c5c34a4 6329 result = gen_reg_rtx (mode);
390b17c2 6330 emit_move_insn (result, hard_libcall_value (mode, libfunc));
47ac041c 6331
5c5c34a4
JJ		 6332 switch (comparison)
6333 {
6334 default:
f90b7a5a 6335 return gen_rtx_NE (VOIDmode, result, const0_rtx);
5c5c34a4
JJ		 6336 case ORDERED:
6337 case UNORDERED:
19047e4a 6338 new_comparison = (comparison == UNORDERED ? EQ : NE);
f90b7a5a 6339 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
5c5c34a4
JJ		 6340 case UNGT:
6341 case UNGE:
19047e4a 6342 new_comparison = (comparison == UNGT ? GT : NE);
f90b7a5a 6343 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
5c5c34a4 6344 case UNLE:
f90b7a5a 6345 return gen_rtx_NE (VOIDmode, result, const2_rtx);
5c5c34a4
JJ		 6346 case UNLT:
6347 tem = gen_reg_rtx (mode);
6348 if (TARGET_ARCH32)
6349 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6350 else
6351 emit_insn (gen_anddi3 (tem, result, const1_rtx));
f90b7a5a 6352 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
5c5c34a4
JJ		 6353 case UNEQ:
6354 case LTGT:
6355 tem = gen_reg_rtx (mode);
6356 if (TARGET_ARCH32)
6357 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6358 else
6359 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6360 tem2 = gen_reg_rtx (mode);
6361 if (TARGET_ARCH32)
6362 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6363 else
6364 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
19047e4a 6365 new_comparison = (comparison == UNEQ ? EQ : NE);
f90b7a5a 6366 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
5c5c34a4 6367 }
19047e4a 6368
f90b7a5a 6369 gcc_unreachable ();
47ac041c 6370}
5c5c34a4 6371
d88e57d1
RH		 6372/* Generate an unsigned DImode to FP conversion. This is the same code
6373 optabs would emit if we didn't have TFmode patterns. */
6374
6375void
b178305d 6376sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
d88e57d1
RH		 6377{
6378 rtx neglab, donelab, i0, i1, f0, in, out;
d88e57d1
RH		 6379
6380 out = operands[0];
6381 in = force_reg (DImode, operands[1]);
d88e57d1
RH		 6382 neglab = gen_label_rtx ();
6383 donelab = gen_label_rtx ();
6384 i0 = gen_reg_rtx (DImode);
6385 i1 = gen_reg_rtx (DImode);
6386 f0 = gen_reg_rtx (mode);
6387
6388 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6389
6390 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6391 emit_jump_insn (gen_jump (donelab));
6392 emit_barrier ();
6393
6394 emit_label (neglab);
6395
6396 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6397 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6398 emit_insn (gen_iordi3 (i0, i0, i1));
6399 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6400 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6401
6402 emit_label (donelab);
6403}
6404
b178305d
EB		 6405/* Generate an FP to unsigned DImode conversion. This is the same code
6406 optabs would emit if we didn't have TFmode patterns. */
6407
6408void
6409sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6410{
6411 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6412
6413 out = operands[0];
6414 in = force_reg (mode, operands[1]);
6415 neglab = gen_label_rtx ();
6416 donelab = gen_label_rtx ();
6417 i0 = gen_reg_rtx (DImode);
6418 i1 = gen_reg_rtx (DImode);
6419 limit = gen_reg_rtx (mode);
6420 f0 = gen_reg_rtx (mode);
6421
6422 emit_move_insn (limit,
6423 CONST_DOUBLE_FROM_REAL_VALUE (
6424 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6425 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6426
6427 emit_insn (gen_rtx_SET (VOIDmode,
6428 out,
6429 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6430 emit_jump_insn (gen_jump (donelab));
6431 emit_barrier ();
6432
6433 emit_label (neglab);
6434
6435 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6436 emit_insn (gen_rtx_SET (VOIDmode,
6437 i0,
6438 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6439 emit_insn (gen_movdi (i1, const1_rtx));
6440 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6441 emit_insn (gen_xordi3 (out, i0, i1));
6442
6443 emit_label (donelab);
6444}
6445
61a55e8b
DE		 6446/* Return the string to output a conditional branch to LABEL, testing
6447 register REG. LABEL is the operand number of the label; REG is the
6448 operand number of the reg. OP is the conditional expression. The mode
6449 of REG says what kind of comparison we made.
6450
1b3c2c2d
EB		 6451 DEST is the destination insn (i.e. the label), INSN is the source.
6452
5e7a8ee0 6453 REVERSED is nonzero if we should reverse the sense of the comparison.
61a55e8b 6454
4e5b002b 6455 ANNUL is nonzero if we should generate an annulling branch. */
61a55e8b 6456
a6163c22 6457const char *
fc27d102 6458output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
4e5b002b 6459 int annul, rtx insn)
61a55e8b 6460{
a6163c22 6461 static char string[64];
61a55e8b
DE		 6462 enum rtx_code code = GET_CODE (op);
6463 enum machine_mode mode = GET_MODE (XEXP (op, 0));
e0d80184 6464 rtx note;
0b82d204
JJ		 6465 int far;
6466 char *p;
6467
6468 /* branch on register are limited to +-128KB. If it is too far away,
6469 change
4900aa61 6470
0b82d204 6471 brnz,pt %g1, .LC30
4900aa61 6472
0b82d204 6473 to
4900aa61 6474
0b82d204 6475 brz,pn %g1, .+12
a6163c22 6476 nop
0b82d204 6477 ba,pt %xcc, .LC30
4900aa61 6478
0b82d204 6479 and
4900aa61 6480
0b82d204 6481 brgez,a,pn %o1, .LC29
4900aa61 6482
0b82d204 6483 to
4900aa61 6484
0b82d204 6485 brlz,pt %o1, .+16
a6163c22 6486 nop
0b82d204
JJ		 6487 ba,pt %xcc, .LC29 */
6488
6489 far = get_attr_length (insn) >= 3;
61a55e8b
DE		 6490
6491 /* If not floating-point or if EQ or NE, we can just reverse the code. */
0b82d204
JJ		 6492 if (reversed ^ far)
6493 code = reverse_condition (code);
61a55e8b
DE		 6494
6495 /* Only 64 bit versions of these instructions exist. */
f5f7d171 6496 gcc_assert (mode == DImode);
61a55e8b
DE		 6497
6498 /* Start by writing the branch condition. */
6499
6500 switch (code)
6501 {
6502 case NE:
6503 strcpy (string, "brnz");
6504 break;
6505
6506 case EQ:
6507 strcpy (string, "brz");
6508 break;
6509
6510 case GE:
6511 strcpy (string, "brgez");
6512 break;
6513
6514 case LT:
6515 strcpy (string, "brlz");
6516 break;
6517
6518 case LE:
6519 strcpy (string, "brlez");
6520 break;
6521
6522 case GT:
6523 strcpy (string, "brgz");
6524 break;
6525
6526 default:
f5f7d171 6527 gcc_unreachable ();
61a55e8b
DE		 6528 }
6529
0b82d204
JJ		 6530 p = strchr (string, '\0');
6531
61a55e8b 6532 /* Now add the annulling, reg, label, and nop. */
0b82d204 6533 if (annul && ! far)
e0d80184 6534 {
0b82d204
JJ		 6535 strcpy (p, ",a");
6536 p += 2;
e0d80184 6537 }
61a55e8b 6538
4f31cce8 6539 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
e0d80184 6540 {
0b82d204 6541 strcpy (p,
4f31cce8 6542 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
0b82d204
JJ		 6543 ? ",pt" : ",pn");
6544 p += 3;
e0d80184 6545 }
61a55e8b 6546
0b82d204
JJ		 6547 *p = p < string + 8 ? '\t' : ' ';
6548 p++;
6549 *p++ = '%';
6550 *p++ = '0' + reg;
6551 *p++ = ',';
6552 *p++ = ' ';
6553 if (far)
6554 {
6555 int veryfar = 1, delta;
6556
6557 if (INSN_ADDRESSES_SET_P ())
6558 {
6559 delta = (INSN_ADDRESSES (INSN_UID (dest))
6560 - INSN_ADDRESSES (INSN_UID (insn)));
6561 /* Leave some instructions for "slop". */
6562 if (delta >= -260000 && delta < 260000)
6563 veryfar = 0;
6564 }
6565
a6163c22 6566 strcpy (p, ".+12\n\t nop\n\t");
4e5b002b
EB		 6567 /* Skip the next insn if requested or
6568 if we know that it will be a nop. */
6569 if (annul || ! final_sequence)
0b82d204 6570 p[3] = '6';
a6163c22 6571 p += 12;
0b82d204
JJ		 6572 if (veryfar)
6573 {
6574 strcpy (p, "b\t");
6575 p += 2;
6576 }
6577 else
6578 {
6579 strcpy (p, "ba,pt\t%%xcc, ");
6580 p += 13;
6581 }
6582 }
6583 *p++ = '%';
6584 *p++ = 'l';
6585 *p++ = '0' + label;
4e5b002b
EB		 6586 *p++ = '%';
6587 *p++ = '#';
0b82d204 6588 *p = '\0';
ab835497 6589
ab835497
RK		 6590 return string;
6591}
6592
e48addee
JJ		 6593/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6594 Such instructions cannot be used in the delay slot of return insn on v9.
6595 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6596 */
284d86e9 6597
e48addee 6598static int
fc27d102 6599epilogue_renumber (register rtx *where, int test)
284d86e9 6600{
e48addee
JJ		 6601 register const char *fmt;
6602 register int i;
6603 register enum rtx_code code;
6604
6605 if (*where == 0)
6606 return 0;
6607
6608 code = GET_CODE (*where);
284d86e9
JC		 6609
6610 switch (code)
6611 {
284d86e9 6612 case REG:
e48addee
JJ		 6613 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6614 return 1;
6615 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
f1c25d3b 6616 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
e48addee
JJ		 6617 case SCRATCH:
6618 case CC0:
6619 case PC:
284d86e9
JC		 6620 case CONST_INT:
6621 case CONST_DOUBLE:
e48addee 6622 return 0;
76a7c776 6623
09ebda1b
SC		 6624 /* Do not replace the frame pointer with the stack pointer because
6625 it can cause the delayed instruction to load below the stack.
6626 This occurs when instructions like:
6627
6628 (set (reg/i:SI 24 %i0)
6629 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6630 (const_int -20 [0xffffffec])) 0))
6631
6632 are in the return delayed slot. */
6633 case PLUS:
6634 if (GET_CODE (XEXP (*where, 0)) == REG
563c12b0 6635 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
09ebda1b
SC		 6636 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6637 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6638 return 1;
6639 break;
6640
6641 case MEM:
6642 if (SPARC_STACK_BIAS
6643 && GET_CODE (XEXP (*where, 0)) == REG
563c12b0 6644 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
09ebda1b
SC		 6645 return 1;
6646 break;
6647
76a7c776
DM		 6648 default:
6649 break;
e48addee 6650 }
284d86e9 6651
e48addee 6652 fmt = GET_RTX_FORMAT (code);
284d86e9 6653
e48addee
JJ		 6654 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6655 {
6656 if (fmt[i] == 'E')
6657 {
6658 register int j;
6659 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6660 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6661 return 1;
6662 }
6663 else if (fmt[i] == 'e'
6664 && epilogue_renumber (&(XEXP (*where, i)), test))
6665 return 1;
284d86e9 6666 }
e48addee 6667 return 0;
284d86e9 6668}
ab835497
RK		 6669\f
6670/* Leaf functions and non-leaf functions have different needs. */
6671
8b60264b 6672static const int
ab835497
RK		 6673reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6674
8b60264b 6675static const int
ab835497
RK		 6676reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6677
8b60264b 6678static const int *const reg_alloc_orders[] = {
ab835497
RK		 6679 reg_leaf_alloc_order,
6680 reg_nonleaf_alloc_order};
6681
6682void
fc27d102 6683order_regs_for_local_alloc (void)
ab835497
RK		 6684{
6685 static int last_order_nonleaf = 1;
6686
6fb5fa3c 6687 if (df_regs_ever_live_p (15) != last_order_nonleaf)
ab835497
RK		 6688 {
6689 last_order_nonleaf = !last_order_nonleaf;
2e09e75a 6690 memcpy ((char *) reg_alloc_order,
8b60264b 6691 (const char *) reg_alloc_orders[last_order_nonleaf],
2e09e75a 6692 FIRST_PSEUDO_REGISTER * sizeof (int));
ab835497
RK		 6693 }
6694}
6695\f
e0d80184
DM		 6696/* Return 1 if REG and MEM are legitimate enough to allow the various
6697 mem<-->reg splits to be run. */
6698
6699int
fc27d102 6700sparc_splitdi_legitimate (rtx reg, rtx mem)
e0d80184 6701{
e0d80184 6702 /* Punt if we are here by mistake. */
f5f7d171 6703 gcc_assert (reload_completed);
e0d80184
DM		 6704
6705 /* We must have an offsettable memory reference. */
6706 if (! offsettable_memref_p (mem))
6707 return 0;
6708
6709 /* If we have legitimate args for ldd/std, we do not want
6710 the split to happen. */
6711 if ((REGNO (reg) % 2) == 0
6712 && mem_min_alignment (mem, 8))
6713 return 0;
6714
6715 /* Success. */
6716 return 1;
6717}
6718
e61c29e9 6719/* Return 1 if x and y are some kind of REG and they refer to
fae778eb 6720 different hard registers. This test is guaranteed to be
e61c29e9
DM		 6721 run after reload. */
6722
6723int
fc27d102 6724sparc_absnegfloat_split_legitimate (rtx x, rtx y)
e61c29e9 6725{
e61c29e9
DM		 6726 if (GET_CODE (x) != REG)
6727 return 0;
e61c29e9
DM		 6728 if (GET_CODE (y) != REG)
6729 return 0;
6730 if (REGNO (x) == REGNO (y))
6731 return 0;
6732 return 1;
6733}
6734
35016322 6735/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4900aa61 6736 This makes them candidates for using ldd and std insns.
35016322 6737
bfd6bc60 6738 Note reg1 and reg2 *must* be hard registers. */
35016322
JW		 6739
6740int
fc27d102 6741registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
35016322 6742{
35016322 6743 /* We might have been passed a SUBREG. */
4900aa61 6744 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35016322
JW		 6745 return 0;
6746
35016322
JW		 6747 if (REGNO (reg1) % 2 != 0)
6748 return 0;
6749
4900aa61
EB		 6750 /* Integer ldd is deprecated in SPARC V9 */
6751 if (TARGET_V9 && REGNO (reg1) < 32)
6752 return 0;
bfd6bc60 6753
35016322 6754 return (REGNO (reg1) == REGNO (reg2) - 1);
35016322
JW		 6755}
6756
2aad5d68 6757/* Return 1 if the addresses in mem1 and mem2 are suitable for use in
303f8933 6758 an ldd or std insn.
4900aa61 6759
2aad5d68
DN		 6760 This can only happen when addr1 and addr2, the addresses in mem1
6761 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
303f8933
DN		 6762 addr1 must also be aligned on a 64-bit boundary.
6763
6764 Also iff dependent_reg_rtx is not null it should not be used to
6765 compute the address for mem1, i.e. we cannot optimize a sequence
6766 like:
6767 ld [%o0], %o0
6768 ld [%o0 + 4], %o1
6769 to
bcdd764b 6770 ldd [%o0], %o0
0acf409f
DM		 6771 nor:
6772 ld [%g3 + 4], %g3
6773 ld [%g3], %g2
6774 to
6775 ldd [%g3], %g2
6776
6777 But, note that the transformation from:
6778 ld [%g2 + 4], %g3
6779 ld [%g2], %g2
6780 to
6781 ldd [%g2], %g2
6782 is perfectly fine. Thus, the peephole2 patterns always pass us
6783 the destination register of the first load, never the second one.
6784
303f8933
DN		 6785 For stores we don't have a similar problem, so dependent_reg_rtx is
6786 NULL_RTX. */
35016322
JW		 6787
6788int
fc27d102 6789mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
35016322 6790{
2aad5d68 6791 rtx addr1, addr2;
0d587737 6792 unsigned int reg1;
6a151f87 6793 HOST_WIDE_INT offset1;
35016322 6794
303f8933
DN		 6795 /* The mems cannot be volatile. */
6796 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6797 return 0;
2aad5d68 6798
303f8933 6799 /* MEM1 should be aligned on a 64-bit boundary. */
2aad5d68
DN		 6800 if (MEM_ALIGN (mem1) < 64)
6801 return 0;
4900aa61 6802
303f8933
DN		 6803 addr1 = XEXP (mem1, 0);
6804 addr2 = XEXP (mem2, 0);
4900aa61 6805
35016322
JW		 6806 /* Extract a register number and offset (if used) from the first addr. */
6807 if (GET_CODE (addr1) == PLUS)
6808 {
6809 /* If not a REG, return zero. */
6810 if (GET_CODE (XEXP (addr1, 0)) != REG)
6811 return 0;
6812 else
6813 {
6814 reg1 = REGNO (XEXP (addr1, 0));
6815 /* The offset must be constant! */
6816 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6817 return 0;
6818 offset1 = INTVAL (XEXP (addr1, 1));
6819 }
6820 }
6821 else if (GET_CODE (addr1) != REG)
6822 return 0;
6823 else
6824 {
6825 reg1 = REGNO (addr1);
6826 /* This was a simple (mem (reg)) expression. Offset is 0. */
6827 offset1 = 0;
6828 }
6829
6830 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6831 if (GET_CODE (addr2) != PLUS)
6832 return 0;
6833
6834 if (GET_CODE (XEXP (addr2, 0)) != REG
6835 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6836 return 0;
6837
35016322
JW		 6838 if (reg1 != REGNO (XEXP (addr2, 0)))
6839 return 0;
6840
303f8933
DN		 6841 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6842 return 0;
4900aa61
EB		 6843
6844 /* The first offset must be evenly divisible by 8 to ensure the
35016322
JW		 6845 address is 64 bit aligned. */
6846 if (offset1 % 8 != 0)
6847 return 0;
6848
6849 /* The offset for the second addr must be 4 more than the first addr. */
6850 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6851 return 0;
6852
6853 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6854 instructions. */
6855 return 1;
6856}
7c56249d 6857
157891a3
EB		 6858/* Return 1 if reg is a pseudo, or is the first register in
6859 a hard register pair. This makes it suitable for use in
7c56249d
JL		 6860 ldd and std insns. */
6861
6862int
fc27d102 6863register_ok_for_ldd (rtx reg)
7c56249d 6864{
7c56249d 6865 /* We might have been passed a SUBREG. */
157891a3 6866 if (!REG_P (reg))
7c56249d
JL		 6867 return 0;
6868
6869 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6870 return (REGNO (reg) % 2 == 0);
157891a3
EB		 6871
6872 return 1;
6873}
6874
6875/* Return 1 if OP is a memory whose address is known to be
6876 aligned to 8-byte boundary, or a pseudo during reload.
6877 This makes it suitable for use in ldd and std insns. */
6878
6879int
6880memory_ok_for_ldd (rtx op)
6881{
6882 if (MEM_P (op))
6883 {
6884 /* In 64-bit mode, we assume that the address is word-aligned. */
6885 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
6886 return 0;
6887
6888 if ((reload_in_progress || reload_completed)
6889 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
6890 return 0;
6891 }
6892 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
6893 {
6894 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
6895 return 0;
6896 }
6897 else
6898 return 0;
6899
6900 return 1;
7c56249d 6901}
ab835497 6902\f
ab835497
RK		 6903/* Print operand X (an rtx) in assembler syntax to file FILE.
6904 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6905 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6906
6907void
fc27d102 6908print_operand (FILE *file, rtx x, int code)
ab835497
RK		 6909{
6910 switch (code)
6911 {
6912 case '#':
4e5b002b
EB		 6913 /* Output an insn in a delay slot. */
6914 if (final_sequence)
6915 sparc_indent_opcode = 1;
6916 else
e0d80184 6917 fputs ("\n\t nop", file);
ab835497
RK		 6918 return;
6919 case '*':
c6ce0969 6920 /* Output an annul flag if there's nothing for the delay slot and we
4e5b002b
EB		 6921 are optimizing. This is always used with '(' below.
6922 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6923 this is a dbx bug. So, we only do this when optimizing.
6924 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
bfd6bc60 6925 Always emit a nop in case the next instruction is a branch. */
4e5b002b 6926 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
c6ce0969
JW		 6927 fputs (",a", file);
6928 return;
6929 case '(':
6930 /* Output a 'nop' if there's nothing for the delay slot and we are
6931 not optimizing. This is always used with '*' above. */
4e5b002b 6932 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
e0d80184 6933 fputs ("\n\t nop", file);
4e5b002b
EB		 6934 else if (final_sequence)
6935 sparc_indent_opcode = 1;
6936 return;
6937 case ')':
6938 /* Output the right displacement from the saved PC on function return.
6939 The caller may have placed an "unimp" insn immediately after the call
6940 so we have to account for it. This insn is used in the 32-bit ABI
66695571 6941 when calling a function that returns a non zero-sized structure. The
4e5b002b 6942 64-bit ABI doesn't have it. Be careful to have this test be the same
66695571
EB		 6943 as that for the call. The exception is when sparc_std_struct_return
6944 is enabled, the psABI is followed exactly and the adjustment is made
6945 by the code in sparc_struct_value_rtx. The call emitted is the same
6946 when sparc_std_struct_return is enabled. */
6947 if (!TARGET_ARCH64
e3b5732b 6948 && cfun->returns_struct
66695571
EB		 6949 && !sparc_std_struct_return
6950 && DECL_SIZE (DECL_RESULT (current_function_decl))
6951 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
6952 == INTEGER_CST
6953 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
4e5b002b
EB		 6954 fputs ("12", file);
6955 else
6956 fputc ('8', file);
ab835497 6957 return;
61a55e8b 6958 case '_':
a0a301fc
DE		 6959 /* Output the Embedded Medium/Anywhere code model base register. */
6960 fputs (EMBMEDANY_BASE_REG, file);
61a55e8b 6961 return;
5751a10b
JJ		 6962 case '&':
6963 /* Print some local dynamic TLS name. */
6964 assemble_name (file, get_some_local_dynamic_name ());
6965 return;
4e5b002b 6966
ab835497
RK		 6967 case 'Y':
6968 /* Adjust the operand to take into account a RESTORE operation. */
bfd6bc60
JC		 6969 if (GET_CODE (x) == CONST_INT)
6970 break;
6971 else if (GET_CODE (x) != REG)
c725bd79 6972 output_operand_lossage ("invalid %%Y operand");
b3b1e8bd 6973 else if (REGNO (x) < 8)
ab835497
RK		 6974 fputs (reg_names[REGNO (x)], file);
6975 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6976 fputs (reg_names[REGNO (x)-16], file);
6977 else
c725bd79 6978 output_operand_lossage ("invalid %%Y operand");
ab835497 6979 return;
0f39a9aa
DE		 6980 case 'L':
6981 /* Print out the low order register name of a register pair. */
6982 if (WORDS_BIG_ENDIAN)
6983 fputs (reg_names[REGNO (x)+1], file);
6984 else
6985 fputs (reg_names[REGNO (x)], file);
6986 return;
6987 case 'H':
6988 /* Print out the high order register name of a register pair. */
6989 if (WORDS_BIG_ENDIAN)
6990 fputs (reg_names[REGNO (x)], file);
6991 else
6992 fputs (reg_names[REGNO (x)+1], file);
6993 return;
ab835497 6994 case 'R':
795068a4 6995 /* Print out the second register name of a register pair or quad.
ab835497
RK		 6996 I.e., R (%o0) => %o1. */
6997 fputs (reg_names[REGNO (x)+1], file);
6998 return;
795068a4
JW		 6999 case 'S':
7000 /* Print out the third register name of a register quad.
7001 I.e., S (%o0) => %o2. */
7002 fputs (reg_names[REGNO (x)+2], file);
7003 return;
7004 case 'T':
7005 /* Print out the fourth register name of a register quad.
7006 I.e., T (%o0) => %o3. */
7007 fputs (reg_names[REGNO (x)+3], file);
7008 return;
304b7a23
DE		 7009 case 'x':
7010 /* Print a condition code register. */
7011 if (REGNO (x) == SPARC_ICC_REG)
7012 {
7013 /* We don't handle CC[X]_NOOVmode because they're not supposed
7014 to occur here. */
7015 if (GET_MODE (x) == CCmode)
7016 fputs ("%icc", file);
7017 else if (GET_MODE (x) == CCXmode)
7018 fputs ("%xcc", file);
7019 else
f5f7d171 7020 gcc_unreachable ();
304b7a23
DE		 7021 }
7022 else
7023 /* %fccN register */
7024 fputs (reg_names[REGNO (x)], file);
7025 return;
ab835497
RK		 7026 case 'm':
7027 /* Print the operand's address only. */
7028 output_address (XEXP (x, 0));
7029 return;
7030 case 'r':
7031 /* In this case we need a register. Use %g0 if the
77a02b01 7032 operand is const0_rtx. */
76052e74
RS		 7033 if (x == const0_rtx
7034 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
ab835497
RK		 7035 {
7036 fputs ("%g0", file);
7037 return;
7038 }
7039 else
7040 break;
7041
61a55e8b 7042 case 'A':
ab835497
RK		 7043 switch (GET_CODE (x))
7044 {
7045 case IOR: fputs ("or", file); break;
7046 case AND: fputs ("and", file); break;
7047 case XOR: fputs ("xor", file); break;
c725bd79 7048 default: output_operand_lossage ("invalid %%A operand");
ab835497
RK		 7049 }
7050 return;
7051
7052 case 'B':
7053 switch (GET_CODE (x))
7054 {
7055 case IOR: fputs ("orn", file); break;
7056 case AND: fputs ("andn", file); break;
7057 case XOR: fputs ("xnor", file); break;
c725bd79 7058 default: output_operand_lossage ("invalid %%B operand");
ab835497
RK		 7059 }
7060 return;
7061
304b7a23
DE		 7062 /* These are used by the conditional move instructions. */
7063 case 'c' :
61a55e8b 7064 case 'C':
304b7a23 7065 {
5c5c34a4
JJ		 7066 enum rtx_code rc = GET_CODE (x);
7067
7068 if (code == 'c')
7069 {
7070 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7071 if (mode == CCFPmode || mode == CCFPEmode)
7072 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7073 else
7074 rc = reverse_condition (GET_CODE (x));
7075 }
304b7a23
DE		 7076 switch (rc)
7077 {
7078 case NE: fputs ("ne", file); break;
7079 case EQ: fputs ("e", file); break;
7080 case GE: fputs ("ge", file); break;
7081 case GT: fputs ("g", file); break;
7082 case LE: fputs ("le", file); break;
7083 case LT: fputs ("l", file); break;
7084 case GEU: fputs ("geu", file); break;
7085 case GTU: fputs ("gu", file); break;
7086 case LEU: fputs ("leu", file); break;
7087 case LTU: fputs ("lu", file); break;
5c5c34a4
JJ		 7088 case LTGT: fputs ("lg", file); break;
7089 case UNORDERED: fputs ("u", file); break;
7090 case ORDERED: fputs ("o", file); break;
7091 case UNLT: fputs ("ul", file); break;
7092 case UNLE: fputs ("ule", file); break;
7093 case UNGT: fputs ("ug", file); break;
7094 case UNGE: fputs ("uge", file); break;
7095 case UNEQ: fputs ("ue", file); break;
304b7a23 7096 default: output_operand_lossage (code == 'c'
c725bd79
NB		 7097 ? "invalid %%c operand"
7098 : "invalid %%C operand");
304b7a23
DE		 7099 }
7100 return;
7101 }
7102
7103 /* These are used by the movr instruction pattern. */
7104 case 'd':
61a55e8b 7105 case 'D':
304b7a23
DE		 7106 {
7107 enum rtx_code rc = (code == 'd'
7108 ? reverse_condition (GET_CODE (x))
7109 : GET_CODE (x));
7110 switch (rc)
7111 {
7112 case NE: fputs ("ne", file); break;
7113 case EQ: fputs ("e", file); break;
7114 case GE: fputs ("gez", file); break;
7115 case LT: fputs ("lz", file); break;
7116 case LE: fputs ("lez", file); break;
7117 case GT: fputs ("gz", file); break;
7118 default: output_operand_lossage (code == 'd'
c725bd79
NB		 7119 ? "invalid %%d operand"
7120 : "invalid %%D operand");
304b7a23
DE		 7121 }
7122 return;
7123 }
61a55e8b 7124
ab835497
RK		 7125 case 'b':
7126 {
7127 /* Print a sign-extended character. */
9e0625a3 7128 int i = trunc_int_for_mode (INTVAL (x), QImode);
ab835497
RK		 7129 fprintf (file, "%d", i);
7130 return;
7131 }
7132
d2889939
RK		 7133 case 'f':
7134 /* Operand must be a MEM; write its address. */
7135 if (GET_CODE (x) != MEM)
c725bd79 7136 output_operand_lossage ("invalid %%f operand");
d2889939
RK		 7137 output_address (XEXP (x, 0));
7138 return;
7139
8707fe93
RH		 7140 case 's':
7141 {
7142 /* Print a sign-extended 32-bit value. */
7143 HOST_WIDE_INT i;
7144 if (GET_CODE(x) == CONST_INT)
7145 i = INTVAL (x);
7146 else if (GET_CODE(x) == CONST_DOUBLE)
7147 i = CONST_DOUBLE_LOW (x);
7148 else
ffa916ba
KG		 7149 {
7150 output_operand_lossage ("invalid %%s operand");
7151 return;
7152 }
8707fe93
RH		 7153 i = trunc_int_for_mode (i, SImode);
7154 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7155 return;
7156 }
7157
ab835497
RK		 7158 case 0:
7159 /* Do nothing special. */
7160 break;
7161
7162 default:
7163 /* Undocumented flag. */
415f583e 7164 output_operand_lossage ("invalid operand output code");
ab835497
RK		 7165 }
7166
7167 if (GET_CODE (x) == REG)
7168 fputs (reg_names[REGNO (x)], file);
7169 else if (GET_CODE (x) == MEM)
7170 {
7171 fputc ('[', file);
ab835497 7172 /* Poor Sun assembler doesn't understand absolute addressing. */
e6c1be7e 7173 if (CONSTANT_P (XEXP (x, 0)))
ab835497
RK		 7174 fputs ("%g0+", file);
7175 output_address (XEXP (x, 0));
7176 fputc (']', file);
7177 }
7178 else if (GET_CODE (x) == HIGH)
7179 {
7180 fputs ("%hi(", file);
7181 output_addr_const (file, XEXP (x, 0));
7182 fputc (')', file);
7183 }
7184 else if (GET_CODE (x) == LO_SUM)
7185 {
7186 print_operand (file, XEXP (x, 0), 0);
e0d80184
DM		 7187 if (TARGET_CM_MEDMID)
7188 fputs ("+%l44(", file);
7189 else
7190 fputs ("+%lo(", file);
ab835497
RK		 7191 output_addr_const (file, XEXP (x, 1));
7192 fputc (')', file);
7193 }
e601abce
JW		 7194 else if (GET_CODE (x) == CONST_DOUBLE
7195 && (GET_MODE (x) == VOIDmode
7196 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
ab835497
RK		 7197 {
7198 if (CONST_DOUBLE_HIGH (x) == 0)
0d9484c5 7199 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
ab835497
RK		 7200 else if (CONST_DOUBLE_HIGH (x) == -1
7201 && CONST_DOUBLE_LOW (x) < 0)
0d9484c5 7202 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
ab835497 7203 else
e601abce 7204 output_operand_lossage ("long long constant not a valid immediate operand");
ab835497 7205 }
e601abce
JW		 7206 else if (GET_CODE (x) == CONST_DOUBLE)
7207 output_operand_lossage ("floating point constant not a valid immediate operand");
ab835497
RK		 7208 else { output_addr_const (file, x); }
7209}
7210\f
301d03af
RS		 7211/* Target hook for assembling integer objects. The sparc version has
7212 special handling for aligned DI-mode objects. */
ab835497 7213
301d03af 7214static bool
fc27d102 7215sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
ab835497 7216{
301d03af
RS		 7217 /* ??? We only output .xword's for symbols and only then in environments
7218 where the assembler can handle them. */
7219 if (aligned_p && size == 8
7220 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
ab835497 7221 {
301d03af 7222 if (TARGET_V9)
61a55e8b 7223 {
301d03af
RS		 7224 assemble_integer_with_op ("\t.xword\t", x);
7225 return true;
61a55e8b
DE		 7226 }
7227 else
7228 {
301d03af
RS		 7229 assemble_aligned_integer (4, const0_rtx);
7230 assemble_aligned_integer (4, x);
7231 return true;
61a55e8b 7232 }
ab835497 7233 }
301d03af 7234 return default_assemble_integer (x, size, aligned_p);
ab835497 7235}
210aa14a 7236\f
b0468b84
RK		 7237/* Return the value of a code used in the .proc pseudo-op that says
7238 what kind of result this function returns. For non-C types, we pick
7239 the closest C type. */
7240
77a02b01
JW		 7241#ifndef SHORT_TYPE_SIZE
7242#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7243#endif
7244
7245#ifndef INT_TYPE_SIZE
7246#define INT_TYPE_SIZE BITS_PER_WORD
7247#endif
7248
7249#ifndef LONG_TYPE_SIZE
7250#define LONG_TYPE_SIZE BITS_PER_WORD
7251#endif
7252
7253#ifndef LONG_LONG_TYPE_SIZE
7254#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7255#endif
7256
7257#ifndef FLOAT_TYPE_SIZE
7258#define FLOAT_TYPE_SIZE BITS_PER_WORD
7259#endif
7260
7261#ifndef DOUBLE_TYPE_SIZE
7262#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7263#endif
7264
7265#ifndef LONG_DOUBLE_TYPE_SIZE
7266#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7267#endif
210aa14a
RS		 7268
7269unsigned long
fc27d102 7270sparc_type_code (register tree type)
210aa14a
RS		 7271{
7272 register unsigned long qualifiers = 0;
e5e809f4 7273 register unsigned shift;
210aa14a 7274
abc95ed3 7275 /* Only the first 30 bits of the qualifier are valid. We must refrain from
aee2c3c5
JW		 7276 setting more, since some assemblers will give an error for this. Also,
7277 we must be careful to avoid shifts of 32 bits or more to avoid getting
7278 unpredictable results. */
7279
e5e809f4 7280 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
210aa14a
RS		 7281 {
7282 switch (TREE_CODE (type))
7283 {
7284 case ERROR_MARK:
7285 return qualifiers;
4900aa61 7286
210aa14a 7287 case ARRAY_TYPE:
e5e809f4 7288 qualifiers |= (3 << shift);
210aa14a
RS		 7289 break;
7290
7291 case FUNCTION_TYPE:
7292 case METHOD_TYPE:
e5e809f4 7293 qualifiers |= (2 << shift);
210aa14a
RS		 7294 break;
7295
7296 case POINTER_TYPE:
7297 case REFERENCE_TYPE:
7298 case OFFSET_TYPE:
e5e809f4 7299 qualifiers |= (1 << shift);
210aa14a 7300 break;
ab835497 7301
210aa14a
RS		 7302 case RECORD_TYPE:
7303 return (qualifiers | 8);
7304
7305 case UNION_TYPE:
b0468b84 7306 case QUAL_UNION_TYPE:
210aa14a
RS		 7307 return (qualifiers | 9);
7308
7309 case ENUMERAL_TYPE:
7310 return (qualifiers | 10);
7311
7312 case VOID_TYPE:
7313 return (qualifiers | 16);
7314
7315 case INTEGER_TYPE:
654209e6
JW		 7316 /* If this is a range type, consider it to be the underlying
7317 type. */
7318 if (TREE_TYPE (type) != 0)
e5e809f4 7319 break;
654209e6 7320
77a02b01 7321 /* Carefully distinguish all the standard types of C,
b0468b84 7322 without messing up if the language is not C. We do this by
8df83eae 7323 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
b0468b84
RK		 7324 look at both the names and the above fields, but that's redundant.
7325 Any type whose size is between two C types will be considered
7326 to be the wider of the two types. Also, we do not have a
7327 special code to use for "long long", so anything wider than
7328 long is treated the same. Note that we can't distinguish
7329 between "int" and "long" in this code if they are the same
7330 size, but that's fine, since neither can the assembler. */
7331
7332 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8df83eae 7333 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
4900aa61 7334
b0468b84 7335 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8df83eae 7336 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
4900aa61 7337
b0468b84 7338 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8df83eae 7339 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
4900aa61 7340
b0468b84 7341 else
8df83eae 7342 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
4900aa61 7343
210aa14a 7344 case REAL_TYPE:
e5e809f4
JL		 7345 /* If this is a range type, consider it to be the underlying
7346 type. */
7347 if (TREE_TYPE (type) != 0)
7348 break;
7349
77a02b01
JW		 7350 /* Carefully distinguish all the standard types of C,
7351 without messing up if the language is not C. */
b0468b84 7352
77a02b01 7353 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
210aa14a 7354 return (qualifiers | 6);
b0468b84 7355
4900aa61 7356 else
b0468b84 7357 return (qualifiers | 7);
4900aa61 7358
210aa14a 7359 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
13d39dbc 7360 /* ??? We need to distinguish between double and float complex types,
c82aa69a
JW		 7361 but I don't know how yet because I can't reach this code from
7362 existing front-ends. */
7363 return (qualifiers | 7); /* Who knows? */
7364
1b5963f7 7365 case VECTOR_TYPE:
62de55f7 7366 case BOOLEAN_TYPE: /* Boolean truth value type. */
210aa14a 7367 case LANG_TYPE: /* ? */
26902ae0 7368 return qualifiers;
4900aa61 7369
210aa14a 7370 default:
f5f7d171 7371 gcc_unreachable (); /* Not a type! */
210aa14a
RS		 7372 }
7373 }
e5e809f4
JL		 7374
7375 return qualifiers;
210aa14a 7376}
ead69aea 7377\f
61a55e8b
DE		 7378/* Nested function support. */
7379
7380/* Emit RTL insns to initialize the variable parts of a trampoline.
7381 FNADDR is an RTX for the address of the function's pure code.
7382 CXT is an RTX for the static chain value for the function.
7383
7384 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7385 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7386 (to store insns). This is a bit excessive. Perhaps a different
7387 mechanism would be better here.
7388
849a528d 7389 Emit enough FLUSH insns to synchronize the data and instruction caches. */
61a55e8b 7390
809e78cc
RH		 7391static void
7392sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
61a55e8b 7393{
1ec0c607 7394 /* SPARC 32-bit trampoline:
c6b0465b 7395
e0d80184
DM		 7396 sethi %hi(fn), %g1
7397 sethi %hi(static), %g2
7398 jmp %g1+%lo(fn)
7399 or %g2, %lo(static), %g2
c6b0465b
JC		 7400
7401 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7402 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7403 */
7404
35aa3c1c 7405 emit_move_insn
809e78cc 7406 (adjust_address (m_tramp, SImode, 0),
35aa3c1c
RK		 7407 expand_binop (SImode, ior_optab,
7408 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7409 size_int (10), 0, 1),
7410 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7411 NULL_RTX, 1, OPTAB_DIRECT));
7412
7413 emit_move_insn
809e78cc 7414 (adjust_address (m_tramp, SImode, 4),
35aa3c1c
RK		 7415 expand_binop (SImode, ior_optab,
7416 expand_shift (RSHIFT_EXPR, SImode, cxt,
7417 size_int (10), 0, 1),
7418 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7419 NULL_RTX, 1, OPTAB_DIRECT));
7420
7421 emit_move_insn
809e78cc 7422 (adjust_address (m_tramp, SImode, 8),
35aa3c1c
RK		 7423 expand_binop (SImode, ior_optab,
7424 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7425 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7426 NULL_RTX, 1, OPTAB_DIRECT));
7427
7428 emit_move_insn
809e78cc 7429 (adjust_address (m_tramp, SImode, 12),
35aa3c1c
RK		 7430 expand_binop (SImode, ior_optab,
7431 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7432 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7433 NULL_RTX, 1, OPTAB_DIRECT));
c6b0465b 7434
c6b0465b
JC		 7435 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7436 aligned on a 16 byte boundary so one flush clears it all. */
809e78cc 7437 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
84643cbf 7438 if (sparc_cpu != PROCESSOR_ULTRASPARC
4c837a1e 7439 && sparc_cpu != PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 7440 && sparc_cpu != PROCESSOR_NIAGARA
7441 && sparc_cpu != PROCESSOR_NIAGARA2)
809e78cc 7442 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
1ec0c607
WH		 7443
7444 /* Call __enable_execute_stack after writing onto the stack to make sure
7445 the stack address is accessible. */
e7a742ec 7446#ifdef ENABLE_EXECUTE_STACK
f1c25d3b 7447 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
809e78cc 7448 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
1ec0c607
WH		 7449#endif
7450
61a55e8b
DE		 7451}
7452
1ec0c607 7453/* The 64-bit version is simpler because it makes more sense to load the
849a528d
RK		 7454 values as "immediate" data out of the trampoline. It's also easier since
7455 we can read the PC without clobbering a register. */
7456
809e78cc
RH		 7457static void
7458sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
61a55e8b 7459{
1ec0c607 7460 /* SPARC 64-bit trampoline:
345a6161 7461
e0d80184
DM		 7462 rd %pc, %g1
7463 ldx [%g1+24], %g5
7464 jmp %g5
7465 ldx [%g1+16], %g5
c6b0465b
JC		 7466 +16 bytes data
7467 */
7468
809e78cc 7469 emit_move_insn (adjust_address (m_tramp, SImode, 0),
e3aaacf4 7470 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
809e78cc 7471 emit_move_insn (adjust_address (m_tramp, SImode, 4),
e3aaacf4 7472 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
809e78cc 7473 emit_move_insn (adjust_address (m_tramp, SImode, 8),
e3aaacf4 7474 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
809e78cc 7475 emit_move_insn (adjust_address (m_tramp, SImode, 12),
e3aaacf4 7476 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
809e78cc
RH		 7477 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
7478 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
7479 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
345a6161 7480
fae15c93 7481 if (sparc_cpu != PROCESSOR_ULTRASPARC
4c837a1e 7482 && sparc_cpu != PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 7483 && sparc_cpu != PROCESSOR_NIAGARA
7484 && sparc_cpu != PROCESSOR_NIAGARA2)
809e78cc 7485 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
1ec0c607
WH		 7486
7487 /* Call __enable_execute_stack after writing onto the stack to make sure
7488 the stack address is accessible. */
e7a742ec 7489#ifdef ENABLE_EXECUTE_STACK
f1c25d3b 7490 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
809e78cc 7491 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
1ec0c607 7492#endif
61a55e8b 7493}
809e78cc
RH		 7494
7495/* Worker for TARGET_TRAMPOLINE_INIT. */
7496
7497static void
7498sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
7499{
7500 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
7501 cxt = force_reg (Pmode, cxt);
7502 if (TARGET_ARCH64)
7503 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
7504 else
7505 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
7506}
61a55e8b 7507\f
dbb54862
JW		 7508/* Adjust the cost of a scheduling dependency. Return the new cost of
7509 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7510
8947065c 7511static int
fc27d102 7512supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
dbb54862
JW		 7513{
7514 enum attr_type insn_type;
7515
7516 if (! recog_memoized (insn))
7517 return 0;
7518
7519 insn_type = get_attr_type (insn);
7520
7521 if (REG_NOTE_KIND (link) == 0)
7522 {
7523 /* Data dependency; DEP_INSN writes a register that INSN reads some
7524 cycles later. */
7525
7526 /* if a load, then the dependence must be on the memory address;
3bc8b61e
DM		 7527 add an extra "cycle". Note that the cost could be two cycles
7528 if the reg was written late in an instruction group; we ca not tell
dbb54862
JW		 7529 here. */
7530 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7531 return cost + 3;
7532
7533 /* Get the delay only if the address of the store is the dependence. */
7534 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7535 {
7536 rtx pat = PATTERN(insn);
7537 rtx dep_pat = PATTERN (dep_insn);
7538
7539 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3bc8b61e 7540 return cost; /* This should not happen! */
dbb54862
JW		 7541
7542 /* The dependency between the two instructions was on the data that
7543 is being stored. Assume that this implies that the address of the
7544 store is not dependent. */
7545 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7546 return cost;
7547
7548 return cost + 3; /* An approximation. */
7549 }
7550
7551 /* A shift instruction cannot receive its data from an instruction
7552 in the same cycle; add a one cycle penalty. */
7553 if (insn_type == TYPE_SHIFT)
7554 return cost + 3; /* Split before cascade into shift. */
7555 }
7556 else
7557 {
7558 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7559 INSN writes some cycles later. */
7560
7561 /* These are only significant for the fpu unit; writing a fp reg before
7562 the fpu has finished with it stalls the processor. */
7563
7564 /* Reusing an integer register causes no problems. */
7565 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7566 return 0;
7567 }
7568
7569 return cost;
7570}
bfd6bc60 7571
8947065c 7572static int
fc27d102 7573hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8947065c
RH		 7574{
7575 enum attr_type insn_type, dep_type;
7576 rtx pat = PATTERN(insn);
7577 rtx dep_pat = PATTERN (dep_insn);
7578
7579 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7580 return cost;
7581
7582 insn_type = get_attr_type (insn);
7583 dep_type = get_attr_type (dep_insn);
7584
7585 switch (REG_NOTE_KIND (link))
7586 {
7587 case 0:
7588 /* Data dependency; DEP_INSN writes a register that INSN reads some
7589 cycles later. */
7590
7591 switch (insn_type)
7592 {
7593 case TYPE_STORE:
7594 case TYPE_FPSTORE:
80ffc95e 7595 /* Get the delay iff the address of the store is the dependence. */
8947065c
RH		 7596 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7597 return cost;
7598
7599 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7600 return cost;
7601 return cost + 3;
7602
7603 case TYPE_LOAD:
7604 case TYPE_SLOAD:
7605 case TYPE_FPLOAD:
7606 /* If a load, then the dependence must be on the memory address. If
7607 the addresses aren't equal, then it might be a false dependency */
7608 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7609 {
7610 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
4900aa61 7611 || GET_CODE (SET_DEST (dep_pat)) != MEM
8947065c
RH		 7612 || GET_CODE (SET_SRC (pat)) != MEM
7613 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7614 XEXP (SET_SRC (pat), 0)))
7615 return cost + 2;
7616
4900aa61 7617 return cost + 8;
8947065c
RH		 7618 }
7619 break;
7620
7621 case TYPE_BRANCH:
7622 /* Compare to branch latency is 0. There is no benefit from
7623 separating compare and branch. */
7624 if (dep_type == TYPE_COMPARE)
7625 return 0;
7626 /* Floating point compare to branch latency is less than
7627 compare to conditional move. */
7628 if (dep_type == TYPE_FPCMP)
7629 return cost - 1;
7630 break;
3bb5de61
KG		 7631 default:
7632 break;
8947065c
RH		 7633 }
7634 break;
7635
7636 case REG_DEP_ANTI:
80ffc95e 7637 /* Anti-dependencies only penalize the fpu unit. */
8947065c
RH		 7638 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7639 return 0;
7640 break;
7641
7642 default:
7643 break;
4900aa61 7644 }
8947065c
RH		 7645
7646 return cost;
7647}
7648
c237e94a 7649static int
fc27d102 7650sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8947065c
RH		 7651{
7652 switch (sparc_cpu)
7653 {
7654 case PROCESSOR_SUPERSPARC:
7655 cost = supersparc_adjust_cost (insn, link, dep, cost);
7656 break;
7657 case PROCESSOR_HYPERSPARC:
7658 case PROCESSOR_SPARCLITE86X:
7659 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7660 break;
8947065c
RH		 7661 default:
7662 break;
7663 }
7664 return cost;
7665}
7666
fae15c93 7667static void
fc27d102
KG		 7668sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7669 int sched_verbose ATTRIBUTE_UNUSED,
7670 int max_ready ATTRIBUTE_UNUSED)
4900aa61
EB		 7671{}
7672
fae15c93 7673static int
fc27d102 7674sparc_use_sched_lookahead (void)
fae15c93 7675{
9eeaed6e
DM		 7676 if (sparc_cpu == PROCESSOR_NIAGARA
7677 || sparc_cpu == PROCESSOR_NIAGARA2)
4c837a1e 7678 return 0;
fae15c93
VM		 7679 if (sparc_cpu == PROCESSOR_ULTRASPARC
7680 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7681 return 4;
7682 if ((1 << sparc_cpu) &
7683 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7684 (1 << PROCESSOR_SPARCLITE86X)))
7685 return 3;
3bc8b61e
DM		 7686 return 0;
7687}
7688
fae15c93 7689static int
fc27d102 7690sparc_issue_rate (void)
bfd6bc60
JC		 7691{
7692 switch (sparc_cpu)
7693 {
4c837a1e 7694 case PROCESSOR_NIAGARA:
9eeaed6e 7695 case PROCESSOR_NIAGARA2:
fae15c93
VM		 7696 default:
7697 return 1;
7698 case PROCESSOR_V9:
284d86e9 7699 /* Assume V9 processors are capable of at least dual-issue. */
bfd6bc60 7700 return 2;
fae15c93
VM		 7701 case PROCESSOR_SUPERSPARC:
7702 return 3;
393049a9
RH		 7703 case PROCESSOR_HYPERSPARC:
7704 case PROCESSOR_SPARCLITE86X:
7705 return 2;
fae15c93
VM		 7706 case PROCESSOR_ULTRASPARC:
7707 case PROCESSOR_ULTRASPARC3:
7708 return 4;
bfd6bc60
JC		 7709 }
7710}
284d86e9
JC		 7711
7712static int
fc27d102 7713set_extends (rtx insn)
284d86e9
JC		 7714{
7715 register rtx pat = PATTERN (insn);
7716
7717 switch (GET_CODE (SET_SRC (pat)))
7718 {
80ffc95e 7719 /* Load and some shift instructions zero extend. */
284d86e9
JC		 7720 case MEM:
7721 case ZERO_EXTEND:
7722 /* sethi clears the high bits */
7723 case HIGH:
7724 /* LO_SUM is used with sethi. sethi cleared the high
7725 bits and the values used with lo_sum are positive */
7726 case LO_SUM:
284d86e9
JC		 7727 /* Store flag stores 0 or 1 */
7728 case LT: case LTU:
7729 case GT: case GTU:
7730 case LE: case LEU:
7731 case GE: case GEU:
7732 case EQ:
7733 case NE:
7734 return 1;
7735 case AND:
7736 {
4df1190a 7737 rtx op0 = XEXP (SET_SRC (pat), 0);
284d86e9
JC		 7738 rtx op1 = XEXP (SET_SRC (pat), 1);
7739 if (GET_CODE (op1) == CONST_INT)
7740 return INTVAL (op1) >= 0;
4df1190a
JJ		 7741 if (GET_CODE (op0) != REG)
7742 return 0;
7743 if (sparc_check_64 (op0, insn) == 1)
284d86e9 7744 return 1;
4df1190a
JJ		 7745 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7746 }
7747 case IOR:
7748 case XOR:
7749 {
7750 rtx op0 = XEXP (SET_SRC (pat), 0);
7751 rtx op1 = XEXP (SET_SRC (pat), 1);
7752 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7753 return 0;
7754 if (GET_CODE (op1) == CONST_INT)
7755 return INTVAL (op1) >= 0;
7756 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
284d86e9 7757 }
284d86e9
JC		 7758 case LSHIFTRT:
7759 return GET_MODE (SET_SRC (pat)) == SImode;
80ffc95e 7760 /* Positive integers leave the high bits zero. */
284d86e9 7761 case CONST_DOUBLE:
4df1190a 7762 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
284d86e9 7763 case CONST_INT:
4df1190a 7764 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
284d86e9
JC		 7765 case ASHIFTRT:
7766 case SIGN_EXTEND:
7767 return - (GET_MODE (SET_SRC (pat)) == SImode);
4df1190a
JJ		 7768 case REG:
7769 return sparc_check_64 (SET_SRC (pat), insn);
284d86e9
JC		 7770 default:
7771 return 0;
7772 }
7773}
7774
80ffc95e 7775/* We _ought_ to have only one kind per function, but... */
e2500fed
GK		 7776static GTY(()) rtx sparc_addr_diff_list;
7777static GTY(()) rtx sparc_addr_list;
e0d80184
DM		 7778
7779void
fc27d102 7780sparc_defer_case_vector (rtx lab, rtx vec, int diff)
e0d80184
DM		 7781{
7782 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7783 if (diff)
7784 sparc_addr_diff_list
7785 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7786 else
7787 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7788}
7789
4900aa61 7790static void
fc27d102 7791sparc_output_addr_vec (rtx vec)
e0d80184
DM		 7792{
7793 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7794 int idx, vlen = XVECLEN (body, 0);
7795
4900aa61 7796#ifdef ASM_OUTPUT_ADDR_VEC_START
d1accaa3
JJ		 7797 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7798#endif
7799
e0d80184
DM		 7800#ifdef ASM_OUTPUT_CASE_LABEL
7801 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7802 NEXT_INSN (lab));
7803#else
4977bab6 7804 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
e0d80184
DM		 7805#endif
7806
7807 for (idx = 0; idx < vlen; idx++)
7808 {
7809 ASM_OUTPUT_ADDR_VEC_ELT
7810 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7811 }
4900aa61 7812
d1accaa3
JJ		 7813#ifdef ASM_OUTPUT_ADDR_VEC_END
7814 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7815#endif
e0d80184
DM		 7816}
7817
4900aa61 7818static void
fc27d102 7819sparc_output_addr_diff_vec (rtx vec)
e0d80184
DM		 7820{
7821 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7822 rtx base = XEXP (XEXP (body, 0), 0);
7823 int idx, vlen = XVECLEN (body, 1);
7824
4900aa61 7825#ifdef ASM_OUTPUT_ADDR_VEC_START
d1accaa3
JJ		 7826 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7827#endif
7828
e0d80184
DM		 7829#ifdef ASM_OUTPUT_CASE_LABEL
7830 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7831 NEXT_INSN (lab));
7832#else
4977bab6 7833 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
e0d80184
DM		 7834#endif
7835
7836 for (idx = 0; idx < vlen; idx++)
7837 {
7838 ASM_OUTPUT_ADDR_DIFF_ELT
7839 (asm_out_file,
7840 body,
7841 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7842 CODE_LABEL_NUMBER (base));
7843 }
4900aa61 7844
d1accaa3
JJ		 7845#ifdef ASM_OUTPUT_ADDR_VEC_END
7846 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7847#endif
e0d80184
DM		 7848}
7849
7850static void
fc27d102 7851sparc_output_deferred_case_vectors (void)
e0d80184
DM		 7852{
7853 rtx t;
d676da68 7854 int align;
e0d80184 7855
f3b8847b
DM		 7856 if (sparc_addr_list == NULL_RTX
7857 && sparc_addr_diff_list == NULL_RTX)
7858 return;
7859
e0d80184 7860 /* Align to cache line in the function's code section. */
d6b5193b 7861 switch_to_section (current_function_section ());
d676da68
DM		 7862
7863 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7864 if (align > 0)
f3b8847b 7865 ASM_OUTPUT_ALIGN (asm_out_file, align);
4900aa61 7866
e0d80184
DM		 7867 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7868 sparc_output_addr_vec (XEXP (t, 0));
7869 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7870 sparc_output_addr_diff_vec (XEXP (t, 0));
7871
7872 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7873}
7874
284d86e9
JC		 7875/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7876 unknown. Return 1 if the high bits are zero, -1 if the register is
7877 sign extended. */
7878int
fc27d102 7879sparc_check_64 (rtx x, rtx insn)
284d86e9
JC		 7880{
7881 /* If a register is set only once it is safe to ignore insns this
7882 code does not know how to handle. The loop will either recognize
7883 the single set and return the correct value or fail to recognize
7884 it and return 0. */
7885 int set_once = 0;
4df1190a
JJ		 7886 rtx y = x;
7887
f5f7d171 7888 gcc_assert (GET_CODE (x) == REG);
4df1190a
JJ		 7889
7890 if (GET_MODE (x) == DImode)
7891 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
284d86e9 7892
4df1190a 7893 if (flag_expensive_optimizations
b718216c 7894 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
284d86e9
JC		 7895 set_once = 1;
7896
7897 if (insn == 0)
d6f4ec51
KG		 7898 {
7899 if (set_once)
7900 insn = get_last_insn_anywhere ();
7901 else
7902 return 0;
7903 }
284d86e9 7904
d6f4ec51 7905 while ((insn = PREV_INSN (insn)))
284d86e9
JC		 7906 {
7907 switch (GET_CODE (insn))
7908 {
7909 case JUMP_INSN:
7910 case NOTE:
7911 break;
7912 case CODE_LABEL:
7913 case CALL_INSN:
7914 default:
7915 if (! set_once)
7916 return 0;
7917 break;
7918 case INSN:
7919 {
7920 rtx pat = PATTERN (insn);
7921 if (GET_CODE (pat) != SET)
7922 return 0;
7923 if (rtx_equal_p (x, SET_DEST (pat)))
4df1190a
JJ		 7924 return set_extends (insn);
7925 if (y && rtx_equal_p (y, SET_DEST (pat)))
7926 return set_extends (insn);
7927 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
284d86e9
JC		 7928 return 0;
7929 }
7930 }
7931 }
7932 return 0;
7933}
7934
01d3224a
EB		 7935/* Returns assembly code to perform a DImode shift using
7936 a 64-bit global or out register on SPARC-V8+. */
a6163c22
EB		 7937const char *
7938output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
284d86e9
JC		 7939{
7940 static char asm_code[60];
7941
01d3224a
EB		 7942 /* The scratch register is only required when the destination
7943 register is not a 64-bit global or out register. */
7944 if (which_alternative != 2)
284d86e9 7945 operands[3] = operands[0];
01d3224a 7946
1c8b4e29
EB		 7947 /* We can only shift by constants <= 63. */
7948 if (GET_CODE (operands[2]) == CONST_INT)
7949 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7950
c6b0465b
JC		 7951 if (GET_CODE (operands[1]) == CONST_INT)
7952 {
4df1190a 7953 output_asm_insn ("mov\t%1, %3", operands);
c6b0465b
JC		 7954 }
7955 else
7956 {
4df1190a 7957 output_asm_insn ("sllx\t%H1, 32, %3", operands);
c6b0465b 7958 if (sparc_check_64 (operands[1], insn) <= 0)
4df1190a
JJ		 7959 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7960 output_asm_insn ("or\t%L1, %3, %3", operands);
c6b0465b 7961 }
284d86e9
JC		 7962
7963 strcpy(asm_code, opcode);
01d3224a 7964
284d86e9 7965 if (which_alternative != 2)
4df1190a 7966 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
284d86e9 7967 else
4df1190a 7968 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
284d86e9 7969}
2be15d0f 7970\f
89a8b315
RH		 7971/* Output rtl to increment the profiler label LABELNO
7972 for profiling a function entry. */
2be15d0f
RH		 7973
7974void
fc27d102 7975sparc_profile_hook (int labelno)
2be15d0f
RH		 7976{
7977 char buf[32];
89a8b315 7978 rtx lab, fun;
2be15d0f 7979
89a8b315 7980 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
cc44abe6
DM		 7981 if (NO_PROFILE_COUNTERS)
7982 {
7983 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
7984 }
7985 else
7986 {
7987 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7988 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7989 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7990 }
2be15d0f 7991}
89a8b315 7992\f
d1ced155
EB		 7993/* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
7994
7c262518 7995static void
d1ced155
EB		 7996sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
7997 tree decl ATTRIBUTE_UNUSED)
7c262518
RH		 7998{
7999 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8000
8001 if (!(flags & SECTION_DEBUG))
8002 fputs (",#alloc", asm_out_file);
8003 if (flags & SECTION_WRITE)
8004 fputs (",#write", asm_out_file);
2f3321ca
EB		 8005 if (flags & SECTION_TLS)
8006 fputs (",#tls", asm_out_file);
7c262518
RH		 8007 if (flags & SECTION_CODE)
8008 fputs (",#execinstr", asm_out_file);
8009
8010 /* ??? Handle SECTION_BSS. */
8011
8012 fputc ('\n', asm_out_file);
8013}
f451b552 8014
60b85c4c 8015/* We do not allow indirect calls to be optimized into sibling calls.
951661a1
EB		 8016
8017 We cannot use sibling calls when delayed branches are disabled
8018 because they will likely require the call delay slot to be filled.
8019
60b85c4c 8020 Also, on SPARC 32-bit we cannot emit a sibling call when the
4977bab6
ZW		 8021 current function returns a structure. This is because the "unimp
8022 after call" convention would cause the callee to return to the
8023 wrong place. The generic code already disallows cases where the
8024 function being called returns a structure.
8025
8026 It may seem strange how this last case could occur. Usually there
8027 is code after the call which jumps to epilogue code which dumps the
8028 return value into the struct return area. That ought to invalidate
951661a1 8029 the sibling call right? Well, in the C++ case we can end up passing
4977bab6
ZW		 8030 the pointer to the struct return area to a constructor (which returns
8031 void) and then nothing else happens. Such a sibling call would look
1910440e
RS		 8032 valid without the added check here.
8033
8034 VxWorks PIC PLT entries require the global pointer to be initialized
8035 on entry. We therefore can't emit sibling calls to them. */
4977bab6 8036static bool
fc27d102 8037sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4977bab6 8038{
951661a1
EB		 8039 return (decl
8040 && flag_delayed_branch
e3b5732b 8041 && (TARGET_ARCH64 || ! cfun->returns_struct)
1910440e
RS		 8042 && !(TARGET_VXWORKS_RTP
8043 && flag_pic
8044 && !targetm.binds_local_p (decl)));
4977bab6 8045}
c15c90bb
ZW		 8046\f
8047/* libfunc renaming. */
8048#include "config/gofast.h"
8049
8050static void
8051sparc_init_libfuncs (void)
8052{
8053 if (TARGET_ARCH32)
8054 {
8055 /* Use the subroutines that Sun's library provides for integer
8056 multiply and divide. The `*' prevents an underscore from
8057 being prepended by the compiler. .umul is a little faster
ff482c8d 8058 than .mul. */
c15c90bb
ZW		 8059 set_optab_libfunc (smul_optab, SImode, "*.umul");
8060 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8061 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8062 set_optab_libfunc (smod_optab, SImode, "*.rem");
8063 set_optab_libfunc (umod_optab, SImode, "*.urem");
8064
8065 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8066 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8067 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8068 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8069 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8070 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8071
8072 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8073 is because with soft-float, the SFmode and DFmode sqrt
8074 instructions will be absent, and the compiler will notice and
8075 try to use the TFmode sqrt instruction for calls to the
8076 builtin function sqrt, but this fails. */
8077 if (TARGET_FPU)
8078 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8079
c9034561
ZW		 8080 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8081 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8082 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8083 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8084 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8085 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
c15c90bb 8086
85363ca0
ZW		 8087 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8088 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8089 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8090 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8091
8092 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8093 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8094 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9b336fa4 8095 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
c15c90bb 8096
45dcc026
JJ		 8097 if (DITF_CONVERSION_LIBFUNCS)
8098 {
8099 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8100 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8101 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9b336fa4 8102 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
45dcc026
JJ		 8103 }
8104
c15c90bb
ZW		 8105 if (SUN_CONVERSION_LIBFUNCS)
8106 {
85363ca0
ZW		 8107 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8108 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8109 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8110 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
c15c90bb
ZW		 8111 }
8112 }
8113 if (TARGET_ARCH64)
8114 {
8115 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8116 do not exist in the library. Make sure the compiler does not
8117 emit calls to them by accident. (It should always use the
8118 hardware instructions.) */
8119 set_optab_libfunc (smul_optab, SImode, 0);
8120 set_optab_libfunc (sdiv_optab, SImode, 0);
8121 set_optab_libfunc (udiv_optab, SImode, 0);
8122 set_optab_libfunc (smod_optab, SImode, 0);
8123 set_optab_libfunc (umod_optab, SImode, 0);
8124
8125 if (SUN_INTEGER_MULTIPLY_64)
8126 {
8127 set_optab_libfunc (smul_optab, DImode, "__mul64");
8128 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8129 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8130 set_optab_libfunc (smod_optab, DImode, "__rem64");
8131 set_optab_libfunc (umod_optab, DImode, "__urem64");
8132 }
8133
8134 if (SUN_CONVERSION_LIBFUNCS)
8135 {
85363ca0
ZW		 8136 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8137 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8138 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8139 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
c15c90bb
ZW		 8140 }
8141 }
4977bab6 8142
c15c90bb
ZW		 8143 gofast_maybe_init_libfuncs ();
8144}
8145\f
16f59241 8146#define def_builtin(NAME, CODE, TYPE) \
c79efc4d
RÁE		 8147 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
8148 NULL_TREE)
16f59241
JM		 8149
8150/* Implement the TARGET_INIT_BUILTINS target hook.
8151 Create builtin functions for special SPARC instructions. */
8152
8153static void
8154sparc_init_builtins (void)
8155{
8156 if (TARGET_VIS)
8157 sparc_vis_init_builtins ();
8158}
8159
8160/* Create builtin functions for VIS 1.0 instructions. */
8161
8162static void
8163sparc_vis_init_builtins (void)
8164{
8165 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
8166 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
8167 tree v4hi = build_vector_type (intHI_type_node, 4);
8168 tree v2hi = build_vector_type (intHI_type_node, 2);
8169 tree v2si = build_vector_type (intSI_type_node, 2);
8170
8171 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
8172 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
8173 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
8174 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
8175 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
8176 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
8177 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
8178 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
8179 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
8180 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
8181 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
8182 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
8183 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
8184 v8qi, v8qi,
8185 intDI_type_node, 0);
8186 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
8187 intDI_type_node,
8188 intDI_type_node, 0);
8189 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
8190 ptr_type_node,
8191 intSI_type_node, 0);
8192 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
8193 ptr_type_node,
8194 intDI_type_node, 0);
8195
8196 /* Packing and expanding vectors. */
8197 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
8198 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
8199 v8qi_ftype_v2si_v8qi);
8200 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
8201 v2hi_ftype_v2si);
8202 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
8203 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
8204 v8qi_ftype_v4qi_v4qi);
8205
8206 /* Multiplications. */
8207 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
8208 v4hi_ftype_v4qi_v4hi);
8209 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
8210 v4hi_ftype_v4qi_v2hi);
8211 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
8212 v4hi_ftype_v4qi_v2hi);
8213 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
8214 v4hi_ftype_v8qi_v4hi);
8215 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
8216 v4hi_ftype_v8qi_v4hi);
8217 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
8218 v2si_ftype_v4qi_v2hi);
8219 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
8220 v2si_ftype_v4qi_v2hi);
8221
8222 /* Data aligning. */
8223 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
8224 v4hi_ftype_v4hi_v4hi);
8225 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
8226 v8qi_ftype_v8qi_v8qi);
8227 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
8228 v2si_ftype_v2si_v2si);
8229 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
8230 di_ftype_di_di);
8231 if (TARGET_ARCH64)
8232 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
8233 ptr_ftype_ptr_di);
8234 else
8235 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
8236 ptr_ftype_ptr_si);
8237
8238 /* Pixel distance. */
8239 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
8240 di_ftype_v8qi_v8qi_di);
8241}
8242
8243/* Handle TARGET_EXPAND_BUILTIN target hook.
0fa2e4df 8244 Expand builtin functions for sparc intrinsics. */
16f59241
JM		 8245
8246static rtx
724d7c55
EB		 8247sparc_expand_builtin (tree exp, rtx target,
8248 rtx subtarget ATTRIBUTE_UNUSED,
8249 enum machine_mode tmode ATTRIBUTE_UNUSED,
8250 int ignore ATTRIBUTE_UNUSED)
16f59241 8251{
5039610b
SL		 8252 tree arg;
8253 call_expr_arg_iterator iter;
8254 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16f59241
JM		 8255 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
8256 rtx pat, op[4];
8257 enum machine_mode mode[4];
8258 int arg_count = 0;
8259
724d7c55
EB		 8260 mode[0] = insn_data[icode].operand[0].mode;
8261 if (!target
8262 || GET_MODE (target) != mode[0]
8263 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
8264 op[0] = gen_reg_rtx (mode[0]);
16f59241 8265 else
724d7c55 8266 op[0] = target;
16f59241 8267
5039610b 8268 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
16f59241 8269 {
16f59241
JM		 8270 arg_count++;
8271 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
84217346 8272 op[arg_count] = expand_normal (arg);
16f59241
JM		 8273
8274 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
8275 mode[arg_count]))
8276 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
8277 }
8278
8279 switch (arg_count)
8280 {
8281 case 1:
8282 pat = GEN_FCN (icode) (op[0], op[1]);
8283 break;
8284 case 2:
8285 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
8286 break;
8287 case 3:
8288 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
8289 break;
8290 default:
8291 gcc_unreachable ();
8292 }
8293
8294 if (!pat)
8295 return NULL_RTX;
8296
8297 emit_insn (pat);
8298
8299 return op[0];
8300}
8b0096b4
JM		 8301
8302static int
8303sparc_vis_mul8x16 (int e8, int e16)
8304{
8305 return (e8 * e16 + 128) / 256;
8306}
8307
8308/* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
8309 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
8310 constants. A tree list with the results of the multiplications is returned,
8311 and each element in the list is of INNER_TYPE. */
8312
8313static tree
8314sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
8315{
8316 tree n_elts = NULL_TREE;
8317 int scale;
8318
8319 switch (fncode)
8320 {
8321 case CODE_FOR_fmul8x16_vis:
8322 for (; elts0 && elts1;
8323 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8324 {
8325 int val
8326 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8327 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
8328 n_elts = tree_cons (NULL_TREE,
8329 build_int_cst (inner_type, val),
8330 n_elts);
8331 }
8332 break;
8333
8334 case CODE_FOR_fmul8x16au_vis:
8335 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
8336
8337 for (; elts0; elts0 = TREE_CHAIN (elts0))
8338 {
8339 int val
8340 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8341 scale);
8342 n_elts = tree_cons (NULL_TREE,
8343 build_int_cst (inner_type, val),
8344 n_elts);
8345 }
8346 break;
8347
8348 case CODE_FOR_fmul8x16al_vis:
8349 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
8350
8351 for (; elts0; elts0 = TREE_CHAIN (elts0))
8352 {
8353 int val
8354 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8355 scale);
8356 n_elts = tree_cons (NULL_TREE,
8357 build_int_cst (inner_type, val),
8358 n_elts);
8359 }
8360 break;
8361
8362 default:
8363 gcc_unreachable ();
8364 }
8365
8366 return nreverse (n_elts);
8367
8368}
8369/* Handle TARGET_FOLD_BUILTIN target hook.
607fb860 8370 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
8b0096b4
JM		 8371 result of the function call is ignored. NULL_TREE is returned if the
8372 function could not be folded. */
8373
8374static tree
f311c3b4
NF		 8375sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
8376 tree *args, bool ignore)
8b0096b4
JM		 8377{
8378 tree arg0, arg1, arg2;
8379 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
bbbbb16a 8380 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
8b0096b4 8381
724d7c55 8382 if (ignore
bbbbb16a
ILT		 8383 && icode != CODE_FOR_alignaddrsi_vis
8384 && icode != CODE_FOR_alignaddrdi_vis)
724d7c55 8385 return fold_convert (rtype, integer_zero_node);
8b0096b4 8386
bbbbb16a 8387 switch (icode)
8b0096b4
JM		 8388 {
8389 case CODE_FOR_fexpand_vis:
f311c3b4 8390 arg0 = args[0];
8b0096b4
JM		 8391 STRIP_NOPS (arg0);
8392
8393 if (TREE_CODE (arg0) == VECTOR_CST)
8394 {
8395 tree inner_type = TREE_TYPE (rtype);
8396 tree elts = TREE_VECTOR_CST_ELTS (arg0);
8397 tree n_elts = NULL_TREE;
8398
8399 for (; elts; elts = TREE_CHAIN (elts))
8400 {
8401 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
8402 n_elts = tree_cons (NULL_TREE,
8403 build_int_cst (inner_type, val),
8404 n_elts);
8405 }
8406 return build_vector (rtype, nreverse (n_elts));
8407 }
8408 break;
8409
8410 case CODE_FOR_fmul8x16_vis:
8411 case CODE_FOR_fmul8x16au_vis:
8412 case CODE_FOR_fmul8x16al_vis:
f311c3b4
NF		 8413 arg0 = args[0];
8414 arg1 = args[1];
8b0096b4
JM		 8415 STRIP_NOPS (arg0);
8416 STRIP_NOPS (arg1);
8417
8418 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
8419 {
8420 tree inner_type = TREE_TYPE (rtype);
8421 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8422 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
bbbbb16a
ILT		 8423 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
8424 elts1);
8b0096b4
JM		 8425
8426 return build_vector (rtype, n_elts);
8427 }
8428 break;
8429
8430 case CODE_FOR_fpmerge_vis:
f311c3b4
NF		 8431 arg0 = args[0];
8432 arg1 = args[1];
8b0096b4
JM		 8433 STRIP_NOPS (arg0);
8434 STRIP_NOPS (arg1);
8435
8436 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
8437 {
8438 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8439 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8440 tree n_elts = NULL_TREE;
8441
8442 for (; elts0 && elts1;
8443 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8444 {
8445 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
8446 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
8447 }
8448
8449 return build_vector (rtype, nreverse (n_elts));
8450 }
8451 break;
8452
8453 case CODE_FOR_pdist_vis:
f311c3b4
NF		 8454 arg0 = args[0];
8455 arg1 = args[1];
8456 arg2 = args[2];
8b0096b4
JM		 8457 STRIP_NOPS (arg0);
8458 STRIP_NOPS (arg1);
8459 STRIP_NOPS (arg2);
8460
8461 if (TREE_CODE (arg0) == VECTOR_CST
8462 && TREE_CODE (arg1) == VECTOR_CST
8463 && TREE_CODE (arg2) == INTEGER_CST)
8464 {
8465 int overflow = 0;
8466 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
8467 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
8468 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8469 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8470
8471 for (; elts0 && elts1;
8472 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8473 {
8474 unsigned HOST_WIDE_INT
8475 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8476 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
8477 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
8478 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
8479
8480 unsigned HOST_WIDE_INT l;
8481 HOST_WIDE_INT h;
8482
8483 overflow |= neg_double (low1, high1, &l, &h);
8484 overflow |= add_double (low0, high0, l, h, &l, &h);
8485 if (h < 0)
8486 overflow |= neg_double (l, h, &l, &h);
8487
8488 overflow |= add_double (low, high, l, h, &low, &high);
8489 }
8490
8491 gcc_assert (overflow == 0);
8492
8493 return build_int_cst_wide (rtype, low, high);
8494 }
8495
8496 default:
8497 break;
8498 }
724d7c55 8499
8b0096b4
JM		 8500 return NULL_TREE;
8501}
16f59241 8502\f
214c6394
DM		 8503/* ??? This duplicates information provided to the compiler by the
8504 ??? scheduler description. Some day, teach genautomata to output
8505 ??? the latencies and then CSE will just use that. */
8506
3c50106f 8507static bool
f40751dd
JH		 8508sparc_rtx_costs (rtx x, int code, int outer_code, int *total,
8509 bool speed ATTRIBUTE_UNUSED)
2ce04b6b 8510{
18df6de9
DM		 8511 enum machine_mode mode = GET_MODE (x);
8512 bool float_mode_p = FLOAT_MODE_P (mode);
8513
2ce04b6b
DM		 8514 switch (code)
8515 {
18df6de9
DM		 8516 case CONST_INT:
8517 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
214c6394 8518 {
18df6de9 8519 *total = 0;
3c50106f 8520 return true;
214c6394 8521 }
18df6de9 8522 /* FALLTHRU */
214c6394 8523
18df6de9
DM		 8524 case HIGH:
8525 *total = 2;
8526 return true;
214c6394 8527
18df6de9
DM		 8528 case CONST:
8529 case LABEL_REF:
8530 case SYMBOL_REF:
8531 *total = 4;
8532 return true;
214c6394 8533
18df6de9 8534 case CONST_DOUBLE:
ca075703
DM		 8535 if (GET_MODE (x) == VOIDmode
8536 && ((CONST_DOUBLE_HIGH (x) == 0
8537 && CONST_DOUBLE_LOW (x) < 0x1000)
8538 || (CONST_DOUBLE_HIGH (x) == -1
8539 && CONST_DOUBLE_LOW (x) < 0
8540 && CONST_DOUBLE_LOW (x) >= -0x1000)))
18df6de9
DM		 8541 *total = 0;
8542 else
8543 *total = 8;
3c50106f 8544 return true;
214c6394 8545
18df6de9
DM		 8546 case MEM:
8547 /* If outer-code was a sign or zero extension, a cost
8548 of COSTS_N_INSNS (1) was already added in. This is
8549 why we are subtracting it back out. */
8550 if (outer_code == ZERO_EXTEND)
214c6394 8551 {
18df6de9 8552 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
214c6394 8553 }
18df6de9 8554 else if (outer_code == SIGN_EXTEND)
3c50106f 8555 {
18df6de9 8556 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
3c50106f 8557 }
18df6de9 8558 else if (float_mode_p)
3c50106f 8559 {
18df6de9 8560 *total = sparc_costs->float_load;
3c50106f 8561 }
18df6de9 8562 else
3c50106f 8563 {
18df6de9 8564 *total = sparc_costs->int_load;
3c50106f 8565 }
214c6394 8566
3c50106f 8567 return true;
2ce04b6b 8568
18df6de9
DM		 8569 case PLUS:
8570 case MINUS:
8571 if (float_mode_p)
8572 *total = sparc_costs->float_plusminus;
8573 else
8574 *total = COSTS_N_INSNS (1);
8575 return false;
214c6394 8576
18df6de9
DM		 8577 case MULT:
8578 if (float_mode_p)
8579 *total = sparc_costs->float_mul;
e08eb33c 8580 else if (! TARGET_HARD_MUL)
bf6c40e9 8581 *total = COSTS_N_INSNS (25);
18df6de9
DM		 8582 else
8583 {
8584 int bit_cost;
214c6394 8585
18df6de9
DM		 8586 bit_cost = 0;
8587 if (sparc_costs->int_mul_bit_factor)
8588 {
8589 int nbits;
214c6394 8590
18df6de9
DM		 8591 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8592 {
8593 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8594 for (nbits = 0; value != 0; value &= value - 1)
8595 nbits++;
8596 }
8597 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
ca075703 8598 && GET_MODE (XEXP (x, 1)) == VOIDmode)
18df6de9
DM		 8599 {
8600 rtx x1 = XEXP (x, 1);
ca075703
DM		 8601 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
8602 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
18df6de9
DM		 8603
8604 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8605 nbits++;
8606 for (; value2 != 0; value2 &= value2 - 1)
8607 nbits++;
8608 }
214c6394 8609 else
18df6de9 8610 nbits = 7;
214c6394 8611
18df6de9
DM		 8612 if (nbits < 3)
8613 nbits = 3;
8614 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
ffe384ff 8615 bit_cost = COSTS_N_INSNS (bit_cost);
214c6394 8616 }
18df6de9
DM		 8617
8618 if (mode == DImode)
ffe384ff 8619 *total = sparc_costs->int_mulX + bit_cost;
18df6de9 8620 else
ffe384ff 8621 *total = sparc_costs->int_mul + bit_cost;
214c6394 8622 }
18df6de9 8623 return false;
214c6394 8624
18df6de9
DM		 8625 case ASHIFT:
8626 case ASHIFTRT:
8627 case LSHIFTRT:
8628 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8629 return false;
2ce04b6b 8630
18df6de9
DM		 8631 case DIV:
8632 case UDIV:
8633 case MOD:
8634 case UMOD:
8635 if (float_mode_p)
214c6394 8636 {
18df6de9
DM		 8637 if (mode == DFmode)
8638 *total = sparc_costs->float_div_df;
214c6394 8639 else
18df6de9 8640 *total = sparc_costs->float_div_sf;
214c6394 8641 }
18df6de9 8642 else
214c6394 8643 {
18df6de9
DM		 8644 if (mode == DImode)
8645 *total = sparc_costs->int_divX;
214c6394 8646 else
18df6de9 8647 *total = sparc_costs->int_div;
214c6394 8648 }
18df6de9 8649 return false;
2ce04b6b 8650
18df6de9
DM		 8651 case NEG:
8652 if (! float_mode_p)
3c50106f 8653 {
18df6de9
DM		 8654 *total = COSTS_N_INSNS (1);
8655 return false;
3c50106f 8656 }
5efb1046 8657 /* FALLTHRU */
2ce04b6b 8658
18df6de9
DM		 8659 case ABS:
8660 case FLOAT:
8661 case UNSIGNED_FLOAT:
8662 case FIX:
8663 case UNSIGNED_FIX:
8664 case FLOAT_EXTEND:
8665 case FLOAT_TRUNCATE:
8666 *total = sparc_costs->float_move;
8667 return false;
2ce04b6b 8668
18df6de9
DM		 8669 case SQRT:
8670 if (mode == DFmode)
8671 *total = sparc_costs->float_sqrt_df;
8672 else
8673 *total = sparc_costs->float_sqrt_sf;
8674 return false;
2ce04b6b 8675
18df6de9
DM		 8676 case COMPARE:
8677 if (float_mode_p)
8678 *total = sparc_costs->float_cmp;
3c50106f 8679 else
18df6de9
DM		 8680 *total = COSTS_N_INSNS (1);
8681 return false;
8682
8683 case IF_THEN_ELSE:
8684 if (float_mode_p)
8685 *total = sparc_costs->float_cmove;
8686 else
8687 *total = sparc_costs->int_cmove;
8688 return false;
2ce04b6b 8689
893e18a5
JM		 8690 case IOR:
8691 /* Handle the NAND vector patterns. */
8692 if (sparc_vector_mode_supported_p (GET_MODE (x))
8693 && GET_CODE (XEXP (x, 0)) == NOT
8694 && GET_CODE (XEXP (x, 1)) == NOT)
8695 {
8696 *total = COSTS_N_INSNS (1);
8697 return true;
8698 }
8699 else
8700 return false;
8701
2ce04b6b 8702 default:
3c50106f
RH		 8703 return false;
8704 }
2ce04b6b 8705}
fb49053f 8706
68ba34f3
AS		 8707/* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
8708 This is achieved by means of a manual dynamic stack space allocation in
8709 the current frame. We make the assumption that SEQ doesn't contain any
8710 function calls, with the possible exception of calls to the PIC helper. */
951661a1
EB		 8711
8712static void
1b970c28 8713emit_and_preserve (rtx seq, rtx reg, rtx reg2)
951661a1 8714{
68ba34f3
AS		 8715 /* We must preserve the lowest 16 words for the register save area. */
8716 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
8717 /* We really need only 2 words of fresh stack space. */
8718 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
951661a1 8719
68ba34f3
AS		 8720 rtx slot
8721 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
8722 SPARC_STACK_BIAS + offset));
8723
8724 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
951661a1 8725 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
1b970c28
EB		 8726 if (reg2)
8727 emit_insn (gen_rtx_SET (VOIDmode,
8728 adjust_address (slot, word_mode, UNITS_PER_WORD),
8729 reg2));
951661a1 8730 emit_insn (seq);
1b970c28
EB		 8731 if (reg2)
8732 emit_insn (gen_rtx_SET (VOIDmode,
8733 reg2,
8734 adjust_address (slot, word_mode, UNITS_PER_WORD)));
951661a1 8735 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
68ba34f3 8736 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
951661a1
EB		 8737}
8738
b9bf58e5
EB		 8739/* Output the assembler code for a thunk function. THUNK_DECL is the
8740 declaration for the thunk function itself, FUNCTION is the decl for
8741 the target function. DELTA is an immediate constant offset to be
8742 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8743 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
e133041b 8744
c590b625 8745static void
fc27d102 8746sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
b9bf58e5 8747 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
fc27d102 8748 tree function)
e133041b 8749{
0a2aaacc 8750 rtx this_rtx, insn, funexp;
951661a1 8751 unsigned int int_arg_first;
e133041b
RH		 8752
8753 reload_completed = 1;
fe3ad572 8754 epilogue_completed = 1;
e133041b 8755
2e040219 8756 emit_note (NOTE_INSN_PROLOGUE_END);
e133041b 8757
951661a1
EB		 8758 if (flag_delayed_branch)
8759 {
8760 /* We will emit a regular sibcall below, so we need to instruct
8761 output_sibcall that we are in a leaf function. */
22d66adf 8762 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
951661a1
EB		 8763
8764 /* This will cause final.c to invoke leaf_renumber_regs so we
8765 must behave as if we were in a not-yet-leafified function. */
8766 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8767 }
8768 else
8769 {
8770 /* We will emit the sibcall manually below, so we will need to
8771 manually spill non-leaf registers. */
22d66adf 8772 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
951661a1
EB		 8773
8774 /* We really are in a leaf function. */
8775 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8776 }
8777
e133041b
RH		 8778 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8779 returns a structure, the structure return pointer is there instead. */
4900aa61
EB		 8780 if (TARGET_ARCH64
8781 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
0a2aaacc 8782 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
e133041b 8783 else
0a2aaacc 8784 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
e133041b
RH		 8785
8786 /* Add DELTA. When possible use a plain add, otherwise load it into
8787 a register first. */
b9bf58e5 8788 if (delta)
e133041b 8789 {
b9bf58e5
EB		 8790 rtx delta_rtx = GEN_INT (delta);
8791
8792 if (! SPARC_SIMM13_P (delta))
8793 {
8794 rtx scratch = gen_rtx_REG (Pmode, 1);
8795 emit_move_insn (scratch, delta_rtx);
8796 delta_rtx = scratch;
8797 }
8798
0a2aaacc
KG		 8799 /* THIS_RTX += DELTA. */
8800 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
b9bf58e5
EB		 8801 }
8802
0a2aaacc 8803 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
b9bf58e5
EB		 8804 if (vcall_offset)
8805 {
8806 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
e133041b 8807 rtx scratch = gen_rtx_REG (Pmode, 1);
ed1fe829 8808
f5f7d171 8809 gcc_assert (vcall_offset < 0);
b9bf58e5 8810
0a2aaacc
KG		 8811 /* SCRATCH = *THIS_RTX. */
8812 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
b9bf58e5
EB		 8813
8814 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8815 may not have any available scratch register at this point. */
8816 if (SPARC_SIMM13_P (vcall_offset))
8817 ;
8818 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8819 else if (! fixed_regs[5]
8820 /* The below sequence is made up of at least 2 insns,
8821 while the default method may need only one. */
8822 && vcall_offset < -8192)
8823 {
8824 rtx scratch2 = gen_rtx_REG (Pmode, 5);
8825 emit_move_insn (scratch2, vcall_offset_rtx);
8826 vcall_offset_rtx = scratch2;
8827 }
e133041b 8828 else
ed1fe829 8829 {
b9bf58e5
EB		 8830 rtx increment = GEN_INT (-4096);
8831
8832 /* VCALL_OFFSET is a negative number whose typical range can be
8833 estimated as -32768..0 in 32-bit mode. In almost all cases
8834 it is therefore cheaper to emit multiple add insns than
8835 spilling and loading the constant into a register (at least
8836 6 insns). */
8837 while (! SPARC_SIMM13_P (vcall_offset))
8838 {
8839 emit_insn (gen_add2_insn (scratch, increment));
8840 vcall_offset += 4096;
8841 }
8842 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
ed1fe829
EB		 8843 }
8844
0a2aaacc 8845 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
b9bf58e5
EB		 8846 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
8847 gen_rtx_PLUS (Pmode,
8848 scratch,
8849 vcall_offset_rtx)));
e133041b 8850
0a2aaacc
KG		 8851 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
8852 emit_insn (gen_add2_insn (this_rtx, scratch));
b9bf58e5 8853 }
e133041b
RH		 8854
8855 /* Generate a tail call to the target function. */
8856 if (! TREE_USED (function))
8857 {
8858 assemble_external (function);
8859 TREE_USED (function) = 1;
8860 }
8861 funexp = XEXP (DECL_RTL (function), 0);
951661a1
EB		 8862
8863 if (flag_delayed_branch)
8864 {
8865 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8866 insn = emit_call_insn (gen_sibcall (funexp));
8867 SIBLING_CALL_P (insn) = 1;
8868 }
8869 else
8870 {
8871 /* The hoops we have to jump through in order to generate a sibcall
8872 without using delay slots... */
1b970c28 8873 rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1);
951661a1
EB		 8874
8875 if (flag_pic)
8876 {
8877 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
1b970c28 8878 spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
951661a1 8879 start_sequence ();
5e77eb53
EB		 8880 /* Delay emitting the PIC helper function because it needs to
8881 change the section and we are emitting assembly code. */
9fd52c6c 8882 load_pic_register (); /* clobbers %o7 */
208384fd 8883 scratch = legitimize_pic_address (funexp, scratch);
951661a1
EB		 8884 seq = get_insns ();
8885 end_sequence ();
1b970c28 8886 emit_and_preserve (seq, spill_reg, spill_reg2);
951661a1
EB		 8887 }
8888 else if (TARGET_ARCH32)
8889 {
8890 emit_insn (gen_rtx_SET (VOIDmode,
8891 scratch,
8892 gen_rtx_HIGH (SImode, funexp)));
8893 emit_insn (gen_rtx_SET (VOIDmode,
8894 scratch,
8895 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8896 }
8897 else /* TARGET_ARCH64 */
8898 {
8899 switch (sparc_cmodel)
8900 {
8901 case CM_MEDLOW:
8902 case CM_MEDMID:
8903 /* The destination can serve as a temporary. */
8904 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8905 break;
8906
8907 case CM_MEDANY:
8908 case CM_EMBMEDANY:
8909 /* The destination cannot serve as a temporary. */
8910 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8911 start_sequence ();
8912 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8913 seq = get_insns ();
8914 end_sequence ();
1b970c28 8915 emit_and_preserve (seq, spill_reg, 0);
951661a1
EB		 8916 break;
8917
8918 default:
f5f7d171 8919 gcc_unreachable ();
951661a1
EB		 8920 }
8921 }
8922
8923 emit_jump_insn (gen_indirect_jump (scratch));
8924 }
8925
e133041b
RH		 8926 emit_barrier ();
8927
8928 /* Run just enough of rest_of_compilation to get the insns emitted.
8929 There's not really enough bulk here to make other passes such as
8930 instruction scheduling worth while. Note that use_thunk calls
8931 assemble_start_function and assemble_end_function. */
8932 insn = get_insns ();
55e092c4 8933 insn_locators_alloc ();
e133041b
RH		 8934 shorten_branches (insn);
8935 final_start_function (insn, file, 1);
c9d691e9 8936 final (insn, file, 1);
e133041b
RH		 8937 final_end_function ();
8938
8939 reload_completed = 0;
fe3ad572 8940 epilogue_completed = 0;
e133041b 8941}
e2500fed 8942
b9bf58e5
EB		 8943/* Return true if sparc_output_mi_thunk would be able to output the
8944 assembler code for the thunk function specified by the arguments
8945 it is passed, and false otherwise. */
8946static bool
3101faab 8947sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
b9bf58e5
EB		 8948 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
8949 HOST_WIDE_INT vcall_offset,
3101faab 8950 const_tree function ATTRIBUTE_UNUSED)
b9bf58e5
EB		 8951{
8952 /* Bound the loop used in the default method above. */
8953 return (vcall_offset >= -32768 || ! fixed_regs[5]);
8954}
8955
5751a10b
JJ		 8956/* How to allocate a 'struct machine_function'. */
8957
8958static struct machine_function *
8959sparc_init_machine_status (void)
8960{
5ead67f6 8961 return GGC_CNEW (struct machine_function);
5751a10b
JJ		 8962}
8963
8964/* Locate some local-dynamic symbol still in use by this function
8965 so that we can print its name in local-dynamic base patterns. */
8966
8967static const char *
8968get_some_local_dynamic_name (void)
8969{
8970 rtx insn;
8971
8972 if (cfun->machine->some_ld_name)
8973 return cfun->machine->some_ld_name;
8974
8975 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8976 if (INSN_P (insn)
8977 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8978 return cfun->machine->some_ld_name;
8979
f5f7d171 8980 gcc_unreachable ();
5751a10b
JJ		 8981}
8982
8983static int
8984get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8985{
8986 rtx x = *px;
8987
8988 if (x
8989 && GET_CODE (x) == SYMBOL_REF
8990 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8991 {
8992 cfun->machine->some_ld_name = XSTR (x, 0);
8993 return 1;
8994 }
8995
8996 return 0;
8997}
8998
e54c7471
EB		 8999/* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
9000 This is called from dwarf2out.c to emit call frame instructions
9001 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
9002static void
9003sparc_dwarf_handle_frame_unspec (const char *label,
9004 rtx pattern ATTRIBUTE_UNUSED,
9005 int index ATTRIBUTE_UNUSED)
9006{
9007 gcc_assert (index == UNSPECV_SAVEW);
9008 dwarf2out_window_save (label);
9009}
9010
fdbe66f2 9011/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5751a10b
JJ		 9012 We need to emit DTP-relative relocations. */
9013
fdbe66f2 9014static void
5751a10b
JJ		 9015sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9016{
9017 switch (size)
9018 {
9019 case 4:
9020 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9021 break;
9022 case 8:
9023 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9024 break;
9025 default:
f5f7d171 9026 gcc_unreachable ();
5751a10b
JJ		 9027 }
9028 output_addr_const (file, x);
9029 fputs (")", file);
9030}
9031
fdbe66f2
EB		 9032/* Do whatever processing is required at the end of a file. */
9033
9034static void
9035sparc_file_end (void)
5e77eb53 9036{
9fd52c6c
DM		 9037 /* If need to emit the special PIC helper function, do so now. */
9038 if (pic_helper_needed)
9039 {
9040 unsigned int regno = REGNO (pic_offset_table_rtx);
9041 const char *pic_name = reg_names[regno];
9042 char name[32];
9043#ifdef DWARF2_UNWIND_INFO
9044 bool do_cfi;
9045#endif
9046
9047 get_pc_thunk_name (name, regno);
9048 if (USE_HIDDEN_LINKONCE)
9049 {
9050 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
9051 get_identifier (name),
9052 build_function_type (void_type_node,
9053 void_list_node));
9054 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
9055 NULL_TREE, void_type_node);
9056 TREE_STATIC (decl) = 1;
9057 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
9058 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
9059 DECL_VISIBILITY_SPECIFIED (decl) = 1;
9060 allocate_struct_function (decl, true);
9061 current_function_decl = decl;
9062 init_varasm_status ();
9063 assemble_start_function (decl, name);
9064 }
9065 else
9066 {
9067 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9068 switch_to_section (text_section);
9069 if (align > 0)
9070 ASM_OUTPUT_ALIGN (asm_out_file, align);
9071 ASM_OUTPUT_LABEL (asm_out_file, name);
9072 }
9073
9074#ifdef DWARF2_UNWIND_INFO
9075 do_cfi = dwarf2out_do_cfi_asm ();
9076 if (do_cfi)
9077 fprintf (asm_out_file, "\t.cfi_startproc\n");
9078#endif
9079 if (flag_delayed_branch)
9080 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
9081 pic_name, pic_name);
9082 else
9083 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
9084 pic_name, pic_name);
9085#ifdef DWARF2_UNWIND_INFO
9086 if (do_cfi)
9087 fprintf (asm_out_file, "\t.cfi_endproc\n");
9088#endif
9089 }
5e77eb53
EB		 9090
9091 if (NEED_INDICATE_EXEC_STACK)
9092 file_end_indicate_exec_stack ();
9093}
9094
7269aee7 9095#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3 9096/* Implement TARGET_MANGLE_TYPE. */
7269aee7
AH		 9097
9098static const char *
3101faab 9099sparc_mangle_type (const_tree type)
7269aee7
AH		 9100{
9101 if (!TARGET_64BIT
9102 && TYPE_MAIN_VARIANT (type) == long_double_type_node
9103 && TARGET_LONG_DOUBLE_128)
9104 return "g";
9105
9106 /* For all other types, use normal C++ mangling. */
9107 return NULL;
9108}
9109#endif
9110
396b535a
JJ		 9111/* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
9112 compare and swap on the word containing the byte or half-word. */
9113
9114void
9115sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
9116{
9117 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
9118 rtx addr = gen_reg_rtx (Pmode);
9119 rtx off = gen_reg_rtx (SImode);
9120 rtx oldv = gen_reg_rtx (SImode);
9121 rtx newv = gen_reg_rtx (SImode);
9122 rtx oldvalue = gen_reg_rtx (SImode);
9123 rtx newvalue = gen_reg_rtx (SImode);
9124 rtx res = gen_reg_rtx (SImode);
9125 rtx resv = gen_reg_rtx (SImode);
9126 rtx memsi, val, mask, end_label, loop_label, cc;
9127
9128 emit_insn (gen_rtx_SET (VOIDmode, addr,
9129 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
9130
9131 if (Pmode != SImode)
9132 addr1 = gen_lowpart (SImode, addr1);
9133 emit_insn (gen_rtx_SET (VOIDmode, off,
9134 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
9135
9136 memsi = gen_rtx_MEM (SImode, addr);
44d64274 9137 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
396b535a
JJ		 9138 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
9139
9140 val = force_reg (SImode, memsi);
9141
9142 emit_insn (gen_rtx_SET (VOIDmode, off,
9143 gen_rtx_XOR (SImode, off,
9144 GEN_INT (GET_MODE (mem) == QImode
9145 ? 3 : 2))));
9146
9147 emit_insn (gen_rtx_SET (VOIDmode, off,
9148 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
9149
9150 if (GET_MODE (mem) == QImode)
9151 mask = force_reg (SImode, GEN_INT (0xff));
9152 else
9153 mask = force_reg (SImode, GEN_INT (0xffff));
9154
9155 emit_insn (gen_rtx_SET (VOIDmode, mask,
9156 gen_rtx_ASHIFT (SImode, mask, off)));
9157
9158 emit_insn (gen_rtx_SET (VOIDmode, val,
9159 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
9160 val)));
9161
9162 oldval = gen_lowpart (SImode, oldval);
9163 emit_insn (gen_rtx_SET (VOIDmode, oldv,
9164 gen_rtx_ASHIFT (SImode, oldval, off)));
9165
9166 newval = gen_lowpart_common (SImode, newval);
9167 emit_insn (gen_rtx_SET (VOIDmode, newv,
9168 gen_rtx_ASHIFT (SImode, newval, off)));
9169
9170 emit_insn (gen_rtx_SET (VOIDmode, oldv,
9171 gen_rtx_AND (SImode, oldv, mask)));
9172
9173 emit_insn (gen_rtx_SET (VOIDmode, newv,
9174 gen_rtx_AND (SImode, newv, mask)));
9175
9176 end_label = gen_label_rtx ();
9177 loop_label = gen_label_rtx ();
9178 emit_label (loop_label);
9179
9180 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
9181 gen_rtx_IOR (SImode, oldv, val)));
9182
9183 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
9184 gen_rtx_IOR (SImode, newv, val)));
9185
9186 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
9187
9188 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
9189
9190 emit_insn (gen_rtx_SET (VOIDmode, resv,
9191 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
9192 res)));
9193
f90b7a5a 9194 cc = gen_compare_reg_1 (NE, resv, val);
396b535a
JJ		 9195 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
9196
f90b7a5a
PB		 9197 /* Use cbranchcc4 to separate the compare and branch! */
9198 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
9199 cc, const0_rtx, loop_label));
396b535a
JJ		 9200
9201 emit_label (end_label);
9202
9203 emit_insn (gen_rtx_SET (VOIDmode, res,
9204 gen_rtx_AND (SImode, res, mask)));
9205
9206 emit_insn (gen_rtx_SET (VOIDmode, res,
9207 gen_rtx_LSHIFTRT (SImode, res, off)));
9208
9209 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
9210}
9211
b52b1749
AS		 9212/* Implement TARGET_FRAME_POINTER_REQUIRED. */
9213
9214bool
9215sparc_frame_pointer_required (void)
9216{
9217 return !(leaf_function_p () && only_leaf_regs_used ());
9218}
9219
9220/* The way this is structured, we can't eliminate SFP in favor of SP
9221 if the frame pointer is required: we want to use the SFP->HFP elimination
9222 in that case. But the test in update_eliminables doesn't know we are
9223 assuming below that we only do the former elimination. */
9224
9225bool
9226sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9227{
4900aa61 9228 return (to == HARD_FRAME_POINTER_REGNUM
b52b1749
AS		 9229 || !targetm.frame_pointer_required ());
9230}
9231
e2500fed 9232#include "gt-sparc.h"
Mirror of https://gcc.gnu.org/git/gcc.git