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8c660648 | 1 | /* Instruction scheduling pass. |
a5cad800 | 2 | Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc. |
8c660648 JL |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
4 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, but | |
14 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to the Free | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | ||
24 | /* Instruction scheduling pass. | |
25 | ||
26 | This pass implements list scheduling within basic blocks. It is | |
27 | run twice: (1) after flow analysis, but before register allocation, | |
28 | and (2) after register allocation. | |
29 | ||
30 | The first run performs interblock scheduling, moving insns between | |
31 | different blocks in the same "region", and the second runs only | |
32 | basic block scheduling. | |
33 | ||
34 | Interblock motions performed are useful motions and speculative | |
35 | motions, including speculative loads. Motions requiring code | |
36 | duplication are not supported. The identification of motion type | |
37 | and the check for validity of speculative motions requires | |
38 | construction and analysis of the function's control flow graph. | |
39 | The scheduler works as follows: | |
40 | ||
41 | We compute insn priorities based on data dependencies. Flow | |
42 | analysis only creates a fraction of the data-dependencies we must | |
43 | observe: namely, only those dependencies which the combiner can be | |
44 | expected to use. For this pass, we must therefore create the | |
45 | remaining dependencies we need to observe: register dependencies, | |
46 | memory dependencies, dependencies to keep function calls in order, | |
47 | and the dependence between a conditional branch and the setting of | |
48 | condition codes are all dealt with here. | |
49 | ||
50 | The scheduler first traverses the data flow graph, starting with | |
51 | the last instruction, and proceeding to the first, assigning values | |
52 | to insn_priority as it goes. This sorts the instructions | |
53 | topologically by data dependence. | |
54 | ||
55 | Once priorities have been established, we order the insns using | |
56 | list scheduling. This works as follows: starting with a list of | |
57 | all the ready insns, and sorted according to priority number, we | |
58 | schedule the insn from the end of the list by placing its | |
59 | predecessors in the list according to their priority order. We | |
60 | consider this insn scheduled by setting the pointer to the "end" of | |
61 | the list to point to the previous insn. When an insn has no | |
62 | predecessors, we either queue it until sufficient time has elapsed | |
63 | or add it to the ready list. As the instructions are scheduled or | |
64 | when stalls are introduced, the queue advances and dumps insns into | |
65 | the ready list. When all insns down to the lowest priority have | |
66 | been scheduled, the critical path of the basic block has been made | |
67 | as short as possible. The remaining insns are then scheduled in | |
68 | remaining slots. | |
69 | ||
70 | Function unit conflicts are resolved during forward list scheduling | |
71 | by tracking the time when each insn is committed to the schedule | |
72 | and from that, the time the function units it uses must be free. | |
73 | As insns on the ready list are considered for scheduling, those | |
74 | that would result in a blockage of the already committed insns are | |
75 | queued until no blockage will result. | |
76 | ||
77 | The following list shows the order in which we want to break ties | |
78 | among insns in the ready list: | |
79 | ||
80 | 1. choose insn with the longest path to end of bb, ties | |
81 | broken by | |
82 | 2. choose insn with least contribution to register pressure, | |
83 | ties broken by | |
84 | 3. prefer in-block upon interblock motion, ties broken by | |
85 | 4. prefer useful upon speculative motion, ties broken by | |
86 | 5. choose insn with largest control flow probability, ties | |
87 | broken by | |
88 | 6. choose insn with the least dependences upon the previously | |
89 | scheduled insn, or finally | |
2db45993 JL |
90 | 7 choose the insn which has the most insns dependent on it. |
91 | 8. choose insn with lowest UID. | |
8c660648 JL |
92 | |
93 | Memory references complicate matters. Only if we can be certain | |
94 | that memory references are not part of the data dependency graph | |
95 | (via true, anti, or output dependence), can we move operations past | |
96 | memory references. To first approximation, reads can be done | |
97 | independently, while writes introduce dependencies. Better | |
98 | approximations will yield fewer dependencies. | |
99 | ||
100 | Before reload, an extended analysis of interblock data dependences | |
101 | is required for interblock scheduling. This is performed in | |
102 | compute_block_backward_dependences (). | |
103 | ||
104 | Dependencies set up by memory references are treated in exactly the | |
105 | same way as other dependencies, by using LOG_LINKS backward | |
106 | dependences. LOG_LINKS are translated into INSN_DEPEND forward | |
107 | dependences for the purpose of forward list scheduling. | |
108 | ||
109 | Having optimized the critical path, we may have also unduly | |
110 | extended the lifetimes of some registers. If an operation requires | |
111 | that constants be loaded into registers, it is certainly desirable | |
112 | to load those constants as early as necessary, but no earlier. | |
113 | I.e., it will not do to load up a bunch of registers at the | |
114 | beginning of a basic block only to use them at the end, if they | |
115 | could be loaded later, since this may result in excessive register | |
116 | utilization. | |
117 | ||
118 | Note that since branches are never in basic blocks, but only end | |
119 | basic blocks, this pass will not move branches. But that is ok, | |
120 | since we can use GNU's delayed branch scheduling pass to take care | |
121 | of this case. | |
122 | ||
123 | Also note that no further optimizations based on algebraic | |
124 | identities are performed, so this pass would be a good one to | |
125 | perform instruction splitting, such as breaking up a multiply | |
126 | instruction into shifts and adds where that is profitable. | |
127 | ||
128 | Given the memory aliasing analysis that this pass should perform, | |
129 | it should be possible to remove redundant stores to memory, and to | |
130 | load values from registers instead of hitting memory. | |
131 | ||
132 | Before reload, speculative insns are moved only if a 'proof' exists | |
133 | that no exception will be caused by this, and if no live registers | |
134 | exist that inhibit the motion (live registers constraints are not | |
135 | represented by data dependence edges). | |
136 | ||
137 | This pass must update information that subsequent passes expect to | |
138 | be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, | |
3b413743 RH |
139 | reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD, |
140 | BLOCK_END. | |
8c660648 JL |
141 | |
142 | The information in the line number notes is carefully retained by | |
143 | this pass. Notes that refer to the starting and ending of | |
144 | exception regions are also carefully retained by this pass. All | |
145 | other NOTE insns are grouped in their same relative order at the | |
146 | beginning of basic blocks and regions that have been scheduled. | |
147 | ||
148 | The main entry point for this pass is schedule_insns(), called for | |
149 | each function. The work of the scheduler is organized in three | |
150 | levels: (1) function level: insns are subject to splitting, | |
151 | control-flow-graph is constructed, regions are computed (after | |
152 | reload, each region is of one block), (2) region level: control | |
153 | flow graph attributes required for interblock scheduling are | |
154 | computed (dominators, reachability, etc.), data dependences and | |
155 | priorities are computed, and (3) block level: insns in the block | |
156 | are actually scheduled. */ | |
157 | \f | |
8c660648 | 158 | #include "config.h" |
5835e573 | 159 | #include "system.h" |
8c660648 JL |
160 | #include "rtl.h" |
161 | #include "basic-block.h" | |
162 | #include "regs.h" | |
163 | #include "hard-reg-set.h" | |
164 | #include "flags.h" | |
165 | #include "insn-config.h" | |
166 | #include "insn-attr.h" | |
167 | #include "except.h" | |
487a6e06 | 168 | #include "toplev.h" |
79c9824e | 169 | #include "recog.h" |
8c660648 JL |
170 | |
171 | extern char *reg_known_equiv_p; | |
172 | extern rtx *reg_known_value; | |
173 | ||
174 | #ifdef INSN_SCHEDULING | |
175 | ||
8c660648 JL |
176 | /* target_units bitmask has 1 for each unit in the cpu. It should be |
177 | possible to compute this variable from the machine description. | |
178 | But currently it is computed by examinning the insn list. Since | |
179 | this is only needed for visualization, it seems an acceptable | |
180 | solution. (For understanding the mapping of bits to units, see | |
181 | definition of function_units[] in "insn-attrtab.c") */ | |
182 | ||
61822835 | 183 | static int target_units = 0; |
8c660648 JL |
184 | |
185 | /* issue_rate is the number of insns that can be scheduled in the same | |
186 | machine cycle. It can be defined in the config/mach/mach.h file, | |
187 | otherwise we set it to 1. */ | |
188 | ||
189 | static int issue_rate; | |
190 | ||
62d65906 JL |
191 | #ifndef ISSUE_RATE |
192 | #define ISSUE_RATE 1 | |
8c660648 JL |
193 | #endif |
194 | ||
cc132865 | 195 | /* sched-verbose controls the amount of debugging output the |
8c660648 JL |
196 | scheduler prints. It is controlled by -fsched-verbose-N: |
197 | N>0 and no -DSR : the output is directed to stderr. | |
198 | N>=10 will direct the printouts to stderr (regardless of -dSR). | |
199 | N=1: same as -dSR. | |
200 | N=2: bb's probabilities, detailed ready list info, unit/insn info. | |
201 | N=3: rtl at abort point, control-flow, regions info. | |
cc132865 | 202 | N=5: dependences info. */ |
8c660648 JL |
203 | |
204 | #define MAX_RGN_BLOCKS 10 | |
205 | #define MAX_RGN_INSNS 100 | |
206 | ||
8c660648 JL |
207 | static int sched_verbose_param = 0; |
208 | static int sched_verbose = 0; | |
8c660648 JL |
209 | |
210 | /* nr_inter/spec counts interblock/speculative motion for the function */ | |
211 | static int nr_inter, nr_spec; | |
212 | ||
213 | ||
214 | /* debugging file. all printouts are sent to dump, which is always set, | |
215 | either to stderr, or to the dump listing file (-dRS). */ | |
216 | static FILE *dump = 0; | |
217 | ||
218 | /* fix_sched_param() is called from toplev.c upon detection | |
219 | of the -fsched-***-N options. */ | |
220 | ||
221 | void | |
222 | fix_sched_param (param, val) | |
223 | char *param, *val; | |
224 | { | |
cc132865 | 225 | if (!strcmp (param, "verbose")) |
8c660648 | 226 | sched_verbose_param = atoi (val); |
8c660648 JL |
227 | else |
228 | warning ("fix_sched_param: unknown param: %s", param); | |
229 | } | |
230 | ||
231 | ||
232 | /* Arrays set up by scheduling for the same respective purposes as | |
233 | similar-named arrays set up by flow analysis. We work with these | |
234 | arrays during the scheduling pass so we can compare values against | |
235 | unscheduled code. | |
236 | ||
237 | Values of these arrays are copied at the end of this pass into the | |
238 | arrays set up by flow analysis. */ | |
239 | static int *sched_reg_n_calls_crossed; | |
240 | static int *sched_reg_live_length; | |
241 | static int *sched_reg_basic_block; | |
242 | ||
243 | /* We need to know the current block number during the post scheduling | |
244 | update of live register information so that we can also update | |
245 | REG_BASIC_BLOCK if a register changes blocks. */ | |
246 | static int current_block_num; | |
247 | ||
248 | /* Element N is the next insn that sets (hard or pseudo) register | |
249 | N within the current basic block; or zero, if there is no | |
250 | such insn. Needed for new registers which may be introduced | |
251 | by splitting insns. */ | |
252 | static rtx *reg_last_uses; | |
253 | static rtx *reg_last_sets; | |
254 | static regset reg_pending_sets; | |
255 | static int reg_pending_sets_all; | |
256 | ||
257 | /* Vector indexed by INSN_UID giving the original ordering of the insns. */ | |
258 | static int *insn_luid; | |
259 | #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)]) | |
260 | ||
261 | /* Vector indexed by INSN_UID giving each instruction a priority. */ | |
262 | static int *insn_priority; | |
263 | #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)]) | |
264 | ||
265 | static short *insn_costs; | |
266 | #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)] | |
267 | ||
268 | /* Vector indexed by INSN_UID giving an encoding of the function units | |
269 | used. */ | |
270 | static short *insn_units; | |
271 | #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)] | |
272 | ||
273 | /* Vector indexed by INSN_UID giving each instruction a register-weight. | |
274 | This weight is an estimation of the insn contribution to registers pressure. */ | |
275 | static int *insn_reg_weight; | |
276 | #define INSN_REG_WEIGHT(INSN) (insn_reg_weight[INSN_UID (INSN)]) | |
277 | ||
278 | /* Vector indexed by INSN_UID giving list of insns which | |
279 | depend upon INSN. Unlike LOG_LINKS, it represents forward dependences. */ | |
280 | static rtx *insn_depend; | |
281 | #define INSN_DEPEND(INSN) insn_depend[INSN_UID (INSN)] | |
282 | ||
283 | /* Vector indexed by INSN_UID. Initialized to the number of incoming | |
284 | edges in forward dependence graph (= number of LOG_LINKS). As | |
285 | scheduling procedes, dependence counts are decreased. An | |
286 | instruction moves to the ready list when its counter is zero. */ | |
287 | static int *insn_dep_count; | |
288 | #define INSN_DEP_COUNT(INSN) (insn_dep_count[INSN_UID (INSN)]) | |
289 | ||
290 | /* Vector indexed by INSN_UID giving an encoding of the blockage range | |
291 | function. The unit and the range are encoded. */ | |
292 | static unsigned int *insn_blockage; | |
293 | #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)] | |
294 | #define UNIT_BITS 5 | |
295 | #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) | |
296 | #define ENCODE_BLOCKAGE(U, R) \ | |
297 | ((((U) << UNIT_BITS) << BLOCKAGE_BITS \ | |
298 | | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ | |
299 | | MAX_BLOCKAGE_COST (R)) | |
300 | #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) | |
301 | #define BLOCKAGE_RANGE(B) \ | |
302 | (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ | |
5835e573 | 303 | | ((B) & BLOCKAGE_MASK)) |
8c660648 JL |
304 | |
305 | /* Encodings of the `<name>_unit_blockage_range' function. */ | |
306 | #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) | |
307 | #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) | |
308 | ||
309 | #define DONE_PRIORITY -1 | |
310 | #define MAX_PRIORITY 0x7fffffff | |
311 | #define TAIL_PRIORITY 0x7ffffffe | |
312 | #define LAUNCH_PRIORITY 0x7f000001 | |
313 | #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) | |
314 | #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) | |
315 | ||
316 | /* Vector indexed by INSN_UID giving number of insns referring to this insn. */ | |
317 | static int *insn_ref_count; | |
318 | #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)]) | |
319 | ||
320 | /* Vector indexed by INSN_UID giving line-number note in effect for each | |
321 | insn. For line-number notes, this indicates whether the note may be | |
322 | reused. */ | |
323 | static rtx *line_note; | |
324 | #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)]) | |
325 | ||
326 | /* Vector indexed by basic block number giving the starting line-number | |
327 | for each basic block. */ | |
328 | static rtx *line_note_head; | |
329 | ||
330 | /* List of important notes we must keep around. This is a pointer to the | |
331 | last element in the list. */ | |
332 | static rtx note_list; | |
333 | ||
334 | /* Regsets telling whether a given register is live or dead before the last | |
335 | scheduled insn. Must scan the instructions once before scheduling to | |
336 | determine what registers are live or dead at the end of the block. */ | |
337 | static regset bb_live_regs; | |
338 | ||
339 | /* Regset telling whether a given register is live after the insn currently | |
340 | being scheduled. Before processing an insn, this is equal to bb_live_regs | |
341 | above. This is used so that we can find registers that are newly born/dead | |
342 | after processing an insn. */ | |
343 | static regset old_live_regs; | |
344 | ||
345 | /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns | |
346 | during the initial scan and reused later. If there are not exactly as | |
347 | many REG_DEAD notes in the post scheduled code as there were in the | |
348 | prescheduled code then we trigger an abort because this indicates a bug. */ | |
349 | static rtx dead_notes; | |
350 | ||
351 | /* Queues, etc. */ | |
352 | ||
353 | /* An instruction is ready to be scheduled when all insns preceding it | |
354 | have already been scheduled. It is important to ensure that all | |
355 | insns which use its result will not be executed until its result | |
356 | has been computed. An insn is maintained in one of four structures: | |
357 | ||
358 | (P) the "Pending" set of insns which cannot be scheduled until | |
359 | their dependencies have been satisfied. | |
360 | (Q) the "Queued" set of insns that can be scheduled when sufficient | |
361 | time has passed. | |
362 | (R) the "Ready" list of unscheduled, uncommitted insns. | |
363 | (S) the "Scheduled" list of insns. | |
364 | ||
365 | Initially, all insns are either "Pending" or "Ready" depending on | |
366 | whether their dependencies are satisfied. | |
367 | ||
368 | Insns move from the "Ready" list to the "Scheduled" list as they | |
369 | are committed to the schedule. As this occurs, the insns in the | |
370 | "Pending" list have their dependencies satisfied and move to either | |
371 | the "Ready" list or the "Queued" set depending on whether | |
372 | sufficient time has passed to make them ready. As time passes, | |
373 | insns move from the "Queued" set to the "Ready" list. Insns may | |
374 | move from the "Ready" list to the "Queued" set if they are blocked | |
375 | due to a function unit conflict. | |
376 | ||
377 | The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled | |
378 | insns, i.e., those that are ready, queued, and pending. | |
379 | The "Queued" set (Q) is implemented by the variable `insn_queue'. | |
380 | The "Ready" list (R) is implemented by the variables `ready' and | |
381 | `n_ready'. | |
382 | The "Scheduled" list (S) is the new insn chain built by this pass. | |
383 | ||
384 | The transition (R->S) is implemented in the scheduling loop in | |
385 | `schedule_block' when the best insn to schedule is chosen. | |
386 | The transition (R->Q) is implemented in `queue_insn' when an | |
38e01259 | 387 | insn is found to have a function unit conflict with the already |
8c660648 JL |
388 | committed insns. |
389 | The transitions (P->R and P->Q) are implemented in `schedule_insn' as | |
390 | insns move from the ready list to the scheduled list. | |
391 | The transition (Q->R) is implemented in 'queue_to_insn' as time | |
392 | passes or stalls are introduced. */ | |
393 | ||
394 | /* Implement a circular buffer to delay instructions until sufficient | |
395 | time has passed. INSN_QUEUE_SIZE is a power of two larger than | |
396 | MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the | |
397 | longest time an isnsn may be queued. */ | |
398 | static rtx insn_queue[INSN_QUEUE_SIZE]; | |
399 | static int q_ptr = 0; | |
400 | static int q_size = 0; | |
401 | #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) | |
402 | #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1)) | |
403 | ||
404 | /* Vector indexed by INSN_UID giving the minimum clock tick at which | |
405 | the insn becomes ready. This is used to note timing constraints for | |
406 | insns in the pending list. */ | |
407 | static int *insn_tick; | |
408 | #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)]) | |
409 | ||
410 | /* Data structure for keeping track of register information | |
411 | during that register's life. */ | |
412 | ||
413 | struct sometimes | |
414 | { | |
415 | int regno; | |
416 | int live_length; | |
417 | int calls_crossed; | |
418 | }; | |
419 | ||
420 | /* Forward declarations. */ | |
421 | static void add_dependence PROTO ((rtx, rtx, enum reg_note)); | |
422 | static void remove_dependence PROTO ((rtx, rtx)); | |
423 | static rtx find_insn_list PROTO ((rtx, rtx)); | |
424 | static int insn_unit PROTO ((rtx)); | |
425 | static unsigned int blockage_range PROTO ((int, rtx)); | |
426 | static void clear_units PROTO ((void)); | |
427 | static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int)); | |
428 | static void schedule_unit PROTO ((int, rtx, int)); | |
429 | static int actual_hazard PROTO ((int, rtx, int, int)); | |
430 | static int potential_hazard PROTO ((int, rtx, int)); | |
431 | static int insn_cost PROTO ((rtx, rtx, rtx)); | |
432 | static int priority PROTO ((rtx)); | |
433 | static void free_pending_lists PROTO ((void)); | |
434 | static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx)); | |
435 | static void flush_pending_lists PROTO ((rtx, int)); | |
436 | static void sched_analyze_1 PROTO ((rtx, rtx)); | |
437 | static void sched_analyze_2 PROTO ((rtx, rtx)); | |
438 | static void sched_analyze_insn PROTO ((rtx, rtx, rtx)); | |
439 | static void sched_analyze PROTO ((rtx, rtx)); | |
5835e573 | 440 | static void sched_note_set PROTO ((rtx, int)); |
01c7f350 | 441 | static int rank_for_schedule PROTO ((const GENERIC_PTR, const GENERIC_PTR)); |
8c660648 JL |
442 | static void swap_sort PROTO ((rtx *, int)); |
443 | static void queue_insn PROTO ((rtx, int)); | |
444 | static int schedule_insn PROTO ((rtx, rtx *, int, int)); | |
445 | static void create_reg_dead_note PROTO ((rtx, rtx)); | |
446 | static void attach_deaths PROTO ((rtx, rtx, int)); | |
447 | static void attach_deaths_insn PROTO ((rtx)); | |
448 | static int new_sometimes_live PROTO ((struct sometimes *, int, int)); | |
449 | static void finish_sometimes_live PROTO ((struct sometimes *, int)); | |
5835e573 | 450 | static int schedule_block PROTO ((int, int)); |
5835e573 | 451 | static void split_hard_reg_notes PROTO ((rtx, rtx, rtx)); |
8c660648 JL |
452 | static void new_insn_dead_notes PROTO ((rtx, rtx, rtx, rtx)); |
453 | static void update_n_sets PROTO ((rtx, int)); | |
459b3825 | 454 | static char *safe_concat PROTO ((char *, char *, char *)); |
cc4fe0e2 L |
455 | static int insn_issue_delay PROTO ((rtx)); |
456 | static int birthing_insn_p PROTO ((rtx)); | |
457 | static void adjust_priority PROTO ((rtx)); | |
8c660648 JL |
458 | |
459 | /* Mapping of insns to their original block prior to scheduling. */ | |
460 | static int *insn_orig_block; | |
461 | #define INSN_BLOCK(insn) (insn_orig_block[INSN_UID (insn)]) | |
462 | ||
463 | /* Some insns (e.g. call) are not allowed to move across blocks. */ | |
464 | static char *cant_move; | |
465 | #define CANT_MOVE(insn) (cant_move[INSN_UID (insn)]) | |
466 | ||
467 | /* Control flow graph edges are kept in circular lists. */ | |
468 | typedef struct | |
469 | { | |
470 | int from_block; | |
471 | int to_block; | |
472 | int next_in; | |
473 | int next_out; | |
474 | } | |
475 | edge; | |
476 | static edge *edge_table; | |
477 | ||
478 | #define NEXT_IN(edge) (edge_table[edge].next_in) | |
479 | #define NEXT_OUT(edge) (edge_table[edge].next_out) | |
480 | #define FROM_BLOCK(edge) (edge_table[edge].from_block) | |
481 | #define TO_BLOCK(edge) (edge_table[edge].to_block) | |
482 | ||
483 | /* Number of edges in the control flow graph. (in fact larger than | |
484 | that by 1, since edge 0 is unused.) */ | |
485 | static int nr_edges; | |
486 | ||
487 | /* Circular list of incoming/outgoing edges of a block */ | |
488 | static int *in_edges; | |
489 | static int *out_edges; | |
490 | ||
491 | #define IN_EDGES(block) (in_edges[block]) | |
492 | #define OUT_EDGES(block) (out_edges[block]) | |
493 | ||
494 | /* List of labels which cannot be deleted, needed for control | |
495 | flow graph construction. */ | |
496 | extern rtx forced_labels; | |
497 | ||
498 | ||
168cbdf9 | 499 | static int is_cfg_nonregular PROTO ((void)); |
a2e68776 JL |
500 | static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *, |
501 | int *, int *)); | |
8c660648 JL |
502 | static void new_edge PROTO ((int, int)); |
503 | ||
504 | ||
505 | /* A region is the main entity for interblock scheduling: insns | |
506 | are allowed to move between blocks in the same region, along | |
507 | control flow graph edges, in the 'up' direction. */ | |
508 | typedef struct | |
509 | { | |
510 | int rgn_nr_blocks; /* number of blocks in region */ | |
511 | int rgn_blocks; /* blocks in the region (actually index in rgn_bb_table) */ | |
512 | } | |
513 | region; | |
514 | ||
515 | /* Number of regions in the procedure */ | |
516 | static int nr_regions; | |
517 | ||
518 | /* Table of region descriptions */ | |
519 | static region *rgn_table; | |
520 | ||
521 | /* Array of lists of regions' blocks */ | |
522 | static int *rgn_bb_table; | |
523 | ||
524 | /* Topological order of blocks in the region (if b2 is reachable from | |
525 | b1, block_to_bb[b2] > block_to_bb[b1]). | |
526 | Note: A basic block is always referred to by either block or b, | |
527 | while its topological order name (in the region) is refered to by | |
528 | bb. | |
529 | */ | |
530 | static int *block_to_bb; | |
531 | ||
532 | /* The number of the region containing a block. */ | |
533 | static int *containing_rgn; | |
534 | ||
535 | #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks) | |
536 | #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks) | |
537 | #define BLOCK_TO_BB(block) (block_to_bb[block]) | |
538 | #define CONTAINING_RGN(block) (containing_rgn[block]) | |
539 | ||
540 | void debug_regions PROTO ((void)); | |
541 | static void find_single_block_region PROTO ((void)); | |
a2e68776 JL |
542 | static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *, |
543 | int *, int *, sbitmap *)); | |
8c660648 JL |
544 | static int too_large PROTO ((int, int *, int *)); |
545 | ||
546 | extern void debug_live PROTO ((int, int)); | |
547 | ||
548 | /* Blocks of the current region being scheduled. */ | |
549 | static int current_nr_blocks; | |
550 | static int current_blocks; | |
551 | ||
552 | /* The mapping from bb to block */ | |
553 | #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)]) | |
554 | ||
555 | ||
556 | /* Bit vectors and bitset operations are needed for computations on | |
557 | the control flow graph. */ | |
558 | ||
559 | typedef unsigned HOST_WIDE_INT *bitset; | |
560 | typedef struct | |
561 | { | |
562 | int *first_member; /* pointer to the list start in bitlst_table. */ | |
563 | int nr_members; /* the number of members of the bit list. */ | |
564 | } | |
565 | bitlst; | |
566 | ||
61822835 JL |
567 | static int bitlst_table_last; |
568 | static int bitlst_table_size; | |
8c660648 JL |
569 | static int *bitlst_table; |
570 | ||
571 | static char bitset_member PROTO ((bitset, int, int)); | |
572 | static void extract_bitlst PROTO ((bitset, int, bitlst *)); | |
573 | ||
574 | /* target info declarations. | |
575 | ||
576 | The block currently being scheduled is referred to as the "target" block, | |
577 | while other blocks in the region from which insns can be moved to the | |
578 | target are called "source" blocks. The candidate structure holds info | |
579 | about such sources: are they valid? Speculative? Etc. */ | |
580 | typedef bitlst bblst; | |
581 | typedef struct | |
582 | { | |
583 | char is_valid; | |
584 | char is_speculative; | |
585 | int src_prob; | |
586 | bblst split_bbs; | |
587 | bblst update_bbs; | |
588 | } | |
589 | candidate; | |
590 | ||
591 | static candidate *candidate_table; | |
592 | ||
593 | /* A speculative motion requires checking live information on the path | |
594 | from 'source' to 'target'. The split blocks are those to be checked. | |
595 | After a speculative motion, live information should be modified in | |
596 | the 'update' blocks. | |
597 | ||
598 | Lists of split and update blocks for each candidate of the current | |
599 | target are in array bblst_table */ | |
61822835 | 600 | static int *bblst_table, bblst_size, bblst_last; |
8c660648 JL |
601 | |
602 | #define IS_VALID(src) ( candidate_table[src].is_valid ) | |
603 | #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative ) | |
604 | #define SRC_PROB(src) ( candidate_table[src].src_prob ) | |
605 | ||
606 | /* The bb being currently scheduled. */ | |
61822835 | 607 | static int target_bb; |
8c660648 JL |
608 | |
609 | /* List of edges. */ | |
610 | typedef bitlst edgelst; | |
611 | ||
612 | /* target info functions */ | |
613 | static void split_edges PROTO ((int, int, edgelst *)); | |
614 | static void compute_trg_info PROTO ((int)); | |
615 | void debug_candidate PROTO ((int)); | |
616 | void debug_candidates PROTO ((int)); | |
617 | ||
618 | ||
619 | /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */ | |
620 | typedef bitset bbset; | |
621 | ||
622 | /* Number of words of the bbset. */ | |
61822835 | 623 | static int bbset_size; |
8c660648 JL |
624 | |
625 | /* Dominators array: dom[i] contains the bbset of dominators of | |
626 | bb i in the region. */ | |
61822835 | 627 | static bbset *dom; |
8c660648 JL |
628 | |
629 | /* bb 0 is the only region entry */ | |
630 | #define IS_RGN_ENTRY(bb) (!bb) | |
631 | ||
632 | /* Is bb_src dominated by bb_trg. */ | |
633 | #define IS_DOMINATED(bb_src, bb_trg) \ | |
634 | ( bitset_member (dom[bb_src], bb_trg, bbset_size) ) | |
635 | ||
636 | /* Probability: Prob[i] is a float in [0, 1] which is the probability | |
637 | of bb i relative to the region entry. */ | |
61822835 | 638 | static float *prob; |
8c660648 JL |
639 | |
640 | /* The probability of bb_src, relative to bb_trg. Note, that while the | |
641 | 'prob[bb]' is a float in [0, 1], this macro returns an integer | |
642 | in [0, 100]. */ | |
643 | #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \ | |
644 | prob[bb_trg]))) | |
645 | ||
646 | /* Bit-set of edges, where bit i stands for edge i. */ | |
647 | typedef bitset edgeset; | |
648 | ||
649 | /* Number of edges in the region. */ | |
61822835 | 650 | static int rgn_nr_edges; |
8c660648 JL |
651 | |
652 | /* Array of size rgn_nr_edges. */ | |
61822835 | 653 | static int *rgn_edges; |
8c660648 JL |
654 | |
655 | /* Number of words in an edgeset. */ | |
61822835 | 656 | static int edgeset_size; |
8c660648 JL |
657 | |
658 | /* Mapping from each edge in the graph to its number in the rgn. */ | |
61822835 | 659 | static int *edge_to_bit; |
8c660648 JL |
660 | #define EDGE_TO_BIT(edge) (edge_to_bit[edge]) |
661 | ||
662 | /* The split edges of a source bb is different for each target | |
663 | bb. In order to compute this efficiently, the 'potential-split edges' | |
664 | are computed for each bb prior to scheduling a region. This is actually | |
665 | the split edges of each bb relative to the region entry. | |
666 | ||
667 | pot_split[bb] is the set of potential split edges of bb. */ | |
61822835 | 668 | static edgeset *pot_split; |
8c660648 JL |
669 | |
670 | /* For every bb, a set of its ancestor edges. */ | |
61822835 | 671 | static edgeset *ancestor_edges; |
8c660648 JL |
672 | |
673 | static void compute_dom_prob_ps PROTO ((int)); | |
674 | ||
675 | #define ABS_VALUE(x) (((x)<0)?(-(x)):(x)) | |
676 | #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (INSN_BLOCK (INSN)))) | |
677 | #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (INSN_BLOCK (INSN)))) | |
678 | #define INSN_BB(INSN) (BLOCK_TO_BB (INSN_BLOCK (INSN))) | |
679 | ||
680 | /* parameters affecting the decision of rank_for_schedule() */ | |
681 | #define MIN_DIFF_PRIORITY 2 | |
682 | #define MIN_PROBABILITY 40 | |
683 | #define MIN_PROB_DIFF 10 | |
684 | ||
685 | /* speculative scheduling functions */ | |
686 | static int check_live_1 PROTO ((int, rtx)); | |
687 | static void update_live_1 PROTO ((int, rtx)); | |
5835e573 KG |
688 | static int check_live PROTO ((rtx, int)); |
689 | static void update_live PROTO ((rtx, int)); | |
8c660648 JL |
690 | static void set_spec_fed PROTO ((rtx)); |
691 | static int is_pfree PROTO ((rtx, int, int)); | |
692 | static int find_conditional_protection PROTO ((rtx, int)); | |
693 | static int is_conditionally_protected PROTO ((rtx, int, int)); | |
694 | static int may_trap_exp PROTO ((rtx, int)); | |
ac957f13 | 695 | static int haifa_classify_insn PROTO ((rtx)); |
e009aaf3 | 696 | static int is_prisky PROTO ((rtx, int, int)); |
8c660648 JL |
697 | static int is_exception_free PROTO ((rtx, int, int)); |
698 | ||
699 | static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx)); | |
700 | static void compute_block_forward_dependences PROTO ((int)); | |
701 | static void init_rgn_data_dependences PROTO ((int)); | |
702 | static void add_branch_dependences PROTO ((rtx, rtx)); | |
703 | static void compute_block_backward_dependences PROTO ((int)); | |
704 | void debug_dependencies PROTO ((void)); | |
705 | ||
706 | /* Notes handling mechanism: | |
707 | ========================= | |
708 | Generally, NOTES are saved before scheduling and restored after scheduling. | |
709 | The scheduler distinguishes between three types of notes: | |
710 | ||
711 | (1) LINE_NUMBER notes, generated and used for debugging. Here, | |
712 | before scheduling a region, a pointer to the LINE_NUMBER note is | |
713 | added to the insn following it (in save_line_notes()), and the note | |
714 | is removed (in rm_line_notes() and unlink_line_notes()). After | |
715 | scheduling the region, this pointer is used for regeneration of | |
716 | the LINE_NUMBER note (in restore_line_notes()). | |
717 | ||
718 | (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes: | |
719 | Before scheduling a region, a pointer to the note is added to the insn | |
720 | that follows or precedes it. (This happens as part of the data dependence | |
721 | computation). After scheduling an insn, the pointer contained in it is | |
722 | used for regenerating the corresponding note (in reemit_notes). | |
723 | ||
724 | (3) All other notes (e.g. INSN_DELETED): Before scheduling a block, | |
725 | these notes are put in a list (in rm_other_notes() and | |
726 | unlink_other_notes ()). After scheduling the block, these notes are | |
727 | inserted at the beginning of the block (in schedule_block()). */ | |
728 | ||
729 | static rtx unlink_other_notes PROTO ((rtx, rtx)); | |
730 | static rtx unlink_line_notes PROTO ((rtx, rtx)); | |
731 | static void rm_line_notes PROTO ((int)); | |
732 | static void save_line_notes PROTO ((int)); | |
733 | static void restore_line_notes PROTO ((int)); | |
734 | static void rm_redundant_line_notes PROTO ((void)); | |
735 | static void rm_other_notes PROTO ((rtx, rtx)); | |
736 | static rtx reemit_notes PROTO ((rtx, rtx)); | |
737 | ||
738 | static void get_block_head_tail PROTO ((int, rtx *, rtx *)); | |
739 | ||
740 | static void find_pre_sched_live PROTO ((int)); | |
741 | static void find_post_sched_live PROTO ((int)); | |
742 | static void update_reg_usage PROTO ((void)); | |
c6a754f2 | 743 | static int queue_to_ready PROTO ((rtx [], int)); |
8c660648 | 744 | |
9a8b0889 | 745 | static void debug_ready_list PROTO ((rtx[], int)); |
cc4fe0e2 | 746 | static void init_target_units PROTO ((void)); |
8c660648 | 747 | static void insn_print_units PROTO ((rtx)); |
cc4fe0e2 L |
748 | static int get_visual_tbl_length PROTO ((void)); |
749 | static void init_block_visualization PROTO ((void)); | |
8c660648 JL |
750 | static void print_block_visualization PROTO ((int, char *)); |
751 | static void visualize_scheduled_insns PROTO ((int, int)); | |
752 | static void visualize_no_unit PROTO ((rtx)); | |
753 | static void visualize_stall_cycles PROTO ((int, int)); | |
754 | static void print_exp PROTO ((char *, rtx, int)); | |
755 | static void print_value PROTO ((char *, rtx, int)); | |
756 | static void print_pattern PROTO ((char *, rtx, int)); | |
757 | static void print_insn PROTO ((char *, rtx, int)); | |
758 | void debug_reg_vector PROTO ((regset)); | |
759 | ||
760 | static rtx move_insn1 PROTO ((rtx, rtx)); | |
761 | static rtx move_insn PROTO ((rtx, rtx)); | |
762 | static rtx group_leader PROTO ((rtx)); | |
763 | static int set_priorities PROTO ((int)); | |
764 | static void init_rtx_vector PROTO ((rtx **, rtx *, int, int)); | |
765 | static void schedule_region PROTO ((int)); | |
8c660648 JL |
766 | |
767 | #endif /* INSN_SCHEDULING */ | |
768 | \f | |
769 | #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) | |
770 | ||
771 | /* Helper functions for instruction scheduling. */ | |
772 | ||
ebb7b10b RH |
773 | /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */ |
774 | static rtx unused_insn_list; | |
775 | ||
776 | /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */ | |
777 | static rtx unused_expr_list; | |
778 | ||
779 | static void free_list PROTO ((rtx *, rtx *)); | |
780 | static rtx alloc_INSN_LIST PROTO ((rtx, rtx)); | |
781 | static rtx alloc_EXPR_LIST PROTO ((int, rtx, rtx)); | |
782 | ||
783 | static void | |
784 | free_list (listp, unused_listp) | |
785 | rtx *listp, *unused_listp; | |
786 | { | |
787 | register rtx link, prev_link; | |
788 | ||
789 | if (*listp == 0) | |
790 | return; | |
791 | ||
792 | prev_link = *listp; | |
793 | link = XEXP (prev_link, 1); | |
794 | ||
795 | while (link) | |
796 | { | |
797 | prev_link = link; | |
798 | link = XEXP (link, 1); | |
799 | } | |
800 | ||
801 | XEXP (prev_link, 1) = *unused_listp; | |
802 | *unused_listp = *listp; | |
803 | *listp = 0; | |
804 | } | |
805 | ||
459b3825 | 806 | static rtx |
ebb7b10b RH |
807 | alloc_INSN_LIST (val, next) |
808 | rtx val, next; | |
809 | { | |
810 | rtx r; | |
811 | ||
812 | if (unused_insn_list) | |
813 | { | |
814 | r = unused_insn_list; | |
815 | unused_insn_list = XEXP (r, 1); | |
816 | XEXP (r, 0) = val; | |
817 | XEXP (r, 1) = next; | |
818 | PUT_REG_NOTE_KIND (r, VOIDmode); | |
819 | } | |
820 | else | |
821 | r = gen_rtx_INSN_LIST (VOIDmode, val, next); | |
822 | ||
823 | return r; | |
824 | } | |
825 | ||
459b3825 | 826 | static rtx |
ebb7b10b RH |
827 | alloc_EXPR_LIST (kind, val, next) |
828 | int kind; | |
829 | rtx val, next; | |
830 | { | |
831 | rtx r; | |
832 | ||
c92293e7 | 833 | if (unused_expr_list) |
ebb7b10b | 834 | { |
c92293e7 CM |
835 | r = unused_expr_list; |
836 | unused_expr_list = XEXP (r, 1); | |
ebb7b10b RH |
837 | XEXP (r, 0) = val; |
838 | XEXP (r, 1) = next; | |
839 | PUT_REG_NOTE_KIND (r, kind); | |
840 | } | |
841 | else | |
842 | r = gen_rtx_EXPR_LIST (kind, val, next); | |
843 | ||
844 | return r; | |
845 | } | |
846 | ||
8c660648 JL |
847 | /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the |
848 | LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type | |
849 | of dependence that this link represents. */ | |
850 | ||
851 | static void | |
852 | add_dependence (insn, elem, dep_type) | |
853 | rtx insn; | |
854 | rtx elem; | |
855 | enum reg_note dep_type; | |
856 | { | |
857 | rtx link, next; | |
858 | ||
859 | /* Don't depend an insn on itself. */ | |
860 | if (insn == elem) | |
861 | return; | |
862 | ||
863 | /* If elem is part of a sequence that must be scheduled together, then | |
864 | make the dependence point to the last insn of the sequence. | |
865 | When HAVE_cc0, it is possible for NOTEs to exist between users and | |
866 | setters of the condition codes, so we must skip past notes here. | |
867 | Otherwise, NOTEs are impossible here. */ | |
868 | ||
869 | next = NEXT_INSN (elem); | |
870 | ||
871 | #ifdef HAVE_cc0 | |
872 | while (next && GET_CODE (next) == NOTE) | |
873 | next = NEXT_INSN (next); | |
874 | #endif | |
875 | ||
876 | if (next && SCHED_GROUP_P (next) | |
877 | && GET_CODE (next) != CODE_LABEL) | |
878 | { | |
879 | /* Notes will never intervene here though, so don't bother checking | |
880 | for them. */ | |
881 | /* We must reject CODE_LABELs, so that we don't get confused by one | |
882 | that has LABEL_PRESERVE_P set, which is represented by the same | |
883 | bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be | |
884 | SCHED_GROUP_P. */ | |
885 | while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)) | |
886 | && GET_CODE (NEXT_INSN (next)) != CODE_LABEL) | |
887 | next = NEXT_INSN (next); | |
888 | ||
889 | /* Again, don't depend an insn on itself. */ | |
890 | if (insn == next) | |
891 | return; | |
892 | ||
893 | /* Make the dependence to NEXT, the last insn of the group, instead | |
894 | of the original ELEM. */ | |
895 | elem = next; | |
896 | } | |
897 | ||
898 | #ifdef INSN_SCHEDULING | |
899 | /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.) | |
900 | No need for interblock dependences with calls, since | |
901 | calls are not moved between blocks. Note: the edge where | |
902 | elem is a CALL is still required. */ | |
903 | if (GET_CODE (insn) == CALL_INSN | |
904 | && (INSN_BB (elem) != INSN_BB (insn))) | |
905 | return; | |
906 | ||
907 | #endif | |
908 | ||
909 | /* Check that we don't already have this dependence. */ | |
910 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
911 | if (XEXP (link, 0) == elem) | |
912 | { | |
913 | /* If this is a more restrictive type of dependence than the existing | |
914 | one, then change the existing dependence to this type. */ | |
915 | if ((int) dep_type < (int) REG_NOTE_KIND (link)) | |
916 | PUT_REG_NOTE_KIND (link, dep_type); | |
917 | return; | |
918 | } | |
919 | /* Might want to check one level of transitivity to save conses. */ | |
920 | ||
ebb7b10b RH |
921 | link = alloc_INSN_LIST (elem, LOG_LINKS (insn)); |
922 | LOG_LINKS (insn) = link; | |
923 | ||
8c660648 JL |
924 | /* Insn dependency, not data dependency. */ |
925 | PUT_REG_NOTE_KIND (link, dep_type); | |
8c660648 JL |
926 | } |
927 | ||
928 | /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS | |
929 | of INSN. Abort if not found. */ | |
930 | ||
931 | static void | |
932 | remove_dependence (insn, elem) | |
933 | rtx insn; | |
934 | rtx elem; | |
935 | { | |
ebb7b10b | 936 | rtx prev, link, next; |
8c660648 JL |
937 | int found = 0; |
938 | ||
ebb7b10b | 939 | for (prev = 0, link = LOG_LINKS (insn); link; link = next) |
8c660648 | 940 | { |
ebb7b10b | 941 | next = XEXP (link, 1); |
8c660648 JL |
942 | if (XEXP (link, 0) == elem) |
943 | { | |
944 | if (prev) | |
ebb7b10b | 945 | XEXP (prev, 1) = next; |
8c660648 | 946 | else |
ebb7b10b RH |
947 | LOG_LINKS (insn) = next; |
948 | ||
949 | XEXP (link, 1) = unused_insn_list; | |
950 | unused_insn_list = link; | |
951 | ||
8c660648 JL |
952 | found = 1; |
953 | } | |
6d8ccdbb JL |
954 | else |
955 | prev = link; | |
8c660648 JL |
956 | } |
957 | ||
958 | if (!found) | |
959 | abort (); | |
960 | return; | |
961 | } | |
962 | \f | |
963 | #ifndef INSN_SCHEDULING | |
964 | void | |
965 | schedule_insns (dump_file) | |
966 | FILE *dump_file; | |
967 | { | |
968 | } | |
969 | #else | |
970 | #ifndef __GNUC__ | |
971 | #define __inline | |
972 | #endif | |
973 | ||
cbb13457 MM |
974 | #ifndef HAIFA_INLINE |
975 | #define HAIFA_INLINE __inline | |
976 | #endif | |
977 | ||
8c660648 JL |
978 | /* Computation of memory dependencies. */ |
979 | ||
980 | /* The *_insns and *_mems are paired lists. Each pending memory operation | |
981 | will have a pointer to the MEM rtx on one list and a pointer to the | |
982 | containing insn on the other list in the same place in the list. */ | |
983 | ||
984 | /* We can't use add_dependence like the old code did, because a single insn | |
985 | may have multiple memory accesses, and hence needs to be on the list | |
986 | once for each memory access. Add_dependence won't let you add an insn | |
987 | to a list more than once. */ | |
988 | ||
989 | /* An INSN_LIST containing all insns with pending read operations. */ | |
990 | static rtx pending_read_insns; | |
991 | ||
992 | /* An EXPR_LIST containing all MEM rtx's which are pending reads. */ | |
993 | static rtx pending_read_mems; | |
994 | ||
995 | /* An INSN_LIST containing all insns with pending write operations. */ | |
996 | static rtx pending_write_insns; | |
997 | ||
998 | /* An EXPR_LIST containing all MEM rtx's which are pending writes. */ | |
999 | static rtx pending_write_mems; | |
1000 | ||
1001 | /* Indicates the combined length of the two pending lists. We must prevent | |
1002 | these lists from ever growing too large since the number of dependencies | |
1003 | produced is at least O(N*N), and execution time is at least O(4*N*N), as | |
1004 | a function of the length of these pending lists. */ | |
1005 | ||
1006 | static int pending_lists_length; | |
1007 | ||
8c660648 JL |
1008 | /* The last insn upon which all memory references must depend. |
1009 | This is an insn which flushed the pending lists, creating a dependency | |
1010 | between it and all previously pending memory references. This creates | |
1011 | a barrier (or a checkpoint) which no memory reference is allowed to cross. | |
1012 | ||
1013 | This includes all non constant CALL_INSNs. When we do interprocedural | |
1014 | alias analysis, this restriction can be relaxed. | |
1015 | This may also be an INSN that writes memory if the pending lists grow | |
1016 | too large. */ | |
1017 | ||
1018 | static rtx last_pending_memory_flush; | |
1019 | ||
1020 | /* The last function call we have seen. All hard regs, and, of course, | |
1021 | the last function call, must depend on this. */ | |
1022 | ||
1023 | static rtx last_function_call; | |
1024 | ||
1025 | /* The LOG_LINKS field of this is a list of insns which use a pseudo register | |
1026 | that does not already cross a call. We create dependencies between each | |
1027 | of those insn and the next call insn, to ensure that they won't cross a call | |
1028 | after scheduling is done. */ | |
1029 | ||
1030 | static rtx sched_before_next_call; | |
1031 | ||
1032 | /* Pointer to the last instruction scheduled. Used by rank_for_schedule, | |
1033 | so that insns independent of the last scheduled insn will be preferred | |
1034 | over dependent instructions. */ | |
1035 | ||
1036 | static rtx last_scheduled_insn; | |
1037 | ||
1038 | /* Data structures for the computation of data dependences in a regions. We | |
1039 | keep one copy of each of the declared above variables for each bb in the | |
1040 | region. Before analyzing the data dependences for a bb, its variables | |
1041 | are initialized as a function of the variables of its predecessors. When | |
1042 | the analysis for a bb completes, we save the contents of each variable X | |
1043 | to a corresponding bb_X[bb] variable. For example, pending_read_insns is | |
1044 | copied to bb_pending_read_insns[bb]. Another change is that few | |
1045 | variables are now a list of insns rather than a single insn: | |
1046 | last_pending_memory_flash, last_function_call, reg_last_sets. The | |
1047 | manipulation of these variables was changed appropriately. */ | |
1048 | ||
1049 | static rtx **bb_reg_last_uses; | |
1050 | static rtx **bb_reg_last_sets; | |
1051 | ||
1052 | static rtx *bb_pending_read_insns; | |
1053 | static rtx *bb_pending_read_mems; | |
1054 | static rtx *bb_pending_write_insns; | |
1055 | static rtx *bb_pending_write_mems; | |
1056 | static int *bb_pending_lists_length; | |
1057 | ||
1058 | static rtx *bb_last_pending_memory_flush; | |
1059 | static rtx *bb_last_function_call; | |
1060 | static rtx *bb_sched_before_next_call; | |
1061 | ||
1062 | /* functions for construction of the control flow graph. */ | |
1063 | ||
1064 | /* Return 1 if control flow graph should not be constructed, 0 otherwise. | |
168cbdf9 | 1065 | |
8c660648 | 1066 | We decide not to build the control flow graph if there is possibly more |
168cbdf9 JL |
1067 | than one entry to the function, if computed branches exist, of if we |
1068 | have nonlocal gotos. */ | |
8c660648 | 1069 | |
168cbdf9 | 1070 | static int |
8c660648 JL |
1071 | is_cfg_nonregular () |
1072 | { | |
1073 | int b; | |
1074 | rtx insn; | |
1075 | RTX_CODE code; | |
1076 | ||
168cbdf9 JL |
1077 | /* If we have a label that could be the target of a nonlocal goto, then |
1078 | the cfg is not well structured. */ | |
1079 | if (nonlocal_label_rtx_list () != NULL) | |
1080 | return 1; | |
8c660648 | 1081 | |
168cbdf9 | 1082 | /* If we have any forced labels, then the cfg is not well structured. */ |
8c660648 | 1083 | if (forced_labels) |
168cbdf9 | 1084 | return 1; |
8c660648 | 1085 | |
4d1d8045 BS |
1086 | /* If this function has a computed jump, then we consider the cfg |
1087 | not well structured. */ | |
1088 | if (current_function_has_computed_jump) | |
1089 | return 1; | |
1090 | ||
168cbdf9 JL |
1091 | /* If we have exception handlers, then we consider the cfg not well |
1092 | structured. ?!? We should be able to handle this now that flow.c | |
1093 | computes an accurate cfg for EH. */ | |
8c660648 | 1094 | if (exception_handler_labels) |
168cbdf9 | 1095 | return 1; |
8c660648 | 1096 | |
168cbdf9 JL |
1097 | /* If we have non-jumping insns which refer to labels, then we consider |
1098 | the cfg not well structured. */ | |
8c660648 JL |
1099 | /* check for labels referred to other thn by jumps */ |
1100 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 1101 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
1102 | { |
1103 | code = GET_CODE (insn); | |
1104 | if (GET_RTX_CLASS (code) == 'i') | |
1105 | { | |
1106 | rtx note; | |
1107 | ||
1108 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1109 | if (REG_NOTE_KIND (note) == REG_LABEL) | |
168cbdf9 | 1110 | return 1; |
8c660648 JL |
1111 | } |
1112 | ||
3b413743 | 1113 | if (insn == BLOCK_END (b)) |
8c660648 JL |
1114 | break; |
1115 | } | |
1116 | ||
168cbdf9 | 1117 | /* All the tests passed. Consider the cfg well structured. */ |
8c660648 JL |
1118 | return 0; |
1119 | } | |
1120 | ||
5ece9746 JL |
1121 | /* Build the control flow graph and set nr_edges. |
1122 | ||
1123 | Instead of trying to build a cfg ourselves, we rely on flow to | |
168cbdf9 | 1124 | do it for us. Stamp out useless code (and bug) duplication. |
8c660648 | 1125 | |
168cbdf9 JL |
1126 | Return nonzero if an irregularity in the cfg is found which would |
1127 | prevent cross block scheduling. */ | |
1128 | ||
1129 | static int | |
a2e68776 JL |
1130 | build_control_flow (s_preds, s_succs, num_preds, num_succs) |
1131 | int_list_ptr *s_preds; | |
1132 | int_list_ptr *s_succs; | |
1133 | int *num_preds; | |
1134 | int *num_succs; | |
8c660648 | 1135 | { |
081f5e7e | 1136 | int i; |
5ece9746 | 1137 | int_list_ptr succ; |
168cbdf9 | 1138 | int unreachable; |
5ece9746 | 1139 | |
168cbdf9 JL |
1140 | /* Count the number of edges in the cfg. */ |
1141 | nr_edges = 0; | |
1142 | unreachable = 0; | |
1143 | for (i = 0; i < n_basic_blocks; i++) | |
1144 | { | |
1145 | nr_edges += num_succs[i]; | |
15ebe47d JL |
1146 | |
1147 | /* Unreachable loops with more than one basic block are detected | |
1148 | during the DFS traversal in find_rgns. | |
1149 | ||
1150 | Unreachable loops with a single block are detected here. This | |
1151 | test is redundant with the one in find_rgns, but it's much | |
1152 | cheaper to go ahead and catch the trivial case here. */ | |
a8afd67b JW |
1153 | if (num_preds[i] == 0 |
1154 | || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i)) | |
168cbdf9 JL |
1155 | unreachable = 1; |
1156 | } | |
1157 | ||
1158 | /* Account for entry/exit edges. */ | |
1159 | nr_edges += 2; | |
1160 | ||
1161 | in_edges = (int *) xmalloc (n_basic_blocks * sizeof (int)); | |
1162 | out_edges = (int *) xmalloc (n_basic_blocks * sizeof (int)); | |
1163 | bzero ((char *) in_edges, n_basic_blocks * sizeof (int)); | |
1164 | bzero ((char *) out_edges, n_basic_blocks * sizeof (int)); | |
1165 | ||
1166 | edge_table = (edge *) xmalloc ((nr_edges) * sizeof (edge)); | |
1167 | bzero ((char *) edge_table, ((nr_edges) * sizeof (edge))); | |
1168 | ||
8c660648 JL |
1169 | nr_edges = 0; |
1170 | for (i = 0; i < n_basic_blocks; i++) | |
5ece9746 JL |
1171 | for (succ = s_succs[i]; succ; succ = succ->next) |
1172 | { | |
1173 | if (INT_LIST_VAL (succ) != EXIT_BLOCK) | |
1174 | new_edge (i, INT_LIST_VAL (succ)); | |
1175 | } | |
8c660648 JL |
1176 | |
1177 | /* increment by 1, since edge 0 is unused. */ | |
1178 | nr_edges++; | |
1179 | ||
168cbdf9 | 1180 | return unreachable; |
8c660648 JL |
1181 | } |
1182 | ||
1183 | ||
5ece9746 | 1184 | /* Record an edge in the control flow graph from SOURCE to TARGET. |
8c660648 | 1185 | |
5ece9746 JL |
1186 | In theory, this is redundant with the s_succs computed above, but |
1187 | we have not converted all of haifa to use information from the | |
1188 | integer lists. */ | |
8c660648 JL |
1189 | |
1190 | static void | |
1191 | new_edge (source, target) | |
1192 | int source, target; | |
1193 | { | |
1194 | int e, next_edge; | |
1195 | int curr_edge, fst_edge; | |
1196 | ||
1197 | /* check for duplicates */ | |
1198 | fst_edge = curr_edge = OUT_EDGES (source); | |
1199 | while (curr_edge) | |
1200 | { | |
1201 | if (FROM_BLOCK (curr_edge) == source | |
1202 | && TO_BLOCK (curr_edge) == target) | |
1203 | { | |
1204 | return; | |
1205 | } | |
1206 | ||
1207 | curr_edge = NEXT_OUT (curr_edge); | |
1208 | ||
1209 | if (fst_edge == curr_edge) | |
1210 | break; | |
1211 | } | |
1212 | ||
1213 | e = ++nr_edges; | |
1214 | ||
1215 | FROM_BLOCK (e) = source; | |
1216 | TO_BLOCK (e) = target; | |
1217 | ||
1218 | if (OUT_EDGES (source)) | |
1219 | { | |
1220 | next_edge = NEXT_OUT (OUT_EDGES (source)); | |
1221 | NEXT_OUT (OUT_EDGES (source)) = e; | |
1222 | NEXT_OUT (e) = next_edge; | |
1223 | } | |
1224 | else | |
1225 | { | |
1226 | OUT_EDGES (source) = e; | |
1227 | NEXT_OUT (e) = e; | |
1228 | } | |
1229 | ||
1230 | if (IN_EDGES (target)) | |
1231 | { | |
1232 | next_edge = NEXT_IN (IN_EDGES (target)); | |
1233 | NEXT_IN (IN_EDGES (target)) = e; | |
1234 | NEXT_IN (e) = next_edge; | |
1235 | } | |
1236 | else | |
1237 | { | |
1238 | IN_EDGES (target) = e; | |
1239 | NEXT_IN (e) = e; | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | ||
1244 | /* BITSET macros for operations on the control flow graph. */ | |
1245 | ||
1246 | /* Compute bitwise union of two bitsets. */ | |
1247 | #define BITSET_UNION(set1, set2, len) \ | |
1248 | do { register bitset tp = set1, sp = set2; \ | |
1249 | register int i; \ | |
1250 | for (i = 0; i < len; i++) \ | |
1251 | *(tp++) |= *(sp++); } while (0) | |
1252 | ||
1253 | /* Compute bitwise intersection of two bitsets. */ | |
1254 | #define BITSET_INTER(set1, set2, len) \ | |
1255 | do { register bitset tp = set1, sp = set2; \ | |
1256 | register int i; \ | |
1257 | for (i = 0; i < len; i++) \ | |
1258 | *(tp++) &= *(sp++); } while (0) | |
1259 | ||
1260 | /* Compute bitwise difference of two bitsets. */ | |
1261 | #define BITSET_DIFFER(set1, set2, len) \ | |
1262 | do { register bitset tp = set1, sp = set2; \ | |
1263 | register int i; \ | |
1264 | for (i = 0; i < len; i++) \ | |
1265 | *(tp++) &= ~*(sp++); } while (0) | |
1266 | ||
1267 | /* Inverts every bit of bitset 'set' */ | |
1268 | #define BITSET_INVERT(set, len) \ | |
1269 | do { register bitset tmpset = set; \ | |
1270 | register int i; \ | |
1271 | for (i = 0; i < len; i++, tmpset++) \ | |
1272 | *tmpset = ~*tmpset; } while (0) | |
1273 | ||
1274 | /* Turn on the index'th bit in bitset set. */ | |
1275 | #define BITSET_ADD(set, index, len) \ | |
1276 | { \ | |
1277 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1278 | abort (); \ | |
1279 | else \ | |
1280 | set[index/HOST_BITS_PER_WIDE_INT] |= \ | |
1281 | 1 << (index % HOST_BITS_PER_WIDE_INT); \ | |
1282 | } | |
1283 | ||
1284 | /* Turn off the index'th bit in set. */ | |
1285 | #define BITSET_REMOVE(set, index, len) \ | |
1286 | { \ | |
1287 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1288 | abort (); \ | |
1289 | else \ | |
1290 | set[index/HOST_BITS_PER_WIDE_INT] &= \ | |
1291 | ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \ | |
1292 | } | |
1293 | ||
1294 | ||
1295 | /* Check if the index'th bit in bitset set is on. */ | |
1296 | ||
1297 | static char | |
1298 | bitset_member (set, index, len) | |
1299 | bitset set; | |
1300 | int index, len; | |
1301 | { | |
1302 | if (index >= HOST_BITS_PER_WIDE_INT * len) | |
1303 | abort (); | |
1304 | return (set[index / HOST_BITS_PER_WIDE_INT] & | |
1305 | 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0; | |
1306 | } | |
1307 | ||
1308 | ||
1309 | /* Translate a bit-set SET to a list BL of the bit-set members. */ | |
1310 | ||
1311 | static void | |
1312 | extract_bitlst (set, len, bl) | |
1313 | bitset set; | |
1314 | int len; | |
1315 | bitlst *bl; | |
1316 | { | |
1317 | int i, j, offset; | |
1318 | unsigned HOST_WIDE_INT word; | |
1319 | ||
1320 | /* bblst table space is reused in each call to extract_bitlst */ | |
1321 | bitlst_table_last = 0; | |
1322 | ||
1323 | bl->first_member = &bitlst_table[bitlst_table_last]; | |
1324 | bl->nr_members = 0; | |
1325 | ||
1326 | for (i = 0; i < len; i++) | |
1327 | { | |
1328 | word = set[i]; | |
1329 | offset = i * HOST_BITS_PER_WIDE_INT; | |
1330 | for (j = 0; word; j++) | |
1331 | { | |
1332 | if (word & 1) | |
1333 | { | |
1334 | bitlst_table[bitlst_table_last++] = offset; | |
1335 | (bl->nr_members)++; | |
1336 | } | |
1337 | word >>= 1; | |
1338 | ++offset; | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | } | |
1343 | ||
1344 | ||
1345 | /* functions for the construction of regions */ | |
1346 | ||
1347 | /* Print the regions, for debugging purposes. Callable from debugger. */ | |
1348 | ||
1349 | void | |
1350 | debug_regions () | |
1351 | { | |
1352 | int rgn, bb; | |
1353 | ||
1354 | fprintf (dump, "\n;; ------------ REGIONS ----------\n\n"); | |
1355 | for (rgn = 0; rgn < nr_regions; rgn++) | |
1356 | { | |
1357 | fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn, | |
1358 | rgn_table[rgn].rgn_nr_blocks); | |
1359 | fprintf (dump, ";;\tbb/block: "); | |
1360 | ||
1361 | for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++) | |
1362 | { | |
1363 | current_blocks = RGN_BLOCKS (rgn); | |
1364 | ||
1365 | if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb))) | |
1366 | abort (); | |
1367 | ||
1368 | fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb)); | |
1369 | } | |
1370 | ||
1371 | fprintf (dump, "\n\n"); | |
1372 | } | |
1373 | } | |
1374 | ||
1375 | ||
1376 | /* Build a single block region for each basic block in the function. | |
1377 | This allows for using the same code for interblock and basic block | |
1378 | scheduling. */ | |
1379 | ||
1380 | static void | |
1381 | find_single_block_region () | |
1382 | { | |
1383 | int i; | |
1384 | ||
1385 | for (i = 0; i < n_basic_blocks; i++) | |
1386 | { | |
1387 | rgn_bb_table[i] = i; | |
1388 | RGN_NR_BLOCKS (i) = 1; | |
1389 | RGN_BLOCKS (i) = i; | |
1390 | CONTAINING_RGN (i) = i; | |
1391 | BLOCK_TO_BB (i) = 0; | |
1392 | } | |
1393 | nr_regions = n_basic_blocks; | |
1394 | } | |
1395 | ||
1396 | ||
1397 | /* Update number of blocks and the estimate for number of insns | |
1398 | in the region. Return 1 if the region is "too large" for interblock | |
1399 | scheduling (compile time considerations), otherwise return 0. */ | |
1400 | ||
1401 | static int | |
1402 | too_large (block, num_bbs, num_insns) | |
1403 | int block, *num_bbs, *num_insns; | |
1404 | { | |
1405 | (*num_bbs)++; | |
3b413743 RH |
1406 | (*num_insns) += (INSN_LUID (BLOCK_END (block)) - |
1407 | INSN_LUID (BLOCK_HEAD (block))); | |
cc132865 | 1408 | if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS)) |
8c660648 JL |
1409 | return 1; |
1410 | else | |
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | ||
1415 | /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk] | |
1416 | is still an inner loop. Put in max_hdr[blk] the header of the most inner | |
1417 | loop containing blk. */ | |
1418 | #define UPDATE_LOOP_RELATIONS(blk, hdr) \ | |
1419 | { \ | |
1420 | if (max_hdr[blk] == -1) \ | |
1421 | max_hdr[blk] = hdr; \ | |
1422 | else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \ | |
a2e68776 | 1423 | RESET_BIT (inner, hdr); \ |
8c660648 JL |
1424 | else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \ |
1425 | { \ | |
a2e68776 | 1426 | RESET_BIT (inner,max_hdr[blk]); \ |
8c660648 JL |
1427 | max_hdr[blk] = hdr; \ |
1428 | } \ | |
1429 | } | |
1430 | ||
1431 | ||
a2e68776 JL |
1432 | /* Find regions for interblock scheduling. |
1433 | ||
1434 | A region for scheduling can be: | |
1435 | ||
1436 | * A loop-free procedure, or | |
1437 | ||
1438 | * A reducible inner loop, or | |
1439 | ||
1440 | * A basic block not contained in any other region. | |
1441 | ||
1442 | ||
1443 | ?!? In theory we could build other regions based on extended basic | |
1444 | blocks or reverse extended basic blocks. Is it worth the trouble? | |
1445 | ||
1446 | Loop blocks that form a region are put into the region's block list | |
1447 | in topological order. | |
1448 | ||
1449 | This procedure stores its results into the following global (ick) variables | |
1450 | ||
1451 | * rgn_nr | |
1452 | * rgn_table | |
1453 | * rgn_bb_table | |
1454 | * block_to_bb | |
1455 | * containing region | |
1456 | ||
1457 | ||
1458 | We use dominator relationships to avoid making regions out of non-reducible | |
1459 | loops. | |
8c660648 | 1460 | |
a2e68776 JL |
1461 | This procedure needs to be converted to work on pred/succ lists instead |
1462 | of edge tables. That would simplify it somewhat. */ | |
8c660648 JL |
1463 | |
1464 | static void | |
a2e68776 JL |
1465 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom) |
1466 | int_list_ptr *s_preds; | |
1467 | int_list_ptr *s_succs; | |
1468 | int *num_preds; | |
1469 | int *num_succs; | |
1470 | sbitmap *dom; | |
8c660648 JL |
1471 | { |
1472 | int *max_hdr, *dfs_nr, *stack, *queue, *degree; | |
a2e68776 | 1473 | char no_loops = 1; |
487a6e06 | 1474 | int node, child, loop_head, i, head, tail; |
8c660648 | 1475 | int count = 0, sp, idx = 0, current_edge = out_edges[0]; |
15ebe47d | 1476 | int num_bbs, num_insns, unreachable; |
8c660648 | 1477 | int too_large_failure; |
8c660648 | 1478 | |
a2e68776 JL |
1479 | /* Note if an edge has been passed. */ |
1480 | sbitmap passed; | |
1481 | ||
1482 | /* Note if a block is a natural loop header. */ | |
1483 | sbitmap header; | |
1484 | ||
1485 | /* Note if a block is an natural inner loop header. */ | |
1486 | sbitmap inner; | |
1487 | ||
1488 | /* Note if a block is in the block queue. */ | |
1489 | sbitmap in_queue; | |
1490 | ||
cc132865 JL |
1491 | /* Note if a block is in the block queue. */ |
1492 | sbitmap in_stack; | |
1493 | ||
a2e68776 JL |
1494 | /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops |
1495 | and a mapping from block to its loop header (if the block is contained | |
1496 | in a loop, else -1). | |
1497 | ||
1498 | Store results in HEADER, INNER, and MAX_HDR respectively, these will | |
1499 | be used as inputs to the second traversal. | |
1500 | ||
1501 | STACK, SP and DFS_NR are only used during the first traversal. */ | |
1502 | ||
1503 | /* Allocate and initialize variables for the first traversal. */ | |
8c660648 JL |
1504 | max_hdr = (int *) alloca (n_basic_blocks * sizeof (int)); |
1505 | dfs_nr = (int *) alloca (n_basic_blocks * sizeof (int)); | |
52b7724b | 1506 | bzero ((char *) dfs_nr, n_basic_blocks * sizeof (int)); |
8c660648 | 1507 | stack = (int *) alloca (nr_edges * sizeof (int)); |
8c660648 | 1508 | |
a2e68776 JL |
1509 | inner = sbitmap_alloc (n_basic_blocks); |
1510 | sbitmap_ones (inner); | |
1511 | ||
1512 | header = sbitmap_alloc (n_basic_blocks); | |
1513 | sbitmap_zero (header); | |
8c660648 | 1514 | |
a2e68776 JL |
1515 | passed = sbitmap_alloc (nr_edges); |
1516 | sbitmap_zero (passed); | |
1517 | ||
1518 | in_queue = sbitmap_alloc (n_basic_blocks); | |
1519 | sbitmap_zero (in_queue); | |
8c660648 | 1520 | |
cc132865 JL |
1521 | in_stack = sbitmap_alloc (n_basic_blocks); |
1522 | sbitmap_zero (in_stack); | |
1523 | ||
8c660648 | 1524 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 | 1525 | max_hdr[i] = -1; |
8c660648 | 1526 | |
a2e68776 | 1527 | /* DFS traversal to find inner loops in the cfg. */ |
8c660648 | 1528 | |
8c660648 JL |
1529 | sp = -1; |
1530 | while (1) | |
1531 | { | |
a2e68776 | 1532 | if (current_edge == 0 || TEST_BIT (passed, current_edge)) |
8c660648 | 1533 | { |
a2e68776 | 1534 | /* We have reached a leaf node or a node that was already |
cc132865 | 1535 | processed. Pop edges off the stack until we find |
a2e68776 JL |
1536 | an edge that has not yet been processed. */ |
1537 | while (sp >= 0 | |
1538 | && (current_edge == 0 || TEST_BIT (passed, current_edge))) | |
8c660648 | 1539 | { |
a2e68776 | 1540 | /* Pop entry off the stack. */ |
8c660648 JL |
1541 | current_edge = stack[sp--]; |
1542 | node = FROM_BLOCK (current_edge); | |
1543 | child = TO_BLOCK (current_edge); | |
cc132865 JL |
1544 | RESET_BIT (in_stack, child); |
1545 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) | |
8c660648 JL |
1546 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
1547 | current_edge = NEXT_OUT (current_edge); | |
1548 | } | |
1549 | ||
a2e68776 JL |
1550 | /* See if have finished the DFS tree traversal. */ |
1551 | if (sp < 0 && TEST_BIT (passed, current_edge)) | |
8c660648 | 1552 | break; |
a2e68776 JL |
1553 | |
1554 | /* Nope, continue the traversal with the popped node. */ | |
8c660648 JL |
1555 | continue; |
1556 | } | |
1557 | ||
a2e68776 | 1558 | /* Process a node. */ |
8c660648 | 1559 | node = FROM_BLOCK (current_edge); |
8c660648 | 1560 | child = TO_BLOCK (current_edge); |
cc132865 | 1561 | SET_BIT (in_stack, node); |
a2e68776 | 1562 | dfs_nr[node] = ++count; |
8c660648 | 1563 | |
cc132865 JL |
1564 | /* If the successor is in the stack, then we've found a loop. |
1565 | Mark the loop, if it is not a natural loop, then it will | |
1566 | be rejected during the second traversal. */ | |
1567 | if (TEST_BIT (in_stack, child)) | |
8c660648 JL |
1568 | { |
1569 | no_loops = 0; | |
a2e68776 | 1570 | SET_BIT (header, child); |
8c660648 | 1571 | UPDATE_LOOP_RELATIONS (node, child); |
a2e68776 | 1572 | SET_BIT (passed, current_edge); |
8c660648 JL |
1573 | current_edge = NEXT_OUT (current_edge); |
1574 | continue; | |
1575 | } | |
1576 | ||
a2e68776 JL |
1577 | /* If the child was already visited, then there is no need to visit |
1578 | it again. Just update the loop relationships and restart | |
1579 | with a new edge. */ | |
8c660648 JL |
1580 | if (dfs_nr[child]) |
1581 | { | |
cc132865 | 1582 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) |
8c660648 | 1583 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
a2e68776 | 1584 | SET_BIT (passed, current_edge); |
8c660648 JL |
1585 | current_edge = NEXT_OUT (current_edge); |
1586 | continue; | |
1587 | } | |
1588 | ||
a2e68776 | 1589 | /* Push an entry on the stack and continue DFS traversal. */ |
8c660648 | 1590 | stack[++sp] = current_edge; |
a2e68776 | 1591 | SET_BIT (passed, current_edge); |
8c660648 | 1592 | current_edge = OUT_EDGES (child); |
a2e68776 | 1593 | } |
8c660648 | 1594 | |
15ebe47d JL |
1595 | /* Another check for unreachable blocks. The earlier test in |
1596 | is_cfg_nonregular only finds unreachable blocks that do not | |
1597 | form a loop. | |
a2e68776 | 1598 | |
15ebe47d JL |
1599 | The DFS traversal will mark every block that is reachable from |
1600 | the entry node by placing a nonzero value in dfs_nr. Thus if | |
1601 | dfs_nr is zero for any block, then it must be unreachable. */ | |
1602 | unreachable = 0; | |
1603 | for (i = 0; i < n_basic_blocks; i++) | |
1604 | if (dfs_nr[i] == 0) | |
1605 | { | |
1606 | unreachable = 1; | |
1607 | break; | |
1608 | } | |
a2e68776 JL |
1609 | |
1610 | /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array | |
1611 | to hold degree counts. */ | |
1612 | degree = dfs_nr; | |
8c660648 | 1613 | |
a2e68776 | 1614 | /* Compute the in-degree of every block in the graph */ |
8c660648 | 1615 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 JL |
1616 | degree[i] = num_preds[i]; |
1617 | ||
15ebe47d JL |
1618 | /* Do not perform region scheduling if there are any unreachable |
1619 | blocks. */ | |
1620 | if (!unreachable) | |
8c660648 | 1621 | { |
15ebe47d JL |
1622 | if (no_loops) |
1623 | SET_BIT (header, 0); | |
8c660648 | 1624 | |
15ebe47d JL |
1625 | /* Second travsersal:find reducible inner loops and topologically sort |
1626 | block of each region. */ | |
8c660648 | 1627 | |
15ebe47d | 1628 | queue = (int *) alloca (n_basic_blocks * sizeof (int)); |
8c660648 | 1629 | |
cc132865 JL |
1630 | /* Find blocks which are inner loop headers. We still have non-reducible |
1631 | loops to consider at this point. */ | |
15ebe47d JL |
1632 | for (i = 0; i < n_basic_blocks; i++) |
1633 | { | |
1634 | if (TEST_BIT (header, i) && TEST_BIT (inner, i)) | |
1635 | { | |
1636 | int_list_ptr ps; | |
cc132865 JL |
1637 | int j; |
1638 | ||
1639 | /* Now check that the loop is reducible. We do this separate | |
1640 | from finding inner loops so that we do not find a reducible | |
1641 | loop which contains an inner non-reducible loop. | |
1642 | ||
1643 | A simple way to find reducible/natrual loops is to verify | |
1644 | that each block in the loop is dominated by the loop | |
1645 | header. | |
1646 | ||
1647 | If there exists a block that is not dominated by the loop | |
1648 | header, then the block is reachable from outside the loop | |
1649 | and thus the loop is not a natural loop. */ | |
1650 | for (j = 0; j < n_basic_blocks; j++) | |
1651 | { | |
1652 | /* First identify blocks in the loop, except for the loop | |
1653 | entry block. */ | |
1654 | if (i == max_hdr[j] && i != j) | |
1655 | { | |
1656 | /* Now verify that the block is dominated by the loop | |
1657 | header. */ | |
1658 | if (!TEST_BIT (dom[j], i)) | |
1659 | break; | |
1660 | } | |
1661 | } | |
1662 | ||
1663 | /* If we exited the loop early, then I is the header of a non | |
1664 | reducible loop and we should quit processing it now. */ | |
1665 | if (j != n_basic_blocks) | |
1666 | continue; | |
8c660648 | 1667 | |
cc132865 JL |
1668 | /* I is a header of an inner loop, or block 0 in a subroutine |
1669 | with no loops at all. */ | |
15ebe47d JL |
1670 | head = tail = -1; |
1671 | too_large_failure = 0; | |
1672 | loop_head = max_hdr[i]; | |
8c660648 | 1673 | |
15ebe47d | 1674 | /* Decrease degree of all I's successors for topological |
a59bfd78 | 1675 | ordering. */ |
15ebe47d JL |
1676 | for (ps = s_succs[i]; ps; ps = ps->next) |
1677 | if (INT_LIST_VAL (ps) != EXIT_BLOCK | |
1678 | && INT_LIST_VAL (ps) != ENTRY_BLOCK) | |
cc132865 | 1679 | --degree[INT_LIST_VAL(ps)]; |
a2e68776 | 1680 | |
15ebe47d JL |
1681 | /* Estimate # insns, and count # blocks in the region. */ |
1682 | num_bbs = 1; | |
3b413743 RH |
1683 | num_insns = (INSN_LUID (BLOCK_END (i)) |
1684 | - INSN_LUID (BLOCK_HEAD (i))); | |
8c660648 | 1685 | |
15ebe47d JL |
1686 | |
1687 | /* Find all loop latches (blocks which back edges to the loop | |
1688 | header) or all the leaf blocks in the cfg has no loops. | |
1689 | ||
1690 | Place those blocks into the queue. */ | |
1691 | if (no_loops) | |
1692 | { | |
1693 | for (j = 0; j < n_basic_blocks; j++) | |
1694 | /* Leaf nodes have only a single successor which must | |
1695 | be EXIT_BLOCK. */ | |
1696 | if (num_succs[j] == 1 | |
1697 | && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK) | |
8c660648 | 1698 | { |
15ebe47d JL |
1699 | queue[++tail] = j; |
1700 | SET_BIT (in_queue, j); | |
1701 | ||
1702 | if (too_large (j, &num_bbs, &num_insns)) | |
1703 | { | |
1704 | too_large_failure = 1; | |
1705 | break; | |
1706 | } | |
8c660648 | 1707 | } |
15ebe47d JL |
1708 | } |
1709 | else | |
8c660648 | 1710 | { |
15ebe47d | 1711 | int_list_ptr ps; |
a2e68776 | 1712 | |
15ebe47d | 1713 | for (ps = s_preds[i]; ps; ps = ps->next) |
8c660648 | 1714 | { |
15ebe47d | 1715 | node = INT_LIST_VAL (ps); |
8c660648 | 1716 | |
15ebe47d JL |
1717 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK) |
1718 | continue; | |
1719 | ||
1720 | if (max_hdr[node] == loop_head && node != i) | |
8c660648 | 1721 | { |
15ebe47d JL |
1722 | /* This is a loop latch. */ |
1723 | queue[++tail] = node; | |
1724 | SET_BIT (in_queue, node); | |
1725 | ||
1726 | if (too_large (node, &num_bbs, &num_insns)) | |
1727 | { | |
1728 | too_large_failure = 1; | |
1729 | break; | |
1730 | } | |
8c660648 | 1731 | } |
15ebe47d | 1732 | |
8c660648 | 1733 | } |
8c660648 | 1734 | } |
8c660648 | 1735 | |
15ebe47d | 1736 | /* Now add all the blocks in the loop to the queue. |
a2e68776 JL |
1737 | |
1738 | We know the loop is a natural loop; however the algorithm | |
1739 | above will not always mark certain blocks as being in the | |
1740 | loop. Consider: | |
1741 | node children | |
1742 | a b,c | |
1743 | b c | |
1744 | c a,d | |
1745 | d b | |
1746 | ||
1747 | ||
1748 | The algorithm in the DFS traversal may not mark B & D as part | |
1749 | of the loop (ie they will not have max_hdr set to A). | |
1750 | ||
1751 | We know they can not be loop latches (else they would have | |
1752 | had max_hdr set since they'd have a backedge to a dominator | |
1753 | block). So we don't need them on the initial queue. | |
1754 | ||
1755 | We know they are part of the loop because they are dominated | |
1756 | by the loop header and can be reached by a backwards walk of | |
1757 | the edges starting with nodes on the initial queue. | |
1758 | ||
1759 | It is safe and desirable to include those nodes in the | |
1760 | loop/scheduling region. To do so we would need to decrease | |
1761 | the degree of a node if it is the target of a backedge | |
1762 | within the loop itself as the node is placed in the queue. | |
1763 | ||
1764 | We do not do this because I'm not sure that the actual | |
1765 | scheduling code will properly handle this case. ?!? */ | |
1766 | ||
15ebe47d | 1767 | while (head < tail && !too_large_failure) |
8c660648 | 1768 | { |
15ebe47d JL |
1769 | int_list_ptr ps; |
1770 | child = queue[++head]; | |
8c660648 | 1771 | |
15ebe47d | 1772 | for (ps = s_preds[child]; ps; ps = ps->next) |
8c660648 | 1773 | { |
15ebe47d | 1774 | node = INT_LIST_VAL (ps); |
8c660648 | 1775 | |
15ebe47d JL |
1776 | /* See discussion above about nodes not marked as in |
1777 | this loop during the initial DFS traversal. */ | |
1778 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK | |
1779 | || max_hdr[node] != loop_head) | |
8c660648 | 1780 | { |
15ebe47d | 1781 | tail = -1; |
8c660648 JL |
1782 | break; |
1783 | } | |
15ebe47d JL |
1784 | else if (!TEST_BIT (in_queue, node) && node != i) |
1785 | { | |
1786 | queue[++tail] = node; | |
1787 | SET_BIT (in_queue, node); | |
1788 | ||
1789 | if (too_large (node, &num_bbs, &num_insns)) | |
1790 | { | |
1791 | too_large_failure = 1; | |
1792 | break; | |
1793 | } | |
1794 | } | |
8c660648 | 1795 | } |
8c660648 | 1796 | } |
8c660648 | 1797 | |
15ebe47d JL |
1798 | if (tail >= 0 && !too_large_failure) |
1799 | { | |
1800 | /* Place the loop header into list of region blocks. */ | |
1801 | degree[i] = -1; | |
1802 | rgn_bb_table[idx] = i; | |
1803 | RGN_NR_BLOCKS (nr_regions) = num_bbs; | |
1804 | RGN_BLOCKS (nr_regions) = idx++; | |
1805 | CONTAINING_RGN (i) = nr_regions; | |
1806 | BLOCK_TO_BB (i) = count = 0; | |
1807 | ||
1808 | /* Remove blocks from queue[] when their in degree becomes | |
a2e68776 JL |
1809 | zero. Repeat until no blocks are left on the list. This |
1810 | produces a topological list of blocks in the region. */ | |
15ebe47d | 1811 | while (tail >= 0) |
8c660648 | 1812 | { |
15ebe47d JL |
1813 | int_list_ptr ps; |
1814 | ||
1815 | if (head < 0) | |
1816 | head = tail; | |
1817 | child = queue[head]; | |
1818 | if (degree[child] == 0) | |
1819 | { | |
1820 | degree[child] = -1; | |
1821 | rgn_bb_table[idx++] = child; | |
1822 | BLOCK_TO_BB (child) = ++count; | |
1823 | CONTAINING_RGN (child) = nr_regions; | |
1824 | queue[head] = queue[tail--]; | |
1825 | ||
1826 | for (ps = s_succs[child]; ps; ps = ps->next) | |
1827 | if (INT_LIST_VAL (ps) != ENTRY_BLOCK | |
1828 | && INT_LIST_VAL (ps) != EXIT_BLOCK) | |
1829 | --degree[INT_LIST_VAL (ps)]; | |
1830 | } | |
1831 | else | |
1832 | --head; | |
8c660648 | 1833 | } |
15ebe47d | 1834 | ++nr_regions; |
8c660648 | 1835 | } |
8c660648 JL |
1836 | } |
1837 | } | |
1838 | } | |
1839 | ||
a2e68776 JL |
1840 | /* Any block that did not end up in a region is placed into a region |
1841 | by itself. */ | |
8c660648 JL |
1842 | for (i = 0; i < n_basic_blocks; i++) |
1843 | if (degree[i] >= 0) | |
1844 | { | |
1845 | rgn_bb_table[idx] = i; | |
1846 | RGN_NR_BLOCKS (nr_regions) = 1; | |
1847 | RGN_BLOCKS (nr_regions) = idx++; | |
1848 | CONTAINING_RGN (i) = nr_regions++; | |
1849 | BLOCK_TO_BB (i) = 0; | |
1850 | } | |
1851 | ||
a2e68776 JL |
1852 | free (passed); |
1853 | free (header); | |
1854 | free (inner); | |
1855 | free (in_queue); | |
cc132865 | 1856 | free (in_stack); |
a2e68776 | 1857 | } |
8c660648 JL |
1858 | |
1859 | ||
1860 | /* functions for regions scheduling information */ | |
1861 | ||
1862 | /* Compute dominators, probability, and potential-split-edges of bb. | |
1863 | Assume that these values were already computed for bb's predecessors. */ | |
1864 | ||
1865 | static void | |
1866 | compute_dom_prob_ps (bb) | |
1867 | int bb; | |
1868 | { | |
1869 | int nxt_in_edge, fst_in_edge, pred; | |
1870 | int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges; | |
1871 | ||
1872 | prob[bb] = 0.0; | |
1873 | if (IS_RGN_ENTRY (bb)) | |
1874 | { | |
1875 | BITSET_ADD (dom[bb], 0, bbset_size); | |
1876 | prob[bb] = 1.0; | |
1877 | return; | |
1878 | } | |
1879 | ||
1880 | fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb)); | |
1881 | ||
1882 | /* intialize dom[bb] to '111..1' */ | |
1883 | BITSET_INVERT (dom[bb], bbset_size); | |
1884 | ||
1885 | do | |
1886 | { | |
1887 | pred = FROM_BLOCK (nxt_in_edge); | |
1888 | BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size); | |
1889 | ||
1890 | BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)], | |
1891 | edgeset_size); | |
1892 | ||
1893 | BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size); | |
1894 | ||
1895 | nr_out_edges = 1; | |
1896 | nr_rgn_out_edges = 0; | |
1897 | fst_out_edge = OUT_EDGES (pred); | |
1898 | nxt_out_edge = NEXT_OUT (fst_out_edge); | |
1899 | BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)], | |
1900 | edgeset_size); | |
1901 | ||
1902 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size); | |
1903 | ||
1904 | /* the successor doesn't belong the region? */ | |
1905 | if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) != | |
1906 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1907 | ++nr_rgn_out_edges; | |
1908 | ||
1909 | while (fst_out_edge != nxt_out_edge) | |
1910 | { | |
1911 | ++nr_out_edges; | |
1912 | /* the successor doesn't belong the region? */ | |
1913 | if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) != | |
1914 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1915 | ++nr_rgn_out_edges; | |
1916 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size); | |
1917 | nxt_out_edge = NEXT_OUT (nxt_out_edge); | |
1918 | ||
1919 | } | |
1920 | ||
1921 | /* now nr_rgn_out_edges is the number of region-exit edges from pred, | |
1922 | and nr_out_edges will be the number of pred out edges not leaving | |
1923 | the region. */ | |
1924 | nr_out_edges -= nr_rgn_out_edges; | |
1925 | if (nr_rgn_out_edges > 0) | |
1926 | prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1927 | else | |
1928 | prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1929 | nxt_in_edge = NEXT_IN (nxt_in_edge); | |
1930 | } | |
1931 | while (fst_in_edge != nxt_in_edge); | |
1932 | ||
1933 | BITSET_ADD (dom[bb], bb, bbset_size); | |
1934 | BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size); | |
1935 | ||
1936 | if (sched_verbose >= 2) | |
1937 | fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb])); | |
1938 | } /* compute_dom_prob_ps */ | |
1939 | ||
1940 | /* functions for target info */ | |
1941 | ||
1942 | /* Compute in BL the list of split-edges of bb_src relatively to bb_trg. | |
1943 | Note that bb_trg dominates bb_src. */ | |
1944 | ||
1945 | static void | |
1946 | split_edges (bb_src, bb_trg, bl) | |
1947 | int bb_src; | |
1948 | int bb_trg; | |
1949 | edgelst *bl; | |
1950 | { | |
1951 | int es = edgeset_size; | |
1952 | edgeset src = (edgeset) alloca (es * sizeof (HOST_WIDE_INT)); | |
1953 | ||
1954 | while (es--) | |
1955 | src[es] = (pot_split[bb_src])[es]; | |
1956 | BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size); | |
1957 | extract_bitlst (src, edgeset_size, bl); | |
1958 | } | |
1959 | ||
1960 | ||
1961 | /* Find the valid candidate-source-blocks for the target block TRG, compute | |
1962 | their probability, and check if they are speculative or not. | |
1963 | For speculative sources, compute their update-blocks and split-blocks. */ | |
1964 | ||
1965 | static void | |
1966 | compute_trg_info (trg) | |
1967 | int trg; | |
1968 | { | |
1969 | register candidate *sp; | |
1970 | edgelst el; | |
1971 | int check_block, update_idx; | |
1972 | int i, j, k, fst_edge, nxt_edge; | |
1973 | ||
1974 | /* define some of the fields for the target bb as well */ | |
1975 | sp = candidate_table + trg; | |
1976 | sp->is_valid = 1; | |
1977 | sp->is_speculative = 0; | |
1978 | sp->src_prob = 100; | |
1979 | ||
1980 | for (i = trg + 1; i < current_nr_blocks; i++) | |
1981 | { | |
1982 | sp = candidate_table + i; | |
1983 | ||
1984 | sp->is_valid = IS_DOMINATED (i, trg); | |
1985 | if (sp->is_valid) | |
1986 | { | |
1987 | sp->src_prob = GET_SRC_PROB (i, trg); | |
1988 | sp->is_valid = (sp->src_prob >= MIN_PROBABILITY); | |
1989 | } | |
1990 | ||
1991 | if (sp->is_valid) | |
1992 | { | |
1993 | split_edges (i, trg, &el); | |
1994 | sp->is_speculative = (el.nr_members) ? 1 : 0; | |
1995 | if (sp->is_speculative && !flag_schedule_speculative) | |
1996 | sp->is_valid = 0; | |
1997 | } | |
1998 | ||
1999 | if (sp->is_valid) | |
2000 | { | |
2001 | sp->split_bbs.first_member = &bblst_table[bblst_last]; | |
2002 | sp->split_bbs.nr_members = el.nr_members; | |
2003 | for (j = 0; j < el.nr_members; bblst_last++, j++) | |
2004 | bblst_table[bblst_last] = | |
2005 | TO_BLOCK (rgn_edges[el.first_member[j]]); | |
2006 | sp->update_bbs.first_member = &bblst_table[bblst_last]; | |
2007 | update_idx = 0; | |
2008 | for (j = 0; j < el.nr_members; j++) | |
2009 | { | |
2010 | check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]); | |
2011 | fst_edge = nxt_edge = OUT_EDGES (check_block); | |
2012 | do | |
2013 | { | |
2014 | for (k = 0; k < el.nr_members; k++) | |
2015 | if (EDGE_TO_BIT (nxt_edge) == el.first_member[k]) | |
2016 | break; | |
2017 | ||
2018 | if (k >= el.nr_members) | |
2019 | { | |
2020 | bblst_table[bblst_last++] = TO_BLOCK (nxt_edge); | |
2021 | update_idx++; | |
2022 | } | |
2023 | ||
2024 | nxt_edge = NEXT_OUT (nxt_edge); | |
2025 | } | |
2026 | while (fst_edge != nxt_edge); | |
2027 | } | |
2028 | sp->update_bbs.nr_members = update_idx; | |
2029 | ||
2030 | } | |
2031 | else | |
2032 | { | |
2033 | sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0; | |
2034 | ||
2035 | sp->is_speculative = 0; | |
2036 | sp->src_prob = 0; | |
2037 | } | |
2038 | } | |
2039 | } /* compute_trg_info */ | |
2040 | ||
2041 | ||
2042 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2043 | ||
2044 | void | |
2045 | debug_candidate (i) | |
2046 | int i; | |
2047 | { | |
2048 | if (!candidate_table[i].is_valid) | |
2049 | return; | |
2050 | ||
2051 | if (candidate_table[i].is_speculative) | |
2052 | { | |
2053 | int j; | |
2054 | fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i); | |
2055 | ||
2056 | fprintf (dump, "split path: "); | |
2057 | for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++) | |
2058 | { | |
2059 | int b = candidate_table[i].split_bbs.first_member[j]; | |
2060 | ||
2061 | fprintf (dump, " %d ", b); | |
2062 | } | |
2063 | fprintf (dump, "\n"); | |
2064 | ||
2065 | fprintf (dump, "update path: "); | |
2066 | for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++) | |
2067 | { | |
2068 | int b = candidate_table[i].update_bbs.first_member[j]; | |
2069 | ||
2070 | fprintf (dump, " %d ", b); | |
2071 | } | |
2072 | fprintf (dump, "\n"); | |
2073 | } | |
2074 | else | |
2075 | { | |
2076 | fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i)); | |
2077 | } | |
2078 | } | |
2079 | ||
2080 | ||
2081 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2082 | ||
2083 | void | |
2084 | debug_candidates (trg) | |
2085 | int trg; | |
2086 | { | |
2087 | int i; | |
2088 | ||
2089 | fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n", | |
2090 | BB_TO_BLOCK (trg), trg); | |
2091 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2092 | debug_candidate (i); | |
2093 | } | |
2094 | ||
2095 | ||
2096 | /* functions for speculative scheduing */ | |
2097 | ||
2098 | /* Return 0 if x is a set of a register alive in the beginning of one | |
2099 | of the split-blocks of src, otherwise return 1. */ | |
2100 | ||
2101 | static int | |
2102 | check_live_1 (src, x) | |
2103 | int src; | |
2104 | rtx x; | |
2105 | { | |
5835e573 | 2106 | register int i; |
8c660648 JL |
2107 | register int regno; |
2108 | register rtx reg = SET_DEST (x); | |
2109 | ||
2110 | if (reg == 0) | |
2111 | return 1; | |
2112 | ||
2113 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2114 | || GET_CODE (reg) == SIGN_EXTRACT | |
2115 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2116 | reg = XEXP (reg, 0); | |
2117 | ||
c0222c21 DM |
2118 | if (GET_CODE (reg) == PARALLEL |
2119 | && GET_MODE (reg) == BLKmode) | |
2120 | { | |
2121 | register int i; | |
2122 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2123 | if (check_live_1 (src, XVECEXP (reg, 0, i))) | |
2124 | return 1; | |
2125 | return 0; | |
2126 | } | |
2127 | ||
8c660648 JL |
2128 | if (GET_CODE (reg) != REG) |
2129 | return 1; | |
2130 | ||
2131 | regno = REGNO (reg); | |
2132 | ||
2133 | if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) | |
2134 | { | |
2135 | /* Global registers are assumed live */ | |
2136 | return 0; | |
2137 | } | |
2138 | else | |
2139 | { | |
2140 | if (regno < FIRST_PSEUDO_REGISTER) | |
2141 | { | |
2142 | /* check for hard registers */ | |
2143 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2144 | while (--j >= 0) | |
2145 | { | |
2146 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2147 | { | |
2148 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2149 | ||
2150 | if (REGNO_REG_SET_P (basic_block_live_at_start[b], regno + j)) | |
2151 | { | |
2152 | return 0; | |
2153 | } | |
2154 | } | |
2155 | } | |
2156 | } | |
2157 | else | |
2158 | { | |
2159 | /* check for psuedo registers */ | |
2160 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2161 | { | |
2162 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2163 | ||
2164 | if (REGNO_REG_SET_P (basic_block_live_at_start[b], regno)) | |
2165 | { | |
2166 | return 0; | |
2167 | } | |
2168 | } | |
2169 | } | |
2170 | } | |
2171 | ||
2172 | return 1; | |
2173 | } | |
2174 | ||
2175 | ||
2176 | /* If x is a set of a register R, mark that R is alive in the beginning | |
2177 | of every update-block of src. */ | |
2178 | ||
2179 | static void | |
2180 | update_live_1 (src, x) | |
2181 | int src; | |
2182 | rtx x; | |
2183 | { | |
5835e573 | 2184 | register int i; |
8c660648 JL |
2185 | register int regno; |
2186 | register rtx reg = SET_DEST (x); | |
2187 | ||
2188 | if (reg == 0) | |
2189 | return; | |
2190 | ||
2191 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2192 | || GET_CODE (reg) == SIGN_EXTRACT | |
2193 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2194 | reg = XEXP (reg, 0); | |
2195 | ||
c0222c21 DM |
2196 | if (GET_CODE (reg) == PARALLEL |
2197 | && GET_MODE (reg) == BLKmode) | |
2198 | { | |
2199 | register int i; | |
2200 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2201 | update_live_1 (src, XVECEXP (reg, 0, i)); | |
2202 | return; | |
2203 | } | |
2204 | ||
8c660648 JL |
2205 | if (GET_CODE (reg) != REG) |
2206 | return; | |
2207 | ||
2208 | /* Global registers are always live, so the code below does not apply | |
2209 | to them. */ | |
2210 | ||
2211 | regno = REGNO (reg); | |
2212 | ||
2213 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
2214 | { | |
2215 | if (regno < FIRST_PSEUDO_REGISTER) | |
2216 | { | |
2217 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2218 | while (--j >= 0) | |
2219 | { | |
2220 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2221 | { | |
2222 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2223 | ||
2224 | SET_REGNO_REG_SET (basic_block_live_at_start[b], regno + j); | |
2225 | } | |
2226 | } | |
2227 | } | |
2228 | else | |
2229 | { | |
2230 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2231 | { | |
2232 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2233 | ||
2234 | SET_REGNO_REG_SET (basic_block_live_at_start[b], regno); | |
2235 | } | |
2236 | } | |
2237 | } | |
2238 | } | |
2239 | ||
2240 | ||
2241 | /* Return 1 if insn can be speculatively moved from block src to trg, | |
2242 | otherwise return 0. Called before first insertion of insn to | |
2243 | ready-list or before the scheduling. */ | |
2244 | ||
2245 | static int | |
5835e573 | 2246 | check_live (insn, src) |
8c660648 JL |
2247 | rtx insn; |
2248 | int src; | |
8c660648 JL |
2249 | { |
2250 | /* find the registers set by instruction */ | |
2251 | if (GET_CODE (PATTERN (insn)) == SET | |
2252 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2253 | return check_live_1 (src, PATTERN (insn)); | |
2254 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2255 | { | |
2256 | int j; | |
2257 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2258 | if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2259 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2260 | && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j))) | |
2261 | return 0; | |
2262 | ||
2263 | return 1; | |
2264 | } | |
2265 | ||
2266 | return 1; | |
2267 | } | |
2268 | ||
2269 | ||
2270 | /* Update the live registers info after insn was moved speculatively from | |
2271 | block src to trg. */ | |
2272 | ||
2273 | static void | |
5835e573 | 2274 | update_live (insn, src) |
8c660648 | 2275 | rtx insn; |
5835e573 | 2276 | int src; |
8c660648 JL |
2277 | { |
2278 | /* find the registers set by instruction */ | |
2279 | if (GET_CODE (PATTERN (insn)) == SET | |
2280 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2281 | update_live_1 (src, PATTERN (insn)); | |
2282 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2283 | { | |
2284 | int j; | |
2285 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2286 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2287 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2288 | update_live_1 (src, XVECEXP (PATTERN (insn), 0, j)); | |
2289 | } | |
2290 | } | |
2291 | ||
2292 | /* Exception Free Loads: | |
2293 | ||
2294 | We define five classes of speculative loads: IFREE, IRISKY, | |
2295 | PFREE, PRISKY, and MFREE. | |
2296 | ||
2297 | IFREE loads are loads that are proved to be exception-free, just | |
2298 | by examining the load insn. Examples for such loads are loads | |
2299 | from TOC and loads of global data. | |
2300 | ||
2301 | IRISKY loads are loads that are proved to be exception-risky, | |
2302 | just by examining the load insn. Examples for such loads are | |
2303 | volatile loads and loads from shared memory. | |
2304 | ||
2305 | PFREE loads are loads for which we can prove, by examining other | |
2306 | insns, that they are exception-free. Currently, this class consists | |
2307 | of loads for which we are able to find a "similar load", either in | |
2308 | the target block, or, if only one split-block exists, in that split | |
2309 | block. Load2 is similar to load1 if both have same single base | |
2310 | register. We identify only part of the similar loads, by finding | |
2311 | an insn upon which both load1 and load2 have a DEF-USE dependence. | |
2312 | ||
2313 | PRISKY loads are loads for which we can prove, by examining other | |
2314 | insns, that they are exception-risky. Currently we have two proofs for | |
2315 | such loads. The first proof detects loads that are probably guarded by a | |
2316 | test on the memory address. This proof is based on the | |
2317 | backward and forward data dependence information for the region. | |
2318 | Let load-insn be the examined load. | |
2319 | Load-insn is PRISKY iff ALL the following hold: | |
2320 | ||
2321 | - insn1 is not in the same block as load-insn | |
2322 | - there is a DEF-USE dependence chain (insn1, ..., load-insn) | |
2323 | - test-insn is either a compare or a branch, not in the same block as load-insn | |
2324 | - load-insn is reachable from test-insn | |
2325 | - there is a DEF-USE dependence chain (insn1, ..., test-insn) | |
2326 | ||
2327 | This proof might fail when the compare and the load are fed | |
2328 | by an insn not in the region. To solve this, we will add to this | |
2329 | group all loads that have no input DEF-USE dependence. | |
2330 | ||
2331 | The second proof detects loads that are directly or indirectly | |
2332 | fed by a speculative load. This proof is affected by the | |
2333 | scheduling process. We will use the flag fed_by_spec_load. | |
2334 | Initially, all insns have this flag reset. After a speculative | |
2335 | motion of an insn, if insn is either a load, or marked as | |
2336 | fed_by_spec_load, we will also mark as fed_by_spec_load every | |
2337 | insn1 for which a DEF-USE dependence (insn, insn1) exists. A | |
2338 | load which is fed_by_spec_load is also PRISKY. | |
2339 | ||
2340 | MFREE (maybe-free) loads are all the remaining loads. They may be | |
2341 | exception-free, but we cannot prove it. | |
2342 | ||
2343 | Now, all loads in IFREE and PFREE classes are considered | |
2344 | exception-free, while all loads in IRISKY and PRISKY classes are | |
2345 | considered exception-risky. As for loads in the MFREE class, | |
2346 | these are considered either exception-free or exception-risky, | |
2347 | depending on whether we are pessimistic or optimistic. We have | |
2348 | to take the pessimistic approach to assure the safety of | |
2349 | speculative scheduling, but we can take the optimistic approach | |
2350 | by invoking the -fsched_spec_load_dangerous option. */ | |
2351 | ||
2352 | enum INSN_TRAP_CLASS | |
2353 | { | |
2354 | TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2, | |
2355 | PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5 | |
2356 | }; | |
2357 | ||
2358 | #define WORST_CLASS(class1, class2) \ | |
2359 | ((class1 > class2) ? class1 : class2) | |
2360 | ||
2361 | /* Indexed by INSN_UID, and set if there's DEF-USE dependence between */ | |
2362 | /* some speculatively moved load insn and this one. */ | |
2363 | char *fed_by_spec_load; | |
2364 | char *is_load_insn; | |
2365 | ||
2366 | /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */ | |
2367 | #define IS_REACHABLE(bb_from, bb_to) \ | |
2368 | (bb_from == bb_to \ | |
2369 | || IS_RGN_ENTRY (bb_from) \ | |
2370 | || (bitset_member (ancestor_edges[bb_to], \ | |
2371 | EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \ | |
2372 | edgeset_size))) | |
2373 | #define FED_BY_SPEC_LOAD(insn) (fed_by_spec_load[INSN_UID (insn)]) | |
2374 | #define IS_LOAD_INSN(insn) (is_load_insn[INSN_UID (insn)]) | |
2375 | ||
2376 | /* Non-zero iff the address is comprised from at most 1 register */ | |
2377 | #define CONST_BASED_ADDRESS_P(x) \ | |
2378 | (GET_CODE (x) == REG \ | |
2379 | || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \ | |
2380 | || (GET_CODE (x) == LO_SUM)) \ | |
2381 | && (GET_CODE (XEXP (x, 0)) == CONST_INT \ | |
2382 | || GET_CODE (XEXP (x, 1)) == CONST_INT))) | |
2383 | ||
2384 | /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */ | |
2385 | ||
2386 | static void | |
2387 | set_spec_fed (load_insn) | |
2388 | rtx load_insn; | |
2389 | { | |
2390 | rtx link; | |
2391 | ||
2392 | for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1)) | |
2393 | if (GET_MODE (link) == VOIDmode) | |
2394 | FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1; | |
2395 | } /* set_spec_fed */ | |
2396 | ||
2397 | /* On the path from the insn to load_insn_bb, find a conditional branch */ | |
2398 | /* depending on insn, that guards the speculative load. */ | |
2399 | ||
2400 | static int | |
2401 | find_conditional_protection (insn, load_insn_bb) | |
2402 | rtx insn; | |
2403 | int load_insn_bb; | |
2404 | { | |
2405 | rtx link; | |
2406 | ||
2407 | /* iterate through DEF-USE forward dependences */ | |
2408 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
2409 | { | |
2410 | rtx next = XEXP (link, 0); | |
2411 | if ((CONTAINING_RGN (INSN_BLOCK (next)) == | |
2412 | CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb))) | |
2413 | && IS_REACHABLE (INSN_BB (next), load_insn_bb) | |
2414 | && load_insn_bb != INSN_BB (next) | |
2415 | && GET_MODE (link) == VOIDmode | |
2416 | && (GET_CODE (next) == JUMP_INSN | |
2417 | || find_conditional_protection (next, load_insn_bb))) | |
2418 | return 1; | |
2419 | } | |
2420 | return 0; | |
2421 | } /* find_conditional_protection */ | |
2422 | ||
2423 | /* Returns 1 if the same insn1 that participates in the computation | |
2424 | of load_insn's address is feeding a conditional branch that is | |
2425 | guarding on load_insn. This is true if we find a the two DEF-USE | |
2426 | chains: | |
2427 | insn1 -> ... -> conditional-branch | |
2428 | insn1 -> ... -> load_insn, | |
2429 | and if a flow path exist: | |
2430 | insn1 -> ... -> conditional-branch -> ... -> load_insn, | |
2431 | and if insn1 is on the path | |
2432 | region-entry -> ... -> bb_trg -> ... load_insn. | |
2433 | ||
2434 | Locate insn1 by climbing on LOG_LINKS from load_insn. | |
2435 | Locate the branch by following INSN_DEPEND from insn1. */ | |
2436 | ||
2437 | static int | |
2438 | is_conditionally_protected (load_insn, bb_src, bb_trg) | |
2439 | rtx load_insn; | |
2440 | int bb_src, bb_trg; | |
2441 | { | |
2442 | rtx link; | |
2443 | ||
2444 | for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1)) | |
2445 | { | |
2446 | rtx insn1 = XEXP (link, 0); | |
2447 | ||
2448 | /* must be a DEF-USE dependence upon non-branch */ | |
2449 | if (GET_MODE (link) != VOIDmode | |
2450 | || GET_CODE (insn1) == JUMP_INSN) | |
2451 | continue; | |
2452 | ||
2453 | /* must exist a path: region-entry -> ... -> bb_trg -> ... load_insn */ | |
2454 | if (INSN_BB (insn1) == bb_src | |
2455 | || (CONTAINING_RGN (INSN_BLOCK (insn1)) | |
2456 | != CONTAINING_RGN (BB_TO_BLOCK (bb_src))) | |
2457 | || (!IS_REACHABLE (bb_trg, INSN_BB (insn1)) | |
2458 | && !IS_REACHABLE (INSN_BB (insn1), bb_trg))) | |
2459 | continue; | |
2460 | ||
2461 | /* now search for the conditional-branch */ | |
2462 | if (find_conditional_protection (insn1, bb_src)) | |
2463 | return 1; | |
2464 | ||
2465 | /* recursive step: search another insn1, "above" current insn1. */ | |
2466 | return is_conditionally_protected (insn1, bb_src, bb_trg); | |
2467 | } | |
2468 | ||
2469 | /* the chain does not exsist */ | |
2470 | return 0; | |
2471 | } /* is_conditionally_protected */ | |
2472 | ||
2473 | /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence | |
2474 | load_insn can move speculatively from bb_src to bb_trg. All the | |
2475 | following must hold: | |
2476 | ||
2477 | (1) both loads have 1 base register (PFREE_CANDIDATEs). | |
2478 | (2) load_insn and load1 have a def-use dependence upon | |
2479 | the same insn 'insn1'. | |
2480 | (3) either load2 is in bb_trg, or: | |
2481 | - there's only one split-block, and | |
2482 | - load1 is on the escape path, and | |
2483 | ||
2484 | From all these we can conclude that the two loads access memory | |
2485 | addresses that differ at most by a constant, and hence if moving | |
2486 | load_insn would cause an exception, it would have been caused by | |
2487 | load2 anyhow. */ | |
2488 | ||
2489 | static int | |
2490 | is_pfree (load_insn, bb_src, bb_trg) | |
2491 | rtx load_insn; | |
2492 | int bb_src, bb_trg; | |
2493 | { | |
2494 | rtx back_link; | |
2495 | register candidate *candp = candidate_table + bb_src; | |
2496 | ||
2497 | if (candp->split_bbs.nr_members != 1) | |
2498 | /* must have exactly one escape block */ | |
2499 | return 0; | |
2500 | ||
2501 | for (back_link = LOG_LINKS (load_insn); | |
2502 | back_link; back_link = XEXP (back_link, 1)) | |
2503 | { | |
2504 | rtx insn1 = XEXP (back_link, 0); | |
2505 | ||
2506 | if (GET_MODE (back_link) == VOIDmode) | |
2507 | { | |
2508 | /* found a DEF-USE dependence (insn1, load_insn) */ | |
2509 | rtx fore_link; | |
2510 | ||
2511 | for (fore_link = INSN_DEPEND (insn1); | |
2512 | fore_link; fore_link = XEXP (fore_link, 1)) | |
2513 | { | |
2514 | rtx insn2 = XEXP (fore_link, 0); | |
2515 | if (GET_MODE (fore_link) == VOIDmode) | |
2516 | { | |
2517 | /* found a DEF-USE dependence (insn1, insn2) */ | |
ac957f13 | 2518 | if (haifa_classify_insn (insn2) != PFREE_CANDIDATE) |
8c660648 JL |
2519 | /* insn2 not guaranteed to be a 1 base reg load */ |
2520 | continue; | |
2521 | ||
2522 | if (INSN_BB (insn2) == bb_trg) | |
2523 | /* insn2 is the similar load, in the target block */ | |
2524 | return 1; | |
2525 | ||
2526 | if (*(candp->split_bbs.first_member) == INSN_BLOCK (insn2)) | |
2527 | /* insn2 is a similar load, in a split-block */ | |
2528 | return 1; | |
2529 | } | |
2530 | } | |
2531 | } | |
2532 | } | |
2533 | ||
2534 | /* couldn't find a similar load */ | |
2535 | return 0; | |
2536 | } /* is_pfree */ | |
2537 | ||
2538 | /* Returns a class that insn with GET_DEST(insn)=x may belong to, | |
2539 | as found by analyzing insn's expression. */ | |
2540 | ||
2541 | static int | |
2542 | may_trap_exp (x, is_store) | |
2543 | rtx x; | |
2544 | int is_store; | |
2545 | { | |
2546 | enum rtx_code code; | |
2547 | ||
2548 | if (x == 0) | |
2549 | return TRAP_FREE; | |
2550 | code = GET_CODE (x); | |
2551 | if (is_store) | |
2552 | { | |
2553 | if (code == MEM) | |
2554 | return TRAP_RISKY; | |
2555 | else | |
2556 | return TRAP_FREE; | |
2557 | } | |
2558 | if (code == MEM) | |
2559 | { | |
2560 | /* The insn uses memory */ | |
2561 | /* a volatile load */ | |
2562 | if (MEM_VOLATILE_P (x)) | |
2563 | return IRISKY; | |
2564 | /* an exception-free load */ | |
2565 | if (!may_trap_p (x)) | |
2566 | return IFREE; | |
2567 | /* a load with 1 base register, to be further checked */ | |
2568 | if (CONST_BASED_ADDRESS_P (XEXP (x, 0))) | |
2569 | return PFREE_CANDIDATE; | |
2570 | /* no info on the load, to be further checked */ | |
2571 | return PRISKY_CANDIDATE; | |
2572 | } | |
2573 | else | |
2574 | { | |
2575 | char *fmt; | |
2576 | int i, insn_class = TRAP_FREE; | |
2577 | ||
2578 | /* neither store nor load, check if it may cause a trap */ | |
2579 | if (may_trap_p (x)) | |
2580 | return TRAP_RISKY; | |
2581 | /* recursive step: walk the insn... */ | |
2582 | fmt = GET_RTX_FORMAT (code); | |
2583 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2584 | { | |
2585 | if (fmt[i] == 'e') | |
2586 | { | |
2587 | int tmp_class = may_trap_exp (XEXP (x, i), is_store); | |
2588 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2589 | } | |
2590 | else if (fmt[i] == 'E') | |
2591 | { | |
2592 | int j; | |
2593 | for (j = 0; j < XVECLEN (x, i); j++) | |
2594 | { | |
2595 | int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store); | |
2596 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2597 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2598 | break; | |
2599 | } | |
2600 | } | |
2601 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2602 | break; | |
2603 | } | |
2604 | return insn_class; | |
2605 | } | |
2606 | } /* may_trap_exp */ | |
2607 | ||
2608 | ||
2609 | /* Classifies insn for the purpose of verifying that it can be | |
2610 | moved speculatively, by examining it's patterns, returning: | |
2611 | TRAP_RISKY: store, or risky non-load insn (e.g. division by variable). | |
2612 | TRAP_FREE: non-load insn. | |
2613 | IFREE: load from a globaly safe location. | |
2614 | IRISKY: volatile load. | |
2615 | PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for | |
2616 | being either PFREE or PRISKY. */ | |
2617 | ||
2618 | static int | |
ac957f13 | 2619 | haifa_classify_insn (insn) |
8c660648 JL |
2620 | rtx insn; |
2621 | { | |
2622 | rtx pat = PATTERN (insn); | |
2623 | int tmp_class = TRAP_FREE; | |
2624 | int insn_class = TRAP_FREE; | |
2625 | enum rtx_code code; | |
2626 | ||
2627 | if (GET_CODE (pat) == PARALLEL) | |
2628 | { | |
2629 | int i, len = XVECLEN (pat, 0); | |
2630 | ||
2631 | for (i = len - 1; i >= 0; i--) | |
2632 | { | |
2633 | code = GET_CODE (XVECEXP (pat, 0, i)); | |
2634 | switch (code) | |
2635 | { | |
2636 | case CLOBBER: | |
2637 | /* test if it is a 'store' */ | |
2638 | tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1); | |
2639 | break; | |
2640 | case SET: | |
2641 | /* test if it is a store */ | |
2642 | tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1); | |
2643 | if (tmp_class == TRAP_RISKY) | |
2644 | break; | |
2645 | /* test if it is a load */ | |
2646 | tmp_class = | |
2647 | WORST_CLASS (tmp_class, | |
2648 | may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0)); | |
e0cd0770 JC |
2649 | break; |
2650 | case TRAP_IF: | |
2651 | tmp_class = TRAP_RISKY; | |
2652 | break; | |
8c660648 JL |
2653 | default:; |
2654 | } | |
2655 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2656 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2657 | break; | |
2658 | } | |
2659 | } | |
2660 | else | |
2661 | { | |
2662 | code = GET_CODE (pat); | |
2663 | switch (code) | |
2664 | { | |
2665 | case CLOBBER: | |
2666 | /* test if it is a 'store' */ | |
2667 | tmp_class = may_trap_exp (XEXP (pat, 0), 1); | |
2668 | break; | |
2669 | case SET: | |
2670 | /* test if it is a store */ | |
2671 | tmp_class = may_trap_exp (SET_DEST (pat), 1); | |
2672 | if (tmp_class == TRAP_RISKY) | |
2673 | break; | |
2674 | /* test if it is a load */ | |
2675 | tmp_class = | |
2676 | WORST_CLASS (tmp_class, | |
2677 | may_trap_exp (SET_SRC (pat), 0)); | |
e0cd0770 JC |
2678 | break; |
2679 | case TRAP_IF: | |
2680 | tmp_class = TRAP_RISKY; | |
2681 | break; | |
8c660648 JL |
2682 | default:; |
2683 | } | |
2684 | insn_class = tmp_class; | |
2685 | } | |
2686 | ||
2687 | return insn_class; | |
2688 | ||
ac957f13 | 2689 | } /* haifa_classify_insn */ |
8c660648 JL |
2690 | |
2691 | /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by | |
2692 | a load moved speculatively, or if load_insn is protected by | |
2693 | a compare on load_insn's address). */ | |
2694 | ||
2695 | static int | |
2696 | is_prisky (load_insn, bb_src, bb_trg) | |
2697 | rtx load_insn; | |
2698 | int bb_src, bb_trg; | |
2699 | { | |
2700 | if (FED_BY_SPEC_LOAD (load_insn)) | |
2701 | return 1; | |
2702 | ||
2703 | if (LOG_LINKS (load_insn) == NULL) | |
2704 | /* dependence may 'hide' out of the region. */ | |
2705 | return 1; | |
2706 | ||
2707 | if (is_conditionally_protected (load_insn, bb_src, bb_trg)) | |
2708 | return 1; | |
2709 | ||
2710 | return 0; | |
2711 | } /* is_prisky */ | |
2712 | ||
2713 | /* Insn is a candidate to be moved speculatively from bb_src to bb_trg. | |
2714 | Return 1 if insn is exception-free (and the motion is valid) | |
2715 | and 0 otherwise. */ | |
2716 | ||
2717 | static int | |
2718 | is_exception_free (insn, bb_src, bb_trg) | |
2719 | rtx insn; | |
2720 | int bb_src, bb_trg; | |
2721 | { | |
ac957f13 | 2722 | int insn_class = haifa_classify_insn (insn); |
8c660648 JL |
2723 | |
2724 | /* handle non-load insns */ | |
2725 | switch (insn_class) | |
2726 | { | |
2727 | case TRAP_FREE: | |
2728 | return 1; | |
2729 | case TRAP_RISKY: | |
2730 | return 0; | |
2731 | default:; | |
2732 | } | |
2733 | ||
2734 | /* handle loads */ | |
2735 | if (!flag_schedule_speculative_load) | |
2736 | return 0; | |
2737 | IS_LOAD_INSN (insn) = 1; | |
2738 | switch (insn_class) | |
2739 | { | |
2740 | case IFREE: | |
2741 | return (1); | |
2742 | case IRISKY: | |
2743 | return 0; | |
2744 | case PFREE_CANDIDATE: | |
2745 | if (is_pfree (insn, bb_src, bb_trg)) | |
2746 | return 1; | |
2747 | /* don't 'break' here: PFREE-candidate is also PRISKY-candidate */ | |
2748 | case PRISKY_CANDIDATE: | |
2749 | if (!flag_schedule_speculative_load_dangerous | |
2750 | || is_prisky (insn, bb_src, bb_trg)) | |
2751 | return 0; | |
2752 | break; | |
2753 | default:; | |
2754 | } | |
2755 | ||
2756 | return flag_schedule_speculative_load_dangerous; | |
2757 | } /* is_exception_free */ | |
2758 | ||
2759 | ||
2760 | /* Process an insn's memory dependencies. There are four kinds of | |
2761 | dependencies: | |
2762 | ||
2763 | (0) read dependence: read follows read | |
2764 | (1) true dependence: read follows write | |
2765 | (2) anti dependence: write follows read | |
2766 | (3) output dependence: write follows write | |
2767 | ||
2768 | We are careful to build only dependencies which actually exist, and | |
2769 | use transitivity to avoid building too many links. */ | |
2770 | \f | |
2771 | /* Return the INSN_LIST containing INSN in LIST, or NULL | |
2772 | if LIST does not contain INSN. */ | |
2773 | ||
cbb13457 | 2774 | HAIFA_INLINE static rtx |
8c660648 JL |
2775 | find_insn_list (insn, list) |
2776 | rtx insn; | |
2777 | rtx list; | |
2778 | { | |
2779 | while (list) | |
2780 | { | |
2781 | if (XEXP (list, 0) == insn) | |
2782 | return list; | |
2783 | list = XEXP (list, 1); | |
2784 | } | |
2785 | return 0; | |
2786 | } | |
2787 | ||
2788 | ||
2789 | /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 otherwise. */ | |
2790 | ||
cbb13457 | 2791 | HAIFA_INLINE static char |
8c660648 JL |
2792 | find_insn_mem_list (insn, x, list, list1) |
2793 | rtx insn, x; | |
2794 | rtx list, list1; | |
2795 | { | |
2796 | while (list) | |
2797 | { | |
2798 | if (XEXP (list, 0) == insn | |
2799 | && XEXP (list1, 0) == x) | |
2800 | return 1; | |
2801 | list = XEXP (list, 1); | |
2802 | list1 = XEXP (list1, 1); | |
2803 | } | |
2804 | return 0; | |
2805 | } | |
2806 | ||
2807 | ||
2808 | /* Compute the function units used by INSN. This caches the value | |
2809 | returned by function_units_used. A function unit is encoded as the | |
2810 | unit number if the value is non-negative and the compliment of a | |
2811 | mask if the value is negative. A function unit index is the | |
2812 | non-negative encoding. */ | |
2813 | ||
cbb13457 | 2814 | HAIFA_INLINE static int |
8c660648 JL |
2815 | insn_unit (insn) |
2816 | rtx insn; | |
2817 | { | |
2818 | register int unit = INSN_UNIT (insn); | |
2819 | ||
2820 | if (unit == 0) | |
2821 | { | |
2822 | recog_memoized (insn); | |
2823 | ||
2824 | /* A USE insn, or something else we don't need to understand. | |
2825 | We can't pass these directly to function_units_used because it will | |
2826 | trigger a fatal error for unrecognizable insns. */ | |
2827 | if (INSN_CODE (insn) < 0) | |
2828 | unit = -1; | |
2829 | else | |
2830 | { | |
2831 | unit = function_units_used (insn); | |
2832 | /* Increment non-negative values so we can cache zero. */ | |
2833 | if (unit >= 0) | |
2834 | unit++; | |
2835 | } | |
2836 | /* We only cache 16 bits of the result, so if the value is out of | |
2837 | range, don't cache it. */ | |
2838 | if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT | |
2839 | || unit >= 0 | |
2840 | || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) | |
2841 | INSN_UNIT (insn) = unit; | |
2842 | } | |
2843 | return (unit > 0 ? unit - 1 : unit); | |
2844 | } | |
2845 | ||
2846 | /* Compute the blockage range for executing INSN on UNIT. This caches | |
2847 | the value returned by the blockage_range_function for the unit. | |
2848 | These values are encoded in an int where the upper half gives the | |
2849 | minimum value and the lower half gives the maximum value. */ | |
2850 | ||
cbb13457 | 2851 | HAIFA_INLINE static unsigned int |
8c660648 JL |
2852 | blockage_range (unit, insn) |
2853 | int unit; | |
2854 | rtx insn; | |
2855 | { | |
2856 | unsigned int blockage = INSN_BLOCKAGE (insn); | |
2857 | unsigned int range; | |
2858 | ||
79c9824e | 2859 | if ((int) UNIT_BLOCKED (blockage) != unit + 1) |
8c660648 JL |
2860 | { |
2861 | range = function_units[unit].blockage_range_function (insn); | |
2862 | /* We only cache the blockage range for one unit and then only if | |
2863 | the values fit. */ | |
2864 | if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) | |
2865 | INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); | |
2866 | } | |
2867 | else | |
2868 | range = BLOCKAGE_RANGE (blockage); | |
2869 | ||
2870 | return range; | |
2871 | } | |
2872 | ||
2873 | /* A vector indexed by function unit instance giving the last insn to use | |
2874 | the unit. The value of the function unit instance index for unit U | |
2875 | instance I is (U + I * FUNCTION_UNITS_SIZE). */ | |
2876 | static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2877 | ||
2878 | /* A vector indexed by function unit instance giving the minimum time when | |
2879 | the unit will unblock based on the maximum blockage cost. */ | |
2880 | static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2881 | ||
2882 | /* A vector indexed by function unit number giving the number of insns | |
2883 | that remain to use the unit. */ | |
2884 | static int unit_n_insns[FUNCTION_UNITS_SIZE]; | |
2885 | ||
2886 | /* Reset the function unit state to the null state. */ | |
2887 | ||
2888 | static void | |
2889 | clear_units () | |
2890 | { | |
2891 | bzero ((char *) unit_last_insn, sizeof (unit_last_insn)); | |
2892 | bzero ((char *) unit_tick, sizeof (unit_tick)); | |
2893 | bzero ((char *) unit_n_insns, sizeof (unit_n_insns)); | |
2894 | } | |
2895 | ||
2896 | /* Return the issue-delay of an insn */ | |
2897 | ||
cbb13457 | 2898 | HAIFA_INLINE static int |
8c660648 JL |
2899 | insn_issue_delay (insn) |
2900 | rtx insn; | |
2901 | { | |
8c660648 JL |
2902 | int i, delay = 0; |
2903 | int unit = insn_unit (insn); | |
2904 | ||
2905 | /* efficiency note: in fact, we are working 'hard' to compute a | |
2906 | value that was available in md file, and is not available in | |
2907 | function_units[] structure. It would be nice to have this | |
2908 | value there, too. */ | |
2909 | if (unit >= 0) | |
2910 | { | |
2911 | if (function_units[unit].blockage_range_function && | |
2912 | function_units[unit].blockage_function) | |
2913 | delay = function_units[unit].blockage_function (insn, insn); | |
2914 | } | |
2915 | else | |
2916 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2917 | if ((unit & 1) != 0 && function_units[i].blockage_range_function | |
2918 | && function_units[i].blockage_function) | |
2919 | delay = MAX (delay, function_units[i].blockage_function (insn, insn)); | |
2920 | ||
2921 | return delay; | |
2922 | } | |
2923 | ||
2924 | /* Return the actual hazard cost of executing INSN on the unit UNIT, | |
2925 | instance INSTANCE at time CLOCK if the previous actual hazard cost | |
2926 | was COST. */ | |
2927 | ||
cbb13457 | 2928 | HAIFA_INLINE static int |
8c660648 JL |
2929 | actual_hazard_this_instance (unit, instance, insn, clock, cost) |
2930 | int unit, instance, clock, cost; | |
2931 | rtx insn; | |
2932 | { | |
2933 | int tick = unit_tick[instance]; /* issue time of the last issued insn */ | |
2934 | ||
2935 | if (tick - clock > cost) | |
2936 | { | |
2937 | /* The scheduler is operating forward, so unit's last insn is the | |
2938 | executing insn and INSN is the candidate insn. We want a | |
2939 | more exact measure of the blockage if we execute INSN at CLOCK | |
2940 | given when we committed the execution of the unit's last insn. | |
2941 | ||
2942 | The blockage value is given by either the unit's max blockage | |
2943 | constant, blockage range function, or blockage function. Use | |
2944 | the most exact form for the given unit. */ | |
2945 | ||
2946 | if (function_units[unit].blockage_range_function) | |
2947 | { | |
2948 | if (function_units[unit].blockage_function) | |
2949 | tick += (function_units[unit].blockage_function | |
2950 | (unit_last_insn[instance], insn) | |
2951 | - function_units[unit].max_blockage); | |
2952 | else | |
2953 | tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) | |
2954 | - function_units[unit].max_blockage); | |
2955 | } | |
2956 | if (tick - clock > cost) | |
2957 | cost = tick - clock; | |
2958 | } | |
2959 | return cost; | |
2960 | } | |
2961 | ||
2962 | /* Record INSN as having begun execution on the units encoded by UNIT at | |
2963 | time CLOCK. */ | |
2964 | ||
cbb13457 | 2965 | HAIFA_INLINE static void |
8c660648 JL |
2966 | schedule_unit (unit, insn, clock) |
2967 | int unit, clock; | |
2968 | rtx insn; | |
2969 | { | |
2970 | int i; | |
2971 | ||
2972 | if (unit >= 0) | |
2973 | { | |
2974 | int instance = unit; | |
2975 | #if MAX_MULTIPLICITY > 1 | |
2976 | /* Find the first free instance of the function unit and use that | |
2977 | one. We assume that one is free. */ | |
2978 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2979 | { | |
2980 | if (!actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
2981 | break; | |
2982 | instance += FUNCTION_UNITS_SIZE; | |
2983 | } | |
2984 | #endif | |
2985 | unit_last_insn[instance] = insn; | |
2986 | unit_tick[instance] = (clock + function_units[unit].max_blockage); | |
2987 | } | |
2988 | else | |
2989 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2990 | if ((unit & 1) != 0) | |
2991 | schedule_unit (i, insn, clock); | |
2992 | } | |
2993 | ||
2994 | /* Return the actual hazard cost of executing INSN on the units encoded by | |
2995 | UNIT at time CLOCK if the previous actual hazard cost was COST. */ | |
2996 | ||
cbb13457 | 2997 | HAIFA_INLINE static int |
8c660648 JL |
2998 | actual_hazard (unit, insn, clock, cost) |
2999 | int unit, clock, cost; | |
3000 | rtx insn; | |
3001 | { | |
3002 | int i; | |
3003 | ||
3004 | if (unit >= 0) | |
3005 | { | |
3006 | /* Find the instance of the function unit with the minimum hazard. */ | |
3007 | int instance = unit; | |
3008 | int best_cost = actual_hazard_this_instance (unit, instance, insn, | |
3009 | clock, cost); | |
3010 | int this_cost; | |
3011 | ||
3012 | #if MAX_MULTIPLICITY > 1 | |
3013 | if (best_cost > cost) | |
3014 | { | |
3015 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
3016 | { | |
3017 | instance += FUNCTION_UNITS_SIZE; | |
3018 | this_cost = actual_hazard_this_instance (unit, instance, insn, | |
3019 | clock, cost); | |
3020 | if (this_cost < best_cost) | |
3021 | { | |
3022 | best_cost = this_cost; | |
3023 | if (this_cost <= cost) | |
3024 | break; | |
3025 | } | |
3026 | } | |
3027 | } | |
3028 | #endif | |
3029 | cost = MAX (cost, best_cost); | |
3030 | } | |
3031 | else | |
3032 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3033 | if ((unit & 1) != 0) | |
3034 | cost = actual_hazard (i, insn, clock, cost); | |
3035 | ||
3036 | return cost; | |
3037 | } | |
3038 | ||
3039 | /* Return the potential hazard cost of executing an instruction on the | |
3040 | units encoded by UNIT if the previous potential hazard cost was COST. | |
3041 | An insn with a large blockage time is chosen in preference to one | |
3042 | with a smaller time; an insn that uses a unit that is more likely | |
3043 | to be used is chosen in preference to one with a unit that is less | |
3044 | used. We are trying to minimize a subsequent actual hazard. */ | |
3045 | ||
cbb13457 | 3046 | HAIFA_INLINE static int |
8c660648 JL |
3047 | potential_hazard (unit, insn, cost) |
3048 | int unit, cost; | |
3049 | rtx insn; | |
3050 | { | |
3051 | int i, ncost; | |
3052 | unsigned int minb, maxb; | |
3053 | ||
3054 | if (unit >= 0) | |
3055 | { | |
3056 | minb = maxb = function_units[unit].max_blockage; | |
3057 | if (maxb > 1) | |
3058 | { | |
3059 | if (function_units[unit].blockage_range_function) | |
3060 | { | |
3061 | maxb = minb = blockage_range (unit, insn); | |
3062 | maxb = MAX_BLOCKAGE_COST (maxb); | |
3063 | minb = MIN_BLOCKAGE_COST (minb); | |
3064 | } | |
3065 | ||
3066 | if (maxb > 1) | |
3067 | { | |
3068 | /* Make the number of instructions left dominate. Make the | |
3069 | minimum delay dominate the maximum delay. If all these | |
3070 | are the same, use the unit number to add an arbitrary | |
3071 | ordering. Other terms can be added. */ | |
3072 | ncost = minb * 0x40 + maxb; | |
3073 | ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; | |
3074 | if (ncost > cost) | |
3075 | cost = ncost; | |
3076 | } | |
3077 | } | |
3078 | } | |
3079 | else | |
3080 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3081 | if ((unit & 1) != 0) | |
3082 | cost = potential_hazard (i, insn, cost); | |
3083 | ||
3084 | return cost; | |
3085 | } | |
3086 | ||
3087 | /* Compute cost of executing INSN given the dependence LINK on the insn USED. | |
3088 | This is the number of cycles between instruction issue and | |
3089 | instruction results. */ | |
3090 | ||
cbb13457 | 3091 | HAIFA_INLINE static int |
8c660648 JL |
3092 | insn_cost (insn, link, used) |
3093 | rtx insn, link, used; | |
3094 | { | |
3095 | register int cost = INSN_COST (insn); | |
3096 | ||
3097 | if (cost == 0) | |
3098 | { | |
3099 | recog_memoized (insn); | |
3100 | ||
3101 | /* A USE insn, or something else we don't need to understand. | |
3102 | We can't pass these directly to result_ready_cost because it will | |
3103 | trigger a fatal error for unrecognizable insns. */ | |
3104 | if (INSN_CODE (insn) < 0) | |
3105 | { | |
3106 | INSN_COST (insn) = 1; | |
3107 | return 1; | |
3108 | } | |
3109 | else | |
3110 | { | |
3111 | cost = result_ready_cost (insn); | |
3112 | ||
3113 | if (cost < 1) | |
3114 | cost = 1; | |
3115 | ||
3116 | INSN_COST (insn) = cost; | |
3117 | } | |
3118 | } | |
3119 | ||
3120 | /* in this case estimate cost without caring how insn is used. */ | |
3121 | if (link == 0 && used == 0) | |
3122 | return cost; | |
3123 | ||
3124 | /* A USE insn should never require the value used to be computed. This | |
3125 | allows the computation of a function's result and parameter values to | |
3126 | overlap the return and call. */ | |
3127 | recog_memoized (used); | |
3128 | if (INSN_CODE (used) < 0) | |
3129 | LINK_COST_FREE (link) = 1; | |
3130 | ||
3131 | /* If some dependencies vary the cost, compute the adjustment. Most | |
3132 | commonly, the adjustment is complete: either the cost is ignored | |
3133 | (in the case of an output- or anti-dependence), or the cost is | |
3134 | unchanged. These values are cached in the link as LINK_COST_FREE | |
3135 | and LINK_COST_ZERO. */ | |
3136 | ||
3137 | if (LINK_COST_FREE (link)) | |
3138 | cost = 1; | |
3139 | #ifdef ADJUST_COST | |
3140 | else if (!LINK_COST_ZERO (link)) | |
3141 | { | |
3142 | int ncost = cost; | |
3143 | ||
3144 | ADJUST_COST (used, link, insn, ncost); | |
3145 | if (ncost <= 1) | |
3146 | LINK_COST_FREE (link) = ncost = 1; | |
3147 | if (cost == ncost) | |
3148 | LINK_COST_ZERO (link) = 1; | |
3149 | cost = ncost; | |
3150 | } | |
3151 | #endif | |
3152 | return cost; | |
3153 | } | |
3154 | ||
3155 | /* Compute the priority number for INSN. */ | |
3156 | ||
3157 | static int | |
3158 | priority (insn) | |
3159 | rtx insn; | |
3160 | { | |
3161 | int this_priority; | |
3162 | rtx link; | |
3163 | ||
3164 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
3165 | return 0; | |
3166 | ||
3167 | if ((this_priority = INSN_PRIORITY (insn)) == 0) | |
3168 | { | |
3169 | if (INSN_DEPEND (insn) == 0) | |
3170 | this_priority = insn_cost (insn, 0, 0); | |
3171 | else | |
3172 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
3173 | { | |
3174 | rtx next; | |
3175 | int next_priority; | |
3176 | ||
6d8ccdbb JL |
3177 | if (RTX_INTEGRATED_P (link)) |
3178 | continue; | |
3179 | ||
8c660648 JL |
3180 | next = XEXP (link, 0); |
3181 | ||
3182 | /* critical path is meaningful in block boundaries only */ | |
3183 | if (INSN_BLOCK (next) != INSN_BLOCK (insn)) | |
3184 | continue; | |
3185 | ||
3186 | next_priority = insn_cost (insn, link, next) + priority (next); | |
3187 | if (next_priority > this_priority) | |
3188 | this_priority = next_priority; | |
3189 | } | |
3190 | INSN_PRIORITY (insn) = this_priority; | |
3191 | } | |
3192 | return this_priority; | |
3193 | } | |
3194 | \f | |
3195 | ||
3196 | /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add | |
3197 | them to the unused_*_list variables, so that they can be reused. */ | |
3198 | ||
8c660648 JL |
3199 | static void |
3200 | free_pending_lists () | |
3201 | { | |
8c660648 JL |
3202 | if (current_nr_blocks <= 1) |
3203 | { | |
ebb7b10b RH |
3204 | free_list (&pending_read_insns, &unused_insn_list); |
3205 | free_list (&pending_write_insns, &unused_insn_list); | |
3206 | free_list (&pending_read_mems, &unused_expr_list); | |
3207 | free_list (&pending_write_mems, &unused_expr_list); | |
8c660648 JL |
3208 | } |
3209 | else | |
3210 | { | |
3211 | /* interblock scheduling */ | |
3212 | int bb; | |
3213 | ||
3214 | for (bb = 0; bb < current_nr_blocks; bb++) | |
3215 | { | |
ebb7b10b RH |
3216 | free_list (&bb_pending_read_insns[bb], &unused_insn_list); |
3217 | free_list (&bb_pending_write_insns[bb], &unused_insn_list); | |
3218 | free_list (&bb_pending_read_mems[bb], &unused_expr_list); | |
3219 | free_list (&bb_pending_write_mems[bb], &unused_expr_list); | |
8c660648 JL |
3220 | } |
3221 | } | |
3222 | } | |
3223 | ||
3224 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
3225 | The MEM is a memory reference contained within INSN, which we are saving | |
3226 | so that we can do memory aliasing on it. */ | |
3227 | ||
3228 | static void | |
3229 | add_insn_mem_dependence (insn_list, mem_list, insn, mem) | |
3230 | rtx *insn_list, *mem_list, insn, mem; | |
3231 | { | |
3232 | register rtx link; | |
3233 | ||
ebb7b10b | 3234 | link = alloc_INSN_LIST (insn, *insn_list); |
8c660648 JL |
3235 | *insn_list = link; |
3236 | ||
ebb7b10b | 3237 | link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list); |
8c660648 JL |
3238 | *mem_list = link; |
3239 | ||
3240 | pending_lists_length++; | |
3241 | } | |
3242 | \f | |
3243 | ||
3244 | /* Make a dependency between every memory reference on the pending lists | |
3245 | and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush | |
3246 | the read list. */ | |
3247 | ||
3248 | static void | |
3249 | flush_pending_lists (insn, only_write) | |
3250 | rtx insn; | |
3251 | int only_write; | |
3252 | { | |
3253 | rtx u; | |
3254 | rtx link; | |
3255 | ||
3256 | while (pending_read_insns && ! only_write) | |
3257 | { | |
3258 | add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI); | |
3259 | ||
3260 | link = pending_read_insns; | |
3261 | pending_read_insns = XEXP (pending_read_insns, 1); | |
3262 | XEXP (link, 1) = unused_insn_list; | |
3263 | unused_insn_list = link; | |
3264 | ||
3265 | link = pending_read_mems; | |
3266 | pending_read_mems = XEXP (pending_read_mems, 1); | |
3267 | XEXP (link, 1) = unused_expr_list; | |
3268 | unused_expr_list = link; | |
3269 | } | |
3270 | while (pending_write_insns) | |
3271 | { | |
3272 | add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI); | |
3273 | ||
3274 | link = pending_write_insns; | |
3275 | pending_write_insns = XEXP (pending_write_insns, 1); | |
3276 | XEXP (link, 1) = unused_insn_list; | |
3277 | unused_insn_list = link; | |
3278 | ||
3279 | link = pending_write_mems; | |
3280 | pending_write_mems = XEXP (pending_write_mems, 1); | |
3281 | XEXP (link, 1) = unused_expr_list; | |
3282 | unused_expr_list = link; | |
3283 | } | |
3284 | pending_lists_length = 0; | |
3285 | ||
3286 | /* last_pending_memory_flush is now a list of insns */ | |
3287 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3288 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3289 | ||
ebb7b10b RH |
3290 | free_list (&last_pending_memory_flush, &unused_insn_list); |
3291 | last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); | |
8c660648 JL |
3292 | } |
3293 | ||
3294 | /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated | |
3295 | by the write to the destination of X, and reads of everything mentioned. */ | |
3296 | ||
3297 | static void | |
3298 | sched_analyze_1 (x, insn) | |
3299 | rtx x; | |
3300 | rtx insn; | |
3301 | { | |
3302 | register int regno; | |
3303 | register rtx dest = SET_DEST (x); | |
3304 | ||
3305 | if (dest == 0) | |
3306 | return; | |
3307 | ||
c0222c21 DM |
3308 | if (GET_CODE (dest) == PARALLEL |
3309 | && GET_MODE (dest) == BLKmode) | |
3310 | { | |
3311 | register int i; | |
3312 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
3313 | sched_analyze_1 (XVECEXP (dest, 0, i), insn); | |
3314 | if (GET_CODE (x) == SET) | |
3315 | sched_analyze_2 (SET_SRC (x), insn); | |
3316 | return; | |
3317 | } | |
3318 | ||
8c660648 JL |
3319 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG |
3320 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3321 | { | |
3322 | if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3323 | { | |
3324 | /* The second and third arguments are values read by this insn. */ | |
3325 | sched_analyze_2 (XEXP (dest, 1), insn); | |
3326 | sched_analyze_2 (XEXP (dest, 2), insn); | |
3327 | } | |
3328 | dest = SUBREG_REG (dest); | |
3329 | } | |
3330 | ||
3331 | if (GET_CODE (dest) == REG) | |
3332 | { | |
3333 | register int i; | |
3334 | ||
3335 | regno = REGNO (dest); | |
3336 | ||
3337 | /* A hard reg in a wide mode may really be multiple registers. | |
3338 | If so, mark all of them just like the first. */ | |
3339 | if (regno < FIRST_PSEUDO_REGISTER) | |
3340 | { | |
3341 | i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
3342 | while (--i >= 0) | |
3343 | { | |
3344 | rtx u; | |
3345 | ||
3346 | for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1)) | |
3347 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3348 | reg_last_uses[regno + i] = 0; | |
3349 | ||
3350 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3351 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3352 | ||
3353 | SET_REGNO_REG_SET (reg_pending_sets, regno + i); | |
3354 | ||
3355 | if ((call_used_regs[regno + i] || global_regs[regno + i])) | |
3356 | /* Function calls clobber all call_used regs. */ | |
3357 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3358 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3359 | } | |
3360 | } | |
3361 | else | |
3362 | { | |
3363 | rtx u; | |
3364 | ||
3365 | for (u = reg_last_uses[regno]; u; u = XEXP (u, 1)) | |
3366 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3367 | reg_last_uses[regno] = 0; | |
3368 | ||
3369 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3370 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3371 | ||
3372 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
3373 | ||
3374 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3375 | by that during reloading. We need only add dependencies for | |
3376 | the address in the REG_EQUIV note. */ | |
3377 | if (!reload_completed | |
3378 | && reg_known_equiv_p[regno] | |
3379 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3380 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3381 | ||
3382 | /* Don't let it cross a call after scheduling if it doesn't | |
3383 | already cross one. */ | |
3384 | ||
3385 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3386 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3387 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3388 | } | |
3389 | } | |
3390 | else if (GET_CODE (dest) == MEM) | |
3391 | { | |
3392 | /* Writing memory. */ | |
3393 | ||
3394 | if (pending_lists_length > 32) | |
3395 | { | |
3396 | /* Flush all pending reads and writes to prevent the pending lists | |
3397 | from getting any larger. Insn scheduling runs too slowly when | |
3398 | these lists get long. The number 32 was chosen because it | |
3399 | seems like a reasonable number. When compiling GCC with itself, | |
3400 | this flush occurs 8 times for sparc, and 10 times for m88k using | |
3401 | the number 32. */ | |
3402 | flush_pending_lists (insn, 0); | |
3403 | } | |
3404 | else | |
3405 | { | |
3406 | rtx u; | |
3407 | rtx pending, pending_mem; | |
3408 | ||
3409 | pending = pending_read_insns; | |
3410 | pending_mem = pending_read_mems; | |
3411 | while (pending) | |
3412 | { | |
3413 | /* If a dependency already exists, don't create a new one. */ | |
3414 | if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) | |
3415 | if (anti_dependence (XEXP (pending_mem, 0), dest)) | |
3416 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
3417 | ||
3418 | pending = XEXP (pending, 1); | |
3419 | pending_mem = XEXP (pending_mem, 1); | |
3420 | } | |
3421 | ||
3422 | pending = pending_write_insns; | |
3423 | pending_mem = pending_write_mems; | |
3424 | while (pending) | |
3425 | { | |
3426 | /* If a dependency already exists, don't create a new one. */ | |
3427 | if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) | |
3428 | if (output_dependence (XEXP (pending_mem, 0), dest)) | |
3429 | add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); | |
3430 | ||
3431 | pending = XEXP (pending, 1); | |
3432 | pending_mem = XEXP (pending_mem, 1); | |
3433 | } | |
3434 | ||
3435 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3436 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3437 | ||
3438 | add_insn_mem_dependence (&pending_write_insns, &pending_write_mems, | |
3439 | insn, dest); | |
3440 | } | |
3441 | sched_analyze_2 (XEXP (dest, 0), insn); | |
3442 | } | |
3443 | ||
3444 | /* Analyze reads. */ | |
3445 | if (GET_CODE (x) == SET) | |
3446 | sched_analyze_2 (SET_SRC (x), insn); | |
3447 | } | |
3448 | ||
3449 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
3450 | ||
3451 | static void | |
3452 | sched_analyze_2 (x, insn) | |
3453 | rtx x; | |
3454 | rtx insn; | |
3455 | { | |
3456 | register int i; | |
3457 | register int j; | |
3458 | register enum rtx_code code; | |
3459 | register char *fmt; | |
3460 | ||
3461 | if (x == 0) | |
3462 | return; | |
3463 | ||
3464 | code = GET_CODE (x); | |
3465 | ||
3466 | switch (code) | |
3467 | { | |
3468 | case CONST_INT: | |
3469 | case CONST_DOUBLE: | |
3470 | case SYMBOL_REF: | |
3471 | case CONST: | |
3472 | case LABEL_REF: | |
3473 | /* Ignore constants. Note that we must handle CONST_DOUBLE here | |
3474 | because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but | |
3475 | this does not mean that this insn is using cc0. */ | |
3476 | return; | |
3477 | ||
3478 | #ifdef HAVE_cc0 | |
3479 | case CC0: | |
3480 | { | |
3481 | rtx link, prev; | |
3482 | ||
3483 | /* User of CC0 depends on immediately preceding insn. */ | |
3484 | SCHED_GROUP_P (insn) = 1; | |
3485 | ||
3486 | /* There may be a note before this insn now, but all notes will | |
3487 | be removed before we actually try to schedule the insns, so | |
3488 | it won't cause a problem later. We must avoid it here though. */ | |
3489 | prev = prev_nonnote_insn (insn); | |
3490 | ||
3491 | /* Make a copy of all dependencies on the immediately previous insn, | |
3492 | and add to this insn. This is so that all the dependencies will | |
3493 | apply to the group. Remove an explicit dependence on this insn | |
3494 | as SCHED_GROUP_P now represents it. */ | |
3495 | ||
3496 | if (find_insn_list (prev, LOG_LINKS (insn))) | |
3497 | remove_dependence (insn, prev); | |
3498 | ||
3499 | for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) | |
3500 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3501 | ||
3502 | return; | |
3503 | } | |
3504 | #endif | |
3505 | ||
3506 | case REG: | |
3507 | { | |
3508 | rtx u; | |
3509 | int regno = REGNO (x); | |
3510 | if (regno < FIRST_PSEUDO_REGISTER) | |
3511 | { | |
3512 | int i; | |
3513 | ||
3514 | i = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3515 | while (--i >= 0) | |
3516 | { | |
3517 | reg_last_uses[regno + i] | |
ebb7b10b | 3518 | = alloc_INSN_LIST (insn, reg_last_uses[regno + i]); |
8c660648 JL |
3519 | |
3520 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3521 | add_dependence (insn, XEXP (u, 0), 0); | |
3522 | ||
3523 | if ((call_used_regs[regno + i] || global_regs[regno + i])) | |
3524 | /* Function calls clobber all call_used regs. */ | |
3525 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3526 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3527 | } | |
3528 | } | |
3529 | else | |
3530 | { | |
ebb7b10b | 3531 | reg_last_uses[regno] = alloc_INSN_LIST (insn, reg_last_uses[regno]); |
8c660648 JL |
3532 | |
3533 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3534 | add_dependence (insn, XEXP (u, 0), 0); | |
3535 | ||
3536 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3537 | by that during reloading. We need only add dependencies for | |
3538 | the address in the REG_EQUIV note. */ | |
3539 | if (!reload_completed | |
3540 | && reg_known_equiv_p[regno] | |
3541 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3542 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3543 | ||
3544 | /* If the register does not already cross any calls, then add this | |
3545 | insn to the sched_before_next_call list so that it will still | |
3546 | not cross calls after scheduling. */ | |
3547 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3548 | add_dependence (sched_before_next_call, insn, REG_DEP_ANTI); | |
3549 | } | |
3550 | return; | |
3551 | } | |
3552 | ||
3553 | case MEM: | |
3554 | { | |
3555 | /* Reading memory. */ | |
3556 | rtx u; | |
3557 | rtx pending, pending_mem; | |
3558 | ||
3559 | pending = pending_read_insns; | |
3560 | pending_mem = pending_read_mems; | |
3561 | while (pending) | |
3562 | { | |
3563 | /* If a dependency already exists, don't create a new one. */ | |
3564 | if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) | |
3565 | if (read_dependence (XEXP (pending_mem, 0), x)) | |
3566 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
3567 | ||
3568 | pending = XEXP (pending, 1); | |
3569 | pending_mem = XEXP (pending_mem, 1); | |
3570 | } | |
3571 | ||
3572 | pending = pending_write_insns; | |
3573 | pending_mem = pending_write_mems; | |
3574 | while (pending) | |
3575 | { | |
3576 | /* If a dependency already exists, don't create a new one. */ | |
3577 | if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn))) | |
3578 | if (true_dependence (XEXP (pending_mem, 0), VOIDmode, | |
3579 | x, rtx_varies_p)) | |
3580 | add_dependence (insn, XEXP (pending, 0), 0); | |
3581 | ||
3582 | pending = XEXP (pending, 1); | |
3583 | pending_mem = XEXP (pending_mem, 1); | |
3584 | } | |
3585 | ||
3586 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3587 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3588 | ||
3589 | /* Always add these dependencies to pending_reads, since | |
3590 | this insn may be followed by a write. */ | |
3591 | add_insn_mem_dependence (&pending_read_insns, &pending_read_mems, | |
3592 | insn, x); | |
3593 | ||
3594 | /* Take advantage of tail recursion here. */ | |
3595 | sched_analyze_2 (XEXP (x, 0), insn); | |
3596 | return; | |
3597 | } | |
3598 | ||
e0cd0770 JC |
3599 | /* Force pending stores to memory in case a trap handler needs them. */ |
3600 | case TRAP_IF: | |
3601 | flush_pending_lists (insn, 1); | |
3602 | break; | |
3603 | ||
8c660648 JL |
3604 | case ASM_OPERANDS: |
3605 | case ASM_INPUT: | |
3606 | case UNSPEC_VOLATILE: | |
8c660648 JL |
3607 | { |
3608 | rtx u; | |
3609 | ||
3610 | /* Traditional and volatile asm instructions must be considered to use | |
3611 | and clobber all hard registers, all pseudo-registers and all of | |
3612 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
3613 | ||
3614 | Consider for instance a volatile asm that changes the fpu rounding | |
3615 | mode. An insn should not be moved across this even if it only uses | |
3616 | pseudo-regs because it might give an incorrectly rounded result. */ | |
3617 | if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) | |
3618 | { | |
3619 | int max_reg = max_reg_num (); | |
3620 | for (i = 0; i < max_reg; i++) | |
3621 | { | |
3622 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3623 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3624 | reg_last_uses[i] = 0; | |
3625 | ||
3626 | /* reg_last_sets[r] is now a list of insns */ | |
3627 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) | |
3628 | add_dependence (insn, XEXP (u, 0), 0); | |
3629 | } | |
3630 | reg_pending_sets_all = 1; | |
3631 | ||
3632 | flush_pending_lists (insn, 0); | |
3633 | } | |
3634 | ||
3635 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
3636 | We can not just fall through here since then we would be confused | |
3637 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
3638 | traditional asms unlike their normal usage. */ | |
3639 | ||
3640 | if (code == ASM_OPERANDS) | |
3641 | { | |
3642 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
3643 | sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn); | |
3644 | return; | |
3645 | } | |
3646 | break; | |
3647 | } | |
3648 | ||
3649 | case PRE_DEC: | |
3650 | case POST_DEC: | |
3651 | case PRE_INC: | |
3652 | case POST_INC: | |
3653 | /* These both read and modify the result. We must handle them as writes | |
3654 | to get proper dependencies for following instructions. We must handle | |
3655 | them as reads to get proper dependencies from this to previous | |
3656 | instructions. Thus we need to pass them to both sched_analyze_1 | |
3657 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
3658 | to get the proper antecedent for the read. */ | |
3659 | sched_analyze_2 (XEXP (x, 0), insn); | |
3660 | sched_analyze_1 (x, insn); | |
3661 | return; | |
5835e573 KG |
3662 | |
3663 | default: | |
3664 | break; | |
8c660648 JL |
3665 | } |
3666 | ||
3667 | /* Other cases: walk the insn. */ | |
3668 | fmt = GET_RTX_FORMAT (code); | |
3669 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3670 | { | |
3671 | if (fmt[i] == 'e') | |
3672 | sched_analyze_2 (XEXP (x, i), insn); | |
3673 | else if (fmt[i] == 'E') | |
3674 | for (j = 0; j < XVECLEN (x, i); j++) | |
3675 | sched_analyze_2 (XVECEXP (x, i, j), insn); | |
3676 | } | |
3677 | } | |
3678 | ||
3679 | /* Analyze an INSN with pattern X to find all dependencies. */ | |
3680 | ||
3681 | static void | |
3682 | sched_analyze_insn (x, insn, loop_notes) | |
3683 | rtx x, insn; | |
3684 | rtx loop_notes; | |
3685 | { | |
3686 | register RTX_CODE code = GET_CODE (x); | |
3687 | rtx link; | |
3688 | int maxreg = max_reg_num (); | |
3689 | int i; | |
3690 | ||
3691 | if (code == SET || code == CLOBBER) | |
3692 | sched_analyze_1 (x, insn); | |
3693 | else if (code == PARALLEL) | |
3694 | { | |
3695 | register int i; | |
3696 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
3697 | { | |
3698 | code = GET_CODE (XVECEXP (x, 0, i)); | |
3699 | if (code == SET || code == CLOBBER) | |
3700 | sched_analyze_1 (XVECEXP (x, 0, i), insn); | |
3701 | else | |
3702 | sched_analyze_2 (XVECEXP (x, 0, i), insn); | |
3703 | } | |
3704 | } | |
3705 | else | |
3706 | sched_analyze_2 (x, insn); | |
3707 | ||
3708 | /* Mark registers CLOBBERED or used by called function. */ | |
3709 | if (GET_CODE (insn) == CALL_INSN) | |
3710 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
3711 | { | |
3712 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
3713 | sched_analyze_1 (XEXP (link, 0), insn); | |
3714 | else | |
3715 | sched_analyze_2 (XEXP (link, 0), insn); | |
3716 | } | |
3717 | ||
1f1ed00c JL |
3718 | /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic |
3719 | block, then we must be sure that no instructions are scheduled across it. | |
8c660648 JL |
3720 | Otherwise, the reg_n_refs info (which depends on loop_depth) would |
3721 | become incorrect. */ | |
3722 | ||
3723 | if (loop_notes) | |
3724 | { | |
3725 | int max_reg = max_reg_num (); | |
1f1ed00c | 3726 | int schedule_barrier_found = 0; |
8c660648 JL |
3727 | rtx link; |
3728 | ||
1f1ed00c JL |
3729 | /* Update loop_notes with any notes from this insn. Also determine |
3730 | if any of the notes on the list correspond to instruction scheduling | |
3731 | barriers (loop, eh & setjmp notes, but not range notes. */ | |
8c660648 JL |
3732 | link = loop_notes; |
3733 | while (XEXP (link, 1)) | |
1f1ed00c | 3734 | { |
54c3cf4b JL |
3735 | if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG |
3736 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END | |
3737 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG | |
3738 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END | |
3739 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP) | |
1f1ed00c JL |
3740 | schedule_barrier_found = 1; |
3741 | ||
3742 | link = XEXP (link, 1); | |
3743 | } | |
8c660648 JL |
3744 | XEXP (link, 1) = REG_NOTES (insn); |
3745 | REG_NOTES (insn) = loop_notes; | |
1f1ed00c JL |
3746 | |
3747 | /* Add dependencies if a scheduling barrier was found. */ | |
3748 | if (schedule_barrier_found) | |
3749 | { | |
3750 | for (i = 0; i < max_reg; i++) | |
3751 | { | |
3752 | rtx u; | |
3753 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3754 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3755 | reg_last_uses[i] = 0; | |
3756 | ||
3757 | /* reg_last_sets[r] is now a list of insns */ | |
3758 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) | |
3759 | add_dependence (insn, XEXP (u, 0), 0); | |
3760 | } | |
3761 | reg_pending_sets_all = 1; | |
3762 | ||
3763 | flush_pending_lists (insn, 0); | |
3764 | } | |
3765 | ||
8c660648 JL |
3766 | } |
3767 | ||
8c660648 JL |
3768 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, |
3769 | { | |
3770 | /* reg_last_sets[r] is now a list of insns */ | |
ebb7b10b | 3771 | free_list (®_last_sets[i], &unused_insn_list); |
8c660648 | 3772 | reg_last_sets[i] |
ebb7b10b | 3773 | = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3774 | }); |
3775 | CLEAR_REG_SET (reg_pending_sets); | |
3776 | ||
3777 | if (reg_pending_sets_all) | |
3778 | { | |
3779 | for (i = 0; i < maxreg; i++) | |
ebb7b10b RH |
3780 | { |
3781 | /* reg_last_sets[r] is now a list of insns */ | |
3782 | free_list (®_last_sets[i], &unused_insn_list); | |
3783 | reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); | |
3784 | } | |
8c660648 JL |
3785 | |
3786 | reg_pending_sets_all = 0; | |
3787 | } | |
3788 | ||
3789 | /* Handle function calls and function returns created by the epilogue | |
3790 | threading code. */ | |
3791 | if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
3792 | { | |
3793 | rtx dep_insn; | |
3794 | rtx prev_dep_insn; | |
3795 | ||
3796 | /* When scheduling instructions, we make sure calls don't lose their | |
3797 | accompanying USE insns by depending them one on another in order. | |
3798 | ||
3799 | Also, we must do the same thing for returns created by the epilogue | |
3800 | threading code. Note this code works only in this special case, | |
3801 | because other passes make no guarantee that they will never emit | |
3802 | an instruction between a USE and a RETURN. There is such a guarantee | |
3803 | for USE instructions immediately before a call. */ | |
3804 | ||
3805 | prev_dep_insn = insn; | |
3806 | dep_insn = PREV_INSN (insn); | |
3807 | while (GET_CODE (dep_insn) == INSN | |
3808 | && GET_CODE (PATTERN (dep_insn)) == USE | |
3809 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG) | |
3810 | { | |
3811 | SCHED_GROUP_P (prev_dep_insn) = 1; | |
3812 | ||
3813 | /* Make a copy of all dependencies on dep_insn, and add to insn. | |
3814 | This is so that all of the dependencies will apply to the | |
3815 | group. */ | |
3816 | ||
3817 | for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1)) | |
3818 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3819 | ||
3820 | prev_dep_insn = dep_insn; | |
3821 | dep_insn = PREV_INSN (dep_insn); | |
3822 | } | |
3823 | } | |
3824 | } | |
3825 | ||
3826 | /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS | |
3827 | for every dependency. */ | |
3828 | ||
3829 | static void | |
3830 | sched_analyze (head, tail) | |
3831 | rtx head, tail; | |
3832 | { | |
3833 | register rtx insn; | |
3834 | register rtx u; | |
3835 | rtx loop_notes = 0; | |
3836 | ||
3837 | for (insn = head;; insn = NEXT_INSN (insn)) | |
3838 | { | |
3839 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
3840 | { | |
062ae7ed JL |
3841 | /* Make each JUMP_INSN a scheduling barrier for memory references. */ |
3842 | if (GET_CODE (insn) == JUMP_INSN) | |
3843 | last_pending_memory_flush | |
3844 | = alloc_INSN_LIST (insn, last_pending_memory_flush); | |
8c660648 JL |
3845 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); |
3846 | loop_notes = 0; | |
3847 | } | |
3848 | else if (GET_CODE (insn) == CALL_INSN) | |
3849 | { | |
3850 | rtx x; | |
3851 | register int i; | |
3852 | ||
3853 | CANT_MOVE (insn) = 1; | |
3854 | ||
3855 | /* Any instruction using a hard register which may get clobbered | |
3856 | by a call needs to be marked as dependent on this call. | |
3857 | This prevents a use of a hard return reg from being moved | |
3858 | past a void call (i.e. it does not explicitly set the hard | |
3859 | return reg). */ | |
3860 | ||
3861 | /* If this call is followed by a NOTE_INSN_SETJMP, then assume that | |
3862 | all registers, not just hard registers, may be clobbered by this | |
3863 | call. */ | |
3864 | ||
3865 | /* Insn, being a CALL_INSN, magically depends on | |
3866 | `last_function_call' already. */ | |
3867 | ||
3868 | if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE | |
3869 | && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP) | |
3870 | { | |
3871 | int max_reg = max_reg_num (); | |
3872 | for (i = 0; i < max_reg; i++) | |
3873 | { | |
3874 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3875 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3876 | ||
3877 | reg_last_uses[i] = 0; | |
3878 | ||
3879 | /* reg_last_sets[r] is now a list of insns */ | |
3880 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) | |
3881 | add_dependence (insn, XEXP (u, 0), 0); | |
3882 | } | |
3883 | reg_pending_sets_all = 1; | |
3884 | ||
3885 | /* Add a pair of fake REG_NOTE which we will later | |
3886 | convert back into a NOTE_INSN_SETJMP note. See | |
3887 | reemit_notes for why we use a pair of NOTEs. */ | |
ebb7b10b RH |
3888 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD, |
3889 | GEN_INT (0), | |
3890 | REG_NOTES (insn)); | |
3891 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD, | |
3892 | GEN_INT (NOTE_INSN_SETJMP), | |
3893 | REG_NOTES (insn)); | |
8c660648 JL |
3894 | } |
3895 | else | |
3896 | { | |
3897 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3898 | if (call_used_regs[i] || global_regs[i]) | |
3899 | { | |
3900 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3901 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3902 | reg_last_uses[i] = 0; | |
3903 | ||
3904 | /* reg_last_sets[r] is now a list of insns */ | |
3905 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) | |
3906 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3907 | ||
3908 | SET_REGNO_REG_SET (reg_pending_sets, i); | |
3909 | } | |
3910 | } | |
3911 | ||
3912 | /* For each insn which shouldn't cross a call, add a dependence | |
3913 | between that insn and this call insn. */ | |
3914 | x = LOG_LINKS (sched_before_next_call); | |
3915 | while (x) | |
3916 | { | |
3917 | add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); | |
3918 | x = XEXP (x, 1); | |
3919 | } | |
3920 | LOG_LINKS (sched_before_next_call) = 0; | |
3921 | ||
3922 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); | |
3923 | loop_notes = 0; | |
3924 | ||
3925 | /* In the absence of interprocedural alias analysis, we must flush | |
3926 | all pending reads and writes, and start new dependencies starting | |
3927 | from here. But only flush writes for constant calls (which may | |
3928 | be passed a pointer to something we haven't written yet). */ | |
3929 | flush_pending_lists (insn, CONST_CALL_P (insn)); | |
3930 | ||
3931 | /* Depend this function call (actually, the user of this | |
3932 | function call) on all hard register clobberage. */ | |
3933 | ||
3934 | /* last_function_call is now a list of insns */ | |
ebb7b10b RH |
3935 | free_list(&last_function_call, &unused_insn_list); |
3936 | last_function_call = alloc_INSN_LIST (insn, NULL_RTX); | |
8c660648 JL |
3937 | } |
3938 | ||
3939 | /* See comments on reemit_notes as to why we do this. */ | |
6dfdecdb RH |
3940 | /* ??? Actually, the reemit_notes just say what is done, not why. */ |
3941 | ||
3942 | else if (GET_CODE (insn) == NOTE | |
3943 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START | |
3944 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END)) | |
3945 | { | |
3946 | loop_notes = alloc_EXPR_LIST (REG_DEAD, NOTE_RANGE_INFO (insn), | |
3947 | loop_notes); | |
3948 | loop_notes = alloc_EXPR_LIST (REG_DEAD, | |
3949 | GEN_INT (NOTE_LINE_NUMBER (insn)), | |
3950 | loop_notes); | |
3951 | } | |
8c660648 JL |
3952 | else if (GET_CODE (insn) == NOTE |
3953 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG | |
3954 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END | |
3955 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG | |
3956 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END | |
3957 | || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP | |
3958 | && GET_CODE (PREV_INSN (insn)) != CALL_INSN))) | |
3959 | { | |
ebb7b10b RH |
3960 | loop_notes = alloc_EXPR_LIST (REG_DEAD, |
3961 | GEN_INT (NOTE_BLOCK_NUMBER (insn)), | |
3962 | loop_notes); | |
3963 | loop_notes = alloc_EXPR_LIST (REG_DEAD, | |
3964 | GEN_INT (NOTE_LINE_NUMBER (insn)), | |
3965 | loop_notes); | |
8c660648 JL |
3966 | CONST_CALL_P (loop_notes) = CONST_CALL_P (insn); |
3967 | } | |
3968 | ||
3969 | if (insn == tail) | |
3970 | return; | |
3971 | } | |
3972 | abort (); | |
3973 | } | |
3974 | \f | |
3975 | /* Called when we see a set of a register. If death is true, then we are | |
3976 | scanning backwards. Mark that register as unborn. If nobody says | |
3977 | otherwise, that is how things will remain. If death is false, then we | |
3978 | are scanning forwards. Mark that register as being born. */ | |
3979 | ||
3980 | static void | |
5835e573 | 3981 | sched_note_set (x, death) |
8c660648 JL |
3982 | rtx x; |
3983 | int death; | |
3984 | { | |
3985 | register int regno; | |
3986 | register rtx reg = SET_DEST (x); | |
3987 | int subreg_p = 0; | |
3988 | ||
3989 | if (reg == 0) | |
3990 | return; | |
3991 | ||
c0222c21 DM |
3992 | if (GET_CODE (reg) == PARALLEL |
3993 | && GET_MODE (reg) == BLKmode) | |
3994 | { | |
3995 | register int i; | |
3996 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
3997 | sched_note_set (XVECEXP (reg, 0, i), death); | |
3998 | return; | |
3999 | } | |
4000 | ||
8c660648 JL |
4001 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART |
4002 | || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT) | |
4003 | { | |
4004 | /* Must treat modification of just one hardware register of a multi-reg | |
4005 | value or just a byte field of a register exactly the same way that | |
4006 | mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg | |
4007 | does not kill the entire register. */ | |
4008 | if (GET_CODE (reg) != SUBREG | |
4009 | || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg)) | |
4010 | subreg_p = 1; | |
4011 | ||
4012 | reg = SUBREG_REG (reg); | |
4013 | } | |
4014 | ||
4015 | if (GET_CODE (reg) != REG) | |
4016 | return; | |
4017 | ||
4018 | /* Global registers are always live, so the code below does not apply | |
4019 | to them. */ | |
4020 | ||
4021 | regno = REGNO (reg); | |
4022 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
4023 | { | |
4024 | if (death) | |
4025 | { | |
4026 | /* If we only set part of the register, then this set does not | |
4027 | kill it. */ | |
4028 | if (subreg_p) | |
4029 | return; | |
4030 | ||
4031 | /* Try killing this register. */ | |
4032 | if (regno < FIRST_PSEUDO_REGISTER) | |
4033 | { | |
4034 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
4035 | while (--j >= 0) | |
4036 | { | |
4037 | CLEAR_REGNO_REG_SET (bb_live_regs, regno + j); | |
4038 | } | |
4039 | } | |
4040 | else | |
4041 | { | |
4042 | /* Recompute REG_BASIC_BLOCK as we update all the other | |
4043 | dataflow information. */ | |
4044 | if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN) | |
4045 | sched_reg_basic_block[regno] = current_block_num; | |
4046 | else if (sched_reg_basic_block[regno] != current_block_num) | |
4047 | sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL; | |
4048 | ||
4049 | CLEAR_REGNO_REG_SET (bb_live_regs, regno); | |
4050 | } | |
4051 | } | |
4052 | else | |
4053 | { | |
4054 | /* Make the register live again. */ | |
4055 | if (regno < FIRST_PSEUDO_REGISTER) | |
4056 | { | |
4057 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
4058 | while (--j >= 0) | |
4059 | { | |
4060 | SET_REGNO_REG_SET (bb_live_regs, regno + j); | |
4061 | } | |
4062 | } | |
4063 | else | |
4064 | { | |
4065 | SET_REGNO_REG_SET (bb_live_regs, regno); | |
4066 | } | |
4067 | } | |
4068 | } | |
4069 | } | |
4070 | \f | |
4071 | /* Macros and functions for keeping the priority queue sorted, and | |
4072 | dealing with queueing and dequeueing of instructions. */ | |
4073 | ||
4074 | #define SCHED_SORT(READY, N_READY) \ | |
4075 | do { if ((N_READY) == 2) \ | |
4076 | swap_sort (READY, N_READY); \ | |
4077 | else if ((N_READY) > 2) \ | |
4078 | qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ | |
4079 | while (0) | |
4080 | ||
4081 | /* Returns a positive value if x is preferred; returns a negative value if | |
4082 | y is preferred. Should never return 0, since that will make the sort | |
4083 | unstable. */ | |
4084 | ||
4085 | static int | |
4086 | rank_for_schedule (x, y) | |
01c7f350 MM |
4087 | const GENERIC_PTR x; |
4088 | const GENERIC_PTR y; | |
8c660648 | 4089 | { |
01c7f350 MM |
4090 | rtx tmp = *(rtx *)y; |
4091 | rtx tmp2 = *(rtx *)x; | |
8c660648 | 4092 | rtx link; |
2db45993 | 4093 | int tmp_class, tmp2_class, depend_count1, depend_count2; |
8c660648 JL |
4094 | int val, priority_val, spec_val, prob_val, weight_val; |
4095 | ||
4096 | ||
8c660648 JL |
4097 | /* prefer insn with higher priority */ |
4098 | priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp); | |
4099 | if (priority_val) | |
4100 | return priority_val; | |
4101 | ||
4102 | /* prefer an insn with smaller contribution to registers-pressure */ | |
4103 | if (!reload_completed && | |
4104 | (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2))) | |
4105 | return (weight_val); | |
4106 | ||
4107 | /* some comparison make sense in interblock scheduling only */ | |
4108 | if (INSN_BB (tmp) != INSN_BB (tmp2)) | |
4109 | { | |
4110 | /* prefer an inblock motion on an interblock motion */ | |
4111 | if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb)) | |
4112 | return 1; | |
4113 | if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb)) | |
4114 | return -1; | |
4115 | ||
4116 | /* prefer a useful motion on a speculative one */ | |
4117 | if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2))) | |
4118 | return (spec_val); | |
4119 | ||
4120 | /* prefer a more probable (speculative) insn */ | |
4121 | prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp); | |
4122 | if (prob_val) | |
4123 | return (prob_val); | |
4124 | } | |
4125 | ||
4126 | /* compare insns based on their relation to the last-scheduled-insn */ | |
4127 | if (last_scheduled_insn) | |
4128 | { | |
4129 | /* Classify the instructions into three classes: | |
4130 | 1) Data dependent on last schedule insn. | |
4131 | 2) Anti/Output dependent on last scheduled insn. | |
4132 | 3) Independent of last scheduled insn, or has latency of one. | |
4133 | Choose the insn from the highest numbered class if different. */ | |
4134 | link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn)); | |
4135 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1) | |
4136 | tmp_class = 3; | |
4137 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4138 | tmp_class = 1; | |
4139 | else | |
4140 | tmp_class = 2; | |
4141 | ||
4142 | link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn)); | |
4143 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1) | |
4144 | tmp2_class = 3; | |
4145 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4146 | tmp2_class = 1; | |
4147 | else | |
4148 | tmp2_class = 2; | |
4149 | ||
4150 | if ((val = tmp2_class - tmp_class)) | |
4151 | return val; | |
4152 | } | |
4153 | ||
2db45993 JL |
4154 | /* Prefer the insn which has more later insns that depend on it. |
4155 | This gives the scheduler more freedom when scheduling later | |
4156 | instructions at the expense of added register pressure. */ | |
4157 | depend_count1 = 0; | |
4158 | for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1)) | |
4159 | depend_count1++; | |
4160 | ||
4161 | depend_count2 = 0; | |
4162 | for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1)) | |
4163 | depend_count2++; | |
4164 | ||
4165 | val = depend_count2 - depend_count1; | |
4166 | if (val) | |
4167 | return val; | |
4168 | ||
8c660648 JL |
4169 | /* If insns are equally good, sort by INSN_LUID (original insn order), |
4170 | so that we make the sort stable. This minimizes instruction movement, | |
4171 | thus minimizing sched's effect on debugging and cross-jumping. */ | |
4172 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
4173 | } | |
4174 | ||
4175 | /* Resort the array A in which only element at index N may be out of order. */ | |
4176 | ||
cbb13457 | 4177 | HAIFA_INLINE static void |
8c660648 JL |
4178 | swap_sort (a, n) |
4179 | rtx *a; | |
4180 | int n; | |
4181 | { | |
4182 | rtx insn = a[n - 1]; | |
4183 | int i = n - 2; | |
4184 | ||
4185 | while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0) | |
4186 | { | |
4187 | a[i + 1] = a[i]; | |
4188 | i -= 1; | |
4189 | } | |
4190 | a[i + 1] = insn; | |
4191 | } | |
4192 | ||
4193 | static int max_priority; | |
4194 | ||
4195 | /* Add INSN to the insn queue so that it can be executed at least | |
4196 | N_CYCLES after the currently executing insn. Preserve insns | |
4197 | chain for debugging purposes. */ | |
4198 | ||
cbb13457 | 4199 | HAIFA_INLINE static void |
8c660648 JL |
4200 | queue_insn (insn, n_cycles) |
4201 | rtx insn; | |
4202 | int n_cycles; | |
4203 | { | |
4204 | int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); | |
ebb7b10b | 4205 | rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]); |
8c660648 JL |
4206 | insn_queue[next_q] = link; |
4207 | q_size += 1; | |
4208 | ||
4209 | if (sched_verbose >= 2) | |
4210 | { | |
4211 | fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn)); | |
4212 | ||
4213 | if (INSN_BB (insn) != target_bb) | |
4214 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
4215 | ||
4216 | fprintf (dump, "queued for %d cycles.\n", n_cycles); | |
4217 | } | |
4218 | ||
4219 | } | |
4220 | ||
4221 | /* Return nonzero if PAT is the pattern of an insn which makes a | |
4222 | register live. */ | |
4223 | ||
cbb13457 | 4224 | HAIFA_INLINE static int |
8c660648 JL |
4225 | birthing_insn_p (pat) |
4226 | rtx pat; | |
4227 | { | |
4228 | int j; | |
4229 | ||
4230 | if (reload_completed == 1) | |
4231 | return 0; | |
4232 | ||
4233 | if (GET_CODE (pat) == SET | |
c0222c21 DM |
4234 | && (GET_CODE (SET_DEST (pat)) == REG |
4235 | || (GET_CODE (SET_DEST (pat)) == PARALLEL | |
4236 | && GET_MODE (SET_DEST (pat)) == BLKmode))) | |
8c660648 JL |
4237 | { |
4238 | rtx dest = SET_DEST (pat); | |
c0222c21 | 4239 | int i; |
8c660648 JL |
4240 | |
4241 | /* It would be more accurate to use refers_to_regno_p or | |
c0222c21 DM |
4242 | reg_mentioned_p to determine when the dest is not live before this |
4243 | insn. */ | |
4244 | if (GET_CODE (dest) == REG) | |
4245 | { | |
4246 | i = REGNO (dest); | |
4247 | if (REGNO_REG_SET_P (bb_live_regs, i)) | |
4248 | return (REG_N_SETS (i) == 1); | |
4249 | } | |
4250 | else | |
4251 | { | |
4252 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
4253 | { | |
4254 | int regno = REGNO (SET_DEST (XVECEXP (dest, 0, i))); | |
4255 | if (REGNO_REG_SET_P (bb_live_regs, regno)) | |
4256 | return (REG_N_SETS (regno) == 1); | |
4257 | } | |
4258 | } | |
8c660648 JL |
4259 | return 0; |
4260 | } | |
4261 | if (GET_CODE (pat) == PARALLEL) | |
4262 | { | |
4263 | for (j = 0; j < XVECLEN (pat, 0); j++) | |
4264 | if (birthing_insn_p (XVECEXP (pat, 0, j))) | |
4265 | return 1; | |
4266 | } | |
4267 | return 0; | |
4268 | } | |
4269 | ||
4270 | /* PREV is an insn that is ready to execute. Adjust its priority if that | |
4271 | will help shorten register lifetimes. */ | |
4272 | ||
cbb13457 | 4273 | HAIFA_INLINE static void |
8c660648 JL |
4274 | adjust_priority (prev) |
4275 | rtx prev; | |
4276 | { | |
4277 | /* Trying to shorten register lives after reload has completed | |
4278 | is useless and wrong. It gives inaccurate schedules. */ | |
4279 | if (reload_completed == 0) | |
4280 | { | |
4281 | rtx note; | |
4282 | int n_deaths = 0; | |
4283 | ||
4284 | /* ??? This code has no effect, because REG_DEAD notes are removed | |
4285 | before we ever get here. */ | |
4286 | for (note = REG_NOTES (prev); note; note = XEXP (note, 1)) | |
4287 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
4288 | n_deaths += 1; | |
4289 | ||
4290 | /* Defer scheduling insns which kill registers, since that | |
4291 | shortens register lives. Prefer scheduling insns which | |
4292 | make registers live for the same reason. */ | |
4293 | switch (n_deaths) | |
4294 | { | |
4295 | default: | |
4296 | INSN_PRIORITY (prev) >>= 3; | |
4297 | break; | |
4298 | case 3: | |
4299 | INSN_PRIORITY (prev) >>= 2; | |
4300 | break; | |
4301 | case 2: | |
4302 | case 1: | |
4303 | INSN_PRIORITY (prev) >>= 1; | |
4304 | break; | |
4305 | case 0: | |
4306 | if (birthing_insn_p (PATTERN (prev))) | |
4307 | { | |
4308 | int max = max_priority; | |
4309 | ||
4310 | if (max > INSN_PRIORITY (prev)) | |
4311 | INSN_PRIORITY (prev) = max; | |
4312 | } | |
4313 | break; | |
4314 | } | |
4315 | #ifdef ADJUST_PRIORITY | |
4316 | ADJUST_PRIORITY (prev); | |
4317 | #endif | |
4318 | } | |
4319 | } | |
4320 | ||
4bdc8810 RH |
4321 | /* Clock at which the previous instruction was issued. */ |
4322 | static int last_clock_var; | |
4323 | ||
8c660648 JL |
4324 | /* INSN is the "currently executing insn". Launch each insn which was |
4325 | waiting on INSN. READY is a vector of insns which are ready to fire. | |
4326 | N_READY is the number of elements in READY. CLOCK is the current | |
4327 | cycle. */ | |
4328 | ||
4329 | static int | |
4330 | schedule_insn (insn, ready, n_ready, clock) | |
4331 | rtx insn; | |
4332 | rtx *ready; | |
4333 | int n_ready; | |
4334 | int clock; | |
4335 | { | |
4336 | rtx link; | |
4337 | int unit; | |
4338 | ||
4339 | unit = insn_unit (insn); | |
4340 | ||
4341 | if (sched_verbose >= 2) | |
4342 | { | |
4343 | fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", INSN_UID (insn)); | |
4344 | insn_print_units (insn); | |
4345 | fprintf (dump, "\n"); | |
4346 | } | |
4347 | ||
4348 | if (sched_verbose && unit == -1) | |
4349 | visualize_no_unit (insn); | |
4350 | ||
4351 | if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose) | |
4352 | schedule_unit (unit, insn, clock); | |
4353 | ||
4354 | if (INSN_DEPEND (insn) == 0) | |
4355 | return n_ready; | |
4356 | ||
4357 | /* This is used by the function adjust_priority above. */ | |
4358 | if (n_ready > 0) | |
4359 | max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); | |
4360 | else | |
4361 | max_priority = INSN_PRIORITY (insn); | |
4362 | ||
4363 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
4364 | { | |
4365 | rtx next = XEXP (link, 0); | |
4366 | int cost = insn_cost (insn, link, next); | |
4367 | ||
4368 | INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost); | |
4369 | ||
4370 | if ((INSN_DEP_COUNT (next) -= 1) == 0) | |
4371 | { | |
4372 | int effective_cost = INSN_TICK (next) - clock; | |
4373 | ||
4374 | /* For speculative insns, before inserting to ready/queue, | |
4375 | check live, exception-free, and issue-delay */ | |
4376 | if (INSN_BB (next) != target_bb | |
4377 | && (!IS_VALID (INSN_BB (next)) | |
4378 | || CANT_MOVE (next) | |
4379 | || (IS_SPECULATIVE_INSN (next) | |
4380 | && (insn_issue_delay (next) > 3 | |
5835e573 | 4381 | || !check_live (next, INSN_BB (next)) |
8c660648 JL |
4382 | || !is_exception_free (next, INSN_BB (next), target_bb))))) |
4383 | continue; | |
4384 | ||
4385 | if (sched_verbose >= 2) | |
4386 | { | |
4387 | fprintf (dump, ";;\t\tdependences resolved: insn %d ", INSN_UID (next)); | |
4388 | ||
4389 | if (current_nr_blocks > 1 && INSN_BB (next) != target_bb) | |
4390 | fprintf (dump, "/b%d ", INSN_BLOCK (next)); | |
4391 | ||
4392 | if (effective_cost <= 1) | |
4393 | fprintf (dump, "into ready\n"); | |
4394 | else | |
4395 | fprintf (dump, "into queue with cost=%d\n", effective_cost); | |
4396 | } | |
4397 | ||
4398 | /* Adjust the priority of NEXT and either put it on the ready | |
4399 | list or queue it. */ | |
4400 | adjust_priority (next); | |
4401 | if (effective_cost <= 1) | |
4402 | ready[n_ready++] = next; | |
4403 | else | |
4404 | queue_insn (next, effective_cost); | |
4405 | } | |
4406 | } | |
4407 | ||
4bdc8810 RH |
4408 | /* Annotate the instruction with issue information -- TImode |
4409 | indicates that the instruction is expected not to be able | |
4410 | to issue on the same cycle as the previous insn. A machine | |
4411 | may use this information to decide how the instruction should | |
4412 | be aligned. */ | |
4413 | if (reload_completed && issue_rate > 1) | |
4414 | { | |
4415 | PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode); | |
4416 | last_clock_var = clock; | |
4417 | } | |
4418 | ||
8c660648 JL |
4419 | return n_ready; |
4420 | } | |
4421 | ||
4422 | ||
4423 | /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the | |
4424 | dead_notes list. */ | |
4425 | ||
4426 | static void | |
4427 | create_reg_dead_note (reg, insn) | |
4428 | rtx reg, insn; | |
4429 | { | |
4430 | rtx link; | |
4431 | ||
4432 | /* The number of registers killed after scheduling must be the same as the | |
4433 | number of registers killed before scheduling. The number of REG_DEAD | |
4434 | notes may not be conserved, i.e. two SImode hard register REG_DEAD notes | |
4435 | might become one DImode hard register REG_DEAD note, but the number of | |
4436 | registers killed will be conserved. | |
4437 | ||
4438 | We carefully remove REG_DEAD notes from the dead_notes list, so that | |
4439 | there will be none left at the end. If we run out early, then there | |
4440 | is a bug somewhere in flow, combine and/or sched. */ | |
4441 | ||
4442 | if (dead_notes == 0) | |
4443 | { | |
4444 | if (current_nr_blocks <= 1) | |
4445 | abort (); | |
4446 | else | |
ebb7b10b | 4447 | link = alloc_EXPR_LIST (REG_DEAD, NULL_RTX, NULL_RTX); |
8c660648 JL |
4448 | } |
4449 | else | |
4450 | { | |
4451 | /* Number of regs killed by REG. */ | |
4452 | int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1 | |
4453 | : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg))); | |
4454 | /* Number of regs killed by REG_DEAD notes taken off the list. */ | |
4455 | int reg_note_regs; | |
4456 | ||
4457 | link = dead_notes; | |
4458 | reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 | |
4459 | : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), | |
4460 | GET_MODE (XEXP (link, 0)))); | |
4461 | while (reg_note_regs < regs_killed) | |
4462 | { | |
4463 | link = XEXP (link, 1); | |
04029ca2 JL |
4464 | |
4465 | /* LINK might be zero if we killed more registers after scheduling | |
4466 | than before, and the last hard register we kill is actually | |
4467 | multiple hard regs. | |
4468 | ||
4469 | This is normal for interblock scheduling, so deal with it in | |
4470 | that case, else abort. */ | |
4471 | if (link == NULL_RTX && current_nr_blocks <= 1) | |
4472 | abort (); | |
4473 | else if (link == NULL_RTX) | |
ebb7b10b RH |
4474 | link = alloc_EXPR_LIST (REG_DEAD, gen_rtx_REG (word_mode, 0), |
4475 | NULL_RTX); | |
04029ca2 | 4476 | |
8c660648 JL |
4477 | reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 |
4478 | : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), | |
4479 | GET_MODE (XEXP (link, 0)))); | |
4480 | } | |
4481 | dead_notes = XEXP (link, 1); | |
4482 | ||
4483 | /* If we took too many regs kills off, put the extra ones back. */ | |
4484 | while (reg_note_regs > regs_killed) | |
4485 | { | |
4486 | rtx temp_reg, temp_link; | |
4487 | ||
38a448ca | 4488 | temp_reg = gen_rtx_REG (word_mode, 0); |
ebb7b10b | 4489 | temp_link = alloc_EXPR_LIST (REG_DEAD, temp_reg, dead_notes); |
8c660648 JL |
4490 | dead_notes = temp_link; |
4491 | reg_note_regs--; | |
4492 | } | |
4493 | } | |
4494 | ||
4495 | XEXP (link, 0) = reg; | |
4496 | XEXP (link, 1) = REG_NOTES (insn); | |
4497 | REG_NOTES (insn) = link; | |
4498 | } | |
4499 | ||
4500 | /* Subroutine on attach_deaths_insn--handles the recursive search | |
4501 | through INSN. If SET_P is true, then x is being modified by the insn. */ | |
4502 | ||
4503 | static void | |
4504 | attach_deaths (x, insn, set_p) | |
4505 | rtx x; | |
4506 | rtx insn; | |
4507 | int set_p; | |
4508 | { | |
4509 | register int i; | |
4510 | register int j; | |
4511 | register enum rtx_code code; | |
4512 | register char *fmt; | |
4513 | ||
4514 | if (x == 0) | |
4515 | return; | |
4516 | ||
4517 | code = GET_CODE (x); | |
4518 | ||
4519 | switch (code) | |
4520 | { | |
4521 | case CONST_INT: | |
4522 | case CONST_DOUBLE: | |
4523 | case LABEL_REF: | |
4524 | case SYMBOL_REF: | |
4525 | case CONST: | |
4526 | case CODE_LABEL: | |
4527 | case PC: | |
4528 | case CC0: | |
4529 | /* Get rid of the easy cases first. */ | |
4530 | return; | |
4531 | ||
4532 | case REG: | |
4533 | { | |
4534 | /* If the register dies in this insn, queue that note, and mark | |
4535 | this register as needing to die. */ | |
4536 | /* This code is very similar to mark_used_1 (if set_p is false) | |
4537 | and mark_set_1 (if set_p is true) in flow.c. */ | |
4538 | ||
4539 | register int regno; | |
4540 | int some_needed; | |
4541 | int all_needed; | |
4542 | ||
4543 | if (set_p) | |
4544 | return; | |
4545 | ||
4546 | regno = REGNO (x); | |
4547 | all_needed = some_needed = REGNO_REG_SET_P (old_live_regs, regno); | |
4548 | if (regno < FIRST_PSEUDO_REGISTER) | |
4549 | { | |
4550 | int n; | |
4551 | ||
4552 | n = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4553 | while (--n > 0) | |
4554 | { | |
4555 | int needed = (REGNO_REG_SET_P (old_live_regs, regno + n)); | |
4556 | some_needed |= needed; | |
4557 | all_needed &= needed; | |
4558 | } | |
4559 | } | |
4560 | ||
4561 | /* If it wasn't live before we started, then add a REG_DEAD note. | |
4562 | We must check the previous lifetime info not the current info, | |
4563 | because we may have to execute this code several times, e.g. | |
4564 | once for a clobber (which doesn't add a note) and later | |
4565 | for a use (which does add a note). | |
4566 | ||
4567 | Always make the register live. We must do this even if it was | |
4568 | live before, because this may be an insn which sets and uses | |
4569 | the same register, in which case the register has already been | |
4570 | killed, so we must make it live again. | |
4571 | ||
4572 | Global registers are always live, and should never have a REG_DEAD | |
4573 | note added for them, so none of the code below applies to them. */ | |
4574 | ||
4575 | if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno]) | |
4576 | { | |
4577 | /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the | |
4578 | STACK_POINTER_REGNUM, since these are always considered to be | |
4579 | live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ | |
4580 | if (regno != FRAME_POINTER_REGNUM | |
4581 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
4582 | && ! (regno == HARD_FRAME_POINTER_REGNUM) | |
4583 | #endif | |
4584 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
4585 | && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
4586 | #endif | |
4587 | && regno != STACK_POINTER_REGNUM) | |
4588 | { | |
d6df9efb | 4589 | if (! all_needed && ! dead_or_set_p (insn, x)) |
8c660648 JL |
4590 | { |
4591 | /* Check for the case where the register dying partially | |
4592 | overlaps the register set by this insn. */ | |
4593 | if (regno < FIRST_PSEUDO_REGISTER | |
4594 | && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) | |
4595 | { | |
4596 | int n = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4597 | while (--n >= 0) | |
4598 | some_needed |= dead_or_set_regno_p (insn, regno + n); | |
4599 | } | |
4600 | ||
4601 | /* If none of the words in X is needed, make a REG_DEAD | |
4602 | note. Otherwise, we must make partial REG_DEAD | |
4603 | notes. */ | |
4604 | if (! some_needed) | |
4605 | create_reg_dead_note (x, insn); | |
4606 | else | |
4607 | { | |
4608 | int i; | |
4609 | ||
4610 | /* Don't make a REG_DEAD note for a part of a | |
4611 | register that is set in the insn. */ | |
4612 | for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; | |
4613 | i >= 0; i--) | |
4614 | if (! REGNO_REG_SET_P (old_live_regs, regno+i) | |
4615 | && ! dead_or_set_regno_p (insn, regno + i)) | |
38a448ca RH |
4616 | create_reg_dead_note (gen_rtx_REG (reg_raw_mode[regno + i], |
4617 | regno + i), | |
8c660648 JL |
4618 | insn); |
4619 | } | |
4620 | } | |
4621 | } | |
4622 | ||
4623 | if (regno < FIRST_PSEUDO_REGISTER) | |
4624 | { | |
4625 | int j = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4626 | while (--j >= 0) | |
4627 | { | |
4628 | SET_REGNO_REG_SET (bb_live_regs, regno + j); | |
4629 | } | |
4630 | } | |
4631 | else | |
4632 | { | |
4633 | /* Recompute REG_BASIC_BLOCK as we update all the other | |
4634 | dataflow information. */ | |
4635 | if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN) | |
4636 | sched_reg_basic_block[regno] = current_block_num; | |
4637 | else if (sched_reg_basic_block[regno] != current_block_num) | |
4638 | sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL; | |
4639 | ||
4640 | SET_REGNO_REG_SET (bb_live_regs, regno); | |
4641 | } | |
4642 | } | |
4643 | return; | |
4644 | } | |
4645 | ||
4646 | case MEM: | |
4647 | /* Handle tail-recursive case. */ | |
4648 | attach_deaths (XEXP (x, 0), insn, 0); | |
4649 | return; | |
4650 | ||
4651 | case SUBREG: | |
d6df9efb JL |
4652 | attach_deaths (SUBREG_REG (x), insn, |
4653 | set_p && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
4654 | <= UNITS_PER_WORD) | |
4655 | || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
4656 | == GET_MODE_SIZE (GET_MODE ((x)))))); | |
4657 | return; | |
4658 | ||
8c660648 | 4659 | case STRICT_LOW_PART: |
d6df9efb | 4660 | attach_deaths (XEXP (x, 0), insn, 0); |
8c660648 JL |
4661 | return; |
4662 | ||
4663 | case ZERO_EXTRACT: | |
4664 | case SIGN_EXTRACT: | |
d6df9efb | 4665 | attach_deaths (XEXP (x, 0), insn, 0); |
8c660648 JL |
4666 | attach_deaths (XEXP (x, 1), insn, 0); |
4667 | attach_deaths (XEXP (x, 2), insn, 0); | |
4668 | return; | |
4669 | ||
c0222c21 DM |
4670 | case PARALLEL: |
4671 | if (set_p | |
4672 | && GET_MODE (x) == BLKmode) | |
4673 | { | |
4674 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4675 | attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); | |
4676 | return; | |
4677 | } | |
4678 | ||
4679 | /* fallthrough */ | |
8c660648 JL |
4680 | default: |
4681 | /* Other cases: walk the insn. */ | |
4682 | fmt = GET_RTX_FORMAT (code); | |
4683 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4684 | { | |
4685 | if (fmt[i] == 'e') | |
4686 | attach_deaths (XEXP (x, i), insn, 0); | |
4687 | else if (fmt[i] == 'E') | |
4688 | for (j = 0; j < XVECLEN (x, i); j++) | |
4689 | attach_deaths (XVECEXP (x, i, j), insn, 0); | |
4690 | } | |
4691 | } | |
4692 | } | |
4693 | ||
4694 | /* After INSN has executed, add register death notes for each register | |
4695 | that is dead after INSN. */ | |
4696 | ||
4697 | static void | |
4698 | attach_deaths_insn (insn) | |
4699 | rtx insn; | |
4700 | { | |
4701 | rtx x = PATTERN (insn); | |
4702 | register RTX_CODE code = GET_CODE (x); | |
4703 | rtx link; | |
4704 | ||
4705 | if (code == SET) | |
4706 | { | |
4707 | attach_deaths (SET_SRC (x), insn, 0); | |
4708 | ||
4709 | /* A register might die here even if it is the destination, e.g. | |
4710 | it is the target of a volatile read and is otherwise unused. | |
4711 | Hence we must always call attach_deaths for the SET_DEST. */ | |
4712 | attach_deaths (SET_DEST (x), insn, 1); | |
4713 | } | |
4714 | else if (code == PARALLEL) | |
4715 | { | |
4716 | register int i; | |
4717 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4718 | { | |
4719 | code = GET_CODE (XVECEXP (x, 0, i)); | |
4720 | if (code == SET) | |
4721 | { | |
4722 | attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0); | |
4723 | ||
4724 | attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); | |
4725 | } | |
4726 | /* Flow does not add REG_DEAD notes to registers that die in | |
4727 | clobbers, so we can't either. */ | |
4728 | else if (code != CLOBBER) | |
4729 | attach_deaths (XVECEXP (x, 0, i), insn, 0); | |
4730 | } | |
4731 | } | |
4732 | /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a | |
4733 | MEM being clobbered, just like flow. */ | |
4734 | else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM) | |
4735 | attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0); | |
4736 | /* Otherwise don't add a death note to things being clobbered. */ | |
4737 | else if (code != CLOBBER) | |
4738 | attach_deaths (x, insn, 0); | |
4739 | ||
4740 | /* Make death notes for things used in the called function. */ | |
4741 | if (GET_CODE (insn) == CALL_INSN) | |
4742 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
4743 | attach_deaths (XEXP (XEXP (link, 0), 0), insn, | |
4744 | GET_CODE (XEXP (link, 0)) == CLOBBER); | |
4745 | } | |
4746 | ||
4747 | /* functions for handlnig of notes */ | |
4748 | ||
4749 | /* Delete notes beginning with INSN and put them in the chain | |
4750 | of notes ended by NOTE_LIST. | |
4751 | Returns the insn following the notes. */ | |
4752 | ||
4753 | static rtx | |
4754 | unlink_other_notes (insn, tail) | |
4755 | rtx insn, tail; | |
4756 | { | |
4757 | rtx prev = PREV_INSN (insn); | |
4758 | ||
4759 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4760 | { | |
4761 | rtx next = NEXT_INSN (insn); | |
4762 | /* Delete the note from its current position. */ | |
4763 | if (prev) | |
4764 | NEXT_INSN (prev) = next; | |
4765 | if (next) | |
4766 | PREV_INSN (next) = prev; | |
4767 | ||
4768 | /* Don't save away NOTE_INSN_SETJMPs, because they must remain | |
4769 | immediately after the call they follow. We use a fake | |
4770 | (REG_DEAD (const_int -1)) note to remember them. | |
4771 | Likewise with NOTE_INSN_{LOOP,EHREGION}_{BEG, END}. */ | |
4772 | if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP | |
4773 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG | |
4774 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END | |
0dfa1860 MM |
4775 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START |
4776 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END | |
8c660648 JL |
4777 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG |
4778 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END) | |
4779 | { | |
4780 | /* Insert the note at the end of the notes list. */ | |
4781 | PREV_INSN (insn) = note_list; | |
4782 | if (note_list) | |
4783 | NEXT_INSN (note_list) = insn; | |
4784 | note_list = insn; | |
4785 | } | |
4786 | ||
4787 | insn = next; | |
4788 | } | |
4789 | return insn; | |
4790 | } | |
4791 | ||
4792 | /* Delete line notes beginning with INSN. Record line-number notes so | |
4793 | they can be reused. Returns the insn following the notes. */ | |
4794 | ||
4795 | static rtx | |
4796 | unlink_line_notes (insn, tail) | |
4797 | rtx insn, tail; | |
4798 | { | |
4799 | rtx prev = PREV_INSN (insn); | |
4800 | ||
4801 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4802 | { | |
4803 | rtx next = NEXT_INSN (insn); | |
4804 | ||
4805 | if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) | |
4806 | { | |
4807 | /* Delete the note from its current position. */ | |
4808 | if (prev) | |
4809 | NEXT_INSN (prev) = next; | |
4810 | if (next) | |
4811 | PREV_INSN (next) = prev; | |
4812 | ||
4813 | /* Record line-number notes so they can be reused. */ | |
4814 | LINE_NOTE (insn) = insn; | |
4815 | } | |
4816 | else | |
4817 | prev = insn; | |
4818 | ||
4819 | insn = next; | |
4820 | } | |
4821 | return insn; | |
4822 | } | |
4823 | ||
4824 | /* Return the head and tail pointers of BB. */ | |
4825 | ||
cbb13457 | 4826 | HAIFA_INLINE static void |
8c660648 JL |
4827 | get_block_head_tail (bb, headp, tailp) |
4828 | int bb; | |
4829 | rtx *headp; | |
4830 | rtx *tailp; | |
4831 | { | |
4832 | ||
55d89719 TK |
4833 | rtx head; |
4834 | rtx tail; | |
8c660648 JL |
4835 | int b; |
4836 | ||
4837 | b = BB_TO_BLOCK (bb); | |
4838 | ||
4839 | /* HEAD and TAIL delimit the basic block being scheduled. */ | |
3b413743 RH |
4840 | head = BLOCK_HEAD (b); |
4841 | tail = BLOCK_END (b); | |
8c660648 JL |
4842 | |
4843 | /* Don't include any notes or labels at the beginning of the | |
4844 | basic block, or notes at the ends of basic blocks. */ | |
4845 | while (head != tail) | |
4846 | { | |
4847 | if (GET_CODE (head) == NOTE) | |
4848 | head = NEXT_INSN (head); | |
4849 | else if (GET_CODE (tail) == NOTE) | |
4850 | tail = PREV_INSN (tail); | |
4851 | else if (GET_CODE (head) == CODE_LABEL) | |
4852 | head = NEXT_INSN (head); | |
4853 | else | |
4854 | break; | |
4855 | } | |
4856 | ||
4857 | *headp = head; | |
4858 | *tailp = tail; | |
4859 | } | |
4860 | ||
4861 | /* Delete line notes from bb. Save them so they can be later restored | |
4862 | (in restore_line_notes ()). */ | |
4863 | ||
4864 | static void | |
4865 | rm_line_notes (bb) | |
4866 | int bb; | |
4867 | { | |
4868 | rtx next_tail; | |
4869 | rtx tail; | |
4870 | rtx head; | |
4871 | rtx insn; | |
4872 | ||
4873 | get_block_head_tail (bb, &head, &tail); | |
4874 | ||
4875 | if (head == tail | |
4876 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4877 | return; | |
4878 | ||
4879 | next_tail = NEXT_INSN (tail); | |
4880 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4881 | { | |
4882 | rtx prev; | |
4883 | ||
4884 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4885 | This is needed to keep the debugger from | |
4886 | getting completely deranged. */ | |
4887 | if (GET_CODE (insn) == NOTE) | |
4888 | { | |
4889 | prev = insn; | |
4890 | insn = unlink_line_notes (insn, next_tail); | |
4891 | ||
4892 | if (prev == tail) | |
4893 | abort (); | |
4894 | if (prev == head) | |
4895 | abort (); | |
4896 | if (insn == next_tail) | |
4897 | abort (); | |
4898 | } | |
4899 | } | |
4900 | } | |
4901 | ||
4902 | /* Save line number notes for each insn in bb. */ | |
4903 | ||
4904 | static void | |
4905 | save_line_notes (bb) | |
4906 | int bb; | |
4907 | { | |
4908 | rtx head, tail; | |
4909 | rtx next_tail; | |
4910 | ||
4911 | /* We must use the true line number for the first insn in the block | |
4912 | that was computed and saved at the start of this pass. We can't | |
4913 | use the current line number, because scheduling of the previous | |
4914 | block may have changed the current line number. */ | |
4915 | ||
4916 | rtx line = line_note_head[BB_TO_BLOCK (bb)]; | |
4917 | rtx insn; | |
4918 | ||
4919 | get_block_head_tail (bb, &head, &tail); | |
4920 | next_tail = NEXT_INSN (tail); | |
4921 | ||
3b413743 | 4922 | for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb)); |
8c660648 JL |
4923 | insn != next_tail; |
4924 | insn = NEXT_INSN (insn)) | |
4925 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4926 | line = insn; | |
4927 | else | |
4928 | LINE_NOTE (insn) = line; | |
4929 | } | |
4930 | ||
4931 | ||
4932 | /* After bb was scheduled, insert line notes into the insns list. */ | |
4933 | ||
4934 | static void | |
4935 | restore_line_notes (bb) | |
4936 | int bb; | |
4937 | { | |
4938 | rtx line, note, prev, new; | |
4939 | int added_notes = 0; | |
4940 | int b; | |
4941 | rtx head, next_tail, insn; | |
4942 | ||
4943 | b = BB_TO_BLOCK (bb); | |
4944 | ||
3b413743 RH |
4945 | head = BLOCK_HEAD (b); |
4946 | next_tail = NEXT_INSN (BLOCK_END (b)); | |
8c660648 JL |
4947 | |
4948 | /* Determine the current line-number. We want to know the current | |
4949 | line number of the first insn of the block here, in case it is | |
4950 | different from the true line number that was saved earlier. If | |
4951 | different, then we need a line number note before the first insn | |
4952 | of this block. If it happens to be the same, then we don't want to | |
4953 | emit another line number note here. */ | |
4954 | for (line = head; line; line = PREV_INSN (line)) | |
4955 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) | |
4956 | break; | |
4957 | ||
4958 | /* Walk the insns keeping track of the current line-number and inserting | |
4959 | the line-number notes as needed. */ | |
4960 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4961 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4962 | line = insn; | |
4963 | /* This used to emit line number notes before every non-deleted note. | |
4964 | However, this confuses a debugger, because line notes not separated | |
4965 | by real instructions all end up at the same address. I can find no | |
4966 | use for line number notes before other notes, so none are emitted. */ | |
4967 | else if (GET_CODE (insn) != NOTE | |
4968 | && (note = LINE_NOTE (insn)) != 0 | |
4969 | && note != line | |
4970 | && (line == 0 | |
4971 | || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) | |
4972 | || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) | |
4973 | { | |
4974 | line = note; | |
4975 | prev = PREV_INSN (insn); | |
4976 | if (LINE_NOTE (note)) | |
4977 | { | |
4978 | /* Re-use the original line-number note. */ | |
4979 | LINE_NOTE (note) = 0; | |
4980 | PREV_INSN (note) = prev; | |
4981 | NEXT_INSN (prev) = note; | |
4982 | PREV_INSN (insn) = note; | |
4983 | NEXT_INSN (note) = insn; | |
4984 | } | |
4985 | else | |
4986 | { | |
4987 | added_notes++; | |
4988 | new = emit_note_after (NOTE_LINE_NUMBER (note), prev); | |
4989 | NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); | |
4990 | RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note); | |
4991 | } | |
4992 | } | |
4993 | if (sched_verbose && added_notes) | |
4994 | fprintf (dump, ";; added %d line-number notes\n", added_notes); | |
4995 | } | |
4996 | ||
4997 | /* After scheduling the function, delete redundant line notes from the | |
4998 | insns list. */ | |
4999 | ||
5000 | static void | |
5001 | rm_redundant_line_notes () | |
5002 | { | |
5003 | rtx line = 0; | |
5004 | rtx insn = get_insns (); | |
5005 | int active_insn = 0; | |
5006 | int notes = 0; | |
5007 | ||
5008 | /* Walk the insns deleting redundant line-number notes. Many of these | |
5009 | are already present. The remainder tend to occur at basic | |
5010 | block boundaries. */ | |
5011 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
5012 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
5013 | { | |
5014 | /* If there are no active insns following, INSN is redundant. */ | |
5015 | if (active_insn == 0) | |
5016 | { | |
5017 | notes++; | |
5018 | NOTE_SOURCE_FILE (insn) = 0; | |
5019 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
5020 | } | |
5021 | /* If the line number is unchanged, LINE is redundant. */ | |
5022 | else if (line | |
5023 | && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) | |
5024 | && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) | |
5025 | { | |
5026 | notes++; | |
5027 | NOTE_SOURCE_FILE (line) = 0; | |
5028 | NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; | |
5029 | line = insn; | |
5030 | } | |
5031 | else | |
5032 | line = insn; | |
5033 | active_insn = 0; | |
5034 | } | |
5035 | else if (!((GET_CODE (insn) == NOTE | |
5036 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) | |
5037 | || (GET_CODE (insn) == INSN | |
5038 | && (GET_CODE (PATTERN (insn)) == USE | |
5039 | || GET_CODE (PATTERN (insn)) == CLOBBER)))) | |
5040 | active_insn++; | |
5041 | ||
5042 | if (sched_verbose && notes) | |
5043 | fprintf (dump, ";; deleted %d line-number notes\n", notes); | |
5044 | } | |
5045 | ||
5046 | /* Delete notes between head and tail and put them in the chain | |
5047 | of notes ended by NOTE_LIST. */ | |
5048 | ||
5049 | static void | |
5050 | rm_other_notes (head, tail) | |
5051 | rtx head; | |
5052 | rtx tail; | |
5053 | { | |
5054 | rtx next_tail; | |
5055 | rtx insn; | |
5056 | ||
5057 | if (head == tail | |
5058 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5059 | return; | |
5060 | ||
5061 | next_tail = NEXT_INSN (tail); | |
5062 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5063 | { | |
5064 | rtx prev; | |
5065 | ||
5066 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
5067 | This is needed to keep the debugger from | |
5068 | getting completely deranged. */ | |
5069 | if (GET_CODE (insn) == NOTE) | |
5070 | { | |
5071 | prev = insn; | |
5072 | ||
5073 | insn = unlink_other_notes (insn, next_tail); | |
5074 | ||
5075 | if (prev == tail) | |
5076 | abort (); | |
5077 | if (prev == head) | |
5078 | abort (); | |
5079 | if (insn == next_tail) | |
5080 | abort (); | |
5081 | } | |
5082 | } | |
5083 | } | |
5084 | ||
5085 | /* Constructor for `sometimes' data structure. */ | |
5086 | ||
5087 | static int | |
5088 | new_sometimes_live (regs_sometimes_live, regno, sometimes_max) | |
5089 | struct sometimes *regs_sometimes_live; | |
5090 | int regno; | |
5091 | int sometimes_max; | |
5092 | { | |
5093 | register struct sometimes *p; | |
5094 | ||
5095 | /* There should never be a register greater than max_regno here. If there | |
5096 | is, it means that a define_split has created a new pseudo reg. This | |
5097 | is not allowed, since there will not be flow info available for any | |
5098 | new register, so catch the error here. */ | |
5099 | if (regno >= max_regno) | |
5100 | abort (); | |
5101 | ||
5102 | p = ®s_sometimes_live[sometimes_max]; | |
5103 | p->regno = regno; | |
5104 | p->live_length = 0; | |
5105 | p->calls_crossed = 0; | |
5106 | sometimes_max++; | |
5107 | return sometimes_max; | |
5108 | } | |
5109 | ||
5110 | /* Count lengths of all regs we are currently tracking, | |
5111 | and find new registers no longer live. */ | |
5112 | ||
5113 | static void | |
5114 | finish_sometimes_live (regs_sometimes_live, sometimes_max) | |
5115 | struct sometimes *regs_sometimes_live; | |
5116 | int sometimes_max; | |
5117 | { | |
5118 | int i; | |
5119 | ||
5120 | for (i = 0; i < sometimes_max; i++) | |
5121 | { | |
5122 | register struct sometimes *p = ®s_sometimes_live[i]; | |
5123 | int regno = p->regno; | |
5124 | ||
5125 | sched_reg_live_length[regno] += p->live_length; | |
5126 | sched_reg_n_calls_crossed[regno] += p->calls_crossed; | |
5127 | } | |
5128 | } | |
5129 | ||
5130 | /* functions for computation of registers live/usage info */ | |
5131 | ||
5132 | /* It is assumed that prior to scheduling basic_block_live_at_start (b) | |
5133 | contains the registers that are alive at the entry to b. | |
5134 | ||
5135 | Two passes follow: The first pass is performed before the scheduling | |
5136 | of a region. It scans each block of the region forward, computing | |
5137 | the set of registers alive at the end of the basic block and | |
5138 | discard REG_DEAD notes (done by find_pre_sched_live ()). | |
5139 | ||
5140 | The second path is invoked after scheduling all region blocks. | |
5141 | It scans each block of the region backward, a block being traversed | |
5142 | only after its succesors in the region. When the set of registers | |
5143 | live at the end of a basic block may be changed by the scheduling | |
5144 | (this may happen for multiple blocks region), it is computed as | |
5145 | the union of the registers live at the start of its succesors. | |
5146 | The last-use information is updated by inserting REG_DEAD notes. | |
5147 | (done by find_post_sched_live ()) */ | |
5148 | ||
5149 | /* Scan all the insns to be scheduled, removing register death notes. | |
5150 | Register death notes end up in DEAD_NOTES. | |
5151 | Recreate the register life information for the end of this basic | |
5152 | block. */ | |
5153 | ||
5154 | static void | |
5155 | find_pre_sched_live (bb) | |
5156 | int bb; | |
5157 | { | |
5158 | rtx insn, next_tail, head, tail; | |
5159 | int b = BB_TO_BLOCK (bb); | |
5160 | ||
5161 | get_block_head_tail (bb, &head, &tail); | |
5162 | COPY_REG_SET (bb_live_regs, basic_block_live_at_start[b]); | |
5163 | next_tail = NEXT_INSN (tail); | |
5164 | ||
5165 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5166 | { | |
5167 | rtx prev, next, link; | |
5168 | int reg_weight = 0; | |
5169 | ||
5170 | /* Handle register life information. */ | |
5171 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
5172 | { | |
5173 | /* See if the register gets born here. */ | |
5174 | /* We must check for registers being born before we check for | |
5175 | registers dying. It is possible for a register to be born and | |
5176 | die in the same insn, e.g. reading from a volatile memory | |
5177 | location into an otherwise unused register. Such a register | |
5178 | must be marked as dead after this insn. */ | |
5179 | if (GET_CODE (PATTERN (insn)) == SET | |
5180 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5181 | { | |
5835e573 | 5182 | sched_note_set (PATTERN (insn), 0); |
8c660648 JL |
5183 | reg_weight++; |
5184 | } | |
5185 | ||
5186 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
5187 | { | |
5188 | int j; | |
5189 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5190 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
5191 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
5192 | { | |
5835e573 | 5193 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0); |
8c660648 JL |
5194 | reg_weight++; |
5195 | } | |
5196 | ||
5197 | /* ??? This code is obsolete and should be deleted. It | |
5198 | is harmless though, so we will leave it in for now. */ | |
5199 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5200 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE) | |
5835e573 | 5201 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0); |
8c660648 JL |
5202 | } |
5203 | ||
5204 | /* Each call cobbers (makes live) all call-clobbered regs | |
5205 | that are not global or fixed. Note that the function-value | |
5206 | reg is a call_clobbered reg. */ | |
5207 | if (GET_CODE (insn) == CALL_INSN) | |
5208 | { | |
5209 | int j; | |
5210 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
5211 | if (call_used_regs[j] && !global_regs[j] | |
5212 | && ! fixed_regs[j]) | |
5213 | { | |
5214 | SET_REGNO_REG_SET (bb_live_regs, j); | |
8c660648 JL |
5215 | } |
5216 | } | |
5217 | ||
5218 | /* Need to know what registers this insn kills. */ | |
5219 | for (prev = 0, link = REG_NOTES (insn); link; link = next) | |
5220 | { | |
5221 | next = XEXP (link, 1); | |
5222 | if ((REG_NOTE_KIND (link) == REG_DEAD | |
5223 | || REG_NOTE_KIND (link) == REG_UNUSED) | |
5224 | /* Verify that the REG_NOTE has a valid value. */ | |
5225 | && GET_CODE (XEXP (link, 0)) == REG) | |
5226 | { | |
5227 | register int regno = REGNO (XEXP (link, 0)); | |
5228 | ||
5229 | reg_weight--; | |
5230 | ||
5231 | /* Only unlink REG_DEAD notes; leave REG_UNUSED notes | |
5232 | alone. */ | |
5233 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
5234 | { | |
5235 | if (prev) | |
5236 | XEXP (prev, 1) = next; | |
5237 | else | |
5238 | REG_NOTES (insn) = next; | |
5239 | XEXP (link, 1) = dead_notes; | |
5240 | dead_notes = link; | |
5241 | } | |
5242 | else | |
5243 | prev = link; | |
5244 | ||
5245 | if (regno < FIRST_PSEUDO_REGISTER) | |
5246 | { | |
5247 | int j = HARD_REGNO_NREGS (regno, | |
5248 | GET_MODE (XEXP (link, 0))); | |
5249 | while (--j >= 0) | |
5250 | { | |
5251 | CLEAR_REGNO_REG_SET (bb_live_regs, regno+j); | |
5252 | } | |
5253 | } | |
5254 | else | |
5255 | { | |
5256 | CLEAR_REGNO_REG_SET (bb_live_regs, regno); | |
5257 | } | |
5258 | } | |
5259 | else | |
5260 | prev = link; | |
5261 | } | |
5262 | } | |
5263 | ||
5264 | INSN_REG_WEIGHT (insn) = reg_weight; | |
5265 | } | |
5266 | } | |
5267 | ||
5268 | /* Update register life and usage information for block bb | |
5269 | after scheduling. Put register dead notes back in the code. */ | |
5270 | ||
5271 | static void | |
5272 | find_post_sched_live (bb) | |
5273 | int bb; | |
5274 | { | |
5275 | int sometimes_max; | |
5276 | int j, i; | |
5277 | int b; | |
5278 | rtx insn; | |
5279 | rtx head, tail, prev_head, next_tail; | |
5280 | ||
5281 | register struct sometimes *regs_sometimes_live; | |
5282 | ||
5283 | b = BB_TO_BLOCK (bb); | |
5284 | ||
5285 | /* compute live regs at the end of bb as a function of its successors. */ | |
5286 | if (current_nr_blocks > 1) | |
5287 | { | |
5288 | int e; | |
5289 | int first_edge; | |
5290 | ||
5291 | first_edge = e = OUT_EDGES (b); | |
5292 | CLEAR_REG_SET (bb_live_regs); | |
5293 | ||
5294 | if (e) | |
5295 | do | |
5296 | { | |
5297 | int b_succ; | |
5298 | ||
5299 | b_succ = TO_BLOCK (e); | |
5300 | IOR_REG_SET (bb_live_regs, basic_block_live_at_start[b_succ]); | |
5301 | e = NEXT_OUT (e); | |
5302 | } | |
5303 | while (e != first_edge); | |
5304 | } | |
5305 | ||
5306 | get_block_head_tail (bb, &head, &tail); | |
5307 | next_tail = NEXT_INSN (tail); | |
5308 | prev_head = PREV_INSN (head); | |
5309 | ||
7eea6443 JL |
5310 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, i, |
5311 | { | |
5312 | sched_reg_basic_block[i] = REG_BLOCK_GLOBAL; | |
5313 | }); | |
8c660648 JL |
5314 | |
5315 | /* if the block is empty, same regs are alive at its end and its start. | |
5316 | since this is not guaranteed after interblock scheduling, make sure they | |
5317 | are truly identical. */ | |
5318 | if (NEXT_INSN (prev_head) == tail | |
5319 | && (GET_RTX_CLASS (GET_CODE (tail)) != 'i')) | |
5320 | { | |
5321 | if (current_nr_blocks > 1) | |
5322 | COPY_REG_SET (basic_block_live_at_start[b], bb_live_regs); | |
5323 | ||
5324 | return; | |
5325 | } | |
5326 | ||
5327 | b = BB_TO_BLOCK (bb); | |
5328 | current_block_num = b; | |
5329 | ||
5330 | /* Keep track of register lives. */ | |
5331 | old_live_regs = ALLOCA_REG_SET (); | |
5332 | regs_sometimes_live | |
5333 | = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes)); | |
5334 | sometimes_max = 0; | |
5335 | ||
5336 | /* initiate "sometimes" data, starting with registers live at end */ | |
5337 | sometimes_max = 0; | |
5338 | COPY_REG_SET (old_live_regs, bb_live_regs); | |
5339 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, j, | |
5340 | { | |
5341 | sometimes_max | |
5342 | = new_sometimes_live (regs_sometimes_live, | |
5343 | j, sometimes_max); | |
5344 | }); | |
5345 | ||
5346 | /* scan insns back, computing regs live info */ | |
5347 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
5348 | { | |
5349 | /* First we kill registers set by this insn, and then we | |
5350 | make registers used by this insn live. This is the opposite | |
5351 | order used above because we are traversing the instructions | |
5352 | backwards. */ | |
5353 | ||
5354 | /* Strictly speaking, we should scan REG_UNUSED notes and make | |
5355 | every register mentioned there live, however, we will just | |
5356 | kill them again immediately below, so there doesn't seem to | |
5357 | be any reason why we bother to do this. */ | |
5358 | ||
5359 | /* See if this is the last notice we must take of a register. */ | |
5360 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5361 | continue; | |
5362 | ||
5363 | if (GET_CODE (PATTERN (insn)) == SET | |
5364 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5835e573 | 5365 | sched_note_set (PATTERN (insn), 1); |
8c660648 JL |
5366 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
5367 | { | |
5368 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5369 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
5370 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
5835e573 | 5371 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 1); |
8c660648 JL |
5372 | } |
5373 | ||
5374 | /* This code keeps life analysis information up to date. */ | |
5375 | if (GET_CODE (insn) == CALL_INSN) | |
5376 | { | |
5377 | register struct sometimes *p; | |
5378 | ||
5379 | /* A call kills all call used registers that are not | |
5380 | global or fixed, except for those mentioned in the call | |
5381 | pattern which will be made live again later. */ | |
5382 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5383 | if (call_used_regs[i] && ! global_regs[i] | |
5384 | && ! fixed_regs[i]) | |
5385 | { | |
5386 | CLEAR_REGNO_REG_SET (bb_live_regs, i); | |
8c660648 JL |
5387 | } |
5388 | ||
5389 | /* Regs live at the time of a call instruction must not | |
5390 | go in a register clobbered by calls. Record this for | |
5391 | all regs now live. Note that insns which are born or | |
5392 | die in a call do not cross a call, so this must be done | |
5393 | after the killings (above) and before the births | |
5394 | (below). */ | |
5395 | p = regs_sometimes_live; | |
5396 | for (i = 0; i < sometimes_max; i++, p++) | |
5397 | if (REGNO_REG_SET_P (bb_live_regs, p->regno)) | |
5398 | p->calls_crossed += 1; | |
5399 | } | |
5400 | ||
5401 | /* Make every register used live, and add REG_DEAD notes for | |
5402 | registers which were not live before we started. */ | |
5403 | attach_deaths_insn (insn); | |
5404 | ||
5405 | /* Find registers now made live by that instruction. */ | |
5406 | EXECUTE_IF_AND_COMPL_IN_REG_SET (bb_live_regs, old_live_regs, 0, j, | |
5407 | { | |
5408 | sometimes_max | |
5409 | = new_sometimes_live (regs_sometimes_live, | |
5410 | j, sometimes_max); | |
5411 | }); | |
5412 | IOR_REG_SET (old_live_regs, bb_live_regs); | |
5413 | ||
5414 | /* Count lengths of all regs we are worrying about now, | |
5415 | and handle registers no longer live. */ | |
5416 | ||
5417 | for (i = 0; i < sometimes_max; i++) | |
5418 | { | |
5419 | register struct sometimes *p = ®s_sometimes_live[i]; | |
5420 | int regno = p->regno; | |
5421 | ||
5422 | p->live_length += 1; | |
5423 | ||
5424 | if (!REGNO_REG_SET_P (bb_live_regs, regno)) | |
5425 | { | |
5426 | /* This is the end of one of this register's lifetime | |
5427 | segments. Save the lifetime info collected so far, | |
5428 | and clear its bit in the old_live_regs entry. */ | |
5429 | sched_reg_live_length[regno] += p->live_length; | |
5430 | sched_reg_n_calls_crossed[regno] += p->calls_crossed; | |
5431 | CLEAR_REGNO_REG_SET (old_live_regs, p->regno); | |
5432 | ||
5433 | /* Delete the reg_sometimes_live entry for this reg by | |
5434 | copying the last entry over top of it. */ | |
5435 | *p = regs_sometimes_live[--sometimes_max]; | |
5436 | /* ...and decrement i so that this newly copied entry | |
5437 | will be processed. */ | |
5438 | i--; | |
5439 | } | |
5440 | } | |
5441 | } | |
5442 | ||
5443 | finish_sometimes_live (regs_sometimes_live, sometimes_max); | |
5444 | ||
5445 | /* In interblock scheduling, basic_block_live_at_start may have changed. */ | |
5446 | if (current_nr_blocks > 1) | |
5447 | COPY_REG_SET (basic_block_live_at_start[b], bb_live_regs); | |
5448 | ||
f187056f JL |
5449 | |
5450 | FREE_REG_SET (old_live_regs); | |
8c660648 JL |
5451 | } /* find_post_sched_live */ |
5452 | ||
5453 | /* After scheduling the subroutine, restore information about uses of | |
5454 | registers. */ | |
5455 | ||
5456 | static void | |
5457 | update_reg_usage () | |
5458 | { | |
5459 | int regno; | |
5460 | ||
5461 | if (n_basic_blocks > 0) | |
7eea6443 JL |
5462 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, regno, |
5463 | { | |
5464 | sched_reg_basic_block[regno] | |
5465 | = REG_BLOCK_GLOBAL; | |
5466 | }); | |
8c660648 JL |
5467 | |
5468 | for (regno = 0; regno < max_regno; regno++) | |
5469 | if (sched_reg_live_length[regno]) | |
5470 | { | |
5471 | if (sched_verbose) | |
5472 | { | |
5473 | if (REG_LIVE_LENGTH (regno) > sched_reg_live_length[regno]) | |
5474 | fprintf (dump, | |
5475 | ";; register %d life shortened from %d to %d\n", | |
5476 | regno, REG_LIVE_LENGTH (regno), | |
5477 | sched_reg_live_length[regno]); | |
5478 | /* Negative values are special; don't overwrite the current | |
5479 | reg_live_length value if it is negative. */ | |
5480 | else if (REG_LIVE_LENGTH (regno) < sched_reg_live_length[regno] | |
5481 | && REG_LIVE_LENGTH (regno) >= 0) | |
5482 | fprintf (dump, | |
5483 | ";; register %d life extended from %d to %d\n", | |
5484 | regno, REG_LIVE_LENGTH (regno), | |
5485 | sched_reg_live_length[regno]); | |
5486 | ||
5487 | if (!REG_N_CALLS_CROSSED (regno) | |
5488 | && sched_reg_n_calls_crossed[regno]) | |
5489 | fprintf (dump, | |
5490 | ";; register %d now crosses calls\n", regno); | |
5491 | else if (REG_N_CALLS_CROSSED (regno) | |
5492 | && !sched_reg_n_calls_crossed[regno] | |
5493 | && REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL) | |
5494 | fprintf (dump, | |
5495 | ";; register %d no longer crosses calls\n", regno); | |
5496 | ||
5497 | if (REG_BASIC_BLOCK (regno) != sched_reg_basic_block[regno] | |
5498 | && sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN | |
5499 | && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN) | |
5500 | fprintf (dump, | |
5501 | ";; register %d changed basic block from %d to %d\n", | |
5502 | regno, REG_BASIC_BLOCK(regno), | |
5503 | sched_reg_basic_block[regno]); | |
5504 | ||
5505 | } | |
5506 | /* Negative values are special; don't overwrite the current | |
5507 | reg_live_length value if it is negative. */ | |
5508 | if (REG_LIVE_LENGTH (regno) >= 0) | |
5509 | REG_LIVE_LENGTH (regno) = sched_reg_live_length[regno]; | |
5510 | ||
5511 | if (sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN | |
5512 | && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN) | |
5513 | REG_BASIC_BLOCK(regno) = sched_reg_basic_block[regno]; | |
5514 | ||
5515 | /* We can't change the value of reg_n_calls_crossed to zero for | |
5516 | pseudos which are live in more than one block. | |
5517 | ||
5518 | This is because combine might have made an optimization which | |
5519 | invalidated basic_block_live_at_start and reg_n_calls_crossed, | |
5520 | but it does not update them. If we update reg_n_calls_crossed | |
5521 | here, the two variables are now inconsistent, and this might | |
5522 | confuse the caller-save code into saving a register that doesn't | |
5523 | need to be saved. This is only a problem when we zero calls | |
5524 | crossed for a pseudo live in multiple basic blocks. | |
5525 | ||
5526 | Alternatively, we could try to correctly update basic block live | |
5527 | at start here in sched, but that seems complicated. | |
5528 | ||
5529 | Note: it is possible that a global register became local, as result | |
5530 | of interblock motion, but will remain marked as a global register. */ | |
5531 | if (sched_reg_n_calls_crossed[regno] | |
5532 | || REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL) | |
5533 | REG_N_CALLS_CROSSED (regno) = sched_reg_n_calls_crossed[regno]; | |
5534 | ||
5535 | } | |
5536 | } | |
5537 | ||
5538 | /* Scheduling clock, modified in schedule_block() and queue_to_ready () */ | |
5539 | static int clock_var; | |
5540 | ||
5541 | /* Move insns that became ready to fire from queue to ready list. */ | |
5542 | ||
5543 | static int | |
5544 | queue_to_ready (ready, n_ready) | |
5545 | rtx ready[]; | |
5546 | int n_ready; | |
5547 | { | |
5548 | rtx insn; | |
5549 | rtx link; | |
5550 | ||
5551 | q_ptr = NEXT_Q (q_ptr); | |
5552 | ||
5553 | /* Add all pending insns that can be scheduled without stalls to the | |
5554 | ready list. */ | |
5555 | for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1)) | |
5556 | { | |
5557 | ||
5558 | insn = XEXP (link, 0); | |
5559 | q_size -= 1; | |
5560 | ||
5561 | if (sched_verbose >= 2) | |
5562 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
5563 | ||
5564 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
5565 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
5566 | ||
5567 | ready[n_ready++] = insn; | |
5568 | if (sched_verbose >= 2) | |
5569 | fprintf (dump, "moving to ready without stalls\n"); | |
5570 | } | |
5571 | insn_queue[q_ptr] = 0; | |
5572 | ||
5573 | /* If there are no ready insns, stall until one is ready and add all | |
5574 | of the pending insns at that point to the ready list. */ | |
5575 | if (n_ready == 0) | |
5576 | { | |
5577 | register int stalls; | |
5578 | ||
5579 | for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) | |
5580 | { | |
5581 | if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])) | |
5582 | { | |
5583 | for (; link; link = XEXP (link, 1)) | |
5584 | { | |
5585 | insn = XEXP (link, 0); | |
5586 | q_size -= 1; | |
5587 | ||
5588 | if (sched_verbose >= 2) | |
5589 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
5590 | ||
5591 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
5592 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
5593 | ||
5594 | ready[n_ready++] = insn; | |
5595 | if (sched_verbose >= 2) | |
5596 | fprintf (dump, "moving to ready with %d stalls\n", stalls); | |
5597 | } | |
5598 | insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; | |
5599 | ||
5600 | if (n_ready) | |
5601 | break; | |
5602 | } | |
5603 | } | |
5604 | ||
5605 | if (sched_verbose && stalls) | |
5606 | visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls); | |
5607 | q_ptr = NEXT_Q_AFTER (q_ptr, stalls); | |
5608 | clock_var += stalls; | |
5609 | } | |
5610 | return n_ready; | |
5611 | } | |
5612 | ||
5613 | /* Print the ready list for debugging purposes. Callable from debugger. */ | |
5614 | ||
9a8b0889 | 5615 | static void |
8c660648 JL |
5616 | debug_ready_list (ready, n_ready) |
5617 | rtx ready[]; | |
5618 | int n_ready; | |
5619 | { | |
5620 | int i; | |
5621 | ||
5622 | for (i = 0; i < n_ready; i++) | |
5623 | { | |
5624 | fprintf (dump, " %d", INSN_UID (ready[i])); | |
5625 | if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb) | |
5626 | fprintf (dump, "/b%d", INSN_BLOCK (ready[i])); | |
5627 | } | |
5628 | fprintf (dump, "\n"); | |
5629 | } | |
5630 | ||
5631 | /* Print names of units on which insn can/should execute, for debugging. */ | |
5632 | ||
5633 | static void | |
5634 | insn_print_units (insn) | |
5635 | rtx insn; | |
5636 | { | |
5637 | int i; | |
5638 | int unit = insn_unit (insn); | |
5639 | ||
5640 | if (unit == -1) | |
5641 | fprintf (dump, "none"); | |
5642 | else if (unit >= 0) | |
5643 | fprintf (dump, "%s", function_units[unit].name); | |
5644 | else | |
5645 | { | |
5646 | fprintf (dump, "["); | |
5647 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
5648 | if (unit & 1) | |
5649 | { | |
5650 | fprintf (dump, "%s", function_units[i].name); | |
5651 | if (unit != 1) | |
5652 | fprintf (dump, " "); | |
5653 | } | |
5654 | fprintf (dump, "]"); | |
5655 | } | |
5656 | } | |
5657 | ||
5658 | /* MAX_VISUAL_LINES is the maximum number of lines in visualization table | |
5659 | of a basic block. If more lines are needed, table is splitted to two. | |
5660 | n_visual_lines is the number of lines printed so far for a block. | |
5661 | visual_tbl contains the block visualization info. | |
5662 | vis_no_unit holds insns in a cycle that are not mapped to any unit. */ | |
5663 | #define MAX_VISUAL_LINES 100 | |
5664 | #define INSN_LEN 30 | |
5665 | int n_visual_lines; | |
5666 | char *visual_tbl; | |
5667 | int n_vis_no_unit; | |
5668 | rtx vis_no_unit[10]; | |
5669 | ||
5670 | /* Finds units that are in use in this fuction. Required only | |
5671 | for visualization. */ | |
5672 | ||
5673 | static void | |
5674 | init_target_units () | |
5675 | { | |
5676 | rtx insn; | |
5677 | int unit; | |
5678 | ||
5679 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
5680 | { | |
5681 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5682 | continue; | |
5683 | ||
5684 | unit = insn_unit (insn); | |
5685 | ||
5686 | if (unit < 0) | |
5687 | target_units |= ~unit; | |
5688 | else | |
5689 | target_units |= (1 << unit); | |
5690 | } | |
5691 | } | |
5692 | ||
5693 | /* Return the length of the visualization table */ | |
5694 | ||
5695 | static int | |
5696 | get_visual_tbl_length () | |
5697 | { | |
5698 | int unit, i; | |
5699 | int n, n1; | |
5700 | char *s; | |
5701 | ||
5702 | /* compute length of one field in line */ | |
5703 | s = (char *) alloca (INSN_LEN + 5); | |
5704 | sprintf (s, " %33s", "uname"); | |
5705 | n1 = strlen (s); | |
5706 | ||
5707 | /* compute length of one line */ | |
5708 | n = strlen (";; "); | |
5709 | n += n1; | |
5710 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5711 | if (function_units[unit].bitmask & target_units) | |
5712 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5713 | n += n1; | |
5714 | n += n1; | |
5715 | n += strlen ("\n") + 2; | |
5716 | ||
5717 | /* compute length of visualization string */ | |
5718 | return (MAX_VISUAL_LINES * n); | |
5719 | } | |
5720 | ||
5721 | /* Init block visualization debugging info */ | |
5722 | ||
5723 | static void | |
5724 | init_block_visualization () | |
5725 | { | |
5726 | strcpy (visual_tbl, ""); | |
5727 | n_visual_lines = 0; | |
5728 | n_vis_no_unit = 0; | |
5729 | } | |
5730 | ||
5731 | #define BUF_LEN 256 | |
5732 | ||
459b3825 MM |
5733 | static char * |
5734 | safe_concat (buf, cur, str) | |
5735 | char *buf; | |
5736 | char *cur; | |
5737 | char *str; | |
5738 | { | |
5739 | char *end = buf + BUF_LEN - 2; /* leave room for null */ | |
5740 | int c; | |
5741 | ||
5742 | if (cur > end) | |
5743 | { | |
5744 | *end = '\0'; | |
5745 | return end; | |
5746 | } | |
5747 | ||
5748 | while (cur < end && (c = *str++) != '\0') | |
5749 | *cur++ = c; | |
5750 | ||
5751 | *cur = '\0'; | |
5752 | return cur; | |
5753 | } | |
5754 | ||
8c660648 JL |
5755 | /* This recognizes rtx, I classified as expressions. These are always */ |
5756 | /* represent some action on values or results of other expression, */ | |
5757 | /* that may be stored in objects representing values. */ | |
5758 | ||
5759 | static void | |
5760 | print_exp (buf, x, verbose) | |
5761 | char *buf; | |
5762 | rtx x; | |
5763 | int verbose; | |
5764 | { | |
459b3825 MM |
5765 | char tmp[BUF_LEN]; |
5766 | char *st[4]; | |
5767 | char *cur = buf; | |
5768 | char *fun = (char *)0; | |
5769 | char *sep; | |
5770 | rtx op[4]; | |
5771 | int i; | |
5772 | ||
5773 | for (i = 0; i < 4; i++) | |
5774 | { | |
5775 | st[i] = (char *)0; | |
5776 | op[i] = NULL_RTX; | |
5777 | } | |
8c660648 JL |
5778 | |
5779 | switch (GET_CODE (x)) | |
5780 | { | |
5781 | case PLUS: | |
459b3825 MM |
5782 | op[0] = XEXP (x, 0); |
5783 | st[1] = "+"; | |
5784 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5785 | break; |
5786 | case LO_SUM: | |
459b3825 MM |
5787 | op[0] = XEXP (x, 0); |
5788 | st[1] = "+low("; | |
5789 | op[1] = XEXP (x, 1); | |
5790 | st[2] = ")"; | |
8c660648 JL |
5791 | break; |
5792 | case MINUS: | |
459b3825 MM |
5793 | op[0] = XEXP (x, 0); |
5794 | st[1] = "-"; | |
5795 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5796 | break; |
5797 | case COMPARE: | |
459b3825 MM |
5798 | fun = "cmp"; |
5799 | op[0] = XEXP (x, 0); | |
5800 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5801 | break; |
5802 | case NEG: | |
459b3825 MM |
5803 | st[0] = "-"; |
5804 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5805 | break; |
5806 | case MULT: | |
459b3825 MM |
5807 | op[0] = XEXP (x, 0); |
5808 | st[1] = "*"; | |
5809 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5810 | break; |
5811 | case DIV: | |
459b3825 MM |
5812 | op[0] = XEXP (x, 0); |
5813 | st[1] = "/"; | |
5814 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5815 | break; |
5816 | case UDIV: | |
459b3825 MM |
5817 | fun = "udiv"; |
5818 | op[0] = XEXP (x, 0); | |
5819 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5820 | break; |
5821 | case MOD: | |
459b3825 MM |
5822 | op[0] = XEXP (x, 0); |
5823 | st[1] = "%"; | |
5824 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5825 | break; |
5826 | case UMOD: | |
459b3825 MM |
5827 | fun = "umod"; |
5828 | op[0] = XEXP (x, 0); | |
5829 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5830 | break; |
5831 | case SMIN: | |
459b3825 MM |
5832 | fun = "smin"; |
5833 | op[0] = XEXP (x, 0); | |
5834 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5835 | break; |
5836 | case SMAX: | |
459b3825 MM |
5837 | fun = "smax"; |
5838 | op[0] = XEXP (x, 0); | |
5839 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5840 | break; |
5841 | case UMIN: | |
459b3825 MM |
5842 | fun = "umin"; |
5843 | op[0] = XEXP (x, 0); | |
5844 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5845 | break; |
5846 | case UMAX: | |
459b3825 MM |
5847 | fun = "umax"; |
5848 | op[0] = XEXP (x, 0); | |
5849 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5850 | break; |
5851 | case NOT: | |
459b3825 MM |
5852 | st[0] = "!"; |
5853 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5854 | break; |
5855 | case AND: | |
459b3825 MM |
5856 | op[0] = XEXP (x, 0); |
5857 | st[1] = "&"; | |
5858 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5859 | break; |
5860 | case IOR: | |
459b3825 MM |
5861 | op[0] = XEXP (x, 0); |
5862 | st[1] = "|"; | |
5863 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5864 | break; |
5865 | case XOR: | |
459b3825 MM |
5866 | op[0] = XEXP (x, 0); |
5867 | st[1] = "^"; | |
5868 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5869 | break; |
5870 | case ASHIFT: | |
459b3825 MM |
5871 | op[0] = XEXP (x, 0); |
5872 | st[1] = "<<"; | |
5873 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5874 | break; |
5875 | case LSHIFTRT: | |
459b3825 MM |
5876 | op[0] = XEXP (x, 0); |
5877 | st[1] = " 0>>"; | |
5878 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5879 | break; |
5880 | case ASHIFTRT: | |
459b3825 MM |
5881 | op[0] = XEXP (x, 0); |
5882 | st[1] = ">>"; | |
5883 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5884 | break; |
5885 | case ROTATE: | |
459b3825 MM |
5886 | op[0] = XEXP (x, 0); |
5887 | st[1] = "<-<"; | |
5888 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5889 | break; |
5890 | case ROTATERT: | |
459b3825 MM |
5891 | op[0] = XEXP (x, 0); |
5892 | st[1] = ">->"; | |
5893 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5894 | break; |
5895 | case ABS: | |
459b3825 MM |
5896 | fun = "abs"; |
5897 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5898 | break; |
5899 | case SQRT: | |
459b3825 MM |
5900 | fun = "sqrt"; |
5901 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5902 | break; |
5903 | case FFS: | |
459b3825 MM |
5904 | fun = "ffs"; |
5905 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5906 | break; |
5907 | case EQ: | |
459b3825 MM |
5908 | op[0] = XEXP (x, 0); |
5909 | st[1] = "=="; | |
5910 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5911 | break; |
5912 | case NE: | |
459b3825 MM |
5913 | op[0] = XEXP (x, 0); |
5914 | st[1] = "!="; | |
5915 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5916 | break; |
5917 | case GT: | |
459b3825 MM |
5918 | op[0] = XEXP (x, 0); |
5919 | st[1] = ">"; | |
5920 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5921 | break; |
5922 | case GTU: | |
459b3825 MM |
5923 | fun = "gtu"; |
5924 | op[0] = XEXP (x, 0); | |
5925 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5926 | break; |
5927 | case LT: | |
459b3825 MM |
5928 | op[0] = XEXP (x, 0); |
5929 | st[1] = "<"; | |
5930 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5931 | break; |
5932 | case LTU: | |
459b3825 MM |
5933 | fun = "ltu"; |
5934 | op[0] = XEXP (x, 0); | |
5935 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5936 | break; |
5937 | case GE: | |
459b3825 MM |
5938 | op[0] = XEXP (x, 0); |
5939 | st[1] = ">="; | |
5940 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5941 | break; |
5942 | case GEU: | |
459b3825 MM |
5943 | fun = "geu"; |
5944 | op[0] = XEXP (x, 0); | |
5945 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5946 | break; |
5947 | case LE: | |
459b3825 MM |
5948 | op[0] = XEXP (x, 0); |
5949 | st[1] = "<="; | |
5950 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5951 | break; |
5952 | case LEU: | |
459b3825 MM |
5953 | fun = "leu"; |
5954 | op[0] = XEXP (x, 0); | |
5955 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5956 | break; |
5957 | case SIGN_EXTRACT: | |
459b3825 MM |
5958 | fun = (verbose) ? "sign_extract" : "sxt"; |
5959 | op[0] = XEXP (x, 0); | |
5960 | op[1] = XEXP (x, 1); | |
5961 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5962 | break; |
5963 | case ZERO_EXTRACT: | |
459b3825 MM |
5964 | fun = (verbose) ? "zero_extract" : "zxt"; |
5965 | op[0] = XEXP (x, 0); | |
5966 | op[1] = XEXP (x, 1); | |
5967 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5968 | break; |
5969 | case SIGN_EXTEND: | |
459b3825 MM |
5970 | fun = (verbose) ? "sign_extend" : "sxn"; |
5971 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5972 | break; |
5973 | case ZERO_EXTEND: | |
459b3825 MM |
5974 | fun = (verbose) ? "zero_extend" : "zxn"; |
5975 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5976 | break; |
5977 | case FLOAT_EXTEND: | |
459b3825 MM |
5978 | fun = (verbose) ? "float_extend" : "fxn"; |
5979 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5980 | break; |
5981 | case TRUNCATE: | |
459b3825 MM |
5982 | fun = (verbose) ? "trunc" : "trn"; |
5983 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5984 | break; |
5985 | case FLOAT_TRUNCATE: | |
459b3825 MM |
5986 | fun = (verbose) ? "float_trunc" : "ftr"; |
5987 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5988 | break; |
5989 | case FLOAT: | |
459b3825 MM |
5990 | fun = (verbose) ? "float" : "flt"; |
5991 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5992 | break; |
5993 | case UNSIGNED_FLOAT: | |
459b3825 MM |
5994 | fun = (verbose) ? "uns_float" : "ufl"; |
5995 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5996 | break; |
5997 | case FIX: | |
459b3825 MM |
5998 | fun = "fix"; |
5999 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6000 | break; |
6001 | case UNSIGNED_FIX: | |
459b3825 MM |
6002 | fun = (verbose) ? "uns_fix" : "ufx"; |
6003 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6004 | break; |
6005 | case PRE_DEC: | |
459b3825 MM |
6006 | st[0] = "--"; |
6007 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6008 | break; |
6009 | case PRE_INC: | |
459b3825 MM |
6010 | st[0] = "++"; |
6011 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6012 | break; |
6013 | case POST_DEC: | |
459b3825 MM |
6014 | op[0] = XEXP (x, 0); |
6015 | st[1] = "--"; | |
8c660648 JL |
6016 | break; |
6017 | case POST_INC: | |
459b3825 MM |
6018 | op[0] = XEXP (x, 0); |
6019 | st[1] = "++"; | |
8c660648 JL |
6020 | break; |
6021 | case CALL: | |
459b3825 MM |
6022 | st[0] = "call "; |
6023 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6024 | if (verbose) |
6025 | { | |
459b3825 MM |
6026 | st[1] = " argc:"; |
6027 | op[1] = XEXP (x, 1); | |
8c660648 | 6028 | } |
8c660648 JL |
6029 | break; |
6030 | case IF_THEN_ELSE: | |
459b3825 MM |
6031 | st[0] = "{("; |
6032 | op[0] = XEXP (x, 0); | |
6033 | st[1] = ")?"; | |
6034 | op[1] = XEXP (x, 1); | |
6035 | st[2] = ":"; | |
6036 | op[2] = XEXP (x, 2); | |
6037 | st[3] = "}"; | |
8c660648 JL |
6038 | break; |
6039 | case TRAP_IF: | |
459b3825 MM |
6040 | fun = "trap_if"; |
6041 | op[0] = TRAP_CONDITION (x); | |
8c660648 JL |
6042 | break; |
6043 | case UNSPEC: | |
8c660648 JL |
6044 | case UNSPEC_VOLATILE: |
6045 | { | |
459b3825 MM |
6046 | cur = safe_concat (buf, cur, "unspec"); |
6047 | if (GET_CODE (x) == UNSPEC_VOLATILE) | |
6048 | cur = safe_concat (buf, cur, "/v"); | |
6049 | cur = safe_concat (buf, cur, "["); | |
6050 | sep = ""; | |
8c660648 JL |
6051 | for (i = 0; i < XVECLEN (x, 0); i++) |
6052 | { | |
459b3825 MM |
6053 | print_pattern (tmp, XVECEXP (x, 0, i), verbose); |
6054 | cur = safe_concat (buf, cur, sep); | |
6055 | cur = safe_concat (buf, cur, tmp); | |
6056 | sep = ","; | |
8c660648 | 6057 | } |
459b3825 MM |
6058 | cur = safe_concat (buf, cur, "] "); |
6059 | sprintf (tmp, "%d", XINT (x, 1)); | |
6060 | cur = safe_concat (buf, cur, tmp); | |
8c660648 JL |
6061 | } |
6062 | break; | |
6063 | default: | |
53c0919d RH |
6064 | /* if (verbose) debug_rtx (x); */ |
6065 | st[0] = GET_RTX_NAME (GET_CODE (x)); | |
459b3825 MM |
6066 | break; |
6067 | } | |
6068 | ||
6069 | /* Print this as a function? */ | |
6070 | if (fun) | |
6071 | { | |
6072 | cur = safe_concat (buf, cur, fun); | |
6073 | cur = safe_concat (buf, cur, "("); | |
6074 | } | |
6075 | ||
6076 | for (i = 0; i < 4; i++) | |
6077 | { | |
6078 | if (st[i]) | |
6079 | cur = safe_concat (buf, cur, st[i]); | |
6080 | ||
6081 | if (op[i]) | |
6082 | { | |
6083 | if (fun && i != 0) | |
6084 | cur = safe_concat (buf, cur, ","); | |
6085 | ||
6086 | print_value (tmp, op[i], verbose); | |
6087 | cur = safe_concat (buf, cur, tmp); | |
6088 | } | |
8c660648 | 6089 | } |
459b3825 MM |
6090 | |
6091 | if (fun) | |
6092 | cur = safe_concat (buf, cur, ")"); | |
6093 | } /* print_exp */ | |
8c660648 JL |
6094 | |
6095 | /* Prints rtxes, i customly classified as values. They're constants, */ | |
6096 | /* registers, labels, symbols and memory accesses. */ | |
6097 | ||
6098 | static void | |
6099 | print_value (buf, x, verbose) | |
6100 | char *buf; | |
6101 | rtx x; | |
6102 | int verbose; | |
6103 | { | |
6104 | char t[BUF_LEN]; | |
459b3825 | 6105 | char *cur = buf; |
8c660648 JL |
6106 | |
6107 | switch (GET_CODE (x)) | |
6108 | { | |
6109 | case CONST_INT: | |
459b3825 MM |
6110 | sprintf (t, "0x%lx", (long)INTVAL (x)); |
6111 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6112 | break; |
6113 | case CONST_DOUBLE: | |
459b3825 MM |
6114 | sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); |
6115 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6116 | break; |
6117 | case CONST_STRING: | |
459b3825 MM |
6118 | cur = safe_concat (buf, cur, "\""); |
6119 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
6120 | cur = safe_concat (buf, cur, "\""); | |
8c660648 JL |
6121 | break; |
6122 | case SYMBOL_REF: | |
459b3825 MM |
6123 | cur = safe_concat (buf, cur, "`"); |
6124 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
6125 | cur = safe_concat (buf, cur, "'"); | |
8c660648 JL |
6126 | break; |
6127 | case LABEL_REF: | |
459b3825 MM |
6128 | sprintf (t, "L%d", INSN_UID (XEXP (x, 0))); |
6129 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6130 | break; |
6131 | case CONST: | |
459b3825 MM |
6132 | print_value (t, XEXP (x, 0), verbose); |
6133 | cur = safe_concat (buf, cur, "const("); | |
6134 | cur = safe_concat (buf, cur, t); | |
6135 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
6136 | break; |
6137 | case HIGH: | |
459b3825 MM |
6138 | print_value (t, XEXP (x, 0), verbose); |
6139 | cur = safe_concat (buf, cur, "high("); | |
6140 | cur = safe_concat (buf, cur, t); | |
6141 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
6142 | break; |
6143 | case REG: | |
459b3825 MM |
6144 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) |
6145 | { | |
6146 | int c = reg_names[ REGNO (x) ][0]; | |
6147 | if (c >= '0' && c <= '9') | |
6148 | cur = safe_concat (buf, cur, "%"); | |
6149 | ||
6150 | cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]); | |
6151 | } | |
8c660648 | 6152 | else |
459b3825 MM |
6153 | { |
6154 | sprintf (t, "r%d", REGNO (x)); | |
6155 | cur = safe_concat (buf, cur, t); | |
6156 | } | |
8c660648 JL |
6157 | break; |
6158 | case SUBREG: | |
459b3825 MM |
6159 | print_value (t, SUBREG_REG (x), verbose); |
6160 | cur = safe_concat (buf, cur, t); | |
6b879bcc | 6161 | sprintf (t, "#%d", SUBREG_WORD (x)); |
459b3825 | 6162 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
6163 | break; |
6164 | case SCRATCH: | |
459b3825 | 6165 | cur = safe_concat (buf, cur, "scratch"); |
8c660648 JL |
6166 | break; |
6167 | case CC0: | |
459b3825 | 6168 | cur = safe_concat (buf, cur, "cc0"); |
8c660648 JL |
6169 | break; |
6170 | case PC: | |
459b3825 | 6171 | cur = safe_concat (buf, cur, "pc"); |
8c660648 JL |
6172 | break; |
6173 | case MEM: | |
6174 | print_value (t, XEXP (x, 0), verbose); | |
459b3825 MM |
6175 | cur = safe_concat (buf, cur, "["); |
6176 | cur = safe_concat (buf, cur, t); | |
6177 | cur = safe_concat (buf, cur, "]"); | |
8c660648 JL |
6178 | break; |
6179 | default: | |
459b3825 MM |
6180 | print_exp (t, x, verbose); |
6181 | cur = safe_concat (buf, cur, t); | |
6182 | break; | |
8c660648 JL |
6183 | } |
6184 | } /* print_value */ | |
6185 | ||
6186 | /* The next step in insn detalization, its pattern recognition */ | |
6187 | ||
6188 | static void | |
6189 | print_pattern (buf, x, verbose) | |
6190 | char *buf; | |
6191 | rtx x; | |
6192 | int verbose; | |
6193 | { | |
6194 | char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN]; | |
6195 | ||
6196 | switch (GET_CODE (x)) | |
6197 | { | |
6198 | case SET: | |
6199 | print_value (t1, SET_DEST (x), verbose); | |
6200 | print_value (t2, SET_SRC (x), verbose); | |
6201 | sprintf (buf, "%s=%s", t1, t2); | |
6202 | break; | |
6203 | case RETURN: | |
6204 | sprintf (buf, "return"); | |
6205 | break; | |
6206 | case CALL: | |
6207 | print_exp (buf, x, verbose); | |
6208 | break; | |
6209 | case CLOBBER: | |
6210 | print_value (t1, XEXP (x, 0), verbose); | |
6211 | sprintf (buf, "clobber %s", t1); | |
6212 | break; | |
6213 | case USE: | |
6214 | print_value (t1, XEXP (x, 0), verbose); | |
6215 | sprintf (buf, "use %s", t1); | |
6216 | break; | |
6217 | case PARALLEL: | |
6218 | { | |
6219 | int i; | |
6220 | ||
6221 | sprintf (t1, "{"); | |
6222 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6223 | { | |
6224 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6225 | sprintf (t3, "%s%s;", t1, t2); | |
6226 | strcpy (t1, t3); | |
6227 | } | |
6228 | sprintf (buf, "%s}", t1); | |
6229 | } | |
6230 | break; | |
6231 | case SEQUENCE: | |
6232 | { | |
6233 | int i; | |
6234 | ||
6235 | sprintf (t1, "%%{"); | |
6236 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6237 | { | |
6238 | print_insn (t2, XVECEXP (x, 0, i), verbose); | |
6239 | sprintf (t3, "%s%s;", t1, t2); | |
6240 | strcpy (t1, t3); | |
6241 | } | |
6242 | sprintf (buf, "%s%%}", t1); | |
6243 | } | |
6244 | break; | |
6245 | case ASM_INPUT: | |
c4fa3460 | 6246 | sprintf (buf, "asm {%s}", XSTR (x, 0)); |
8c660648 JL |
6247 | break; |
6248 | case ADDR_VEC: | |
6249 | break; | |
6250 | case ADDR_DIFF_VEC: | |
6251 | print_value (buf, XEXP (x, 0), verbose); | |
6252 | break; | |
6253 | case TRAP_IF: | |
6254 | print_value (t1, TRAP_CONDITION (x), verbose); | |
6255 | sprintf (buf, "trap_if %s", t1); | |
6256 | break; | |
6257 | case UNSPEC: | |
6258 | { | |
6259 | int i; | |
6260 | ||
6261 | sprintf (t1, "unspec{"); | |
6262 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6263 | { | |
6264 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6265 | sprintf (t3, "%s%s;", t1, t2); | |
6266 | strcpy (t1, t3); | |
6267 | } | |
6268 | sprintf (buf, "%s}", t1); | |
6269 | } | |
6270 | break; | |
6271 | case UNSPEC_VOLATILE: | |
6272 | { | |
6273 | int i; | |
6274 | ||
6275 | sprintf (t1, "unspec/v{"); | |
6276 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6277 | { | |
6278 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6279 | sprintf (t3, "%s%s;", t1, t2); | |
6280 | strcpy (t1, t3); | |
6281 | } | |
6282 | sprintf (buf, "%s}", t1); | |
6283 | } | |
6284 | break; | |
6285 | default: | |
6286 | print_value (buf, x, verbose); | |
6287 | } | |
6288 | } /* print_pattern */ | |
6289 | ||
6290 | /* This is the main function in rtl visualization mechanism. It | |
6291 | accepts an rtx and tries to recognize it as an insn, then prints it | |
6292 | properly in human readable form, resembling assembler mnemonics. */ | |
6293 | /* For every insn it prints its UID and BB the insn belongs */ | |
6294 | /* too. (probably the last "option" should be extended somehow, since */ | |
6295 | /* it depends now on sched.c inner variables ...) */ | |
6296 | ||
6297 | static void | |
6298 | print_insn (buf, x, verbose) | |
6299 | char *buf; | |
6300 | rtx x; | |
6301 | int verbose; | |
6302 | { | |
6303 | char t[BUF_LEN]; | |
6304 | rtx insn = x; | |
6305 | ||
6306 | switch (GET_CODE (x)) | |
6307 | { | |
6308 | case INSN: | |
6309 | print_pattern (t, PATTERN (x), verbose); | |
6310 | if (verbose) | |
6311 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x), | |
6312 | INSN_UID (x), t); | |
6313 | else | |
6314 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
6315 | break; | |
6316 | case JUMP_INSN: | |
6317 | print_pattern (t, PATTERN (x), verbose); | |
6318 | if (verbose) | |
6319 | sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x), | |
6320 | INSN_UID (x), t); | |
6321 | else | |
6322 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
6323 | break; | |
6324 | case CALL_INSN: | |
6325 | x = PATTERN (insn); | |
6326 | if (GET_CODE (x) == PARALLEL) | |
6327 | { | |
6328 | x = XVECEXP (x, 0, 0); | |
6329 | print_pattern (t, x, verbose); | |
6330 | } | |
6331 | else | |
6332 | strcpy (t, "call <...>"); | |
6333 | if (verbose) | |
6334 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn), | |
6335 | INSN_UID (insn), t); | |
6336 | else | |
6337 | sprintf (buf, "%-4d %s", INSN_UID (insn), t); | |
6338 | break; | |
6339 | case CODE_LABEL: | |
6340 | sprintf (buf, "L%d:", INSN_UID (x)); | |
6341 | break; | |
6342 | case BARRIER: | |
6343 | sprintf (buf, "i% 4d: barrier", INSN_UID (x)); | |
6344 | break; | |
6345 | case NOTE: | |
6346 | if (NOTE_LINE_NUMBER (x) > 0) | |
6347 | sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x), | |
6348 | NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x)); | |
6349 | else | |
6350 | sprintf (buf, "%4d %s", INSN_UID (x), | |
6351 | GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x))); | |
6352 | break; | |
6353 | default: | |
6354 | if (verbose) | |
6355 | { | |
6356 | sprintf (buf, "Not an INSN at all\n"); | |
6357 | debug_rtx (x); | |
6358 | } | |
6359 | else | |
6360 | sprintf (buf, "i%-4d <What?>", INSN_UID (x)); | |
6361 | } | |
6362 | } /* print_insn */ | |
6363 | ||
8c660648 JL |
6364 | /* Print visualization debugging info */ |
6365 | ||
6366 | static void | |
6367 | print_block_visualization (b, s) | |
6368 | int b; | |
6369 | char *s; | |
6370 | { | |
6371 | int unit, i; | |
8c660648 JL |
6372 | |
6373 | /* print header */ | |
6374 | fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s); | |
6375 | ||
6376 | /* Print names of units */ | |
2f308fec | 6377 | fprintf (dump, ";; %-8s", "clock"); |
8c660648 JL |
6378 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) |
6379 | if (function_units[unit].bitmask & target_units) | |
6380 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
2f308fec RH |
6381 | fprintf (dump, " %-33s", function_units[unit].name); |
6382 | fprintf (dump, " %-8s\n", "no-unit"); | |
6383 | ||
6384 | fprintf (dump, ";; %-8s", "====="); | |
6385 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
6386 | if (function_units[unit].bitmask & target_units) | |
6387 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
6388 | fprintf (dump, " %-33s", "=============================="); | |
6389 | fprintf (dump, " %-8s\n", "======="); | |
8c660648 JL |
6390 | |
6391 | /* Print insns in each cycle */ | |
6392 | fprintf (dump, "%s\n", visual_tbl); | |
6393 | } | |
6394 | ||
6395 | /* Print insns in the 'no_unit' column of visualization */ | |
6396 | ||
6397 | static void | |
6398 | visualize_no_unit (insn) | |
6399 | rtx insn; | |
6400 | { | |
6401 | vis_no_unit[n_vis_no_unit] = insn; | |
6402 | n_vis_no_unit++; | |
6403 | } | |
6404 | ||
6405 | /* Print insns scheduled in clock, for visualization. */ | |
6406 | ||
6407 | static void | |
6408 | visualize_scheduled_insns (b, clock) | |
6409 | int b, clock; | |
6410 | { | |
6411 | int i, unit; | |
6412 | ||
6413 | /* if no more room, split table into two */ | |
6414 | if (n_visual_lines >= MAX_VISUAL_LINES) | |
6415 | { | |
6416 | print_block_visualization (b, "(incomplete)"); | |
6417 | init_block_visualization (); | |
6418 | } | |
6419 | ||
6420 | n_visual_lines++; | |
6421 | ||
6422 | sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock); | |
6423 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
6424 | if (function_units[unit].bitmask & target_units) | |
6425 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
6426 | { | |
6427 | int instance = unit + i * FUNCTION_UNITS_SIZE; | |
6428 | rtx insn = unit_last_insn[instance]; | |
6429 | ||
6430 | /* print insns that still keep the unit busy */ | |
6431 | if (insn && | |
6432 | actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
6433 | { | |
6434 | char str[BUF_LEN]; | |
6435 | print_insn (str, insn, 0); | |
6436 | str[INSN_LEN] = '\0'; | |
6437 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str); | |
6438 | } | |
6439 | else | |
6440 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------"); | |
6441 | } | |
6442 | ||
6443 | /* print insns that are not assigned to any unit */ | |
6444 | for (i = 0; i < n_vis_no_unit; i++) | |
6445 | sprintf (visual_tbl + strlen (visual_tbl), " %-8d", | |
6446 | INSN_UID (vis_no_unit[i])); | |
6447 | n_vis_no_unit = 0; | |
6448 | ||
6449 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
6450 | } | |
6451 | ||
6452 | /* Print stalled cycles */ | |
6453 | ||
6454 | static void | |
6455 | visualize_stall_cycles (b, stalls) | |
6456 | int b, stalls; | |
6457 | { | |
6458 | int i; | |
6459 | ||
6460 | /* if no more room, split table into two */ | |
6461 | if (n_visual_lines >= MAX_VISUAL_LINES) | |
6462 | { | |
6463 | print_block_visualization (b, "(incomplete)"); | |
6464 | init_block_visualization (); | |
6465 | } | |
6466 | ||
6467 | n_visual_lines++; | |
6468 | ||
6469 | sprintf (visual_tbl + strlen (visual_tbl), ";; "); | |
6470 | for (i = 0; i < stalls; i++) | |
6471 | sprintf (visual_tbl + strlen (visual_tbl), "."); | |
6472 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
6473 | } | |
6474 | ||
6475 | /* move_insn1: Remove INSN from insn chain, and link it after LAST insn */ | |
6476 | ||
6477 | static rtx | |
6478 | move_insn1 (insn, last) | |
6479 | rtx insn, last; | |
6480 | { | |
6481 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
6482 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
6483 | ||
6484 | NEXT_INSN (insn) = NEXT_INSN (last); | |
6485 | PREV_INSN (NEXT_INSN (last)) = insn; | |
6486 | ||
6487 | NEXT_INSN (last) = insn; | |
6488 | PREV_INSN (insn) = last; | |
6489 | ||
6490 | return insn; | |
6491 | } | |
6492 | ||
6493 | /* Search INSN for fake REG_DEAD note pairs for NOTE_INSN_SETJMP, | |
6494 | NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into | |
6495 | NOTEs. The REG_DEAD note following first one is contains the saved | |
6496 | value for NOTE_BLOCK_NUMBER which is useful for | |
6497 | NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction | |
6498 | output by the instruction scheduler. Return the new value of LAST. */ | |
6499 | ||
6500 | static rtx | |
6501 | reemit_notes (insn, last) | |
6502 | rtx insn; | |
6503 | rtx last; | |
6504 | { | |
6505 | rtx note, retval; | |
6506 | ||
6507 | retval = last; | |
6508 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
6509 | { | |
6510 | if (REG_NOTE_KIND (note) == REG_DEAD | |
6511 | && GET_CODE (XEXP (note, 0)) == CONST_INT) | |
6512 | { | |
6dfdecdb RH |
6513 | int note_type = INTVAL (XEXP (note, 0)); |
6514 | if (note_type == NOTE_INSN_SETJMP) | |
8c660648 | 6515 | { |
6dfdecdb | 6516 | retval = emit_note_after (NOTE_INSN_SETJMP, insn); |
8c660648 JL |
6517 | CONST_CALL_P (retval) = CONST_CALL_P (note); |
6518 | remove_note (insn, note); | |
6519 | note = XEXP (note, 1); | |
6520 | } | |
6dfdecdb RH |
6521 | else if (note_type == NOTE_INSN_RANGE_START |
6522 | || note_type == NOTE_INSN_RANGE_END) | |
6523 | { | |
6524 | last = emit_note_before (note_type, last); | |
6525 | remove_note (insn, note); | |
6526 | note = XEXP (note, 1); | |
6527 | NOTE_RANGE_INFO (last) = XEXP (note, 0); | |
6528 | } | |
8c660648 JL |
6529 | else |
6530 | { | |
6531 | last = emit_note_before (INTVAL (XEXP (note, 0)), last); | |
6532 | remove_note (insn, note); | |
6533 | note = XEXP (note, 1); | |
6534 | NOTE_BLOCK_NUMBER (last) = INTVAL (XEXP (note, 0)); | |
6535 | } | |
6536 | remove_note (insn, note); | |
6537 | } | |
6538 | } | |
6539 | return retval; | |
6540 | } | |
6541 | ||
6542 | /* Move INSN, and all insns which should be issued before it, | |
c9e03727 JL |
6543 | due to SCHED_GROUP_P flag. Reemit notes if needed. |
6544 | ||
6545 | Return the last insn emitted by the scheduler, which is the | |
6546 | return value from the first call to reemit_notes. */ | |
8c660648 JL |
6547 | |
6548 | static rtx | |
6549 | move_insn (insn, last) | |
6550 | rtx insn, last; | |
6551 | { | |
c9e03727 | 6552 | rtx retval = NULL; |
8c660648 | 6553 | |
c9e03727 JL |
6554 | /* If INSN has SCHED_GROUP_P set, then issue it and any other |
6555 | insns with SCHED_GROUP_P set first. */ | |
8c660648 JL |
6556 | while (SCHED_GROUP_P (insn)) |
6557 | { | |
6558 | rtx prev = PREV_INSN (insn); | |
c9e03727 JL |
6559 | |
6560 | /* Move a SCHED_GROUP_P insn. */ | |
8c660648 | 6561 | move_insn1 (insn, last); |
c9e03727 JL |
6562 | /* If this is the first call to reemit_notes, then record |
6563 | its return value. */ | |
6564 | if (retval == NULL_RTX) | |
6565 | retval = reemit_notes (insn, insn); | |
6566 | else | |
6567 | reemit_notes (insn, insn); | |
8c660648 JL |
6568 | insn = prev; |
6569 | } | |
6570 | ||
c9e03727 | 6571 | /* Now move the first non SCHED_GROUP_P insn. */ |
8c660648 | 6572 | move_insn1 (insn, last); |
c9e03727 JL |
6573 | |
6574 | /* If this is the first call to reemit_notes, then record | |
6575 | its return value. */ | |
6576 | if (retval == NULL_RTX) | |
6577 | retval = reemit_notes (insn, insn); | |
6578 | else | |
6579 | reemit_notes (insn, insn); | |
6580 | ||
6581 | return retval; | |
8c660648 JL |
6582 | } |
6583 | ||
6584 | /* Return an insn which represents a SCHED_GROUP, which is | |
6585 | the last insn in the group. */ | |
6586 | ||
6587 | static rtx | |
6588 | group_leader (insn) | |
6589 | rtx insn; | |
6590 | { | |
6591 | rtx prev; | |
6592 | ||
6593 | do | |
6594 | { | |
6595 | prev = insn; | |
6596 | insn = next_nonnote_insn (insn); | |
6597 | } | |
6598 | while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL)); | |
6599 | ||
6600 | return prev; | |
6601 | } | |
6602 | ||
6603 | /* Use forward list scheduling to rearrange insns of block BB in region RGN, | |
6604 | possibly bringing insns from subsequent blocks in the same region. | |
6605 | Return number of insns scheduled. */ | |
6606 | ||
6607 | static int | |
5835e573 | 6608 | schedule_block (bb, rgn_n_insns) |
8c660648 | 6609 | int bb; |
8c660648 JL |
6610 | int rgn_n_insns; |
6611 | { | |
6612 | /* Local variables. */ | |
6613 | rtx insn, last; | |
6614 | rtx *ready; | |
6615 | int i; | |
6616 | int n_ready = 0; | |
6617 | int can_issue_more; | |
6618 | ||
6619 | /* flow block of this bb */ | |
6620 | int b = BB_TO_BLOCK (bb); | |
6621 | ||
6622 | /* target_n_insns == number of insns in b before scheduling starts. | |
6623 | sched_target_n_insns == how many of b's insns were scheduled. | |
6624 | sched_n_insns == how many insns were scheduled in b */ | |
6625 | int target_n_insns = 0; | |
6626 | int sched_target_n_insns = 0; | |
6627 | int sched_n_insns = 0; | |
6628 | ||
6629 | #define NEED_NOTHING 0 | |
6630 | #define NEED_HEAD 1 | |
6631 | #define NEED_TAIL 2 | |
6632 | int new_needs; | |
6633 | ||
6634 | /* head/tail info for this block */ | |
6635 | rtx prev_head; | |
6636 | rtx next_tail; | |
6637 | rtx head; | |
6638 | rtx tail; | |
6639 | int bb_src; | |
6640 | ||
484df988 JL |
6641 | /* We used to have code to avoid getting parameters moved from hard |
6642 | argument registers into pseudos. | |
8c660648 | 6643 | |
484df988 JL |
6644 | However, it was removed when it proved to be of marginal benefit |
6645 | and caused problems because schedule_block and compute_forward_dependences | |
6646 | had different notions of what the "head" insn was. */ | |
6647 | get_block_head_tail (bb, &head, &tail); | |
8c660648 | 6648 | |
1447b516 JL |
6649 | /* Interblock scheduling could have moved the original head insn from this |
6650 | block into a proceeding block. This may also cause schedule_block and | |
6651 | compute_forward_dependences to have different notions of what the | |
6652 | "head" insn was. | |
6653 | ||
6654 | If the interblock movement happened to make this block start with | |
6655 | some notes (LOOP, EH or SETJMP) before the first real insn, then | |
6656 | HEAD will have various special notes attached to it which must be | |
6657 | removed so that we don't end up with extra copies of the notes. */ | |
6658 | if (GET_RTX_CLASS (GET_CODE (head)) == 'i') | |
6659 | { | |
6660 | rtx note; | |
6661 | ||
6662 | for (note = REG_NOTES (head); note; note = XEXP (note, 1)) | |
6663 | if (REG_NOTE_KIND (note) == REG_DEAD | |
6664 | && GET_CODE (XEXP (note, 0)) == CONST_INT) | |
6665 | remove_note (head, note); | |
6666 | } | |
6667 | ||
8c660648 JL |
6668 | next_tail = NEXT_INSN (tail); |
6669 | prev_head = PREV_INSN (head); | |
6670 | ||
6671 | /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need | |
6672 | to schedule this block. */ | |
6673 | if (head == tail | |
6674 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6675 | return (sched_n_insns); | |
6676 | ||
6677 | /* debug info */ | |
6678 | if (sched_verbose) | |
6679 | { | |
6680 | fprintf (dump, ";; ======================================================\n"); | |
6681 | fprintf (dump, | |
6682 | ";; -- basic block %d from %d to %d -- %s reload\n", | |
3b413743 | 6683 | b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)), |
8c660648 JL |
6684 | (reload_completed ? "after" : "before")); |
6685 | fprintf (dump, ";; ======================================================\n"); | |
8c660648 JL |
6686 | fprintf (dump, "\n"); |
6687 | ||
6688 | visual_tbl = (char *) alloca (get_visual_tbl_length ()); | |
6689 | init_block_visualization (); | |
6690 | } | |
6691 | ||
6692 | /* remove remaining note insns from the block, save them in | |
6693 | note_list. These notes are restored at the end of | |
6694 | schedule_block (). */ | |
6695 | note_list = 0; | |
6696 | rm_other_notes (head, tail); | |
6697 | ||
6698 | target_bb = bb; | |
6699 | ||
6700 | /* prepare current target block info */ | |
6701 | if (current_nr_blocks > 1) | |
6702 | { | |
6703 | candidate_table = (candidate *) alloca (current_nr_blocks * sizeof (candidate)); | |
6704 | ||
6705 | bblst_last = 0; | |
6706 | /* ??? It is not clear why bblst_size is computed this way. The original | |
6707 | number was clearly too small as it resulted in compiler failures. | |
6708 | Multiplying by the original number by 2 (to account for update_bbs | |
6709 | members) seems to be a reasonable solution. */ | |
6710 | /* ??? Or perhaps there is a bug somewhere else in this file? */ | |
6711 | bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2; | |
6712 | bblst_table = (int *) alloca (bblst_size * sizeof (int)); | |
6713 | ||
6714 | bitlst_table_last = 0; | |
6715 | bitlst_table_size = rgn_nr_edges; | |
6716 | bitlst_table = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
6717 | ||
6718 | compute_trg_info (bb); | |
6719 | } | |
6720 | ||
6721 | clear_units (); | |
6722 | ||
6723 | /* Allocate the ready list */ | |
6724 | ready = (rtx *) alloca ((rgn_n_insns + 1) * sizeof (rtx)); | |
6725 | ||
6726 | /* Print debugging information. */ | |
6727 | if (sched_verbose >= 5) | |
6728 | debug_dependencies (); | |
6729 | ||
6730 | ||
6731 | /* Initialize ready list with all 'ready' insns in target block. | |
6732 | Count number of insns in the target block being scheduled. */ | |
6733 | n_ready = 0; | |
6734 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6735 | { | |
6736 | rtx next; | |
6737 | ||
6738 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6739 | continue; | |
6740 | next = NEXT_INSN (insn); | |
6741 | ||
6742 | if (INSN_DEP_COUNT (insn) == 0 | |
6743 | && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
6744 | ready[n_ready++] = insn; | |
6745 | if (!(SCHED_GROUP_P (insn))) | |
6746 | target_n_insns++; | |
6747 | } | |
6748 | ||
6749 | /* Add to ready list all 'ready' insns in valid source blocks. | |
6750 | For speculative insns, check-live, exception-free, and | |
6751 | issue-delay. */ | |
6752 | for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++) | |
6753 | if (IS_VALID (bb_src)) | |
6754 | { | |
6755 | rtx src_head; | |
6756 | rtx src_next_tail; | |
6757 | rtx tail, head; | |
6758 | ||
6759 | get_block_head_tail (bb_src, &head, &tail); | |
6760 | src_next_tail = NEXT_INSN (tail); | |
6761 | src_head = head; | |
6762 | ||
6763 | if (head == tail | |
6764 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6765 | continue; | |
6766 | ||
6767 | for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn)) | |
6768 | { | |
6769 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6770 | continue; | |
6771 | ||
6772 | if (!CANT_MOVE (insn) | |
6773 | && (!IS_SPECULATIVE_INSN (insn) | |
6774 | || (insn_issue_delay (insn) <= 3 | |
5835e573 | 6775 | && check_live (insn, bb_src) |
8c660648 JL |
6776 | && is_exception_free (insn, bb_src, target_bb)))) |
6777 | ||
6778 | { | |
6779 | rtx next; | |
6780 | ||
6781 | next = NEXT_INSN (insn); | |
6782 | if (INSN_DEP_COUNT (insn) == 0 | |
6783 | && (SCHED_GROUP_P (next) == 0 | |
6784 | || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
6785 | ready[n_ready++] = insn; | |
6786 | } | |
6787 | } | |
6788 | } | |
6789 | ||
e4da5f6d MM |
6790 | #ifdef MD_SCHED_INIT |
6791 | MD_SCHED_INIT (dump, sched_verbose); | |
6792 | #endif | |
6793 | ||
8c660648 JL |
6794 | /* no insns scheduled in this block yet */ |
6795 | last_scheduled_insn = 0; | |
6796 | ||
6797 | /* Sort the ready list */ | |
6798 | SCHED_SORT (ready, n_ready); | |
e4da5f6d MM |
6799 | #ifdef MD_SCHED_REORDER |
6800 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready); | |
6801 | #endif | |
8c660648 JL |
6802 | |
6803 | if (sched_verbose >= 2) | |
6804 | { | |
6d3352d9 | 6805 | fprintf (dump, ";;\t\tReady list initially: "); |
8c660648 JL |
6806 | debug_ready_list (ready, n_ready); |
6807 | } | |
6808 | ||
6809 | /* Q_SIZE is the total number of insns in the queue. */ | |
6810 | q_ptr = 0; | |
6811 | q_size = 0; | |
6812 | clock_var = 0; | |
4bdc8810 | 6813 | last_clock_var = 0; |
8c660648 JL |
6814 | bzero ((char *) insn_queue, sizeof (insn_queue)); |
6815 | ||
6816 | /* We start inserting insns after PREV_HEAD. */ | |
6817 | last = prev_head; | |
6818 | ||
6819 | /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */ | |
3b413743 | 6820 | new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b) |
8c660648 | 6821 | ? NEED_HEAD : NEED_NOTHING); |
3b413743 | 6822 | if (PREV_INSN (next_tail) == BLOCK_END (b)) |
8c660648 JL |
6823 | new_needs |= NEED_TAIL; |
6824 | ||
6825 | /* loop until all the insns in BB are scheduled. */ | |
6826 | while (sched_target_n_insns < target_n_insns) | |
6827 | { | |
6828 | int b1; | |
6829 | ||
8c660648 JL |
6830 | clock_var++; |
6831 | ||
6832 | /* Add to the ready list all pending insns that can be issued now. | |
6833 | If there are no ready insns, increment clock until one | |
6834 | is ready and add all pending insns at that point to the ready | |
6835 | list. */ | |
6836 | n_ready = queue_to_ready (ready, n_ready); | |
6837 | ||
6838 | if (n_ready == 0) | |
6839 | abort (); | |
6840 | ||
6841 | if (sched_verbose >= 2) | |
6842 | { | |
6843 | fprintf (dump, ";;\t\tReady list after queue_to_ready: "); | |
6844 | debug_ready_list (ready, n_ready); | |
6845 | } | |
6846 | ||
6847 | /* Sort the ready list. */ | |
6848 | SCHED_SORT (ready, n_ready); | |
e4da5f6d MM |
6849 | #ifdef MD_SCHED_REORDER |
6850 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready); | |
6851 | #endif | |
8c660648 JL |
6852 | |
6853 | if (sched_verbose) | |
6854 | { | |
47312d84 | 6855 | fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var); |
8c660648 JL |
6856 | debug_ready_list (ready, n_ready); |
6857 | } | |
6858 | ||
6859 | /* Issue insns from ready list. | |
6860 | It is important to count down from n_ready, because n_ready may change | |
6861 | as insns are issued. */ | |
6862 | can_issue_more = issue_rate; | |
6863 | for (i = n_ready - 1; i >= 0 && can_issue_more; i--) | |
6864 | { | |
6865 | rtx insn = ready[i]; | |
6866 | int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0); | |
6867 | ||
6868 | if (cost > 1) | |
6869 | { | |
6870 | queue_insn (insn, cost); | |
6871 | ready[i] = ready[--n_ready]; /* remove insn from ready list */ | |
6872 | } | |
6873 | else if (cost == 0) | |
6874 | { | |
8c660648 JL |
6875 | /* an interblock motion? */ |
6876 | if (INSN_BB (insn) != target_bb) | |
6877 | { | |
4f64eaca JL |
6878 | rtx temp; |
6879 | ||
8c660648 JL |
6880 | if (IS_SPECULATIVE_INSN (insn)) |
6881 | { | |
6882 | ||
5835e573 | 6883 | if (!check_live (insn, INSN_BB (insn))) |
8c660648 JL |
6884 | { |
6885 | /* speculative motion, live check failed, remove | |
6886 | insn from ready list */ | |
6887 | ready[i] = ready[--n_ready]; | |
6888 | continue; | |
6889 | } | |
5835e573 | 6890 | update_live (insn, INSN_BB (insn)); |
8c660648 JL |
6891 | |
6892 | /* for speculative load, mark insns fed by it. */ | |
6893 | if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn)) | |
6894 | set_spec_fed (insn); | |
6895 | ||
6896 | nr_spec++; | |
6897 | } | |
6898 | nr_inter++; | |
6899 | ||
4f64eaca JL |
6900 | temp = insn; |
6901 | while (SCHED_GROUP_P (temp)) | |
6902 | temp = PREV_INSN (temp); | |
6903 | ||
6904 | /* Update source block boundaries. */ | |
6905 | b1 = INSN_BLOCK (temp); | |
3b413743 RH |
6906 | if (temp == BLOCK_HEAD (b1) |
6907 | && insn == BLOCK_END (b1)) | |
8c660648 | 6908 | { |
4f64eaca JL |
6909 | /* We moved all the insns in the basic block. |
6910 | Emit a note after the last insn and update the | |
6911 | begin/end boundaries to point to the note. */ | |
6912 | emit_note_after (NOTE_INSN_DELETED, insn); | |
3b413743 RH |
6913 | BLOCK_END (b1) = NEXT_INSN (insn); |
6914 | BLOCK_HEAD (b1) = NEXT_INSN (insn); | |
8c660648 | 6915 | } |
3b413743 | 6916 | else if (insn == BLOCK_END (b1)) |
8c660648 | 6917 | { |
4f64eaca JL |
6918 | /* We took insns from the end of the basic block, |
6919 | so update the end of block boundary so that it | |
6920 | points to the first insn we did not move. */ | |
3b413743 | 6921 | BLOCK_END (b1) = PREV_INSN (temp); |
8c660648 | 6922 | } |
3b413743 | 6923 | else if (temp == BLOCK_HEAD (b1)) |
8c660648 | 6924 | { |
4f64eaca JL |
6925 | /* We took insns from the start of the basic block, |
6926 | so update the start of block boundary so that | |
6927 | it points to the first insn we did not move. */ | |
3b413743 | 6928 | BLOCK_HEAD (b1) = NEXT_INSN (insn); |
8c660648 JL |
6929 | } |
6930 | } | |
6931 | else | |
6932 | { | |
6933 | /* in block motion */ | |
6934 | sched_target_n_insns++; | |
6935 | } | |
6936 | ||
6937 | last_scheduled_insn = insn; | |
6938 | last = move_insn (insn, last); | |
6939 | sched_n_insns++; | |
6940 | ||
e4da5f6d MM |
6941 | #ifdef MD_SCHED_VARIABLE_ISSUE |
6942 | MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, can_issue_more); | |
6943 | #else | |
8c660648 | 6944 | can_issue_more--; |
e4da5f6d | 6945 | #endif |
8c660648 | 6946 | |
8c660648 JL |
6947 | n_ready = schedule_insn (insn, ready, n_ready, clock_var); |
6948 | ||
6949 | /* remove insn from ready list */ | |
6950 | ready[i] = ready[--n_ready]; | |
6951 | ||
6952 | /* close this block after scheduling its jump */ | |
6953 | if (GET_CODE (last_scheduled_insn) == JUMP_INSN) | |
6954 | break; | |
6955 | } | |
6956 | } | |
6957 | ||
6958 | /* debug info */ | |
6959 | if (sched_verbose) | |
6960 | { | |
6961 | visualize_scheduled_insns (b, clock_var); | |
8c660648 JL |
6962 | } |
6963 | } | |
6964 | ||
6965 | /* debug info */ | |
6966 | if (sched_verbose) | |
6967 | { | |
6968 | fprintf (dump, ";;\tReady list (final): "); | |
6969 | debug_ready_list (ready, n_ready); | |
6970 | print_block_visualization (b, ""); | |
6971 | } | |
6972 | ||
6973 | /* Sanity check -- queue must be empty now. Meaningless if region has | |
cc132865 | 6974 | multiple bbs. */ |
8c660648 | 6975 | if (current_nr_blocks > 1) |
cc132865 JL |
6976 | if (!flag_schedule_interblock && q_size != 0) |
6977 | abort (); | |
8c660648 JL |
6978 | |
6979 | /* update head/tail boundaries. */ | |
6980 | head = NEXT_INSN (prev_head); | |
6981 | tail = last; | |
6982 | ||
8c660648 JL |
6983 | /* Restore-other-notes: NOTE_LIST is the end of a chain of notes |
6984 | previously found among the insns. Insert them at the beginning | |
6985 | of the insns. */ | |
6986 | if (note_list != 0) | |
6987 | { | |
6988 | rtx note_head = note_list; | |
6989 | ||
6990 | while (PREV_INSN (note_head)) | |
6991 | { | |
6992 | note_head = PREV_INSN (note_head); | |
6993 | } | |
6994 | ||
6995 | PREV_INSN (note_head) = PREV_INSN (head); | |
6996 | NEXT_INSN (PREV_INSN (head)) = note_head; | |
6997 | PREV_INSN (head) = note_list; | |
6998 | NEXT_INSN (note_list) = head; | |
6999 | head = note_head; | |
7000 | } | |
7001 | ||
7002 | /* update target block boundaries. */ | |
7003 | if (new_needs & NEED_HEAD) | |
3b413743 | 7004 | BLOCK_HEAD (b) = head; |
8c660648 JL |
7005 | |
7006 | if (new_needs & NEED_TAIL) | |
3b413743 | 7007 | BLOCK_END (b) = tail; |
8c660648 JL |
7008 | |
7009 | /* debugging */ | |
7010 | if (sched_verbose) | |
7011 | { | |
7012 | fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n", | |
3b413743 | 7013 | clock_var, INSN_UID (BLOCK_HEAD (b))); |
8c660648 | 7014 | fprintf (dump, ";; new basic block end = %d\n\n", |
3b413743 | 7015 | INSN_UID (BLOCK_END (b))); |
8c660648 JL |
7016 | } |
7017 | ||
7018 | return (sched_n_insns); | |
7019 | } /* schedule_block () */ | |
7020 | \f | |
7021 | ||
7022 | /* print the bit-set of registers, S. callable from debugger */ | |
7023 | ||
7024 | extern void | |
7025 | debug_reg_vector (s) | |
7026 | regset s; | |
7027 | { | |
7028 | int regno; | |
7029 | ||
7030 | EXECUTE_IF_SET_IN_REG_SET (s, 0, regno, | |
7031 | { | |
7032 | fprintf (dump, " %d", regno); | |
7033 | }); | |
7034 | ||
7035 | fprintf (dump, "\n"); | |
7036 | } | |
7037 | ||
7038 | /* Use the backward dependences from LOG_LINKS to build | |
7039 | forward dependences in INSN_DEPEND. */ | |
7040 | ||
7041 | static void | |
7042 | compute_block_forward_dependences (bb) | |
7043 | int bb; | |
7044 | { | |
7045 | rtx insn, link; | |
7046 | rtx tail, head; | |
7047 | rtx next_tail; | |
7048 | enum reg_note dep_type; | |
7049 | ||
7050 | get_block_head_tail (bb, &head, &tail); | |
7051 | next_tail = NEXT_INSN (tail); | |
7052 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7053 | { | |
7054 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
7055 | continue; | |
7056 | ||
7057 | insn = group_leader (insn); | |
7058 | ||
7059 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
7060 | { | |
7061 | rtx x = group_leader (XEXP (link, 0)); | |
7062 | rtx new_link; | |
7063 | ||
7064 | if (x != XEXP (link, 0)) | |
7065 | continue; | |
7066 | ||
7067 | /* Ignore dependences upon deleted insn */ | |
7068 | if (GET_CODE (x) == NOTE || INSN_DELETED_P (x)) | |
7069 | continue; | |
7070 | if (find_insn_list (insn, INSN_DEPEND (x))) | |
7071 | continue; | |
7072 | ||
ebb7b10b | 7073 | new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x)); |
8c660648 JL |
7074 | |
7075 | dep_type = REG_NOTE_KIND (link); | |
7076 | PUT_REG_NOTE_KIND (new_link, dep_type); | |
7077 | ||
8c660648 JL |
7078 | INSN_DEPEND (x) = new_link; |
7079 | INSN_DEP_COUNT (insn) += 1; | |
7080 | } | |
7081 | } | |
7082 | } | |
7083 | ||
7084 | /* Initialize variables for region data dependence analysis. | |
7085 | n_bbs is the number of region blocks */ | |
7086 | ||
6d3352d9 | 7087 | __inline static void |
8c660648 JL |
7088 | init_rgn_data_dependences (n_bbs) |
7089 | int n_bbs; | |
7090 | { | |
7091 | int bb; | |
7092 | ||
7093 | /* variables for which one copy exists for each block */ | |
7094 | bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx)); | |
7095 | bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx)); | |
7096 | bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx)); | |
7097 | bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx)); | |
7098 | bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (rtx)); | |
7099 | bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx)); | |
7100 | bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx)); | |
7101 | bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx)); | |
7102 | ||
7103 | /* Create an insn here so that we can hang dependencies off of it later. */ | |
7104 | for (bb = 0; bb < n_bbs; bb++) | |
7105 | { | |
7106 | bb_sched_before_next_call[bb] = | |
38a448ca RH |
7107 | gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
7108 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
7109 | LOG_LINKS (bb_sched_before_next_call[bb]) = 0; |
7110 | } | |
7111 | } | |
7112 | ||
7113 | /* Add dependences so that branches are scheduled to run last in their block */ | |
7114 | ||
7115 | static void | |
7116 | add_branch_dependences (head, tail) | |
7117 | rtx head, tail; | |
7118 | { | |
7119 | ||
7120 | rtx insn, last; | |
7121 | ||
7122 | /* For all branches, calls, uses, and cc0 setters, force them to remain | |
7123 | in order at the end of the block by adding dependencies and giving | |
7124 | the last a high priority. There may be notes present, and prev_head | |
7125 | may also be a note. | |
7126 | ||
7127 | Branches must obviously remain at the end. Calls should remain at the | |
7128 | end since moving them results in worse register allocation. Uses remain | |
7129 | at the end to ensure proper register allocation. cc0 setters remaim | |
7130 | at the end because they can't be moved away from their cc0 user. */ | |
7131 | insn = tail; | |
7132 | last = 0; | |
7133 | while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
7134 | || (GET_CODE (insn) == INSN | |
7135 | && (GET_CODE (PATTERN (insn)) == USE | |
7136 | #ifdef HAVE_cc0 | |
7137 | || sets_cc0_p (PATTERN (insn)) | |
7138 | #endif | |
7139 | )) | |
7140 | || GET_CODE (insn) == NOTE) | |
7141 | { | |
7142 | if (GET_CODE (insn) != NOTE) | |
7143 | { | |
7144 | if (last != 0 | |
7145 | && !find_insn_list (insn, LOG_LINKS (last))) | |
7146 | { | |
7147 | add_dependence (last, insn, REG_DEP_ANTI); | |
7148 | INSN_REF_COUNT (insn)++; | |
7149 | } | |
7150 | ||
7151 | CANT_MOVE (insn) = 1; | |
7152 | ||
7153 | last = insn; | |
326ee7a3 JL |
7154 | /* Skip over insns that are part of a group. |
7155 | Make each insn explicitly depend on the previous insn. | |
7156 | This ensures that only the group header will ever enter | |
7157 | the ready queue (and, when scheduled, will automatically | |
7158 | schedule the SCHED_GROUP_P block). */ | |
8c660648 | 7159 | while (SCHED_GROUP_P (insn)) |
326ee7a3 JL |
7160 | { |
7161 | rtx temp = prev_nonnote_insn (insn); | |
7162 | add_dependence (insn, temp, REG_DEP_ANTI); | |
7163 | insn = temp; | |
7164 | } | |
8c660648 JL |
7165 | } |
7166 | ||
7167 | /* Don't overrun the bounds of the basic block. */ | |
7168 | if (insn == head) | |
7169 | break; | |
7170 | ||
7171 | insn = PREV_INSN (insn); | |
7172 | } | |
7173 | ||
7174 | /* make sure these insns are scheduled last in their block */ | |
7175 | insn = last; | |
7176 | if (insn != 0) | |
7177 | while (insn != head) | |
7178 | { | |
7179 | insn = prev_nonnote_insn (insn); | |
7180 | ||
7181 | if (INSN_REF_COUNT (insn) != 0) | |
7182 | continue; | |
7183 | ||
7184 | if (!find_insn_list (last, LOG_LINKS (insn))) | |
7185 | add_dependence (last, insn, REG_DEP_ANTI); | |
7186 | INSN_REF_COUNT (insn) = 1; | |
7187 | ||
7188 | /* Skip over insns that are part of a group. */ | |
7189 | while (SCHED_GROUP_P (insn)) | |
7190 | insn = prev_nonnote_insn (insn); | |
7191 | } | |
7192 | } | |
7193 | ||
7194 | /* Compute bacward dependences inside BB. In a multiple blocks region: | |
7195 | (1) a bb is analyzed after its predecessors, and (2) the lists in | |
7196 | effect at the end of bb (after analyzing for bb) are inherited by | |
7197 | bb's successrs. | |
7198 | ||
7199 | Specifically for reg-reg data dependences, the block insns are | |
7200 | scanned by sched_analyze () top-to-bottom. Two lists are | |
7201 | naintained by sched_analyze (): reg_last_defs[] for register DEFs, | |
7202 | and reg_last_uses[] for register USEs. | |
7203 | ||
7204 | When analysis is completed for bb, we update for its successors: | |
7205 | ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb]) | |
7206 | ; - USES[succ] = Union (USES [succ], DEFS [bb]) | |
7207 | ||
7208 | The mechanism for computing mem-mem data dependence is very | |
7209 | similar, and the result is interblock dependences in the region. */ | |
7210 | ||
7211 | static void | |
7212 | compute_block_backward_dependences (bb) | |
7213 | int bb; | |
7214 | { | |
7215 | int b; | |
7216 | rtx x; | |
7217 | rtx head, tail; | |
7218 | int max_reg = max_reg_num (); | |
7219 | ||
7220 | b = BB_TO_BLOCK (bb); | |
7221 | ||
7222 | if (current_nr_blocks == 1) | |
7223 | { | |
7224 | reg_last_uses = (rtx *) alloca (max_reg * sizeof (rtx)); | |
7225 | reg_last_sets = (rtx *) alloca (max_reg * sizeof (rtx)); | |
7226 | ||
7227 | bzero ((char *) reg_last_uses, max_reg * sizeof (rtx)); | |
7228 | bzero ((char *) reg_last_sets, max_reg * sizeof (rtx)); | |
7229 | ||
7230 | pending_read_insns = 0; | |
7231 | pending_read_mems = 0; | |
7232 | pending_write_insns = 0; | |
7233 | pending_write_mems = 0; | |
7234 | pending_lists_length = 0; | |
7235 | last_function_call = 0; | |
7236 | last_pending_memory_flush = 0; | |
7237 | sched_before_next_call | |
38a448ca RH |
7238 | = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
7239 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
7240 | LOG_LINKS (sched_before_next_call) = 0; |
7241 | } | |
7242 | else | |
7243 | { | |
7244 | reg_last_uses = bb_reg_last_uses[bb]; | |
7245 | reg_last_sets = bb_reg_last_sets[bb]; | |
7246 | ||
7247 | pending_read_insns = bb_pending_read_insns[bb]; | |
7248 | pending_read_mems = bb_pending_read_mems[bb]; | |
7249 | pending_write_insns = bb_pending_write_insns[bb]; | |
7250 | pending_write_mems = bb_pending_write_mems[bb]; | |
7251 | pending_lists_length = bb_pending_lists_length[bb]; | |
7252 | last_function_call = bb_last_function_call[bb]; | |
7253 | last_pending_memory_flush = bb_last_pending_memory_flush[bb]; | |
7254 | ||
7255 | sched_before_next_call = bb_sched_before_next_call[bb]; | |
7256 | } | |
7257 | ||
7258 | /* do the analysis for this block */ | |
7259 | get_block_head_tail (bb, &head, &tail); | |
7260 | sched_analyze (head, tail); | |
7261 | add_branch_dependences (head, tail); | |
7262 | ||
7263 | if (current_nr_blocks > 1) | |
7264 | { | |
7265 | int e, first_edge; | |
7266 | int b_succ, bb_succ; | |
7267 | int reg; | |
7268 | rtx link_insn, link_mem; | |
7269 | rtx u; | |
7270 | ||
7271 | /* these lists should point to the right place, for correct freeing later. */ | |
7272 | bb_pending_read_insns[bb] = pending_read_insns; | |
7273 | bb_pending_read_mems[bb] = pending_read_mems; | |
7274 | bb_pending_write_insns[bb] = pending_write_insns; | |
7275 | bb_pending_write_mems[bb] = pending_write_mems; | |
7276 | ||
7277 | /* bb's structures are inherited by it's successors */ | |
7278 | first_edge = e = OUT_EDGES (b); | |
7279 | if (e > 0) | |
7280 | do | |
7281 | { | |
7282 | b_succ = TO_BLOCK (e); | |
7283 | bb_succ = BLOCK_TO_BB (b_succ); | |
7284 | ||
7285 | /* only bbs "below" bb, in the same region, are interesting */ | |
7286 | if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ) | |
7287 | || bb_succ <= bb) | |
7288 | { | |
7289 | e = NEXT_OUT (e); | |
7290 | continue; | |
7291 | } | |
7292 | ||
7293 | for (reg = 0; reg < max_reg; reg++) | |
7294 | { | |
7295 | ||
7296 | /* reg-last-uses lists are inherited by bb_succ */ | |
7297 | for (u = reg_last_uses[reg]; u; u = XEXP (u, 1)) | |
7298 | { | |
7299 | if (find_insn_list (XEXP (u, 0), (bb_reg_last_uses[bb_succ])[reg])) | |
7300 | continue; | |
7301 | ||
7302 | (bb_reg_last_uses[bb_succ])[reg] | |
ebb7b10b RH |
7303 | = alloc_INSN_LIST (XEXP (u, 0), |
7304 | (bb_reg_last_uses[bb_succ])[reg]); | |
8c660648 JL |
7305 | } |
7306 | ||
7307 | /* reg-last-defs lists are inherited by bb_succ */ | |
7308 | for (u = reg_last_sets[reg]; u; u = XEXP (u, 1)) | |
7309 | { | |
7310 | if (find_insn_list (XEXP (u, 0), (bb_reg_last_sets[bb_succ])[reg])) | |
7311 | continue; | |
7312 | ||
7313 | (bb_reg_last_sets[bb_succ])[reg] | |
ebb7b10b RH |
7314 | = alloc_INSN_LIST (XEXP (u, 0), |
7315 | (bb_reg_last_sets[bb_succ])[reg]); | |
8c660648 JL |
7316 | } |
7317 | } | |
7318 | ||
7319 | /* mem read/write lists are inherited by bb_succ */ | |
7320 | link_insn = pending_read_insns; | |
7321 | link_mem = pending_read_mems; | |
7322 | while (link_insn) | |
7323 | { | |
7324 | if (!(find_insn_mem_list (XEXP (link_insn, 0), XEXP (link_mem, 0), | |
7325 | bb_pending_read_insns[bb_succ], | |
7326 | bb_pending_read_mems[bb_succ]))) | |
7327 | add_insn_mem_dependence (&bb_pending_read_insns[bb_succ], | |
7328 | &bb_pending_read_mems[bb_succ], | |
7329 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
7330 | link_insn = XEXP (link_insn, 1); | |
7331 | link_mem = XEXP (link_mem, 1); | |
7332 | } | |
7333 | ||
7334 | link_insn = pending_write_insns; | |
7335 | link_mem = pending_write_mems; | |
7336 | while (link_insn) | |
7337 | { | |
7338 | if (!(find_insn_mem_list (XEXP (link_insn, 0), XEXP (link_mem, 0), | |
7339 | bb_pending_write_insns[bb_succ], | |
7340 | bb_pending_write_mems[bb_succ]))) | |
7341 | add_insn_mem_dependence (&bb_pending_write_insns[bb_succ], | |
7342 | &bb_pending_write_mems[bb_succ], | |
7343 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
7344 | ||
7345 | link_insn = XEXP (link_insn, 1); | |
7346 | link_mem = XEXP (link_mem, 1); | |
7347 | } | |
7348 | ||
7349 | /* last_function_call is inherited by bb_succ */ | |
7350 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
7351 | { | |
7352 | if (find_insn_list (XEXP (u, 0), bb_last_function_call[bb_succ])) | |
7353 | continue; | |
7354 | ||
7355 | bb_last_function_call[bb_succ] | |
ebb7b10b RH |
7356 | = alloc_INSN_LIST (XEXP (u, 0), |
7357 | bb_last_function_call[bb_succ]); | |
8c660648 JL |
7358 | } |
7359 | ||
7360 | /* last_pending_memory_flush is inherited by bb_succ */ | |
7361 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
7362 | { | |
7363 | if (find_insn_list (XEXP (u, 0), bb_last_pending_memory_flush[bb_succ])) | |
7364 | continue; | |
7365 | ||
7366 | bb_last_pending_memory_flush[bb_succ] | |
ebb7b10b RH |
7367 | = alloc_INSN_LIST (XEXP (u, 0), |
7368 | bb_last_pending_memory_flush[bb_succ]); | |
8c660648 JL |
7369 | } |
7370 | ||
7371 | /* sched_before_next_call is inherited by bb_succ */ | |
7372 | x = LOG_LINKS (sched_before_next_call); | |
7373 | for (; x; x = XEXP (x, 1)) | |
7374 | add_dependence (bb_sched_before_next_call[bb_succ], | |
7375 | XEXP (x, 0), REG_DEP_ANTI); | |
7376 | ||
7377 | e = NEXT_OUT (e); | |
7378 | } | |
7379 | while (e != first_edge); | |
7380 | } | |
ebb7b10b | 7381 | |
7eea6443 JL |
7382 | /* Free up the INSN_LISTs |
7383 | ||
7384 | Note this loop is executed max_reg * nr_regions times. It's first | |
7385 | implementation accounted for over 90% of the calls to free_list. | |
7386 | The list was empty for the vast majority of those calls. On the PA, | |
7387 | not calling free_list in those cases improves -O2 compile times by | |
7388 | 3-5% on average. */ | |
ebb7b10b RH |
7389 | for (b = 0; b < max_reg; ++b) |
7390 | { | |
7eea6443 JL |
7391 | if (reg_last_sets[b]) |
7392 | free_list (®_last_sets[b], &unused_insn_list); | |
7393 | if (reg_last_uses[b]) | |
7394 | free_list (®_last_uses[b], &unused_insn_list); | |
ebb7b10b RH |
7395 | } |
7396 | ||
7397 | /* Assert that we won't need bb_reg_last_* for this block anymore. */ | |
7398 | if (current_nr_blocks > 1) | |
7399 | { | |
7400 | bb_reg_last_uses[bb] = (rtx *) NULL_RTX; | |
7401 | bb_reg_last_sets[bb] = (rtx *) NULL_RTX; | |
7402 | } | |
8c660648 JL |
7403 | } |
7404 | ||
7405 | /* Print dependences for debugging, callable from debugger */ | |
7406 | ||
7407 | void | |
7408 | debug_dependencies () | |
7409 | { | |
7410 | int bb; | |
7411 | ||
7412 | fprintf (dump, ";; --------------- forward dependences: ------------ \n"); | |
7413 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7414 | { | |
7415 | if (1) | |
7416 | { | |
7417 | rtx head, tail; | |
7418 | rtx next_tail; | |
7419 | rtx insn; | |
7420 | ||
7421 | get_block_head_tail (bb, &head, &tail); | |
7422 | next_tail = NEXT_INSN (tail); | |
7423 | fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n", | |
7424 | BB_TO_BLOCK (bb), bb); | |
7425 | ||
7426 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
7427 | "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units"); | |
7428 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
7429 | "----", "----", "--", "---", "----", "----", "--------", "-----"); | |
7430 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7431 | { | |
7432 | rtx link; | |
7433 | int unit, range; | |
7434 | ||
7435 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
7436 | { | |
7437 | int n; | |
7438 | fprintf (dump, ";; %6d ", INSN_UID (insn)); | |
7439 | if (GET_CODE (insn) == NOTE) | |
ebc25a17 MM |
7440 | { |
7441 | n = NOTE_LINE_NUMBER (insn); | |
7442 | if (n < 0) | |
7443 | fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n)); | |
7444 | else | |
7445 | fprintf (dump, "line %d, file %s\n", n, | |
7446 | NOTE_SOURCE_FILE (insn)); | |
7447 | } | |
7448 | else | |
4f64eaca | 7449 | fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn))); |
8c660648 JL |
7450 | continue; |
7451 | } | |
7452 | ||
7453 | unit = insn_unit (insn); | |
7454 | range = (unit < 0 | |
7455 | || function_units[unit].blockage_range_function == 0) ? 0 : | |
7456 | function_units[unit].blockage_range_function (insn); | |
7457 | fprintf (dump, | |
7458 | ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ", | |
7459 | (SCHED_GROUP_P (insn) ? "+" : " "), | |
7460 | INSN_UID (insn), | |
7461 | INSN_CODE (insn), | |
7462 | INSN_BB (insn), | |
7463 | INSN_DEP_COUNT (insn), | |
7464 | INSN_PRIORITY (insn), | |
7465 | insn_cost (insn, 0, 0), | |
7466 | (int) MIN_BLOCKAGE_COST (range), | |
7467 | (int) MAX_BLOCKAGE_COST (range)); | |
7468 | insn_print_units (insn); | |
7469 | fprintf (dump, "\t: "); | |
7470 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
7471 | fprintf (dump, "%d ", INSN_UID (XEXP (link, 0))); | |
7472 | fprintf (dump, "\n"); | |
7473 | } | |
7474 | } | |
7475 | } | |
7476 | fprintf (dump, "\n"); | |
7477 | } | |
7478 | ||
7479 | /* Set_priorities: compute priority of each insn in the block */ | |
7480 | ||
7481 | static int | |
7482 | set_priorities (bb) | |
7483 | int bb; | |
7484 | { | |
7485 | rtx insn; | |
7486 | int n_insn; | |
7487 | ||
7488 | rtx tail; | |
7489 | rtx prev_head; | |
7490 | rtx head; | |
7491 | ||
7492 | get_block_head_tail (bb, &head, &tail); | |
7493 | prev_head = PREV_INSN (head); | |
7494 | ||
7495 | if (head == tail | |
7496 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
7497 | return 0; | |
7498 | ||
7499 | n_insn = 0; | |
7500 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
7501 | { | |
7502 | ||
7503 | if (GET_CODE (insn) == NOTE) | |
7504 | continue; | |
7505 | ||
7506 | if (!(SCHED_GROUP_P (insn))) | |
7507 | n_insn++; | |
7508 | (void) priority (insn); | |
7509 | } | |
7510 | ||
7511 | return n_insn; | |
7512 | } | |
7513 | ||
7514 | /* Make each element of VECTOR point at an rtx-vector, | |
7515 | taking the space for all those rtx-vectors from SPACE. | |
7516 | SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors. | |
7517 | BYTES_PER_ELT is the number of bytes in one rtx-vector. | |
7518 | (this is the same as init_regset_vector () in flow.c) */ | |
7519 | ||
7520 | static void | |
7521 | init_rtx_vector (vector, space, nelts, bytes_per_elt) | |
7522 | rtx **vector; | |
7523 | rtx *space; | |
7524 | int nelts; | |
7525 | int bytes_per_elt; | |
7526 | { | |
7527 | register int i; | |
7528 | register rtx *p = space; | |
7529 | ||
7530 | for (i = 0; i < nelts; i++) | |
7531 | { | |
7532 | vector[i] = p; | |
7533 | p += bytes_per_elt / sizeof (*p); | |
7534 | } | |
7535 | } | |
7536 | ||
7537 | /* Schedule a region. A region is either an inner loop, a loop-free | |
7538 | subroutine, or a single basic block. Each bb in the region is | |
7539 | scheduled after its flow predecessors. */ | |
7540 | ||
7541 | static void | |
7542 | schedule_region (rgn) | |
7543 | int rgn; | |
7544 | { | |
7545 | int bb; | |
7546 | int rgn_n_insns = 0; | |
7547 | int sched_rgn_n_insns = 0; | |
7548 | ||
7549 | /* set variables for the current region */ | |
7550 | current_nr_blocks = RGN_NR_BLOCKS (rgn); | |
7551 | current_blocks = RGN_BLOCKS (rgn); | |
7552 | ||
7553 | reg_pending_sets = ALLOCA_REG_SET (); | |
7554 | reg_pending_sets_all = 0; | |
7555 | ||
7556 | /* initializations for region data dependence analyisis */ | |
7557 | if (current_nr_blocks > 1) | |
7558 | { | |
7559 | rtx *space; | |
7560 | int maxreg = max_reg_num (); | |
7561 | ||
7562 | bb_reg_last_uses = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7563 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7564 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
7565 | init_rtx_vector (bb_reg_last_uses, space, current_nr_blocks, maxreg * sizeof (rtx *)); | |
7566 | ||
7567 | bb_reg_last_sets = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7568 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7569 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
7570 | init_rtx_vector (bb_reg_last_sets, space, current_nr_blocks, maxreg * sizeof (rtx *)); | |
7571 | ||
7572 | bb_pending_read_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7573 | bb_pending_read_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7574 | bb_pending_write_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7575 | bb_pending_write_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7576 | bb_pending_lists_length = (int *) alloca (current_nr_blocks * sizeof (int)); | |
7577 | bb_last_pending_memory_flush = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7578 | bb_last_function_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7579 | bb_sched_before_next_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7580 | ||
7581 | init_rgn_data_dependences (current_nr_blocks); | |
7582 | } | |
7583 | ||
7584 | /* compute LOG_LINKS */ | |
7585 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7586 | compute_block_backward_dependences (bb); | |
7587 | ||
7588 | /* compute INSN_DEPEND */ | |
7589 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) | |
7590 | compute_block_forward_dependences (bb); | |
7591 | ||
7592 | /* Delete line notes, compute live-regs at block end, and set priorities. */ | |
7593 | dead_notes = 0; | |
7594 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7595 | { | |
7596 | if (reload_completed == 0) | |
7597 | find_pre_sched_live (bb); | |
7598 | ||
7599 | if (write_symbols != NO_DEBUG) | |
7600 | { | |
7601 | save_line_notes (bb); | |
7602 | rm_line_notes (bb); | |
7603 | } | |
7604 | ||
7605 | rgn_n_insns += set_priorities (bb); | |
7606 | } | |
7607 | ||
7608 | /* compute interblock info: probabilities, split-edges, dominators, etc. */ | |
7609 | if (current_nr_blocks > 1) | |
7610 | { | |
7611 | int i; | |
7612 | ||
7613 | prob = (float *) alloca ((current_nr_blocks) * sizeof (float)); | |
7614 | ||
7615 | bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1; | |
7616 | dom = (bbset *) alloca (current_nr_blocks * sizeof (bbset)); | |
7617 | for (i = 0; i < current_nr_blocks; i++) | |
7618 | { | |
7619 | dom[i] = (bbset) alloca (bbset_size * sizeof (HOST_WIDE_INT)); | |
7620 | bzero ((char *) dom[i], bbset_size * sizeof (HOST_WIDE_INT)); | |
7621 | } | |
7622 | ||
7623 | /* edge to bit */ | |
7624 | rgn_nr_edges = 0; | |
7625 | edge_to_bit = (int *) alloca (nr_edges * sizeof (int)); | |
7626 | for (i = 1; i < nr_edges; i++) | |
7627 | if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn) | |
7628 | EDGE_TO_BIT (i) = rgn_nr_edges++; | |
7629 | rgn_edges = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
7630 | ||
7631 | rgn_nr_edges = 0; | |
7632 | for (i = 1; i < nr_edges; i++) | |
7633 | if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn)) | |
7634 | rgn_edges[rgn_nr_edges++] = i; | |
7635 | ||
7636 | /* split edges */ | |
7637 | edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1; | |
7638 | pot_split = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset)); | |
7639 | ancestor_edges = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset)); | |
7640 | for (i = 0; i < current_nr_blocks; i++) | |
7641 | { | |
7642 | pot_split[i] = | |
7643 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
7644 | bzero ((char *) pot_split[i], | |
7645 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
7646 | ancestor_edges[i] = | |
7647 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
7648 | bzero ((char *) ancestor_edges[i], | |
7649 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
7650 | } | |
7651 | ||
7652 | /* compute probabilities, dominators, split_edges */ | |
7653 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7654 | compute_dom_prob_ps (bb); | |
7655 | } | |
7656 | ||
7657 | /* now we can schedule all blocks */ | |
7658 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7659 | { | |
5835e573 | 7660 | sched_rgn_n_insns += schedule_block (bb, rgn_n_insns); |
8c660648 JL |
7661 | |
7662 | #ifdef USE_C_ALLOCA | |
7663 | alloca (0); | |
7664 | #endif | |
7665 | } | |
7666 | ||
cc132865 JL |
7667 | /* sanity check: verify that all region insns were scheduled */ |
7668 | if (sched_rgn_n_insns != rgn_n_insns) | |
7669 | abort (); | |
8c660648 JL |
7670 | |
7671 | /* update register life and usage information */ | |
7672 | if (reload_completed == 0) | |
7673 | { | |
7674 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) | |
7675 | find_post_sched_live (bb); | |
7676 | ||
7677 | if (current_nr_blocks <= 1) | |
7678 | /* Sanity check. There should be no REG_DEAD notes leftover at the end. | |
7679 | In practice, this can occur as the result of bugs in flow, combine.c, | |
7680 | and/or sched.c. The values of the REG_DEAD notes remaining are | |
7681 | meaningless, because dead_notes is just used as a free list. */ | |
7682 | if (dead_notes != 0) | |
7683 | abort (); | |
7684 | } | |
7685 | ||
7686 | /* restore line notes. */ | |
7687 | if (write_symbols != NO_DEBUG) | |
7688 | { | |
7689 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7690 | restore_line_notes (bb); | |
7691 | } | |
7692 | ||
7693 | /* Done with this region */ | |
7694 | free_pending_lists (); | |
f187056f JL |
7695 | |
7696 | FREE_REG_SET (reg_pending_sets); | |
8c660648 JL |
7697 | } |
7698 | ||
8c660648 JL |
7699 | /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are |
7700 | needed for the hard register mentioned in the note. This can happen | |
7701 | if the reference to the hard register in the original insn was split into | |
7702 | several smaller hard register references in the split insns. */ | |
7703 | ||
7704 | static void | |
5835e573 KG |
7705 | split_hard_reg_notes (note, first, last) |
7706 | rtx note, first, last; | |
8c660648 JL |
7707 | { |
7708 | rtx reg, temp, link; | |
7709 | int n_regs, i, new_reg; | |
7710 | rtx insn; | |
7711 | ||
7712 | /* Assume that this is a REG_DEAD note. */ | |
7713 | if (REG_NOTE_KIND (note) != REG_DEAD) | |
7714 | abort (); | |
7715 | ||
7716 | reg = XEXP (note, 0); | |
7717 | ||
7718 | n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); | |
7719 | ||
7720 | for (i = 0; i < n_regs; i++) | |
7721 | { | |
7722 | new_reg = REGNO (reg) + i; | |
7723 | ||
7724 | /* Check for references to new_reg in the split insns. */ | |
7725 | for (insn = last;; insn = PREV_INSN (insn)) | |
7726 | { | |
7727 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
7728 | && (temp = regno_use_in (new_reg, PATTERN (insn)))) | |
7729 | { | |
7730 | /* Create a new reg dead note ere. */ | |
ebb7b10b | 7731 | link = alloc_EXPR_LIST (REG_DEAD, temp, REG_NOTES (insn)); |
8c660648 JL |
7732 | REG_NOTES (insn) = link; |
7733 | ||
7734 | /* If killed multiple registers here, then add in the excess. */ | |
7735 | i += HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) - 1; | |
7736 | ||
7737 | break; | |
7738 | } | |
7739 | /* It isn't mentioned anywhere, so no new reg note is needed for | |
7740 | this register. */ | |
7741 | if (insn == first) | |
7742 | break; | |
7743 | } | |
7744 | } | |
7745 | } | |
7746 | ||
7747 | /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an | |
7748 | insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */ | |
7749 | ||
7750 | static void | |
7751 | new_insn_dead_notes (pat, insn, last, orig_insn) | |
7752 | rtx pat, insn, last, orig_insn; | |
7753 | { | |
7754 | rtx dest, tem, set; | |
7755 | ||
7756 | /* PAT is either a CLOBBER or a SET here. */ | |
7757 | dest = XEXP (pat, 0); | |
7758 | ||
7759 | while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG | |
7760 | || GET_CODE (dest) == STRICT_LOW_PART | |
7761 | || GET_CODE (dest) == SIGN_EXTRACT) | |
7762 | dest = XEXP (dest, 0); | |
7763 | ||
7764 | if (GET_CODE (dest) == REG) | |
7765 | { | |
93da030f R |
7766 | /* If the original insn already used this register, we may not add new |
7767 | notes for it. One example for a split that needs this test is | |
7768 | when a multi-word memory access with register-indirect addressing | |
7769 | is split into multiple memory accesses with auto-increment and | |
7770 | one adjusting add instruction for the address register. */ | |
7771 | if (reg_referenced_p (dest, PATTERN (orig_insn))) | |
7772 | return; | |
8c660648 JL |
7773 | for (tem = last; tem != insn; tem = PREV_INSN (tem)) |
7774 | { | |
7775 | if (GET_RTX_CLASS (GET_CODE (tem)) == 'i' | |
7776 | && reg_overlap_mentioned_p (dest, PATTERN (tem)) | |
7777 | && (set = single_set (tem))) | |
7778 | { | |
7779 | rtx tem_dest = SET_DEST (set); | |
7780 | ||
7781 | while (GET_CODE (tem_dest) == ZERO_EXTRACT | |
7782 | || GET_CODE (tem_dest) == SUBREG | |
7783 | || GET_CODE (tem_dest) == STRICT_LOW_PART | |
7784 | || GET_CODE (tem_dest) == SIGN_EXTRACT) | |
7785 | tem_dest = XEXP (tem_dest, 0); | |
7786 | ||
7787 | if (!rtx_equal_p (tem_dest, dest)) | |
7788 | { | |
7789 | /* Use the same scheme as combine.c, don't put both REG_DEAD | |
7790 | and REG_UNUSED notes on the same insn. */ | |
7791 | if (!find_regno_note (tem, REG_UNUSED, REGNO (dest)) | |
7792 | && !find_regno_note (tem, REG_DEAD, REGNO (dest))) | |
7793 | { | |
ebb7b10b RH |
7794 | rtx note = alloc_EXPR_LIST (REG_DEAD, dest, |
7795 | REG_NOTES (tem)); | |
8c660648 JL |
7796 | REG_NOTES (tem) = note; |
7797 | } | |
7798 | /* The reg only dies in one insn, the last one that uses | |
7799 | it. */ | |
7800 | break; | |
7801 | } | |
7802 | else if (reg_overlap_mentioned_p (dest, SET_SRC (set))) | |
7803 | /* We found an instruction that both uses the register, | |
7804 | and sets it, so no new REG_NOTE is needed for this set. */ | |
7805 | break; | |
7806 | } | |
7807 | } | |
7808 | /* If this is a set, it must die somewhere, unless it is the dest of | |
7809 | the original insn, and hence is live after the original insn. Abort | |
7810 | if it isn't supposed to be live after the original insn. | |
7811 | ||
7812 | If this is a clobber, then just add a REG_UNUSED note. */ | |
7813 | if (tem == insn) | |
7814 | { | |
7815 | int live_after_orig_insn = 0; | |
7816 | rtx pattern = PATTERN (orig_insn); | |
7817 | int i; | |
7818 | ||
7819 | if (GET_CODE (pat) == CLOBBER) | |
7820 | { | |
ebb7b10b | 7821 | rtx note = alloc_EXPR_LIST (REG_UNUSED, dest, REG_NOTES (insn)); |
8c660648 JL |
7822 | REG_NOTES (insn) = note; |
7823 | return; | |
7824 | } | |
7825 | ||
7826 | /* The original insn could have multiple sets, so search the | |
7827 | insn for all sets. */ | |
7828 | if (GET_CODE (pattern) == SET) | |
7829 | { | |
7830 | if (reg_overlap_mentioned_p (dest, SET_DEST (pattern))) | |
7831 | live_after_orig_insn = 1; | |
7832 | } | |
7833 | else if (GET_CODE (pattern) == PARALLEL) | |
7834 | { | |
7835 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
7836 | if (GET_CODE (XVECEXP (pattern, 0, i)) == SET | |
7837 | && reg_overlap_mentioned_p (dest, | |
7838 | SET_DEST (XVECEXP (pattern, | |
7839 | 0, i)))) | |
7840 | live_after_orig_insn = 1; | |
7841 | } | |
7842 | ||
7843 | if (!live_after_orig_insn) | |
7844 | abort (); | |
7845 | } | |
7846 | } | |
7847 | } | |
7848 | ||
7849 | /* Subroutine of update_flow_info. Update the value of reg_n_sets for all | |
7850 | registers modified by X. INC is -1 if the containing insn is being deleted, | |
7851 | and is 1 if the containing insn is a newly generated insn. */ | |
7852 | ||
7853 | static void | |
7854 | update_n_sets (x, inc) | |
7855 | rtx x; | |
7856 | int inc; | |
7857 | { | |
7858 | rtx dest = SET_DEST (x); | |
7859 | ||
7860 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG | |
7861 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
7862 | dest = SUBREG_REG (dest); | |
7863 | ||
7864 | if (GET_CODE (dest) == REG) | |
7865 | { | |
7866 | int regno = REGNO (dest); | |
7867 | ||
7868 | if (regno < FIRST_PSEUDO_REGISTER) | |
7869 | { | |
7870 | register int i; | |
7871 | int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
7872 | ||
7873 | for (i = regno; i < endregno; i++) | |
7874 | REG_N_SETS (i) += inc; | |
7875 | } | |
7876 | else | |
7877 | REG_N_SETS (regno) += inc; | |
7878 | } | |
7879 | } | |
7880 | ||
7881 | /* Updates all flow-analysis related quantities (including REG_NOTES) for | |
7882 | the insns from FIRST to LAST inclusive that were created by splitting | |
7883 | ORIG_INSN. NOTES are the original REG_NOTES. */ | |
7884 | ||
ca545bb5 | 7885 | void |
8c660648 JL |
7886 | update_flow_info (notes, first, last, orig_insn) |
7887 | rtx notes; | |
7888 | rtx first, last; | |
7889 | rtx orig_insn; | |
7890 | { | |
7891 | rtx insn, note; | |
7892 | rtx next; | |
7893 | rtx orig_dest, temp; | |
7894 | rtx set; | |
7895 | ||
7896 | /* Get and save the destination set by the original insn. */ | |
7897 | ||
7898 | orig_dest = single_set (orig_insn); | |
7899 | if (orig_dest) | |
7900 | orig_dest = SET_DEST (orig_dest); | |
7901 | ||
7902 | /* Move REG_NOTES from the original insn to where they now belong. */ | |
7903 | ||
7904 | for (note = notes; note; note = next) | |
7905 | { | |
7906 | next = XEXP (note, 1); | |
7907 | switch (REG_NOTE_KIND (note)) | |
7908 | { | |
7909 | case REG_DEAD: | |
7910 | case REG_UNUSED: | |
7911 | /* Move these notes from the original insn to the last new insn where | |
7912 | the register is now set. */ | |
7913 | ||
7914 | for (insn = last;; insn = PREV_INSN (insn)) | |
7915 | { | |
7916 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
7917 | && reg_mentioned_p (XEXP (note, 0), PATTERN (insn))) | |
7918 | { | |
7919 | /* If this note refers to a multiple word hard register, it | |
7920 | may have been split into several smaller hard register | |
7921 | references, so handle it specially. */ | |
7922 | temp = XEXP (note, 0); | |
7923 | if (REG_NOTE_KIND (note) == REG_DEAD | |
7924 | && GET_CODE (temp) == REG | |
7925 | && REGNO (temp) < FIRST_PSEUDO_REGISTER | |
7926 | && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) > 1) | |
5835e573 | 7927 | split_hard_reg_notes (note, first, last); |
8c660648 JL |
7928 | else |
7929 | { | |
7930 | XEXP (note, 1) = REG_NOTES (insn); | |
7931 | REG_NOTES (insn) = note; | |
7932 | } | |
7933 | ||
7934 | /* Sometimes need to convert REG_UNUSED notes to REG_DEAD | |
7935 | notes. */ | |
7936 | /* ??? This won't handle multiple word registers correctly, | |
7937 | but should be good enough for now. */ | |
7938 | if (REG_NOTE_KIND (note) == REG_UNUSED | |
272299b9 | 7939 | && GET_CODE (XEXP (note, 0)) != SCRATCH |
8c660648 JL |
7940 | && !dead_or_set_p (insn, XEXP (note, 0))) |
7941 | PUT_REG_NOTE_KIND (note, REG_DEAD); | |
7942 | ||
7943 | /* The reg only dies in one insn, the last one that uses | |
7944 | it. */ | |
7945 | break; | |
7946 | } | |
7947 | /* It must die somewhere, fail it we couldn't find where it died. | |
7948 | ||
7949 | If this is a REG_UNUSED note, then it must be a temporary | |
7950 | register that was not needed by this instantiation of the | |
7951 | pattern, so we can safely ignore it. */ | |
7952 | if (insn == first) | |
a1ef0af4 | 7953 | { |
8c660648 JL |
7954 | if (REG_NOTE_KIND (note) != REG_UNUSED) |
7955 | abort (); | |
7956 | ||
7957 | break; | |
7958 | } | |
7959 | } | |
7960 | break; | |
7961 | ||
7962 | case REG_WAS_0: | |
fcdc0d6e R |
7963 | /* If the insn that set the register to 0 was deleted, this |
7964 | note cannot be relied on any longer. The destination might | |
7965 | even have been moved to memory. | |
7966 | This was observed for SH4 with execute/920501-6.c compilation, | |
7967 | -O2 -fomit-frame-pointer -finline-functions . */ | |
7968 | if (GET_CODE (XEXP (note, 0)) == NOTE | |
7969 | || INSN_DELETED_P (XEXP (note, 0))) | |
7970 | break; | |
8c660648 JL |
7971 | /* This note applies to the dest of the original insn. Find the |
7972 | first new insn that now has the same dest, and move the note | |
7973 | there. */ | |
7974 | ||
7975 | if (!orig_dest) | |
7976 | abort (); | |
7977 | ||
7978 | for (insn = first;; insn = NEXT_INSN (insn)) | |
7979 | { | |
7980 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
7981 | && (temp = single_set (insn)) | |
7982 | && rtx_equal_p (SET_DEST (temp), orig_dest)) | |
7983 | { | |
7984 | XEXP (note, 1) = REG_NOTES (insn); | |
7985 | REG_NOTES (insn) = note; | |
7986 | /* The reg is only zero before one insn, the first that | |
7987 | uses it. */ | |
7988 | break; | |
7989 | } | |
7990 | /* If this note refers to a multiple word hard | |
7991 | register, it may have been split into several smaller | |
7992 | hard register references. We could split the notes, | |
7993 | but simply dropping them is good enough. */ | |
7994 | if (GET_CODE (orig_dest) == REG | |
7995 | && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER | |
7996 | && HARD_REGNO_NREGS (REGNO (orig_dest), | |
7997 | GET_MODE (orig_dest)) > 1) | |
7998 | break; | |
7999 | /* It must be set somewhere, fail if we couldn't find where it | |
8000 | was set. */ | |
8001 | if (insn == last) | |
8002 | abort (); | |
8003 | } | |
8004 | break; | |
8005 | ||
8006 | case REG_EQUAL: | |
8007 | case REG_EQUIV: | |
8008 | /* A REG_EQUIV or REG_EQUAL note on an insn with more than one | |
8009 | set is meaningless. Just drop the note. */ | |
8010 | if (!orig_dest) | |
8011 | break; | |
8012 | ||
8013 | case REG_NO_CONFLICT: | |
8014 | /* These notes apply to the dest of the original insn. Find the last | |
8015 | new insn that now has the same dest, and move the note there. */ | |
8016 | ||
8017 | if (!orig_dest) | |
8018 | abort (); | |
8019 | ||
8020 | for (insn = last;; insn = PREV_INSN (insn)) | |
8021 | { | |
8022 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
8023 | && (temp = single_set (insn)) | |
8024 | && rtx_equal_p (SET_DEST (temp), orig_dest)) | |
8025 | { | |
8026 | XEXP (note, 1) = REG_NOTES (insn); | |
8027 | REG_NOTES (insn) = note; | |
8028 | /* Only put this note on one of the new insns. */ | |
8029 | break; | |
8030 | } | |
8031 | ||
8032 | /* The original dest must still be set someplace. Abort if we | |
8033 | couldn't find it. */ | |
8034 | if (insn == first) | |
8035 | { | |
8036 | /* However, if this note refers to a multiple word hard | |
8037 | register, it may have been split into several smaller | |
8038 | hard register references. We could split the notes, | |
8039 | but simply dropping them is good enough. */ | |
8040 | if (GET_CODE (orig_dest) == REG | |
8041 | && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER | |
8042 | && HARD_REGNO_NREGS (REGNO (orig_dest), | |
8043 | GET_MODE (orig_dest)) > 1) | |
8044 | break; | |
8045 | /* Likewise for multi-word memory references. */ | |
8046 | if (GET_CODE (orig_dest) == MEM | |
9ae4ec46 | 8047 | && SIZE_FOR_MODE (orig_dest) > UNITS_PER_WORD) |
8c660648 JL |
8048 | break; |
8049 | abort (); | |
8050 | } | |
8051 | } | |
8052 | break; | |
8053 | ||
8054 | case REG_LIBCALL: | |
8055 | /* Move a REG_LIBCALL note to the first insn created, and update | |
8056 | the corresponding REG_RETVAL note. */ | |
8057 | XEXP (note, 1) = REG_NOTES (first); | |
8058 | REG_NOTES (first) = note; | |
8059 | ||
8060 | insn = XEXP (note, 0); | |
8061 | note = find_reg_note (insn, REG_RETVAL, NULL_RTX); | |
8062 | if (note) | |
8063 | XEXP (note, 0) = first; | |
8064 | break; | |
8065 | ||
8066 | case REG_EXEC_COUNT: | |
8067 | /* Move a REG_EXEC_COUNT note to the first insn created. */ | |
8068 | XEXP (note, 1) = REG_NOTES (first); | |
8069 | REG_NOTES (first) = note; | |
8070 | break; | |
8071 | ||
8072 | case REG_RETVAL: | |
8073 | /* Move a REG_RETVAL note to the last insn created, and update | |
8074 | the corresponding REG_LIBCALL note. */ | |
8075 | XEXP (note, 1) = REG_NOTES (last); | |
8076 | REG_NOTES (last) = note; | |
8077 | ||
8078 | insn = XEXP (note, 0); | |
8079 | note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); | |
8080 | if (note) | |
8081 | XEXP (note, 0) = last; | |
8082 | break; | |
8083 | ||
8084 | case REG_NONNEG: | |
8085 | case REG_BR_PROB: | |
8086 | /* This should be moved to whichever instruction is a JUMP_INSN. */ | |
8087 | ||
8088 | for (insn = last;; insn = PREV_INSN (insn)) | |
8089 | { | |
8090 | if (GET_CODE (insn) == JUMP_INSN) | |
8091 | { | |
8092 | XEXP (note, 1) = REG_NOTES (insn); | |
8093 | REG_NOTES (insn) = note; | |
8094 | /* Only put this note on one of the new insns. */ | |
8095 | break; | |
8096 | } | |
8097 | /* Fail if we couldn't find a JUMP_INSN. */ | |
8098 | if (insn == first) | |
8099 | abort (); | |
8100 | } | |
8101 | break; | |
8102 | ||
8103 | case REG_INC: | |
8104 | /* reload sometimes leaves obsolete REG_INC notes around. */ | |
8105 | if (reload_completed) | |
8106 | break; | |
8107 | /* This should be moved to whichever instruction now has the | |
8108 | increment operation. */ | |
8109 | abort (); | |
8110 | ||
8111 | case REG_LABEL: | |
8112 | /* Should be moved to the new insn(s) which use the label. */ | |
8113 | for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) | |
8114 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
8115 | && reg_mentioned_p (XEXP (note, 0), PATTERN (insn))) | |
ebb7b10b RH |
8116 | { |
8117 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_LABEL, | |
38a448ca RH |
8118 | XEXP (note, 0), |
8119 | REG_NOTES (insn)); | |
ebb7b10b | 8120 | } |
8c660648 JL |
8121 | break; |
8122 | ||
8123 | case REG_CC_SETTER: | |
8124 | case REG_CC_USER: | |
8125 | /* These two notes will never appear until after reorg, so we don't | |
8126 | have to handle them here. */ | |
8127 | default: | |
8128 | abort (); | |
8129 | } | |
8130 | } | |
8131 | ||
8132 | /* Each new insn created, except the last, has a new set. If the destination | |
8133 | is a register, then this reg is now live across several insns, whereas | |
8134 | previously the dest reg was born and died within the same insn. To | |
8135 | reflect this, we now need a REG_DEAD note on the insn where this | |
8136 | dest reg dies. | |
8137 | ||
8138 | Similarly, the new insns may have clobbers that need REG_UNUSED notes. */ | |
8139 | ||
8140 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
8141 | { | |
8142 | rtx pat; | |
8143 | int i; | |
8144 | ||
8145 | pat = PATTERN (insn); | |
8146 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) | |
8147 | new_insn_dead_notes (pat, insn, last, orig_insn); | |
8148 | else if (GET_CODE (pat) == PARALLEL) | |
8149 | { | |
8150 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
8151 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET | |
8152 | || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER) | |
8153 | new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn); | |
8154 | } | |
8155 | } | |
8156 | ||
8157 | /* If any insn, except the last, uses the register set by the last insn, | |
8158 | then we need a new REG_DEAD note on that insn. In this case, there | |
8159 | would not have been a REG_DEAD note for this register in the original | |
8160 | insn because it was used and set within one insn. */ | |
8161 | ||
8162 | set = single_set (last); | |
8163 | if (set) | |
8164 | { | |
8165 | rtx dest = SET_DEST (set); | |
8166 | ||
8167 | while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG | |
8168 | || GET_CODE (dest) == STRICT_LOW_PART | |
8169 | || GET_CODE (dest) == SIGN_EXTRACT) | |
8170 | dest = XEXP (dest, 0); | |
8171 | ||
8172 | if (GET_CODE (dest) == REG | |
8173 | /* Global registers are always live, so the code below does not | |
8174 | apply to them. */ | |
8175 | && (REGNO (dest) >= FIRST_PSEUDO_REGISTER | |
8176 | || ! global_regs[REGNO (dest)])) | |
8177 | { | |
8178 | rtx stop_insn = PREV_INSN (first); | |
8179 | ||
8180 | /* If the last insn uses the register that it is setting, then | |
8181 | we don't want to put a REG_DEAD note there. Search backwards | |
8182 | to find the first insn that sets but does not use DEST. */ | |
8183 | ||
8184 | insn = last; | |
8185 | if (reg_overlap_mentioned_p (dest, SET_SRC (set))) | |
8186 | { | |
8187 | for (insn = PREV_INSN (insn); insn != first; | |
8188 | insn = PREV_INSN (insn)) | |
8189 | { | |
8190 | if ((set = single_set (insn)) | |
8191 | && reg_mentioned_p (dest, SET_DEST (set)) | |
8192 | && ! reg_overlap_mentioned_p (dest, SET_SRC (set))) | |
8193 | break; | |
8194 | } | |
8195 | } | |
8196 | ||
8197 | /* Now find the first insn that uses but does not set DEST. */ | |
8198 | ||
8199 | for (insn = PREV_INSN (insn); insn != stop_insn; | |
8200 | insn = PREV_INSN (insn)) | |
8201 | { | |
8202 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
8203 | && reg_mentioned_p (dest, PATTERN (insn)) | |
8204 | && (set = single_set (insn))) | |
8205 | { | |
8206 | rtx insn_dest = SET_DEST (set); | |
8207 | ||
8208 | while (GET_CODE (insn_dest) == ZERO_EXTRACT | |
8209 | || GET_CODE (insn_dest) == SUBREG | |
8210 | || GET_CODE (insn_dest) == STRICT_LOW_PART | |
8211 | || GET_CODE (insn_dest) == SIGN_EXTRACT) | |
8212 | insn_dest = XEXP (insn_dest, 0); | |
8213 | ||
8214 | if (insn_dest != dest) | |
8215 | { | |
ebb7b10b | 8216 | note = alloc_EXPR_LIST (REG_DEAD, dest, REG_NOTES (insn)); |
8c660648 JL |
8217 | REG_NOTES (insn) = note; |
8218 | /* The reg only dies in one insn, the last one | |
8219 | that uses it. */ | |
8220 | break; | |
8221 | } | |
8222 | } | |
8223 | } | |
8224 | } | |
8225 | } | |
8226 | ||
8227 | /* If the original dest is modifying a multiple register target, and the | |
8228 | original instruction was split such that the original dest is now set | |
8229 | by two or more SUBREG sets, then the split insns no longer kill the | |
8230 | destination of the original insn. | |
8231 | ||
8232 | In this case, if there exists an instruction in the same basic block, | |
8233 | before the split insn, which uses the original dest, and this use is | |
8234 | killed by the original insn, then we must remove the REG_DEAD note on | |
8235 | this insn, because it is now superfluous. | |
8236 | ||
8237 | This does not apply when a hard register gets split, because the code | |
8238 | knows how to handle overlapping hard registers properly. */ | |
8239 | if (orig_dest && GET_CODE (orig_dest) == REG) | |
8240 | { | |
8241 | int found_orig_dest = 0; | |
8242 | int found_split_dest = 0; | |
8243 | ||
8244 | for (insn = first;; insn = NEXT_INSN (insn)) | |
8245 | { | |
acceac1a R |
8246 | rtx pat; |
8247 | int i; | |
8248 | ||
8249 | /* I'm not sure if this can happen, but let's be safe. */ | |
8250 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
8251 | continue; | |
8252 | ||
8253 | pat = PATTERN (insn); | |
8254 | i = GET_CODE (pat) == PARALLEL ? XVECLEN (pat, 0) : 0; | |
8255 | set = pat; | |
8256 | ||
8257 | for (;;) | |
8c660648 | 8258 | { |
acceac1a | 8259 | if (GET_CODE (set) == SET) |
8c660648 | 8260 | { |
acceac1a R |
8261 | if (GET_CODE (SET_DEST (set)) == REG |
8262 | && REGNO (SET_DEST (set)) == REGNO (orig_dest)) | |
8263 | { | |
8264 | found_orig_dest = 1; | |
8265 | break; | |
8266 | } | |
8267 | else if (GET_CODE (SET_DEST (set)) == SUBREG | |
8268 | && SUBREG_REG (SET_DEST (set)) == orig_dest) | |
8269 | { | |
8270 | found_split_dest = 1; | |
8271 | break; | |
8272 | } | |
8c660648 | 8273 | } |
acceac1a R |
8274 | if (--i < 0) |
8275 | break; | |
8276 | set = XVECEXP (pat, 0, i); | |
8c660648 JL |
8277 | } |
8278 | ||
8279 | if (insn == last) | |
8280 | break; | |
8281 | } | |
8282 | ||
8283 | if (found_split_dest) | |
8284 | { | |
8285 | /* Search backwards from FIRST, looking for the first insn that uses | |
8286 | the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN. | |
8287 | If we find an insn, and it has a REG_DEAD note, then delete the | |
8288 | note. */ | |
8289 | ||
8290 | for (insn = first; insn; insn = PREV_INSN (insn)) | |
8291 | { | |
8292 | if (GET_CODE (insn) == CODE_LABEL | |
8293 | || GET_CODE (insn) == JUMP_INSN) | |
8294 | break; | |
8295 | else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
8296 | && reg_mentioned_p (orig_dest, insn)) | |
8297 | { | |
8298 | note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest)); | |
8299 | if (note) | |
8300 | remove_note (insn, note); | |
8301 | } | |
8302 | } | |
8303 | } | |
8304 | else if (!found_orig_dest) | |
8305 | { | |
faff4ab8 JW |
8306 | int i, regno; |
8307 | ||
8308 | /* Should never reach here for a pseudo reg. */ | |
8309 | if (REGNO (orig_dest) >= FIRST_PSEUDO_REGISTER) | |
8310 | abort (); | |
8311 | ||
8312 | /* This can happen for a hard register, if the splitter | |
8313 | does not bother to emit instructions which would be no-ops. | |
8314 | We try to verify that this is the case by checking to see if | |
8315 | the original instruction uses all of the registers that it | |
8316 | set. This case is OK, because deleting a no-op can not affect | |
8317 | REG_DEAD notes on other insns. If this is not the case, then | |
8318 | abort. */ | |
8319 | ||
8320 | regno = REGNO (orig_dest); | |
8321 | for (i = HARD_REGNO_NREGS (regno, GET_MODE (orig_dest)) - 1; | |
8322 | i >= 0; i--) | |
8323 | if (! refers_to_regno_p (regno + i, regno + i + 1, orig_insn, | |
8324 | NULL_PTR)) | |
8325 | break; | |
8326 | if (i >= 0) | |
8327 | abort (); | |
8c660648 JL |
8328 | } |
8329 | } | |
8330 | ||
8331 | /* Update reg_n_sets. This is necessary to prevent local alloc from | |
8332 | converting REG_EQUAL notes to REG_EQUIV when splitting has modified | |
8333 | a reg from set once to set multiple times. */ | |
8334 | ||
8335 | { | |
8336 | rtx x = PATTERN (orig_insn); | |
8337 | RTX_CODE code = GET_CODE (x); | |
8338 | ||
8339 | if (code == SET || code == CLOBBER) | |
8340 | update_n_sets (x, -1); | |
8341 | else if (code == PARALLEL) | |
8342 | { | |
8343 | int i; | |
8344 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
8345 | { | |
8346 | code = GET_CODE (XVECEXP (x, 0, i)); | |
8347 | if (code == SET || code == CLOBBER) | |
8348 | update_n_sets (XVECEXP (x, 0, i), -1); | |
8349 | } | |
8350 | } | |
8351 | ||
8352 | for (insn = first;; insn = NEXT_INSN (insn)) | |
8353 | { | |
8354 | x = PATTERN (insn); | |
8355 | code = GET_CODE (x); | |
8356 | ||
8357 | if (code == SET || code == CLOBBER) | |
8358 | update_n_sets (x, 1); | |
8359 | else if (code == PARALLEL) | |
8360 | { | |
8361 | int i; | |
8362 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
8363 | { | |
8364 | code = GET_CODE (XVECEXP (x, 0, i)); | |
8365 | if (code == SET || code == CLOBBER) | |
8366 | update_n_sets (XVECEXP (x, 0, i), 1); | |
8367 | } | |
8368 | } | |
8369 | ||
8370 | if (insn == last) | |
8371 | break; | |
8372 | } | |
8373 | } | |
8374 | } | |
8375 | ||
8c660648 JL |
8376 | /* The one entry point in this file. DUMP_FILE is the dump file for |
8377 | this pass. */ | |
8378 | ||
8379 | void | |
8380 | schedule_insns (dump_file) | |
8381 | FILE *dump_file; | |
8382 | { | |
8383 | ||
8384 | int max_uid; | |
8385 | int b; | |
8c660648 JL |
8386 | rtx insn; |
8387 | int rgn; | |
8388 | ||
8389 | int luid; | |
8390 | ||
8391 | /* disable speculative loads in their presence if cc0 defined */ | |
8392 | #ifdef HAVE_cc0 | |
8393 | flag_schedule_speculative_load = 0; | |
8394 | #endif | |
8395 | ||
8396 | /* Taking care of this degenerate case makes the rest of | |
8397 | this code simpler. */ | |
8398 | if (n_basic_blocks == 0) | |
8399 | return; | |
8400 | ||
8401 | /* set dump and sched_verbose for the desired debugging output. If no | |
8402 | dump-file was specified, but -fsched-verbose-N (any N), print to stderr. | |
8403 | For -fsched-verbose-N, N>=10, print everything to stderr. */ | |
8404 | sched_verbose = sched_verbose_param; | |
8405 | if (sched_verbose_param == 0 && dump_file) | |
8406 | sched_verbose = 1; | |
8407 | dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file); | |
8408 | ||
8409 | nr_inter = 0; | |
8410 | nr_spec = 0; | |
8411 | ||
8412 | /* Initialize the unused_*_lists. We can't use the ones left over from | |
8413 | the previous function, because gcc has freed that memory. We can use | |
8414 | the ones left over from the first sched pass in the second pass however, | |
8415 | so only clear them on the first sched pass. The first pass is before | |
8416 | reload if flag_schedule_insns is set, otherwise it is afterwards. */ | |
8417 | ||
8418 | if (reload_completed == 0 || !flag_schedule_insns) | |
8419 | { | |
8420 | unused_insn_list = 0; | |
8421 | unused_expr_list = 0; | |
8422 | } | |
8423 | ||
8424 | /* initialize issue_rate */ | |
62d65906 | 8425 | issue_rate = ISSUE_RATE; |
8c660648 JL |
8426 | |
8427 | /* do the splitting first for all blocks */ | |
8428 | for (b = 0; b < n_basic_blocks; b++) | |
ca545bb5 | 8429 | split_block_insns (b, 1); |
8c660648 JL |
8430 | |
8431 | max_uid = (get_max_uid () + 1); | |
8432 | ||
7c74b010 | 8433 | cant_move = (char *) xmalloc (max_uid * sizeof (char)); |
8c660648 JL |
8434 | bzero ((char *) cant_move, max_uid * sizeof (char)); |
8435 | ||
7c74b010 | 8436 | fed_by_spec_load = (char *) xmalloc (max_uid * sizeof (char)); |
8c660648 JL |
8437 | bzero ((char *) fed_by_spec_load, max_uid * sizeof (char)); |
8438 | ||
7c74b010 | 8439 | is_load_insn = (char *) xmalloc (max_uid * sizeof (char)); |
8c660648 JL |
8440 | bzero ((char *) is_load_insn, max_uid * sizeof (char)); |
8441 | ||
7c74b010 JW |
8442 | insn_orig_block = (int *) xmalloc (max_uid * sizeof (int)); |
8443 | insn_luid = (int *) xmalloc (max_uid * sizeof (int)); | |
8c660648 JL |
8444 | |
8445 | luid = 0; | |
8446 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 8447 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
8448 | { |
8449 | INSN_BLOCK (insn) = b; | |
8450 | INSN_LUID (insn) = luid++; | |
8451 | ||
3b413743 | 8452 | if (insn == BLOCK_END (b)) |
8c660648 JL |
8453 | break; |
8454 | } | |
8455 | ||
8456 | /* after reload, remove inter-blocks dependences computed before reload. */ | |
8457 | if (reload_completed) | |
8458 | { | |
8459 | int b; | |
8460 | rtx insn; | |
8461 | ||
8462 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 8463 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 | 8464 | { |
c995fea1 | 8465 | rtx link, prev; |
8c660648 JL |
8466 | |
8467 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
8468 | { | |
c995fea1 RH |
8469 | prev = NULL_RTX; |
8470 | link = LOG_LINKS (insn); | |
8471 | while (link) | |
8c660648 JL |
8472 | { |
8473 | rtx x = XEXP (link, 0); | |
8474 | ||
8475 | if (INSN_BLOCK (x) != b) | |
c995fea1 RH |
8476 | { |
8477 | remove_dependence (insn, x); | |
8478 | link = prev ? XEXP (prev, 1) : LOG_LINKS (insn); | |
8479 | } | |
8480 | else | |
8481 | prev = link, link = XEXP (prev, 1); | |
8c660648 JL |
8482 | } |
8483 | } | |
8484 | ||
3b413743 | 8485 | if (insn == BLOCK_END (b)) |
8c660648 JL |
8486 | break; |
8487 | } | |
8488 | } | |
8489 | ||
8490 | nr_regions = 0; | |
8491 | rgn_table = (region *) alloca ((n_basic_blocks) * sizeof (region)); | |
8492 | rgn_bb_table = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
8493 | block_to_bb = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
8494 | containing_rgn = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
8495 | ||
8496 | /* compute regions for scheduling */ | |
8497 | if (reload_completed | |
8498 | || n_basic_blocks == 1 | |
8499 | || !flag_schedule_interblock) | |
8500 | { | |
8501 | find_single_block_region (); | |
8502 | } | |
8503 | else | |
8504 | { | |
8c660648 | 8505 | /* verify that a 'good' control flow graph can be built */ |
168cbdf9 | 8506 | if (is_cfg_nonregular ()) |
8c660648 JL |
8507 | { |
8508 | find_single_block_region (); | |
8509 | } | |
8510 | else | |
8511 | { | |
a2e68776 JL |
8512 | int_list_ptr *s_preds, *s_succs; |
8513 | int *num_preds, *num_succs; | |
8514 | sbitmap *dom, *pdom; | |
8515 | ||
8516 | s_preds = (int_list_ptr *) alloca (n_basic_blocks | |
8517 | * sizeof (int_list_ptr)); | |
8518 | s_succs = (int_list_ptr *) alloca (n_basic_blocks | |
8519 | * sizeof (int_list_ptr)); | |
8520 | num_preds = (int *) alloca (n_basic_blocks * sizeof (int)); | |
8521 | num_succs = (int *) alloca (n_basic_blocks * sizeof (int)); | |
8522 | dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
8523 | pdom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
8524 | ||
8525 | /* The scheduler runs after flow; therefore, we can't blindly call | |
8526 | back into find_basic_blocks since doing so could invalidate the | |
8527 | info in basic_block_live_at_start. | |
8528 | ||
8529 | Consider a block consisting entirely of dead stores; after life | |
8530 | analysis it would be a block of NOTE_INSN_DELETED notes. If | |
8531 | we call find_basic_blocks again, then the block would be removed | |
8532 | entirely and invalidate our the register live information. | |
8533 | ||
8534 | We could (should?) recompute register live information. Doing | |
8535 | so may even be beneficial. */ | |
8536 | ||
5d27de7d | 8537 | compute_preds_succs (s_preds, s_succs, num_preds, num_succs); |
a2e68776 JL |
8538 | |
8539 | /* Compute the dominators and post dominators. We don't currently use | |
8540 | post dominators, but we should for speculative motion analysis. */ | |
8541 | compute_dominators (dom, pdom, s_preds, s_succs); | |
8542 | ||
168cbdf9 JL |
8543 | /* build_control_flow will return nonzero if it detects unreachable |
8544 | blocks or any other irregularity with the cfg which prevents | |
8545 | cross block scheduling. */ | |
a2e68776 | 8546 | if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0) |
168cbdf9 JL |
8547 | find_single_block_region (); |
8548 | else | |
a2e68776 | 8549 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom); |
8c660648 JL |
8550 | |
8551 | if (sched_verbose >= 3) | |
a2e68776 | 8552 | debug_regions (); |
8c660648 | 8553 | |
a2e68776 JL |
8554 | /* For now. This will move as more and more of haifa is converted |
8555 | to using the cfg code in flow.c */ | |
8556 | free_bb_mem (); | |
8557 | free (dom); | |
8558 | free (pdom); | |
8c660648 JL |
8559 | } |
8560 | } | |
8561 | ||
8562 | /* Allocate data for this pass. See comments, above, | |
7c74b010 JW |
8563 | for what these vectors do. |
8564 | ||
8565 | We use xmalloc instead of alloca, because max_uid can be very large | |
8566 | when there is a lot of function inlining. If we used alloca, we could | |
8567 | exceed stack limits on some hosts for some inputs. */ | |
8568 | insn_priority = (int *) xmalloc (max_uid * sizeof (int)); | |
8569 | insn_reg_weight = (int *) xmalloc (max_uid * sizeof (int)); | |
8570 | insn_tick = (int *) xmalloc (max_uid * sizeof (int)); | |
8571 | insn_costs = (short *) xmalloc (max_uid * sizeof (short)); | |
8572 | insn_units = (short *) xmalloc (max_uid * sizeof (short)); | |
8573 | insn_blockage = (unsigned int *) xmalloc (max_uid * sizeof (unsigned int)); | |
8574 | insn_ref_count = (int *) xmalloc (max_uid * sizeof (int)); | |
8c660648 JL |
8575 | |
8576 | /* Allocate for forward dependencies */ | |
7c74b010 JW |
8577 | insn_dep_count = (int *) xmalloc (max_uid * sizeof (int)); |
8578 | insn_depend = (rtx *) xmalloc (max_uid * sizeof (rtx)); | |
8c660648 JL |
8579 | |
8580 | if (reload_completed == 0) | |
8581 | { | |
8582 | int i; | |
8583 | ||
8584 | sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int)); | |
8585 | sched_reg_live_length = (int *) alloca (max_regno * sizeof (int)); | |
8586 | sched_reg_basic_block = (int *) alloca (max_regno * sizeof (int)); | |
8587 | bb_live_regs = ALLOCA_REG_SET (); | |
8588 | bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int)); | |
8589 | bzero ((char *) sched_reg_live_length, max_regno * sizeof (int)); | |
8590 | ||
8591 | for (i = 0; i < max_regno; i++) | |
8592 | sched_reg_basic_block[i] = REG_BLOCK_UNKNOWN; | |
8593 | } | |
8594 | else | |
8595 | { | |
8596 | sched_reg_n_calls_crossed = 0; | |
8597 | sched_reg_live_length = 0; | |
8598 | bb_live_regs = 0; | |
8599 | } | |
8600 | init_alias_analysis (); | |
8601 | ||
8602 | if (write_symbols != NO_DEBUG) | |
8603 | { | |
8604 | rtx line; | |
8605 | ||
7c74b010 | 8606 | line_note = (rtx *) xmalloc (max_uid * sizeof (rtx)); |
8c660648 JL |
8607 | bzero ((char *) line_note, max_uid * sizeof (rtx)); |
8608 | line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx)); | |
8609 | bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx)); | |
8610 | ||
8611 | /* Save-line-note-head: | |
8612 | Determine the line-number at the start of each basic block. | |
8613 | This must be computed and saved now, because after a basic block's | |
8614 | predecessor has been scheduled, it is impossible to accurately | |
8615 | determine the correct line number for the first insn of the block. */ | |
8616 | ||
8617 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 8618 | for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line)) |
8c660648 JL |
8619 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) |
8620 | { | |
8621 | line_note_head[b] = line; | |
8622 | break; | |
8623 | } | |
8624 | } | |
8625 | ||
8626 | bzero ((char *) insn_priority, max_uid * sizeof (int)); | |
8627 | bzero ((char *) insn_reg_weight, max_uid * sizeof (int)); | |
8628 | bzero ((char *) insn_tick, max_uid * sizeof (int)); | |
8629 | bzero ((char *) insn_costs, max_uid * sizeof (short)); | |
8630 | bzero ((char *) insn_units, max_uid * sizeof (short)); | |
8631 | bzero ((char *) insn_blockage, max_uid * sizeof (unsigned int)); | |
8632 | bzero ((char *) insn_ref_count, max_uid * sizeof (int)); | |
8633 | ||
8634 | /* Initialize for forward dependencies */ | |
8635 | bzero ((char *) insn_depend, max_uid * sizeof (rtx)); | |
8636 | bzero ((char *) insn_dep_count, max_uid * sizeof (int)); | |
8637 | ||
8638 | /* Find units used in this fuction, for visualization */ | |
8639 | if (sched_verbose) | |
8640 | init_target_units (); | |
8641 | ||
8642 | /* ??? Add a NOTE after the last insn of the last basic block. It is not | |
8643 | known why this is done. */ | |
8644 | ||
3b413743 | 8645 | insn = BLOCK_END (n_basic_blocks - 1); |
8c660648 JL |
8646 | if (NEXT_INSN (insn) == 0 |
8647 | || (GET_CODE (insn) != NOTE | |
8648 | && GET_CODE (insn) != CODE_LABEL | |
3b413743 RH |
8649 | /* Don't emit a NOTE if it would end up between an unconditional |
8650 | jump and a BARRIER. */ | |
8c660648 JL |
8651 | && !(GET_CODE (insn) == JUMP_INSN |
8652 | && GET_CODE (NEXT_INSN (insn)) == BARRIER))) | |
3b413743 | 8653 | emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1)); |
8c660648 JL |
8654 | |
8655 | /* Schedule every region in the subroutine */ | |
8656 | for (rgn = 0; rgn < nr_regions; rgn++) | |
8657 | { | |
8658 | schedule_region (rgn); | |
8659 | ||
8660 | #ifdef USE_C_ALLOCA | |
8661 | alloca (0); | |
8662 | #endif | |
8663 | } | |
8664 | ||
8665 | /* Reposition the prologue and epilogue notes in case we moved the | |
8666 | prologue/epilogue insns. */ | |
8667 | if (reload_completed) | |
8668 | reposition_prologue_and_epilogue_notes (get_insns ()); | |
8669 | ||
8670 | /* delete redundant line notes. */ | |
8671 | if (write_symbols != NO_DEBUG) | |
8672 | rm_redundant_line_notes (); | |
8673 | ||
8674 | /* Update information about uses of registers in the subroutine. */ | |
8675 | if (reload_completed == 0) | |
8676 | update_reg_usage (); | |
8677 | ||
8678 | if (sched_verbose) | |
8679 | { | |
8680 | if (reload_completed == 0 && flag_schedule_interblock) | |
8681 | { | |
8682 | fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n", | |
8683 | nr_inter, nr_spec); | |
8684 | } | |
8685 | else | |
8686 | { | |
8687 | if (nr_inter > 0) | |
8688 | abort (); | |
8689 | } | |
8690 | fprintf (dump, "\n\n"); | |
8691 | } | |
f187056f | 8692 | |
7c74b010 JW |
8693 | free (cant_move); |
8694 | free (fed_by_spec_load); | |
8695 | free (is_load_insn); | |
8696 | free (insn_orig_block); | |
8697 | free (insn_luid); | |
8698 | ||
8699 | free (insn_priority); | |
8700 | free (insn_reg_weight); | |
8701 | free (insn_tick); | |
8702 | free (insn_costs); | |
8703 | free (insn_units); | |
8704 | free (insn_blockage); | |
8705 | free (insn_ref_count); | |
8706 | ||
8707 | free (insn_dep_count); | |
8708 | free (insn_depend); | |
8709 | ||
8710 | if (write_symbols != NO_DEBUG) | |
8711 | free (line_note); | |
8712 | ||
f187056f JL |
8713 | if (bb_live_regs) |
8714 | FREE_REG_SET (bb_live_regs); | |
168cbdf9 JL |
8715 | |
8716 | if (edge_table) | |
8717 | { | |
8718 | free (edge_table); | |
8719 | edge_table = NULL; | |
8720 | } | |
8721 | ||
8722 | if (in_edges) | |
8723 | { | |
8724 | free (in_edges); | |
8725 | in_edges = NULL; | |
8726 | } | |
8727 | if (out_edges) | |
8728 | { | |
8729 | free (out_edges); | |
8730 | out_edges = NULL; | |
8731 | } | |
8c660648 JL |
8732 | } |
8733 | #endif /* INSN_SCHEDULING */ |