]>
Commit | Line | Data |
---|---|---|
47dd2e78 | 1 | /* Communication between the Integrated Register Allocator (IRA) and |
2 | the rest of the compiler. | |
cfaf579d | 3 | Copyright (C) 2006, 2007, 2008, 2009 |
47dd2e78 | 4 | Free Software Foundation, Inc. |
5 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
6 | ||
7 | This file is part of GCC. | |
8 | ||
9 | GCC is free software; you can redistribute it and/or modify it under | |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 3, or (at your option) any later | |
12 | version. | |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GCC; see the file COPYING3. If not see | |
21 | <http://www.gnu.org/licenses/>. */ | |
22 | ||
a7dcf969 | 23 | /* Function specific hard registers can not be used for the register |
24 | allocation. */ | |
25 | extern HARD_REG_SET ira_no_alloc_regs; | |
26 | ||
95c83f01 | 27 | /* True if we have allocno conflicts. It is false for non-optimized |
28 | mode or when the conflict table is too big. */ | |
29 | extern bool ira_conflicts_p; | |
30 | ||
a1e0509e | 31 | struct target_ira { |
32 | /* Number of given class hard registers available for the register | |
33 | allocation for given classes. */ | |
34 | int x_ira_available_class_regs[N_REG_CLASSES]; | |
35 | ||
36 | /* Map: hard register number -> cover class it belongs to. If the | |
37 | corresponding class is NO_REGS, the hard register is not available | |
38 | for allocation. */ | |
39 | enum reg_class x_ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER]; | |
40 | ||
41 | /* Number of cover classes. Cover classes is non-intersected register | |
42 | classes containing all hard-registers available for the | |
43 | allocation. */ | |
44 | int x_ira_reg_class_cover_size; | |
45 | ||
46 | /* The array containing cover classes (see also comments for macro | |
47 | IRA_COVER_CLASSES;. Only first IRA_REG_CLASS_COVER_SIZE elements are | |
48 | used for this. */ | |
49 | enum reg_class x_ira_reg_class_cover[N_REG_CLASSES]; | |
50 | ||
51 | /* Map of all register classes to corresponding cover class containing | |
52 | the given class. If given class is not a subset of a cover class, | |
53 | we translate it into the cheapest cover class. */ | |
54 | enum reg_class x_ira_class_translate[N_REG_CLASSES]; | |
55 | ||
56 | /* Map: register class x machine mode -> number of hard registers of | |
57 | given class needed to store value of given mode. If the number for | |
58 | some hard-registers of the register class is different, the size | |
59 | will be negative. */ | |
60 | int x_ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
61 | ||
62 | /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */ | |
63 | short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; | |
64 | ||
65 | /* Array of number of hard registers of given class which are | |
66 | available for the allocation. The order is defined by the | |
67 | allocation order. */ | |
68 | short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
69 | ||
70 | /* The number of elements of the above array for given register | |
71 | class. */ | |
72 | int x_ira_class_hard_regs_num[N_REG_CLASSES]; | |
73 | }; | |
74 | ||
75 | extern struct target_ira default_target_ira; | |
76 | #if SWITCHABLE_TARGET | |
77 | extern struct target_ira *this_target_ira; | |
78 | #else | |
79 | #define this_target_ira (&default_target_ira) | |
80 | #endif | |
81 | ||
82 | #define ira_available_class_regs \ | |
83 | (this_target_ira->x_ira_available_class_regs) | |
84 | #define ira_hard_regno_cover_class \ | |
85 | (this_target_ira->x_ira_hard_regno_cover_class) | |
86 | #define ira_reg_class_cover_size \ | |
87 | (this_target_ira->x_ira_reg_class_cover_size) | |
88 | #define ira_reg_class_cover \ | |
89 | (this_target_ira->x_ira_reg_class_cover) | |
90 | #define ira_class_translate \ | |
91 | (this_target_ira->x_ira_class_translate) | |
92 | #define ira_reg_class_nregs \ | |
93 | (this_target_ira->x_ira_reg_class_nregs) | |
94 | #define ira_memory_move_cost \ | |
95 | (this_target_ira->x_ira_memory_move_cost) | |
96 | #define ira_class_hard_regs \ | |
97 | (this_target_ira->x_ira_class_hard_regs) | |
98 | #define ira_class_hard_regs_num \ | |
99 | (this_target_ira->x_ira_class_hard_regs_num) | |
a7dcf969 | 100 | |
47dd2e78 | 101 | extern void ira_init_once (void); |
102 | extern void ira_init (void); | |
103 | extern void ira_finish_once (void); | |
a7dcf969 | 104 | extern void ira_setup_eliminable_regset (void); |
47dd2e78 | 105 | extern rtx ira_eliminate_regs (rtx, enum machine_mode); |
a7dcf969 | 106 | extern void ira_set_pseudo_classes (FILE *); |
107 | extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *); | |
47dd2e78 | 108 | |
109 | extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *); | |
110 | extern void ira_mark_allocation_change (int); | |
111 | extern void ira_mark_memory_move_deletion (int, int); | |
112 | extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *, | |
113 | HARD_REG_SET *, bitmap); | |
114 | extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int); | |
115 | extern void ira_mark_new_stack_slot (rtx, int, unsigned int); | |
116 | extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); | |
732f3fd8 | 117 | extern bool ira_bad_reload_regno (int, rtx, rtx); |
47dd2e78 | 118 | |
4164ad58 | 119 | extern void ira_adjust_equiv_reg_cost (unsigned, int); |