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50654f6c | 1 | /* Rtl-level induction variable analysis. |
5624e564 | 2 | Copyright (C) 2004-2015 Free Software Foundation, Inc. |
b8698a0f | 3 | |
50654f6c | 4 | This file is part of GCC. |
b8698a0f | 5 | |
50654f6c ZD |
6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the | |
9dcd6f09 | 8 | Free Software Foundation; either version 3, or (at your option) any |
50654f6c | 9 | later version. |
b8698a0f | 10 | |
50654f6c ZD |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
b8698a0f | 15 | |
50654f6c | 16 | You should have received a copy of the GNU General Public License |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
50654f6c | 19 | |
03fd2215 ZD |
20 | /* This is a simple analysis of induction variables of the loop. The major use |
21 | is for determining the number of iterations of a loop for loop unrolling, | |
22 | doloop optimization and branch prediction. The iv information is computed | |
23 | on demand. | |
24 | ||
2b49e1a0 KZ |
25 | Induction variables are analyzed by walking the use-def chains. When |
26 | a basic induction variable (biv) is found, it is cached in the bivs | |
27 | hash table. When register is proved to be a biv, its description | |
28 | is stored to DF_REF_DATA of the def reference. | |
03fd2215 ZD |
29 | |
30 | The analysis works always with one loop -- you must call | |
31 | iv_analysis_loop_init (loop) for it. All the other functions then work with | |
32 | this loop. When you need to work with another loop, just call | |
33 | iv_analysis_loop_init for it. When you no longer need iv analysis, call | |
34 | iv_analysis_done () to clean up the memory. | |
35 | ||
36 | The available functions are: | |
b8698a0f | 37 | |
03fd2215 ZD |
38 | iv_analyze (insn, reg, iv): Stores the description of the induction variable |
39 | corresponding to the use of register REG in INSN to IV. Returns true if | |
40 | REG is an induction variable in INSN. false otherwise. | |
41 | If use of REG is not found in INSN, following insns are scanned (so that | |
42 | we may call this function on insn returned by get_condition). | |
43 | iv_analyze_result (insn, def, iv): Stores to IV the description of the iv | |
44 | corresponding to DEF, which is a register defined in INSN. | |
45 | iv_analyze_expr (insn, rhs, mode, iv): Stores to IV the description of iv | |
46 | corresponding to expression EXPR evaluated at INSN. All registers used bu | |
47 | EXPR must also be used in INSN. | |
6fb5fa3c | 48 | */ |
50654f6c ZD |
49 | |
50 | #include "config.h" | |
51 | #include "system.h" | |
52 | #include "coretypes.h" | |
53 | #include "tm.h" | |
54 | #include "rtl.h" | |
55 | #include "hard-reg-set.h" | |
7932a3db | 56 | #include "obstack.h" |
60393bbc AM |
57 | #include "predict.h" |
58 | #include "vec.h" | |
59 | #include "hashtab.h" | |
60 | #include "hash-set.h" | |
61 | #include "machmode.h" | |
62 | #include "input.h" | |
63 | #include "function.h" | |
64 | #include "dominance.h" | |
65 | #include "cfg.h" | |
50654f6c ZD |
66 | #include "basic-block.h" |
67 | #include "cfgloop.h" | |
40e23961 | 68 | #include "symtab.h" |
50654f6c | 69 | #include "expr.h" |
f9cc1a70 | 70 | #include "intl.h" |
718f9c0f | 71 | #include "diagnostic-core.h" |
03fd2215 | 72 | #include "df.h" |
4a8fb1a1 | 73 | #include "hash-table.h" |
7ee2468b | 74 | #include "dumpfile.h" |
4ca29add | 75 | #include "rtl-iter.h" |
50654f6c | 76 | |
03fd2215 | 77 | /* Possible return values of iv_get_reaching_def. */ |
50654f6c | 78 | |
03fd2215 | 79 | enum iv_grd_result |
50654f6c | 80 | { |
03fd2215 ZD |
81 | /* More than one reaching def, or reaching def that does not |
82 | dominate the use. */ | |
83 | GRD_INVALID, | |
50654f6c | 84 | |
03fd2215 ZD |
85 | /* The use is trivial invariant of the loop, i.e. is not changed |
86 | inside the loop. */ | |
87 | GRD_INVARIANT, | |
50654f6c | 88 | |
03fd2215 ZD |
89 | /* The use is reached by initial value and a value from the |
90 | previous iteration. */ | |
91 | GRD_MAYBE_BIV, | |
92 | ||
93 | /* The use has single dominating def. */ | |
94 | GRD_SINGLE_DOM | |
95 | }; | |
96 | ||
97 | /* Information about a biv. */ | |
98 | ||
99 | struct biv_entry | |
100 | { | |
101 | unsigned regno; /* The register of the biv. */ | |
102 | struct rtx_iv iv; /* Value of the biv. */ | |
50654f6c ZD |
103 | }; |
104 | ||
6fb5fa3c DB |
105 | static bool clean_slate = true; |
106 | ||
107 | static unsigned int iv_ref_table_size = 0; | |
108 | ||
109 | /* Table of rtx_ivs indexed by the df_ref uid field. */ | |
110 | static struct rtx_iv ** iv_ref_table; | |
111 | ||
03fd2215 | 112 | /* Induction variable stored at the reference. */ |
c3284718 RS |
113 | #define DF_REF_IV(REF) iv_ref_table[DF_REF_ID (REF)] |
114 | #define DF_REF_IV_SET(REF, IV) iv_ref_table[DF_REF_ID (REF)] = (IV) | |
50654f6c | 115 | |
03fd2215 | 116 | /* The current loop. */ |
50654f6c | 117 | |
03fd2215 | 118 | static struct loop *current_loop; |
50654f6c | 119 | |
4a8fb1a1 LC |
120 | /* Hashtable helper. */ |
121 | ||
122 | struct biv_entry_hasher : typed_free_remove <biv_entry> | |
123 | { | |
124 | typedef biv_entry value_type; | |
125 | typedef rtx_def compare_type; | |
126 | static inline hashval_t hash (const value_type *); | |
127 | static inline bool equal (const value_type *, const compare_type *); | |
128 | }; | |
129 | ||
130 | /* Returns hash value for biv B. */ | |
131 | ||
132 | inline hashval_t | |
133 | biv_entry_hasher::hash (const value_type *b) | |
134 | { | |
135 | return b->regno; | |
136 | } | |
137 | ||
138 | /* Compares biv B and register R. */ | |
139 | ||
140 | inline bool | |
141 | biv_entry_hasher::equal (const value_type *b, const compare_type *r) | |
142 | { | |
143 | return b->regno == REGNO (r); | |
144 | } | |
145 | ||
03fd2215 | 146 | /* Bivs of the current loop. */ |
50654f6c | 147 | |
c203e8a7 | 148 | static hash_table<biv_entry_hasher> *bivs; |
50654f6c | 149 | |
1b20d55a | 150 | static bool iv_analyze_op (rtx_insn *, rtx, struct rtx_iv *); |
50654f6c | 151 | |
1c1ad7bb SB |
152 | /* Return the RTX code corresponding to the IV extend code EXTEND. */ |
153 | static inline enum rtx_code | |
154 | iv_extend_to_rtx_code (enum iv_extend_code extend) | |
155 | { | |
156 | switch (extend) | |
157 | { | |
158 | case IV_SIGN_EXTEND: | |
159 | return SIGN_EXTEND; | |
160 | case IV_ZERO_EXTEND: | |
161 | return ZERO_EXTEND; | |
162 | case IV_UNKNOWN_EXTEND: | |
163 | return UNKNOWN; | |
164 | } | |
165 | gcc_unreachable (); | |
166 | } | |
167 | ||
50654f6c ZD |
168 | /* Dumps information about IV to FILE. */ |
169 | ||
170 | extern void dump_iv_info (FILE *, struct rtx_iv *); | |
171 | void | |
172 | dump_iv_info (FILE *file, struct rtx_iv *iv) | |
173 | { | |
174 | if (!iv->base) | |
175 | { | |
176 | fprintf (file, "not simple"); | |
177 | return; | |
178 | } | |
179 | ||
6797f908 ZD |
180 | if (iv->step == const0_rtx |
181 | && !iv->first_special) | |
182 | fprintf (file, "invariant "); | |
50654f6c ZD |
183 | |
184 | print_rtl (file, iv->base); | |
6797f908 ZD |
185 | if (iv->step != const0_rtx) |
186 | { | |
187 | fprintf (file, " + "); | |
188 | print_rtl (file, iv->step); | |
189 | fprintf (file, " * iteration"); | |
190 | } | |
50654f6c ZD |
191 | fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode)); |
192 | ||
193 | if (iv->mode != iv->extend_mode) | |
194 | fprintf (file, " %s to %s", | |
1c1ad7bb | 195 | rtx_name[iv_extend_to_rtx_code (iv->extend)], |
50654f6c ZD |
196 | GET_MODE_NAME (iv->extend_mode)); |
197 | ||
198 | if (iv->mult != const1_rtx) | |
199 | { | |
200 | fprintf (file, " * "); | |
201 | print_rtl (file, iv->mult); | |
202 | } | |
203 | if (iv->delta != const0_rtx) | |
204 | { | |
205 | fprintf (file, " + "); | |
206 | print_rtl (file, iv->delta); | |
207 | } | |
208 | if (iv->first_special) | |
209 | fprintf (file, " (first special)"); | |
210 | } | |
211 | ||
6c3b938d RS |
212 | /* Generates a subreg to get the least significant part of EXPR (in mode |
213 | INNER_MODE) to OUTER_MODE. */ | |
50654f6c | 214 | |
6c3b938d | 215 | rtx |
ef4bddc2 RS |
216 | lowpart_subreg (machine_mode outer_mode, rtx expr, |
217 | machine_mode inner_mode) | |
50654f6c | 218 | { |
6c3b938d RS |
219 | return simplify_gen_subreg (outer_mode, expr, inner_mode, |
220 | subreg_lowpart_offset (outer_mode, inner_mode)); | |
50654f6c ZD |
221 | } |
222 | ||
b8698a0f | 223 | static void |
6fb5fa3c DB |
224 | check_iv_ref_table_size (void) |
225 | { | |
c3284718 | 226 | if (iv_ref_table_size < DF_DEFS_TABLE_SIZE ()) |
6fb5fa3c DB |
227 | { |
228 | unsigned int new_size = DF_DEFS_TABLE_SIZE () + (DF_DEFS_TABLE_SIZE () / 4); | |
d3bfe4de | 229 | iv_ref_table = XRESIZEVEC (struct rtx_iv *, iv_ref_table, new_size); |
b8698a0f | 230 | memset (&iv_ref_table[iv_ref_table_size], 0, |
6fb5fa3c DB |
231 | (new_size - iv_ref_table_size) * sizeof (struct rtx_iv *)); |
232 | iv_ref_table_size = new_size; | |
233 | } | |
234 | } | |
235 | ||
236 | ||
50654f6c ZD |
237 | /* Checks whether REG is a well-behaved register. */ |
238 | ||
239 | static bool | |
240 | simple_reg_p (rtx reg) | |
241 | { | |
242 | unsigned r; | |
243 | ||
244 | if (GET_CODE (reg) == SUBREG) | |
245 | { | |
246 | if (!subreg_lowpart_p (reg)) | |
247 | return false; | |
248 | reg = SUBREG_REG (reg); | |
249 | } | |
250 | ||
251 | if (!REG_P (reg)) | |
252 | return false; | |
253 | ||
254 | r = REGNO (reg); | |
255 | if (HARD_REGISTER_NUM_P (r)) | |
256 | return false; | |
257 | ||
258 | if (GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) | |
259 | return false; | |
260 | ||
50654f6c ZD |
261 | return true; |
262 | } | |
263 | ||
03fd2215 | 264 | /* Clears the information about ivs stored in df. */ |
50654f6c | 265 | |
03fd2215 ZD |
266 | static void |
267 | clear_iv_info (void) | |
50654f6c | 268 | { |
6fb5fa3c | 269 | unsigned i, n_defs = DF_DEFS_TABLE_SIZE (); |
03fd2215 | 270 | struct rtx_iv *iv; |
50654f6c | 271 | |
6fb5fa3c | 272 | check_iv_ref_table_size (); |
03fd2215 | 273 | for (i = 0; i < n_defs; i++) |
50654f6c | 274 | { |
6fb5fa3c DB |
275 | iv = iv_ref_table[i]; |
276 | if (iv) | |
277 | { | |
278 | free (iv); | |
279 | iv_ref_table[i] = NULL; | |
280 | } | |
50654f6c | 281 | } |
50654f6c | 282 | |
c203e8a7 | 283 | bivs->empty (); |
50654f6c ZD |
284 | } |
285 | ||
50654f6c ZD |
286 | |
287 | /* Prepare the data for an induction variable analysis of a LOOP. */ | |
288 | ||
289 | void | |
290 | iv_analysis_loop_init (struct loop *loop) | |
291 | { | |
03fd2215 | 292 | current_loop = loop; |
50654f6c | 293 | |
03fd2215 | 294 | /* Clear the information from the analysis of the previous loop. */ |
6fb5fa3c | 295 | if (clean_slate) |
7faaba28 | 296 | { |
6fb5fa3c | 297 | df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN); |
c203e8a7 | 298 | bivs = new hash_table<biv_entry_hasher> (10); |
6fb5fa3c | 299 | clean_slate = false; |
7faaba28 ZD |
300 | } |
301 | else | |
302 | clear_iv_info (); | |
50654f6c | 303 | |
6fb5fa3c DB |
304 | /* Get rid of the ud chains before processing the rescans. Then add |
305 | the problem back. */ | |
306 | df_remove_problem (df_chain); | |
307 | df_process_deferred_rescans (); | |
7b19209f | 308 | df_set_flags (DF_RD_PRUNE_DEAD_DEFS); |
6fb5fa3c | 309 | df_chain_add_problem (DF_UD_CHAIN); |
c580edc8 | 310 | df_note_add_problem (); |
7be64667 | 311 | df_analyze_loop (loop); |
6fb5fa3c | 312 | if (dump_file) |
ffd640ed | 313 | df_dump_region (dump_file); |
6fb5fa3c DB |
314 | |
315 | check_iv_ref_table_size (); | |
50654f6c ZD |
316 | } |
317 | ||
03fd2215 ZD |
318 | /* Finds the definition of REG that dominates loop latch and stores |
319 | it to DEF. Returns false if there is not a single definition | |
320 | dominating the latch. If REG has no definition in loop, DEF | |
321 | is set to NULL and true is returned. */ | |
50654f6c | 322 | |
03fd2215 | 323 | static bool |
57512f53 | 324 | latch_dominating_def (rtx reg, df_ref *def) |
50654f6c | 325 | { |
57512f53 | 326 | df_ref single_rd = NULL, adef; |
03fd2215 | 327 | unsigned regno = REGNO (reg); |
6fb5fa3c | 328 | struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch); |
50654f6c | 329 | |
57512f53 | 330 | for (adef = DF_REG_DEF_CHAIN (regno); adef; adef = DF_REF_NEXT_REG (adef)) |
50654f6c | 331 | { |
57512f53 | 332 | if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef)) |
b33a91c9 | 333 | || !bitmap_bit_p (&bb_info->out, DF_REF_ID (adef))) |
03fd2215 ZD |
334 | continue; |
335 | ||
336 | /* More than one reaching definition. */ | |
337 | if (single_rd) | |
338 | return false; | |
339 | ||
340 | if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef))) | |
341 | return false; | |
342 | ||
343 | single_rd = adef; | |
50654f6c | 344 | } |
50654f6c | 345 | |
03fd2215 ZD |
346 | *def = single_rd; |
347 | return true; | |
348 | } | |
50654f6c | 349 | |
03fd2215 | 350 | /* Gets definition of REG reaching its use in INSN and stores it to DEF. */ |
50654f6c | 351 | |
03fd2215 | 352 | static enum iv_grd_result |
1b20d55a | 353 | iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def) |
03fd2215 | 354 | { |
57512f53 | 355 | df_ref use, adef; |
03fd2215 | 356 | basic_block def_bb, use_bb; |
1b20d55a | 357 | rtx_insn *def_insn; |
03fd2215 | 358 | bool dom_p; |
b8698a0f | 359 | |
03fd2215 ZD |
360 | *def = NULL; |
361 | if (!simple_reg_p (reg)) | |
362 | return GRD_INVALID; | |
363 | if (GET_CODE (reg) == SUBREG) | |
364 | reg = SUBREG_REG (reg); | |
365 | gcc_assert (REG_P (reg)); | |
50654f6c | 366 | |
6fb5fa3c | 367 | use = df_find_use (insn, reg); |
03fd2215 | 368 | gcc_assert (use != NULL); |
50654f6c | 369 | |
03fd2215 ZD |
370 | if (!DF_REF_CHAIN (use)) |
371 | return GRD_INVARIANT; | |
50654f6c | 372 | |
03fd2215 ZD |
373 | /* More than one reaching def. */ |
374 | if (DF_REF_CHAIN (use)->next) | |
375 | return GRD_INVALID; | |
50654f6c | 376 | |
03fd2215 | 377 | adef = DF_REF_CHAIN (use)->ref; |
6848da6a ZD |
378 | |
379 | /* We do not handle setting only part of the register. */ | |
57512f53 | 380 | if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE) |
6848da6a ZD |
381 | return GRD_INVALID; |
382 | ||
03fd2215 ZD |
383 | def_insn = DF_REF_INSN (adef); |
384 | def_bb = DF_REF_BB (adef); | |
385 | use_bb = BLOCK_FOR_INSN (insn); | |
50654f6c | 386 | |
03fd2215 | 387 | if (use_bb == def_bb) |
6fb5fa3c | 388 | dom_p = (DF_INSN_LUID (def_insn) < DF_INSN_LUID (insn)); |
03fd2215 ZD |
389 | else |
390 | dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb); | |
50654f6c | 391 | |
03fd2215 ZD |
392 | if (dom_p) |
393 | { | |
394 | *def = adef; | |
395 | return GRD_SINGLE_DOM; | |
50654f6c | 396 | } |
03fd2215 ZD |
397 | |
398 | /* The definition does not dominate the use. This is still OK if | |
399 | this may be a use of a biv, i.e. if the def_bb dominates loop | |
400 | latch. */ | |
401 | if (just_once_each_iteration_p (current_loop, def_bb)) | |
402 | return GRD_MAYBE_BIV; | |
403 | ||
404 | return GRD_INVALID; | |
50654f6c ZD |
405 | } |
406 | ||
407 | /* Sets IV to invariant CST in MODE. Always returns true (just for | |
408 | consistency with other iv manipulation functions that may fail). */ | |
409 | ||
410 | static bool | |
ef4bddc2 | 411 | iv_constant (struct rtx_iv *iv, rtx cst, machine_mode mode) |
50654f6c ZD |
412 | { |
413 | if (mode == VOIDmode) | |
414 | mode = GET_MODE (cst); | |
415 | ||
50654f6c ZD |
416 | iv->mode = mode; |
417 | iv->base = cst; | |
418 | iv->step = const0_rtx; | |
419 | iv->first_special = false; | |
1c1ad7bb | 420 | iv->extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
421 | iv->extend_mode = iv->mode; |
422 | iv->delta = const0_rtx; | |
423 | iv->mult = const1_rtx; | |
424 | ||
425 | return true; | |
426 | } | |
427 | ||
428 | /* Evaluates application of subreg to MODE on IV. */ | |
429 | ||
430 | static bool | |
ef4bddc2 | 431 | iv_subreg (struct rtx_iv *iv, machine_mode mode) |
50654f6c | 432 | { |
6797f908 ZD |
433 | /* If iv is invariant, just calculate the new value. */ |
434 | if (iv->step == const0_rtx | |
435 | && !iv->first_special) | |
436 | { | |
437 | rtx val = get_iv_value (iv, const0_rtx); | |
50fae5a6 JJ |
438 | val = lowpart_subreg (mode, val, |
439 | iv->extend == IV_UNKNOWN_EXTEND | |
440 | ? iv->mode : iv->extend_mode); | |
6797f908 ZD |
441 | |
442 | iv->base = val; | |
1c1ad7bb | 443 | iv->extend = IV_UNKNOWN_EXTEND; |
6797f908 ZD |
444 | iv->mode = iv->extend_mode = mode; |
445 | iv->delta = const0_rtx; | |
446 | iv->mult = const1_rtx; | |
447 | return true; | |
448 | } | |
449 | ||
50654f6c ZD |
450 | if (iv->extend_mode == mode) |
451 | return true; | |
452 | ||
453 | if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode)) | |
454 | return false; | |
455 | ||
1c1ad7bb | 456 | iv->extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
457 | iv->mode = mode; |
458 | ||
459 | iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, | |
460 | simplify_gen_binary (MULT, iv->extend_mode, | |
461 | iv->base, iv->mult)); | |
462 | iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult); | |
463 | iv->mult = const1_rtx; | |
464 | iv->delta = const0_rtx; | |
465 | iv->first_special = false; | |
466 | ||
467 | return true; | |
468 | } | |
469 | ||
470 | /* Evaluates application of EXTEND to MODE on IV. */ | |
471 | ||
472 | static bool | |
ef4bddc2 | 473 | iv_extend (struct rtx_iv *iv, enum iv_extend_code extend, machine_mode mode) |
50654f6c | 474 | { |
6797f908 ZD |
475 | /* If iv is invariant, just calculate the new value. */ |
476 | if (iv->step == const0_rtx | |
477 | && !iv->first_special) | |
478 | { | |
479 | rtx val = get_iv_value (iv, const0_rtx); | |
50fae5a6 JJ |
480 | if (iv->extend_mode != iv->mode |
481 | && iv->extend != IV_UNKNOWN_EXTEND | |
482 | && iv->extend != extend) | |
483 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); | |
1c1ad7bb | 484 | val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode, |
50fae5a6 JJ |
485 | val, |
486 | iv->extend == extend | |
487 | ? iv->extend_mode : iv->mode); | |
6797f908 | 488 | iv->base = val; |
1c1ad7bb | 489 | iv->extend = IV_UNKNOWN_EXTEND; |
6797f908 ZD |
490 | iv->mode = iv->extend_mode = mode; |
491 | iv->delta = const0_rtx; | |
492 | iv->mult = const1_rtx; | |
493 | return true; | |
494 | } | |
495 | ||
50654f6c ZD |
496 | if (mode != iv->extend_mode) |
497 | return false; | |
498 | ||
1c1ad7bb | 499 | if (iv->extend != IV_UNKNOWN_EXTEND |
50654f6c ZD |
500 | && iv->extend != extend) |
501 | return false; | |
502 | ||
503 | iv->extend = extend; | |
504 | ||
505 | return true; | |
506 | } | |
507 | ||
508 | /* Evaluates negation of IV. */ | |
509 | ||
510 | static bool | |
511 | iv_neg (struct rtx_iv *iv) | |
512 | { | |
1c1ad7bb | 513 | if (iv->extend == IV_UNKNOWN_EXTEND) |
50654f6c ZD |
514 | { |
515 | iv->base = simplify_gen_unary (NEG, iv->extend_mode, | |
516 | iv->base, iv->extend_mode); | |
517 | iv->step = simplify_gen_unary (NEG, iv->extend_mode, | |
518 | iv->step, iv->extend_mode); | |
519 | } | |
520 | else | |
521 | { | |
522 | iv->delta = simplify_gen_unary (NEG, iv->extend_mode, | |
523 | iv->delta, iv->extend_mode); | |
524 | iv->mult = simplify_gen_unary (NEG, iv->extend_mode, | |
525 | iv->mult, iv->extend_mode); | |
526 | } | |
527 | ||
528 | return true; | |
529 | } | |
530 | ||
531 | /* Evaluates addition or subtraction (according to OP) of IV1 to IV0. */ | |
532 | ||
533 | static bool | |
534 | iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) | |
535 | { | |
ef4bddc2 | 536 | machine_mode mode; |
50654f6c ZD |
537 | rtx arg; |
538 | ||
a1105617 | 539 | /* Extend the constant to extend_mode of the other operand if necessary. */ |
1c1ad7bb | 540 | if (iv0->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
541 | && iv0->mode == iv0->extend_mode |
542 | && iv0->step == const0_rtx | |
543 | && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode)) | |
544 | { | |
545 | iv0->extend_mode = iv1->extend_mode; | |
546 | iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode, | |
547 | iv0->base, iv0->mode); | |
548 | } | |
1c1ad7bb | 549 | if (iv1->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
550 | && iv1->mode == iv1->extend_mode |
551 | && iv1->step == const0_rtx | |
552 | && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode)) | |
553 | { | |
554 | iv1->extend_mode = iv0->extend_mode; | |
555 | iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode, | |
556 | iv1->base, iv1->mode); | |
557 | } | |
558 | ||
559 | mode = iv0->extend_mode; | |
560 | if (mode != iv1->extend_mode) | |
561 | return false; | |
562 | ||
1c1ad7bb SB |
563 | if (iv0->extend == IV_UNKNOWN_EXTEND |
564 | && iv1->extend == IV_UNKNOWN_EXTEND) | |
50654f6c ZD |
565 | { |
566 | if (iv0->mode != iv1->mode) | |
567 | return false; | |
568 | ||
569 | iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base); | |
570 | iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step); | |
571 | ||
572 | return true; | |
573 | } | |
574 | ||
575 | /* Handle addition of constant. */ | |
1c1ad7bb | 576 | if (iv1->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
577 | && iv1->mode == mode |
578 | && iv1->step == const0_rtx) | |
579 | { | |
580 | iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base); | |
581 | return true; | |
582 | } | |
583 | ||
1c1ad7bb | 584 | if (iv0->extend == IV_UNKNOWN_EXTEND |
50654f6c ZD |
585 | && iv0->mode == mode |
586 | && iv0->step == const0_rtx) | |
587 | { | |
588 | arg = iv0->base; | |
589 | *iv0 = *iv1; | |
590 | if (op == MINUS | |
591 | && !iv_neg (iv0)) | |
592 | return false; | |
593 | ||
594 | iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg); | |
595 | return true; | |
596 | } | |
597 | ||
598 | return false; | |
599 | } | |
600 | ||
601 | /* Evaluates multiplication of IV by constant CST. */ | |
602 | ||
603 | static bool | |
604 | iv_mult (struct rtx_iv *iv, rtx mby) | |
605 | { | |
ef4bddc2 | 606 | machine_mode mode = iv->extend_mode; |
50654f6c ZD |
607 | |
608 | if (GET_MODE (mby) != VOIDmode | |
609 | && GET_MODE (mby) != mode) | |
610 | return false; | |
611 | ||
1c1ad7bb | 612 | if (iv->extend == IV_UNKNOWN_EXTEND) |
50654f6c ZD |
613 | { |
614 | iv->base = simplify_gen_binary (MULT, mode, iv->base, mby); | |
615 | iv->step = simplify_gen_binary (MULT, mode, iv->step, mby); | |
616 | } | |
617 | else | |
618 | { | |
619 | iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby); | |
620 | iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby); | |
621 | } | |
622 | ||
623 | return true; | |
624 | } | |
625 | ||
abe0d774 RE |
626 | /* Evaluates shift of IV by constant CST. */ |
627 | ||
628 | static bool | |
629 | iv_shift (struct rtx_iv *iv, rtx mby) | |
630 | { | |
ef4bddc2 | 631 | machine_mode mode = iv->extend_mode; |
abe0d774 RE |
632 | |
633 | if (GET_MODE (mby) != VOIDmode | |
634 | && GET_MODE (mby) != mode) | |
635 | return false; | |
636 | ||
1c1ad7bb | 637 | if (iv->extend == IV_UNKNOWN_EXTEND) |
abe0d774 RE |
638 | { |
639 | iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby); | |
640 | iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby); | |
641 | } | |
642 | else | |
643 | { | |
644 | iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby); | |
645 | iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby); | |
646 | } | |
647 | ||
648 | return true; | |
649 | } | |
650 | ||
50654f6c | 651 | /* The recursive part of get_biv_step. Gets the value of the single value |
03fd2215 | 652 | defined by DEF wrto initial value of REG inside loop, in shape described |
50654f6c ZD |
653 | at get_biv_step. */ |
654 | ||
655 | static bool | |
57512f53 | 656 | get_biv_step_1 (df_ref def, rtx reg, |
ef4bddc2 RS |
657 | rtx *inner_step, machine_mode *inner_mode, |
658 | enum iv_extend_code *extend, machine_mode outer_mode, | |
50654f6c ZD |
659 | rtx *outer_step) |
660 | { | |
3c3f4b56 | 661 | rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX; |
03fd2215 | 662 | rtx next, nextr, tmp; |
50654f6c | 663 | enum rtx_code code; |
1b20d55a | 664 | rtx_insn *insn = DF_REF_INSN (def); |
57512f53 | 665 | df_ref next_def; |
03fd2215 | 666 | enum iv_grd_result res; |
50654f6c ZD |
667 | |
668 | set = single_set (insn); | |
03fd2215 ZD |
669 | if (!set) |
670 | return false; | |
671 | ||
50654f6c | 672 | rhs = find_reg_equal_equiv_note (insn); |
0aea6467 ZD |
673 | if (rhs) |
674 | rhs = XEXP (rhs, 0); | |
675 | else | |
50654f6c | 676 | rhs = SET_SRC (set); |
50654f6c ZD |
677 | |
678 | code = GET_CODE (rhs); | |
679 | switch (code) | |
680 | { | |
681 | case SUBREG: | |
682 | case REG: | |
683 | next = rhs; | |
684 | break; | |
685 | ||
686 | case PLUS: | |
687 | case MINUS: | |
688 | op0 = XEXP (rhs, 0); | |
689 | op1 = XEXP (rhs, 1); | |
690 | ||
691 | if (code == PLUS && CONSTANT_P (op0)) | |
692 | { | |
693 | tmp = op0; op0 = op1; op1 = tmp; | |
694 | } | |
695 | ||
696 | if (!simple_reg_p (op0) | |
697 | || !CONSTANT_P (op1)) | |
698 | return false; | |
699 | ||
700 | if (GET_MODE (rhs) != outer_mode) | |
701 | { | |
702 | /* ppc64 uses expressions like | |
703 | ||
704 | (set x:SI (plus:SI (subreg:SI y:DI) 1)). | |
705 | ||
706 | this is equivalent to | |
707 | ||
708 | (set x':DI (plus:DI y:DI 1)) | |
709 | (set x:SI (subreg:SI (x':DI)). */ | |
710 | if (GET_CODE (op0) != SUBREG) | |
711 | return false; | |
712 | if (GET_MODE (SUBREG_REG (op0)) != outer_mode) | |
713 | return false; | |
714 | } | |
715 | ||
716 | next = op0; | |
717 | break; | |
718 | ||
719 | case SIGN_EXTEND: | |
720 | case ZERO_EXTEND: | |
721 | if (GET_MODE (rhs) != outer_mode) | |
722 | return false; | |
723 | ||
724 | op0 = XEXP (rhs, 0); | |
725 | if (!simple_reg_p (op0)) | |
726 | return false; | |
727 | ||
728 | next = op0; | |
729 | break; | |
730 | ||
731 | default: | |
732 | return false; | |
733 | } | |
734 | ||
735 | if (GET_CODE (next) == SUBREG) | |
736 | { | |
737 | if (!subreg_lowpart_p (next)) | |
738 | return false; | |
739 | ||
740 | nextr = SUBREG_REG (next); | |
741 | if (GET_MODE (nextr) != outer_mode) | |
742 | return false; | |
743 | } | |
744 | else | |
745 | nextr = next; | |
746 | ||
03fd2215 ZD |
747 | res = iv_get_reaching_def (insn, nextr, &next_def); |
748 | ||
749 | if (res == GRD_INVALID || res == GRD_INVARIANT) | |
50654f6c ZD |
750 | return false; |
751 | ||
03fd2215 | 752 | if (res == GRD_MAYBE_BIV) |
50654f6c ZD |
753 | { |
754 | if (!rtx_equal_p (nextr, reg)) | |
755 | return false; | |
756 | ||
757 | *inner_step = const0_rtx; | |
1c1ad7bb | 758 | *extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
759 | *inner_mode = outer_mode; |
760 | *outer_step = const0_rtx; | |
761 | } | |
03fd2215 | 762 | else if (!get_biv_step_1 (next_def, reg, |
50654f6c ZD |
763 | inner_step, inner_mode, extend, outer_mode, |
764 | outer_step)) | |
765 | return false; | |
766 | ||
767 | if (GET_CODE (next) == SUBREG) | |
768 | { | |
ef4bddc2 | 769 | machine_mode amode = GET_MODE (next); |
50654f6c ZD |
770 | |
771 | if (GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode)) | |
772 | return false; | |
773 | ||
774 | *inner_mode = amode; | |
775 | *inner_step = simplify_gen_binary (PLUS, outer_mode, | |
776 | *inner_step, *outer_step); | |
777 | *outer_step = const0_rtx; | |
1c1ad7bb | 778 | *extend = IV_UNKNOWN_EXTEND; |
50654f6c ZD |
779 | } |
780 | ||
781 | switch (code) | |
782 | { | |
783 | case REG: | |
784 | case SUBREG: | |
785 | break; | |
786 | ||
787 | case PLUS: | |
788 | case MINUS: | |
789 | if (*inner_mode == outer_mode | |
790 | /* See comment in previous switch. */ | |
791 | || GET_MODE (rhs) != outer_mode) | |
792 | *inner_step = simplify_gen_binary (code, outer_mode, | |
793 | *inner_step, op1); | |
794 | else | |
795 | *outer_step = simplify_gen_binary (code, outer_mode, | |
796 | *outer_step, op1); | |
797 | break; | |
798 | ||
799 | case SIGN_EXTEND: | |
800 | case ZERO_EXTEND: | |
b5e624c6 | 801 | gcc_assert (GET_MODE (op0) == *inner_mode |
1c1ad7bb | 802 | && *extend == IV_UNKNOWN_EXTEND |
b5e624c6 | 803 | && *outer_step == const0_rtx); |
50654f6c | 804 | |
1c1ad7bb | 805 | *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND; |
50654f6c ZD |
806 | break; |
807 | ||
808 | default: | |
03fd2215 | 809 | return false; |
50654f6c ZD |
810 | } |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
815 | /* Gets the operation on register REG inside loop, in shape | |
816 | ||
817 | OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP)) | |
818 | ||
03fd2215 ZD |
819 | If the operation cannot be described in this shape, return false. |
820 | LAST_DEF is the definition of REG that dominates loop latch. */ | |
50654f6c ZD |
821 | |
822 | static bool | |
57512f53 | 823 | get_biv_step (df_ref last_def, rtx reg, rtx *inner_step, |
ef4bddc2 RS |
824 | machine_mode *inner_mode, enum iv_extend_code *extend, |
825 | machine_mode *outer_mode, rtx *outer_step) | |
50654f6c ZD |
826 | { |
827 | *outer_mode = GET_MODE (reg); | |
828 | ||
03fd2215 | 829 | if (!get_biv_step_1 (last_def, reg, |
50654f6c ZD |
830 | inner_step, inner_mode, extend, *outer_mode, |
831 | outer_step)) | |
832 | return false; | |
833 | ||
1c1ad7bb | 834 | gcc_assert ((*inner_mode == *outer_mode) != (*extend != IV_UNKNOWN_EXTEND)); |
b5e624c6 | 835 | gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx); |
50654f6c ZD |
836 | |
837 | return true; | |
838 | } | |
839 | ||
03fd2215 ZD |
840 | /* Records information that DEF is induction variable IV. */ |
841 | ||
842 | static void | |
57512f53 | 843 | record_iv (df_ref def, struct rtx_iv *iv) |
03fd2215 | 844 | { |
5ed6ace5 | 845 | struct rtx_iv *recorded_iv = XNEW (struct rtx_iv); |
03fd2215 ZD |
846 | |
847 | *recorded_iv = *iv; | |
6fb5fa3c | 848 | check_iv_ref_table_size (); |
03fd2215 ZD |
849 | DF_REF_IV_SET (def, recorded_iv); |
850 | } | |
851 | ||
852 | /* If DEF was already analyzed for bivness, store the description of the biv to | |
853 | IV and return true. Otherwise return false. */ | |
854 | ||
855 | static bool | |
856 | analyzed_for_bivness_p (rtx def, struct rtx_iv *iv) | |
857 | { | |
c203e8a7 | 858 | struct biv_entry *biv = bivs->find_with_hash (def, REGNO (def)); |
03fd2215 ZD |
859 | |
860 | if (!biv) | |
861 | return false; | |
862 | ||
863 | *iv = biv->iv; | |
864 | return true; | |
865 | } | |
866 | ||
867 | static void | |
868 | record_biv (rtx def, struct rtx_iv *iv) | |
869 | { | |
5ed6ace5 | 870 | struct biv_entry *biv = XNEW (struct biv_entry); |
c203e8a7 | 871 | biv_entry **slot = bivs->find_slot_with_hash (def, REGNO (def), INSERT); |
03fd2215 ZD |
872 | |
873 | biv->regno = REGNO (def); | |
874 | biv->iv = *iv; | |
875 | gcc_assert (!*slot); | |
876 | *slot = biv; | |
877 | } | |
878 | ||
50654f6c ZD |
879 | /* Determines whether DEF is a biv and if so, stores its description |
880 | to *IV. */ | |
881 | ||
882 | static bool | |
6d4e0ecc | 883 | iv_analyze_biv (rtx def, struct rtx_iv *iv) |
50654f6c | 884 | { |
50654f6c | 885 | rtx inner_step, outer_step; |
ef4bddc2 | 886 | machine_mode inner_mode, outer_mode; |
1c1ad7bb | 887 | enum iv_extend_code extend; |
57512f53 | 888 | df_ref last_def; |
50654f6c | 889 | |
c263766c | 890 | if (dump_file) |
50654f6c | 891 | { |
cc9795d4 | 892 | fprintf (dump_file, "Analyzing "); |
c263766c RH |
893 | print_rtl (dump_file, def); |
894 | fprintf (dump_file, " for bivness.\n"); | |
50654f6c | 895 | } |
b8698a0f | 896 | |
50654f6c ZD |
897 | if (!REG_P (def)) |
898 | { | |
899 | if (!CONSTANT_P (def)) | |
900 | return false; | |
901 | ||
902 | return iv_constant (iv, def, VOIDmode); | |
903 | } | |
904 | ||
03fd2215 | 905 | if (!latch_dominating_def (def, &last_def)) |
50654f6c | 906 | { |
c263766c RH |
907 | if (dump_file) |
908 | fprintf (dump_file, " not simple.\n"); | |
50654f6c ZD |
909 | return false; |
910 | } | |
911 | ||
03fd2215 ZD |
912 | if (!last_def) |
913 | return iv_constant (iv, def, VOIDmode); | |
914 | ||
915 | if (analyzed_for_bivness_p (def, iv)) | |
50654f6c | 916 | { |
c263766c RH |
917 | if (dump_file) |
918 | fprintf (dump_file, " already analysed.\n"); | |
50654f6c ZD |
919 | return iv->base != NULL_RTX; |
920 | } | |
921 | ||
03fd2215 | 922 | if (!get_biv_step (last_def, def, &inner_step, &inner_mode, &extend, |
50654f6c ZD |
923 | &outer_mode, &outer_step)) |
924 | { | |
925 | iv->base = NULL_RTX; | |
926 | goto end; | |
927 | } | |
928 | ||
929 | /* Loop transforms base to es (base + inner_step) + outer_step, | |
930 | where es means extend of subreg between inner_mode and outer_mode. | |
931 | The corresponding induction variable is | |
932 | ||
933 | es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step */ | |
934 | ||
935 | iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step); | |
936 | iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step); | |
937 | iv->mode = inner_mode; | |
938 | iv->extend_mode = outer_mode; | |
939 | iv->extend = extend; | |
940 | iv->mult = const1_rtx; | |
941 | iv->delta = outer_step; | |
942 | iv->first_special = inner_mode != outer_mode; | |
943 | ||
c263766c RH |
944 | end: |
945 | if (dump_file) | |
50654f6c | 946 | { |
c263766c RH |
947 | fprintf (dump_file, " "); |
948 | dump_iv_info (dump_file, iv); | |
949 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
950 | } |
951 | ||
03fd2215 | 952 | record_biv (def, iv); |
50654f6c ZD |
953 | return iv->base != NULL_RTX; |
954 | } | |
955 | ||
b8698a0f | 956 | /* Analyzes expression RHS used at INSN and stores the result to *IV. |
03fd2215 | 957 | The mode of the induction variable is MODE. */ |
50654f6c | 958 | |
03fd2215 | 959 | bool |
ef4bddc2 | 960 | iv_analyze_expr (rtx_insn *insn, rtx rhs, machine_mode mode, |
1b20d55a | 961 | struct rtx_iv *iv) |
50654f6c | 962 | { |
03fd2215 ZD |
963 | rtx mby = NULL_RTX, tmp; |
964 | rtx op0 = NULL_RTX, op1 = NULL_RTX; | |
965 | struct rtx_iv iv0, iv1; | |
966 | enum rtx_code code = GET_CODE (rhs); | |
ef4bddc2 | 967 | machine_mode omode = mode; |
50654f6c | 968 | |
03fd2215 ZD |
969 | iv->mode = VOIDmode; |
970 | iv->base = NULL_RTX; | |
971 | iv->step = NULL_RTX; | |
50654f6c | 972 | |
03fd2215 | 973 | gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode); |
50654f6c | 974 | |
03fd2215 ZD |
975 | if (CONSTANT_P (rhs) |
976 | || REG_P (rhs) | |
977 | || code == SUBREG) | |
50654f6c | 978 | { |
03fd2215 ZD |
979 | if (!iv_analyze_op (insn, rhs, iv)) |
980 | return false; | |
b8698a0f | 981 | |
03fd2215 | 982 | if (iv->mode == VOIDmode) |
50654f6c | 983 | { |
03fd2215 ZD |
984 | iv->mode = mode; |
985 | iv->extend_mode = mode; | |
50654f6c | 986 | } |
03fd2215 ZD |
987 | |
988 | return true; | |
50654f6c ZD |
989 | } |
990 | ||
03fd2215 | 991 | switch (code) |
50654f6c | 992 | { |
03fd2215 ZD |
993 | case REG: |
994 | op0 = rhs; | |
995 | break; | |
50654f6c | 996 | |
03fd2215 ZD |
997 | case SIGN_EXTEND: |
998 | case ZERO_EXTEND: | |
999 | case NEG: | |
1000 | op0 = XEXP (rhs, 0); | |
1001 | omode = GET_MODE (op0); | |
1002 | break; | |
1003 | ||
1004 | case PLUS: | |
1005 | case MINUS: | |
1006 | op0 = XEXP (rhs, 0); | |
1007 | op1 = XEXP (rhs, 1); | |
1008 | break; | |
1009 | ||
1010 | case MULT: | |
1011 | op0 = XEXP (rhs, 0); | |
1012 | mby = XEXP (rhs, 1); | |
1013 | if (!CONSTANT_P (mby)) | |
50654f6c | 1014 | { |
03fd2215 ZD |
1015 | tmp = op0; |
1016 | op0 = mby; | |
1017 | mby = tmp; | |
50654f6c | 1018 | } |
03fd2215 ZD |
1019 | if (!CONSTANT_P (mby)) |
1020 | return false; | |
1021 | break; | |
50654f6c | 1022 | |
03fd2215 ZD |
1023 | case ASHIFT: |
1024 | op0 = XEXP (rhs, 0); | |
1025 | mby = XEXP (rhs, 1); | |
1026 | if (!CONSTANT_P (mby)) | |
1027 | return false; | |
1028 | break; | |
1029 | ||
1030 | default: | |
50654f6c ZD |
1031 | return false; |
1032 | } | |
1033 | ||
03fd2215 ZD |
1034 | if (op0 |
1035 | && !iv_analyze_expr (insn, op0, omode, &iv0)) | |
1036 | return false; | |
50654f6c | 1037 | |
03fd2215 ZD |
1038 | if (op1 |
1039 | && !iv_analyze_expr (insn, op1, omode, &iv1)) | |
50654f6c ZD |
1040 | return false; |
1041 | ||
03fd2215 | 1042 | switch (code) |
50654f6c | 1043 | { |
03fd2215 | 1044 | case SIGN_EXTEND: |
1c1ad7bb SB |
1045 | if (!iv_extend (&iv0, IV_SIGN_EXTEND, mode)) |
1046 | return false; | |
1047 | break; | |
1048 | ||
03fd2215 | 1049 | case ZERO_EXTEND: |
1c1ad7bb | 1050 | if (!iv_extend (&iv0, IV_ZERO_EXTEND, mode)) |
03fd2215 ZD |
1051 | return false; |
1052 | break; | |
1053 | ||
1054 | case NEG: | |
1055 | if (!iv_neg (&iv0)) | |
50654f6c | 1056 | return false; |
03fd2215 | 1057 | break; |
50654f6c | 1058 | |
03fd2215 ZD |
1059 | case PLUS: |
1060 | case MINUS: | |
1061 | if (!iv_add (&iv0, &iv1, code)) | |
50654f6c | 1062 | return false; |
03fd2215 | 1063 | break; |
50654f6c | 1064 | |
03fd2215 ZD |
1065 | case MULT: |
1066 | if (!iv_mult (&iv0, mby)) | |
1067 | return false; | |
1068 | break; | |
1069 | ||
1070 | case ASHIFT: | |
1071 | if (!iv_shift (&iv0, mby)) | |
1072 | return false; | |
1073 | break; | |
1074 | ||
1075 | default: | |
1076 | break; | |
50654f6c ZD |
1077 | } |
1078 | ||
03fd2215 ZD |
1079 | *iv = iv0; |
1080 | return iv->base != NULL_RTX; | |
1081 | } | |
1082 | ||
1083 | /* Analyzes iv DEF and stores the result to *IV. */ | |
1084 | ||
1085 | static bool | |
57512f53 | 1086 | iv_analyze_def (df_ref def, struct rtx_iv *iv) |
03fd2215 | 1087 | { |
1b20d55a | 1088 | rtx_insn *insn = DF_REF_INSN (def); |
03fd2215 ZD |
1089 | rtx reg = DF_REF_REG (def); |
1090 | rtx set, rhs; | |
50654f6c | 1091 | |
c263766c | 1092 | if (dump_file) |
50654f6c | 1093 | { |
4dad0aca | 1094 | fprintf (dump_file, "Analyzing def of "); |
03fd2215 | 1095 | print_rtl (dump_file, reg); |
c263766c RH |
1096 | fprintf (dump_file, " in insn "); |
1097 | print_rtl_single (dump_file, insn); | |
50654f6c | 1098 | } |
b8698a0f | 1099 | |
6fb5fa3c | 1100 | check_iv_ref_table_size (); |
03fd2215 | 1101 | if (DF_REF_IV (def)) |
50654f6c | 1102 | { |
c263766c RH |
1103 | if (dump_file) |
1104 | fprintf (dump_file, " already analysed.\n"); | |
03fd2215 | 1105 | *iv = *DF_REF_IV (def); |
50654f6c ZD |
1106 | return iv->base != NULL_RTX; |
1107 | } | |
1108 | ||
1109 | iv->mode = VOIDmode; | |
1110 | iv->base = NULL_RTX; | |
1111 | iv->step = NULL_RTX; | |
1112 | ||
6fb5fa3c DB |
1113 | if (!REG_P (reg)) |
1114 | return false; | |
1115 | ||
50654f6c | 1116 | set = single_set (insn); |
6fb5fa3c DB |
1117 | if (!set) |
1118 | return false; | |
1119 | ||
1120 | if (!REG_P (SET_DEST (set))) | |
03fd2215 ZD |
1121 | return false; |
1122 | ||
6fb5fa3c | 1123 | gcc_assert (SET_DEST (set) == reg); |
50654f6c | 1124 | rhs = find_reg_equal_equiv_note (insn); |
0aea6467 ZD |
1125 | if (rhs) |
1126 | rhs = XEXP (rhs, 0); | |
1127 | else | |
50654f6c | 1128 | rhs = SET_SRC (set); |
50654f6c | 1129 | |
03fd2215 ZD |
1130 | iv_analyze_expr (insn, rhs, GET_MODE (reg), iv); |
1131 | record_iv (def, iv); | |
1132 | ||
1133 | if (dump_file) | |
50654f6c | 1134 | { |
03fd2215 ZD |
1135 | print_rtl (dump_file, reg); |
1136 | fprintf (dump_file, " in insn "); | |
1137 | print_rtl_single (dump_file, insn); | |
1138 | fprintf (dump_file, " is "); | |
1139 | dump_iv_info (dump_file, iv); | |
1140 | fprintf (dump_file, "\n"); | |
50654f6c | 1141 | } |
50654f6c | 1142 | |
03fd2215 ZD |
1143 | return iv->base != NULL_RTX; |
1144 | } | |
50654f6c | 1145 | |
03fd2215 | 1146 | /* Analyzes operand OP of INSN and stores the result to *IV. */ |
50654f6c | 1147 | |
03fd2215 | 1148 | static bool |
1b20d55a | 1149 | iv_analyze_op (rtx_insn *insn, rtx op, struct rtx_iv *iv) |
03fd2215 | 1150 | { |
57512f53 | 1151 | df_ref def = NULL; |
03fd2215 | 1152 | enum iv_grd_result res; |
abe0d774 | 1153 | |
03fd2215 ZD |
1154 | if (dump_file) |
1155 | { | |
4dad0aca | 1156 | fprintf (dump_file, "Analyzing operand "); |
03fd2215 ZD |
1157 | print_rtl (dump_file, op); |
1158 | fprintf (dump_file, " of insn "); | |
1159 | print_rtl_single (dump_file, insn); | |
1160 | } | |
abe0d774 | 1161 | |
cdf1bf8b | 1162 | if (function_invariant_p (op)) |
03fd2215 ZD |
1163 | res = GRD_INVARIANT; |
1164 | else if (GET_CODE (op) == SUBREG) | |
1165 | { | |
1166 | if (!subreg_lowpart_p (op)) | |
1167 | return false; | |
50654f6c | 1168 | |
03fd2215 ZD |
1169 | if (!iv_analyze_op (insn, SUBREG_REG (op), iv)) |
1170 | return false; | |
50654f6c | 1171 | |
03fd2215 ZD |
1172 | return iv_subreg (iv, GET_MODE (op)); |
1173 | } | |
1174 | else | |
50654f6c | 1175 | { |
03fd2215 ZD |
1176 | res = iv_get_reaching_def (insn, op, &def); |
1177 | if (res == GRD_INVALID) | |
50654f6c | 1178 | { |
03fd2215 ZD |
1179 | if (dump_file) |
1180 | fprintf (dump_file, " not simple.\n"); | |
1181 | return false; | |
50654f6c ZD |
1182 | } |
1183 | } | |
1184 | ||
03fd2215 | 1185 | if (res == GRD_INVARIANT) |
50654f6c | 1186 | { |
03fd2215 | 1187 | iv_constant (iv, op, VOIDmode); |
50654f6c | 1188 | |
03fd2215 | 1189 | if (dump_file) |
50654f6c | 1190 | { |
03fd2215 ZD |
1191 | fprintf (dump_file, " "); |
1192 | dump_iv_info (dump_file, iv); | |
1193 | fprintf (dump_file, "\n"); | |
50654f6c | 1194 | } |
03fd2215 | 1195 | return true; |
50654f6c ZD |
1196 | } |
1197 | ||
03fd2215 ZD |
1198 | if (res == GRD_MAYBE_BIV) |
1199 | return iv_analyze_biv (op, iv); | |
50654f6c | 1200 | |
03fd2215 ZD |
1201 | return iv_analyze_def (def, iv); |
1202 | } | |
50654f6c | 1203 | |
03fd2215 | 1204 | /* Analyzes value VAL at INSN and stores the result to *IV. */ |
50654f6c | 1205 | |
03fd2215 | 1206 | bool |
1b20d55a | 1207 | iv_analyze (rtx_insn *insn, rtx val, struct rtx_iv *iv) |
03fd2215 ZD |
1208 | { |
1209 | rtx reg; | |
50654f6c | 1210 | |
03fd2215 ZD |
1211 | /* We must find the insn in that val is used, so that we get to UD chains. |
1212 | Since the function is sometimes called on result of get_condition, | |
1213 | this does not necessarily have to be directly INSN; scan also the | |
1214 | following insns. */ | |
1215 | if (simple_reg_p (val)) | |
1216 | { | |
1217 | if (GET_CODE (val) == SUBREG) | |
1218 | reg = SUBREG_REG (val); | |
1219 | else | |
1220 | reg = val; | |
abe0d774 | 1221 | |
6fb5fa3c | 1222 | while (!df_find_use (insn, reg)) |
03fd2215 | 1223 | insn = NEXT_INSN (insn); |
50654f6c ZD |
1224 | } |
1225 | ||
03fd2215 ZD |
1226 | return iv_analyze_op (insn, val, iv); |
1227 | } | |
50654f6c | 1228 | |
03fd2215 | 1229 | /* Analyzes definition of DEF in INSN and stores the result to IV. */ |
50654f6c | 1230 | |
03fd2215 | 1231 | bool |
1b20d55a | 1232 | iv_analyze_result (rtx_insn *insn, rtx def, struct rtx_iv *iv) |
03fd2215 | 1233 | { |
57512f53 | 1234 | df_ref adef; |
50654f6c | 1235 | |
6fb5fa3c | 1236 | adef = df_find_def (insn, def); |
03fd2215 ZD |
1237 | if (!adef) |
1238 | return false; | |
1239 | ||
1240 | return iv_analyze_def (adef, iv); | |
50654f6c ZD |
1241 | } |
1242 | ||
03fd2215 | 1243 | /* Checks whether definition of register REG in INSN is a basic induction |
113d659a ZD |
1244 | variable. IV analysis must have been initialized (via a call to |
1245 | iv_analysis_loop_init) for this function to produce a result. */ | |
1246 | ||
1247 | bool | |
1b20d55a | 1248 | biv_p (rtx_insn *insn, rtx reg) |
113d659a ZD |
1249 | { |
1250 | struct rtx_iv iv; | |
57512f53 | 1251 | df_ref def, last_def; |
113d659a | 1252 | |
03fd2215 | 1253 | if (!simple_reg_p (reg)) |
113d659a ZD |
1254 | return false; |
1255 | ||
6fb5fa3c | 1256 | def = df_find_def (insn, reg); |
03fd2215 ZD |
1257 | gcc_assert (def != NULL); |
1258 | if (!latch_dominating_def (reg, &last_def)) | |
1259 | return false; | |
1260 | if (last_def != def) | |
113d659a ZD |
1261 | return false; |
1262 | ||
03fd2215 ZD |
1263 | if (!iv_analyze_biv (reg, &iv)) |
1264 | return false; | |
1265 | ||
1266 | return iv.step != const0_rtx; | |
113d659a ZD |
1267 | } |
1268 | ||
50654f6c ZD |
1269 | /* Calculates value of IV at ITERATION-th iteration. */ |
1270 | ||
1271 | rtx | |
1272 | get_iv_value (struct rtx_iv *iv, rtx iteration) | |
1273 | { | |
1274 | rtx val; | |
1275 | ||
1276 | /* We would need to generate some if_then_else patterns, and so far | |
1277 | it is not needed anywhere. */ | |
b5e624c6 | 1278 | gcc_assert (!iv->first_special); |
50654f6c ZD |
1279 | |
1280 | if (iv->step != const0_rtx && iteration != const0_rtx) | |
1281 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base, | |
1282 | simplify_gen_binary (MULT, iv->extend_mode, | |
1283 | iv->step, iteration)); | |
1284 | else | |
1285 | val = iv->base; | |
1286 | ||
1287 | if (iv->extend_mode == iv->mode) | |
1288 | return val; | |
1289 | ||
6c3b938d | 1290 | val = lowpart_subreg (iv->mode, val, iv->extend_mode); |
50654f6c | 1291 | |
1c1ad7bb | 1292 | if (iv->extend == IV_UNKNOWN_EXTEND) |
50654f6c ZD |
1293 | return val; |
1294 | ||
1c1ad7bb SB |
1295 | val = simplify_gen_unary (iv_extend_to_rtx_code (iv->extend), |
1296 | iv->extend_mode, val, iv->mode); | |
50654f6c ZD |
1297 | val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, |
1298 | simplify_gen_binary (MULT, iv->extend_mode, | |
1299 | iv->mult, val)); | |
1300 | ||
1301 | return val; | |
1302 | } | |
1303 | ||
1304 | /* Free the data for an induction variable analysis. */ | |
1305 | ||
1306 | void | |
1307 | iv_analysis_done (void) | |
1308 | { | |
6fb5fa3c | 1309 | if (!clean_slate) |
50654f6c | 1310 | { |
03fd2215 | 1311 | clear_iv_info (); |
6fb5fa3c | 1312 | clean_slate = true; |
0d475361 | 1313 | df_finish_pass (true); |
c203e8a7 TS |
1314 | delete bivs; |
1315 | bivs = NULL; | |
6fb5fa3c DB |
1316 | free (iv_ref_table); |
1317 | iv_ref_table = NULL; | |
1318 | iv_ref_table_size = 0; | |
50654f6c ZD |
1319 | } |
1320 | } | |
1321 | ||
1322 | /* Computes inverse to X modulo (1 << MOD). */ | |
1323 | ||
a9243bfc RB |
1324 | static uint64_t |
1325 | inverse (uint64_t x, int mod) | |
50654f6c | 1326 | { |
a9243bfc RB |
1327 | uint64_t mask = |
1328 | ((uint64_t) 1 << (mod - 1) << 1) - 1; | |
1329 | uint64_t rslt = 1; | |
50654f6c ZD |
1330 | int i; |
1331 | ||
1332 | for (i = 0; i < mod - 1; i++) | |
1333 | { | |
1334 | rslt = (rslt * x) & mask; | |
1335 | x = (x * x) & mask; | |
1336 | } | |
1337 | ||
1338 | return rslt; | |
1339 | } | |
1340 | ||
b42b06e6 | 1341 | /* Checks whether any register in X is in set ALT. */ |
50654f6c | 1342 | |
b42b06e6 RS |
1343 | static bool |
1344 | altered_reg_used (const_rtx x, bitmap alt) | |
50654f6c | 1345 | { |
b42b06e6 RS |
1346 | subrtx_iterator::array_type array; |
1347 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
1348 | { | |
1349 | const_rtx x = *iter; | |
1350 | if (REG_P (x) && REGNO_REG_SET_P (alt, REGNO (x))) | |
1351 | return true; | |
1352 | } | |
1353 | return false; | |
50654f6c ZD |
1354 | } |
1355 | ||
1356 | /* Marks registers altered by EXPR in set ALT. */ | |
1357 | ||
1358 | static void | |
7bc980e1 | 1359 | mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt) |
50654f6c ZD |
1360 | { |
1361 | if (GET_CODE (expr) == SUBREG) | |
1362 | expr = SUBREG_REG (expr); | |
1363 | if (!REG_P (expr)) | |
1364 | return; | |
1365 | ||
d3bfe4de | 1366 | SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr)); |
50654f6c ZD |
1367 | } |
1368 | ||
1369 | /* Checks whether RHS is simple enough to process. */ | |
1370 | ||
1371 | static bool | |
1372 | simple_rhs_p (rtx rhs) | |
1373 | { | |
1374 | rtx op0, op1; | |
1375 | ||
cdf1bf8b | 1376 | if (function_invariant_p (rhs) |
4aa97413 | 1377 | || (REG_P (rhs) && !HARD_REGISTER_P (rhs))) |
50654f6c ZD |
1378 | return true; |
1379 | ||
1380 | switch (GET_CODE (rhs)) | |
1381 | { | |
1382 | case PLUS: | |
1383 | case MINUS: | |
b30321cd | 1384 | case AND: |
50654f6c ZD |
1385 | op0 = XEXP (rhs, 0); |
1386 | op1 = XEXP (rhs, 1); | |
b30321cd | 1387 | /* Allow reg OP const and reg OP reg. */ |
dc5b3407 | 1388 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0)) |
ce72fe6c | 1389 | && !function_invariant_p (op0)) |
dc5b3407 ZD |
1390 | return false; |
1391 | if (!(REG_P (op1) && !HARD_REGISTER_P (op1)) | |
ce72fe6c | 1392 | && !function_invariant_p (op1)) |
dc5b3407 | 1393 | return false; |
50654f6c | 1394 | |
dc5b3407 ZD |
1395 | return true; |
1396 | ||
1397 | case ASHIFT: | |
b30321cd BS |
1398 | case ASHIFTRT: |
1399 | case LSHIFTRT: | |
1400 | case MULT: | |
dc5b3407 ZD |
1401 | op0 = XEXP (rhs, 0); |
1402 | op1 = XEXP (rhs, 1); | |
b30321cd | 1403 | /* Allow reg OP const. */ |
dc5b3407 ZD |
1404 | if (!(REG_P (op0) && !HARD_REGISTER_P (op0))) |
1405 | return false; | |
ce72fe6c | 1406 | if (!function_invariant_p (op1)) |
dc5b3407 ZD |
1407 | return false; |
1408 | ||
1409 | return true; | |
50654f6c ZD |
1410 | |
1411 | default: | |
1412 | return false; | |
1413 | } | |
1414 | } | |
1415 | ||
4ca29add RS |
1416 | /* If REGNO has a single definition, return its known value, otherwise return |
1417 | null. */ | |
60081874 | 1418 | |
4ca29add RS |
1419 | static rtx |
1420 | find_single_def_src (unsigned int regno) | |
60081874 | 1421 | { |
60081874 | 1422 | df_ref adef; |
f63426af | 1423 | rtx set, src; |
60081874 | 1424 | |
f63426af BS |
1425 | for (;;) |
1426 | { | |
1427 | rtx note; | |
1428 | adef = DF_REG_DEF_CHAIN (regno); | |
1429 | if (adef == NULL || DF_REF_NEXT_REG (adef) != NULL | |
4ca29add RS |
1430 | || DF_REF_IS_ARTIFICIAL (adef)) |
1431 | return NULL_RTX; | |
f63426af BS |
1432 | |
1433 | set = single_set (DF_REF_INSN (adef)); | |
1434 | if (set == NULL || !REG_P (SET_DEST (set)) | |
1435 | || REGNO (SET_DEST (set)) != regno) | |
4ca29add | 1436 | return NULL_RTX; |
60081874 | 1437 | |
f63426af BS |
1438 | note = find_reg_equal_equiv_note (DF_REF_INSN (adef)); |
1439 | ||
1440 | if (note && function_invariant_p (XEXP (note, 0))) | |
1441 | { | |
1442 | src = XEXP (note, 0); | |
1443 | break; | |
1444 | } | |
1445 | src = SET_SRC (set); | |
1446 | ||
1447 | if (REG_P (src)) | |
1448 | { | |
1449 | regno = REGNO (src); | |
1450 | continue; | |
1451 | } | |
1452 | break; | |
1453 | } | |
1454 | if (!function_invariant_p (src)) | |
4ca29add RS |
1455 | return NULL_RTX; |
1456 | ||
1457 | return src; | |
1458 | } | |
1459 | ||
1460 | /* If any registers in *EXPR that have a single definition, try to replace | |
1461 | them with the known-equivalent values. */ | |
60081874 | 1462 | |
4ca29add RS |
1463 | static void |
1464 | replace_single_def_regs (rtx *expr) | |
1465 | { | |
1466 | subrtx_var_iterator::array_type array; | |
1467 | repeat: | |
1468 | FOR_EACH_SUBRTX_VAR (iter, array, *expr, NONCONST) | |
1469 | { | |
1470 | rtx x = *iter; | |
1471 | if (REG_P (x)) | |
1472 | if (rtx new_x = find_single_def_src (REGNO (x))) | |
1473 | { | |
1474 | *expr = simplify_replace_rtx (*expr, x, new_x); | |
1475 | goto repeat; | |
1476 | } | |
1477 | } | |
60081874 BS |
1478 | } |
1479 | ||
ed853664 BS |
1480 | /* A subroutine of simplify_using_initial_values, this function examines INSN |
1481 | to see if it contains a suitable set that we can use to make a replacement. | |
1482 | If it is suitable, return true and set DEST and SRC to the lhs and rhs of | |
1483 | the set; return false otherwise. */ | |
50654f6c | 1484 | |
ed853664 | 1485 | static bool |
1b20d55a | 1486 | suitable_set_for_replacement (rtx_insn *insn, rtx *dest, rtx *src) |
50654f6c ZD |
1487 | { |
1488 | rtx set = single_set (insn); | |
cddbddb7 | 1489 | rtx lhs = NULL_RTX, rhs; |
50654f6c | 1490 | |
ed853664 BS |
1491 | if (!set) |
1492 | return false; | |
50654f6c | 1493 | |
ed853664 BS |
1494 | lhs = SET_DEST (set); |
1495 | if (!REG_P (lhs)) | |
1496 | return false; | |
50654f6c ZD |
1497 | |
1498 | rhs = find_reg_equal_equiv_note (insn); | |
0aea6467 ZD |
1499 | if (rhs) |
1500 | rhs = XEXP (rhs, 0); | |
1501 | else | |
50654f6c ZD |
1502 | rhs = SET_SRC (set); |
1503 | ||
1504 | if (!simple_rhs_p (rhs)) | |
ed853664 | 1505 | return false; |
50654f6c | 1506 | |
ed853664 BS |
1507 | *dest = lhs; |
1508 | *src = rhs; | |
1509 | return true; | |
50654f6c ZD |
1510 | } |
1511 | ||
60081874 BS |
1512 | /* Using the data returned by suitable_set_for_replacement, replace DEST |
1513 | with SRC in *EXPR and return the new expression. Also call | |
1514 | replace_single_def_regs if the replacement changed something. */ | |
1515 | static void | |
1516 | replace_in_expr (rtx *expr, rtx dest, rtx src) | |
1517 | { | |
1518 | rtx old = *expr; | |
1519 | *expr = simplify_replace_rtx (*expr, dest, src); | |
1520 | if (old == *expr) | |
1521 | return; | |
4ca29add | 1522 | replace_single_def_regs (expr); |
60081874 BS |
1523 | } |
1524 | ||
50654f6c ZD |
1525 | /* Checks whether A implies B. */ |
1526 | ||
1527 | static bool | |
1528 | implies_p (rtx a, rtx b) | |
1529 | { | |
0aea6467 | 1530 | rtx op0, op1, opb0, opb1, r; |
ef4bddc2 | 1531 | machine_mode mode; |
50654f6c | 1532 | |
cca1130d BS |
1533 | if (rtx_equal_p (a, b)) |
1534 | return true; | |
1535 | ||
50654f6c ZD |
1536 | if (GET_CODE (a) == EQ) |
1537 | { | |
1538 | op0 = XEXP (a, 0); | |
1539 | op1 = XEXP (a, 1); | |
1540 | ||
cca1130d BS |
1541 | if (REG_P (op0) |
1542 | || (GET_CODE (op0) == SUBREG | |
1543 | && REG_P (SUBREG_REG (op0)))) | |
50654f6c ZD |
1544 | { |
1545 | r = simplify_replace_rtx (b, op0, op1); | |
1546 | if (r == const_true_rtx) | |
1547 | return true; | |
1548 | } | |
1549 | ||
cca1130d BS |
1550 | if (REG_P (op1) |
1551 | || (GET_CODE (op1) == SUBREG | |
1552 | && REG_P (SUBREG_REG (op1)))) | |
50654f6c ZD |
1553 | { |
1554 | r = simplify_replace_rtx (b, op1, op0); | |
1555 | if (r == const_true_rtx) | |
1556 | return true; | |
1557 | } | |
1558 | } | |
1559 | ||
60683019 BS |
1560 | if (b == const_true_rtx) |
1561 | return true; | |
1562 | ||
1563 | if ((GET_RTX_CLASS (GET_CODE (a)) != RTX_COMM_COMPARE | |
1564 | && GET_RTX_CLASS (GET_CODE (a)) != RTX_COMPARE) | |
1565 | || (GET_RTX_CLASS (GET_CODE (b)) != RTX_COMM_COMPARE | |
1566 | && GET_RTX_CLASS (GET_CODE (b)) != RTX_COMPARE)) | |
1567 | return false; | |
1568 | ||
1569 | op0 = XEXP (a, 0); | |
1570 | op1 = XEXP (a, 1); | |
1571 | opb0 = XEXP (b, 0); | |
1572 | opb1 = XEXP (b, 1); | |
1573 | ||
1574 | mode = GET_MODE (op0); | |
1575 | if (mode != GET_MODE (opb0)) | |
1576 | mode = VOIDmode; | |
1577 | else if (mode == VOIDmode) | |
1578 | { | |
1579 | mode = GET_MODE (op1); | |
1580 | if (mode != GET_MODE (opb1)) | |
1581 | mode = VOIDmode; | |
1582 | } | |
1583 | ||
0aea6467 ZD |
1584 | /* A < B implies A + 1 <= B. */ |
1585 | if ((GET_CODE (a) == GT || GET_CODE (a) == LT) | |
1586 | && (GET_CODE (b) == GE || GET_CODE (b) == LE)) | |
1587 | { | |
0aea6467 ZD |
1588 | |
1589 | if (GET_CODE (a) == GT) | |
1590 | { | |
1591 | r = op0; | |
1592 | op0 = op1; | |
1593 | op1 = r; | |
1594 | } | |
1595 | ||
1596 | if (GET_CODE (b) == GE) | |
1597 | { | |
1598 | r = opb0; | |
1599 | opb0 = opb1; | |
1600 | opb1 = r; | |
1601 | } | |
1602 | ||
d4538829 | 1603 | if (SCALAR_INT_MODE_P (mode) |
0aea6467 ZD |
1604 | && rtx_equal_p (op1, opb1) |
1605 | && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx) | |
1606 | return true; | |
60683019 BS |
1607 | return false; |
1608 | } | |
1609 | ||
1610 | /* A < B or A > B imply A != B. TODO: Likewise | |
1611 | A + n < B implies A != B + n if neither wraps. */ | |
1612 | if (GET_CODE (b) == NE | |
1613 | && (GET_CODE (a) == GT || GET_CODE (a) == GTU | |
1614 | || GET_CODE (a) == LT || GET_CODE (a) == LTU)) | |
1615 | { | |
1616 | if (rtx_equal_p (op0, opb0) | |
1617 | && rtx_equal_p (op1, opb1)) | |
1618 | return true; | |
0aea6467 ZD |
1619 | } |
1620 | ||
60683019 BS |
1621 | /* For unsigned comparisons, A != 0 implies A > 0 and A >= 1. */ |
1622 | if (GET_CODE (a) == NE | |
1623 | && op1 == const0_rtx) | |
1624 | { | |
1625 | if ((GET_CODE (b) == GTU | |
1626 | && opb1 == const0_rtx) | |
1627 | || (GET_CODE (b) == GEU | |
1628 | && opb1 == const1_rtx)) | |
1629 | return rtx_equal_p (op0, opb0); | |
1630 | } | |
1631 | ||
1632 | /* A != N is equivalent to A - (N + 1) <u -1. */ | |
1633 | if (GET_CODE (a) == NE | |
481683e1 | 1634 | && CONST_INT_P (op1) |
60683019 BS |
1635 | && GET_CODE (b) == LTU |
1636 | && opb1 == constm1_rtx | |
1637 | && GET_CODE (opb0) == PLUS | |
481683e1 | 1638 | && CONST_INT_P (XEXP (opb0, 1)) |
60683019 BS |
1639 | /* Avoid overflows. */ |
1640 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1641 | != ((unsigned HOST_WIDE_INT)1 | |
1642 | << (HOST_BITS_PER_WIDE_INT - 1)) - 1) | |
1643 | && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1)) | |
1644 | return rtx_equal_p (op0, XEXP (opb0, 0)); | |
1645 | ||
1646 | /* Likewise, A != N implies A - N > 0. */ | |
1647 | if (GET_CODE (a) == NE | |
481683e1 | 1648 | && CONST_INT_P (op1)) |
60683019 BS |
1649 | { |
1650 | if (GET_CODE (b) == GTU | |
1651 | && GET_CODE (opb0) == PLUS | |
1652 | && opb1 == const0_rtx | |
481683e1 | 1653 | && CONST_INT_P (XEXP (opb0, 1)) |
60683019 BS |
1654 | /* Avoid overflows. */ |
1655 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1656 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1657 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1658 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1659 | if (GET_CODE (b) == GEU | |
1660 | && GET_CODE (opb0) == PLUS | |
1661 | && opb1 == const1_rtx | |
481683e1 | 1662 | && CONST_INT_P (XEXP (opb0, 1)) |
60683019 BS |
1663 | /* Avoid overflows. */ |
1664 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) | |
1665 | != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
1666 | && rtx_equal_p (XEXP (opb0, 0), op0)) | |
1667 | return INTVAL (op1) == -INTVAL (XEXP (opb0, 1)); | |
1668 | } | |
1669 | ||
1670 | /* A >s X, where X is positive, implies A <u Y, if Y is negative. */ | |
1671 | if ((GET_CODE (a) == GT || GET_CODE (a) == GE) | |
481683e1 | 1672 | && CONST_INT_P (op1) |
60683019 BS |
1673 | && ((GET_CODE (a) == GT && op1 == constm1_rtx) |
1674 | || INTVAL (op1) >= 0) | |
1675 | && GET_CODE (b) == LTU | |
481683e1 | 1676 | && CONST_INT_P (opb1) |
b1c92d54 | 1677 | && rtx_equal_p (op0, opb0)) |
60683019 BS |
1678 | return INTVAL (opb1) < 0; |
1679 | ||
50654f6c ZD |
1680 | return false; |
1681 | } | |
1682 | ||
1683 | /* Canonicalizes COND so that | |
1684 | ||
1685 | (1) Ensure that operands are ordered according to | |
1686 | swap_commutative_operands_p. | |
1687 | (2) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
1688 | for GE, GEU, and LEU. */ | |
1689 | ||
1690 | rtx | |
1691 | canon_condition (rtx cond) | |
1692 | { | |
1693 | rtx tem; | |
1694 | rtx op0, op1; | |
1695 | enum rtx_code code; | |
ef4bddc2 | 1696 | machine_mode mode; |
50654f6c ZD |
1697 | |
1698 | code = GET_CODE (cond); | |
1699 | op0 = XEXP (cond, 0); | |
1700 | op1 = XEXP (cond, 1); | |
1701 | ||
1702 | if (swap_commutative_operands_p (op0, op1)) | |
1703 | { | |
1704 | code = swap_condition (code); | |
1705 | tem = op0; | |
1706 | op0 = op1; | |
1707 | op1 = tem; | |
1708 | } | |
1709 | ||
1710 | mode = GET_MODE (op0); | |
1711 | if (mode == VOIDmode) | |
1712 | mode = GET_MODE (op1); | |
b5e624c6 | 1713 | gcc_assert (mode != VOIDmode); |
50654f6c | 1714 | |
481683e1 | 1715 | if (CONST_INT_P (op1) |
50654f6c ZD |
1716 | && GET_MODE_CLASS (mode) != MODE_CC |
1717 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1718 | { | |
1719 | HOST_WIDE_INT const_val = INTVAL (op1); | |
1720 | unsigned HOST_WIDE_INT uconst_val = const_val; | |
1721 | unsigned HOST_WIDE_INT max_val | |
1722 | = (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode); | |
1723 | ||
1724 | switch (code) | |
1725 | { | |
1726 | case LE: | |
1727 | if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) | |
1728 | code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); | |
1729 | break; | |
1730 | ||
1731 | /* When cross-compiling, const_val might be sign-extended from | |
1732 | BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ | |
1733 | case GE: | |
1734 | if ((HOST_WIDE_INT) (const_val & max_val) | |
1735 | != (((HOST_WIDE_INT) 1 | |
1736 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
1737 | code = GT, op1 = gen_int_mode (const_val - 1, mode); | |
1738 | break; | |
1739 | ||
1740 | case LEU: | |
1741 | if (uconst_val < max_val) | |
1742 | code = LTU, op1 = gen_int_mode (uconst_val + 1, mode); | |
1743 | break; | |
1744 | ||
1745 | case GEU: | |
1746 | if (uconst_val != 0) | |
1747 | code = GTU, op1 = gen_int_mode (uconst_val - 1, mode); | |
1748 | break; | |
1749 | ||
1750 | default: | |
1751 | break; | |
1752 | } | |
1753 | } | |
1754 | ||
1755 | if (op0 != XEXP (cond, 0) | |
1756 | || op1 != XEXP (cond, 1) | |
1757 | || code != GET_CODE (cond) | |
1758 | || GET_MODE (cond) != SImode) | |
1759 | cond = gen_rtx_fmt_ee (code, SImode, op0, op1); | |
1760 | ||
1761 | return cond; | |
1762 | } | |
1763 | ||
da4cfeac RB |
1764 | /* Reverses CONDition; returns NULL if we cannot. */ |
1765 | ||
1766 | static rtx | |
1767 | reversed_condition (rtx cond) | |
1768 | { | |
1769 | enum rtx_code reversed; | |
1770 | reversed = reversed_comparison_code (cond, NULL); | |
1771 | if (reversed == UNKNOWN) | |
1772 | return NULL_RTX; | |
1773 | else | |
1774 | return gen_rtx_fmt_ee (reversed, | |
1775 | GET_MODE (cond), XEXP (cond, 0), | |
1776 | XEXP (cond, 1)); | |
1777 | } | |
1778 | ||
50654f6c ZD |
1779 | /* Tries to use the fact that COND holds to simplify EXPR. ALTERED is the |
1780 | set of altered regs. */ | |
1781 | ||
1782 | void | |
1783 | simplify_using_condition (rtx cond, rtx *expr, regset altered) | |
1784 | { | |
1785 | rtx rev, reve, exp = *expr; | |
1786 | ||
50654f6c ZD |
1787 | /* If some register gets altered later, we do not really speak about its |
1788 | value at the time of comparison. */ | |
b42b06e6 | 1789 | if (altered && altered_reg_used (cond, altered)) |
50654f6c ZD |
1790 | return; |
1791 | ||
1569e190 BS |
1792 | if (GET_CODE (cond) == EQ |
1793 | && REG_P (XEXP (cond, 0)) && CONSTANT_P (XEXP (cond, 1))) | |
1794 | { | |
1795 | *expr = simplify_replace_rtx (*expr, XEXP (cond, 0), XEXP (cond, 1)); | |
1796 | return; | |
1797 | } | |
1798 | ||
1799 | if (!COMPARISON_P (exp)) | |
1800 | return; | |
1801 | ||
50654f6c ZD |
1802 | rev = reversed_condition (cond); |
1803 | reve = reversed_condition (exp); | |
1804 | ||
1805 | cond = canon_condition (cond); | |
1806 | exp = canon_condition (exp); | |
1807 | if (rev) | |
1808 | rev = canon_condition (rev); | |
1809 | if (reve) | |
1810 | reve = canon_condition (reve); | |
1811 | ||
1812 | if (rtx_equal_p (exp, cond)) | |
1813 | { | |
1814 | *expr = const_true_rtx; | |
1815 | return; | |
1816 | } | |
1817 | ||
50654f6c ZD |
1818 | if (rev && rtx_equal_p (exp, rev)) |
1819 | { | |
1820 | *expr = const0_rtx; | |
1821 | return; | |
1822 | } | |
1823 | ||
1824 | if (implies_p (cond, exp)) | |
1825 | { | |
1826 | *expr = const_true_rtx; | |
1827 | return; | |
1828 | } | |
b8698a0f | 1829 | |
50654f6c ZD |
1830 | if (reve && implies_p (cond, reve)) |
1831 | { | |
1832 | *expr = const0_rtx; | |
1833 | return; | |
1834 | } | |
1835 | ||
1836 | /* A proof by contradiction. If *EXPR implies (not cond), *EXPR must | |
1837 | be false. */ | |
1838 | if (rev && implies_p (exp, rev)) | |
1839 | { | |
1840 | *expr = const0_rtx; | |
1841 | return; | |
1842 | } | |
1843 | ||
1844 | /* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true. */ | |
1845 | if (rev && reve && implies_p (reve, rev)) | |
1846 | { | |
1847 | *expr = const_true_rtx; | |
1848 | return; | |
1849 | } | |
1850 | ||
1851 | /* We would like to have some other tests here. TODO. */ | |
1852 | ||
1853 | return; | |
1854 | } | |
1855 | ||
1856 | /* Use relationship between A and *B to eventually eliminate *B. | |
1857 | OP is the operation we consider. */ | |
1858 | ||
1859 | static void | |
1860 | eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b) | |
1861 | { | |
b5e624c6 | 1862 | switch (op) |
50654f6c | 1863 | { |
b5e624c6 | 1864 | case AND: |
50654f6c ZD |
1865 | /* If A implies *B, we may replace *B by true. */ |
1866 | if (implies_p (a, *b)) | |
1867 | *b = const_true_rtx; | |
b5e624c6 NS |
1868 | break; |
1869 | ||
1870 | case IOR: | |
50654f6c ZD |
1871 | /* If *B implies A, we may replace *B by false. */ |
1872 | if (implies_p (*b, a)) | |
1873 | *b = const0_rtx; | |
b5e624c6 NS |
1874 | break; |
1875 | ||
1876 | default: | |
1877 | gcc_unreachable (); | |
50654f6c | 1878 | } |
50654f6c ZD |
1879 | } |
1880 | ||
1881 | /* Eliminates the conditions in TAIL that are implied by HEAD. OP is the | |
1882 | operation we consider. */ | |
1883 | ||
1884 | static void | |
1885 | eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail) | |
1886 | { | |
1887 | rtx elt; | |
1888 | ||
1889 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1890 | eliminate_implied_condition (op, *head, &XEXP (elt, 0)); | |
1891 | for (elt = tail; elt; elt = XEXP (elt, 1)) | |
1892 | eliminate_implied_condition (op, XEXP (elt, 0), head); | |
1893 | } | |
1894 | ||
1895 | /* Simplifies *EXPR using initial values at the start of the LOOP. If *EXPR | |
1896 | is a list, its elements are assumed to be combined using OP. */ | |
1897 | ||
1898 | static void | |
1899 | simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr) | |
1900 | { | |
ed853664 | 1901 | bool expression_valid; |
2f33ff0a DM |
1902 | rtx head, tail, last_valid_expr; |
1903 | rtx_expr_list *cond_list; | |
1b20d55a | 1904 | rtx_insn *insn; |
50654f6c | 1905 | rtx neutral, aggr; |
ed853664 | 1906 | regset altered, this_altered; |
50654f6c ZD |
1907 | edge e; |
1908 | ||
1909 | if (!*expr) | |
1910 | return; | |
1911 | ||
1912 | if (CONSTANT_P (*expr)) | |
1913 | return; | |
1914 | ||
1915 | if (GET_CODE (*expr) == EXPR_LIST) | |
1916 | { | |
1917 | head = XEXP (*expr, 0); | |
1918 | tail = XEXP (*expr, 1); | |
1919 | ||
1920 | eliminate_implied_conditions (op, &head, tail); | |
1921 | ||
b5e624c6 | 1922 | switch (op) |
50654f6c | 1923 | { |
b5e624c6 | 1924 | case AND: |
50654f6c ZD |
1925 | neutral = const_true_rtx; |
1926 | aggr = const0_rtx; | |
b5e624c6 NS |
1927 | break; |
1928 | ||
1929 | case IOR: | |
50654f6c ZD |
1930 | neutral = const0_rtx; |
1931 | aggr = const_true_rtx; | |
b5e624c6 | 1932 | break; |
50654f6c | 1933 | |
b5e624c6 NS |
1934 | default: |
1935 | gcc_unreachable (); | |
1936 | } | |
b8698a0f | 1937 | |
f822d252 | 1938 | simplify_using_initial_values (loop, UNKNOWN, &head); |
50654f6c ZD |
1939 | if (head == aggr) |
1940 | { | |
1941 | XEXP (*expr, 0) = aggr; | |
1942 | XEXP (*expr, 1) = NULL_RTX; | |
1943 | return; | |
1944 | } | |
1945 | else if (head == neutral) | |
1946 | { | |
1947 | *expr = tail; | |
1948 | simplify_using_initial_values (loop, op, expr); | |
1949 | return; | |
1950 | } | |
1951 | simplify_using_initial_values (loop, op, &tail); | |
1952 | ||
1953 | if (tail && XEXP (tail, 0) == aggr) | |
1954 | { | |
1955 | *expr = tail; | |
1956 | return; | |
1957 | } | |
b8698a0f | 1958 | |
50654f6c ZD |
1959 | XEXP (*expr, 0) = head; |
1960 | XEXP (*expr, 1) = tail; | |
1961 | return; | |
1962 | } | |
1963 | ||
b5e624c6 | 1964 | gcc_assert (op == UNKNOWN); |
50654f6c | 1965 | |
4ca29add | 1966 | replace_single_def_regs (expr); |
60081874 BS |
1967 | if (CONSTANT_P (*expr)) |
1968 | return; | |
1969 | ||
50654f6c | 1970 | e = loop_preheader_edge (loop); |
fefa31b5 | 1971 | if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
50654f6c ZD |
1972 | return; |
1973 | ||
04389919 | 1974 | altered = ALLOC_REG_SET (®_obstack); |
ed853664 | 1975 | this_altered = ALLOC_REG_SET (®_obstack); |
50654f6c | 1976 | |
ed853664 BS |
1977 | expression_valid = true; |
1978 | last_valid_expr = *expr; | |
2f33ff0a | 1979 | cond_list = NULL; |
50654f6c ZD |
1980 | while (1) |
1981 | { | |
1982 | insn = BB_END (e->src); | |
1983 | if (any_condjump_p (insn)) | |
1984 | { | |
45d09c02 | 1985 | rtx cond = get_condition (BB_END (e->src), NULL, false, true); |
1569e190 | 1986 | |
50654f6c ZD |
1987 | if (cond && (e->flags & EDGE_FALLTHRU)) |
1988 | cond = reversed_condition (cond); | |
1989 | if (cond) | |
1990 | { | |
1569e190 | 1991 | rtx old = *expr; |
50654f6c | 1992 | simplify_using_condition (cond, expr, altered); |
1569e190 BS |
1993 | if (old != *expr) |
1994 | { | |
1995 | rtx note; | |
1996 | if (CONSTANT_P (*expr)) | |
1997 | goto out; | |
1998 | for (note = cond_list; note; note = XEXP (note, 1)) | |
1999 | { | |
2000 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
2001 | if (CONSTANT_P (*expr)) | |
2002 | goto out; | |
2003 | } | |
2004 | } | |
2005 | cond_list = alloc_EXPR_LIST (0, cond, cond_list); | |
50654f6c ZD |
2006 | } |
2007 | } | |
2008 | ||
2009 | FOR_BB_INSNS_REVERSE (e->src, insn) | |
2010 | { | |
ed853664 | 2011 | rtx src, dest; |
1569e190 | 2012 | rtx old = *expr; |
ed853664 | 2013 | |
50654f6c ZD |
2014 | if (!INSN_P (insn)) |
2015 | continue; | |
ed853664 BS |
2016 | |
2017 | CLEAR_REG_SET (this_altered); | |
2018 | note_stores (PATTERN (insn), mark_altered, this_altered); | |
2019 | if (CALL_P (insn)) | |
50654f6c | 2020 | { |
ed853664 | 2021 | /* Kill all call clobbered registers. */ |
c7fb4c7a SB |
2022 | unsigned int i; |
2023 | hard_reg_set_iterator hrsi; | |
2024 | EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, | |
2025 | 0, i, hrsi) | |
2026 | SET_REGNO_REG_SET (this_altered, i); | |
50654f6c | 2027 | } |
ed853664 BS |
2028 | |
2029 | if (suitable_set_for_replacement (insn, &dest, &src)) | |
48982394 | 2030 | { |
2f33ff0a | 2031 | rtx_expr_list **pnote, **pnote_next; |
1569e190 | 2032 | |
60081874 | 2033 | replace_in_expr (expr, dest, src); |
ed853664 BS |
2034 | if (CONSTANT_P (*expr)) |
2035 | goto out; | |
1569e190 BS |
2036 | |
2037 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
2038 | { | |
2039 | rtx note = *pnote; | |
2040 | rtx old_cond = XEXP (note, 0); | |
2041 | ||
2f33ff0a | 2042 | pnote_next = (rtx_expr_list **)&XEXP (note, 1); |
60081874 BS |
2043 | replace_in_expr (&XEXP (note, 0), dest, src); |
2044 | ||
1569e190 BS |
2045 | /* We can no longer use a condition that has been simplified |
2046 | to a constant, and simplify_using_condition will abort if | |
2047 | we try. */ | |
2048 | if (CONSTANT_P (XEXP (note, 0))) | |
2049 | { | |
2050 | *pnote = *pnote_next; | |
2051 | pnote_next = pnote; | |
2052 | free_EXPR_LIST_node (note); | |
2053 | } | |
2054 | /* Retry simplifications with this condition if either the | |
2055 | expression or the condition changed. */ | |
2056 | else if (old_cond != XEXP (note, 0) || old != *expr) | |
2057 | simplify_using_condition (XEXP (note, 0), expr, altered); | |
2058 | } | |
48982394 | 2059 | } |
ed853664 | 2060 | else |
4fc2e37d | 2061 | { |
2f33ff0a | 2062 | rtx_expr_list **pnote, **pnote_next; |
4fc2e37d EB |
2063 | |
2064 | /* If we did not use this insn to make a replacement, any overlap | |
2065 | between stores in this insn and our expression will cause the | |
2066 | expression to become invalid. */ | |
b42b06e6 | 2067 | if (altered_reg_used (*expr, this_altered)) |
4fc2e37d EB |
2068 | goto out; |
2069 | ||
2070 | /* Likewise for the conditions. */ | |
2071 | for (pnote = &cond_list; *pnote; pnote = pnote_next) | |
2072 | { | |
2073 | rtx note = *pnote; | |
2074 | rtx old_cond = XEXP (note, 0); | |
2075 | ||
2f33ff0a | 2076 | pnote_next = (rtx_expr_list **)&XEXP (note, 1); |
b42b06e6 | 2077 | if (altered_reg_used (old_cond, this_altered)) |
4fc2e37d EB |
2078 | { |
2079 | *pnote = *pnote_next; | |
2080 | pnote_next = pnote; | |
2081 | free_EXPR_LIST_node (note); | |
2082 | } | |
2083 | } | |
2084 | } | |
ed853664 | 2085 | |
1569e190 BS |
2086 | if (CONSTANT_P (*expr)) |
2087 | goto out; | |
2088 | ||
ed853664 BS |
2089 | IOR_REG_SET (altered, this_altered); |
2090 | ||
2091 | /* If the expression now contains regs that have been altered, we | |
2092 | can't return it to the caller. However, it is still valid for | |
2093 | further simplification, so keep searching to see if we can | |
2094 | eventually turn it into a constant. */ | |
b42b06e6 | 2095 | if (altered_reg_used (*expr, altered)) |
ed853664 BS |
2096 | expression_valid = false; |
2097 | if (expression_valid) | |
2098 | last_valid_expr = *expr; | |
50654f6c ZD |
2099 | } |
2100 | ||
c5cbcccf | 2101 | if (!single_pred_p (e->src) |
fefa31b5 | 2102 | || single_pred (e->src) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
50654f6c | 2103 | break; |
c5cbcccf | 2104 | e = single_pred_edge (e->src); |
50654f6c ZD |
2105 | } |
2106 | ||
ed853664 | 2107 | out: |
1569e190 | 2108 | free_EXPR_LIST_list (&cond_list); |
ed853664 BS |
2109 | if (!CONSTANT_P (*expr)) |
2110 | *expr = last_valid_expr; | |
50654f6c | 2111 | FREE_REG_SET (altered); |
ed853664 | 2112 | FREE_REG_SET (this_altered); |
50654f6c ZD |
2113 | } |
2114 | ||
2115 | /* Transforms invariant IV into MODE. Adds assumptions based on the fact | |
2116 | that IV occurs as left operands of comparison COND and its signedness | |
2117 | is SIGNED_P to DESC. */ | |
2118 | ||
2119 | static void | |
ef4bddc2 | 2120 | shorten_into_mode (struct rtx_iv *iv, machine_mode mode, |
50654f6c ZD |
2121 | enum rtx_code cond, bool signed_p, struct niter_desc *desc) |
2122 | { | |
2123 | rtx mmin, mmax, cond_over, cond_under; | |
2124 | ||
0aea6467 | 2125 | get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax); |
50654f6c ZD |
2126 | cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode, |
2127 | iv->base, mmin); | |
2128 | cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode, | |
2129 | iv->base, mmax); | |
2130 | ||
2131 | switch (cond) | |
2132 | { | |
2133 | case LE: | |
2134 | case LT: | |
2135 | case LEU: | |
2136 | case LTU: | |
2137 | if (cond_under != const0_rtx) | |
2138 | desc->infinite = | |
2139 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2140 | if (cond_over != const0_rtx) | |
2141 | desc->noloop_assumptions = | |
2142 | alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions); | |
2143 | break; | |
2144 | ||
2145 | case GE: | |
2146 | case GT: | |
2147 | case GEU: | |
2148 | case GTU: | |
2149 | if (cond_over != const0_rtx) | |
2150 | desc->infinite = | |
2151 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2152 | if (cond_under != const0_rtx) | |
2153 | desc->noloop_assumptions = | |
2154 | alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions); | |
2155 | break; | |
2156 | ||
2157 | case NE: | |
2158 | if (cond_over != const0_rtx) | |
2159 | desc->infinite = | |
2160 | alloc_EXPR_LIST (0, cond_over, desc->infinite); | |
2161 | if (cond_under != const0_rtx) | |
2162 | desc->infinite = | |
2163 | alloc_EXPR_LIST (0, cond_under, desc->infinite); | |
2164 | break; | |
2165 | ||
2166 | default: | |
b5e624c6 | 2167 | gcc_unreachable (); |
50654f6c ZD |
2168 | } |
2169 | ||
2170 | iv->mode = mode; | |
1c1ad7bb | 2171 | iv->extend = signed_p ? IV_SIGN_EXTEND : IV_ZERO_EXTEND; |
50654f6c ZD |
2172 | } |
2173 | ||
2174 | /* Transforms IV0 and IV1 compared by COND so that they are both compared as | |
a1105617 | 2175 | subregs of the same mode if possible (sometimes it is necessary to add |
50654f6c ZD |
2176 | some assumptions to DESC). */ |
2177 | ||
2178 | static bool | |
2179 | canonicalize_iv_subregs (struct rtx_iv *iv0, struct rtx_iv *iv1, | |
2180 | enum rtx_code cond, struct niter_desc *desc) | |
2181 | { | |
ef4bddc2 | 2182 | machine_mode comp_mode; |
50654f6c ZD |
2183 | bool signed_p; |
2184 | ||
2185 | /* If the ivs behave specially in the first iteration, or are | |
2186 | added/multiplied after extending, we ignore them. */ | |
2187 | if (iv0->first_special || iv0->mult != const1_rtx || iv0->delta != const0_rtx) | |
2188 | return false; | |
2189 | if (iv1->first_special || iv1->mult != const1_rtx || iv1->delta != const0_rtx) | |
2190 | return false; | |
2191 | ||
2192 | /* If there is some extend, it must match signedness of the comparison. */ | |
2193 | switch (cond) | |
2194 | { | |
2195 | case LE: | |
2196 | case LT: | |
1c1ad7bb SB |
2197 | if (iv0->extend == IV_ZERO_EXTEND |
2198 | || iv1->extend == IV_ZERO_EXTEND) | |
50654f6c ZD |
2199 | return false; |
2200 | signed_p = true; | |
2201 | break; | |
2202 | ||
2203 | case LEU: | |
2204 | case LTU: | |
1c1ad7bb SB |
2205 | if (iv0->extend == IV_SIGN_EXTEND |
2206 | || iv1->extend == IV_SIGN_EXTEND) | |
50654f6c ZD |
2207 | return false; |
2208 | signed_p = false; | |
2209 | break; | |
2210 | ||
2211 | case NE: | |
1c1ad7bb SB |
2212 | if (iv0->extend != IV_UNKNOWN_EXTEND |
2213 | && iv1->extend != IV_UNKNOWN_EXTEND | |
50654f6c ZD |
2214 | && iv0->extend != iv1->extend) |
2215 | return false; | |
2216 | ||
2217 | signed_p = false; | |
1c1ad7bb SB |
2218 | if (iv0->extend != IV_UNKNOWN_EXTEND) |
2219 | signed_p = iv0->extend == IV_SIGN_EXTEND; | |
2220 | if (iv1->extend != IV_UNKNOWN_EXTEND) | |
2221 | signed_p = iv1->extend == IV_SIGN_EXTEND; | |
50654f6c ZD |
2222 | break; |
2223 | ||
2224 | default: | |
b5e624c6 | 2225 | gcc_unreachable (); |
50654f6c ZD |
2226 | } |
2227 | ||
2228 | /* Values of both variables should be computed in the same mode. These | |
2229 | might indeed be different, if we have comparison like | |
2230 | ||
2231 | (compare (subreg:SI (iv0)) (subreg:SI (iv1))) | |
2232 | ||
2233 | and iv0 and iv1 are both ivs iterating in SI mode, but calculated | |
2234 | in different modes. This does not seem impossible to handle, but | |
2235 | it hardly ever occurs in practice. | |
b8698a0f | 2236 | |
50654f6c ZD |
2237 | The only exception is the case when one of operands is invariant. |
2238 | For example pentium 3 generates comparisons like | |
2239 | (lt (subreg:HI (reg:SI)) 100). Here we assign HImode to 100, but we | |
2240 | definitely do not want this prevent the optimization. */ | |
2241 | comp_mode = iv0->extend_mode; | |
2242 | if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode)) | |
2243 | comp_mode = iv1->extend_mode; | |
2244 | ||
2245 | if (iv0->extend_mode != comp_mode) | |
2246 | { | |
2247 | if (iv0->mode != iv0->extend_mode | |
2248 | || iv0->step != const0_rtx) | |
2249 | return false; | |
2250 | ||
2251 | iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2252 | comp_mode, iv0->base, iv0->mode); | |
2253 | iv0->extend_mode = comp_mode; | |
2254 | } | |
2255 | ||
2256 | if (iv1->extend_mode != comp_mode) | |
2257 | { | |
2258 | if (iv1->mode != iv1->extend_mode | |
2259 | || iv1->step != const0_rtx) | |
2260 | return false; | |
2261 | ||
2262 | iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND, | |
2263 | comp_mode, iv1->base, iv1->mode); | |
2264 | iv1->extend_mode = comp_mode; | |
2265 | } | |
2266 | ||
2267 | /* Check that both ivs belong to a range of a single mode. If one of the | |
2268 | operands is an invariant, we may need to shorten it into the common | |
2269 | mode. */ | |
2270 | if (iv0->mode == iv0->extend_mode | |
2271 | && iv0->step == const0_rtx | |
2272 | && iv0->mode != iv1->mode) | |
2273 | shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc); | |
2274 | ||
2275 | if (iv1->mode == iv1->extend_mode | |
2276 | && iv1->step == const0_rtx | |
2277 | && iv0->mode != iv1->mode) | |
2278 | shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc); | |
2279 | ||
2280 | if (iv0->mode != iv1->mode) | |
2281 | return false; | |
2282 | ||
2283 | desc->mode = iv0->mode; | |
2284 | desc->signed_p = signed_p; | |
2285 | ||
2286 | return true; | |
2287 | } | |
2288 | ||
daa57386 RG |
2289 | /* Tries to estimate the maximum number of iterations in LOOP, and return the |
2290 | result. This function is called from iv_number_of_iterations with | |
28af33b0 BS |
2291 | a number of fields in DESC already filled in. OLD_NITER is the original |
2292 | expression for the number of iterations, before we tried to simplify it. */ | |
c67dc1a3 | 2293 | |
a9243bfc | 2294 | static uint64_t |
28af33b0 | 2295 | determine_max_iter (struct loop *loop, struct niter_desc *desc, rtx old_niter) |
c67dc1a3 BS |
2296 | { |
2297 | rtx niter = desc->niter_expr; | |
60683019 | 2298 | rtx mmin, mmax, cmp; |
a9243bfc RB |
2299 | uint64_t nmax, inc; |
2300 | uint64_t andmax = 0; | |
43ffba00 JH |
2301 | |
2302 | /* We used to look for constant operand 0 of AND, | |
2303 | but canonicalization should always make this impossible. */ | |
2304 | gcc_checking_assert (GET_CODE (niter) != AND | |
2305 | || !CONST_INT_P (XEXP (niter, 0))); | |
c67dc1a3 BS |
2306 | |
2307 | if (GET_CODE (niter) == AND | |
43ffba00 | 2308 | && CONST_INT_P (XEXP (niter, 1))) |
c67dc1a3 | 2309 | { |
43ffba00 JH |
2310 | andmax = UINTVAL (XEXP (niter, 1)); |
2311 | niter = XEXP (niter, 0); | |
c67dc1a3 BS |
2312 | } |
2313 | ||
2314 | get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax); | |
d7ca26e4 | 2315 | nmax = UINTVAL (mmax) - UINTVAL (mmin); |
c67dc1a3 BS |
2316 | |
2317 | if (GET_CODE (niter) == UDIV) | |
2318 | { | |
481683e1 | 2319 | if (!CONST_INT_P (XEXP (niter, 1))) |
daa57386 | 2320 | return nmax; |
c67dc1a3 BS |
2321 | inc = INTVAL (XEXP (niter, 1)); |
2322 | niter = XEXP (niter, 0); | |
2323 | } | |
2324 | else | |
2325 | inc = 1; | |
2326 | ||
60683019 BS |
2327 | /* We could use a binary search here, but for now improving the upper |
2328 | bound by just one eliminates one important corner case. */ | |
28af33b0 BS |
2329 | cmp = simplify_gen_relational (desc->signed_p ? LT : LTU, VOIDmode, |
2330 | desc->mode, old_niter, mmax); | |
60683019 BS |
2331 | simplify_using_initial_values (loop, UNKNOWN, &cmp); |
2332 | if (cmp == const_true_rtx) | |
c67dc1a3 | 2333 | { |
60683019 | 2334 | nmax--; |
c67dc1a3 | 2335 | |
60683019 BS |
2336 | if (dump_file) |
2337 | fprintf (dump_file, ";; improved upper bound by one.\n"); | |
c67dc1a3 | 2338 | } |
43ffba00 JH |
2339 | nmax /= inc; |
2340 | if (andmax) | |
2341 | nmax = MIN (nmax, andmax); | |
2342 | if (dump_file) | |
a9243bfc | 2343 | fprintf (dump_file, ";; Determined upper bound %"PRId64".\n", |
43ffba00 JH |
2344 | nmax); |
2345 | return nmax; | |
c67dc1a3 BS |
2346 | } |
2347 | ||
50654f6c ZD |
2348 | /* Computes number of iterations of the CONDITION in INSN in LOOP and stores |
2349 | the result into DESC. Very similar to determine_number_of_iterations | |
2350 | (basically its rtl version), complicated by things like subregs. */ | |
2351 | ||
e3715ebd | 2352 | static void |
1b20d55a | 2353 | iv_number_of_iterations (struct loop *loop, rtx_insn *insn, rtx condition, |
50654f6c ZD |
2354 | struct niter_desc *desc) |
2355 | { | |
03fd2215 | 2356 | rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1; |
50654f6c | 2357 | struct rtx_iv iv0, iv1, tmp_iv; |
0aea6467 | 2358 | rtx assumption, may_not_xform; |
50654f6c | 2359 | enum rtx_code cond; |
ef4bddc2 | 2360 | machine_mode mode, comp_mode; |
0aea6467 | 2361 | rtx mmin, mmax, mode_mmin, mode_mmax; |
a9243bfc RB |
2362 | uint64_t s, size, d, inv, max; |
2363 | int64_t up, down, inc, step_val; | |
50654f6c | 2364 | int was_sharp = false; |
fe3f617f | 2365 | rtx old_niter; |
6b9b7b4c | 2366 | bool step_is_pow2; |
50654f6c ZD |
2367 | |
2368 | /* The meaning of these assumptions is this: | |
2369 | if !assumptions | |
2370 | then the rest of information does not have to be valid | |
2371 | if noloop_assumptions then the loop does not roll | |
2372 | if infinite then this exit is never used */ | |
2373 | ||
2374 | desc->assumptions = NULL_RTX; | |
2375 | desc->noloop_assumptions = NULL_RTX; | |
2376 | desc->infinite = NULL_RTX; | |
2377 | desc->simple_p = true; | |
2378 | ||
2379 | desc->const_iter = false; | |
2380 | desc->niter_expr = NULL_RTX; | |
50654f6c ZD |
2381 | |
2382 | cond = GET_CODE (condition); | |
b5e624c6 | 2383 | gcc_assert (COMPARISON_P (condition)); |
50654f6c ZD |
2384 | |
2385 | mode = GET_MODE (XEXP (condition, 0)); | |
2386 | if (mode == VOIDmode) | |
2387 | mode = GET_MODE (XEXP (condition, 1)); | |
2388 | /* The constant comparisons should be folded. */ | |
b5e624c6 | 2389 | gcc_assert (mode != VOIDmode); |
50654f6c ZD |
2390 | |
2391 | /* We only handle integers or pointers. */ | |
2392 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2393 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) | |
2394 | goto fail; | |
2395 | ||
2396 | op0 = XEXP (condition, 0); | |
03fd2215 | 2397 | if (!iv_analyze (insn, op0, &iv0)) |
50654f6c ZD |
2398 | goto fail; |
2399 | if (iv0.extend_mode == VOIDmode) | |
2400 | iv0.mode = iv0.extend_mode = mode; | |
b8698a0f | 2401 | |
50654f6c | 2402 | op1 = XEXP (condition, 1); |
03fd2215 | 2403 | if (!iv_analyze (insn, op1, &iv1)) |
50654f6c ZD |
2404 | goto fail; |
2405 | if (iv1.extend_mode == VOIDmode) | |
2406 | iv1.mode = iv1.extend_mode = mode; | |
2407 | ||
2408 | if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT | |
2409 | || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT) | |
2410 | goto fail; | |
2411 | ||
2412 | /* Check condition and normalize it. */ | |
2413 | ||
2414 | switch (cond) | |
2415 | { | |
2416 | case GE: | |
2417 | case GT: | |
2418 | case GEU: | |
2419 | case GTU: | |
2420 | tmp_iv = iv0; iv0 = iv1; iv1 = tmp_iv; | |
2421 | cond = swap_condition (cond); | |
2422 | break; | |
2423 | case NE: | |
2424 | case LE: | |
2425 | case LEU: | |
2426 | case LT: | |
2427 | case LTU: | |
2428 | break; | |
2429 | default: | |
2430 | goto fail; | |
2431 | } | |
2432 | ||
2433 | /* Handle extends. This is relatively nontrivial, so we only try in some | |
2434 | easy cases, when we can canonicalize the ivs (possibly by adding some | |
2435 | assumptions) to shape subreg (base + i * step). This function also fills | |
2436 | in desc->mode and desc->signed_p. */ | |
2437 | ||
2438 | if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc)) | |
2439 | goto fail; | |
2440 | ||
2441 | comp_mode = iv0.extend_mode; | |
2442 | mode = iv0.mode; | |
50b6ee8b | 2443 | size = GET_MODE_PRECISION (mode); |
0aea6467 | 2444 | get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax); |
6c3b938d RS |
2445 | mode_mmin = lowpart_subreg (mode, mmin, comp_mode); |
2446 | mode_mmax = lowpart_subreg (mode, mmax, comp_mode); | |
50654f6c | 2447 | |
481683e1 | 2448 | if (!CONST_INT_P (iv0.step) || !CONST_INT_P (iv1.step)) |
50654f6c ZD |
2449 | goto fail; |
2450 | ||
2451 | /* We can take care of the case of two induction variables chasing each other | |
2452 | if the test is NE. I have never seen a loop using it, but still it is | |
2453 | cool. */ | |
2454 | if (iv0.step != const0_rtx && iv1.step != const0_rtx) | |
2455 | { | |
2456 | if (cond != NE) | |
2457 | goto fail; | |
2458 | ||
2459 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2460 | iv1.step = const0_rtx; | |
2461 | } | |
2462 | ||
3461a16e JJ |
2463 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
2464 | iv1.step = lowpart_subreg (mode, iv1.step, comp_mode); | |
2465 | ||
50654f6c ZD |
2466 | /* This is either infinite loop or the one that ends immediately, depending |
2467 | on initial values. Unswitching should remove this kind of conditions. */ | |
2468 | if (iv0.step == const0_rtx && iv1.step == const0_rtx) | |
2469 | goto fail; | |
2470 | ||
6b9b7b4c ZD |
2471 | if (cond != NE) |
2472 | { | |
2473 | if (iv0.step == const0_rtx) | |
2474 | step_val = -INTVAL (iv1.step); | |
2475 | else | |
6e17f9c1 | 2476 | step_val = INTVAL (iv0.step); |
6b9b7b4c ZD |
2477 | |
2478 | /* Ignore loops of while (i-- < 10) type. */ | |
2479 | if (step_val < 0) | |
2480 | goto fail; | |
2481 | ||
2482 | step_is_pow2 = !(step_val & (step_val - 1)); | |
2483 | } | |
2484 | else | |
2485 | { | |
2486 | /* We do not care about whether the step is power of two in this | |
2487 | case. */ | |
2488 | step_is_pow2 = false; | |
2489 | step_val = 0; | |
2490 | } | |
50654f6c ZD |
2491 | |
2492 | /* Some more condition normalization. We must record some assumptions | |
2493 | due to overflows. */ | |
2494 | switch (cond) | |
2495 | { | |
2496 | case LT: | |
2497 | case LTU: | |
2498 | /* We want to take care only of non-sharp relationals; this is easy, | |
2499 | as in cases the overflow would make the transformation unsafe | |
2500 | the loop does not roll. Seemingly it would make more sense to want | |
2501 | to take care of sharp relationals instead, as NE is more similar to | |
2502 | them, but the problem is that here the transformation would be more | |
2503 | difficult due to possibly infinite loops. */ | |
2504 | if (iv0.step == const0_rtx) | |
2505 | { | |
6c3b938d | 2506 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
0aea6467 ZD |
2507 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2508 | mode_mmax); | |
50654f6c | 2509 | if (assumption == const_true_rtx) |
4fbe4f91 | 2510 | goto zero_iter_simplify; |
50654f6c ZD |
2511 | iv0.base = simplify_gen_binary (PLUS, comp_mode, |
2512 | iv0.base, const1_rtx); | |
2513 | } | |
2514 | else | |
2515 | { | |
6c3b938d | 2516 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
0aea6467 ZD |
2517 | assumption = simplify_gen_relational (EQ, SImode, mode, tmp, |
2518 | mode_mmin); | |
50654f6c | 2519 | if (assumption == const_true_rtx) |
4fbe4f91 | 2520 | goto zero_iter_simplify; |
50654f6c ZD |
2521 | iv1.base = simplify_gen_binary (PLUS, comp_mode, |
2522 | iv1.base, constm1_rtx); | |
2523 | } | |
2524 | ||
2525 | if (assumption != const0_rtx) | |
2526 | desc->noloop_assumptions = | |
2527 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2528 | cond = (cond == LT) ? LE : LEU; | |
2529 | ||
2530 | /* It will be useful to be able to tell the difference once more in | |
2531 | LE -> NE reduction. */ | |
2532 | was_sharp = true; | |
2533 | break; | |
2534 | default: ; | |
2535 | } | |
2536 | ||
2537 | /* Take care of trivially infinite loops. */ | |
2538 | if (cond != NE) | |
2539 | { | |
2540 | if (iv0.step == const0_rtx) | |
2541 | { | |
6c3b938d | 2542 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); |
0aea6467 | 2543 | if (rtx_equal_p (tmp, mode_mmin)) |
50654f6c ZD |
2544 | { |
2545 | desc->infinite = | |
2546 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
4fbe4f91 ZD |
2547 | /* Fill in the remaining fields somehow. */ |
2548 | goto zero_iter_simplify; | |
50654f6c ZD |
2549 | } |
2550 | } | |
2551 | else | |
2552 | { | |
6c3b938d | 2553 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); |
0aea6467 | 2554 | if (rtx_equal_p (tmp, mode_mmax)) |
50654f6c ZD |
2555 | { |
2556 | desc->infinite = | |
2557 | alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX); | |
4fbe4f91 ZD |
2558 | /* Fill in the remaining fields somehow. */ |
2559 | goto zero_iter_simplify; | |
50654f6c ZD |
2560 | } |
2561 | } | |
2562 | } | |
2563 | ||
2564 | /* If we can we want to take care of NE conditions instead of size | |
2565 | comparisons, as they are much more friendly (most importantly | |
2566 | this takes care of special handling of loops with step 1). We can | |
2567 | do it if we first check that upper bound is greater or equal to | |
2568 | lower bound, their difference is constant c modulo step and that | |
2569 | there is not an overflow. */ | |
2570 | if (cond != NE) | |
2571 | { | |
2572 | if (iv0.step == const0_rtx) | |
2573 | step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode); | |
2574 | else | |
2575 | step = iv0.step; | |
3461a16e | 2576 | step = lowpart_subreg (mode, step, comp_mode); |
50654f6c | 2577 | delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); |
6c3b938d | 2578 | delta = lowpart_subreg (mode, delta, comp_mode); |
50654f6c ZD |
2579 | delta = simplify_gen_binary (UMOD, mode, delta, step); |
2580 | may_xform = const0_rtx; | |
0aea6467 | 2581 | may_not_xform = const_true_rtx; |
50654f6c | 2582 | |
481683e1 | 2583 | if (CONST_INT_P (delta)) |
50654f6c ZD |
2584 | { |
2585 | if (was_sharp && INTVAL (delta) == INTVAL (step) - 1) | |
2586 | { | |
2587 | /* A special case. We have transformed condition of type | |
2588 | for (i = 0; i < 4; i += 4) | |
2589 | into | |
2590 | for (i = 0; i <= 3; i += 4) | |
2591 | obviously if the test for overflow during that transformation | |
2592 | passed, we cannot overflow here. Most importantly any | |
2593 | loop with sharp end condition and step 1 falls into this | |
a1105617 | 2594 | category, so handling this case specially is definitely |
50654f6c ZD |
2595 | worth the troubles. */ |
2596 | may_xform = const_true_rtx; | |
2597 | } | |
2598 | else if (iv0.step == const0_rtx) | |
2599 | { | |
2600 | bound = simplify_gen_binary (PLUS, comp_mode, mmin, step); | |
2601 | bound = simplify_gen_binary (MINUS, comp_mode, bound, delta); | |
6c3b938d RS |
2602 | bound = lowpart_subreg (mode, bound, comp_mode); |
2603 | tmp = lowpart_subreg (mode, iv0.base, comp_mode); | |
50654f6c ZD |
2604 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2605 | bound, tmp); | |
0aea6467 ZD |
2606 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2607 | SImode, mode, | |
2608 | bound, tmp); | |
50654f6c ZD |
2609 | } |
2610 | else | |
2611 | { | |
2612 | bound = simplify_gen_binary (MINUS, comp_mode, mmax, step); | |
2613 | bound = simplify_gen_binary (PLUS, comp_mode, bound, delta); | |
6c3b938d RS |
2614 | bound = lowpart_subreg (mode, bound, comp_mode); |
2615 | tmp = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c ZD |
2616 | may_xform = simplify_gen_relational (cond, SImode, mode, |
2617 | tmp, bound); | |
0aea6467 ZD |
2618 | may_not_xform = simplify_gen_relational (reverse_condition (cond), |
2619 | SImode, mode, | |
2620 | tmp, bound); | |
50654f6c ZD |
2621 | } |
2622 | } | |
2623 | ||
2624 | if (may_xform != const0_rtx) | |
2625 | { | |
2626 | /* We perform the transformation always provided that it is not | |
2627 | completely senseless. This is OK, as we would need this assumption | |
2628 | to determine the number of iterations anyway. */ | |
2629 | if (may_xform != const_true_rtx) | |
0aea6467 ZD |
2630 | { |
2631 | /* If the step is a power of two and the final value we have | |
2632 | computed overflows, the cycle is infinite. Otherwise it | |
2633 | is nontrivial to compute the number of iterations. */ | |
6b9b7b4c | 2634 | if (step_is_pow2) |
0aea6467 ZD |
2635 | desc->infinite = alloc_EXPR_LIST (0, may_not_xform, |
2636 | desc->infinite); | |
2637 | else | |
2638 | desc->assumptions = alloc_EXPR_LIST (0, may_xform, | |
2639 | desc->assumptions); | |
2640 | } | |
50654f6c ZD |
2641 | |
2642 | /* We are going to lose some information about upper bound on | |
2643 | number of iterations in this step, so record the information | |
2644 | here. */ | |
2645 | inc = INTVAL (iv0.step) - INTVAL (iv1.step); | |
481683e1 | 2646 | if (CONST_INT_P (iv1.base)) |
50654f6c ZD |
2647 | up = INTVAL (iv1.base); |
2648 | else | |
0aea6467 | 2649 | up = INTVAL (mode_mmax) - inc; |
481683e1 | 2650 | down = INTVAL (CONST_INT_P (iv0.base) |
0aea6467 ZD |
2651 | ? iv0.base |
2652 | : mode_mmin); | |
d7ca26e4 | 2653 | max = (uint64_t) (up - down) / inc + 1; |
bcd8d322 JH |
2654 | if (!desc->infinite |
2655 | && !desc->assumptions) | |
807e902e | 2656 | record_niter_bound (loop, max, false, true); |
50654f6c ZD |
2657 | |
2658 | if (iv0.step == const0_rtx) | |
2659 | { | |
2660 | iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta); | |
2661 | iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step); | |
2662 | } | |
2663 | else | |
2664 | { | |
2665 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta); | |
2666 | iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step); | |
2667 | } | |
2668 | ||
6c3b938d RS |
2669 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2670 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c ZD |
2671 | assumption = simplify_gen_relational (reverse_condition (cond), |
2672 | SImode, mode, tmp0, tmp1); | |
2673 | if (assumption == const_true_rtx) | |
4fbe4f91 | 2674 | goto zero_iter_simplify; |
50654f6c ZD |
2675 | else if (assumption != const0_rtx) |
2676 | desc->noloop_assumptions = | |
2677 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2678 | cond = NE; | |
2679 | } | |
2680 | } | |
2681 | ||
2682 | /* Count the number of iterations. */ | |
2683 | if (cond == NE) | |
2684 | { | |
2685 | /* Everything we do here is just arithmetics modulo size of mode. This | |
2686 | makes us able to do more involved computations of number of iterations | |
2687 | than in other cases. First transform the condition into shape | |
2688 | s * i <> c, with s positive. */ | |
2689 | iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base); | |
2690 | iv0.base = const0_rtx; | |
2691 | iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step); | |
2692 | iv1.step = const0_rtx; | |
2693 | if (INTVAL (iv0.step) < 0) | |
2694 | { | |
807e902e KZ |
2695 | iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, comp_mode); |
2696 | iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, comp_mode); | |
50654f6c | 2697 | } |
6c3b938d | 2698 | iv0.step = lowpart_subreg (mode, iv0.step, comp_mode); |
50654f6c ZD |
2699 | |
2700 | /* Let nsd (s, size of mode) = d. If d does not divide c, the loop | |
2701 | is infinite. Otherwise, the number of iterations is | |
2702 | (inverse(s/d) * (c/d)) mod (size of mode/d). */ | |
2703 | s = INTVAL (iv0.step); d = 1; | |
2704 | while (s % 2 != 1) | |
2705 | { | |
2706 | s /= 2; | |
2707 | d *= 2; | |
2708 | size--; | |
2709 | } | |
a9243bfc | 2710 | bound = GEN_INT (((uint64_t) 1 << (size - 1 ) << 1) - 1); |
50654f6c | 2711 | |
6c3b938d | 2712 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); |
69a59f0f | 2713 | tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode)); |
50654f6c ZD |
2714 | assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx); |
2715 | desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2716 | ||
69a59f0f | 2717 | tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode)); |
0aea6467 | 2718 | inv = inverse (s, size); |
bb80db7b | 2719 | tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode)); |
50654f6c ZD |
2720 | desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound); |
2721 | } | |
2722 | else | |
2723 | { | |
2724 | if (iv1.step == const0_rtx) | |
2725 | /* Condition in shape a + s * i <= b | |
2726 | We must know that b + s does not overflow and a <= b + s and then we | |
2727 | can compute number of iterations as (b + s - a) / s. (It might | |
2728 | seem that we in fact could be more clever about testing the b + s | |
2729 | overflow condition using some information about b - a mod s, | |
2730 | but it was already taken into account during LE -> NE transform). */ | |
2731 | { | |
2732 | step = iv0.step; | |
6c3b938d RS |
2733 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2734 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c | 2735 | |
0aea6467 | 2736 | bound = simplify_gen_binary (MINUS, mode, mode_mmax, |
6c3b938d RS |
2737 | lowpart_subreg (mode, step, |
2738 | comp_mode)); | |
6b9b7b4c ZD |
2739 | if (step_is_pow2) |
2740 | { | |
2741 | rtx t0, t1; | |
2742 | ||
2743 | /* If s is power of 2, we know that the loop is infinite if | |
2744 | a % s <= b % s and b + s overflows. */ | |
2745 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2746 | SImode, mode, | |
2747 | tmp1, bound); | |
2748 | ||
2749 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2750 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2751 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2752 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2753 | desc->infinite = | |
2754 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2755 | } | |
2756 | else | |
2757 | { | |
2758 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2759 | tmp1, bound); | |
2760 | desc->assumptions = | |
2761 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2762 | } | |
50654f6c ZD |
2763 | |
2764 | tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step); | |
6c3b938d | 2765 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
50654f6c ZD |
2766 | assumption = simplify_gen_relational (reverse_condition (cond), |
2767 | SImode, mode, tmp0, tmp); | |
2768 | ||
2769 | delta = simplify_gen_binary (PLUS, mode, tmp1, step); | |
2770 | delta = simplify_gen_binary (MINUS, mode, delta, tmp0); | |
2771 | } | |
2772 | else | |
2773 | { | |
2774 | /* Condition in shape a <= b - s * i | |
2775 | We must know that a - s does not overflow and a - s <= b and then | |
2776 | we can again compute number of iterations as (b - (a - s)) / s. */ | |
2777 | step = simplify_gen_unary (NEG, mode, iv1.step, mode); | |
6c3b938d RS |
2778 | tmp0 = lowpart_subreg (mode, iv0.base, comp_mode); |
2779 | tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); | |
50654f6c | 2780 | |
c9eb8097 | 2781 | bound = simplify_gen_binary (PLUS, mode, mode_mmin, |
6c3b938d | 2782 | lowpart_subreg (mode, step, comp_mode)); |
6b9b7b4c ZD |
2783 | if (step_is_pow2) |
2784 | { | |
2785 | rtx t0, t1; | |
2786 | ||
2787 | /* If s is power of 2, we know that the loop is infinite if | |
2788 | a % s <= b % s and a - s overflows. */ | |
2789 | assumption = simplify_gen_relational (reverse_condition (cond), | |
2790 | SImode, mode, | |
2791 | bound, tmp0); | |
2792 | ||
2793 | t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step); | |
2794 | t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step); | |
2795 | tmp = simplify_gen_relational (cond, SImode, mode, t0, t1); | |
2796 | assumption = simplify_gen_binary (AND, SImode, assumption, tmp); | |
2797 | desc->infinite = | |
2798 | alloc_EXPR_LIST (0, assumption, desc->infinite); | |
2799 | } | |
2800 | else | |
2801 | { | |
2802 | assumption = simplify_gen_relational (cond, SImode, mode, | |
2803 | bound, tmp0); | |
2804 | desc->assumptions = | |
2805 | alloc_EXPR_LIST (0, assumption, desc->assumptions); | |
2806 | } | |
50654f6c ZD |
2807 | |
2808 | tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step); | |
6c3b938d | 2809 | tmp = lowpart_subreg (mode, tmp, comp_mode); |
50654f6c ZD |
2810 | assumption = simplify_gen_relational (reverse_condition (cond), |
2811 | SImode, mode, | |
2812 | tmp, tmp1); | |
2813 | delta = simplify_gen_binary (MINUS, mode, tmp0, step); | |
2814 | delta = simplify_gen_binary (MINUS, mode, tmp1, delta); | |
2815 | } | |
2816 | if (assumption == const_true_rtx) | |
4fbe4f91 | 2817 | goto zero_iter_simplify; |
50654f6c ZD |
2818 | else if (assumption != const0_rtx) |
2819 | desc->noloop_assumptions = | |
2820 | alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions); | |
2821 | delta = simplify_gen_binary (UDIV, mode, delta, step); | |
2822 | desc->niter_expr = delta; | |
2823 | } | |
2824 | ||
fe3f617f ZD |
2825 | old_niter = desc->niter_expr; |
2826 | ||
50654f6c ZD |
2827 | simplify_using_initial_values (loop, AND, &desc->assumptions); |
2828 | if (desc->assumptions | |
2829 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2830 | goto fail; | |
2831 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2832 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
f822d252 | 2833 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
50654f6c ZD |
2834 | |
2835 | /* Rerun the simplification. Consider code (created by copying loop headers) | |
2836 | ||
2837 | i = 0; | |
2838 | ||
2839 | if (0 < n) | |
2840 | { | |
2841 | do | |
2842 | { | |
2843 | i++; | |
2844 | } while (i < n); | |
2845 | } | |
2846 | ||
2847 | The first pass determines that i = 0, the second pass uses it to eliminate | |
2848 | noloop assumption. */ | |
2849 | ||
2850 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2851 | if (desc->assumptions | |
2852 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2853 | goto fail; | |
2854 | simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); | |
2855 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
f822d252 | 2856 | simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); |
50654f6c | 2857 | |
689ba89d ZD |
2858 | if (desc->noloop_assumptions |
2859 | && XEXP (desc->noloop_assumptions, 0) == const_true_rtx) | |
2860 | goto zero_iter; | |
2861 | ||
481683e1 | 2862 | if (CONST_INT_P (desc->niter_expr)) |
50654f6c | 2863 | { |
a9243bfc | 2864 | uint64_t val = INTVAL (desc->niter_expr); |
50654f6c ZD |
2865 | |
2866 | desc->const_iter = true; | |
e3a8f1fa | 2867 | desc->niter = val & GET_MODE_MASK (desc->mode); |
bcd8d322 JH |
2868 | if (!desc->infinite |
2869 | && !desc->assumptions) | |
807e902e | 2870 | record_niter_bound (loop, desc->niter, false, true); |
50654f6c | 2871 | } |
fe3f617f ZD |
2872 | else |
2873 | { | |
daa57386 | 2874 | max = determine_max_iter (loop, desc, old_niter); |
8386a7ea JH |
2875 | if (!max) |
2876 | goto zero_iter_simplify; | |
bcd8d322 JH |
2877 | if (!desc->infinite |
2878 | && !desc->assumptions) | |
807e902e | 2879 | record_niter_bound (loop, max, false, true); |
fe3f617f ZD |
2880 | |
2881 | /* simplify_using_initial_values does a copy propagation on the registers | |
2882 | in the expression for the number of iterations. This prolongs life | |
2883 | ranges of registers and increases register pressure, and usually | |
2884 | brings no gain (and if it happens to do, the cse pass will take care | |
2885 | of it anyway). So prevent this behavior, unless it enabled us to | |
2886 | derive that the number of iterations is a constant. */ | |
2887 | desc->niter_expr = old_niter; | |
2888 | } | |
50654f6c ZD |
2889 | |
2890 | return; | |
2891 | ||
4fbe4f91 ZD |
2892 | zero_iter_simplify: |
2893 | /* Simplify the assumptions. */ | |
2894 | simplify_using_initial_values (loop, AND, &desc->assumptions); | |
2895 | if (desc->assumptions | |
2896 | && XEXP (desc->assumptions, 0) == const0_rtx) | |
2897 | goto fail; | |
2898 | simplify_using_initial_values (loop, IOR, &desc->infinite); | |
50654f6c | 2899 | |
4fbe4f91 | 2900 | /* Fallthru. */ |
50654f6c ZD |
2901 | zero_iter: |
2902 | desc->const_iter = true; | |
2903 | desc->niter = 0; | |
807e902e | 2904 | record_niter_bound (loop, 0, true, true); |
4fbe4f91 | 2905 | desc->noloop_assumptions = NULL_RTX; |
50654f6c ZD |
2906 | desc->niter_expr = const0_rtx; |
2907 | return; | |
4fbe4f91 ZD |
2908 | |
2909 | fail: | |
2910 | desc->simple_p = false; | |
2911 | return; | |
50654f6c ZD |
2912 | } |
2913 | ||
2914 | /* Checks whether E is a simple exit from LOOP and stores its description | |
f2dca510 | 2915 | into DESC. */ |
50654f6c ZD |
2916 | |
2917 | static void | |
2918 | check_simple_exit (struct loop *loop, edge e, struct niter_desc *desc) | |
2919 | { | |
2920 | basic_block exit_bb; | |
61aa0978 DM |
2921 | rtx condition; |
2922 | rtx_insn *at; | |
628f6a4e | 2923 | edge ein; |
50654f6c ZD |
2924 | |
2925 | exit_bb = e->src; | |
2926 | desc->simple_p = false; | |
2927 | ||
2928 | /* It must belong directly to the loop. */ | |
2929 | if (exit_bb->loop_father != loop) | |
2930 | return; | |
2931 | ||
2932 | /* It must be tested (at least) once during any iteration. */ | |
2933 | if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb)) | |
2934 | return; | |
2935 | ||
2936 | /* It must end in a simple conditional jump. */ | |
2937 | if (!any_condjump_p (BB_END (exit_bb))) | |
2938 | return; | |
2939 | ||
628f6a4e BE |
2940 | ein = EDGE_SUCC (exit_bb, 0); |
2941 | if (ein == e) | |
2942 | ein = EDGE_SUCC (exit_bb, 1); | |
50654f6c ZD |
2943 | |
2944 | desc->out_edge = e; | |
628f6a4e | 2945 | desc->in_edge = ein; |
50654f6c ZD |
2946 | |
2947 | /* Test whether the condition is suitable. */ | |
628f6a4e | 2948 | if (!(condition = get_condition (BB_END (ein->src), &at, false, false))) |
50654f6c ZD |
2949 | return; |
2950 | ||
628f6a4e | 2951 | if (ein->flags & EDGE_FALLTHRU) |
50654f6c ZD |
2952 | { |
2953 | condition = reversed_condition (condition); | |
2954 | if (!condition) | |
2955 | return; | |
2956 | } | |
2957 | ||
2958 | /* Check that we are able to determine number of iterations and fill | |
2959 | in information about it. */ | |
61aa0978 | 2960 | iv_number_of_iterations (loop, at, condition, desc); |
50654f6c ZD |
2961 | } |
2962 | ||
f2dca510 | 2963 | /* Finds a simple exit of LOOP and stores its description into DESC. */ |
50654f6c ZD |
2964 | |
2965 | void | |
2966 | find_simple_exit (struct loop *loop, struct niter_desc *desc) | |
2967 | { | |
2968 | unsigned i; | |
2969 | basic_block *body; | |
2970 | edge e; | |
2971 | struct niter_desc act; | |
2972 | bool any = false; | |
628f6a4e | 2973 | edge_iterator ei; |
50654f6c ZD |
2974 | |
2975 | desc->simple_p = false; | |
2976 | body = get_loop_body (loop); | |
2977 | ||
2978 | for (i = 0; i < loop->num_nodes; i++) | |
2979 | { | |
628f6a4e | 2980 | FOR_EACH_EDGE (e, ei, body[i]->succs) |
50654f6c ZD |
2981 | { |
2982 | if (flow_bb_inside_loop_p (loop, e->dest)) | |
2983 | continue; | |
b8698a0f | 2984 | |
50654f6c ZD |
2985 | check_simple_exit (loop, e, &act); |
2986 | if (!act.simple_p) | |
2987 | continue; | |
2988 | ||
50654f6c ZD |
2989 | if (!any) |
2990 | any = true; | |
4fbe4f91 ZD |
2991 | else |
2992 | { | |
2993 | /* Prefer constant iterations; the less the better. */ | |
2994 | if (!act.const_iter | |
2995 | || (desc->const_iter && act.niter >= desc->niter)) | |
2996 | continue; | |
2997 | ||
2998 | /* Also if the actual exit may be infinite, while the old one | |
2999 | not, prefer the old one. */ | |
3000 | if (act.infinite && !desc->infinite) | |
3001 | continue; | |
3002 | } | |
b8698a0f | 3003 | |
50654f6c ZD |
3004 | *desc = act; |
3005 | } | |
3006 | } | |
3007 | ||
c263766c | 3008 | if (dump_file) |
50654f6c ZD |
3009 | { |
3010 | if (desc->simple_p) | |
3011 | { | |
c263766c RH |
3012 | fprintf (dump_file, "Loop %d is simple:\n", loop->num); |
3013 | fprintf (dump_file, " simple exit %d -> %d\n", | |
50654f6c ZD |
3014 | desc->out_edge->src->index, |
3015 | desc->out_edge->dest->index); | |
3016 | if (desc->assumptions) | |
3017 | { | |
c263766c RH |
3018 | fprintf (dump_file, " assumptions: "); |
3019 | print_rtl (dump_file, desc->assumptions); | |
3020 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
3021 | } |
3022 | if (desc->noloop_assumptions) | |
3023 | { | |
c263766c RH |
3024 | fprintf (dump_file, " does not roll if: "); |
3025 | print_rtl (dump_file, desc->noloop_assumptions); | |
3026 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
3027 | } |
3028 | if (desc->infinite) | |
3029 | { | |
c263766c RH |
3030 | fprintf (dump_file, " infinite if: "); |
3031 | print_rtl (dump_file, desc->infinite); | |
3032 | fprintf (dump_file, "\n"); | |
50654f6c ZD |
3033 | } |
3034 | ||
c263766c RH |
3035 | fprintf (dump_file, " number of iterations: "); |
3036 | print_rtl (dump_file, desc->niter_expr); | |
3037 | fprintf (dump_file, "\n"); | |
50654f6c | 3038 | |
e3a8f1fa | 3039 | fprintf (dump_file, " upper bound: %li\n", |
1ef88893 | 3040 | (long)get_max_loop_iterations_int (loop)); |
e3a8f1fa | 3041 | fprintf (dump_file, " realistic bound: %li\n", |
1ef88893 | 3042 | (long)get_estimated_loop_iterations_int (loop)); |
50654f6c ZD |
3043 | } |
3044 | else | |
c263766c | 3045 | fprintf (dump_file, "Loop %d is not simple.\n", loop->num); |
50654f6c ZD |
3046 | } |
3047 | ||
3048 | free (body); | |
3049 | } | |
3050 | ||
3051 | /* Creates a simple loop description of LOOP if it was not computed | |
3052 | already. */ | |
3053 | ||
3054 | struct niter_desc * | |
3055 | get_simple_loop_desc (struct loop *loop) | |
3056 | { | |
3057 | struct niter_desc *desc = simple_loop_desc (loop); | |
3058 | ||
3059 | if (desc) | |
3060 | return desc; | |
3061 | ||
1242bc9d R |
3062 | /* At least desc->infinite is not always initialized by |
3063 | find_simple_loop_exit. */ | |
766090c2 | 3064 | desc = ggc_cleared_alloc<niter_desc> (); |
50654f6c ZD |
3065 | iv_analysis_loop_init (loop); |
3066 | find_simple_exit (loop, desc); | |
ef23e6a2 | 3067 | loop->simple_loop_desc = desc; |
50654f6c | 3068 | |
f9cc1a70 PB |
3069 | if (desc->simple_p && (desc->assumptions || desc->infinite)) |
3070 | { | |
b8698a0f | 3071 | const char *wording; |
f9cc1a70 | 3072 | |
b8698a0f | 3073 | /* Assume that no overflow happens and that the loop is finite. |
f9cc1a70 PB |
3074 | We already warned at the tree level if we ran optimizations there. */ |
3075 | if (!flag_tree_loop_optimize && warn_unsafe_loop_optimizations) | |
3076 | { | |
3077 | if (desc->infinite) | |
3078 | { | |
b8698a0f | 3079 | wording = |
f9cc1a70 PB |
3080 | flag_unsafe_loop_optimizations |
3081 | ? N_("assuming that the loop is not infinite") | |
3082 | : N_("cannot optimize possibly infinite loops"); | |
3083 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
3084 | gettext (wording)); | |
3085 | } | |
3086 | if (desc->assumptions) | |
3087 | { | |
b8698a0f | 3088 | wording = |
f9cc1a70 PB |
3089 | flag_unsafe_loop_optimizations |
3090 | ? N_("assuming that the loop counter does not overflow") | |
3091 | : N_("cannot optimize loop, the loop counter may overflow"); | |
3092 | warning (OPT_Wunsafe_loop_optimizations, "%s", | |
3093 | gettext (wording)); | |
3094 | } | |
3095 | } | |
3096 | ||
3097 | if (flag_unsafe_loop_optimizations) | |
3098 | { | |
3099 | desc->assumptions = NULL_RTX; | |
3100 | desc->infinite = NULL_RTX; | |
3101 | } | |
3102 | } | |
3103 | ||
50654f6c ZD |
3104 | return desc; |
3105 | } | |
3106 | ||
3107 | /* Releases simple loop description for LOOP. */ | |
3108 | ||
3109 | void | |
3110 | free_simple_loop_desc (struct loop *loop) | |
3111 | { | |
3112 | struct niter_desc *desc = simple_loop_desc (loop); | |
3113 | ||
3114 | if (!desc) | |
3115 | return; | |
3116 | ||
ef23e6a2 RB |
3117 | ggc_free (desc); |
3118 | loop->simple_loop_desc = NULL; | |
50654f6c | 3119 | } |