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3eb9a99d | 1 | /* Move registers around to reduce number of move instructions needed. |
3072d30e | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, |
3 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
4 | Free Software Foundation, Inc. | |
3eb9a99d | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
3eb9a99d | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 10 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 11 | version. |
3eb9a99d | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
3eb9a99d | 17 | |
18 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
3eb9a99d | 21 | |
22 | ||
23 | /* This module looks for cases where matching constraints would force | |
24 | an instruction to need a reload, and this reload would be a register | |
25 | to register move. It then attempts to change the registers used by the | |
26 | instruction to avoid the move instruction. */ | |
27 | ||
28 | #include "config.h" | |
405711de | 29 | #include "system.h" |
805e22b2 | 30 | #include "coretypes.h" |
31 | #include "tm.h" | |
32e0908a | 32 | #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ |
7953c610 | 33 | #include "tm_p.h" |
3eb9a99d | 34 | #include "insn-config.h" |
35 | #include "recog.h" | |
36 | #include "output.h" | |
3eb9a99d | 37 | #include "regs.h" |
57fc958f | 38 | #include "hard-reg-set.h" |
39 | #include "flags.h" | |
0a893c29 | 40 | #include "function.h" |
57fc958f | 41 | #include "expr.h" |
2f08c02a | 42 | #include "basic-block.h" |
9d269eaf | 43 | #include "except.h" |
ce1fd7fc | 44 | #include "toplev.h" |
75eb327c | 45 | #include "reload.h" |
77fce4cd | 46 | #include "timevar.h" |
47 | #include "tree-pass.h" | |
3072d30e | 48 | #include "df.h" |
17cdb3a8 | 49 | |
3ad4992f | 50 | static int perhaps_ends_bb_p (rtx); |
51 | static int optimize_reg_copy_1 (rtx, rtx, rtx); | |
52 | static void optimize_reg_copy_2 (rtx, rtx, rtx); | |
53 | static void optimize_reg_copy_3 (rtx, rtx, rtx); | |
f9f428c6 | 54 | static void copy_src_to_dest (rtx, rtx, rtx); |
3eb9a99d | 55 | |
57fc958f | 56 | struct match { |
57 | int with[MAX_RECOG_OPERANDS]; | |
58 | enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; | |
59 | int commutative[MAX_RECOG_OPERANDS]; | |
60 | int early_clobber[MAX_RECOG_OPERANDS]; | |
61 | }; | |
62 | ||
3ad4992f | 63 | static rtx discover_flags_reg (void); |
64 | static void mark_flags_life_zones (rtx); | |
81a410b1 | 65 | static void flags_set_1 (rtx, const_rtx, void *); |
3ad4992f | 66 | |
67 | static int try_auto_increment (rtx, rtx, rtx, rtx, HOST_WIDE_INT, int); | |
68 | static int find_matches (rtx, struct match *); | |
69 | static void replace_in_call_usage (rtx *, unsigned int, rtx, rtx); | |
3f5be5f4 | 70 | static int fixup_match_1 (rtx, rtx, rtx, rtx, rtx, int, int, int); |
3ad4992f | 71 | static int stable_and_no_regs_but_for_p (rtx, rtx, rtx); |
72 | static int regclass_compatible_p (int, int); | |
73 | static int replacement_quality (rtx); | |
3f5be5f4 | 74 | static int fixup_match_2 (rtx, rtx, rtx, rtx); |
3eb9a99d | 75 | |
7fd957fe | 76 | /* Return nonzero if registers with CLASS1 and CLASS2 can be merged without |
1b7b2f8f | 77 | causing too much register allocation problems. */ |
78 | static int | |
3ad4992f | 79 | regclass_compatible_p (int class0, int class1) |
1b7b2f8f | 80 | { |
81 | return (class0 == class1 | |
82 | || (reg_class_subset_p (class0, class1) | |
83 | && ! CLASS_LIKELY_SPILLED_P (class0)) | |
84 | || (reg_class_subset_p (class1, class0) | |
85 | && ! CLASS_LIKELY_SPILLED_P (class1))); | |
86 | } | |
87 | ||
3072d30e | 88 | /* Find the place in the rtx X where REG is used as a memory address. |
89 | Return the MEM rtx that so uses it. | |
90 | If PLUSCONST is nonzero, search instead for a memory address equivalent to | |
91 | (plus REG (const_int PLUSCONST)). | |
92 | ||
93 | If such an address does not appear, return 0. | |
94 | If REG appears more than once, or is used other than in such an address, | |
95 | return (rtx) 1. */ | |
96 | ||
97 | static rtx | |
98 | find_use_as_address (rtx x, rtx reg, HOST_WIDE_INT plusconst) | |
99 | { | |
100 | enum rtx_code code = GET_CODE (x); | |
101 | const char * const fmt = GET_RTX_FORMAT (code); | |
102 | int i; | |
103 | rtx value = 0; | |
104 | rtx tem; | |
105 | ||
106 | if (code == MEM && XEXP (x, 0) == reg && plusconst == 0) | |
107 | return x; | |
108 | ||
109 | if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS | |
110 | && XEXP (XEXP (x, 0), 0) == reg | |
111 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
112 | && INTVAL (XEXP (XEXP (x, 0), 1)) == plusconst) | |
113 | return x; | |
114 | ||
115 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
116 | { | |
117 | /* If REG occurs inside a MEM used in a bit-field reference, | |
118 | that is unacceptable. */ | |
119 | if (find_use_as_address (XEXP (x, 0), reg, 0) != 0) | |
120 | return (rtx) (size_t) 1; | |
121 | } | |
122 | ||
123 | if (x == reg) | |
124 | return (rtx) (size_t) 1; | |
125 | ||
126 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
127 | { | |
128 | if (fmt[i] == 'e') | |
129 | { | |
130 | tem = find_use_as_address (XEXP (x, i), reg, plusconst); | |
131 | if (value == 0) | |
132 | value = tem; | |
133 | else if (tem != 0) | |
134 | return (rtx) (size_t) 1; | |
135 | } | |
136 | else if (fmt[i] == 'E') | |
137 | { | |
138 | int j; | |
139 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
140 | { | |
141 | tem = find_use_as_address (XVECEXP (x, i, j), reg, plusconst); | |
142 | if (value == 0) | |
143 | value = tem; | |
144 | else if (tem != 0) | |
145 | return (rtx) (size_t) 1; | |
146 | } | |
147 | } | |
148 | } | |
149 | ||
150 | return value; | |
151 | } | |
152 | ||
153 | ||
3eb9a99d | 154 | /* INC_INSN is an instruction that adds INCREMENT to REG. |
155 | Try to fold INC_INSN as a post/pre in/decrement into INSN. | |
156 | Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. | |
157 | Return nonzero for success. */ | |
158 | static int | |
3ad4992f | 159 | try_auto_increment (rtx insn, rtx inc_insn, rtx inc_insn_set, rtx reg, |
160 | HOST_WIDE_INT increment, int pre) | |
3eb9a99d | 161 | { |
162 | enum rtx_code inc_code; | |
163 | ||
164 | rtx pset = single_set (insn); | |
165 | if (pset) | |
166 | { | |
167 | /* Can't use the size of SET_SRC, we might have something like | |
168 | (sign_extend:SI (mem:QI ... */ | |
169 | rtx use = find_use_as_address (pset, reg, 0); | |
be051fd5 | 170 | if (use != 0 && use != (rtx) (size_t) 1) |
3eb9a99d | 171 | { |
172 | int size = GET_MODE_SIZE (GET_MODE (use)); | |
173 | if (0 | |
e4e498cf | 174 | || (HAVE_POST_INCREMENT |
175 | && pre == 0 && (inc_code = POST_INC, increment == size)) | |
176 | || (HAVE_PRE_INCREMENT | |
177 | && pre == 1 && (inc_code = PRE_INC, increment == size)) | |
178 | || (HAVE_POST_DECREMENT | |
179 | && pre == 0 && (inc_code = POST_DEC, increment == -size)) | |
180 | || (HAVE_PRE_DECREMENT | |
181 | && pre == 1 && (inc_code = PRE_DEC, increment == -size)) | |
57fc958f | 182 | ) |
183 | { | |
184 | if (inc_insn_set) | |
185 | validate_change | |
4f271297 | 186 | (inc_insn, |
57fc958f | 187 | &SET_SRC (inc_insn_set), |
3eb9a99d | 188 | XEXP (SET_SRC (inc_insn_set), 0), 1); |
57fc958f | 189 | validate_change (insn, &XEXP (use, 0), |
941522d6 | 190 | gen_rtx_fmt_e (inc_code, Pmode, reg), 1); |
57fc958f | 191 | if (apply_change_group ()) |
192 | { | |
cdcbc6d4 | 193 | /* If there is a REG_DEAD note on this insn, we must |
194 | change this not to REG_UNUSED meaning that the register | |
195 | is set, but the value is dead. Failure to do so will | |
73b5bf07 | 196 | result in sched1 dying -- when it recomputes lifetime |
cdcbc6d4 | 197 | information, the number of REG_DEAD notes will have |
198 | changed. */ | |
199 | rtx note = find_reg_note (insn, REG_DEAD, reg); | |
200 | if (note) | |
201 | PUT_MODE (note, REG_UNUSED); | |
202 | ||
a1ddb869 | 203 | add_reg_note (insn, REG_INC, reg); |
204 | ||
57fc958f | 205 | if (! inc_insn_set) |
b36d64df | 206 | delete_insn (inc_insn); |
3eb9a99d | 207 | return 1; |
57fc958f | 208 | } |
209 | } | |
210 | } | |
211 | } | |
212 | return 0; | |
213 | } | |
49de5893 | 214 | \f |
215 | /* Determine if the pattern generated by add_optab has a clobber, | |
216 | such as might be issued for a flags hard register. To make the | |
217 | code elsewhere simpler, we handle cc0 in this same framework. | |
218 | ||
219 | Return the register if one was discovered. Return NULL_RTX if | |
220 | if no flags were found. Return pc_rtx if we got confused. */ | |
221 | ||
222 | static rtx | |
3ad4992f | 223 | discover_flags_reg (void) |
49de5893 | 224 | { |
225 | rtx tmp; | |
1cb249e1 | 226 | tmp = gen_rtx_REG (word_mode, 10000); |
6757f5d6 | 227 | tmp = gen_add3_insn (tmp, tmp, const2_rtx); |
49de5893 | 228 | |
4f271297 | 229 | /* If we get something that isn't a simple set, or a |
49de5893 | 230 | [(set ..) (clobber ..)], this whole function will go wrong. */ |
231 | if (GET_CODE (tmp) == SET) | |
232 | return NULL_RTX; | |
233 | else if (GET_CODE (tmp) == PARALLEL) | |
234 | { | |
235 | int found; | |
236 | ||
237 | if (XVECLEN (tmp, 0) != 2) | |
238 | return pc_rtx; | |
239 | tmp = XVECEXP (tmp, 0, 1); | |
240 | if (GET_CODE (tmp) != CLOBBER) | |
241 | return pc_rtx; | |
242 | tmp = XEXP (tmp, 0); | |
243 | ||
244 | /* Don't do anything foolish if the md wanted to clobber a | |
245 | scratch or something. We only care about hard regs. | |
246 | Moreover we don't like the notion of subregs of hard regs. */ | |
247 | if (GET_CODE (tmp) == SUBREG | |
8ad4c111 | 248 | && REG_P (SUBREG_REG (tmp)) |
49de5893 | 249 | && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) |
250 | return pc_rtx; | |
8ad4c111 | 251 | found = (REG_P (tmp) && REGNO (tmp) < FIRST_PSEUDO_REGISTER); |
49de5893 | 252 | |
49de5893 | 253 | return (found ? tmp : NULL_RTX); |
49de5893 | 254 | } |
255 | ||
256 | return pc_rtx; | |
257 | } | |
258 | ||
259 | /* It is a tedious task identifying when the flags register is live and | |
260 | when it is safe to optimize. Since we process the instruction stream | |
261 | multiple times, locate and record these live zones by marking the | |
4f271297 | 262 | mode of the instructions -- |
49de5893 | 263 | |
264 | QImode is used on the instruction at which the flags becomes live. | |
265 | ||
266 | HImode is used within the range (exclusive) that the flags are | |
267 | live. Thus the user of the flags is not marked. | |
268 | ||
269 | All other instructions are cleared to VOIDmode. */ | |
270 | ||
271 | /* Used to communicate with flags_set_1. */ | |
272 | static rtx flags_set_1_rtx; | |
273 | static int flags_set_1_set; | |
274 | ||
275 | static void | |
3ad4992f | 276 | mark_flags_life_zones (rtx flags) |
49de5893 | 277 | { |
278 | int flags_regno; | |
279 | int flags_nregs; | |
4c26117a | 280 | basic_block block; |
49de5893 | 281 | |
956460dc | 282 | #ifdef HAVE_cc0 |
283 | /* If we found a flags register on a cc0 host, bail. */ | |
284 | if (flags == NULL_RTX) | |
285 | flags = cc0_rtx; | |
286 | else if (flags != cc0_rtx) | |
287 | flags = pc_rtx; | |
288 | #endif | |
4f271297 | 289 | |
49de5893 | 290 | /* Simple cases first: if no flags, clear all modes. If confusing, |
291 | mark the entire function as being in a flags shadow. */ | |
292 | if (flags == NULL_RTX || flags == pc_rtx) | |
293 | { | |
294 | enum machine_mode mode = (flags ? HImode : VOIDmode); | |
295 | rtx insn; | |
337d789b | 296 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
49de5893 | 297 | PUT_MODE (insn, mode); |
298 | return; | |
299 | } | |
300 | ||
301 | #ifdef HAVE_cc0 | |
302 | flags_regno = -1; | |
303 | flags_nregs = 1; | |
304 | #else | |
305 | flags_regno = REGNO (flags); | |
67d6c12b | 306 | flags_nregs = hard_regno_nregs[flags_regno][GET_MODE (flags)]; |
49de5893 | 307 | #endif |
308 | flags_set_1_rtx = flags; | |
57fc958f | 309 | |
49de5893 | 310 | /* Process each basic block. */ |
4c26117a | 311 | FOR_EACH_BB_REVERSE (block) |
49de5893 | 312 | { |
313 | rtx insn, end; | |
314 | int live; | |
315 | ||
5496dbfc | 316 | insn = BB_HEAD (block); |
317 | end = BB_END (block); | |
49de5893 | 318 | |
319 | /* Look out for the (unlikely) case of flags being live across | |
320 | basic block boundaries. */ | |
321 | live = 0; | |
322 | #ifndef HAVE_cc0 | |
323 | { | |
324 | int i; | |
325 | for (i = 0; i < flags_nregs; ++i) | |
deb2741b | 326 | live |= REGNO_REG_SET_P (df_get_live_in (block), flags_regno + i); |
49de5893 | 327 | } |
328 | #endif | |
329 | ||
330 | while (1) | |
331 | { | |
332 | /* Process liveness in reverse order of importance -- | |
333 | alive, death, birth. This lets more important info | |
334 | overwrite the mode of lesser info. */ | |
335 | ||
9204e736 | 336 | if (INSN_P (insn)) |
49de5893 | 337 | { |
338 | #ifdef HAVE_cc0 | |
339 | /* In the cc0 case, death is not marked in reg notes, | |
340 | but is instead the mere use of cc0 when it is alive. */ | |
341 | if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
342 | live = 0; | |
343 | #else | |
344 | /* In the hard reg case, we watch death notes. */ | |
345 | if (live && find_regno_note (insn, REG_DEAD, flags_regno)) | |
346 | live = 0; | |
347 | #endif | |
348 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
349 | ||
3927afe0 | 350 | /* In either case, birth is denoted simply by its presence |
49de5893 | 351 | as the destination of a set. */ |
352 | flags_set_1_set = 0; | |
ec8895d7 | 353 | note_stores (PATTERN (insn), flags_set_1, NULL); |
49de5893 | 354 | if (flags_set_1_set) |
355 | { | |
356 | live = 1; | |
357 | PUT_MODE (insn, QImode); | |
358 | } | |
359 | } | |
360 | else | |
361 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
362 | ||
363 | if (insn == end) | |
364 | break; | |
365 | insn = NEXT_INSN (insn); | |
366 | } | |
367 | } | |
368 | } | |
369 | ||
370 | /* A subroutine of mark_flags_life_zones, called through note_stores. */ | |
371 | ||
372 | static void | |
81a410b1 | 373 | flags_set_1 (rtx x, const_rtx pat, void *data ATTRIBUTE_UNUSED) |
49de5893 | 374 | { |
375 | if (GET_CODE (pat) == SET | |
376 | && reg_overlap_mentioned_p (x, flags_set_1_rtx)) | |
377 | flags_set_1_set = 1; | |
378 | } | |
379 | \f | |
57fc958f | 380 | static int *regno_src_regno; |
381 | ||
382 | /* Indicate how good a choice REG (which appears as a source) is to replace | |
383 | a destination register with. The higher the returned value, the better | |
384 | the choice. The main objective is to avoid using a register that is | |
385 | a candidate for tying to a hard register, since the output might in | |
386 | turn be a candidate to be tied to a different hard register. */ | |
5b379086 | 387 | static int |
3ad4992f | 388 | replacement_quality (rtx reg) |
57fc958f | 389 | { |
390 | int src_regno; | |
391 | ||
392 | /* Bad if this isn't a register at all. */ | |
8ad4c111 | 393 | if (!REG_P (reg)) |
57fc958f | 394 | return 0; |
395 | ||
396 | /* If this register is not meant to get a hard register, | |
397 | it is a poor choice. */ | |
398 | if (REG_LIVE_LENGTH (REGNO (reg)) < 0) | |
399 | return 0; | |
400 | ||
401 | src_regno = regno_src_regno[REGNO (reg)]; | |
402 | ||
403 | /* If it was not copied from another register, it is fine. */ | |
404 | if (src_regno < 0) | |
405 | return 3; | |
406 | ||
407 | /* Copied from a hard register? */ | |
408 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
409 | return 1; | |
410 | ||
411 | /* Copied from a pseudo register - not as bad as from a hard register, | |
412 | yet still cumbersome, since the register live length will be lengthened | |
413 | when the registers get tied. */ | |
414 | return 2; | |
415 | } | |
b9ad0217 | 416 | \f |
417 | /* Return 1 if INSN might end a basic block. */ | |
418 | ||
f82b06e0 | 419 | static int perhaps_ends_bb_p (rtx insn) |
b9ad0217 | 420 | { |
421 | switch (GET_CODE (insn)) | |
422 | { | |
423 | case CODE_LABEL: | |
424 | case JUMP_INSN: | |
425 | /* These always end a basic block. */ | |
426 | return 1; | |
57fc958f | 427 | |
b9ad0217 | 428 | case CALL_INSN: |
429 | /* A CALL_INSN might be the last insn of a basic block, if it is inside | |
430 | an EH region or if there are nonlocal gotos. Note that this test is | |
431 | very conservative. */ | |
3cf1ab8f | 432 | if (nonlocal_goto_handler_labels) |
433 | return 1; | |
d632b59a | 434 | /* Fall through. */ |
b9ad0217 | 435 | default: |
3cf1ab8f | 436 | return can_throw_internal (insn); |
b9ad0217 | 437 | } |
438 | } | |
439 | \f | |
97bcb74e | 440 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
441 | in INSN. | |
442 | ||
443 | Search forward to see if SRC dies before either it or DEST is modified, | |
444 | but don't scan past the end of a basic block. If so, we can replace SRC | |
4f271297 | 445 | with DEST and let SRC die in INSN. |
97bcb74e | 446 | |
447 | This will reduce the number of registers live in that range and may enable | |
448 | DEST to be tied to SRC, thus often saving one register in addition to a | |
449 | register-register copy. */ | |
450 | ||
451 | static int | |
3ad4992f | 452 | optimize_reg_copy_1 (rtx insn, rtx dest, rtx src) |
97bcb74e | 453 | { |
454 | rtx p, q; | |
455 | rtx note; | |
456 | rtx dest_death = 0; | |
457 | int sregno = REGNO (src); | |
458 | int dregno = REGNO (dest); | |
459 | ||
aa40f561 | 460 | /* We don't want to mess with hard regs if register classes are small. */ |
97bcb74e | 461 | if (sregno == dregno |
462 | || (SMALL_REGISTER_CLASSES | |
463 | && (sregno < FIRST_PSEUDO_REGISTER | |
464 | || dregno < FIRST_PSEUDO_REGISTER)) | |
465 | /* We don't see all updates to SP if they are in an auto-inc memory | |
466 | reference, so we must disallow this optimization on them. */ | |
467 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
468 | return 0; | |
469 | ||
470 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
471 | { | |
9ea31f2a | 472 | /* ??? We can't scan past the end of a basic block without updating |
b9ad0217 | 473 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
474 | if (perhaps_ends_bb_p (p)) | |
9ea31f2a | 475 | break; |
b9ad0217 | 476 | else if (! INSN_P (p)) |
97bcb74e | 477 | continue; |
478 | ||
479 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
6360286e | 480 | /* If SRC is an asm-declared register, it must not be replaced |
481 | in any asm. Unfortunately, the REG_EXPR tree for the asm | |
482 | variable may be absent in the SRC rtx, so we can't check the | |
483 | actual register declaration easily (the asm operand will have | |
484 | it, though). To avoid complicating the test for a rare case, | |
485 | we just don't perform register replacement for a hard reg | |
486 | mentioned in an asm. */ | |
487 | || (sregno < FIRST_PSEUDO_REGISTER | |
488 | && asm_noperands (PATTERN (p)) >= 0 | |
489 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
f2ee4302 | 490 | /* Don't change hard registers used by a call. */ |
491 | || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER | |
492 | && find_reg_fusage (p, USE, src)) | |
97bcb74e | 493 | /* Don't change a USE of a register. */ |
494 | || (GET_CODE (PATTERN (p)) == USE | |
495 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
496 | break; | |
497 | ||
498 | /* See if all of SRC dies in P. This test is slightly more | |
499 | conservative than it needs to be. */ | |
500 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
501 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
502 | { | |
503 | int failed = 0; | |
97bcb74e | 504 | int d_length = 0; |
908d57ee | 505 | int s_length = 0; |
97bcb74e | 506 | int d_n_calls = 0; |
908d57ee | 507 | int s_n_calls = 0; |
a8587796 | 508 | int s_freq_calls = 0; |
509 | int d_freq_calls = 0; | |
97bcb74e | 510 | |
511 | /* We can do the optimization. Scan forward from INSN again, | |
512 | replacing regs as we go. Set FAILED if a replacement can't | |
513 | be done. In that case, we can't move the death note for SRC. | |
514 | This should be rare. */ | |
515 | ||
516 | /* Set to stop at next insn. */ | |
517 | for (q = next_real_insn (insn); | |
518 | q != next_real_insn (p); | |
519 | q = next_real_insn (q)) | |
520 | { | |
521 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
522 | { | |
523 | /* If SRC is a hard register, we might miss some | |
524 | overlapping registers with validate_replace_rtx, | |
525 | so we would have to undo it. We can't if DEST is | |
526 | present in the insn, so fail in that combination | |
527 | of cases. */ | |
528 | if (sregno < FIRST_PSEUDO_REGISTER | |
529 | && reg_mentioned_p (dest, PATTERN (q))) | |
530 | failed = 1; | |
fc7c3aae | 531 | |
532 | /* Attempt to replace all uses. */ | |
533 | else if (!validate_replace_rtx (src, dest, q)) | |
534 | failed = 1; | |
97bcb74e | 535 | |
fc7c3aae | 536 | /* If this succeeded, but some part of the register |
537 | is still present, undo the replacement. */ | |
538 | else if (sregno < FIRST_PSEUDO_REGISTER | |
539 | && reg_overlap_mentioned_p (src, PATTERN (q))) | |
97bcb74e | 540 | { |
541 | validate_replace_rtx (dest, src, q); | |
542 | failed = 1; | |
543 | } | |
544 | } | |
545 | ||
908d57ee | 546 | /* For SREGNO, count the total number of insns scanned. |
547 | For DREGNO, count the total number of insns scanned after | |
548 | passing the death note for DREGNO. */ | |
549 | s_length++; | |
97bcb74e | 550 | if (dest_death) |
551 | d_length++; | |
552 | ||
553 | /* If the insn in which SRC dies is a CALL_INSN, don't count it | |
554 | as a call that has been crossed. Otherwise, count it. */ | |
6d7dc5b9 | 555 | if (q != p && CALL_P (q)) |
97bcb74e | 556 | { |
908d57ee | 557 | /* Similarly, total calls for SREGNO, total calls beyond |
558 | the death note for DREGNO. */ | |
559 | s_n_calls++; | |
a8587796 | 560 | s_freq_calls += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (q)); |
97bcb74e | 561 | if (dest_death) |
a8587796 | 562 | { |
563 | d_n_calls++; | |
564 | d_freq_calls += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (q)); | |
565 | } | |
97bcb74e | 566 | } |
567 | ||
568 | /* If DEST dies here, remove the death note and save it for | |
569 | later. Make sure ALL of DEST dies here; again, this is | |
570 | overly conservative. */ | |
571 | if (dest_death == 0 | |
572 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) | |
573 | { | |
574 | if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) | |
575 | failed = 1, dest_death = 0; | |
576 | else | |
577 | remove_note (q, dest_death); | |
578 | } | |
579 | } | |
580 | ||
581 | if (! failed) | |
582 | { | |
908d57ee | 583 | /* These counters need to be updated if and only if we are |
584 | going to move the REG_DEAD note. */ | |
97bcb74e | 585 | if (sregno >= FIRST_PSEUDO_REGISTER) |
586 | { | |
587 | if (REG_LIVE_LENGTH (sregno) >= 0) | |
588 | { | |
908d57ee | 589 | REG_LIVE_LENGTH (sregno) -= s_length; |
97bcb74e | 590 | /* REG_LIVE_LENGTH is only an approximation after |
591 | combine if sched is not run, so make sure that we | |
592 | still have a reasonable value. */ | |
593 | if (REG_LIVE_LENGTH (sregno) < 2) | |
594 | REG_LIVE_LENGTH (sregno) = 2; | |
595 | } | |
596 | ||
908d57ee | 597 | REG_N_CALLS_CROSSED (sregno) -= s_n_calls; |
a8587796 | 598 | REG_FREQ_CALLS_CROSSED (sregno) -= s_freq_calls; |
97bcb74e | 599 | } |
600 | ||
601 | /* Move death note of SRC from P to INSN. */ | |
602 | remove_note (p, note); | |
603 | XEXP (note, 1) = REG_NOTES (insn); | |
604 | REG_NOTES (insn) = note; | |
605 | } | |
606 | ||
88e8363a | 607 | /* DEST is also dead if INSN has a REG_UNUSED note for DEST. */ |
608 | if (! dest_death | |
609 | && (dest_death = find_regno_note (insn, REG_UNUSED, dregno))) | |
610 | { | |
611 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
612 | remove_note (insn, dest_death); | |
613 | } | |
614 | ||
97bcb74e | 615 | /* Put death note of DEST on P if we saw it die. */ |
616 | if (dest_death) | |
617 | { | |
618 | XEXP (dest_death, 1) = REG_NOTES (p); | |
619 | REG_NOTES (p) = dest_death; | |
908d57ee | 620 | |
621 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
622 | { | |
623 | /* If and only if we are moving the death note for DREGNO, | |
624 | then we need to update its counters. */ | |
625 | if (REG_LIVE_LENGTH (dregno) >= 0) | |
626 | REG_LIVE_LENGTH (dregno) += d_length; | |
627 | REG_N_CALLS_CROSSED (dregno) += d_n_calls; | |
a8587796 | 628 | REG_FREQ_CALLS_CROSSED (dregno) += d_freq_calls; |
908d57ee | 629 | } |
97bcb74e | 630 | } |
631 | ||
632 | return ! failed; | |
633 | } | |
634 | ||
635 | /* If SRC is a hard register which is set or killed in some other | |
636 | way, we can't do this optimization. */ | |
637 | else if (sregno < FIRST_PSEUDO_REGISTER | |
638 | && dead_or_set_p (p, src)) | |
639 | break; | |
640 | } | |
641 | return 0; | |
642 | } | |
643 | \f | |
644 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
645 | a sequence of insns that modify DEST followed by an insn that sets | |
646 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
647 | (There is no need to check if the insns in between actually modify | |
648 | DEST. We should not have cases where DEST is not modified, but | |
649 | the optimization is safe if no such modification is detected.) | |
650 | In that case, we can replace all uses of DEST, starting with INSN and | |
651 | ending with the set of SRC to DEST, with SRC. We do not do this | |
652 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
653 | call or if DEST dies before the copy back to SRC. | |
654 | ||
655 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
656 | this for hard registers since the substitutions we may make might fail. */ | |
657 | ||
658 | static void | |
3ad4992f | 659 | optimize_reg_copy_2 (rtx insn, rtx dest, rtx src) |
97bcb74e | 660 | { |
661 | rtx p, q; | |
662 | rtx set; | |
663 | int sregno = REGNO (src); | |
664 | int dregno = REGNO (dest); | |
665 | ||
666 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
667 | { | |
9ea31f2a | 668 | /* ??? We can't scan past the end of a basic block without updating |
b9ad0217 | 669 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
670 | if (perhaps_ends_bb_p (p)) | |
9ea31f2a | 671 | break; |
b9ad0217 | 672 | else if (! INSN_P (p)) |
97bcb74e | 673 | continue; |
674 | ||
675 | set = single_set (p); | |
676 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
677 | && find_reg_note (p, REG_DEAD, dest)) | |
678 | { | |
679 | /* We can do the optimization. Scan forward from INSN again, | |
680 | replacing regs as we go. */ | |
681 | ||
682 | /* Set to stop at next insn. */ | |
683 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
9204e736 | 684 | if (INSN_P (q)) |
97bcb74e | 685 | { |
686 | if (reg_mentioned_p (dest, PATTERN (q))) | |
3072d30e | 687 | { |
688 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); | |
689 | df_insn_rescan (q); | |
690 | } | |
97bcb74e | 691 | |
e1caca42 | 692 | if (CALL_P (q)) |
693 | { | |
a8587796 | 694 | int freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (q)); |
e1caca42 | 695 | REG_N_CALLS_CROSSED (dregno)--; |
696 | REG_N_CALLS_CROSSED (sregno)++; | |
a8587796 | 697 | REG_FREQ_CALLS_CROSSED (dregno) -= freq; |
698 | REG_FREQ_CALLS_CROSSED (sregno) += freq; | |
e1caca42 | 699 | } |
97bcb74e | 700 | } |
701 | ||
702 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
703 | REG_N_DEATHS (dregno)--; | |
704 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
705 | REG_N_DEATHS (sregno)--; | |
706 | return; | |
707 | } | |
708 | ||
709 | if (reg_set_p (src, p) | |
710 | || find_reg_note (p, REG_DEAD, dest) | |
6d7dc5b9 | 711 | || (CALL_P (p) && REG_N_CALLS_CROSSED (sregno) == 0)) |
97bcb74e | 712 | break; |
713 | } | |
714 | } | |
e1caca42 | 715 | |
57fc958f | 716 | /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. |
717 | Look if SRC dies there, and if it is only set once, by loading | |
b903337a | 718 | it from memory. If so, try to incorporate the zero/sign extension |
57fc958f | 719 | into the memory read, change SRC to the mode of DEST, and alter |
720 | the remaining accesses to use the appropriate SUBREG. This allows | |
721 | SRC and DEST to be tied later. */ | |
722 | static void | |
3ad4992f | 723 | optimize_reg_copy_3 (rtx insn, rtx dest, rtx src) |
57fc958f | 724 | { |
725 | rtx src_reg = XEXP (src, 0); | |
726 | int src_no = REGNO (src_reg); | |
727 | int dst_no = REGNO (dest); | |
8d2d4ec8 | 728 | rtx p, set; |
57fc958f | 729 | enum machine_mode old_mode; |
730 | ||
731 | if (src_no < FIRST_PSEUDO_REGISTER | |
732 | || dst_no < FIRST_PSEUDO_REGISTER | |
733 | || ! find_reg_note (insn, REG_DEAD, src_reg) | |
4c922ed0 | 734 | || REG_N_DEATHS (src_no) != 1 |
57fc958f | 735 | || REG_N_SETS (src_no) != 1) |
736 | return; | |
422c8892 | 737 | for (p = PREV_INSN (insn); p && ! reg_set_p (src_reg, p); p = PREV_INSN (p)) |
b9ad0217 | 738 | /* ??? We can't scan past the end of a basic block without updating |
739 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ | |
740 | if (perhaps_ends_bb_p (p)) | |
741 | break; | |
9ea31f2a | 742 | |
422c8892 | 743 | if (! p) |
744 | return; | |
745 | ||
57fc958f | 746 | if (! (set = single_set (p)) |
e16ceb8e | 747 | || !MEM_P (SET_SRC (set)) |
6618e24d | 748 | /* If there's a REG_EQUIV note, this must be an insn that loads an |
749 | argument. Prefer keeping the note over doing this optimization. */ | |
750 | || find_reg_note (p, REG_EQUIV, NULL_RTX) | |
57fc958f | 751 | || SET_DEST (set) != src_reg) |
752 | return; | |
5d92a548 | 753 | |
de132707 | 754 | /* Be conservative: although this optimization is also valid for |
bc311e72 | 755 | volatile memory references, that could cause trouble in later passes. */ |
756 | if (MEM_VOLATILE_P (SET_SRC (set))) | |
757 | return; | |
758 | ||
5d92a548 | 759 | /* Do not use a SUBREG to truncate from one mode to another if truncation |
760 | is not a nop. */ | |
761 | if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) | |
762 | && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), | |
763 | GET_MODE_BITSIZE (GET_MODE (src_reg)))) | |
764 | return; | |
765 | ||
57fc958f | 766 | old_mode = GET_MODE (src_reg); |
767 | PUT_MODE (src_reg, GET_MODE (src)); | |
768 | XEXP (src, 0) = SET_SRC (set); | |
997026ee | 769 | |
770 | /* Include this change in the group so that it's easily undone if | |
771 | one of the changes in the group is invalid. */ | |
772 | validate_change (p, &SET_SRC (set), src, 1); | |
773 | ||
774 | /* Now walk forward making additional replacements. We want to be able | |
775 | to undo all the changes if a later substitution fails. */ | |
57fc958f | 776 | while (p = NEXT_INSN (p), p != insn) |
777 | { | |
9204e736 | 778 | if (! INSN_P (p)) |
57fc958f | 779 | continue; |
997026ee | 780 | |
f024691d | 781 | /* Make a tentative change. */ |
8d2d4ec8 | 782 | validate_replace_rtx_group (src_reg, |
783 | gen_lowpart_SUBREG (old_mode, src_reg), | |
784 | p); | |
997026ee | 785 | } |
786 | ||
787 | validate_replace_rtx_group (src, src_reg, insn); | |
788 | ||
789 | /* Now see if all the changes are valid. */ | |
790 | if (! apply_change_group ()) | |
791 | { | |
792 | /* One or more changes were no good. Back out everything. */ | |
793 | PUT_MODE (src_reg, old_mode); | |
794 | XEXP (src, 0) = src_reg; | |
57fc958f | 795 | } |
6618e24d | 796 | else |
797 | { | |
798 | rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); | |
799 | if (note) | |
800 | remove_note (p, note); | |
801 | } | |
57fc958f | 802 | } |
803 | ||
2f08c02a | 804 | \f |
805 | /* If we were not able to update the users of src to use dest directly, try | |
806 | instead moving the value to dest directly before the operation. */ | |
807 | ||
a986b5e0 | 808 | static void |
f9f428c6 | 809 | copy_src_to_dest (rtx insn, rtx src, rtx dest) |
2f08c02a | 810 | { |
811 | rtx seq; | |
812 | rtx link; | |
813 | rtx next; | |
814 | rtx set; | |
815 | rtx move_insn; | |
816 | rtx *p_insn_notes; | |
817 | rtx *p_move_notes; | |
2f08c02a | 818 | int src_regno; |
819 | int dest_regno; | |
2f08c02a | 820 | int insn_uid; |
821 | int move_uid; | |
822 | ||
823 | /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant | |
824 | or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is | |
825 | parameter when there is no frame pointer that is not allocated a register. | |
826 | For now, we just reject them, rather than incrementing the live length. */ | |
827 | ||
8ad4c111 | 828 | if (REG_P (src) |
39e8e501 | 829 | && REG_LIVE_LENGTH (REGNO (src)) > 0 |
8ad4c111 | 830 | && REG_P (dest) |
39e8e501 | 831 | && REG_LIVE_LENGTH (REGNO (dest)) > 0 |
2f08c02a | 832 | && (set = single_set (insn)) != NULL_RTX |
c0d37149 | 833 | && !reg_mentioned_p (dest, SET_SRC (set)) |
834 | && GET_MODE (src) == GET_MODE (dest)) | |
2f08c02a | 835 | { |
150c4a53 | 836 | int old_num_regs = reg_rtx_no; |
837 | ||
2f08c02a | 838 | /* Generate the src->dest move. */ |
839 | start_sequence (); | |
840 | emit_move_insn (dest, src); | |
31d3e01c | 841 | seq = get_insns (); |
2f08c02a | 842 | end_sequence (); |
150c4a53 | 843 | /* If this sequence uses new registers, we may not use it. */ |
844 | if (old_num_regs != reg_rtx_no | |
845 | || ! validate_replace_rtx (src, dest, insn)) | |
846 | { | |
847 | /* We have to restore reg_rtx_no to its old value, lest | |
848 | recompute_reg_usage will try to compute the usage of the | |
849 | new regs, yet reg_n_info is not valid for them. */ | |
850 | reg_rtx_no = old_num_regs; | |
851 | return; | |
852 | } | |
2f08c02a | 853 | emit_insn_before (seq, insn); |
854 | move_insn = PREV_INSN (insn); | |
855 | p_move_notes = ®_NOTES (move_insn); | |
856 | p_insn_notes = ®_NOTES (insn); | |
857 | ||
45498ea1 | 858 | /* Move any notes mentioning src to the move instruction. */ |
2f08c02a | 859 | for (link = REG_NOTES (insn); link != NULL_RTX; link = next) |
860 | { | |
861 | next = XEXP (link, 1); | |
862 | if (XEXP (link, 0) == src) | |
863 | { | |
864 | *p_move_notes = link; | |
865 | p_move_notes = &XEXP (link, 1); | |
866 | } | |
867 | else | |
868 | { | |
869 | *p_insn_notes = link; | |
870 | p_insn_notes = &XEXP (link, 1); | |
871 | } | |
872 | } | |
873 | ||
874 | *p_move_notes = NULL_RTX; | |
875 | *p_insn_notes = NULL_RTX; | |
876 | ||
2f08c02a | 877 | insn_uid = INSN_UID (insn); |
878 | move_uid = INSN_UID (move_insn); | |
2f08c02a | 879 | |
880 | /* Update the various register tables. */ | |
881 | dest_regno = REGNO (dest); | |
3072d30e | 882 | INC_REG_N_SETS (dest_regno, 1); |
2f08c02a | 883 | REG_LIVE_LENGTH (dest_regno)++; |
2f08c02a | 884 | src_regno = REGNO (src); |
885 | if (! find_reg_note (move_insn, REG_DEAD, src)) | |
886 | REG_LIVE_LENGTH (src_regno)++; | |
2f08c02a | 887 | } |
888 | } | |
889 | ||
681f6fc5 | 890 | /* reg_set_in_bb[REGNO] points to basic block iff the register is set |
891 | only once in the given block and has REG_EQUAL note. */ | |
892 | ||
893 | basic_block *reg_set_in_bb; | |
894 | ||
895 | /* Size of reg_set_in_bb array. */ | |
896 | static unsigned int max_reg_computed; | |
897 | ||
2f08c02a | 898 | \f |
57fc958f | 899 | /* Return whether REG is set in only one location, and is set to a |
900 | constant, but is set in a different basic block from INSN (an | |
901 | instructions which uses REG). In this case REG is equivalent to a | |
902 | constant, and we don't want to break that equivalence, because that | |
903 | may increase register pressure and make reload harder. If REG is | |
904 | set in the same basic block as INSN, we don't worry about it, | |
905 | because we'll probably need a register anyhow (??? but what if REG | |
f9f428c6 | 906 | is used in a different basic block as well as this one?). */ |
57fc958f | 907 | |
681f6fc5 | 908 | static bool |
909 | reg_is_remote_constant_p (rtx reg, rtx insn) | |
57fc958f | 910 | { |
681f6fc5 | 911 | basic_block bb; |
19cb6b50 | 912 | rtx p; |
681f6fc5 | 913 | int max; |
57fc958f | 914 | |
681f6fc5 | 915 | if (!reg_set_in_bb) |
57fc958f | 916 | { |
681f6fc5 | 917 | max_reg_computed = max = max_reg_num (); |
f7f3687c | 918 | reg_set_in_bb = XCNEWVEC (basic_block, max); |
57fc958f | 919 | |
681f6fc5 | 920 | FOR_EACH_BB (bb) |
f9f428c6 | 921 | FOR_BB_INSNS (bb, p) |
922 | { | |
923 | rtx s; | |
924 | ||
925 | if (!INSN_P (p)) | |
926 | continue; | |
927 | s = single_set (p); | |
928 | /* This is the instruction which sets REG. If there is a | |
929 | REG_EQUAL note, then REG is equivalent to a constant. */ | |
930 | if (s != 0 | |
931 | && REG_P (SET_DEST (s)) | |
932 | && REG_N_SETS (REGNO (SET_DEST (s))) == 1 | |
933 | && find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
934 | reg_set_in_bb[REGNO (SET_DEST (s))] = bb; | |
935 | } | |
57fc958f | 936 | } |
f9f428c6 | 937 | |
681f6fc5 | 938 | gcc_assert (REGNO (reg) < max_reg_computed); |
939 | if (reg_set_in_bb[REGNO (reg)] == NULL) | |
940 | return false; | |
f9f428c6 | 941 | return (reg_set_in_bb[REGNO (reg)] != BLOCK_FOR_INSN (insn)); |
57fc958f | 942 | } |
943 | ||
41b0d1e7 | 944 | /* INSN is adding a CONST_INT to a REG. We search backwards looking for |
945 | another add immediate instruction with the same source and dest registers, | |
946 | and if we find one, we change INSN to an increment, and return 1. If | |
947 | no changes are made, we return 0. | |
948 | ||
949 | This changes | |
950 | (set (reg100) (plus reg1 offset1)) | |
951 | ... | |
952 | (set (reg100) (plus reg1 offset2)) | |
953 | to | |
954 | (set (reg100) (plus reg1 offset1)) | |
955 | ... | |
956 | (set (reg100) (plus reg100 offset2-offset1)) */ | |
957 | ||
958 | /* ??? What does this comment mean? */ | |
de132707 | 959 | /* cse disrupts preincrement / postdecrement sequences when it finds a |
57fc958f | 960 | hard register as ultimate source, like the frame pointer. */ |
41b0d1e7 | 961 | |
5b379086 | 962 | static int |
3f5be5f4 | 963 | fixup_match_2 (rtx insn, rtx dst, rtx src, rtx offset) |
57fc958f | 964 | { |
965 | rtx p, dst_death = 0; | |
a8587796 | 966 | int length, num_calls = 0, freq_calls = 0; |
57fc958f | 967 | |
968 | /* If SRC dies in INSN, we'd have to move the death note. This is | |
969 | considered to be very unlikely, so we just skip the optimization | |
970 | in this case. */ | |
971 | if (find_regno_note (insn, REG_DEAD, REGNO (src))) | |
972 | return 0; | |
973 | ||
974 | /* Scan backward to find the first instruction that sets DST. */ | |
975 | ||
976 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
977 | { | |
978 | rtx pset; | |
979 | ||
9ea31f2a | 980 | /* ??? We can't scan past the end of a basic block without updating |
b9ad0217 | 981 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
982 | if (perhaps_ends_bb_p (p)) | |
9ea31f2a | 983 | break; |
b9ad0217 | 984 | else if (! INSN_P (p)) |
2617fe26 | 985 | continue; |
57fc958f | 986 | |
9ea31f2a | 987 | if (find_regno_note (p, REG_DEAD, REGNO (dst))) |
988 | dst_death = p; | |
989 | if (! dst_death) | |
990 | length++; | |
57fc958f | 991 | |
992 | pset = single_set (p); | |
993 | if (pset && SET_DEST (pset) == dst | |
994 | && GET_CODE (SET_SRC (pset)) == PLUS | |
995 | && XEXP (SET_SRC (pset), 0) == src | |
996 | && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) | |
2617fe26 | 997 | { |
57fc958f | 998 | HOST_WIDE_INT newconst |
999 | = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); | |
66bb8168 | 1000 | rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); |
1001 | ||
1002 | if (add && validate_change (insn, &PATTERN (insn), add, 0)) | |
57fc958f | 1003 | { |
1004 | /* Remove the death note for DST from DST_DEATH. */ | |
1005 | if (dst_death) | |
1006 | { | |
1007 | remove_death (REGNO (dst), dst_death); | |
1008 | REG_LIVE_LENGTH (REGNO (dst)) += length; | |
1009 | REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; | |
a8587796 | 1010 | REG_FREQ_CALLS_CROSSED (REGNO (dst)) += freq_calls; |
57fc958f | 1011 | } |
1012 | ||
3f5be5f4 | 1013 | if (dump_file) |
1014 | fprintf (dump_file, | |
57fc958f | 1015 | "Fixed operand of insn %d.\n", |
1016 | INSN_UID (insn)); | |
1017 | ||
1018 | #ifdef AUTO_INC_DEC | |
1019 | for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1020 | { | |
6d7dc5b9 | 1021 | if (LABEL_P (p) |
1022 | || JUMP_P (p)) | |
57fc958f | 1023 | break; |
9204e736 | 1024 | if (! INSN_P (p)) |
d1b1832e | 1025 | continue; |
57fc958f | 1026 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1027 | { | |
1028 | if (try_auto_increment (p, insn, 0, dst, newconst, 0)) | |
1029 | return 1; | |
1030 | break; | |
1031 | } | |
1032 | } | |
1033 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1034 | { | |
6d7dc5b9 | 1035 | if (LABEL_P (p) |
1036 | || JUMP_P (p)) | |
57fc958f | 1037 | break; |
9204e736 | 1038 | if (! INSN_P (p)) |
d00c8ea9 | 1039 | continue; |
57fc958f | 1040 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1041 | { | |
1042 | try_auto_increment (p, insn, 0, dst, newconst, 1); | |
1043 | break; | |
1044 | } | |
1045 | } | |
1046 | #endif | |
1047 | return 1; | |
1048 | } | |
2617fe26 | 1049 | } |
57fc958f | 1050 | |
1051 | if (reg_set_p (dst, PATTERN (p))) | |
2617fe26 | 1052 | break; |
57fc958f | 1053 | |
1054 | /* If we have passed a call instruction, and the | |
1055 | pseudo-reg SRC is not already live across a call, | |
1056 | then don't perform the optimization. */ | |
1057 | /* reg_set_p is overly conservative for CALL_INSNS, thinks that all | |
1058 | hard regs are clobbered. Thus, we only use it for src for | |
1059 | non-call insns. */ | |
6d7dc5b9 | 1060 | if (CALL_P (p)) |
2617fe26 | 1061 | { |
57fc958f | 1062 | if (! dst_death) |
a8587796 | 1063 | { |
1064 | num_calls++; | |
1065 | freq_calls += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p)); | |
1066 | } | |
57fc958f | 1067 | |
2617fe26 | 1068 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) |
1069 | break; | |
57fc958f | 1070 | |
1071 | if (call_used_regs [REGNO (dst)] | |
1072 | || find_reg_fusage (p, CLOBBER, dst)) | |
1073 | break; | |
2617fe26 | 1074 | } |
57fc958f | 1075 | else if (reg_set_p (src, PATTERN (p))) |
2617fe26 | 1076 | break; |
3eb9a99d | 1077 | } |
57fc958f | 1078 | |
3eb9a99d | 1079 | return 0; |
1080 | } | |
3eb9a99d | 1081 | |
4187ae6d | 1082 | /* Main entry for the register move optimization. |
1083 | F is the first instruction. | |
1084 | NREGS is one plus the highest pseudo-reg number used in the instruction. | |
1085 | REGMOVE_DUMP_FILE is a stream for output of a trace of actions taken | |
1086 | (or 0 if none should be output). */ | |
1087 | ||
5327eac6 | 1088 | static void |
3f5be5f4 | 1089 | regmove_optimize (rtx f, int nregs) |
3eb9a99d | 1090 | { |
3eb9a99d | 1091 | rtx insn; |
57fc958f | 1092 | struct match match; |
3eb9a99d | 1093 | int pass; |
1b7b2f8f | 1094 | int i; |
2f08c02a | 1095 | rtx copy_src, copy_dst; |
57fc958f | 1096 | |
3cf1ab8f | 1097 | /* ??? Hack. Regmove doesn't examine the CFG, and gets mightily |
1098 | confused by non-call exceptions ending blocks. */ | |
1099 | if (flag_non_call_exceptions) | |
1100 | return; | |
1101 | ||
3072d30e | 1102 | df_note_add_problem (); |
1103 | df_analyze (); | |
1104 | ||
1105 | regstat_init_n_sets_and_refs (); | |
1106 | regstat_compute_ri (); | |
1107 | ||
49de5893 | 1108 | /* Find out where a potential flags register is live, and so that we |
de132707 | 1109 | can suppress some optimizations in those zones. */ |
49de5893 | 1110 | mark_flags_life_zones (discover_flags_reg ()); |
1111 | ||
4c36ffe6 | 1112 | regno_src_regno = XNEWVEC (int, nregs); |
f9f428c6 | 1113 | for (i = nregs; --i >= 0; ) |
1114 | regno_src_regno[i] = -1; | |
2f08c02a | 1115 | |
3eb9a99d | 1116 | /* A forward/backward pass. Replace output operands with input operands. */ |
1117 | ||
57fc958f | 1118 | for (pass = 0; pass <= 2; pass++) |
3eb9a99d | 1119 | { |
47dd2e78 | 1120 | /* We need fewer optimizations for IRA. */ |
1121 | if ((! flag_regmove || flag_ira) && pass >= flag_expensive_optimizations) | |
b9cf3f63 | 1122 | goto done; |
57fc958f | 1123 | |
3f5be5f4 | 1124 | if (dump_file) |
1125 | fprintf (dump_file, "Starting %s pass...\n", | |
3eb9a99d | 1126 | pass ? "backward" : "forward"); |
1127 | ||
1128 | for (insn = pass ? get_last_insn () : f; insn; | |
1129 | insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) | |
1130 | { | |
57fc958f | 1131 | rtx set; |
7f82be90 | 1132 | int op_no, match_no; |
57fc958f | 1133 | |
57fc958f | 1134 | set = single_set (insn); |
1135 | if (! set) | |
1136 | continue; | |
3eb9a99d | 1137 | |
57fc958f | 1138 | if (flag_expensive_optimizations && ! pass |
1139 | && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND | |
1140 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) | |
8ad4c111 | 1141 | && REG_P (XEXP (SET_SRC (set), 0)) |
1142 | && REG_P (SET_DEST (set))) | |
57fc958f | 1143 | optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); |
1144 | ||
1145 | if (flag_expensive_optimizations && ! pass | |
8ad4c111 | 1146 | && REG_P (SET_SRC (set)) |
1147 | && REG_P (SET_DEST (set))) | |
57fc958f | 1148 | { |
1149 | /* If this is a register-register copy where SRC is not dead, | |
1150 | see if we can optimize it. If this optimization succeeds, | |
1151 | it will become a copy where SRC is dead. */ | |
1152 | if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) | |
1153 | || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) | |
1154 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) | |
3eb9a99d | 1155 | { |
57fc958f | 1156 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
1157 | if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1158 | optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); | |
1159 | if (regno_src_regno[REGNO (SET_DEST (set))] < 0 | |
1160 | && SET_SRC (set) != SET_DEST (set)) | |
3eb9a99d | 1161 | { |
337d789b | 1162 | int srcregno = REGNO (SET_SRC (set)); |
57fc958f | 1163 | if (regno_src_regno[srcregno] >= 0) |
1164 | srcregno = regno_src_regno[srcregno]; | |
1165 | regno_src_regno[REGNO (SET_DEST (set))] = srcregno; | |
3eb9a99d | 1166 | } |
1167 | } | |
57fc958f | 1168 | } |
47dd2e78 | 1169 | |
1170 | /* All optimizations important for IRA have been done. */ | |
1171 | if (! flag_regmove || flag_ira) | |
2617fe26 | 1172 | continue; |
57fc958f | 1173 | |
ef5c3a57 | 1174 | if (! find_matches (insn, &match)) |
57fc958f | 1175 | continue; |
1176 | ||
1177 | /* Now scan through the operands looking for a source operand | |
1178 | which is supposed to match the destination operand. | |
1179 | Then scan forward for an instruction which uses the dest | |
1180 | operand. | |
1181 | If it dies there, then replace the dest in both operands with | |
1182 | the source operand. */ | |
1183 | ||
ed420a25 | 1184 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
57fc958f | 1185 | { |
07e64d6e | 1186 | rtx src, dst, src_subreg; |
57fc958f | 1187 | enum reg_class src_class, dst_class; |
1188 | ||
7f82be90 | 1189 | match_no = match.with[op_no]; |
57fc958f | 1190 | |
1191 | /* Nothing to do if the two operands aren't supposed to match. */ | |
7f82be90 | 1192 | if (match_no < 0) |
57fc958f | 1193 | continue; |
1194 | ||
ed420a25 | 1195 | src = recog_data.operand[op_no]; |
1196 | dst = recog_data.operand[match_no]; | |
57fc958f | 1197 | |
8ad4c111 | 1198 | if (!REG_P (src)) |
57fc958f | 1199 | continue; |
1200 | ||
1201 | src_subreg = src; | |
1202 | if (GET_CODE (dst) == SUBREG | |
1203 | && GET_MODE_SIZE (GET_MODE (dst)) | |
1204 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) | |
1205 | { | |
57fc958f | 1206 | dst = SUBREG_REG (dst); |
f92cbd91 | 1207 | src_subreg = lowpart_subreg (GET_MODE (dst), |
1208 | src, GET_MODE (src)); | |
1209 | if (!src_subreg) | |
1210 | continue; | |
57fc958f | 1211 | } |
8ad4c111 | 1212 | if (!REG_P (dst) |
57fc958f | 1213 | || REGNO (dst) < FIRST_PSEUDO_REGISTER) |
1214 | continue; | |
1215 | ||
1216 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) | |
1217 | { | |
7f82be90 | 1218 | if (match.commutative[op_no] < op_no) |
57fc958f | 1219 | regno_src_regno[REGNO (dst)] = REGNO (src); |
1220 | continue; | |
1221 | } | |
1222 | ||
1223 | if (REG_LIVE_LENGTH (REGNO (src)) < 0) | |
1224 | continue; | |
1225 | ||
7f82be90 | 1226 | /* op_no/src must be a read-only operand, and |
57fc958f | 1227 | match_operand/dst must be a write-only operand. */ |
7f82be90 | 1228 | if (match.use[op_no] != READ |
1229 | || match.use[match_no] != WRITE) | |
57fc958f | 1230 | continue; |
1231 | ||
7f82be90 | 1232 | if (match.early_clobber[match_no] |
40988080 | 1233 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
57fc958f | 1234 | continue; |
1235 | ||
1236 | /* Make sure match_operand is the destination. */ | |
ed420a25 | 1237 | if (recog_data.operand[match_no] != SET_DEST (set)) |
57fc958f | 1238 | continue; |
1239 | ||
aa40f561 | 1240 | /* If the operands already match, then there is nothing to do. */ |
ed420a25 | 1241 | if (operands_match_p (src, dst)) |
57fc958f | 1242 | continue; |
1243 | ||
ed420a25 | 1244 | /* But in the commutative case, we might find a better match. */ |
1245 | if (match.commutative[op_no] >= 0) | |
1246 | { | |
1247 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1248 | if (operands_match_p (comm, dst) | |
1249 | && (replacement_quality (comm) | |
1250 | >= replacement_quality (src))) | |
1251 | continue; | |
1252 | } | |
1253 | ||
57fc958f | 1254 | src_class = reg_preferred_class (REGNO (src)); |
1255 | dst_class = reg_preferred_class (REGNO (dst)); | |
1b7b2f8f | 1256 | if (! regclass_compatible_p (src_class, dst_class)) |
57fc958f | 1257 | continue; |
4f271297 | 1258 | |
e9378ef4 | 1259 | if (GET_MODE (src) != GET_MODE (dst)) |
1260 | continue; | |
1261 | ||
57fc958f | 1262 | if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, |
3f5be5f4 | 1263 | op_no, match_no)) |
57fc958f | 1264 | break; |
3eb9a99d | 1265 | } |
1266 | } | |
1267 | } | |
1268 | ||
1269 | /* A backward pass. Replace input operands with output operands. */ | |
1270 | ||
3f5be5f4 | 1271 | if (dump_file) |
1272 | fprintf (dump_file, "Starting backward pass...\n"); | |
3eb9a99d | 1273 | |
1274 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
1275 | { | |
9204e736 | 1276 | if (INSN_P (insn)) |
3eb9a99d | 1277 | { |
7f82be90 | 1278 | int op_no, match_no; |
2f08c02a | 1279 | int success = 0; |
7f82be90 | 1280 | |
ef5c3a57 | 1281 | if (! find_matches (insn, &match)) |
3eb9a99d | 1282 | continue; |
1283 | ||
3eb9a99d | 1284 | /* Now scan through the operands looking for a destination operand |
1285 | which is supposed to match a source operand. | |
1286 | Then scan backward for an instruction which sets the source | |
1287 | operand. If safe, then replace the source operand with the | |
1288 | dest operand in both instructions. */ | |
1289 | ||
2f08c02a | 1290 | copy_src = NULL_RTX; |
1291 | copy_dst = NULL_RTX; | |
ed420a25 | 1292 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
3eb9a99d | 1293 | { |
57fc958f | 1294 | rtx set, p, src, dst; |
1295 | rtx src_note, dst_note; | |
a8587796 | 1296 | int num_calls = 0, freq_calls = 0; |
57fc958f | 1297 | enum reg_class src_class, dst_class; |
1298 | int length; | |
3eb9a99d | 1299 | |
7f82be90 | 1300 | match_no = match.with[op_no]; |
3eb9a99d | 1301 | |
57fc958f | 1302 | /* Nothing to do if the two operands aren't supposed to match. */ |
7f82be90 | 1303 | if (match_no < 0) |
57fc958f | 1304 | continue; |
3eb9a99d | 1305 | |
ed420a25 | 1306 | dst = recog_data.operand[match_no]; |
1307 | src = recog_data.operand[op_no]; | |
3eb9a99d | 1308 | |
8ad4c111 | 1309 | if (!REG_P (src)) |
57fc958f | 1310 | continue; |
3eb9a99d | 1311 | |
8ad4c111 | 1312 | if (!REG_P (dst) |
57fc958f | 1313 | || REGNO (dst) < FIRST_PSEUDO_REGISTER |
4187ae6d | 1314 | || REG_LIVE_LENGTH (REGNO (dst)) < 0 |
23946132 | 1315 | || GET_MODE (src) != GET_MODE (dst)) |
57fc958f | 1316 | continue; |
3eb9a99d | 1317 | |
aa40f561 | 1318 | /* If the operands already match, then there is nothing to do. */ |
ed420a25 | 1319 | if (operands_match_p (src, dst)) |
57fc958f | 1320 | continue; |
3eb9a99d | 1321 | |
ed420a25 | 1322 | if (match.commutative[op_no] >= 0) |
1323 | { | |
1324 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1325 | if (operands_match_p (comm, dst)) | |
1326 | continue; | |
1327 | } | |
1328 | ||
57fc958f | 1329 | set = single_set (insn); |
1330 | if (! set) | |
1331 | continue; | |
3eb9a99d | 1332 | |
5eac2c25 | 1333 | /* Note that single_set ignores parts of a parallel set for |
1334 | which one of the destinations is REG_UNUSED. We can't | |
1335 | handle that here, since we can wind up rewriting things | |
1336 | such that a single register is set twice within a single | |
1337 | parallel. */ | |
1338 | if (reg_set_p (src, insn)) | |
1339 | continue; | |
1340 | ||
7f82be90 | 1341 | /* match_no/dst must be a write-only operand, and |
57fc958f | 1342 | operand_operand/src must be a read-only operand. */ |
7f82be90 | 1343 | if (match.use[op_no] != READ |
1344 | || match.use[match_no] != WRITE) | |
57fc958f | 1345 | continue; |
3eb9a99d | 1346 | |
7f82be90 | 1347 | if (match.early_clobber[match_no] |
40988080 | 1348 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
57fc958f | 1349 | continue; |
3eb9a99d | 1350 | |
7f82be90 | 1351 | /* Make sure match_no is the destination. */ |
ed420a25 | 1352 | if (recog_data.operand[match_no] != SET_DEST (set)) |
57fc958f | 1353 | continue; |
3eb9a99d | 1354 | |
57fc958f | 1355 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) |
1356 | { | |
1357 | if (GET_CODE (SET_SRC (set)) == PLUS | |
1358 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT | |
1359 | && XEXP (SET_SRC (set), 0) == src | |
1360 | && fixup_match_2 (insn, dst, src, | |
3f5be5f4 | 1361 | XEXP (SET_SRC (set), 1))) |
57fc958f | 1362 | break; |
1363 | continue; | |
1364 | } | |
1365 | src_class = reg_preferred_class (REGNO (src)); | |
1366 | dst_class = reg_preferred_class (REGNO (dst)); | |
33bb1b3f | 1367 | |
1368 | if (! (src_note = find_reg_note (insn, REG_DEAD, src))) | |
2f08c02a | 1369 | { |
33bb1b3f | 1370 | /* We used to force the copy here like in other cases, but |
1371 | it produces worse code, as it eliminates no copy | |
1372 | instructions and the copy emitted will be produced by | |
1373 | reload anyway. On patterns with multiple alternatives, | |
de132707 | 1374 | there may be better solution available. |
33bb1b3f | 1375 | |
1376 | In particular this change produced slower code for numeric | |
1377 | i387 programs. */ | |
1378 | ||
2f08c02a | 1379 | continue; |
1380 | } | |
3eb9a99d | 1381 | |
33bb1b3f | 1382 | if (! regclass_compatible_p (src_class, dst_class)) |
2f08c02a | 1383 | { |
1384 | if (!copy_src) | |
1385 | { | |
1386 | copy_src = src; | |
1387 | copy_dst = dst; | |
1388 | } | |
1389 | continue; | |
1390 | } | |
1391 | ||
33bb1b3f | 1392 | /* Can not modify an earlier insn to set dst if this insn |
1393 | uses an old value in the source. */ | |
1394 | if (reg_overlap_mentioned_p (dst, SET_SRC (set))) | |
2f08c02a | 1395 | { |
1396 | if (!copy_src) | |
1397 | { | |
1398 | copy_src = src; | |
1399 | copy_dst = dst; | |
1400 | } | |
1401 | continue; | |
1402 | } | |
3eb9a99d | 1403 | |
57fc958f | 1404 | /* If src is set once in a different basic block, |
1405 | and is set equal to a constant, then do not use | |
1406 | it for this optimization, as this would make it | |
1407 | no longer equivalent to a constant. */ | |
2f08c02a | 1408 | |
681f6fc5 | 1409 | if (reg_is_remote_constant_p (src, insn)) |
2f08c02a | 1410 | { |
1411 | if (!copy_src) | |
1412 | { | |
1413 | copy_src = src; | |
1414 | copy_dst = dst; | |
1415 | } | |
1416 | continue; | |
1417 | } | |
1418 | ||
1419 | ||
3f5be5f4 | 1420 | if (dump_file) |
1421 | fprintf (dump_file, | |
2f08c02a | 1422 | "Could fix operand %d of insn %d matching operand %d.\n", |
7f82be90 | 1423 | op_no, INSN_UID (insn), match_no); |
3eb9a99d | 1424 | |
57fc958f | 1425 | /* Scan backward to find the first instruction that uses |
1426 | the input operand. If the operand is set here, then | |
7f82be90 | 1427 | replace it in both instructions with match_no. */ |
57fc958f | 1428 | |
1429 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1430 | { | |
1431 | rtx pset; | |
1432 | ||
9ea31f2a | 1433 | /* ??? We can't scan past the end of a basic block without |
1434 | updating the register lifetime info | |
b9ad0217 | 1435 | (REG_DEAD/basic_block_live_at_start). */ |
1436 | if (perhaps_ends_bb_p (p)) | |
9ea31f2a | 1437 | break; |
b9ad0217 | 1438 | else if (! INSN_P (p)) |
57fc958f | 1439 | continue; |
3eb9a99d | 1440 | |
57fc958f | 1441 | length++; |
3eb9a99d | 1442 | |
57fc958f | 1443 | /* ??? See if all of SRC is set in P. This test is much |
1444 | more conservative than it needs to be. */ | |
1445 | pset = single_set (p); | |
1446 | if (pset && SET_DEST (pset) == src) | |
1447 | { | |
1448 | /* We use validate_replace_rtx, in case there | |
1449 | are multiple identical source operands. All of | |
1450 | them have to be changed at the same time. */ | |
1451 | if (validate_replace_rtx (src, dst, insn)) | |
3eb9a99d | 1452 | { |
57fc958f | 1453 | if (validate_change (p, &SET_DEST (pset), |
1454 | dst, 0)) | |
1455 | success = 1; | |
1456 | else | |
3eb9a99d | 1457 | { |
57fc958f | 1458 | /* Change all source operands back. |
1459 | This modifies the dst as a side-effect. */ | |
1460 | validate_replace_rtx (dst, src, insn); | |
1461 | /* Now make sure the dst is right. */ | |
1462 | validate_change (insn, | |
ed420a25 | 1463 | recog_data.operand_loc[match_no], |
57fc958f | 1464 | dst, 0); |
3eb9a99d | 1465 | } |
3eb9a99d | 1466 | } |
57fc958f | 1467 | break; |
1468 | } | |
1469 | ||
02f07e87 | 1470 | /* We can't make this change if SRC is read or |
1471 | partially written in P, since we are going to | |
1472 | eliminate SRC. We can't make this change | |
1473 | if DST is mentioned at all in P, | |
1474 | since we are going to change its value. */ | |
57fc958f | 1475 | if (reg_overlap_mentioned_p (src, PATTERN (p)) |
02f07e87 | 1476 | || reg_mentioned_p (dst, PATTERN (p))) |
57fc958f | 1477 | break; |
3eb9a99d | 1478 | |
57fc958f | 1479 | /* If we have passed a call instruction, and the |
1480 | pseudo-reg DST is not already live across a call, | |
1481 | then don't perform the optimization. */ | |
6d7dc5b9 | 1482 | if (CALL_P (p)) |
57fc958f | 1483 | { |
1484 | num_calls++; | |
a8587796 | 1485 | freq_calls += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p)); |
57fc958f | 1486 | |
1487 | if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) | |
3eb9a99d | 1488 | break; |
57fc958f | 1489 | } |
1490 | } | |
3eb9a99d | 1491 | |
57fc958f | 1492 | if (success) |
1493 | { | |
1494 | int dstno, srcno; | |
3eb9a99d | 1495 | |
57fc958f | 1496 | /* Remove the death note for SRC from INSN. */ |
1497 | remove_note (insn, src_note); | |
1498 | /* Move the death note for SRC to P if it is used | |
1499 | there. */ | |
1500 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1501 | { | |
1502 | XEXP (src_note, 1) = REG_NOTES (p); | |
1503 | REG_NOTES (p) = src_note; | |
3eb9a99d | 1504 | } |
57fc958f | 1505 | /* If there is a REG_DEAD note for DST on P, then remove |
1506 | it, because DST is now set there. */ | |
07e64d6e | 1507 | if ((dst_note = find_reg_note (p, REG_DEAD, dst))) |
57fc958f | 1508 | remove_note (p, dst_note); |
1509 | ||
1510 | dstno = REGNO (dst); | |
1511 | srcno = REGNO (src); | |
1512 | ||
3072d30e | 1513 | INC_REG_N_SETS (dstno, 1); |
1514 | INC_REG_N_SETS (srcno, -1); | |
3eb9a99d | 1515 | |
57fc958f | 1516 | REG_N_CALLS_CROSSED (dstno) += num_calls; |
1517 | REG_N_CALLS_CROSSED (srcno) -= num_calls; | |
a8587796 | 1518 | REG_FREQ_CALLS_CROSSED (dstno) += freq_calls; |
1519 | REG_FREQ_CALLS_CROSSED (srcno) -= freq_calls; | |
57fc958f | 1520 | |
1521 | REG_LIVE_LENGTH (dstno) += length; | |
1522 | if (REG_LIVE_LENGTH (srcno) >= 0) | |
3eb9a99d | 1523 | { |
57fc958f | 1524 | REG_LIVE_LENGTH (srcno) -= length; |
1525 | /* REG_LIVE_LENGTH is only an approximation after | |
1526 | combine if sched is not run, so make sure that we | |
1527 | still have a reasonable value. */ | |
1528 | if (REG_LIVE_LENGTH (srcno) < 2) | |
1529 | REG_LIVE_LENGTH (srcno) = 2; | |
1530 | } | |
3eb9a99d | 1531 | |
3f5be5f4 | 1532 | if (dump_file) |
1533 | fprintf (dump_file, | |
57fc958f | 1534 | "Fixed operand %d of insn %d matching operand %d.\n", |
7f82be90 | 1535 | op_no, INSN_UID (insn), match_no); |
3eb9a99d | 1536 | |
57fc958f | 1537 | break; |
3eb9a99d | 1538 | } |
1539 | } | |
2f08c02a | 1540 | |
1541 | /* If we weren't able to replace any of the alternatives, try an | |
de132707 | 1542 | alternative approach of copying the source to the destination. */ |
2f08c02a | 1543 | if (!success && copy_src != NULL_RTX) |
f9f428c6 | 1544 | copy_src_to_dest (insn, copy_src, copy_dst); |
3eb9a99d | 1545 | } |
1546 | } | |
3e056287 | 1547 | |
b9cf3f63 | 1548 | done: |
1549 | /* Clean up. */ | |
1550 | free (regno_src_regno); | |
681f6fc5 | 1551 | if (reg_set_in_bb) |
1552 | { | |
1553 | free (reg_set_in_bb); | |
1554 | reg_set_in_bb = NULL; | |
1555 | } | |
3072d30e | 1556 | regstat_free_n_sets_and_refs (); |
1557 | regstat_free_ri (); | |
3eb9a99d | 1558 | } |
1559 | ||
7f82be90 | 1560 | /* Returns nonzero if INSN's pattern has matching constraints for any operand. |
1561 | Returns 0 if INSN can't be recognized, or if the alternative can't be | |
1562 | determined. | |
41b0d1e7 | 1563 | |
1564 | Initialize the info in MATCHP based on the constraints. */ | |
57fc958f | 1565 | |
1566 | static int | |
3ad4992f | 1567 | find_matches (rtx insn, struct match *matchp) |
57fc958f | 1568 | { |
1569 | int likely_spilled[MAX_RECOG_OPERANDS]; | |
7f82be90 | 1570 | int op_no; |
57fc958f | 1571 | int any_matches = 0; |
1572 | ||
7f82be90 | 1573 | extract_insn (insn); |
1574 | if (! constrain_operands (0)) | |
1575 | return 0; | |
57fc958f | 1576 | |
1577 | /* Must initialize this before main loop, because the code for | |
1578 | the commutative case may set matches for operands other than | |
1579 | the current one. */ | |
ed420a25 | 1580 | for (op_no = recog_data.n_operands; --op_no >= 0; ) |
7f82be90 | 1581 | matchp->with[op_no] = matchp->commutative[op_no] = -1; |
57fc958f | 1582 | |
ed420a25 | 1583 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
57fc958f | 1584 | { |
a8482e91 | 1585 | const char *p; |
1586 | char c; | |
57fc958f | 1587 | int i = 0; |
1588 | ||
ed420a25 | 1589 | p = recog_data.constraints[op_no]; |
57fc958f | 1590 | |
7f82be90 | 1591 | likely_spilled[op_no] = 0; |
1592 | matchp->use[op_no] = READ; | |
1593 | matchp->early_clobber[op_no] = 0; | |
57fc958f | 1594 | if (*p == '=') |
7f82be90 | 1595 | matchp->use[op_no] = WRITE; |
57fc958f | 1596 | else if (*p == '+') |
7f82be90 | 1597 | matchp->use[op_no] = READWRITE; |
57fc958f | 1598 | |
1599 | for (;*p && i < which_alternative; p++) | |
1600 | if (*p == ',') | |
1601 | i++; | |
1602 | ||
48ea5577 | 1603 | while ((c = *p) != '\0' && c != ',') |
1604 | { | |
1605 | switch (c) | |
2c7f203c | 1606 | { |
48ea5577 | 1607 | case '=': |
1608 | break; | |
1609 | case '+': | |
1610 | break; | |
1611 | case '&': | |
1612 | matchp->early_clobber[op_no] = 1; | |
1613 | break; | |
1614 | case '%': | |
1615 | matchp->commutative[op_no] = op_no + 1; | |
1616 | matchp->commutative[op_no + 1] = op_no; | |
1617 | break; | |
1618 | ||
1619 | case '0': case '1': case '2': case '3': case '4': | |
1620 | case '5': case '6': case '7': case '8': case '9': | |
1621 | { | |
1622 | char *end; | |
1623 | unsigned long match_ul = strtoul (p, &end, 10); | |
1624 | int match = match_ul; | |
80fabb90 | 1625 | |
48ea5577 | 1626 | p = end; |
2c7f203c | 1627 | |
48ea5577 | 1628 | if (match < op_no && likely_spilled[match]) |
1629 | continue; | |
1630 | matchp->with[op_no] = match; | |
1631 | any_matches = 1; | |
1632 | if (matchp->commutative[op_no] >= 0) | |
1633 | matchp->with[matchp->commutative[op_no]] = match; | |
1634 | } | |
1635 | continue; | |
2c7f203c | 1636 | |
57fc958f | 1637 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': |
1638 | case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': | |
1639 | case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': | |
1640 | case 'C': case 'D': case 'W': case 'Y': case 'Z': | |
48ea5577 | 1641 | if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p) )) |
7f82be90 | 1642 | likely_spilled[op_no] = 1; |
57fc958f | 1643 | break; |
1644 | } | |
48ea5577 | 1645 | p += CONSTRAINT_LEN (c, p); |
1646 | } | |
57fc958f | 1647 | } |
7f82be90 | 1648 | return any_matches; |
57fc958f | 1649 | } |
1650 | ||
e99ff895 | 1651 | /* Try to replace all occurrences of DST_REG with SRC in LOC, that is |
1652 | assumed to be in INSN. */ | |
1653 | ||
1654 | static void | |
3ad4992f | 1655 | replace_in_call_usage (rtx *loc, unsigned int dst_reg, rtx src, rtx insn) |
e99ff895 | 1656 | { |
1657 | rtx x = *loc; | |
1658 | enum rtx_code code; | |
1659 | const char *fmt; | |
1660 | int i, j; | |
1661 | ||
1662 | if (! x) | |
1663 | return; | |
4f271297 | 1664 | |
e99ff895 | 1665 | code = GET_CODE (x); |
1666 | if (code == REG) | |
1667 | { | |
1668 | if (REGNO (x) != dst_reg) | |
1669 | return; | |
4f271297 | 1670 | |
e99ff895 | 1671 | validate_change (insn, loc, src, 1); |
1672 | ||
1673 | return; | |
1674 | } | |
4f271297 | 1675 | |
e99ff895 | 1676 | /* Process each of our operands recursively. */ |
1677 | fmt = GET_RTX_FORMAT (code); | |
1678 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
1679 | if (*fmt == 'e') | |
1680 | replace_in_call_usage (&XEXP (x, i), dst_reg, src, insn); | |
1681 | else if (*fmt == 'E') | |
1682 | for (j = 0; j < XVECLEN (x, i); j++) | |
1683 | replace_in_call_usage (& XVECEXP (x, i, j), dst_reg, src, insn); | |
1684 | } | |
1685 | ||
57fc958f | 1686 | /* Try to replace output operand DST in SET, with input operand SRC. SET is |
0f96ee0f | 1687 | the only set in INSN. INSN has just been recognized and constrained. |
57fc958f | 1688 | SRC is operand number OPERAND_NUMBER in INSN. |
1689 | DST is operand number MATCH_NUMBER in INSN. | |
1690 | If BACKWARD is nonzero, we have been called in a backward pass. | |
1691 | Return nonzero for success. */ | |
b9ad0217 | 1692 | |
57fc958f | 1693 | static int |
3ad4992f | 1694 | fixup_match_1 (rtx insn, rtx set, rtx src, rtx src_subreg, rtx dst, |
3f5be5f4 | 1695 | int backward, int operand_number, int match_number) |
57fc958f | 1696 | { |
1697 | rtx p; | |
1698 | rtx post_inc = 0, post_inc_set = 0, search_end = 0; | |
1699 | int success = 0; | |
d8d756b9 | 1700 | int num_calls = 0, freq_calls = 0, s_num_calls = 0, s_freq_calls = 0; |
57fc958f | 1701 | enum rtx_code code = NOTE; |
aec26802 | 1702 | HOST_WIDE_INT insn_const = 0, newconst = 0; |
57fc958f | 1703 | rtx overlap = 0; /* need to move insn ? */ |
ef2c4a29 | 1704 | rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note = NULL_RTX; |
acb0134e | 1705 | int length, s_length; |
57fc958f | 1706 | |
1707 | if (! src_note) | |
1708 | { | |
1709 | /* Look for (set (regX) (op regA constX)) | |
1710 | (set (regY) (op regA constY)) | |
1711 | and change that to | |
1712 | (set (regA) (op regA constX)). | |
1713 | (set (regY) (op regA constY-constX)). | |
1714 | This works for add and shift operations, if | |
1715 | regA is dead after or set by the second insn. */ | |
1716 | ||
1717 | code = GET_CODE (SET_SRC (set)); | |
1718 | if ((code == PLUS || code == LSHIFTRT | |
1719 | || code == ASHIFT || code == ASHIFTRT) | |
1720 | && XEXP (SET_SRC (set), 0) == src | |
1721 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
1722 | insn_const = INTVAL (XEXP (SET_SRC (set), 1)); | |
83969567 | 1723 | else if (! stable_and_no_regs_but_for_p (SET_SRC (set), src, dst)) |
57fc958f | 1724 | return 0; |
1725 | else | |
1726 | /* We might find a src_note while scanning. */ | |
1727 | code = NOTE; | |
1728 | } | |
1729 | ||
3f5be5f4 | 1730 | if (dump_file) |
1731 | fprintf (dump_file, | |
57fc958f | 1732 | "Could fix operand %d of insn %d matching operand %d.\n", |
1733 | operand_number, INSN_UID (insn), match_number); | |
1734 | ||
1735 | /* If SRC is equivalent to a constant set in a different basic block, | |
1736 | then do not use it for this optimization. We want the equivalence | |
1737 | so that if we have to reload this register, we can reload the | |
1738 | constant, rather than extending the lifespan of the register. */ | |
681f6fc5 | 1739 | if (reg_is_remote_constant_p (src, insn)) |
57fc958f | 1740 | return 0; |
1741 | ||
1742 | /* Scan forward to find the next instruction that | |
1743 | uses the output operand. If the operand dies here, | |
1744 | then replace it in both instructions with | |
1745 | operand_number. */ | |
1746 | ||
1747 | for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1748 | { | |
6d7dc5b9 | 1749 | if (CALL_P (p)) |
e99ff895 | 1750 | replace_in_call_usage (& CALL_INSN_FUNCTION_USAGE (p), |
1751 | REGNO (dst), src, p); | |
4f271297 | 1752 | |
9ea31f2a | 1753 | /* ??? We can't scan past the end of a basic block without updating |
b9ad0217 | 1754 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
1755 | if (perhaps_ends_bb_p (p)) | |
9ea31f2a | 1756 | break; |
b9ad0217 | 1757 | else if (! INSN_P (p)) |
57fc958f | 1758 | continue; |
1759 | ||
1760 | length++; | |
1761 | if (src_note) | |
1762 | s_length++; | |
1763 | ||
1764 | if (reg_set_p (src, p) || reg_set_p (dst, p) | |
1765 | || (GET_CODE (PATTERN (p)) == USE | |
1766 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
1767 | break; | |
1768 | ||
1769 | /* See if all of DST dies in P. This test is | |
1770 | slightly more conservative than it needs to be. */ | |
1771 | if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) | |
1772 | && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) | |
1773 | { | |
7287562d | 1774 | /* If we would be moving INSN, check that we won't move it |
1775 | into the shadow of a live a live flags register. */ | |
1776 | /* ??? We only try to move it in front of P, although | |
1777 | we could move it anywhere between OVERLAP and P. */ | |
1778 | if (overlap && GET_MODE (PREV_INSN (p)) != VOIDmode) | |
1779 | break; | |
1780 | ||
57fc958f | 1781 | if (! src_note) |
1782 | { | |
1783 | rtx q; | |
ef2c4a29 | 1784 | rtx set2 = NULL_RTX; |
57fc958f | 1785 | |
1786 | /* If an optimization is done, the value of SRC while P | |
1787 | is executed will be changed. Check that this is OK. */ | |
1788 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1789 | break; | |
1790 | for (q = p; q; q = NEXT_INSN (q)) | |
1791 | { | |
9ea31f2a | 1792 | /* ??? We can't scan past the end of a basic block without |
1793 | updating the register lifetime info | |
b9ad0217 | 1794 | (REG_DEAD/basic_block_live_at_start). */ |
1795 | if (perhaps_ends_bb_p (q)) | |
9ea31f2a | 1796 | { |
1797 | q = 0; | |
1798 | break; | |
1799 | } | |
b9ad0217 | 1800 | else if (! INSN_P (q)) |
57fc958f | 1801 | continue; |
b9ad0217 | 1802 | else if (reg_overlap_mentioned_p (src, PATTERN (q)) |
1803 | || reg_set_p (src, q)) | |
57fc958f | 1804 | break; |
1805 | } | |
1806 | if (q) | |
1807 | set2 = single_set (q); | |
1808 | if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code | |
1809 | || XEXP (SET_SRC (set2), 0) != src | |
1810 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT | |
1811 | || (SET_DEST (set2) != src | |
1812 | && ! find_reg_note (q, REG_DEAD, src))) | |
1813 | { | |
1814 | /* If this is a PLUS, we can still save a register by doing | |
1815 | src += insn_const; | |
1816 | P; | |
1817 | src -= insn_const; . | |
1818 | This also gives opportunities for subsequent | |
1819 | optimizations in the backward pass, so do it there. */ | |
1820 | if (code == PLUS && backward | |
1b7b2f8f | 1821 | /* Don't do this if we can likely tie DST to SET_DEST |
1822 | of P later; we can't do this tying here if we got a | |
1823 | hard register. */ | |
1824 | && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) | |
1825 | && single_set (p) | |
8ad4c111 | 1826 | && REG_P (SET_DEST (single_set (p))) |
1b7b2f8f | 1827 | && (REGNO (SET_DEST (single_set (p))) |
1828 | < FIRST_PSEUDO_REGISTER)) | |
49de5893 | 1829 | /* We may only emit an insn directly after P if we |
1830 | are not in the shadow of a live flags register. */ | |
1831 | && GET_MODE (p) == VOIDmode) | |
57fc958f | 1832 | { |
1833 | search_end = q; | |
1834 | q = insn; | |
1835 | set2 = set; | |
1836 | newconst = -insn_const; | |
1837 | code = MINUS; | |
1838 | } | |
1839 | else | |
1840 | break; | |
1841 | } | |
1842 | else | |
1843 | { | |
1844 | newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; | |
1845 | /* Reject out of range shifts. */ | |
1846 | if (code != PLUS | |
1847 | && (newconst < 0 | |
b9ad0217 | 1848 | || ((unsigned HOST_WIDE_INT) newconst |
1849 | >= (GET_MODE_BITSIZE (GET_MODE | |
1850 | (SET_SRC (set2))))))) | |
57fc958f | 1851 | break; |
1852 | if (code == PLUS) | |
1853 | { | |
1854 | post_inc = q; | |
1855 | if (SET_DEST (set2) != src) | |
1856 | post_inc_set = set2; | |
1857 | } | |
1858 | } | |
1859 | /* We use 1 as last argument to validate_change so that all | |
1860 | changes are accepted or rejected together by apply_change_group | |
1861 | when it is called by validate_replace_rtx . */ | |
1862 | validate_change (q, &XEXP (SET_SRC (set2), 1), | |
1863 | GEN_INT (newconst), 1); | |
1864 | } | |
ed420a25 | 1865 | validate_change (insn, recog_data.operand_loc[match_number], src, 1); |
57fc958f | 1866 | if (validate_replace_rtx (dst, src_subreg, p)) |
1867 | success = 1; | |
1868 | break; | |
1869 | } | |
1870 | ||
1871 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1872 | break; | |
1873 | if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1874 | { | |
7287562d | 1875 | /* INSN was already checked to be movable wrt. the registers that it |
1876 | sets / uses when we found no REG_DEAD note for src on it, but it | |
1877 | still might clobber the flags register. We'll have to check that | |
1878 | we won't insert it into the shadow of a live flags register when | |
1879 | we finally know where we are to move it. */ | |
57fc958f | 1880 | overlap = p; |
1881 | src_note = find_reg_note (p, REG_DEAD, src); | |
1882 | } | |
1883 | ||
1884 | /* If we have passed a call instruction, and the pseudo-reg SRC is not | |
1885 | already live across a call, then don't perform the optimization. */ | |
6d7dc5b9 | 1886 | if (CALL_P (p)) |
57fc958f | 1887 | { |
1888 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1889 | break; | |
1890 | ||
1891 | num_calls++; | |
d8d756b9 | 1892 | freq_calls += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p)); |
57fc958f | 1893 | |
1894 | if (src_note) | |
d8d756b9 | 1895 | { |
1896 | s_num_calls++; | |
1897 | s_freq_calls += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p)); | |
1898 | } | |
57fc958f | 1899 | } |
1900 | } | |
1901 | ||
1902 | if (! success) | |
1903 | return 0; | |
1904 | ||
57fc958f | 1905 | /* Remove the death note for DST from P. */ |
1906 | remove_note (p, dst_note); | |
1907 | if (code == MINUS) | |
1908 | { | |
1909 | post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); | |
e4e498cf | 1910 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1911 | && search_end | |
57fc958f | 1912 | && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) |
1913 | post_inc = 0; | |
57fc958f | 1914 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); |
3072d30e | 1915 | INC_REG_N_SETS (REGNO (src), 1); |
57fc958f | 1916 | REG_LIVE_LENGTH (REGNO (src))++; |
1917 | } | |
1918 | if (overlap) | |
1919 | { | |
1920 | /* The lifetime of src and dest overlap, | |
1921 | but we can change this by moving insn. */ | |
1922 | rtx pat = PATTERN (insn); | |
1923 | if (src_note) | |
1924 | remove_note (overlap, src_note); | |
ef8b109f | 1925 | if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1926 | && code == PLUS | |
57fc958f | 1927 | && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) |
1928 | insn = overlap; | |
1929 | else | |
57fc958f | 1930 | { |
1931 | rtx notes = REG_NOTES (insn); | |
1932 | ||
f2aa2401 | 1933 | p = emit_insn_after_setloc (pat, PREV_INSN (p), INSN_LOCATOR (insn)); |
b36d64df | 1934 | delete_insn (insn); |
f2aa2401 | 1935 | REG_NOTES (p) = notes; |
3072d30e | 1936 | df_notes_rescan (p); |
57fc958f | 1937 | } |
1938 | } | |
1939 | /* Sometimes we'd generate src = const; src += n; | |
1940 | if so, replace the instruction that set src | |
1941 | in the first place. */ | |
1942 | ||
1943 | if (! overlap && (code == PLUS || code == MINUS)) | |
1944 | { | |
1945 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
ef2c4a29 | 1946 | rtx q, set2 = NULL_RTX; |
d8d756b9 | 1947 | int num_calls2 = 0, s_length2 = 0, freq_calls2 = 0; |
57fc958f | 1948 | |
1949 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1950 | { | |
337d789b | 1951 | for (q = PREV_INSN (insn); q; q = PREV_INSN (q)) |
57fc958f | 1952 | { |
9ea31f2a | 1953 | /* ??? We can't scan past the end of a basic block without |
1954 | updating the register lifetime info | |
b9ad0217 | 1955 | (REG_DEAD/basic_block_live_at_start). */ |
1956 | if (perhaps_ends_bb_p (q)) | |
9ea31f2a | 1957 | { |
1958 | q = 0; | |
1959 | break; | |
1960 | } | |
b9ad0217 | 1961 | else if (! INSN_P (q)) |
57fc958f | 1962 | continue; |
b9ad0217 | 1963 | |
57fc958f | 1964 | s_length2++; |
1965 | if (reg_set_p (src, q)) | |
1966 | { | |
1967 | set2 = single_set (q); | |
1968 | break; | |
1969 | } | |
1970 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
1971 | { | |
1972 | q = 0; | |
1973 | break; | |
1974 | } | |
6d7dc5b9 | 1975 | if (CALL_P (p)) |
d8d756b9 | 1976 | { |
1977 | num_calls2++; | |
1978 | freq_calls2 += REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p)); | |
1979 | } | |
57fc958f | 1980 | } |
1981 | if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) | |
1982 | && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) | |
1983 | { | |
b36d64df | 1984 | delete_insn (q); |
3072d30e | 1985 | INC_REG_N_SETS (REGNO (src), -1); |
57fc958f | 1986 | REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; |
d8d756b9 | 1987 | REG_FREQ_CALLS_CROSSED (REGNO (src)) -= freq_calls2; |
57fc958f | 1988 | REG_LIVE_LENGTH (REGNO (src)) -= s_length2; |
1989 | insn_const = 0; | |
1990 | } | |
1991 | } | |
1992 | } | |
ef3ec561 | 1993 | |
5ad6f9ab | 1994 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
e4e498cf | 1995 | && (code == PLUS || code == MINUS) && insn_const |
57fc958f | 1996 | && try_auto_increment (p, insn, 0, src, insn_const, 1)) |
1997 | insn = p; | |
e4e498cf | 1998 | else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1999 | && post_inc | |
57fc958f | 2000 | && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) |
2001 | post_inc = 0; | |
57fc958f | 2002 | /* If post_inc still prevails, try to find an |
2003 | insn where it can be used as a pre-in/decrement. | |
2004 | If code is MINUS, this was already tried. */ | |
2005 | if (post_inc && code == PLUS | |
2006 | /* Check that newconst is likely to be usable | |
2007 | in a pre-in/decrement before starting the search. */ | |
e4e498cf | 2008 | && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) |
2009 | || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) | |
2010 | && exact_log2 (newconst)) | |
57fc958f | 2011 | { |
2012 | rtx q, inc_dest; | |
2013 | ||
2014 | inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; | |
7d27e4c9 | 2015 | for (q = post_inc; (q = NEXT_INSN (q)); ) |
57fc958f | 2016 | { |
9ea31f2a | 2017 | /* ??? We can't scan past the end of a basic block without updating |
b9ad0217 | 2018 | the register lifetime info |
aa40f561 | 2019 | (REG_DEAD/basic_block_live_at_start). */ |
b9ad0217 | 2020 | if (perhaps_ends_bb_p (q)) |
9ea31f2a | 2021 | break; |
b9ad0217 | 2022 | else if (! INSN_P (q)) |
57fc958f | 2023 | continue; |
b9ad0217 | 2024 | else if (src != inc_dest |
2025 | && (reg_overlap_mentioned_p (src, PATTERN (q)) | |
2026 | || reg_set_p (src, q))) | |
57fc958f | 2027 | break; |
b9ad0217 | 2028 | else if (reg_set_p (inc_dest, q)) |
57fc958f | 2029 | break; |
b9ad0217 | 2030 | else if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) |
57fc958f | 2031 | { |
2032 | try_auto_increment (q, post_inc, | |
2033 | post_inc_set, inc_dest, newconst, 1); | |
2034 | break; | |
2035 | } | |
2036 | } | |
2037 | } | |
b9ad0217 | 2038 | |
57fc958f | 2039 | /* Move the death note for DST to INSN if it is used |
2040 | there. */ | |
2041 | if (reg_overlap_mentioned_p (dst, PATTERN (insn))) | |
2042 | { | |
2043 | XEXP (dst_note, 1) = REG_NOTES (insn); | |
2044 | REG_NOTES (insn) = dst_note; | |
2045 | } | |
2046 | ||
2047 | if (src_note) | |
2048 | { | |
2049 | /* Move the death note for SRC from INSN to P. */ | |
2050 | if (! overlap) | |
2051 | remove_note (insn, src_note); | |
2052 | XEXP (src_note, 1) = REG_NOTES (p); | |
2053 | REG_NOTES (p) = src_note; | |
2054 | ||
2055 | REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; | |
d8d756b9 | 2056 | REG_FREQ_CALLS_CROSSED (REGNO (src)) += s_freq_calls; |
57fc958f | 2057 | } |
2058 | ||
3072d30e | 2059 | INC_REG_N_SETS (REGNO (src), 1); |
2060 | INC_REG_N_SETS (REGNO (dst), -1); | |
57fc958f | 2061 | |
2062 | REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; | |
d8d756b9 | 2063 | REG_FREQ_CALLS_CROSSED (REGNO (dst)) -= freq_calls; |
57fc958f | 2064 | |
2065 | REG_LIVE_LENGTH (REGNO (src)) += s_length; | |
2066 | if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) | |
2067 | { | |
2068 | REG_LIVE_LENGTH (REGNO (dst)) -= length; | |
2069 | /* REG_LIVE_LENGTH is only an approximation after | |
2070 | combine if sched is not run, so make sure that we | |
2071 | still have a reasonable value. */ | |
2072 | if (REG_LIVE_LENGTH (REGNO (dst)) < 2) | |
2073 | REG_LIVE_LENGTH (REGNO (dst)) = 2; | |
2074 | } | |
3f5be5f4 | 2075 | if (dump_file) |
2076 | fprintf (dump_file, | |
57fc958f | 2077 | "Fixed operand %d of insn %d matching operand %d.\n", |
2078 | operand_number, INSN_UID (insn), match_number); | |
2079 | return 1; | |
2080 | } | |
2081 | ||
2082 | ||
139c3f48 | 2083 | /* Return nonzero if X is stable and mentions no registers but for |
83969567 | 2084 | mentioning SRC or mentioning / changing DST . If in doubt, presume |
2085 | it is unstable. | |
2086 | The rationale is that we want to check if we can move an insn easily | |
b04fab2a | 2087 | while just paying attention to SRC and DST. */ |
3eb9a99d | 2088 | static int |
3ad4992f | 2089 | stable_and_no_regs_but_for_p (rtx x, rtx src, rtx dst) |
3eb9a99d | 2090 | { |
2091 | RTX_CODE code = GET_CODE (x); | |
2092 | switch (GET_RTX_CLASS (code)) | |
2093 | { | |
6720e96c | 2094 | case RTX_UNARY: |
2095 | case RTX_BIN_ARITH: | |
2096 | case RTX_COMM_ARITH: | |
2097 | case RTX_COMPARE: | |
2098 | case RTX_COMM_COMPARE: | |
2099 | case RTX_TERNARY: | |
2100 | case RTX_BITFIELD_OPS: | |
3eb9a99d | 2101 | { |
2102 | int i; | |
d2ca078f | 2103 | const char *fmt = GET_RTX_FORMAT (code); |
3eb9a99d | 2104 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
83969567 | 2105 | if (fmt[i] == 'e' |
2106 | && ! stable_and_no_regs_but_for_p (XEXP (x, i), src, dst)) | |
3eb9a99d | 2107 | return 0; |
2108 | return 1; | |
2109 | } | |
6720e96c | 2110 | case RTX_OBJ: |
83969567 | 2111 | if (code == REG) |
2112 | return x == src || x == dst; | |
2113 | /* If this is a MEM, look inside - there might be a register hidden in | |
2114 | the address of an unchanging MEM. */ | |
2115 | if (code == MEM | |
2116 | && ! stable_and_no_regs_but_for_p (XEXP (x, 0), src, dst)) | |
2117 | return 0; | |
b4b174c3 | 2118 | /* Fall through. */ |
3eb9a99d | 2119 | default: |
2120 | return ! rtx_unstable_p (x); | |
2121 | } | |
2122 | } | |
f23d70c6 | 2123 | \f |
f23d70c6 | 2124 | |
77fce4cd | 2125 | static bool |
2126 | gate_handle_regmove (void) | |
2127 | { | |
2128 | return (optimize > 0 && flag_regmove); | |
2129 | } | |
2130 | ||
77fce4cd | 2131 | /* Register allocation pre-pass, to reduce number of moves necessary |
2132 | for two-address machines. */ | |
2a1990e9 | 2133 | static unsigned int |
77fce4cd | 2134 | rest_of_handle_regmove (void) |
2135 | { | |
3f5be5f4 | 2136 | regmove_optimize (get_insns (), max_reg_num ()); |
2a1990e9 | 2137 | return 0; |
77fce4cd | 2138 | } |
2139 | ||
20099e35 | 2140 | struct rtl_opt_pass pass_regmove = |
77fce4cd | 2141 | { |
20099e35 | 2142 | { |
2143 | RTL_PASS, | |
77fce4cd | 2144 | "regmove", /* name */ |
2145 | gate_handle_regmove, /* gate */ | |
2146 | rest_of_handle_regmove, /* execute */ | |
2147 | NULL, /* sub */ | |
2148 | NULL, /* next */ | |
2149 | 0, /* static_pass_number */ | |
2150 | TV_REGMOVE, /* tv_id */ | |
2151 | 0, /* properties_required */ | |
2152 | 0, /* properties_provided */ | |
2153 | 0, /* properties_destroyed */ | |
2154 | 0, /* todo_flags_start */ | |
0806b508 | 2155 | TODO_df_finish | TODO_verify_rtl_sharing | |
77fce4cd | 2156 | TODO_dump_func | |
20099e35 | 2157 | TODO_ggc_collect /* todo_flags_finish */ |
2158 | } | |
77fce4cd | 2159 | }; |
2160 |