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1af1688b RK |
1 | /* This file contains the definitions and documentation for the |
2 | Register Transfer Expressions (rtx's) that make up the | |
3 | Register Transfer Language (rtl) used in the Back End of the GNU compiler. | |
711d8c91 | 4 | Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004 |
c5c76735 | 5 | Free Software Foundation, Inc. |
1af1688b | 6 | |
1322177d | 7 | This file is part of GCC. |
1af1688b | 8 | |
1322177d LB |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 2, or (at your option) any later | |
12 | version. | |
1af1688b | 13 | |
1322177d LB |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
1af1688b RK |
18 | |
19 | You should have received a copy of the GNU General Public License | |
1322177d LB |
20 | along with GCC; see the file COPYING. If not, write to the Free |
21 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | 02111-1307, USA. */ | |
1af1688b RK |
23 | |
24 | ||
25 | /* Expression definitions and descriptions for all targets are in this file. | |
26 | Some will not be used for some targets. | |
27 | ||
28 | The fields in the cpp macro call "DEF_RTL_EXPR()" | |
29 | are used to create declarations in the C source of the compiler. | |
30 | ||
31 | The fields are: | |
32 | ||
33 | 1. The internal name of the rtx used in the C source. | |
34 | It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". | |
35 | By convention these are in UPPER_CASE. | |
36 | ||
37 | 2. The name of the rtx in the external ASCII format read by | |
38 | read_rtx(), and printed by print_rtx(). | |
39 | These names are stored in rtx_name[]. | |
40 | By convention these are the internal (field 1) names in lower_case. | |
41 | ||
e1de1560 | 42 | 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. |
1af1688b RK |
43 | These formats are stored in rtx_format[]. |
44 | The meaning of the formats is documented in front of this array in rtl.c | |
45 | ||
46 | 4. The class of the rtx. These are stored in rtx_class and are accessed | |
47 | via the GET_RTX_CLASS macro. They are defined as follows: | |
48 | ||
ec8e098d PB |
49 | RTX_CONST_OBJ |
50 | an rtx code that can be used to represent a constant object | |
51 | (e.g, CONST_INT) | |
52 | RTX_OBJ | |
53 | an rtx code that can be used to represent an object (e.g, REG, MEM) | |
54 | RTX_COMPARE | |
55 | an rtx code for a comparison (e.g, LT, GT) | |
56 | RTX_COMM_COMPARE | |
57 | an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) | |
58 | RTX_UNARY | |
59 | an rtx code for a unary arithmetic expression (e.g, NEG, NOT) | |
60 | RTX_COMM_ARITH | |
61 | an rtx code for a commutative binary operation (e.g,, PLUS, MULT) | |
62 | RTX_TERNARY | |
63 | an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) | |
64 | RTX_BIN_ARITH | |
65 | an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) | |
66 | RTX_BITFIELD_OPS | |
67 | an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) | |
68 | RTX_INSN | |
69 | an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) | |
70 | RTX_MATCH | |
71 | an rtx code for something that matches in insns (e.g, MATCH_DUP) | |
72 | RTX_AUTOINC | |
73 | an rtx code for autoincrement addressing modes (e.g. POST_DEC) | |
74 | RTX_EXTRA | |
75 | everything else | |
1af1688b RK |
76 | |
77 | */ | |
78 | ||
79 | /* --------------------------------------------------------------------- | |
80 | Expressions (and "meta" expressions) used for structuring the | |
81 | rtl representation of a program. | |
82 | --------------------------------------------------------------------- */ | |
83 | ||
84 | /* an expression code name unknown to the reader */ | |
ec8e098d | 85 | DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) |
1af1688b RK |
86 | |
87 | /* (NIL) is used by rtl reader and printer to represent a null pointer. */ | |
88 | ||
ec8e098d | 89 | DEF_RTL_EXPR(NIL, "nil", "*", RTX_EXTRA) |
1af1688b | 90 | |
04d8aa70 AM |
91 | |
92 | /* include a file */ | |
93 | ||
ec8e098d | 94 | DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA) |
04d8aa70 | 95 | |
1af1688b RK |
96 | /* --------------------------------------------------------------------- |
97 | Expressions used in constructing lists. | |
98 | --------------------------------------------------------------------- */ | |
99 | ||
100 | /* a linked list of expressions */ | |
ec8e098d | 101 | DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) |
1af1688b RK |
102 | |
103 | /* a linked list of instructions. | |
104 | The insns are represented in print by their uids. */ | |
ec8e098d | 105 | DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) |
1af1688b RK |
106 | |
107 | /* ---------------------------------------------------------------------- | |
6dc42e49 | 108 | Expression types for machine descriptions. |
1af1688b RK |
109 | These do not appear in actual rtl code in the compiler. |
110 | ---------------------------------------------------------------------- */ | |
111 | ||
112 | /* Appears only in machine descriptions. | |
113 | Means use the function named by the second arg (the string) | |
114 | as a predicate; if matched, store the structure that was matched | |
115 | in the operand table at index specified by the first arg (the integer). | |
116 | If the second arg is the null string, the structure is just stored. | |
117 | ||
118 | A third string argument indicates to the register allocator restrictions | |
119 | on where the operand can be allocated. | |
120 | ||
121 | If the target needs no restriction on any instruction this field should | |
122 | be the null string. | |
123 | ||
124 | The string is prepended by: | |
125 | '=' to indicate the operand is only written to. | |
126 | '+' to indicate the operand is both read and written to. | |
127 | ||
956d6950 | 128 | Each character in the string represents an allocable class for an operand. |
1af1688b RK |
129 | 'g' indicates the operand can be any valid class. |
130 | 'i' indicates the operand can be immediate (in the instruction) data. | |
131 | 'r' indicates the operand can be in a register. | |
132 | 'm' indicates the operand can be in memory. | |
133 | 'o' a subset of the 'm' class. Those memory addressing modes that | |
134 | can be offset at compile time (have a constant added to them). | |
135 | ||
136 | Other characters indicate target dependent operand classes and | |
137 | are described in each target's machine description. | |
138 | ||
139 | For instructions with more than one operand, sets of classes can be | |
140 | separated by a comma to indicate the appropriate multi-operand constraints. | |
141 | There must be a 1 to 1 correspondence between these sets of classes in | |
142 | all operands for an instruction. | |
143 | */ | |
ec8e098d | 144 | DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) |
1af1688b RK |
145 | |
146 | /* Appears only in machine descriptions. | |
147 | Means match a SCRATCH or a register. When used to generate rtl, a | |
148 | SCRATCH is generated. As for MATCH_OPERAND, the mode specifies | |
149 | the desired mode and the first argument is the operand number. | |
150 | The second argument is the constraint. */ | |
ec8e098d | 151 | DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) |
1af1688b RK |
152 | |
153 | /* Appears only in machine descriptions. | |
154 | Means match only something equal to what is stored in the operand table | |
155 | at the index specified by the argument. */ | |
ec8e098d | 156 | DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) |
1af1688b RK |
157 | |
158 | /* Appears only in machine descriptions. | |
159 | Means apply a predicate, AND match recursively the operands of the rtx. | |
160 | Operand 0 is the operand-number, as in match_operand. | |
161 | Operand 1 is a predicate to apply (as a string, a function name). | |
162 | Operand 2 is a vector of expressions, each of which must match | |
163 | one subexpression of the rtx this construct is matching. */ | |
ec8e098d | 164 | DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) |
1af1688b RK |
165 | |
166 | /* Appears only in machine descriptions. | |
167 | Means to match a PARALLEL of arbitrary length. The predicate is applied | |
168 | to the PARALLEL and the initial expressions in the PARALLEL are matched. | |
169 | Operand 0 is the operand-number, as in match_operand. | |
170 | Operand 1 is a predicate to apply to the PARALLEL. | |
171 | Operand 2 is a vector of expressions, each of which must match the | |
172 | corresponding element in the PARALLEL. */ | |
ec8e098d | 173 | DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) |
1af1688b RK |
174 | |
175 | /* Appears only in machine descriptions. | |
176 | Means match only something equal to what is stored in the operand table | |
177 | at the index specified by the argument. For MATCH_OPERATOR. */ | |
ec8e098d | 178 | DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) |
1af1688b | 179 | |
ae3c61fa RK |
180 | /* Appears only in machine descriptions. |
181 | Means match only something equal to what is stored in the operand table | |
182 | at the index specified by the argument. For MATCH_PARALLEL. */ | |
ec8e098d | 183 | DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) |
ae3c61fa | 184 | |
1af1688b RK |
185 | /* Appears only in machine descriptions. |
186 | Defines the pattern for one kind of instruction. | |
187 | Operand: | |
188 | 0: names this instruction. | |
189 | If the name is the null string, the instruction is in the | |
190 | machine description just to be recognized, and will never be emitted by | |
191 | the tree to rtl expander. | |
192 | 1: is the pattern. | |
193 | 2: is a string which is a C expression | |
194 | giving an additional condition for recognizing this pattern. | |
195 | A null string means no extra condition. | |
196 | 3: is the action to execute if this pattern is matched. | |
197 | If this assembler code template starts with a * then it is a fragment of | |
198 | C code to run to decide on a template to use. Otherwise, it is the | |
199 | template to use. | |
200 | 4: optionally, a vector of attributes for this insn. | |
201 | */ | |
ec8e098d | 202 | DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) |
1af1688b RK |
203 | |
204 | /* Definition of a peephole optimization. | |
205 | 1st operand: vector of insn patterns to match | |
206 | 2nd operand: C expression that must be true | |
207 | 3rd operand: template or C code to produce assembler output. | |
208 | 4: optionally, a vector of attributes for this insn. | |
209 | */ | |
ec8e098d | 210 | DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) |
1af1688b RK |
211 | |
212 | /* Definition of a split operation. | |
213 | 1st operand: insn pattern to match | |
214 | 2nd operand: C expression that must be true | |
215 | 3rd operand: vector of insn patterns to place into a SEQUENCE | |
216 | 4th operand: optionally, some C code to execute before generating the | |
217 | insns. This might, for example, create some RTX's and store them in | |
37bef197 TC |
218 | elements of `recog_data.operand' for use by the vector of |
219 | insn-patterns. | |
991b6592 | 220 | (`operands' is an alias here for `recog_data.operand'). */ |
ec8e098d | 221 | DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) |
1af1688b | 222 | |
c88c0d42 CP |
223 | /* Definition of an insn and associated split. |
224 | This is the concatenation, with a few modifications, of a define_insn | |
225 | and a define_split which share the same pattern. | |
226 | Operand: | |
227 | 0: names this instruction. | |
228 | If the name is the null string, the instruction is in the | |
229 | machine description just to be recognized, and will never be emitted by | |
230 | the tree to rtl expander. | |
231 | 1: is the pattern. | |
232 | 2: is a string which is a C expression | |
233 | giving an additional condition for recognizing this pattern. | |
234 | A null string means no extra condition. | |
235 | 3: is the action to execute if this pattern is matched. | |
236 | If this assembler code template starts with a * then it is a fragment of | |
237 | C code to run to decide on a template to use. Otherwise, it is the | |
238 | template to use. | |
239 | 4: C expression that must be true for split. This may start with "&&" | |
240 | in which case the split condition is the logical and of the insn | |
241 | condition and what follows the "&&" of this operand. | |
242 | 5: vector of insn patterns to place into a SEQUENCE | |
243 | 6: optionally, some C code to execute before generating the | |
244 | insns. This might, for example, create some RTX's and store them in | |
37bef197 TC |
245 | elements of `recog_data.operand' for use by the vector of |
246 | insn-patterns. | |
247 | (`operands' is an alias here for `recog_data.operand'). | |
c88c0d42 | 248 | 7: optionally, a vector of attributes for this insn. */ |
ec8e098d | 249 | DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) |
c88c0d42 | 250 | |
ede7cd44 RH |
251 | /* Definition of an RTL peephole operation. |
252 | Follows the same arguments as define_split. */ | |
ec8e098d | 253 | DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) |
ede7cd44 | 254 | |
1af1688b RK |
255 | /* Define how to generate multiple insns for a standard insn name. |
256 | 1st operand: the insn name. | |
257 | 2nd operand: vector of insn-patterns. | |
37bef197 | 258 | Use match_operand to substitute an element of `recog_data.operand'. |
1af1688b RK |
259 | 3rd operand: C expression that must be true for this to be available. |
260 | This may not test any operands. | |
261 | 4th operand: Extra C code to execute before generating the insns. | |
262 | This might, for example, create some RTX's and store them in | |
37bef197 TC |
263 | elements of `recog_data.operand' for use by the vector of |
264 | insn-patterns. | |
265 | (`operands' is an alias here for `recog_data.operand'). */ | |
ec8e098d | 266 | DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA) |
1af1688b RK |
267 | |
268 | /* Define a requirement for delay slots. | |
269 | 1st operand: Condition involving insn attributes that, if true, | |
270 | indicates that the insn requires the number of delay slots | |
271 | shown. | |
272 | 2nd operand: Vector whose length is the three times the number of delay | |
273 | slots required. | |
274 | Each entry gives three conditions, each involving attributes. | |
275 | The first must be true for an insn to occupy that delay slot | |
276 | location. The second is true for all insns that can be | |
277 | annulled if the branch is true and the third is true for all | |
278 | insns that can be annulled if the branch is false. | |
279 | ||
280 | Multiple DEFINE_DELAYs may be present. They indicate differing | |
281 | requirements for delay slots. */ | |
ec8e098d | 282 | DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) |
1af1688b RK |
283 | |
284 | /* Define a set of insns that requires a function unit. This means that | |
285 | these insns produce their result after a delay and that there may be | |
286 | restrictions on the number of insns of this type that can be scheduled | |
287 | simultaneously. | |
288 | ||
289 | More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. | |
290 | Each gives a set of operations and associated delays. The first three | |
291 | operands must be the same for each operation for the same function unit. | |
292 | ||
f6601f3a | 293 | All delays are specified in cycles. |
1af1688b RK |
294 | |
295 | 1st operand: Name of function unit (mostly for documentation) | |
296 | 2nd operand: Number of identical function units in CPU | |
297 | 3rd operand: Total number of simultaneous insns that can execute on this | |
298 | function unit; 0 if unlimited. | |
299 | 4th operand: Condition involving insn attribute, that, if true, specifies | |
300 | those insns that this expression applies to. | |
301 | 5th operand: Constant delay after which insn result will be | |
302 | available. | |
303 | 6th operand: Delay until next insn can be scheduled on the function unit | |
304 | executing this operation. The meaning depends on whether or | |
305 | not the next operand is supplied. | |
306 | 7th operand: If this operand is not specified, the 6th operand gives the | |
f6601f3a TW |
307 | number of cycles after the instruction matching the 4th |
308 | operand begins using the function unit until a subsequent | |
309 | insn can begin. A value of zero should be used for a | |
310 | unit with no issue constraints. If only one operation can | |
311 | be executed a time and the unit is busy for the entire time, | |
312 | the 3rd operand should be specified as 1, the 6th operand | |
956d6950 | 313 | should be specified as 0, and the 7th operand should not |
f6601f3a | 314 | be specified. |
1af1688b RK |
315 | |
316 | If this operand is specified, it is a list of attribute | |
317 | expressions. If an insn for which any of these expressions | |
318 | is true is currently executing on the function unit, the | |
f6601f3a TW |
319 | issue delay will be given by the 6th operand. Otherwise, |
320 | the insn can be immediately scheduled (subject to the limit | |
321 | on the number of simultaneous operations executing on the | |
1af1688b | 322 | unit.) */ |
ec8e098d | 323 | DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", RTX_EXTRA) |
1af1688b RK |
324 | |
325 | /* Define attribute computation for `asm' instructions. */ | |
ec8e098d | 326 | DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) |
1af1688b | 327 | |
3262c1f5 RH |
328 | /* Definition of a conditional execution meta operation. Automatically |
329 | generates new instances of DEFINE_INSN, selected by having attribute | |
330 | "predicable" true. The new pattern will contain a COND_EXEC and the | |
331 | predicate at top-level. | |
332 | ||
333 | Operand: | |
334 | 0: The predicate pattern. The top-level form should match a | |
335 | relational operator. Operands should have only one alternative. | |
336 | 1: A C expression giving an additional condition for recognizing | |
337 | the generated pattern. | |
338 | 2: A template or C code to produce assembler output. */ | |
ec8e098d | 339 | DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) |
3262c1f5 | 340 | |
1af1688b RK |
341 | /* SEQUENCE appears in the result of a `gen_...' function |
342 | for a DEFINE_EXPAND that wants to make several insns. | |
343 | Its elements are the bodies of the insns that should be made. | |
344 | `emit_insn' takes the SEQUENCE apart and makes separate insns. */ | |
ec8e098d | 345 | DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) |
1af1688b | 346 | |
f0f61682 | 347 | /* Refers to the address of its argument. This is only used in alias.c. */ |
ec8e098d | 348 | DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH) |
1af1688b | 349 | |
fae15c93 VM |
350 | /* ---------------------------------------------------------------------- |
351 | Constructions for CPU pipeline description described by NDFAs. | |
352 | These do not appear in actual rtl code in the compiler. | |
353 | ---------------------------------------------------------------------- */ | |
354 | ||
355 | /* (define_cpu_unit string [string]) describes cpu functional | |
356 | units (separated by comma). | |
357 | ||
358 | 1st operand: Names of cpu functional units. | |
359 | 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). | |
360 | ||
361 | All define_reservations, define_cpu_units, and | |
362 | define_query_cpu_units should have unique names which may not be | |
363 | "nothing". */ | |
ec8e098d | 364 | DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) |
fae15c93 VM |
365 | |
366 | /* (define_query_cpu_unit string [string]) describes cpu functional | |
30028c85 VM |
367 | units analogously to define_cpu_unit. The reservation of such |
368 | units can be queried for automaton state. */ | |
ec8e098d | 369 | DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) |
fae15c93 VM |
370 | |
371 | /* (exclusion_set string string) means that each CPU functional unit | |
372 | in the first string can not be reserved simultaneously with any | |
373 | unit whose name is in the second string and vise versa. CPU units | |
374 | in the string are separated by commas. For example, it is useful | |
375 | for description CPU with fully pipelined floating point functional | |
376 | unit which can execute simultaneously only single floating point | |
377 | insns or only double floating point insns. All CPU functional | |
30028c85 | 378 | units in a set should belong to the same automaton. */ |
ec8e098d | 379 | DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) |
fae15c93 VM |
380 | |
381 | /* (presence_set string string) means that each CPU functional unit in | |
30028c85 VM |
382 | the first string can not be reserved unless at least one of pattern |
383 | of units whose names are in the second string is reserved. This is | |
384 | an asymmetric relation. CPU units or unit patterns in the strings | |
385 | are separated by commas. Pattern is one unit name or unit names | |
386 | separated by white-spaces. | |
387 | ||
388 | For example, it is useful for description that slot1 is reserved | |
389 | after slot0 reservation for a VLIW processor. We could describe it | |
390 | by the following construction | |
391 | ||
392 | (presence_set "slot1" "slot0") | |
393 | ||
394 | Or slot1 is reserved only after slot0 and unit b0 reservation. In | |
395 | this case we could write | |
396 | ||
397 | (presence_set "slot1" "slot0 b0") | |
398 | ||
399 | All CPU functional units in a set should belong to the same | |
400 | automaton. */ | |
ec8e098d | 401 | DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) |
fae15c93 | 402 | |
30028c85 VM |
403 | /* (final_presence_set string string) is analogous to `presence_set'. |
404 | The difference between them is when checking is done. When an | |
405 | instruction is issued in given automaton state reflecting all | |
406 | current and planned unit reservations, the automaton state is | |
407 | changed. The first state is a source state, the second one is a | |
408 | result state. Checking for `presence_set' is done on the source | |
409 | state reservation, checking for `final_presence_set' is done on the | |
410 | result reservation. This construction is useful to describe a | |
411 | reservation which is actually two subsequent reservations. For | |
412 | example, if we use | |
413 | ||
414 | (presence_set "slot1" "slot0") | |
415 | ||
416 | the following insn will be never issued (because slot1 requires | |
417 | slot0 which is absent in the source state). | |
418 | ||
419 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
420 | ||
421 | but it can be issued if we use analogous `final_presence_set'. */ | |
ec8e098d | 422 | DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) |
30028c85 | 423 | |
fae15c93 | 424 | /* (absence_set string string) means that each CPU functional unit in |
30028c85 VM |
425 | the first string can be reserved only if each pattern of units |
426 | whose names are in the second string is not reserved. This is an | |
427 | asymmetric relation (actually exclusion set is analogous to this | |
428 | one but it is symmetric). CPU units or unit patterns in the string | |
429 | are separated by commas. Pattern is one unit name or unit names | |
430 | separated by white-spaces. | |
431 | ||
432 | For example, it is useful for description that slot0 can not be | |
433 | reserved after slot1 or slot2 reservation for a VLIW processor. We | |
434 | could describe it by the following construction | |
435 | ||
436 | (absence_set "slot2" "slot0, slot1") | |
437 | ||
438 | Or slot2 can not be reserved if slot0 and unit b0 are reserved or | |
439 | slot1 and unit b1 are reserved . In this case we could write | |
440 | ||
441 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
442 | ||
443 | All CPU functional units in a set should to belong the same | |
444 | automaton. */ | |
ec8e098d | 445 | DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) |
fae15c93 | 446 | |
30028c85 VM |
447 | /* (final_absence_set string string) is analogous to `absence_set' but |
448 | checking is done on the result (state) reservation. See comments | |
449 | for `final_presence_set'. */ | |
ec8e098d | 450 | DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) |
30028c85 | 451 | |
fae15c93 VM |
452 | /* (define_bypass number out_insn_names in_insn_names) names bypass |
453 | with given latency (the first number) from insns given by the first | |
454 | string (see define_insn_reservation) into insns given by the second | |
455 | string. Insn names in the strings are separated by commas. The | |
456 | third operand is optional name of function which is additional | |
457 | guard for the bypass. The function will get the two insns as | |
458 | parameters. If the function returns zero the bypass will be | |
459 | ignored for this case. Additional guard is necessary to recognize | |
460 | complicated bypasses, e.g. when consumer is load address. */ | |
ec8e098d | 461 | DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) |
fae15c93 VM |
462 | |
463 | /* (define_automaton string) describes names of automata generated and | |
464 | used for pipeline hazards recognition. The names are separated by | |
465 | comma. Actually it is possibly to generate the single automaton | |
466 | but unfortunately it can be very large. If we use more one | |
467 | automata, the summary size of the automata usually is less than the | |
468 | single one. The automaton name is used in define_cpu_unit and | |
469 | define_query_cpu_unit. All automata should have unique names. */ | |
ec8e098d | 470 | DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) |
fae15c93 VM |
471 | |
472 | /* (automata_option string) describes option for generation of | |
473 | automata. Currently there are the following options: | |
474 | ||
475 | o "no-minimization" which makes no minimization of automata. This | |
30028c85 VM |
476 | is only worth to do when we are debugging the description and |
477 | need to look more accurately at reservations of states. | |
fae15c93 | 478 | |
e3c8eb86 VM |
479 | o "time" which means printing additional time statistics about |
480 | generation of automata. | |
481 | ||
482 | o "v" which means generation of file describing the result | |
483 | automata. The file has suffix `.dfa' and can be used for the | |
484 | description verification and debugging. | |
485 | ||
486 | o "w" which means generation of warning instead of error for | |
487 | non-critical errors. | |
fae15c93 | 488 | |
dfa849f3 VM |
489 | o "ndfa" which makes nondeterministic finite state automata. |
490 | ||
491 | o "progress" which means output of a progress bar showing how many | |
492 | states were generated so far for automaton being processed. */ | |
ec8e098d | 493 | DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) |
fae15c93 VM |
494 | |
495 | /* (define_reservation string string) names reservation (the first | |
496 | string) of cpu functional units (the 2nd string). Sometimes unit | |
497 | reservations for different insns contain common parts. In such | |
498 | case, you can describe common part and use its name (the 1st | |
499 | parameter) in regular expression in define_insn_reservation. All | |
500 | define_reservations, define_cpu_units, and define_query_cpu_units | |
501 | should have unique names which may not be "nothing". */ | |
ec8e098d | 502 | DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) |
fae15c93 VM |
503 | |
504 | /* (define_insn_reservation name default_latency condition regexpr) | |
505 | describes reservation of cpu functional units (the 3nd operand) for | |
506 | instruction which is selected by the condition (the 2nd parameter). | |
507 | The first parameter is used for output of debugging information. | |
508 | The reservations are described by a regular expression according | |
509 | the following syntax: | |
510 | ||
511 | regexp = regexp "," oneof | |
512 | | oneof | |
513 | ||
514 | oneof = oneof "|" allof | |
515 | | allof | |
516 | ||
517 | allof = allof "+" repeat | |
518 | | repeat | |
519 | ||
520 | repeat = element "*" number | |
521 | | element | |
522 | ||
523 | element = cpu_function_unit_name | |
524 | | reservation_name | |
525 | | result_name | |
526 | | "nothing" | |
527 | | "(" regexp ")" | |
528 | ||
529 | 1. "," is used for describing start of the next cycle in | |
530 | reservation. | |
531 | ||
532 | 2. "|" is used for describing the reservation described by the | |
533 | first regular expression *or* the reservation described by the | |
534 | second regular expression *or* etc. | |
535 | ||
536 | 3. "+" is used for describing the reservation described by the | |
537 | first regular expression *and* the reservation described by the | |
538 | second regular expression *and* etc. | |
539 | ||
4d6922ee | 540 | 4. "*" is used for convenience and simply means sequence in |
fae15c93 VM |
541 | which the regular expression are repeated NUMBER times with |
542 | cycle advancing (see ","). | |
543 | ||
544 | 5. cpu functional unit name which means its reservation. | |
545 | ||
546 | 6. reservation name -- see define_reservation. | |
547 | ||
548 | 7. string "nothing" means no units reservation. */ | |
549 | ||
ec8e098d | 550 | DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) |
fae15c93 | 551 | |
1af1688b RK |
552 | /* ---------------------------------------------------------------------- |
553 | Expressions used for insn attributes. These also do not appear in | |
554 | actual rtl code in the compiler. | |
555 | ---------------------------------------------------------------------- */ | |
556 | ||
557 | /* Definition of an insn attribute. | |
558 | 1st operand: name of the attribute | |
559 | 2nd operand: comma-separated list of possible attribute values | |
991b6592 | 560 | 3rd operand: expression for the default value of the attribute. */ |
ec8e098d | 561 | DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) |
1af1688b | 562 | |
991b6592 | 563 | /* Marker for the name of an attribute. */ |
ec8e098d | 564 | DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) |
1af1688b RK |
565 | |
566 | /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and | |
567 | in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that | |
568 | pattern. | |
569 | ||
570 | (set_attr "name" "value") is equivalent to | |
571 | (set (attr "name") (const_string "value")) */ | |
ec8e098d | 572 | DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) |
1af1688b RK |
573 | |
574 | /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to | |
575 | specify that attribute values are to be assigned according to the | |
576 | alternative matched. | |
577 | ||
578 | The following three expressions are equivalent: | |
579 | ||
580 | (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") | |
581 | (eq_attrq "alternative" "2") (const_string "a2")] | |
582 | (const_string "a3"))) | |
583 | (set_attr_alternative "att" [(const_string "a1") (const_string "a2") | |
584 | (const_string "a3")]) | |
585 | (set_attr "att" "a1,a2,a3") | |
586 | */ | |
ec8e098d | 587 | DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) |
1af1688b RK |
588 | |
589 | /* A conditional expression true if the value of the specified attribute of | |
590 | the current insn equals the specified value. The first operand is the | |
591 | attribute name and the second is the comparison value. */ | |
ec8e098d | 592 | DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) |
1af1688b | 593 | |
8653a1ed ZD |
594 | /* A special case of the above representing a set of alternatives. The first |
595 | operand is bitmap of the set, the second one is the default value. */ | |
ec8e098d | 596 | DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) |
8653a1ed | 597 | |
417a6986 JL |
598 | /* A conditional expression which is true if the specified flag is |
599 | true for the insn being scheduled in reorg. | |
600 | ||
601 | genattr.c defines the following flags which can be tested by | |
602 | (attr_flag "foo") expressions in eligible_for_delay. | |
603 | ||
604 | forward, backward, very_likely, likely, very_unlikely, and unlikely. */ | |
605 | ||
ec8e098d | 606 | DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) |
417a6986 | 607 | |
1af1688b RK |
608 | /* ---------------------------------------------------------------------- |
609 | Expression types used for things in the instruction chain. | |
610 | ||
611 | All formats must start with "iuu" to handle the chain. | |
612 | Each insn expression holds an rtl instruction and its semantics | |
613 | during back-end processing. | |
e1de1560 | 614 | See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. |
1af1688b RK |
615 | |
616 | ---------------------------------------------------------------------- */ | |
617 | ||
618 | /* An instruction that cannot jump. */ | |
ec8e098d | 619 | DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN) |
1af1688b RK |
620 | |
621 | /* An instruction that can possibly jump. | |
e1de1560 | 622 | Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ |
ec8e098d | 623 | DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN) |
1af1688b RK |
624 | |
625 | /* An instruction that can possibly call a subroutine | |
626 | but which will not change which instruction comes next | |
627 | in the current function. | |
e1de1560 RS |
628 | Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE. |
629 | All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ | |
ec8e098d | 630 | DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN) |
1af1688b RK |
631 | |
632 | /* A marker that indicates that control will not flow through. */ | |
ec8e098d | 633 | DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA) |
1af1688b RK |
634 | |
635 | /* Holds a label that is followed by instructions. | |
636 | Operand: | |
a7eaa37d JW |
637 | 4: is used in jump.c for the use-count of the label. |
638 | 5: is used in flow.c to point to the chain of label_ref's to this label. | |
639 | 6: is a number that is unique in the entire compilation. | |
640 | 7: is the user-given name of the label, if any. */ | |
ec8e098d | 641 | DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) |
0dc36574 | 642 | |
c1667470 PB |
643 | #ifdef USE_MAPPED_LOCATION |
644 | /* Say where in the code a source line starts, for symbol table's sake. | |
645 | Operand: | |
646 | 4: unused if line number > 0, note-specific data otherwise. | |
647 | 5: line number if > 0, enum note_insn otherwise. | |
648 | 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */ | |
649 | #else | |
1af1688b | 650 | /* Say where in the code a source line starts, for symbol table's sake. |
f5540cd4 | 651 | Operand: |
a7eaa37d JW |
652 | 4: filename, if line number > 0, note-specific data otherwise. |
653 | 5: line number if > 0, enum note_insn otherwise. | |
654 | 6: unique number if line number == note_insn_deleted_label. */ | |
c1667470 | 655 | #endif |
ec8e098d | 656 | DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) |
1af1688b | 657 | |
1af1688b RK |
658 | /* ---------------------------------------------------------------------- |
659 | Top level constituents of INSN, JUMP_INSN and CALL_INSN. | |
660 | ---------------------------------------------------------------------- */ | |
661 | ||
6b29b0e2 JW |
662 | /* Conditionally execute code. |
663 | Operand 0 is the condition that if true, the code is executed. | |
664 | Operand 1 is the code to be executed (typically a SET). | |
665 | ||
666 | Semantics are that there are no side effects if the condition | |
667 | is false. This pattern is created automatically by the if_convert | |
668 | pass run after reload or by target-specific splitters. */ | |
ec8e098d | 669 | DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) |
6b29b0e2 JW |
670 | |
671 | /* Several operations to be done in parallel (perhaps under COND_EXEC). */ | |
ec8e098d | 672 | DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) |
1af1688b RK |
673 | |
674 | /* A string that is passed through to the assembler as input. | |
675 | One can obviously pass comments through by using the | |
676 | assembler comment syntax. | |
677 | These occur in an insn all by themselves as the PATTERN. | |
678 | They also appear inside an ASM_OPERANDS | |
679 | as a convenient way to hold a string. */ | |
ec8e098d | 680 | DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA) |
1af1688b | 681 | |
c1667470 PB |
682 | #ifdef USE_MAPPED_LOCATION |
683 | /* An assembler instruction with operands. | |
684 | 1st operand is the instruction template. | |
685 | 2nd operand is the constraint for the output. | |
686 | 3rd operand is the number of the output this expression refers to. | |
687 | When an insn stores more than one value, a separate ASM_OPERANDS | |
688 | is made for each output; this integer distinguishes them. | |
689 | 4th is a vector of values of input operands. | |
690 | 5th is a vector of modes and constraints for the input operands. | |
691 | Each element is an ASM_INPUT containing a constraint string | |
692 | and whose mode indicates the mode of the input operand. | |
693 | 6th is the source line number. */ | |
694 | DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA) | |
695 | #else | |
1af1688b RK |
696 | /* An assembler instruction with operands. |
697 | 1st operand is the instruction template. | |
698 | 2nd operand is the constraint for the output. | |
699 | 3rd operand is the number of the output this expression refers to. | |
700 | When an insn stores more than one value, a separate ASM_OPERANDS | |
701 | is made for each output; this integer distinguishes them. | |
702 | 4th is a vector of values of input operands. | |
703 | 5th is a vector of modes and constraints for the input operands. | |
704 | Each element is an ASM_INPUT containing a constraint string | |
705 | and whose mode indicates the mode of the input operand. | |
706 | 6th is the name of the containing source file. | |
707 | 7th is the source line number. */ | |
ec8e098d | 708 | DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA) |
c1667470 | 709 | #endif |
1af1688b | 710 | |
1fcea2b0 RK |
711 | /* A machine-specific operation. |
712 | 1st operand is a vector of operands being used by the operation so that | |
713 | any needed reloads can be done. | |
714 | 2nd operand is a unique value saying which of a number of machine-specific | |
715 | operations is to be performed. | |
716 | (Note that the vector must be the first operand because of the way that | |
717 | genrecog.c record positions within an insn.) | |
718 | This can occur all by itself in a PATTERN, as a component of a PARALLEL, | |
719 | or inside an expression. */ | |
ec8e098d | 720 | DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) |
1fcea2b0 | 721 | |
6dc42e49 | 722 | /* Similar, but a volatile operation and one which may trap. */ |
ec8e098d | 723 | DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) |
1fcea2b0 | 724 | |
1af1688b RK |
725 | /* Vector of addresses, stored as full words. */ |
726 | /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ | |
ec8e098d | 727 | DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) |
1af1688b RK |
728 | |
729 | /* Vector of address differences X0 - BASE, X1 - BASE, ... | |
730 | First operand is BASE; the vector contains the X's. | |
731 | The machine mode of this rtx says how much space to leave | |
33f7f353 JR |
732 | for each difference and is adjusted by branch shortening if |
733 | CASE_VECTOR_SHORTEN_MODE is defined. | |
734 | The third and fourth operands store the target labels with the | |
735 | minimum and maximum addresses respectively. | |
736 | The fifth operand stores flags for use by branch shortening. | |
737 | Set at the start of shorten_branches: | |
738 | min_align: the minimum alignment for any of the target labels. | |
739 | base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. | |
740 | min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. | |
741 | max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. | |
742 | min_after_base: true iff minimum address target label is after BASE. | |
743 | max_after_base: true iff maximum address target label is after BASE. | |
744 | Set by the actual branch shortening process: | |
745 | offset_unsigned: true iff offsets have to be treated as unsigned. | |
746 | scale: scaling that is necessary to make offsets fit into the mode. | |
747 | ||
748 | The third, fourth and fifth operands are only valid when | |
749 | CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing | |
750 | compilations. */ | |
751 | ||
ec8e098d | 752 | DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) |
1af1688b | 753 | |
21b8482a JJ |
754 | /* Memory prefetch, with attributes supported on some targets. |
755 | Operand 1 is the address of the memory to fetch. | |
756 | Operand 2 is 1 for a write access, 0 otherwise. | |
757 | Operand 3 is the level of temporal locality; 0 means there is no | |
758 | temporal locality and 1, 2, and 3 are for increasing levels of temporal | |
759 | locality. | |
760 | ||
761 | The attributes specified by operands 2 and 3 are ignored for targets | |
762 | whose prefetch instructions do not support them. */ | |
ec8e098d | 763 | DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) |
21b8482a | 764 | |
1af1688b RK |
765 | /* ---------------------------------------------------------------------- |
766 | At the top level of an instruction (perhaps under PARALLEL). | |
767 | ---------------------------------------------------------------------- */ | |
768 | ||
769 | /* Assignment. | |
770 | Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. | |
771 | Operand 2 is the value stored there. | |
772 | ALL assignment must use SET. | |
773 | Instructions that do multiple assignments must use multiple SET, | |
774 | under PARALLEL. */ | |
ec8e098d | 775 | DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) |
1af1688b RK |
776 | |
777 | /* Indicate something is used in a way that we don't want to explain. | |
778 | For example, subroutine calls will use the register | |
779 | in which the static chain is passed. */ | |
ec8e098d | 780 | DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) |
1af1688b RK |
781 | |
782 | /* Indicate something is clobbered in a way that we don't want to explain. | |
783 | For example, subroutine calls will clobber some physical registers | |
784 | (the ones that are by convention not saved). */ | |
ec8e098d | 785 | DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) |
1af1688b RK |
786 | |
787 | /* Call a subroutine. | |
788 | Operand 1 is the address to call. | |
789 | Operand 2 is the number of arguments. */ | |
790 | ||
ec8e098d | 791 | DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) |
1af1688b RK |
792 | |
793 | /* Return from a subroutine. */ | |
794 | ||
ec8e098d | 795 | DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) |
1af1688b RK |
796 | |
797 | /* Conditional trap. | |
798 | Operand 1 is the condition. | |
799 | Operand 2 is the trap code. | |
800 | For an unconditional trap, make the condition (const_int 1). */ | |
ec8e098d | 801 | DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) |
1af1688b | 802 | |
52a11cbf RH |
803 | /* Placeholder for _Unwind_Resume before we know if a function call |
804 | or a branch is needed. Operand 1 is the exception region from | |
805 | which control is flowing. */ | |
ec8e098d | 806 | DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA) |
52a11cbf | 807 | |
1af1688b RK |
808 | /* ---------------------------------------------------------------------- |
809 | Primitive values for use in expressions. | |
810 | ---------------------------------------------------------------------- */ | |
811 | ||
812 | /* numeric integer constant */ | |
ec8e098d | 813 | DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) |
1af1688b | 814 | |
aa0b4465 | 815 | /* numeric floating point constant. |
43194145 JZ |
816 | Operands hold the value. They are all 'w' and there may be from 2 to 6; |
817 | see real.h. */ | |
ec8e098d | 818 | DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) |
1af1688b | 819 | |
69ef87e2 | 820 | /* Describes a vector constant. */ |
ec8e098d | 821 | DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA) |
69ef87e2 | 822 | |
1af1688b | 823 | /* String constant. Used only for attributes right now. */ |
ec8e098d | 824 | DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) |
1af1688b RK |
825 | |
826 | /* This is used to encapsulate an expression whose value is constant | |
827 | (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be | |
828 | recognized as a constant operand rather than by arithmetic instructions. */ | |
1af1688b | 829 | |
ec8e098d | 830 | DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) |
c5c76735 | 831 | |
1af1688b RK |
832 | /* program counter. Ordinary jumps are represented |
833 | by a SET whose first operand is (PC). */ | |
ec8e098d | 834 | DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) |
1af1688b | 835 | |
eab5c70a | 836 | /* Used in the cselib routines to describe a value. */ |
ec8e098d | 837 | DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) |
eab5c70a | 838 | |
41472af8 MM |
839 | /* A register. The "operand" is the register number, accessed with |
840 | the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER | |
841 | than a hardware register is being referred to. The second operand | |
08394eef BS |
842 | holds the original register number - this will be different for a |
843 | pseudo register that got turned into a hard register. | |
844 | This rtx needs to have as many (or more) fields as a MEM, since we | |
845 | can change REG rtx's into MEMs during reload. */ | |
ec8e098d | 846 | DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) |
1af1688b RK |
847 | |
848 | /* A scratch register. This represents a register used only within a | |
849 | single insn. It will be turned into a REG during register allocation | |
850 | or reload unless the constraint indicates that the register won't be | |
851 | needed, in which case it can remain a SCRATCH. This code is | |
852 | marked as having one operand so it can be turned into a REG. */ | |
ec8e098d | 853 | DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) |
1af1688b RK |
854 | |
855 | /* One word of a multi-word value. | |
856 | The first operand is the complete value; the second says which word. | |
857 | The WORDS_BIG_ENDIAN flag controls whether word number 0 | |
858 | (as numbered in a SUBREG) is the most or least significant word. | |
859 | ||
860 | This is also used to refer to a value in a different machine mode. | |
861 | For example, it can be used to refer to a SImode value as if it were | |
862 | Qimode, or vice versa. Then the word number is always 0. */ | |
ec8e098d | 863 | DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) |
1af1688b RK |
864 | |
865 | /* This one-argument rtx is used for move instructions | |
866 | that are guaranteed to alter only the low part of a destination. | |
867 | Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) | |
868 | has an unspecified effect on the high part of REG, | |
869 | but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) | |
870 | is guaranteed to alter only the bits of REG that are in HImode. | |
871 | ||
872 | The actual instruction used is probably the same in both cases, | |
873 | but the register constraints may be tighter when STRICT_LOW_PART | |
874 | is in use. */ | |
875 | ||
ec8e098d | 876 | DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) |
1af1688b | 877 | |
ea8fbf8a RS |
878 | /* (CONCAT a b) represents the virtual concatenation of a and b |
879 | to make a value that has as many bits as a and b put together. | |
880 | This is used for complex values. Normally it appears only | |
881 | in DECL_RTLs and during RTL generation, but not in the insn chain. */ | |
ec8e098d | 882 | DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) |
ea8fbf8a | 883 | |
a0fd557a RK |
884 | /* A memory location; operand is the address. The second operand is the |
885 | alias set to which this MEM belongs. We use `0' instead of `w' for this | |
886 | field so that the field need not be specified in machine descriptions. */ | |
ec8e098d | 887 | DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) |
1af1688b RK |
888 | |
889 | /* Reference to an assembler label in the code for this function. | |
890 | The operand is a CODE_LABEL found in the insn chain. | |
891 | The unprinted fields 1 and 2 are used in flow.c for the | |
892 | LABEL_NEXTREF and CONTAINING_INSN. */ | |
ec8e098d | 893 | DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ) |
1af1688b | 894 | |
52859c77 RH |
895 | /* Reference to a named label: |
896 | Operand 0: label name | |
897 | Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) | |
32a61907 ZW |
898 | Operand 2: tree from which this symbol is derived, or null. |
899 | This is either a DECL node, or some kind of constant. */ | |
ec8e098d | 900 | DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) |
1af1688b RK |
901 | |
902 | /* The condition code register is represented, in our imagination, | |
903 | as a register holding a value that can be compared to zero. | |
904 | In fact, the machine has already compared them and recorded the | |
905 | results; but instructions that look at the condition code | |
906 | pretend to be looking at the entire value and comparing it. */ | |
ec8e098d | 907 | DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) |
1af1688b | 908 | |
1af1688b RK |
909 | /* ---------------------------------------------------------------------- |
910 | Expressions for operators in an rtl pattern | |
911 | ---------------------------------------------------------------------- */ | |
912 | ||
913 | /* if_then_else. This is used in representing ordinary | |
914 | conditional jump instructions. | |
915 | Operand: | |
916 | 0: condition | |
917 | 1: then expr | |
918 | 2: else expr */ | |
ec8e098d | 919 | DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) |
1af1688b RK |
920 | |
921 | /* General conditional. The first operand is a vector composed of pairs of | |
922 | expressions. The first element of each pair is evaluated, in turn. | |
923 | The value of the conditional is the second expression of the first pair | |
0e9e1e0a | 924 | whose first expression evaluates nonzero. If none of the expressions is |
1af1688b RK |
925 | true, the second operand will be used as the value of the conditional. |
926 | ||
927 | This should be replaced with use of IF_THEN_ELSE. */ | |
ec8e098d | 928 | DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) |
1af1688b RK |
929 | |
930 | /* Comparison, produces a condition code result. */ | |
ec8e098d | 931 | DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) |
1af1688b RK |
932 | |
933 | /* plus */ | |
ec8e098d | 934 | DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) |
1af1688b RK |
935 | |
936 | /* Operand 0 minus operand 1. */ | |
ec8e098d | 937 | DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) |
1af1688b RK |
938 | |
939 | /* Minus operand 0. */ | |
ec8e098d | 940 | DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) |
1af1688b | 941 | |
ec8e098d | 942 | DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) |
1af1688b RK |
943 | |
944 | /* Operand 0 divided by operand 1. */ | |
ec8e098d | 945 | DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) |
1af1688b | 946 | /* Remainder of operand 0 divided by operand 1. */ |
ec8e098d | 947 | DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) |
1af1688b RK |
948 | |
949 | /* Unsigned divide and remainder. */ | |
ec8e098d PB |
950 | DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) |
951 | DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) | |
1af1688b RK |
952 | |
953 | /* Bitwise operations. */ | |
ec8e098d | 954 | DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) |
1af1688b | 955 | |
ec8e098d | 956 | DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) |
1af1688b | 957 | |
ec8e098d | 958 | DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) |
1af1688b | 959 | |
ec8e098d | 960 | DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) |
1af1688b RK |
961 | |
962 | /* Operand: | |
963 | 0: value to be shifted. | |
160d4f27 | 964 | 1: number of bits. */ |
ec8e098d PB |
965 | DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ |
966 | DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ | |
967 | DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ | |
968 | DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ | |
969 | DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ | |
1af1688b RK |
970 | |
971 | /* Minimum and maximum values of two operands. We need both signed and | |
972 | unsigned forms. (We cannot use MIN for SMIN because it conflicts | |
973 | with a macro of the same name.) */ | |
974 | ||
ec8e098d PB |
975 | DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) |
976 | DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) | |
977 | DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) | |
978 | DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) | |
1af1688b RK |
979 | |
980 | /* These unary operations are used to represent incrementation | |
981 | and decrementation as they occur in memory addresses. | |
982 | The amount of increment or decrement are not represented | |
983 | because they can be understood from the machine-mode of the | |
984 | containing MEM. These operations exist in only two cases: | |
985 | 1. pushes onto the stack. | |
986 | 2. created automatically by the life_analysis pass in flow.c. */ | |
ec8e098d PB |
987 | DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) |
988 | DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) | |
989 | DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) | |
990 | DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) | |
1af1688b | 991 | |
b18cfc28 MH |
992 | /* These binary operations are used to represent generic address |
993 | side-effects in memory addresses, except for simple incrementation | |
994 | or decrementation which use the above operations. They are | |
4b983fdc RH |
995 | created automatically by the life_analysis pass in flow.c. |
996 | The first operand is a REG which is used as the address. | |
997 | The second operand is an expression that is assigned to the | |
998 | register, either before (PRE_MODIFY) or after (POST_MODIFY) | |
999 | evaluating the address. | |
1000 | Currently, the compiler can only handle second operands of the | |
1001 | form (plus (reg) (reg)) and (plus (reg) (const_int)), where | |
1002 | the first operand of the PLUS has to be the same register as | |
1003 | the first operand of the *_MODIFY. */ | |
ec8e098d PB |
1004 | DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) |
1005 | DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) | |
b18cfc28 | 1006 | |
1af1688b RK |
1007 | /* Comparison operations. The ordered comparisons exist in two |
1008 | flavors, signed and unsigned. */ | |
ec8e098d PB |
1009 | DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) |
1010 | DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) | |
1011 | DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) | |
1012 | DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) | |
1013 | DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) | |
1014 | DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) | |
1015 | DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) | |
1016 | DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) | |
1017 | DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) | |
1018 | DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) | |
1af1688b | 1019 | |
14b493d6 | 1020 | /* Additional floating point unordered comparison flavors. */ |
ec8e098d PB |
1021 | DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) |
1022 | DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) | |
1eb8759b | 1023 | |
991b6592 | 1024 | /* These are equivalent to unordered or ... */ |
ec8e098d PB |
1025 | DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) |
1026 | DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) | |
1027 | DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) | |
1028 | DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) | |
1029 | DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) | |
1eb8759b | 1030 | |
7913f3d0 | 1031 | /* This is an ordered NE, ie !UNEQ, ie false for NaN. */ |
ec8e098d | 1032 | DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) |
7913f3d0 | 1033 | |
1af1688b RK |
1034 | /* Represents the result of sign-extending the sole operand. |
1035 | The machine modes of the operand and of the SIGN_EXTEND expression | |
1036 | determine how much sign-extension is going on. */ | |
ec8e098d | 1037 | DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) |
1af1688b RK |
1038 | |
1039 | /* Similar for zero-extension (such as unsigned short to int). */ | |
ec8e098d | 1040 | DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) |
1af1688b RK |
1041 | |
1042 | /* Similar but here the operand has a wider mode. */ | |
ec8e098d | 1043 | DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) |
1af1688b RK |
1044 | |
1045 | /* Similar for extending floating-point values (such as SFmode to DFmode). */ | |
ec8e098d PB |
1046 | DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) |
1047 | DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) | |
1af1688b RK |
1048 | |
1049 | /* Conversion of fixed point operand to floating point value. */ | |
ec8e098d | 1050 | DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) |
1af1688b RK |
1051 | |
1052 | /* With fixed-point machine mode: | |
1053 | Conversion of floating point operand to fixed point value. | |
1054 | Value is defined only when the operand's value is an integer. | |
1055 | With floating-point machine mode (and operand with same mode): | |
1056 | Operand is rounded toward zero to produce an integer value | |
1057 | represented in floating point. */ | |
ec8e098d | 1058 | DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) |
1af1688b RK |
1059 | |
1060 | /* Conversion of unsigned fixed point operand to floating point value. */ | |
ec8e098d | 1061 | DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) |
1af1688b RK |
1062 | |
1063 | /* With fixed-point machine mode: | |
1064 | Conversion of floating point operand to *unsigned* fixed point value. | |
1065 | Value is defined only when the operand's value is an integer. */ | |
ec8e098d | 1066 | DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) |
1af1688b RK |
1067 | |
1068 | /* Absolute value */ | |
ec8e098d | 1069 | DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) |
1af1688b RK |
1070 | |
1071 | /* Square root */ | |
ec8e098d | 1072 | DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) |
1af1688b RK |
1073 | |
1074 | /* Find first bit that is set. | |
1075 | Value is 1 + number of trailing zeros in the arg., | |
1076 | or 0 if arg is 0. */ | |
ec8e098d | 1077 | DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) |
1af1688b | 1078 | |
2928cd7a | 1079 | /* Count leading zeros. */ |
ec8e098d | 1080 | DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) |
2928cd7a RH |
1081 | |
1082 | /* Count trailing zeros. */ | |
ec8e098d | 1083 | DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) |
2928cd7a RH |
1084 | |
1085 | /* Population count (number of 1 bits). */ | |
ec8e098d | 1086 | DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) |
2928cd7a RH |
1087 | |
1088 | /* Population parity (number of 1 bits modulo 2). */ | |
ec8e098d | 1089 | DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) |
2928cd7a | 1090 | |
1af1688b RK |
1091 | /* Reference to a signed bit-field of specified size and position. |
1092 | Operand 0 is the memory unit (usually SImode or QImode) which | |
1093 | contains the field's first bit. Operand 1 is the width, in bits. | |
1094 | Operand 2 is the number of bits in the memory unit before the | |
1095 | first bit of this field. | |
1096 | If BITS_BIG_ENDIAN is defined, the first bit is the msb and | |
1097 | operand 2 counts from the msb of the memory unit. | |
1098 | Otherwise, the first bit is the lsb and operand 2 counts from | |
1099 | the lsb of the memory unit. */ | |
ec8e098d | 1100 | DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) |
1af1688b RK |
1101 | |
1102 | /* Similar for unsigned bit-field. */ | |
ec8e098d | 1103 | DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) |
1af1688b RK |
1104 | |
1105 | /* For RISC machines. These save memory when splitting insns. */ | |
1106 | ||
1107 | /* HIGH are the high-order bits of a constant expression. */ | |
ec8e098d | 1108 | DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) |
1af1688b RK |
1109 | |
1110 | /* LO_SUM is the sum of a register and the low-order bits | |
1111 | of a constant expression. */ | |
ec8e098d | 1112 | DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) |
1af1688b | 1113 | |
b3b42a4d | 1114 | /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn. |
0dfa1860 MM |
1115 | Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of |
1116 | the registers that can be substituted within this range. Operand 3 is the | |
1117 | number of calls in the range. Operand 4 is the number of insns in the | |
1118 | range. Operand 5 is the unique range number for this range. Operand 6 is | |
1119 | the basic block # of the start of the live range. Operand 7 is the basic | |
1120 | block # of the end of the live range. Operand 8 is the loop depth. Operand | |
1121 | 9 is a bitmap of the registers live at the start of the range. Operand 10 | |
1122 | is a bitmap of the registers live at the end of the range. Operand 11 is | |
1123 | marker number for the start of the range. Operand 12 is the marker number | |
1124 | for the end of the range. */ | |
ec8e098d | 1125 | DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", RTX_EXTRA) |
0dfa1860 MM |
1126 | |
1127 | /* Registers that can be substituted within the range. Operand 0 is the | |
1128 | original pseudo register number. Operand 1 will be filled in with the | |
1129 | pseudo register the value is copied for the duration of the range. Operand | |
1130 | 2 is the number of references within the range to the register. Operand 3 | |
1131 | is the number of sets or clobbers of the register in the range. Operand 4 | |
1132 | is the number of deaths the register has. Operand 5 is the copy flags that | |
1133 | give the status of whether a copy is needed from the original register to | |
1134 | the new register at the beginning of the range, or whether a copy from the | |
1135 | new register back to the original at the end of the range. Operand 6 is the | |
1136 | live length. Operand 7 is the number of calls that this register is live | |
1137 | across. Operand 8 is the symbol node of the variable if the register is a | |
1138 | user variable. Operand 9 is the block node that the variable is declared | |
991b6592 | 1139 | in if the register is a user variable. */ |
ec8e098d | 1140 | DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", RTX_EXTRA) |
0dfa1860 MM |
1141 | |
1142 | /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of | |
1143 | the different ranges a variable is in where it is copied to a different | |
1144 | pseudo register. Operand 1 is the block that the variable is declared in. | |
1145 | Operand 2 is the number of distinct ranges. */ | |
ec8e098d | 1146 | DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", RTX_EXTRA) |
0dfa1860 MM |
1147 | |
1148 | /* Information about the registers that are live at the current point. Operand | |
1149 | 0 is the live bitmap. Operand 1 is the original block number. */ | |
ec8e098d | 1150 | DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", RTX_EXTRA) |
0dfa1860 | 1151 | |
f9f27ee5 BS |
1152 | /* Describes a merge operation between two vector values. |
1153 | Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask | |
1154 | that specifies where the parts of the result are taken from. Set bits | |
1155 | indicate operand 0, clear bits indicate operand 1. The parts are defined | |
1156 | by the mode of the vectors. */ | |
ec8e098d | 1157 | DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) |
f9f27ee5 BS |
1158 | |
1159 | /* Describes an operation that selects parts of a vector. | |
1160 | Operands 0 is the source vector, operand 1 is a PARALLEL that contains | |
1161 | a CONST_INT for each of the subparts of the result vector, giving the | |
1162 | number of the source subpart that should be stored into it. */ | |
ec8e098d | 1163 | DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) |
f9f27ee5 BS |
1164 | |
1165 | /* Describes a vector concat operation. Operands 0 and 1 are the source | |
1166 | vectors, the result is a vector that is as long as operands 0 and 1 | |
1167 | combined and is the concatenation of the two source vectors. */ | |
ec8e098d | 1168 | DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) |
f9f27ee5 | 1169 | |
f9f27ee5 BS |
1170 | /* Describes an operation that converts a small vector into a larger one by |
1171 | duplicating the input values. The output vector mode must have the same | |
1172 | submodes as the input vector mode, and the number of output parts must be | |
1173 | an integer multiple of the number of input parts. */ | |
ec8e098d | 1174 | DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) |
f9f27ee5 BS |
1175 | |
1176 | /* Addition with signed saturation */ | |
ec8e098d | 1177 | DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) |
f9f27ee5 BS |
1178 | |
1179 | /* Addition with unsigned saturation */ | |
ec8e098d | 1180 | DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) |
f9f27ee5 BS |
1181 | |
1182 | /* Operand 0 minus operand 1, with signed saturation. */ | |
ec8e098d | 1183 | DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) |
f9f27ee5 BS |
1184 | |
1185 | /* Operand 0 minus operand 1, with unsigned saturation. */ | |
ec8e098d | 1186 | DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) |
f9f27ee5 BS |
1187 | |
1188 | /* Signed saturating truncate. */ | |
ec8e098d | 1189 | DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) |
f9f27ee5 BS |
1190 | |
1191 | /* Unsigned saturating truncate. */ | |
ec8e098d | 1192 | DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) |
f9f27ee5 | 1193 | |
014a1138 | 1194 | /* Information about the variable and its location. */ |
ed5947c9 | 1195 | DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA) |
d9d4fb43 | 1196 | |
1af1688b RK |
1197 | /* |
1198 | Local variables: | |
1199 | mode:c | |
1af1688b RK |
1200 | End: |
1201 | */ |