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62d6a022 | 1 | /* Analyze RTL for GNU compiler. |
9daf6266 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3b23b4cc | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
0a98b6d9 | 4 | 2011, 2012 Free Software Foundation, Inc. |
635aff97 | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
635aff97 | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 10 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 11 | version. |
635aff97 | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
635aff97 | 17 | |
18 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
635aff97 | 21 | |
22 | ||
23 | #include "config.h" | |
405711de | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
0b205f4c | 27 | #include "diagnostic-core.h" |
b8011969 | 28 | #include "hard-reg-set.h" |
b2528b76 | 29 | #include "rtl.h" |
aee989f5 | 30 | #include "insn-config.h" |
31 | #include "recog.h" | |
26619827 | 32 | #include "target.h" |
33 | #include "output.h" | |
77ec0c64 | 34 | #include "tm_p.h" |
350b17ef | 35 | #include "flags.h" |
67d6c12b | 36 | #include "regs.h" |
d263732c | 37 | #include "function.h" |
3072d30e | 38 | #include "df.h" |
e0ab7256 | 39 | #include "tree.h" |
06f9d6ef | 40 | #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */ |
635aff97 | 41 | |
99b86c05 | 42 | /* Forward declarations */ |
81a410b1 | 43 | static void set_of_1 (rtx, const_rtx, void *); |
dd9b9fc5 | 44 | static bool covers_regno_p (const_rtx, unsigned int); |
45 | static bool covers_regno_no_parallel_p (const_rtx, unsigned int); | |
3ad4992f | 46 | static int rtx_referenced_p_1 (rtx *, void *); |
dd9b9fc5 | 47 | static int computed_jump_p_1 (const_rtx); |
81a410b1 | 48 | static void parms_set (rtx, const_rtx, void *); |
ca6d6e84 | 49 | |
b7bf20db | 50 | static unsigned HOST_WIDE_INT cached_nonzero_bits (const_rtx, enum machine_mode, |
51 | const_rtx, enum machine_mode, | |
d263732c | 52 | unsigned HOST_WIDE_INT); |
b7bf20db | 53 | static unsigned HOST_WIDE_INT nonzero_bits1 (const_rtx, enum machine_mode, |
54 | const_rtx, enum machine_mode, | |
d263732c | 55 | unsigned HOST_WIDE_INT); |
b7bf20db | 56 | static unsigned int cached_num_sign_bit_copies (const_rtx, enum machine_mode, const_rtx, |
d263732c | 57 | enum machine_mode, |
58 | unsigned int); | |
b7bf20db | 59 | static unsigned int num_sign_bit_copies1 (const_rtx, enum machine_mode, const_rtx, |
d263732c | 60 | enum machine_mode, unsigned int); |
61 | ||
a87cf6e5 | 62 | /* Offset of the first 'e', 'E' or 'V' operand for each rtx code, or |
63 | -1 if a code has no such operand. */ | |
64 | static int non_rtx_starting_operands[NUM_RTX_CODE]; | |
65 | ||
4956440a | 66 | /* Truncation narrows the mode from SOURCE mode to DESTINATION mode. |
67 | If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is | |
68 | SIGN_EXTEND then while narrowing we also have to enforce the | |
69 | representation and sign-extend the value to mode DESTINATION_REP. | |
70 | ||
71 | If the value is already sign-extended to DESTINATION_REP mode we | |
72 | can just switch to DESTINATION mode on it. For each pair of | |
73 | integral modes SOURCE and DESTINATION, when truncating from SOURCE | |
74 | to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION] | |
75 | contains the number of high-order bits in SOURCE that have to be | |
76 | copies of the sign-bit so that we can do this mode-switch to | |
77 | DESTINATION. */ | |
78 | ||
79 | static unsigned int | |
80 | num_sign_bit_copies_in_rep[MAX_MODE_INT + 1][MAX_MODE_INT + 1]; | |
635aff97 | 81 | \f |
82 | /* Return 1 if the value of X is unstable | |
83 | (would be different at a different point in the program). | |
84 | The frame pointer, arg pointer, etc. are considered stable | |
85 | (within one function) and so is anything marked `unchanging'. */ | |
86 | ||
87 | int | |
dd9b9fc5 | 88 | rtx_unstable_p (const_rtx x) |
635aff97 | 89 | { |
dd9b9fc5 | 90 | const RTX_CODE code = GET_CODE (x); |
19cb6b50 | 91 | int i; |
92 | const char *fmt; | |
635aff97 | 93 | |
a3c6603a | 94 | switch (code) |
95 | { | |
96 | case MEM: | |
b04fab2a | 97 | return !MEM_READONLY_P (x) || rtx_unstable_p (XEXP (x, 0)); |
635aff97 | 98 | |
a3c6603a | 99 | case CONST: |
0349edce | 100 | CASE_CONST_ANY: |
a3c6603a | 101 | case SYMBOL_REF: |
102 | case LABEL_REF: | |
103 | return 0; | |
635aff97 | 104 | |
a3c6603a | 105 | case REG: |
106 | /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ | |
d9c8e13d | 107 | if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx |
b8011969 | 108 | /* The arg pointer varies if it is not a fixed register. */ |
b04fab2a | 109 | || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) |
d9c8e13d | 110 | return 0; |
d9c8e13d | 111 | /* ??? When call-clobbered, the value is stable modulo the restore |
112 | that must happen after a call. This currently screws up local-alloc | |
113 | into believing that the restore is not needed. */ | |
260e669e | 114 | if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED && x == pic_offset_table_rtx) |
d9c8e13d | 115 | return 0; |
d9c8e13d | 116 | return 1; |
a3c6603a | 117 | |
118 | case ASM_OPERANDS: | |
119 | if (MEM_VOLATILE_P (x)) | |
120 | return 1; | |
121 | ||
d632b59a | 122 | /* Fall through. */ |
a3c6603a | 123 | |
124 | default: | |
125 | break; | |
126 | } | |
635aff97 | 127 | |
128 | fmt = GET_RTX_FORMAT (code); | |
129 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
130 | if (fmt[i] == 'e') | |
cac0c8c9 | 131 | { |
132 | if (rtx_unstable_p (XEXP (x, i))) | |
133 | return 1; | |
134 | } | |
135 | else if (fmt[i] == 'E') | |
136 | { | |
137 | int j; | |
138 | for (j = 0; j < XVECLEN (x, i); j++) | |
139 | if (rtx_unstable_p (XVECEXP (x, i, j))) | |
140 | return 1; | |
141 | } | |
142 | ||
635aff97 | 143 | return 0; |
144 | } | |
145 | ||
146 | /* Return 1 if X has a value that can vary even between two | |
147 | executions of the program. 0 means X can be compared reliably | |
148 | against certain constants or near-constants. | |
ea087693 | 149 | FOR_ALIAS is nonzero if we are called from alias analysis; if it is |
150 | zero, we are slightly more conservative. | |
635aff97 | 151 | The frame pointer and the arg pointer are considered constant. */ |
152 | ||
52d07779 | 153 | bool |
154 | rtx_varies_p (const_rtx x, bool for_alias) | |
635aff97 | 155 | { |
70f5822c | 156 | RTX_CODE code; |
19cb6b50 | 157 | int i; |
158 | const char *fmt; | |
635aff97 | 159 | |
70f5822c | 160 | if (!x) |
161 | return 0; | |
162 | ||
163 | code = GET_CODE (x); | |
635aff97 | 164 | switch (code) |
165 | { | |
166 | case MEM: | |
b04fab2a | 167 | return !MEM_READONLY_P (x) || rtx_varies_p (XEXP (x, 0), for_alias); |
002fe3cb | 168 | |
635aff97 | 169 | case CONST: |
0349edce | 170 | CASE_CONST_ANY: |
635aff97 | 171 | case SYMBOL_REF: |
172 | case LABEL_REF: | |
173 | return 0; | |
174 | ||
175 | case REG: | |
176 | /* Note that we have to test for the actual rtx used for the frame | |
177 | and arg pointers and not just the register number in case we have | |
178 | eliminated the frame and/or arg pointer and are using it | |
179 | for pseudos. */ | |
d9c8e13d | 180 | if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx |
b8011969 | 181 | /* The arg pointer varies if it is not a fixed register. */ |
182 | || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) | |
d9c8e13d | 183 | return 0; |
ea087693 | 184 | if (x == pic_offset_table_rtx |
ea087693 | 185 | /* ??? When call-clobbered, the value is stable modulo the restore |
186 | that must happen after a call. This currently screws up | |
187 | local-alloc into believing that the restore is not needed, so we | |
188 | must return 0 only if we are called from alias analysis. */ | |
260e669e | 189 | && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED || for_alias)) |
ea087693 | 190 | return 0; |
d9c8e13d | 191 | return 1; |
635aff97 | 192 | |
193 | case LO_SUM: | |
194 | /* The operand 0 of a LO_SUM is considered constant | |
f7cd7994 | 195 | (in fact it is related specifically to operand 1) |
196 | during alias analysis. */ | |
197 | return (! for_alias && rtx_varies_p (XEXP (x, 0), for_alias)) | |
198 | || rtx_varies_p (XEXP (x, 1), for_alias); | |
2617fe26 | 199 | |
a3c6603a | 200 | case ASM_OPERANDS: |
201 | if (MEM_VOLATILE_P (x)) | |
202 | return 1; | |
203 | ||
d632b59a | 204 | /* Fall through. */ |
a3c6603a | 205 | |
0dbd1c74 | 206 | default: |
207 | break; | |
635aff97 | 208 | } |
209 | ||
210 | fmt = GET_RTX_FORMAT (code); | |
211 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
212 | if (fmt[i] == 'e') | |
cac0c8c9 | 213 | { |
ea087693 | 214 | if (rtx_varies_p (XEXP (x, i), for_alias)) |
cac0c8c9 | 215 | return 1; |
216 | } | |
217 | else if (fmt[i] == 'E') | |
218 | { | |
219 | int j; | |
220 | for (j = 0; j < XVECLEN (x, i); j++) | |
ea087693 | 221 | if (rtx_varies_p (XVECEXP (x, i, j), for_alias)) |
cac0c8c9 | 222 | return 1; |
223 | } | |
224 | ||
635aff97 | 225 | return 0; |
226 | } | |
227 | ||
1aecae7f | 228 | /* Return nonzero if the use of X as an address in a MEM can cause a trap. |
229 | MODE is the mode of the MEM (not that of X) and UNALIGNED_MEMS controls | |
230 | whether nonzero is returned for unaligned memory accesses on strict | |
231 | alignment machines. */ | |
635aff97 | 232 | |
1aecae7f | 233 | static int |
0eee494e | 234 | rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, |
235 | enum machine_mode mode, bool unaligned_mems) | |
635aff97 | 236 | { |
19cb6b50 | 237 | enum rtx_code code = GET_CODE (x); |
635aff97 | 238 | |
0eee494e | 239 | if (STRICT_ALIGNMENT |
240 | && unaligned_mems | |
241 | && GET_MODE_SIZE (mode) != 0) | |
242 | { | |
243 | HOST_WIDE_INT actual_offset = offset; | |
244 | #ifdef SPARC_STACK_BOUNDARY_HACK | |
245 | /* ??? The SPARC port may claim a STACK_BOUNDARY higher than | |
246 | the real alignment of %sp. However, when it does this, the | |
247 | alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */ | |
248 | if (SPARC_STACK_BOUNDARY_HACK | |
249 | && (x == stack_pointer_rtx || x == hard_frame_pointer_rtx)) | |
250 | actual_offset -= STACK_POINTER_OFFSET; | |
251 | #endif | |
252 | ||
99e9b19f | 253 | if (actual_offset % GET_MODE_SIZE (mode) != 0) |
254 | return 1; | |
0eee494e | 255 | } |
256 | ||
635aff97 | 257 | switch (code) |
258 | { | |
259 | case SYMBOL_REF: | |
0eee494e | 260 | if (SYMBOL_REF_WEAK (x)) |
261 | return 1; | |
262 | if (!CONSTANT_POOL_ADDRESS_P (x)) | |
263 | { | |
264 | tree decl; | |
265 | HOST_WIDE_INT decl_size; | |
266 | ||
267 | if (offset < 0) | |
268 | return 1; | |
269 | if (size == 0) | |
270 | size = GET_MODE_SIZE (mode); | |
271 | if (size == 0) | |
272 | return offset != 0; | |
273 | ||
274 | /* If the size of the access or of the symbol is unknown, | |
275 | assume the worst. */ | |
276 | decl = SYMBOL_REF_DECL (x); | |
277 | ||
278 | /* Else check that the access is in bounds. TODO: restructure | |
92ddcd97 | 279 | expr_size/tree_expr_size/int_expr_size and just use the latter. */ |
0eee494e | 280 | if (!decl) |
281 | decl_size = -1; | |
282 | else if (DECL_P (decl) && DECL_SIZE_UNIT (decl)) | |
283 | decl_size = (host_integerp (DECL_SIZE_UNIT (decl), 0) | |
284 | ? tree_low_cst (DECL_SIZE_UNIT (decl), 0) | |
285 | : -1); | |
286 | else if (TREE_CODE (decl) == STRING_CST) | |
287 | decl_size = TREE_STRING_LENGTH (decl); | |
288 | else if (TYPE_SIZE_UNIT (TREE_TYPE (decl))) | |
289 | decl_size = int_size_in_bytes (TREE_TYPE (decl)); | |
290 | else | |
291 | decl_size = -1; | |
292 | ||
293 | return (decl_size <= 0 ? offset != 0 : offset + size > decl_size); | |
294 | } | |
295 | ||
296 | return 0; | |
67f79732 | 297 | |
635aff97 | 298 | case LABEL_REF: |
635aff97 | 299 | return 0; |
300 | ||
301 | case REG: | |
302 | /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ | |
c0c2b734 | 303 | if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx |
304 | || x == stack_pointer_rtx | |
305 | /* The arg pointer varies if it is not a fixed register. */ | |
306 | || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) | |
307 | return 0; | |
308 | /* All of the virtual frame registers are stack references. */ | |
309 | if (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
310 | && REGNO (x) <= LAST_VIRTUAL_REGISTER) | |
311 | return 0; | |
312 | return 1; | |
635aff97 | 313 | |
314 | case CONST: | |
0eee494e | 315 | return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size, |
316 | mode, unaligned_mems); | |
635aff97 | 317 | |
318 | case PLUS: | |
1aecae7f | 319 | /* An address is assumed not to trap if: |
0eee494e | 320 | - it is the pic register plus a constant. */ |
321 | if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1))) | |
322 | return 0; | |
323 | ||
324 | /* - or it is an address that can't trap plus a constant integer, | |
1aecae7f | 325 | with the proper remainder modulo the mode size if we are |
326 | considering unaligned memory references. */ | |
971ba038 | 327 | if (CONST_INT_P (XEXP (x, 1)) |
0eee494e | 328 | && !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)), |
329 | size, mode, unaligned_mems)) | |
1aecae7f | 330 | return 0; |
331 | ||
332 | return 1; | |
635aff97 | 333 | |
334 | case LO_SUM: | |
c0c2b734 | 335 | case PRE_MODIFY: |
0eee494e | 336 | return rtx_addr_can_trap_p_1 (XEXP (x, 1), offset, size, |
337 | mode, unaligned_mems); | |
c0c2b734 | 338 | |
339 | case PRE_DEC: | |
340 | case PRE_INC: | |
341 | case POST_DEC: | |
342 | case POST_INC: | |
343 | case POST_MODIFY: | |
0eee494e | 344 | return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size, |
345 | mode, unaligned_mems); | |
c0c2b734 | 346 | |
0dbd1c74 | 347 | default: |
348 | break; | |
635aff97 | 349 | } |
350 | ||
351 | /* If it isn't one of the case above, it can cause a trap. */ | |
352 | return 1; | |
353 | } | |
354 | ||
1aecae7f | 355 | /* Return nonzero if the use of X as an address in a MEM can cause a trap. */ |
356 | ||
357 | int | |
dd9b9fc5 | 358 | rtx_addr_can_trap_p (const_rtx x) |
1aecae7f | 359 | { |
0eee494e | 360 | return rtx_addr_can_trap_p_1 (x, 0, 0, VOIDmode, false); |
1aecae7f | 361 | } |
362 | ||
805e22b2 | 363 | /* Return true if X is an address that is known to not be zero. */ |
364 | ||
365 | bool | |
dd9b9fc5 | 366 | nonzero_address_p (const_rtx x) |
805e22b2 | 367 | { |
dd9b9fc5 | 368 | const enum rtx_code code = GET_CODE (x); |
805e22b2 | 369 | |
370 | switch (code) | |
371 | { | |
372 | case SYMBOL_REF: | |
373 | return !SYMBOL_REF_WEAK (x); | |
374 | ||
375 | case LABEL_REF: | |
376 | return true; | |
377 | ||
805e22b2 | 378 | case REG: |
379 | /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ | |
380 | if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx | |
381 | || x == stack_pointer_rtx | |
382 | || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) | |
383 | return true; | |
384 | /* All of the virtual frame registers are stack references. */ | |
385 | if (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
386 | && REGNO (x) <= LAST_VIRTUAL_REGISTER) | |
387 | return true; | |
388 | return false; | |
389 | ||
390 | case CONST: | |
391 | return nonzero_address_p (XEXP (x, 0)); | |
392 | ||
393 | case PLUS: | |
971ba038 | 394 | if (CONST_INT_P (XEXP (x, 1))) |
49e98091 | 395 | return nonzero_address_p (XEXP (x, 0)); |
805e22b2 | 396 | /* Handle PIC references. */ |
397 | else if (XEXP (x, 0) == pic_offset_table_rtx | |
398 | && CONSTANT_P (XEXP (x, 1))) | |
399 | return true; | |
400 | return false; | |
401 | ||
402 | case PRE_MODIFY: | |
403 | /* Similar to the above; allow positive offsets. Further, since | |
404 | auto-inc is only allowed in memories, the register must be a | |
405 | pointer. */ | |
971ba038 | 406 | if (CONST_INT_P (XEXP (x, 1)) |
805e22b2 | 407 | && INTVAL (XEXP (x, 1)) > 0) |
408 | return true; | |
409 | return nonzero_address_p (XEXP (x, 0)); | |
410 | ||
411 | case PRE_INC: | |
412 | /* Similarly. Further, the offset is always positive. */ | |
413 | return true; | |
414 | ||
415 | case PRE_DEC: | |
416 | case POST_DEC: | |
417 | case POST_INC: | |
418 | case POST_MODIFY: | |
419 | return nonzero_address_p (XEXP (x, 0)); | |
420 | ||
421 | case LO_SUM: | |
422 | return nonzero_address_p (XEXP (x, 1)); | |
423 | ||
424 | default: | |
425 | break; | |
426 | } | |
427 | ||
428 | /* If it isn't one of the case above, might be zero. */ | |
429 | return false; | |
430 | } | |
431 | ||
2617fe26 | 432 | /* Return 1 if X refers to a memory location whose address |
635aff97 | 433 | cannot be compared reliably with constant addresses, |
2617fe26 | 434 | or if X refers to a BLKmode memory object. |
ea087693 | 435 | FOR_ALIAS is nonzero if we are called from alias analysis; if it is |
436 | zero, we are slightly more conservative. */ | |
635aff97 | 437 | |
52d07779 | 438 | bool |
439 | rtx_addr_varies_p (const_rtx x, bool for_alias) | |
635aff97 | 440 | { |
19cb6b50 | 441 | enum rtx_code code; |
442 | int i; | |
443 | const char *fmt; | |
635aff97 | 444 | |
445 | if (x == 0) | |
446 | return 0; | |
447 | ||
448 | code = GET_CODE (x); | |
449 | if (code == MEM) | |
ea087693 | 450 | return GET_MODE (x) == BLKmode || rtx_varies_p (XEXP (x, 0), for_alias); |
635aff97 | 451 | |
452 | fmt = GET_RTX_FORMAT (code); | |
453 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
454 | if (fmt[i] == 'e') | |
cbea2709 | 455 | { |
ea087693 | 456 | if (rtx_addr_varies_p (XEXP (x, i), for_alias)) |
cbea2709 | 457 | return 1; |
458 | } | |
459 | else if (fmt[i] == 'E') | |
460 | { | |
461 | int j; | |
462 | for (j = 0; j < XVECLEN (x, i); j++) | |
ea087693 | 463 | if (rtx_addr_varies_p (XVECEXP (x, i, j), for_alias)) |
cbea2709 | 464 | return 1; |
465 | } | |
635aff97 | 466 | return 0; |
467 | } | |
468 | \f | |
cf7fb72d | 469 | /* Return the CALL in X if there is one. */ |
470 | ||
471 | rtx | |
472 | get_call_rtx_from (rtx x) | |
473 | { | |
474 | if (INSN_P (x)) | |
475 | x = PATTERN (x); | |
476 | if (GET_CODE (x) == PARALLEL) | |
477 | x = XVECEXP (x, 0, 0); | |
478 | if (GET_CODE (x) == SET) | |
479 | x = SET_SRC (x); | |
480 | if (GET_CODE (x) == CALL && MEM_P (XEXP (x, 0))) | |
481 | return x; | |
482 | return NULL_RTX; | |
483 | } | |
484 | \f | |
635aff97 | 485 | /* Return the value of the integer term in X, if one is apparent; |
486 | otherwise return 0. | |
487 | Only obvious integer terms are detected. | |
04641143 | 488 | This is used in cse.c with the `related_value' field. */ |
635aff97 | 489 | |
d3115c90 | 490 | HOST_WIDE_INT |
dd9b9fc5 | 491 | get_integer_term (const_rtx x) |
635aff97 | 492 | { |
493 | if (GET_CODE (x) == CONST) | |
494 | x = XEXP (x, 0); | |
495 | ||
496 | if (GET_CODE (x) == MINUS | |
971ba038 | 497 | && CONST_INT_P (XEXP (x, 1))) |
635aff97 | 498 | return - INTVAL (XEXP (x, 1)); |
499 | if (GET_CODE (x) == PLUS | |
971ba038 | 500 | && CONST_INT_P (XEXP (x, 1))) |
635aff97 | 501 | return INTVAL (XEXP (x, 1)); |
502 | return 0; | |
503 | } | |
504 | ||
505 | /* If X is a constant, return the value sans apparent integer term; | |
506 | otherwise return 0. | |
507 | Only obvious integer terms are detected. */ | |
508 | ||
509 | rtx | |
dd9b9fc5 | 510 | get_related_value (const_rtx x) |
635aff97 | 511 | { |
512 | if (GET_CODE (x) != CONST) | |
513 | return 0; | |
514 | x = XEXP (x, 0); | |
515 | if (GET_CODE (x) == PLUS | |
971ba038 | 516 | && CONST_INT_P (XEXP (x, 1))) |
635aff97 | 517 | return XEXP (x, 0); |
518 | else if (GET_CODE (x) == MINUS | |
971ba038 | 519 | && CONST_INT_P (XEXP (x, 1))) |
635aff97 | 520 | return XEXP (x, 0); |
521 | return 0; | |
522 | } | |
523 | \f | |
e0ab7256 | 524 | /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points |
525 | to somewhere in the same object or object_block as SYMBOL. */ | |
526 | ||
527 | bool | |
dd9b9fc5 | 528 | offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset) |
e0ab7256 | 529 | { |
530 | tree decl; | |
531 | ||
532 | if (GET_CODE (symbol) != SYMBOL_REF) | |
533 | return false; | |
534 | ||
535 | if (offset == 0) | |
536 | return true; | |
537 | ||
538 | if (offset > 0) | |
539 | { | |
540 | if (CONSTANT_POOL_ADDRESS_P (symbol) | |
541 | && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol))) | |
542 | return true; | |
543 | ||
544 | decl = SYMBOL_REF_DECL (symbol); | |
545 | if (decl && offset < int_size_in_bytes (TREE_TYPE (decl))) | |
546 | return true; | |
547 | } | |
548 | ||
549 | if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol) | |
550 | && SYMBOL_REF_BLOCK (symbol) | |
551 | && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0 | |
552 | && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol) | |
553 | < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size)) | |
554 | return true; | |
555 | ||
556 | return false; | |
557 | } | |
558 | ||
559 | /* Split X into a base and a constant offset, storing them in *BASE_OUT | |
560 | and *OFFSET_OUT respectively. */ | |
561 | ||
562 | void | |
563 | split_const (rtx x, rtx *base_out, rtx *offset_out) | |
564 | { | |
565 | if (GET_CODE (x) == CONST) | |
566 | { | |
567 | x = XEXP (x, 0); | |
971ba038 | 568 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
e0ab7256 | 569 | { |
570 | *base_out = XEXP (x, 0); | |
571 | *offset_out = XEXP (x, 1); | |
572 | return; | |
573 | } | |
574 | } | |
575 | *base_out = x; | |
576 | *offset_out = const0_rtx; | |
577 | } | |
578 | \f | |
40988080 | 579 | /* Return the number of places FIND appears within X. If COUNT_DEST is |
580 | zero, we do not count occurrences inside the destination of a SET. */ | |
581 | ||
582 | int | |
dd9b9fc5 | 583 | count_occurrences (const_rtx x, const_rtx find, int count_dest) |
40988080 | 584 | { |
585 | int i, j; | |
586 | enum rtx_code code; | |
587 | const char *format_ptr; | |
588 | int count; | |
589 | ||
590 | if (x == find) | |
591 | return 1; | |
592 | ||
593 | code = GET_CODE (x); | |
594 | ||
595 | switch (code) | |
596 | { | |
597 | case REG: | |
0349edce | 598 | CASE_CONST_ANY: |
40988080 | 599 | case SYMBOL_REF: |
600 | case CODE_LABEL: | |
601 | case PC: | |
602 | case CC0: | |
603 | return 0; | |
604 | ||
ac6a6c76 | 605 | case EXPR_LIST: |
606 | count = count_occurrences (XEXP (x, 0), find, count_dest); | |
607 | if (XEXP (x, 1)) | |
608 | count += count_occurrences (XEXP (x, 1), find, count_dest); | |
609 | return count; | |
48e1416a | 610 | |
40988080 | 611 | case MEM: |
e16ceb8e | 612 | if (MEM_P (find) && rtx_equal_p (x, find)) |
40988080 | 613 | return 1; |
614 | break; | |
615 | ||
616 | case SET: | |
617 | if (SET_DEST (x) == find && ! count_dest) | |
618 | return count_occurrences (SET_SRC (x), find, count_dest); | |
619 | break; | |
620 | ||
621 | default: | |
622 | break; | |
623 | } | |
624 | ||
625 | format_ptr = GET_RTX_FORMAT (code); | |
626 | count = 0; | |
627 | ||
628 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
629 | { | |
630 | switch (*format_ptr++) | |
631 | { | |
632 | case 'e': | |
633 | count += count_occurrences (XEXP (x, i), find, count_dest); | |
634 | break; | |
635 | ||
636 | case 'E': | |
637 | for (j = 0; j < XVECLEN (x, i); j++) | |
638 | count += count_occurrences (XVECEXP (x, i, j), find, count_dest); | |
639 | break; | |
640 | } | |
641 | } | |
642 | return count; | |
643 | } | |
3072d30e | 644 | |
0a98b6d9 | 645 | \f |
646 | /* Return TRUE if OP is a register or subreg of a register that | |
647 | holds an unsigned quantity. Otherwise, return FALSE. */ | |
648 | ||
649 | bool | |
650 | unsigned_reg_p (rtx op) | |
651 | { | |
652 | if (REG_P (op) | |
653 | && REG_EXPR (op) | |
654 | && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op)))) | |
655 | return true; | |
656 | ||
657 | if (GET_CODE (op) == SUBREG | |
658 | && SUBREG_PROMOTED_UNSIGNED_P (op)) | |
659 | return true; | |
660 | ||
661 | return false; | |
662 | } | |
663 | ||
40988080 | 664 | \f |
635aff97 | 665 | /* Nonzero if register REG appears somewhere within IN. |
666 | Also works if REG is not a register; in this case it checks | |
667 | for a subexpression of IN that is Lisp "equal" to REG. */ | |
668 | ||
669 | int | |
dd9b9fc5 | 670 | reg_mentioned_p (const_rtx reg, const_rtx in) |
635aff97 | 671 | { |
19cb6b50 | 672 | const char *fmt; |
673 | int i; | |
674 | enum rtx_code code; | |
635aff97 | 675 | |
676 | if (in == 0) | |
677 | return 0; | |
678 | ||
679 | if (reg == in) | |
680 | return 1; | |
681 | ||
682 | if (GET_CODE (in) == LABEL_REF) | |
683 | return reg == XEXP (in, 0); | |
684 | ||
685 | code = GET_CODE (in); | |
686 | ||
687 | switch (code) | |
688 | { | |
689 | /* Compare registers by number. */ | |
690 | case REG: | |
8ad4c111 | 691 | return REG_P (reg) && REGNO (in) == REGNO (reg); |
635aff97 | 692 | |
693 | /* These codes have no constituent expressions | |
694 | and are unique. */ | |
695 | case SCRATCH: | |
696 | case CC0: | |
697 | case PC: | |
698 | return 0; | |
699 | ||
0349edce | 700 | CASE_CONST_ANY: |
635aff97 | 701 | /* These are kept unique for a given value. */ |
702 | return 0; | |
2617fe26 | 703 | |
0dbd1c74 | 704 | default: |
705 | break; | |
635aff97 | 706 | } |
707 | ||
708 | if (GET_CODE (reg) == code && rtx_equal_p (reg, in)) | |
709 | return 1; | |
710 | ||
711 | fmt = GET_RTX_FORMAT (code); | |
712 | ||
713 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
714 | { | |
715 | if (fmt[i] == 'E') | |
716 | { | |
19cb6b50 | 717 | int j; |
635aff97 | 718 | for (j = XVECLEN (in, i) - 1; j >= 0; j--) |
719 | if (reg_mentioned_p (reg, XVECEXP (in, i, j))) | |
720 | return 1; | |
721 | } | |
722 | else if (fmt[i] == 'e' | |
723 | && reg_mentioned_p (reg, XEXP (in, i))) | |
724 | return 1; | |
725 | } | |
726 | return 0; | |
727 | } | |
728 | \f | |
729 | /* Return 1 if in between BEG and END, exclusive of BEG and END, there is | |
730 | no CODE_LABEL insn. */ | |
731 | ||
732 | int | |
dd9b9fc5 | 733 | no_labels_between_p (const_rtx beg, const_rtx end) |
635aff97 | 734 | { |
19cb6b50 | 735 | rtx p; |
62de2472 | 736 | if (beg == end) |
737 | return 0; | |
635aff97 | 738 | for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p)) |
6d7dc5b9 | 739 | if (LABEL_P (p)) |
635aff97 | 740 | return 0; |
741 | return 1; | |
742 | } | |
743 | ||
744 | /* Nonzero if register REG is used in an insn between | |
745 | FROM_INSN and TO_INSN (exclusive of those two). */ | |
746 | ||
747 | int | |
dd9b9fc5 | 748 | reg_used_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn) |
635aff97 | 749 | { |
19cb6b50 | 750 | rtx insn; |
635aff97 | 751 | |
752 | if (from_insn == to_insn) | |
753 | return 0; | |
754 | ||
755 | for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) | |
9845d120 | 756 | if (NONDEBUG_INSN_P (insn) |
0c7201ca | 757 | && (reg_overlap_mentioned_p (reg, PATTERN (insn)) |
ecbd66eb | 758 | || (CALL_P (insn) && find_reg_fusage (insn, USE, reg)))) |
635aff97 | 759 | return 1; |
760 | return 0; | |
761 | } | |
762 | \f | |
763 | /* Nonzero if the old value of X, a register, is referenced in BODY. If X | |
764 | is entirely replaced by a new value and the only use is as a SET_DEST, | |
765 | we do not consider it a reference. */ | |
766 | ||
767 | int | |
dd9b9fc5 | 768 | reg_referenced_p (const_rtx x, const_rtx body) |
635aff97 | 769 | { |
770 | int i; | |
771 | ||
772 | switch (GET_CODE (body)) | |
773 | { | |
774 | case SET: | |
775 | if (reg_overlap_mentioned_p (x, SET_SRC (body))) | |
776 | return 1; | |
777 | ||
778 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
779 | of a REG that occupies all of the REG, the insn references X if | |
780 | it is mentioned in the destination. */ | |
781 | if (GET_CODE (SET_DEST (body)) != CC0 | |
782 | && GET_CODE (SET_DEST (body)) != PC | |
8ad4c111 | 783 | && !REG_P (SET_DEST (body)) |
635aff97 | 784 | && ! (GET_CODE (SET_DEST (body)) == SUBREG |
8ad4c111 | 785 | && REG_P (SUBREG_REG (SET_DEST (body))) |
635aff97 | 786 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body)))) |
787 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
788 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body))) | |
789 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
790 | && reg_overlap_mentioned_p (x, SET_DEST (body))) | |
791 | return 1; | |
0dbd1c74 | 792 | return 0; |
635aff97 | 793 | |
794 | case ASM_OPERANDS: | |
795 | for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--) | |
796 | if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i))) | |
797 | return 1; | |
0dbd1c74 | 798 | return 0; |
635aff97 | 799 | |
800 | case CALL: | |
801 | case USE: | |
155b05dc | 802 | case IF_THEN_ELSE: |
635aff97 | 803 | return reg_overlap_mentioned_p (x, body); |
804 | ||
805 | case TRAP_IF: | |
806 | return reg_overlap_mentioned_p (x, TRAP_CONDITION (body)); | |
807 | ||
9f449ed6 | 808 | case PREFETCH: |
809 | return reg_overlap_mentioned_p (x, XEXP (body, 0)); | |
810 | ||
3384a30e | 811 | case UNSPEC: |
812 | case UNSPEC_VOLATILE: | |
57d44d09 | 813 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) |
814 | if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i))) | |
815 | return 1; | |
816 | return 0; | |
817 | ||
635aff97 | 818 | case PARALLEL: |
819 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
820 | if (reg_referenced_p (x, XVECEXP (body, 0, i))) | |
821 | return 1; | |
0dbd1c74 | 822 | return 0; |
2617fe26 | 823 | |
cccfd0f9 | 824 | case CLOBBER: |
e16ceb8e | 825 | if (MEM_P (XEXP (body, 0))) |
cccfd0f9 | 826 | if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0))) |
827 | return 1; | |
828 | return 0; | |
829 | ||
406034fa | 830 | case COND_EXEC: |
831 | if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body))) | |
832 | return 1; | |
833 | return reg_referenced_p (x, COND_EXEC_CODE (body)); | |
834 | ||
0dbd1c74 | 835 | default: |
836 | return 0; | |
635aff97 | 837 | } |
635aff97 | 838 | } |
635aff97 | 839 | \f |
840 | /* Nonzero if register REG is set or clobbered in an insn between | |
841 | FROM_INSN and TO_INSN (exclusive of those two). */ | |
842 | ||
843 | int | |
7ecb5bb2 | 844 | reg_set_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn) |
635aff97 | 845 | { |
7ecb5bb2 | 846 | const_rtx insn; |
635aff97 | 847 | |
848 | if (from_insn == to_insn) | |
849 | return 0; | |
850 | ||
851 | for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) | |
9204e736 | 852 | if (INSN_P (insn) && reg_set_p (reg, insn)) |
635aff97 | 853 | return 1; |
854 | return 0; | |
855 | } | |
856 | ||
857 | /* Internals of reg_set_between_p. */ | |
635aff97 | 858 | int |
7ecb5bb2 | 859 | reg_set_p (const_rtx reg, const_rtx insn) |
635aff97 | 860 | { |
635aff97 | 861 | /* We can be passed an insn or part of one. If we are passed an insn, |
862 | check if a side-effect of the insn clobbers REG. */ | |
805e22b2 | 863 | if (INSN_P (insn) |
864 | && (FIND_REG_INC_NOTE (insn, reg) | |
6d7dc5b9 | 865 | || (CALL_P (insn) |
8ad4c111 | 866 | && ((REG_P (reg) |
3c71a5cc | 867 | && REGNO (reg) < FIRST_PSEUDO_REGISTER |
20128b13 | 868 | && overlaps_hard_reg_set_p (regs_invalidated_by_call, |
869 | GET_MODE (reg), REGNO (reg))) | |
e16ceb8e | 870 | || MEM_P (reg) |
805e22b2 | 871 | || find_reg_fusage (insn, CLOBBER, reg))))) |
872 | return 1; | |
635aff97 | 873 | |
b7995d54 | 874 | return set_of (reg, insn) != NULL_RTX; |
635aff97 | 875 | } |
876 | ||
877 | /* Similar to reg_set_between_p, but check all registers in X. Return 0 | |
878 | only if none of them are modified between START and END. Return 1 if | |
f0b5f617 | 879 | X contains a MEM; this routine does use memory aliasing. */ |
635aff97 | 880 | |
881 | int | |
5493cb9a | 882 | modified_between_p (const_rtx x, const_rtx start, const_rtx end) |
635aff97 | 883 | { |
5493cb9a | 884 | const enum rtx_code code = GET_CODE (x); |
d2ca078f | 885 | const char *fmt; |
2c18b47c | 886 | int i, j; |
c7bf7428 | 887 | rtx insn; |
888 | ||
889 | if (start == end) | |
890 | return 0; | |
635aff97 | 891 | |
892 | switch (code) | |
893 | { | |
0349edce | 894 | CASE_CONST_ANY: |
635aff97 | 895 | case CONST: |
896 | case SYMBOL_REF: | |
897 | case LABEL_REF: | |
898 | return 0; | |
899 | ||
900 | case PC: | |
901 | case CC0: | |
902 | return 1; | |
903 | ||
904 | case MEM: | |
c7bf7428 | 905 | if (modified_between_p (XEXP (x, 0), start, end)) |
635aff97 | 906 | return 1; |
bf0ee60a | 907 | if (MEM_READONLY_P (x)) |
908 | return 0; | |
c7bf7428 | 909 | for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn)) |
910 | if (memory_modified_in_insn_p (x, insn)) | |
911 | return 1; | |
912 | return 0; | |
635aff97 | 913 | break; |
914 | ||
915 | case REG: | |
916 | return reg_set_between_p (x, start, end); | |
2617fe26 | 917 | |
0dbd1c74 | 918 | default: |
919 | break; | |
635aff97 | 920 | } |
921 | ||
922 | fmt = GET_RTX_FORMAT (code); | |
923 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2c18b47c | 924 | { |
925 | if (fmt[i] == 'e' && modified_between_p (XEXP (x, i), start, end)) | |
926 | return 1; | |
927 | ||
1bd8ca86 | 928 | else if (fmt[i] == 'E') |
2c18b47c | 929 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
930 | if (modified_between_p (XVECEXP (x, i, j), start, end)) | |
931 | return 1; | |
932 | } | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
937 | /* Similar to reg_set_p, but check all registers in X. Return 0 only if none | |
938 | of them are modified in INSN. Return 1 if X contains a MEM; this routine | |
c7bf7428 | 939 | does use memory aliasing. */ |
2c18b47c | 940 | |
941 | int | |
5493cb9a | 942 | modified_in_p (const_rtx x, const_rtx insn) |
2c18b47c | 943 | { |
5493cb9a | 944 | const enum rtx_code code = GET_CODE (x); |
d2ca078f | 945 | const char *fmt; |
2c18b47c | 946 | int i, j; |
947 | ||
948 | switch (code) | |
949 | { | |
0349edce | 950 | CASE_CONST_ANY: |
2c18b47c | 951 | case CONST: |
952 | case SYMBOL_REF: | |
953 | case LABEL_REF: | |
954 | return 0; | |
955 | ||
956 | case PC: | |
957 | case CC0: | |
635aff97 | 958 | return 1; |
959 | ||
2c18b47c | 960 | case MEM: |
c7bf7428 | 961 | if (modified_in_p (XEXP (x, 0), insn)) |
2c18b47c | 962 | return 1; |
bf0ee60a | 963 | if (MEM_READONLY_P (x)) |
964 | return 0; | |
c7bf7428 | 965 | if (memory_modified_in_insn_p (x, insn)) |
966 | return 1; | |
967 | return 0; | |
2c18b47c | 968 | break; |
969 | ||
970 | case REG: | |
971 | return reg_set_p (x, insn); | |
0dbd1c74 | 972 | |
973 | default: | |
974 | break; | |
2c18b47c | 975 | } |
976 | ||
977 | fmt = GET_RTX_FORMAT (code); | |
978 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
979 | { | |
980 | if (fmt[i] == 'e' && modified_in_p (XEXP (x, i), insn)) | |
981 | return 1; | |
982 | ||
1bd8ca86 | 983 | else if (fmt[i] == 'E') |
2c18b47c | 984 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
985 | if (modified_in_p (XVECEXP (x, i, j), insn)) | |
986 | return 1; | |
987 | } | |
988 | ||
635aff97 | 989 | return 0; |
990 | } | |
991 | \f | |
b7995d54 | 992 | /* Helper function for set_of. */ |
993 | struct set_of_data | |
994 | { | |
81a410b1 | 995 | const_rtx found; |
996 | const_rtx pat; | |
b7995d54 | 997 | }; |
998 | ||
999 | static void | |
81a410b1 | 1000 | set_of_1 (rtx x, const_rtx pat, void *data1) |
b7995d54 | 1001 | { |
81a410b1 | 1002 | struct set_of_data *const data = (struct set_of_data *) (data1); |
1003 | if (rtx_equal_p (x, data->pat) | |
1004 | || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x))) | |
1005 | data->found = pat; | |
b7995d54 | 1006 | } |
1007 | ||
1008 | /* Give an INSN, return a SET or CLOBBER expression that does modify PAT | |
4a82352a | 1009 | (either directly or via STRICT_LOW_PART and similar modifiers). */ |
81a410b1 | 1010 | const_rtx |
1011 | set_of (const_rtx pat, const_rtx insn) | |
b7995d54 | 1012 | { |
1013 | struct set_of_data data; | |
1014 | data.found = NULL_RTX; | |
1015 | data.pat = pat; | |
1016 | note_stores (INSN_P (insn) ? PATTERN (insn) : insn, set_of_1, &data); | |
1017 | return data.found; | |
1018 | } | |
effd1640 | 1019 | |
1020 | /* This function, called through note_stores, collects sets and | |
1021 | clobbers of hard registers in a HARD_REG_SET, which is pointed to | |
1022 | by DATA. */ | |
1023 | void | |
1024 | record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) | |
1025 | { | |
1026 | HARD_REG_SET *pset = (HARD_REG_SET *)data; | |
1027 | if (REG_P (x) && HARD_REGISTER_P (x)) | |
1028 | add_to_hard_reg_set (pset, GET_MODE (x), REGNO (x)); | |
1029 | } | |
1030 | ||
1031 | /* Examine INSN, and compute the set of hard registers written by it. | |
1032 | Store it in *PSET. Should only be called after reload. */ | |
1033 | void | |
1034 | find_all_hard_reg_sets (const_rtx insn, HARD_REG_SET *pset) | |
1035 | { | |
1036 | rtx link; | |
1037 | ||
1038 | CLEAR_HARD_REG_SET (*pset); | |
1039 | note_stores (PATTERN (insn), record_hard_reg_sets, pset); | |
1040 | if (CALL_P (insn)) | |
1041 | IOR_HARD_REG_SET (*pset, call_used_reg_set); | |
1042 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1043 | if (REG_NOTE_KIND (link) == REG_INC) | |
1044 | record_hard_reg_sets (XEXP (link, 0), NULL, pset); | |
1045 | } | |
1046 | ||
1047 | /* A for_each_rtx subroutine of record_hard_reg_uses. */ | |
1048 | static int | |
1049 | record_hard_reg_uses_1 (rtx *px, void *data) | |
1050 | { | |
1051 | rtx x = *px; | |
1052 | HARD_REG_SET *pused = (HARD_REG_SET *)data; | |
1053 | ||
1054 | if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1055 | { | |
1056 | int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)]; | |
1057 | while (nregs-- > 0) | |
1058 | SET_HARD_REG_BIT (*pused, REGNO (x) + nregs); | |
1059 | } | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | /* Like record_hard_reg_sets, but called through note_uses. */ | |
1064 | void | |
1065 | record_hard_reg_uses (rtx *px, void *data) | |
1066 | { | |
1067 | for_each_rtx (px, record_hard_reg_uses_1, data); | |
1068 | } | |
b7995d54 | 1069 | \f |
635aff97 | 1070 | /* Given an INSN, return a SET expression if this insn has only a single SET. |
1071 | It may also have CLOBBERs, USEs, or SET whose output | |
1072 | will not be used, which we ignore. */ | |
1073 | ||
1074 | rtx | |
dd9b9fc5 | 1075 | single_set_2 (const_rtx insn, const_rtx pat) |
635aff97 | 1076 | { |
b6590daa | 1077 | rtx set = NULL; |
1078 | int set_verified = 1; | |
635aff97 | 1079 | int i; |
b6590daa | 1080 | |
6531eca9 | 1081 | if (GET_CODE (pat) == PARALLEL) |
635aff97 | 1082 | { |
b6590daa | 1083 | for (i = 0; i < XVECLEN (pat, 0); i++) |
6531eca9 | 1084 | { |
b6590daa | 1085 | rtx sub = XVECEXP (pat, 0, i); |
1086 | switch (GET_CODE (sub)) | |
1087 | { | |
1088 | case USE: | |
1089 | case CLOBBER: | |
1090 | break; | |
1091 | ||
1092 | case SET: | |
1093 | /* We can consider insns having multiple sets, where all | |
1094 | but one are dead as single set insns. In common case | |
1095 | only single set is present in the pattern so we want | |
dd5b4b36 | 1096 | to avoid checking for REG_UNUSED notes unless necessary. |
b6590daa | 1097 | |
1098 | When we reach set first time, we just expect this is | |
1099 | the single set we are looking for and only when more | |
1100 | sets are found in the insn, we check them. */ | |
1101 | if (!set_verified) | |
1102 | { | |
1103 | if (find_reg_note (insn, REG_UNUSED, SET_DEST (set)) | |
1104 | && !side_effects_p (set)) | |
1105 | set = NULL; | |
1106 | else | |
1107 | set_verified = 1; | |
1108 | } | |
1109 | if (!set) | |
1110 | set = sub, set_verified = 0; | |
1111 | else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub)) | |
1112 | || side_effects_p (sub)) | |
1113 | return NULL_RTX; | |
1114 | break; | |
1115 | ||
1116 | default: | |
1117 | return NULL_RTX; | |
1118 | } | |
93127143 | 1119 | } |
635aff97 | 1120 | } |
b6590daa | 1121 | return set; |
635aff97 | 1122 | } |
e6cae665 | 1123 | |
1124 | /* Given an INSN, return nonzero if it has more than one SET, else return | |
1125 | zero. */ | |
1126 | ||
21b510d8 | 1127 | int |
dd9b9fc5 | 1128 | multiple_sets (const_rtx insn) |
e6cae665 | 1129 | { |
2c641110 | 1130 | int found; |
e6cae665 | 1131 | int i; |
2617fe26 | 1132 | |
e6cae665 | 1133 | /* INSN must be an insn. */ |
9204e736 | 1134 | if (! INSN_P (insn)) |
e6cae665 | 1135 | return 0; |
1136 | ||
1137 | /* Only a PARALLEL can have multiple SETs. */ | |
1138 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
1139 | { | |
1140 | for (i = 0, found = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
1141 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) | |
1142 | { | |
1143 | /* If we have already found a SET, then return now. */ | |
1144 | if (found) | |
1145 | return 1; | |
1146 | else | |
1147 | found = 1; | |
1148 | } | |
1149 | } | |
2617fe26 | 1150 | |
e6cae665 | 1151 | /* Either zero or one SET. */ |
1152 | return 0; | |
1153 | } | |
635aff97 | 1154 | \f |
c955554c | 1155 | /* Return nonzero if the destination of SET equals the source |
1156 | and there are no side effects. */ | |
1157 | ||
1158 | int | |
dd9b9fc5 | 1159 | set_noop_p (const_rtx set) |
c955554c | 1160 | { |
1161 | rtx src = SET_SRC (set); | |
1162 | rtx dst = SET_DEST (set); | |
1163 | ||
675b92cc | 1164 | if (dst == pc_rtx && src == pc_rtx) |
1165 | return 1; | |
1166 | ||
e16ceb8e | 1167 | if (MEM_P (dst) && MEM_P (src)) |
53fffe66 | 1168 | return rtx_equal_p (dst, src) && !side_effects_p (dst); |
1169 | ||
476d094d | 1170 | if (GET_CODE (dst) == ZERO_EXTRACT) |
c955554c | 1171 | return rtx_equal_p (XEXP (dst, 0), src) |
53fffe66 | 1172 | && ! BYTES_BIG_ENDIAN && XEXP (dst, 2) == const0_rtx |
1173 | && !side_effects_p (src); | |
c955554c | 1174 | |
1175 | if (GET_CODE (dst) == STRICT_LOW_PART) | |
1176 | dst = XEXP (dst, 0); | |
1177 | ||
1178 | if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG) | |
1179 | { | |
1180 | if (SUBREG_BYTE (src) != SUBREG_BYTE (dst)) | |
1181 | return 0; | |
1182 | src = SUBREG_REG (src); | |
1183 | dst = SUBREG_REG (dst); | |
1184 | } | |
1185 | ||
8ad4c111 | 1186 | return (REG_P (src) && REG_P (dst) |
c955554c | 1187 | && REGNO (src) == REGNO (dst)); |
1188 | } | |
b08cd584 | 1189 | \f |
1190 | /* Return nonzero if an insn consists only of SETs, each of which only sets a | |
1191 | value to itself. */ | |
1192 | ||
1193 | int | |
b7bf20db | 1194 | noop_move_p (const_rtx insn) |
b08cd584 | 1195 | { |
1196 | rtx pat = PATTERN (insn); | |
1197 | ||
1805c35c | 1198 | if (INSN_CODE (insn) == NOOP_MOVE_INSN_CODE) |
1199 | return 1; | |
1200 | ||
b08cd584 | 1201 | /* Insns carrying these notes are useful later on. */ |
1202 | if (find_reg_note (insn, REG_EQUAL, NULL_RTX)) | |
1203 | return 0; | |
1204 | ||
1205 | if (GET_CODE (pat) == SET && set_noop_p (pat)) | |
1206 | return 1; | |
1207 | ||
1208 | if (GET_CODE (pat) == PARALLEL) | |
1209 | { | |
1210 | int i; | |
1211 | /* If nothing but SETs of registers to themselves, | |
1212 | this insn can also be deleted. */ | |
1213 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1214 | { | |
1215 | rtx tem = XVECEXP (pat, 0, i); | |
1216 | ||
1217 | if (GET_CODE (tem) == USE | |
1218 | || GET_CODE (tem) == CLOBBER) | |
1219 | continue; | |
1220 | ||
1221 | if (GET_CODE (tem) != SET || ! set_noop_p (tem)) | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | return 1; | |
1226 | } | |
1227 | return 0; | |
1228 | } | |
1229 | \f | |
c955554c | 1230 | |
5c1a1b6c | 1231 | /* Return the last thing that X was assigned from before *PINSN. If VALID_TO |
1232 | is not NULL_RTX then verify that the object is not modified up to VALID_TO. | |
1233 | If the object was modified, if we hit a partial assignment to X, or hit a | |
1234 | CODE_LABEL first, return X. If we found an assignment, update *PINSN to | |
1235 | point to it. ALLOW_HWREG is set to 1 if hardware registers are allowed to | |
1236 | be the src. */ | |
635aff97 | 1237 | |
1238 | rtx | |
3ad4992f | 1239 | find_last_value (rtx x, rtx *pinsn, rtx valid_to, int allow_hwreg) |
635aff97 | 1240 | { |
1241 | rtx p; | |
1242 | ||
6d7dc5b9 | 1243 | for (p = PREV_INSN (*pinsn); p && !LABEL_P (p); |
635aff97 | 1244 | p = PREV_INSN (p)) |
9204e736 | 1245 | if (INSN_P (p)) |
635aff97 | 1246 | { |
1247 | rtx set = single_set (p); | |
d3115c90 | 1248 | rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); |
635aff97 | 1249 | |
1250 | if (set && rtx_equal_p (x, SET_DEST (set))) | |
1251 | { | |
1252 | rtx src = SET_SRC (set); | |
1253 | ||
1254 | if (note && GET_CODE (XEXP (note, 0)) != EXPR_LIST) | |
1255 | src = XEXP (note, 0); | |
1256 | ||
5c1a1b6c | 1257 | if ((valid_to == NULL_RTX |
1258 | || ! modified_between_p (src, PREV_INSN (p), valid_to)) | |
635aff97 | 1259 | /* Reject hard registers because we don't usually want |
1260 | to use them; we'd rather use a pseudo. */ | |
8ad4c111 | 1261 | && (! (REG_P (src) |
e91c8aa9 | 1262 | && REGNO (src) < FIRST_PSEUDO_REGISTER) || allow_hwreg)) |
635aff97 | 1263 | { |
1264 | *pinsn = p; | |
1265 | return src; | |
1266 | } | |
1267 | } | |
2617fe26 | 1268 | |
635aff97 | 1269 | /* If set in non-simple way, we don't have a value. */ |
1270 | if (reg_set_p (x, p)) | |
1271 | break; | |
1272 | } | |
1273 | ||
1274 | return x; | |
2617fe26 | 1275 | } |
635aff97 | 1276 | \f |
1277 | /* Return nonzero if register in range [REGNO, ENDREGNO) | |
1278 | appears either explicitly or implicitly in X | |
1279 | other than being stored into. | |
1280 | ||
1281 | References contained within the substructure at LOC do not count. | |
1282 | LOC may be zero, meaning don't ignore anything. */ | |
1283 | ||
1284 | int | |
dd9b9fc5 | 1285 | refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x, |
3ad4992f | 1286 | rtx *loc) |
635aff97 | 1287 | { |
02e7a332 | 1288 | int i; |
1289 | unsigned int x_regno; | |
1290 | RTX_CODE code; | |
1291 | const char *fmt; | |
635aff97 | 1292 | |
1293 | repeat: | |
1294 | /* The contents of a REG_NONNEG note is always zero, so we must come here | |
1295 | upon repeat in case the last REG_NOTE is a REG_NONNEG note. */ | |
1296 | if (x == 0) | |
1297 | return 0; | |
1298 | ||
1299 | code = GET_CODE (x); | |
1300 | ||
1301 | switch (code) | |
1302 | { | |
1303 | case REG: | |
02e7a332 | 1304 | x_regno = REGNO (x); |
2c18b47c | 1305 | |
1306 | /* If we modifying the stack, frame, or argument pointer, it will | |
1307 | clobber a virtual register. In fact, we could be more precise, | |
1308 | but it isn't worth it. */ | |
02e7a332 | 1309 | if ((x_regno == STACK_POINTER_REGNUM |
2c18b47c | 1310 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
02e7a332 | 1311 | || x_regno == ARG_POINTER_REGNUM |
2c18b47c | 1312 | #endif |
02e7a332 | 1313 | || x_regno == FRAME_POINTER_REGNUM) |
2c18b47c | 1314 | && regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_REGISTER) |
1315 | return 1; | |
1316 | ||
a2c6f0b7 | 1317 | return endregno > x_regno && regno < END_REGNO (x); |
635aff97 | 1318 | |
1319 | case SUBREG: | |
1320 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
1321 | registers are being modified. Otherwise, handle normally. */ | |
8ad4c111 | 1322 | if (REG_P (SUBREG_REG (x)) |
635aff97 | 1323 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) |
1324 | { | |
701e46d0 | 1325 | unsigned int inner_regno = subreg_regno (x); |
02e7a332 | 1326 | unsigned int inner_endregno |
aee171c8 | 1327 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER |
fe2ebfc8 | 1328 | ? subreg_nregs (x) : 1); |
635aff97 | 1329 | |
1330 | return endregno > inner_regno && regno < inner_endregno; | |
1331 | } | |
1332 | break; | |
1333 | ||
1334 | case CLOBBER: | |
1335 | case SET: | |
1336 | if (&SET_DEST (x) != loc | |
1337 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
1338 | a pseudo but not for hard registers since we can | |
1339 | treat each word individually. */ | |
1340 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
1341 | && loc != &SUBREG_REG (SET_DEST (x)) | |
8ad4c111 | 1342 | && REG_P (SUBREG_REG (SET_DEST (x))) |
635aff97 | 1343 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER |
1344 | && refers_to_regno_p (regno, endregno, | |
1345 | SUBREG_REG (SET_DEST (x)), loc)) | |
8ad4c111 | 1346 | || (!REG_P (SET_DEST (x)) |
635aff97 | 1347 | && refers_to_regno_p (regno, endregno, SET_DEST (x), loc)))) |
1348 | return 1; | |
1349 | ||
1350 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
1351 | return 0; | |
1352 | x = SET_SRC (x); | |
1353 | goto repeat; | |
0dbd1c74 | 1354 | |
1355 | default: | |
1356 | break; | |
635aff97 | 1357 | } |
1358 | ||
1359 | /* X does not match, so try its subexpressions. */ | |
1360 | ||
1361 | fmt = GET_RTX_FORMAT (code); | |
1362 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1363 | { | |
1364 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
1365 | { | |
1366 | if (i == 0) | |
1367 | { | |
1368 | x = XEXP (x, 0); | |
1369 | goto repeat; | |
1370 | } | |
1371 | else | |
1372 | if (refers_to_regno_p (regno, endregno, XEXP (x, i), loc)) | |
1373 | return 1; | |
1374 | } | |
1375 | else if (fmt[i] == 'E') | |
1376 | { | |
19cb6b50 | 1377 | int j; |
ea0041f4 | 1378 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
635aff97 | 1379 | if (loc != &XVECEXP (x, i, j) |
1380 | && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j), loc)) | |
1381 | return 1; | |
1382 | } | |
1383 | } | |
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
1388 | we check if any register number in X conflicts with the relevant register | |
1389 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
1390 | contains a MEM (we don't bother checking for memory addresses that can't | |
1391 | conflict because we expect this to be a rare case. */ | |
1392 | ||
1393 | int | |
dd9b9fc5 | 1394 | reg_overlap_mentioned_p (const_rtx x, const_rtx in) |
635aff97 | 1395 | { |
02e7a332 | 1396 | unsigned int regno, endregno; |
635aff97 | 1397 | |
2f3f2ddf | 1398 | /* If either argument is a constant, then modifying X can not |
1399 | affect IN. Here we look at IN, we can profitably combine | |
1400 | CONSTANT_P (x) with the switch statement below. */ | |
1401 | if (CONSTANT_P (in)) | |
8eb7d6fc | 1402 | return 0; |
406034fa | 1403 | |
2f3f2ddf | 1404 | recurse: |
406034fa | 1405 | switch (GET_CODE (x)) |
635aff97 | 1406 | { |
2f3f2ddf | 1407 | case STRICT_LOW_PART: |
1408 | case ZERO_EXTRACT: | |
1409 | case SIGN_EXTRACT: | |
1410 | /* Overly conservative. */ | |
1411 | x = XEXP (x, 0); | |
1412 | goto recurse; | |
1413 | ||
406034fa | 1414 | case SUBREG: |
635aff97 | 1415 | regno = REGNO (SUBREG_REG (x)); |
1416 | if (regno < FIRST_PSEUDO_REGISTER) | |
701e46d0 | 1417 | regno = subreg_regno (x); |
fe2ebfc8 | 1418 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
1419 | ? subreg_nregs (x) : 1); | |
406034fa | 1420 | goto do_reg; |
635aff97 | 1421 | |
406034fa | 1422 | case REG: |
1423 | regno = REGNO (x); | |
a2c6f0b7 | 1424 | endregno = END_REGNO (x); |
fe2ebfc8 | 1425 | do_reg: |
337d789b | 1426 | return refers_to_regno_p (regno, endregno, in, (rtx*) 0); |
635aff97 | 1427 | |
406034fa | 1428 | case MEM: |
1429 | { | |
1430 | const char *fmt; | |
1431 | int i; | |
635aff97 | 1432 | |
e16ceb8e | 1433 | if (MEM_P (in)) |
635aff97 | 1434 | return 1; |
1435 | ||
406034fa | 1436 | fmt = GET_RTX_FORMAT (GET_CODE (in)); |
1437 | for (i = GET_RTX_LENGTH (GET_CODE (in)) - 1; i >= 0; i--) | |
bc99e194 | 1438 | if (fmt[i] == 'e') |
1439 | { | |
1440 | if (reg_overlap_mentioned_p (x, XEXP (in, i))) | |
1441 | return 1; | |
1442 | } | |
1443 | else if (fmt[i] == 'E') | |
1444 | { | |
1445 | int j; | |
1446 | for (j = XVECLEN (in, i) - 1; j >= 0; --j) | |
1447 | if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j))) | |
1448 | return 1; | |
1449 | } | |
3a1b2351 | 1450 | |
406034fa | 1451 | return 0; |
1452 | } | |
1453 | ||
1454 | case SCRATCH: | |
1455 | case PC: | |
1456 | case CC0: | |
1457 | return reg_mentioned_p (x, in); | |
1458 | ||
1459 | case PARALLEL: | |
e291e4ee | 1460 | { |
216b2683 | 1461 | int i; |
e291e4ee | 1462 | |
1463 | /* If any register in here refers to it we return true. */ | |
4b303227 | 1464 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) |
1465 | if (XEXP (XVECEXP (x, 0, i), 0) != 0 | |
1466 | && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0), in)) | |
2f3f2ddf | 1467 | return 1; |
4b303227 | 1468 | return 0; |
e291e4ee | 1469 | } |
635aff97 | 1470 | |
406034fa | 1471 | default: |
04e579b6 | 1472 | gcc_assert (CONSTANT_P (x)); |
2f3f2ddf | 1473 | return 0; |
1474 | } | |
635aff97 | 1475 | } |
1476 | \f | |
635aff97 | 1477 | /* Call FUN on each register or MEM that is stored into or clobbered by X. |
02a63053 | 1478 | (X would be the pattern of an insn). DATA is an arbitrary pointer, |
1479 | ignored by note_stores, but passed to FUN. | |
1480 | ||
1481 | FUN receives three arguments: | |
1482 | 1. the REG, MEM, CC0 or PC being stored in or clobbered, | |
1483 | 2. the SET or CLOBBER rtx that does the store, | |
1484 | 3. the pointer DATA provided to note_stores. | |
635aff97 | 1485 | |
1486 | If the item being stored in or clobbered is a SUBREG of a hard register, | |
1487 | the SUBREG will be passed. */ | |
2617fe26 | 1488 | |
635aff97 | 1489 | void |
81a410b1 | 1490 | note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data) |
635aff97 | 1491 | { |
a80f1c6c | 1492 | int i; |
216b2683 | 1493 | |
a80f1c6c | 1494 | if (GET_CODE (x) == COND_EXEC) |
1495 | x = COND_EXEC_CODE (x); | |
216b2683 | 1496 | |
a80f1c6c | 1497 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) |
1498 | { | |
1499 | rtx dest = SET_DEST (x); | |
1500 | ||
1501 | while ((GET_CODE (dest) == SUBREG | |
1502 | && (!REG_P (SUBREG_REG (dest)) | |
1503 | || REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER)) | |
1504 | || GET_CODE (dest) == ZERO_EXTRACT | |
1505 | || GET_CODE (dest) == STRICT_LOW_PART) | |
1506 | dest = XEXP (dest, 0); | |
1507 | ||
1508 | /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions, | |
1509 | each of whose first operand is a register. */ | |
1510 | if (GET_CODE (dest) == PARALLEL) | |
1511 | { | |
1512 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
1513 | if (XEXP (XVECEXP (dest, 0, i), 0) != 0) | |
1514 | (*fun) (XEXP (XVECEXP (dest, 0, i), 0), x, data); | |
1515 | } | |
1516 | else | |
1517 | (*fun) (dest, x, data); | |
1518 | } | |
02e7a332 | 1519 | |
a80f1c6c | 1520 | else if (GET_CODE (x) == PARALLEL) |
1521 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
1522 | note_stores (XVECEXP (x, 0, i), fun, data); | |
1523 | } | |
635aff97 | 1524 | \f |
99b86c05 | 1525 | /* Like notes_stores, but call FUN for each expression that is being |
1526 | referenced in PBODY, a pointer to the PATTERN of an insn. We only call | |
1527 | FUN for each expression, not any interior subexpressions. FUN receives a | |
1528 | pointer to the expression and the DATA passed to this function. | |
1529 | ||
1530 | Note that this is not quite the same test as that done in reg_referenced_p | |
1531 | since that considers something as being referenced if it is being | |
1532 | partially set, while we do not. */ | |
1533 | ||
1534 | void | |
3ad4992f | 1535 | note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data) |
99b86c05 | 1536 | { |
1537 | rtx body = *pbody; | |
1538 | int i; | |
1539 | ||
1540 | switch (GET_CODE (body)) | |
1541 | { | |
1542 | case COND_EXEC: | |
1543 | (*fun) (&COND_EXEC_TEST (body), data); | |
1544 | note_uses (&COND_EXEC_CODE (body), fun, data); | |
1545 | return; | |
1546 | ||
1547 | case PARALLEL: | |
1548 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
1549 | note_uses (&XVECEXP (body, 0, i), fun, data); | |
1550 | return; | |
1551 | ||
48df5a7f | 1552 | case SEQUENCE: |
1553 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
1554 | note_uses (&PATTERN (XVECEXP (body, 0, i)), fun, data); | |
1555 | return; | |
1556 | ||
99b86c05 | 1557 | case USE: |
1558 | (*fun) (&XEXP (body, 0), data); | |
1559 | return; | |
1560 | ||
1561 | case ASM_OPERANDS: | |
1562 | for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--) | |
1563 | (*fun) (&ASM_OPERANDS_INPUT (body, i), data); | |
1564 | return; | |
1565 | ||
1566 | case TRAP_IF: | |
1567 | (*fun) (&TRAP_CONDITION (body), data); | |
1568 | return; | |
1569 | ||
9f449ed6 | 1570 | case PREFETCH: |
1571 | (*fun) (&XEXP (body, 0), data); | |
1572 | return; | |
1573 | ||
99b86c05 | 1574 | case UNSPEC: |
1575 | case UNSPEC_VOLATILE: | |
1576 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
1577 | (*fun) (&XVECEXP (body, 0, i), data); | |
1578 | return; | |
1579 | ||
1580 | case CLOBBER: | |
e16ceb8e | 1581 | if (MEM_P (XEXP (body, 0))) |
99b86c05 | 1582 | (*fun) (&XEXP (XEXP (body, 0), 0), data); |
1583 | return; | |
1584 | ||
1585 | case SET: | |
1586 | { | |
1587 | rtx dest = SET_DEST (body); | |
1588 | ||
1589 | /* For sets we replace everything in source plus registers in memory | |
1590 | expression in store and operands of a ZERO_EXTRACT. */ | |
1591 | (*fun) (&SET_SRC (body), data); | |
1592 | ||
1593 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
1594 | { | |
1595 | (*fun) (&XEXP (dest, 1), data); | |
1596 | (*fun) (&XEXP (dest, 2), data); | |
1597 | } | |
1598 | ||
1599 | while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART) | |
1600 | dest = XEXP (dest, 0); | |
1601 | ||
e16ceb8e | 1602 | if (MEM_P (dest)) |
99b86c05 | 1603 | (*fun) (&XEXP (dest, 0), data); |
1604 | } | |
1605 | return; | |
1606 | ||
1607 | default: | |
1608 | /* All the other possibilities never store. */ | |
1609 | (*fun) (pbody, data); | |
1610 | return; | |
1611 | } | |
1612 | } | |
1613 | \f | |
635aff97 | 1614 | /* Return nonzero if X's old contents don't survive after INSN. |
1615 | This will be true if X is (cc0) or if X is a register and | |
1616 | X dies in INSN or because INSN entirely sets X. | |
1617 | ||
476d094d | 1618 | "Entirely set" means set directly and not through a SUBREG, or |
1619 | ZERO_EXTRACT, so no trace of the old contents remains. | |
635aff97 | 1620 | Likewise, REG_INC does not count. |
1621 | ||
1622 | REG may be a hard or pseudo reg. Renumbering is not taken into account, | |
1623 | but for this use that makes no difference, since regs don't overlap | |
1624 | during their lifetimes. Therefore, this function may be used | |
3072d30e | 1625 | at any time after deaths have been computed. |
635aff97 | 1626 | |
1627 | If REG is a hard reg that occupies multiple machine registers, this | |
1628 | function will only return 1 if each of those registers will be replaced | |
1629 | by INSN. */ | |
1630 | ||
1631 | int | |
dd9b9fc5 | 1632 | dead_or_set_p (const_rtx insn, const_rtx x) |
635aff97 | 1633 | { |
a2c6f0b7 | 1634 | unsigned int regno, end_regno; |
02e7a332 | 1635 | unsigned int i; |
635aff97 | 1636 | |
1637 | /* Can't use cc0_rtx below since this file is used by genattrtab.c. */ | |
1638 | if (GET_CODE (x) == CC0) | |
1639 | return 1; | |
1640 | ||
04e579b6 | 1641 | gcc_assert (REG_P (x)); |
635aff97 | 1642 | |
1643 | regno = REGNO (x); | |
a2c6f0b7 | 1644 | end_regno = END_REGNO (x); |
1645 | for (i = regno; i < end_regno; i++) | |
635aff97 | 1646 | if (! dead_or_set_regno_p (insn, i)) |
1647 | return 0; | |
1648 | ||
1649 | return 1; | |
1650 | } | |
1651 | ||
30c74f6d | 1652 | /* Return TRUE iff DEST is a register or subreg of a register and |
1653 | doesn't change the number of words of the inner register, and any | |
1654 | part of the register is TEST_REGNO. */ | |
1655 | ||
1656 | static bool | |
dd9b9fc5 | 1657 | covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno) |
30c74f6d | 1658 | { |
1659 | unsigned int regno, endregno; | |
1660 | ||
1661 | if (GET_CODE (dest) == SUBREG | |
1662 | && (((GET_MODE_SIZE (GET_MODE (dest)) | |
1663 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
1664 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
1665 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) | |
1666 | dest = SUBREG_REG (dest); | |
1667 | ||
1668 | if (!REG_P (dest)) | |
1669 | return false; | |
1670 | ||
1671 | regno = REGNO (dest); | |
a2c6f0b7 | 1672 | endregno = END_REGNO (dest); |
30c74f6d | 1673 | return (test_regno >= regno && test_regno < endregno); |
1674 | } | |
1675 | ||
1676 | /* Like covers_regno_no_parallel_p, but also handles PARALLELs where | |
1677 | any member matches the covers_regno_no_parallel_p criteria. */ | |
1678 | ||
1679 | static bool | |
dd9b9fc5 | 1680 | covers_regno_p (const_rtx dest, unsigned int test_regno) |
30c74f6d | 1681 | { |
1682 | if (GET_CODE (dest) == PARALLEL) | |
1683 | { | |
1684 | /* Some targets place small structures in registers for return | |
1685 | values of functions, and those registers are wrapped in | |
1686 | PARALLELs that we may see as the destination of a SET. */ | |
1687 | int i; | |
1688 | ||
1689 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
1690 | { | |
1691 | rtx inner = XEXP (XVECEXP (dest, 0, i), 0); | |
1692 | if (inner != NULL_RTX | |
1693 | && covers_regno_no_parallel_p (inner, test_regno)) | |
1694 | return true; | |
1695 | } | |
1696 | ||
1697 | return false; | |
1698 | } | |
1699 | else | |
1700 | return covers_regno_no_parallel_p (dest, test_regno); | |
1701 | } | |
1702 | ||
3072d30e | 1703 | /* Utility function for dead_or_set_p to check an individual register. */ |
635aff97 | 1704 | |
1705 | int | |
dd9b9fc5 | 1706 | dead_or_set_regno_p (const_rtx insn, unsigned int test_regno) |
635aff97 | 1707 | { |
dd9b9fc5 | 1708 | const_rtx pattern; |
635aff97 | 1709 | |
eb1c92fb | 1710 | /* See if there is a death note for something that includes TEST_REGNO. */ |
1711 | if (find_regno_note (insn, REG_DEAD, test_regno)) | |
1712 | return 1; | |
635aff97 | 1713 | |
6d7dc5b9 | 1714 | if (CALL_P (insn) |
0c7201ca | 1715 | && find_regno_fusage (insn, CLOBBER, test_regno)) |
1716 | return 1; | |
1717 | ||
406034fa | 1718 | pattern = PATTERN (insn); |
1719 | ||
d6e8850f | 1720 | /* If a COND_EXEC is not executed, the value survives. */ |
406034fa | 1721 | if (GET_CODE (pattern) == COND_EXEC) |
d6e8850f | 1722 | return 0; |
406034fa | 1723 | |
1724 | if (GET_CODE (pattern) == SET) | |
30c74f6d | 1725 | return covers_regno_p (SET_DEST (pattern), test_regno); |
406034fa | 1726 | else if (GET_CODE (pattern) == PARALLEL) |
635aff97 | 1727 | { |
19cb6b50 | 1728 | int i; |
635aff97 | 1729 | |
406034fa | 1730 | for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--) |
635aff97 | 1731 | { |
406034fa | 1732 | rtx body = XVECEXP (pattern, 0, i); |
1733 | ||
1734 | if (GET_CODE (body) == COND_EXEC) | |
1735 | body = COND_EXEC_CODE (body); | |
635aff97 | 1736 | |
30c74f6d | 1737 | if ((GET_CODE (body) == SET || GET_CODE (body) == CLOBBER) |
1738 | && covers_regno_p (SET_DEST (body), test_regno)) | |
1739 | return 1; | |
635aff97 | 1740 | } |
1741 | } | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
1746 | /* Return the reg-note of kind KIND in insn INSN, if there is one. | |
1747 | If DATUM is nonzero, look for one whose datum is DATUM. */ | |
1748 | ||
1749 | rtx | |
dd9b9fc5 | 1750 | find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum) |
635aff97 | 1751 | { |
19cb6b50 | 1752 | rtx link; |
635aff97 | 1753 | |
0ea2d350 | 1754 | gcc_checking_assert (insn); |
62d6a022 | 1755 | |
49a945b8 | 1756 | /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */ |
9204e736 | 1757 | if (! INSN_P (insn)) |
49a945b8 | 1758 | return 0; |
b2a24b6f | 1759 | if (datum == 0) |
1760 | { | |
1761 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1762 | if (REG_NOTE_KIND (link) == kind) | |
1763 | return link; | |
1764 | return 0; | |
1765 | } | |
49a945b8 | 1766 | |
635aff97 | 1767 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
b2a24b6f | 1768 | if (REG_NOTE_KIND (link) == kind && datum == XEXP (link, 0)) |
635aff97 | 1769 | return link; |
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | /* Return the reg-note of kind KIND in insn INSN which applies to register | |
da5c9e5f | 1774 | number REGNO, if any. Return 0 if there is no such reg-note. Note that |
1775 | the REGNO of this NOTE need not be REGNO if REGNO is a hard register; | |
1776 | it might be the case that the note overlaps REGNO. */ | |
635aff97 | 1777 | |
1778 | rtx | |
dd9b9fc5 | 1779 | find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno) |
635aff97 | 1780 | { |
19cb6b50 | 1781 | rtx link; |
635aff97 | 1782 | |
49a945b8 | 1783 | /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */ |
9204e736 | 1784 | if (! INSN_P (insn)) |
49a945b8 | 1785 | return 0; |
1786 | ||
635aff97 | 1787 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
1788 | if (REG_NOTE_KIND (link) == kind | |
1789 | /* Verify that it is a register, so that scratch and MEM won't cause a | |
1790 | problem here. */ | |
8ad4c111 | 1791 | && REG_P (XEXP (link, 0)) |
da5c9e5f | 1792 | && REGNO (XEXP (link, 0)) <= regno |
a2c6f0b7 | 1793 | && END_REGNO (XEXP (link, 0)) > regno) |
635aff97 | 1794 | return link; |
1795 | return 0; | |
1796 | } | |
0c7201ca | 1797 | |
53cb61a7 | 1798 | /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and |
1799 | has such a note. */ | |
1800 | ||
1801 | rtx | |
dd9b9fc5 | 1802 | find_reg_equal_equiv_note (const_rtx insn) |
53cb61a7 | 1803 | { |
53fffe66 | 1804 | rtx link; |
53cb61a7 | 1805 | |
53fffe66 | 1806 | if (!INSN_P (insn)) |
53cb61a7 | 1807 | return 0; |
e4f51d19 | 1808 | |
53fffe66 | 1809 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
1810 | if (REG_NOTE_KIND (link) == REG_EQUAL | |
1811 | || REG_NOTE_KIND (link) == REG_EQUIV) | |
1812 | { | |
e4f51d19 | 1813 | /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on |
1814 | insns that have multiple sets. Checking single_set to | |
1815 | make sure of this is not the proper check, as explained | |
1816 | in the comment in set_unique_reg_note. | |
1817 | ||
1818 | This should be changed into an assert. */ | |
1819 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
53fffe66 | 1820 | return 0; |
1821 | return link; | |
1822 | } | |
1823 | return NULL; | |
53cb61a7 | 1824 | } |
1825 | ||
3aba99c8 | 1826 | /* Check whether INSN is a single_set whose source is known to be |
1827 | equivalent to a constant. Return that constant if so, otherwise | |
1828 | return null. */ | |
1829 | ||
1830 | rtx | |
dd9b9fc5 | 1831 | find_constant_src (const_rtx insn) |
3aba99c8 | 1832 | { |
1833 | rtx note, set, x; | |
1834 | ||
1835 | set = single_set (insn); | |
1836 | if (set) | |
1837 | { | |
1838 | x = avoid_constant_pool_reference (SET_SRC (set)); | |
1839 | if (CONSTANT_P (x)) | |
1840 | return x; | |
1841 | } | |
1842 | ||
1843 | note = find_reg_equal_equiv_note (insn); | |
1844 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1845 | return XEXP (note, 0); | |
1846 | ||
1847 | return NULL_RTX; | |
1848 | } | |
1849 | ||
0c7201ca | 1850 | /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found |
1851 | in the CALL_INSN_FUNCTION_USAGE information of INSN. */ | |
1852 | ||
1853 | int | |
dd9b9fc5 | 1854 | find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum) |
0c7201ca | 1855 | { |
1856 | /* If it's not a CALL_INSN, it can't possibly have a | |
1857 | CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */ | |
6d7dc5b9 | 1858 | if (!CALL_P (insn)) |
0c7201ca | 1859 | return 0; |
1860 | ||
04e579b6 | 1861 | gcc_assert (datum); |
0c7201ca | 1862 | |
8ad4c111 | 1863 | if (!REG_P (datum)) |
0c7201ca | 1864 | { |
19cb6b50 | 1865 | rtx link; |
0c7201ca | 1866 | |
1867 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
2617fe26 | 1868 | link; |
0c7201ca | 1869 | link = XEXP (link, 1)) |
2617fe26 | 1870 | if (GET_CODE (XEXP (link, 0)) == code |
ff90a874 | 1871 | && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0))) |
2617fe26 | 1872 | return 1; |
0c7201ca | 1873 | } |
1874 | else | |
1875 | { | |
02e7a332 | 1876 | unsigned int regno = REGNO (datum); |
0c7201ca | 1877 | |
1878 | /* CALL_INSN_FUNCTION_USAGE information cannot contain references | |
1879 | to pseudo registers, so don't bother checking. */ | |
1880 | ||
1881 | if (regno < FIRST_PSEUDO_REGISTER) | |
2617fe26 | 1882 | { |
a2c6f0b7 | 1883 | unsigned int end_regno = END_HARD_REGNO (datum); |
02e7a332 | 1884 | unsigned int i; |
0c7201ca | 1885 | |
1886 | for (i = regno; i < end_regno; i++) | |
1887 | if (find_regno_fusage (insn, code, i)) | |
1888 | return 1; | |
2617fe26 | 1889 | } |
0c7201ca | 1890 | } |
1891 | ||
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found | |
1896 | in the CALL_INSN_FUNCTION_USAGE information of INSN. */ | |
1897 | ||
1898 | int | |
dd9b9fc5 | 1899 | find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno) |
0c7201ca | 1900 | { |
19cb6b50 | 1901 | rtx link; |
0c7201ca | 1902 | |
1903 | /* CALL_INSN_FUNCTION_USAGE information cannot contain references | |
1904 | to pseudo registers, so don't bother checking. */ | |
1905 | ||
1906 | if (regno >= FIRST_PSEUDO_REGISTER | |
6d7dc5b9 | 1907 | || !CALL_P (insn) ) |
0c7201ca | 1908 | return 0; |
1909 | ||
1910 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
005d995b | 1911 | { |
02e7a332 | 1912 | rtx op, reg; |
005d995b | 1913 | |
1914 | if (GET_CODE (op = XEXP (link, 0)) == code | |
8ad4c111 | 1915 | && REG_P (reg = XEXP (op, 0)) |
a2c6f0b7 | 1916 | && REGNO (reg) <= regno |
1917 | && END_HARD_REGNO (reg) > regno) | |
005d995b | 1918 | return 1; |
1919 | } | |
0c7201ca | 1920 | |
1921 | return 0; | |
1922 | } | |
ef15379a | 1923 | |
635aff97 | 1924 | \f |
5859ee98 | 1925 | /* Allocate a register note with kind KIND and datum DATUM. LIST is |
1926 | stored as the pointer to the next register note. */ | |
a1ddb869 | 1927 | |
5859ee98 | 1928 | rtx |
1929 | alloc_reg_note (enum reg_note kind, rtx datum, rtx list) | |
a1ddb869 | 1930 | { |
1931 | rtx note; | |
1932 | ||
1933 | switch (kind) | |
1934 | { | |
1935 | case REG_CC_SETTER: | |
1936 | case REG_CC_USER: | |
1937 | case REG_LABEL_TARGET: | |
1938 | case REG_LABEL_OPERAND: | |
4c0315d0 | 1939 | case REG_TM: |
a1ddb869 | 1940 | /* These types of register notes use an INSN_LIST rather than an |
1941 | EXPR_LIST, so that copying is done right and dumps look | |
1942 | better. */ | |
5859ee98 | 1943 | note = alloc_INSN_LIST (datum, list); |
a1ddb869 | 1944 | PUT_REG_NOTE_KIND (note, kind); |
1945 | break; | |
1946 | ||
1947 | default: | |
5859ee98 | 1948 | note = alloc_EXPR_LIST (kind, datum, list); |
a1ddb869 | 1949 | break; |
1950 | } | |
1951 | ||
5859ee98 | 1952 | return note; |
1953 | } | |
1954 | ||
1955 | /* Add register note with kind KIND and datum DATUM to INSN. */ | |
1956 | ||
1957 | void | |
1958 | add_reg_note (rtx insn, enum reg_note kind, rtx datum) | |
1959 | { | |
1960 | REG_NOTES (insn) = alloc_reg_note (kind, datum, REG_NOTES (insn)); | |
a1ddb869 | 1961 | } |
1962 | ||
635aff97 | 1963 | /* Remove register note NOTE from the REG_NOTES of INSN. */ |
1964 | ||
1965 | void | |
dd9b9fc5 | 1966 | remove_note (rtx insn, const_rtx note) |
635aff97 | 1967 | { |
19cb6b50 | 1968 | rtx link; |
635aff97 | 1969 | |
def93098 | 1970 | if (note == NULL_RTX) |
1971 | return; | |
1972 | ||
635aff97 | 1973 | if (REG_NOTES (insn) == note) |
3072d30e | 1974 | REG_NOTES (insn) = XEXP (note, 1); |
1975 | else | |
1976 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1977 | if (XEXP (link, 1) == note) | |
1978 | { | |
1979 | XEXP (link, 1) = XEXP (note, 1); | |
1980 | break; | |
1981 | } | |
1982 | ||
1983 | switch (REG_NOTE_KIND (note)) | |
635aff97 | 1984 | { |
3072d30e | 1985 | case REG_EQUAL: |
1986 | case REG_EQUIV: | |
1987 | df_notes_rescan (insn); | |
1988 | break; | |
1989 | default: | |
1990 | break; | |
635aff97 | 1991 | } |
635aff97 | 1992 | } |
13d60e7c | 1993 | |
f16feee2 | 1994 | /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */ |
1995 | ||
1996 | void | |
1997 | remove_reg_equal_equiv_notes (rtx insn) | |
1998 | { | |
1999 | rtx *loc; | |
2000 | ||
2001 | loc = ®_NOTES (insn); | |
2002 | while (*loc) | |
2003 | { | |
2004 | enum reg_note kind = REG_NOTE_KIND (*loc); | |
2005 | if (kind == REG_EQUAL || kind == REG_EQUIV) | |
2006 | *loc = XEXP (*loc, 1); | |
2007 | else | |
2008 | loc = &XEXP (*loc, 1); | |
2009 | } | |
2010 | } | |
09669349 | 2011 | |
2012 | /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */ | |
2013 | ||
2014 | void | |
2015 | remove_reg_equal_equiv_notes_for_regno (unsigned int regno) | |
2016 | { | |
2017 | df_ref eq_use; | |
2018 | ||
2019 | if (!df) | |
2020 | return; | |
2021 | ||
2022 | /* This loop is a little tricky. We cannot just go down the chain because | |
2023 | it is being modified by some actions in the loop. So we just iterate | |
2024 | over the head. We plan to drain the list anyway. */ | |
2025 | while ((eq_use = DF_REG_EQ_USE_CHAIN (regno)) != NULL) | |
2026 | { | |
2027 | rtx insn = DF_REF_INSN (eq_use); | |
2028 | rtx note = find_reg_equal_equiv_note (insn); | |
2029 | ||
2030 | /* This assert is generally triggered when someone deletes a REG_EQUAL | |
2031 | or REG_EQUIV note by hacking the list manually rather than calling | |
2032 | remove_note. */ | |
2033 | gcc_assert (note); | |
2034 | ||
2035 | remove_note (insn, note); | |
2036 | } | |
2037 | } | |
f16feee2 | 2038 | |
5cc577b6 | 2039 | /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and |
2040 | return 1 if it is found. A simple equality test is used to determine if | |
2041 | NODE matches. */ | |
2042 | ||
2043 | int | |
dd9b9fc5 | 2044 | in_expr_list_p (const_rtx listp, const_rtx node) |
5cc577b6 | 2045 | { |
dd9b9fc5 | 2046 | const_rtx x; |
5cc577b6 | 2047 | |
2048 | for (x = listp; x; x = XEXP (x, 1)) | |
2049 | if (node == XEXP (x, 0)) | |
2050 | return 1; | |
2051 | ||
2052 | return 0; | |
2053 | } | |
2054 | ||
badb6da9 | 2055 | /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and |
2056 | remove that entry from the list if it is found. | |
13d60e7c | 2057 | |
badb6da9 | 2058 | A simple equality test is used to determine if NODE matches. */ |
13d60e7c | 2059 | |
2060 | void | |
dd9b9fc5 | 2061 | remove_node_from_expr_list (const_rtx node, rtx *listp) |
13d60e7c | 2062 | { |
2063 | rtx temp = *listp; | |
2064 | rtx prev = NULL_RTX; | |
2065 | ||
2066 | while (temp) | |
2067 | { | |
2068 | if (node == XEXP (temp, 0)) | |
2069 | { | |
2070 | /* Splice the node out of the list. */ | |
2071 | if (prev) | |
2072 | XEXP (prev, 1) = XEXP (temp, 1); | |
2073 | else | |
2074 | *listp = XEXP (temp, 1); | |
2075 | ||
2076 | return; | |
2077 | } | |
badb6da9 | 2078 | |
2079 | prev = temp; | |
13d60e7c | 2080 | temp = XEXP (temp, 1); |
2081 | } | |
2082 | } | |
635aff97 | 2083 | \f |
ea275ef9 | 2084 | /* Nonzero if X contains any volatile instructions. These are instructions |
2085 | which may cause unpredictable machine state instructions, and thus no | |
2086 | instructions should be moved or combined across them. This includes | |
2087 | only volatile asms and UNSPEC_VOLATILE instructions. */ | |
2088 | ||
2089 | int | |
dd9b9fc5 | 2090 | volatile_insn_p (const_rtx x) |
ea275ef9 | 2091 | { |
dd9b9fc5 | 2092 | const RTX_CODE code = GET_CODE (x); |
ea275ef9 | 2093 | switch (code) |
2094 | { | |
2095 | case LABEL_REF: | |
2096 | case SYMBOL_REF: | |
ea275ef9 | 2097 | case CONST: |
0349edce | 2098 | CASE_CONST_ANY: |
ea275ef9 | 2099 | case CC0: |
2100 | case PC: | |
2101 | case REG: | |
2102 | case SCRATCH: | |
2103 | case CLOBBER: | |
ea275ef9 | 2104 | case ADDR_VEC: |
2105 | case ADDR_DIFF_VEC: | |
2106 | case CALL: | |
2107 | case MEM: | |
2108 | return 0; | |
2109 | ||
2110 | case UNSPEC_VOLATILE: | |
2111 | /* case TRAP_IF: This isn't clear yet. */ | |
2112 | return 1; | |
2113 | ||
c52051b7 | 2114 | case ASM_INPUT: |
ea275ef9 | 2115 | case ASM_OPERANDS: |
2116 | if (MEM_VOLATILE_P (x)) | |
2117 | return 1; | |
0dbd1c74 | 2118 | |
2119 | default: | |
2120 | break; | |
ea275ef9 | 2121 | } |
2122 | ||
2123 | /* Recursively scan the operands of this expression. */ | |
2124 | ||
2125 | { | |
dd9b9fc5 | 2126 | const char *const fmt = GET_RTX_FORMAT (code); |
19cb6b50 | 2127 | int i; |
2617fe26 | 2128 | |
ea275ef9 | 2129 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2130 | { | |
2131 | if (fmt[i] == 'e') | |
2132 | { | |
c1dadb43 | 2133 | if (volatile_insn_p (XEXP (x, i))) |
ea275ef9 | 2134 | return 1; |
2135 | } | |
1bd8ca86 | 2136 | else if (fmt[i] == 'E') |
ea275ef9 | 2137 | { |
19cb6b50 | 2138 | int j; |
ea275ef9 | 2139 | for (j = 0; j < XVECLEN (x, i); j++) |
c1dadb43 | 2140 | if (volatile_insn_p (XVECEXP (x, i, j))) |
ea275ef9 | 2141 | return 1; |
2142 | } | |
2143 | } | |
2144 | } | |
2145 | return 0; | |
2146 | } | |
2147 | ||
635aff97 | 2148 | /* Nonzero if X contains any volatile memory references |
3384a30e | 2149 | UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */ |
635aff97 | 2150 | |
2151 | int | |
dd9b9fc5 | 2152 | volatile_refs_p (const_rtx x) |
635aff97 | 2153 | { |
dd9b9fc5 | 2154 | const RTX_CODE code = GET_CODE (x); |
635aff97 | 2155 | switch (code) |
2156 | { | |
2157 | case LABEL_REF: | |
2158 | case SYMBOL_REF: | |
635aff97 | 2159 | case CONST: |
0349edce | 2160 | CASE_CONST_ANY: |
635aff97 | 2161 | case CC0: |
2162 | case PC: | |
2163 | case REG: | |
2164 | case SCRATCH: | |
2165 | case CLOBBER: | |
635aff97 | 2166 | case ADDR_VEC: |
2167 | case ADDR_DIFF_VEC: | |
2168 | return 0; | |
2169 | ||
3384a30e | 2170 | case UNSPEC_VOLATILE: |
635aff97 | 2171 | return 1; |
2172 | ||
2173 | case MEM: | |
c52051b7 | 2174 | case ASM_INPUT: |
635aff97 | 2175 | case ASM_OPERANDS: |
2176 | if (MEM_VOLATILE_P (x)) | |
2177 | return 1; | |
0dbd1c74 | 2178 | |
2179 | default: | |
2180 | break; | |
635aff97 | 2181 | } |
2182 | ||
2183 | /* Recursively scan the operands of this expression. */ | |
2184 | ||
2185 | { | |
dd9b9fc5 | 2186 | const char *const fmt = GET_RTX_FORMAT (code); |
19cb6b50 | 2187 | int i; |
2617fe26 | 2188 | |
635aff97 | 2189 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2190 | { | |
2191 | if (fmt[i] == 'e') | |
2192 | { | |
2193 | if (volatile_refs_p (XEXP (x, i))) | |
2194 | return 1; | |
2195 | } | |
1bd8ca86 | 2196 | else if (fmt[i] == 'E') |
635aff97 | 2197 | { |
19cb6b50 | 2198 | int j; |
635aff97 | 2199 | for (j = 0; j < XVECLEN (x, i); j++) |
2200 | if (volatile_refs_p (XVECEXP (x, i, j))) | |
2201 | return 1; | |
2202 | } | |
2203 | } | |
2204 | } | |
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | /* Similar to above, except that it also rejects register pre- and post- | |
2209 | incrementing. */ | |
2210 | ||
2211 | int | |
dd9b9fc5 | 2212 | side_effects_p (const_rtx x) |
635aff97 | 2213 | { |
dd9b9fc5 | 2214 | const RTX_CODE code = GET_CODE (x); |
635aff97 | 2215 | switch (code) |
2216 | { | |
2217 | case LABEL_REF: | |
2218 | case SYMBOL_REF: | |
635aff97 | 2219 | case CONST: |
0349edce | 2220 | CASE_CONST_ANY: |
635aff97 | 2221 | case CC0: |
2222 | case PC: | |
2223 | case REG: | |
2224 | case SCRATCH: | |
635aff97 | 2225 | case ADDR_VEC: |
2226 | case ADDR_DIFF_VEC: | |
9845d120 | 2227 | case VAR_LOCATION: |
635aff97 | 2228 | return 0; |
2229 | ||
2230 | case CLOBBER: | |
2231 | /* Reject CLOBBER with a non-VOID mode. These are made by combine.c | |
2232 | when some combination can't be done. If we see one, don't think | |
2233 | that we can simplify the expression. */ | |
2234 | return (GET_MODE (x) != VOIDmode); | |
2235 | ||
2236 | case PRE_INC: | |
2237 | case PRE_DEC: | |
2238 | case POST_INC: | |
2239 | case POST_DEC: | |
a3da8215 | 2240 | case PRE_MODIFY: |
2241 | case POST_MODIFY: | |
635aff97 | 2242 | case CALL: |
3384a30e | 2243 | case UNSPEC_VOLATILE: |
635aff97 | 2244 | /* case TRAP_IF: This isn't clear yet. */ |
2245 | return 1; | |
2246 | ||
2247 | case MEM: | |
c52051b7 | 2248 | case ASM_INPUT: |
635aff97 | 2249 | case ASM_OPERANDS: |
2250 | if (MEM_VOLATILE_P (x)) | |
2251 | return 1; | |
0dbd1c74 | 2252 | |
2253 | default: | |
2254 | break; | |
635aff97 | 2255 | } |
2256 | ||
2257 | /* Recursively scan the operands of this expression. */ | |
2258 | ||
2259 | { | |
19cb6b50 | 2260 | const char *fmt = GET_RTX_FORMAT (code); |
2261 | int i; | |
2617fe26 | 2262 | |
635aff97 | 2263 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2264 | { | |
2265 | if (fmt[i] == 'e') | |
2266 | { | |
2267 | if (side_effects_p (XEXP (x, i))) | |
2268 | return 1; | |
2269 | } | |
1bd8ca86 | 2270 | else if (fmt[i] == 'E') |
635aff97 | 2271 | { |
19cb6b50 | 2272 | int j; |
635aff97 | 2273 | for (j = 0; j < XVECLEN (x, i); j++) |
2274 | if (side_effects_p (XVECEXP (x, i, j))) | |
2275 | return 1; | |
2276 | } | |
2277 | } | |
2278 | } | |
2279 | return 0; | |
2280 | } | |
2281 | \f | |
5ed26a34 | 2282 | /* Return nonzero if evaluating rtx X might cause a trap. |
0eee494e | 2283 | FLAGS controls how to consider MEMs. A nonzero means the context |
2284 | of the access may have changed from the original, such that the | |
2285 | address may have become invalid. */ | |
635aff97 | 2286 | |
77ad8e5a | 2287 | int |
dd9b9fc5 | 2288 | may_trap_p_1 (const_rtx x, unsigned flags) |
635aff97 | 2289 | { |
2290 | int i; | |
2291 | enum rtx_code code; | |
d2ca078f | 2292 | const char *fmt; |
0eee494e | 2293 | |
2294 | /* We make no distinction currently, but this function is part of | |
2295 | the internal target-hooks ABI so we keep the parameter as | |
2296 | "unsigned flags". */ | |
2297 | bool code_changed = flags != 0; | |
635aff97 | 2298 | |
2299 | if (x == 0) | |
2300 | return 0; | |
2301 | code = GET_CODE (x); | |
2302 | switch (code) | |
2303 | { | |
2304 | /* Handle these cases quickly. */ | |
0349edce | 2305 | CASE_CONST_ANY: |
635aff97 | 2306 | case SYMBOL_REF: |
2307 | case LABEL_REF: | |
2308 | case CONST: | |
2309 | case PC: | |
2310 | case CC0: | |
2311 | case REG: | |
2312 | case SCRATCH: | |
2313 | return 0; | |
2314 | ||
77ad8e5a | 2315 | case UNSPEC: |
3384a30e | 2316 | case UNSPEC_VOLATILE: |
77ad8e5a | 2317 | return targetm.unspec_may_trap_p (x, flags); |
2318 | ||
2319 | case ASM_INPUT: | |
635aff97 | 2320 | case TRAP_IF: |
2321 | return 1; | |
2322 | ||
d18a3f6d | 2323 | case ASM_OPERANDS: |
2324 | return MEM_VOLATILE_P (x); | |
2325 | ||
635aff97 | 2326 | /* Memory ref can trap unless it's a static var or a stack slot. */ |
2327 | case MEM: | |
42982f3e | 2328 | /* Recognize specific pattern of stack checking probes. */ |
2329 | if (flag_stack_check | |
2330 | && MEM_VOLATILE_P (x) | |
2331 | && XEXP (x, 0) == stack_pointer_rtx) | |
2332 | return 1; | |
5ed26a34 | 2333 | if (/* MEM_NOTRAP_P only relates to the actual position of the memory |
0eee494e | 2334 | reference; moving it out of context such as when moving code |
2335 | when optimizing, might cause its address to become invalid. */ | |
2336 | code_changed | |
2337 | || !MEM_NOTRAP_P (x)) | |
2338 | { | |
5b2a69fa | 2339 | HOST_WIDE_INT size = MEM_SIZE_KNOWN_P (x) ? MEM_SIZE (x) : 0; |
0eee494e | 2340 | return rtx_addr_can_trap_p_1 (XEXP (x, 0), 0, size, |
2341 | GET_MODE (x), code_changed); | |
2342 | } | |
2343 | ||
2344 | return 0; | |
635aff97 | 2345 | |
2346 | /* Division by a non-constant might trap. */ | |
2347 | case DIV: | |
2348 | case MOD: | |
2349 | case UDIV: | |
2350 | case UMOD: | |
0a8176f3 | 2351 | if (HONOR_SNANS (GET_MODE (x))) |
2352 | return 1; | |
cee7491d | 2353 | if (SCALAR_FLOAT_MODE_P (GET_MODE (x))) |
8e97b017 | 2354 | return flag_trapping_math; |
2355 | if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx)) | |
635aff97 | 2356 | return 1; |
0dbd1c74 | 2357 | break; |
2358 | ||
4c3aec45 | 2359 | case EXPR_LIST: |
2360 | /* An EXPR_LIST is used to represent a function call. This | |
2361 | certainly may trap. */ | |
2362 | return 1; | |
0dbd1c74 | 2363 | |
27ea6d28 | 2364 | case GE: |
2365 | case GT: | |
2366 | case LE: | |
2367 | case LT: | |
f1278f7e | 2368 | case LTGT: |
51ba663d | 2369 | case COMPARE: |
27ea6d28 | 2370 | /* Some floating point comparisons may trap. */ |
350b17ef | 2371 | if (!flag_trapping_math) |
2372 | break; | |
27ea6d28 | 2373 | /* ??? There is no machine independent way to check for tests that trap |
2374 | when COMPARE is used, though many targets do make this distinction. | |
2375 | For instance, sparc uses CCFPE for compares which generate exceptions | |
2376 | and CCFP for compares which do not generate exceptions. */ | |
0a8176f3 | 2377 | if (HONOR_NANS (GET_MODE (x))) |
51ba663d | 2378 | return 1; |
2379 | /* But often the compare has some CC mode, so check operand | |
2380 | modes as well. */ | |
0a8176f3 | 2381 | if (HONOR_NANS (GET_MODE (XEXP (x, 0))) |
2382 | || HONOR_NANS (GET_MODE (XEXP (x, 1)))) | |
2383 | return 1; | |
2384 | break; | |
2385 | ||
2386 | case EQ: | |
2387 | case NE: | |
2388 | if (HONOR_SNANS (GET_MODE (x))) | |
2389 | return 1; | |
2390 | /* Often comparison is CC mode, so check operand modes. */ | |
2391 | if (HONOR_SNANS (GET_MODE (XEXP (x, 0))) | |
2392 | || HONOR_SNANS (GET_MODE (XEXP (x, 1)))) | |
51ba663d | 2393 | return 1; |
2394 | break; | |
2395 | ||
d0a099f8 | 2396 | case FIX: |
2397 | /* Conversion of floating point might trap. */ | |
2398 | if (flag_trapping_math && HONOR_NANS (GET_MODE (XEXP (x, 0)))) | |
2399 | return 1; | |
2400 | break; | |
2401 | ||
4f63c6d1 | 2402 | case NEG: |
2403 | case ABS: | |
f0fbc1cd | 2404 | case SUBREG: |
4f63c6d1 | 2405 | /* These operations don't trap even with floating point. */ |
2406 | break; | |
2407 | ||
635aff97 | 2408 | default: |
2409 | /* Any floating arithmetic may trap. */ | |
cee7491d | 2410 | if (SCALAR_FLOAT_MODE_P (GET_MODE (x)) |
350b17ef | 2411 | && flag_trapping_math) |
635aff97 | 2412 | return 1; |
2413 | } | |
2414 | ||
2415 | fmt = GET_RTX_FORMAT (code); | |
2416 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2417 | { | |
2418 | if (fmt[i] == 'e') | |
2419 | { | |
5ed26a34 | 2420 | if (may_trap_p_1 (XEXP (x, i), flags)) |
635aff97 | 2421 | return 1; |
2422 | } | |
2423 | else if (fmt[i] == 'E') | |
2424 | { | |
19cb6b50 | 2425 | int j; |
635aff97 | 2426 | for (j = 0; j < XVECLEN (x, i); j++) |
5ed26a34 | 2427 | if (may_trap_p_1 (XVECEXP (x, i, j), flags)) |
635aff97 | 2428 | return 1; |
2429 | } | |
2430 | } | |
2431 | return 0; | |
2432 | } | |
1aecae7f | 2433 | |
2434 | /* Return nonzero if evaluating rtx X might cause a trap. */ | |
2435 | ||
2436 | int | |
dd9b9fc5 | 2437 | may_trap_p (const_rtx x) |
1aecae7f | 2438 | { |
5ed26a34 | 2439 | return may_trap_p_1 (x, 0); |
2440 | } | |
2441 | ||
334ec2d8 | 2442 | /* Same as above, but additionally return nonzero if evaluating rtx X might |
1aecae7f | 2443 | cause a fault. We define a fault for the purpose of this function as a |
2444 | erroneous execution condition that cannot be encountered during the normal | |
2445 | execution of a valid program; the typical example is an unaligned memory | |
2446 | access on a strict alignment machine. The compiler guarantees that it | |
2447 | doesn't generate code that will fault from a valid program, but this | |
2448 | guarantee doesn't mean anything for individual instructions. Consider | |
2449 | the following example: | |
2450 | ||
2451 | struct S { int d; union { char *cp; int *ip; }; }; | |
2452 | ||
2453 | int foo(struct S *s) | |
2454 | { | |
2455 | if (s->d == 1) | |
2456 | return *s->ip; | |
2457 | else | |
2458 | return *s->cp; | |
2459 | } | |
2460 | ||
2461 | on a strict alignment machine. In a valid program, foo will never be | |
2462 | invoked on a structure for which d is equal to 1 and the underlying | |
2463 | unique field of the union not aligned on a 4-byte boundary, but the | |
2464 | expression *s->ip might cause a fault if considered individually. | |
2465 | ||
2466 | At the RTL level, potentially problematic expressions will almost always | |
2467 | verify may_trap_p; for example, the above dereference can be emitted as | |
2468 | (mem:SI (reg:P)) and this expression is may_trap_p for a generic register. | |
2469 | However, suppose that foo is inlined in a caller that causes s->cp to | |
2470 | point to a local character variable and guarantees that s->d is not set | |
2471 | to 1; foo may have been effectively translated into pseudo-RTL as: | |
2472 | ||
2473 | if ((reg:SI) == 1) | |
2474 | (set (reg:SI) (mem:SI (%fp - 7))) | |
2475 | else | |
2476 | (set (reg:QI) (mem:QI (%fp - 7))) | |
2477 | ||
2478 | Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a | |
2479 | memory reference to a stack slot, but it will certainly cause a fault | |
2480 | on a strict alignment machine. */ | |
2481 | ||
2482 | int | |
dd9b9fc5 | 2483 | may_trap_or_fault_p (const_rtx x) |
1aecae7f | 2484 | { |
0eee494e | 2485 | return may_trap_p_1 (x, 1); |
1aecae7f | 2486 | } |
635aff97 | 2487 | \f |
2488 | /* Return nonzero if X contains a comparison that is not either EQ or NE, | |
2489 | i.e., an inequality. */ | |
2490 | ||
2491 | int | |
dd9b9fc5 | 2492 | inequality_comparisons_p (const_rtx x) |
635aff97 | 2493 | { |
19cb6b50 | 2494 | const char *fmt; |
2495 | int len, i; | |
dd9b9fc5 | 2496 | const enum rtx_code code = GET_CODE (x); |
635aff97 | 2497 | |
2498 | switch (code) | |
2499 | { | |
2500 | case REG: | |
2501 | case SCRATCH: | |
2502 | case PC: | |
2503 | case CC0: | |
0349edce | 2504 | CASE_CONST_ANY: |
635aff97 | 2505 | case CONST: |
2506 | case LABEL_REF: | |
2507 | case SYMBOL_REF: | |
2508 | return 0; | |
2509 | ||
2510 | case LT: | |
2511 | case LTU: | |
2512 | case GT: | |
2513 | case GTU: | |
2514 | case LE: | |
2515 | case LEU: | |
2516 | case GE: | |
2517 | case GEU: | |
2518 | return 1; | |
2617fe26 | 2519 | |
0dbd1c74 | 2520 | default: |
2521 | break; | |
635aff97 | 2522 | } |
2523 | ||
2524 | len = GET_RTX_LENGTH (code); | |
2525 | fmt = GET_RTX_FORMAT (code); | |
2526 | ||
2527 | for (i = 0; i < len; i++) | |
2528 | { | |
2529 | if (fmt[i] == 'e') | |
2530 | { | |
2531 | if (inequality_comparisons_p (XEXP (x, i))) | |
2532 | return 1; | |
2533 | } | |
2534 | else if (fmt[i] == 'E') | |
2535 | { | |
19cb6b50 | 2536 | int j; |
635aff97 | 2537 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
2538 | if (inequality_comparisons_p (XVECEXP (x, i, j))) | |
2539 | return 1; | |
2540 | } | |
2541 | } | |
2617fe26 | 2542 | |
635aff97 | 2543 | return 0; |
2544 | } | |
2545 | \f | |
0a20afb5 | 2546 | /* Replace any occurrence of FROM in X with TO. The function does |
2547 | not enter into CONST_DOUBLE for the replace. | |
635aff97 | 2548 | |
2549 | Note that copying is not done so X must not be shared unless all copies | |
2550 | are to be modified. */ | |
2551 | ||
2552 | rtx | |
3ad4992f | 2553 | replace_rtx (rtx x, rtx from, rtx to) |
635aff97 | 2554 | { |
19cb6b50 | 2555 | int i, j; |
2556 | const char *fmt; | |
635aff97 | 2557 | |
2558 | if (x == from) | |
2559 | return to; | |
2560 | ||
2561 | /* Allow this function to make replacements in EXPR_LISTs. */ | |
2562 | if (x == 0) | |
2563 | return 0; | |
2564 | ||
11896b36 | 2565 | if (GET_CODE (x) == SUBREG) |
2566 | { | |
47cfb7f4 | 2567 | rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to); |
11896b36 | 2568 | |
971ba038 | 2569 | if (CONST_INT_P (new_rtx)) |
11896b36 | 2570 | { |
47cfb7f4 | 2571 | x = simplify_subreg (GET_MODE (x), new_rtx, |
11896b36 | 2572 | GET_MODE (SUBREG_REG (x)), |
2573 | SUBREG_BYTE (x)); | |
04e579b6 | 2574 | gcc_assert (x); |
11896b36 | 2575 | } |
2576 | else | |
47cfb7f4 | 2577 | SUBREG_REG (x) = new_rtx; |
11896b36 | 2578 | |
2579 | return x; | |
2580 | } | |
2581 | else if (GET_CODE (x) == ZERO_EXTEND) | |
2582 | { | |
47cfb7f4 | 2583 | rtx new_rtx = replace_rtx (XEXP (x, 0), from, to); |
11896b36 | 2584 | |
971ba038 | 2585 | if (CONST_INT_P (new_rtx)) |
11896b36 | 2586 | { |
2587 | x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
47cfb7f4 | 2588 | new_rtx, GET_MODE (XEXP (x, 0))); |
04e579b6 | 2589 | gcc_assert (x); |
11896b36 | 2590 | } |
2591 | else | |
47cfb7f4 | 2592 | XEXP (x, 0) = new_rtx; |
11896b36 | 2593 | |
2594 | return x; | |
2595 | } | |
2596 | ||
635aff97 | 2597 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
2598 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
2599 | { | |
2600 | if (fmt[i] == 'e') | |
2601 | XEXP (x, i) = replace_rtx (XEXP (x, i), from, to); | |
2602 | else if (fmt[i] == 'E') | |
2603 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2604 | XVECEXP (x, i, j) = replace_rtx (XVECEXP (x, i, j), from, to); | |
2605 | } | |
2606 | ||
2607 | return x; | |
2617fe26 | 2608 | } |
635aff97 | 2609 | \f |
f2756aab | 2610 | /* Replace occurrences of the old label in *X with the new one. |
cda612f5 | 2611 | DATA is a REPLACE_LABEL_DATA containing the old and new labels. */ |
f2756aab | 2612 | |
2613 | int | |
3ad4992f | 2614 | replace_label (rtx *x, void *data) |
f2756aab | 2615 | { |
2616 | rtx l = *x; | |
cda612f5 | 2617 | rtx old_label = ((replace_label_data *) data)->r1; |
2618 | rtx new_label = ((replace_label_data *) data)->r2; | |
2619 | bool update_label_nuses = ((replace_label_data *) data)->update_label_nuses; | |
f2756aab | 2620 | |
2621 | if (l == NULL_RTX) | |
2622 | return 0; | |
2623 | ||
e48e460b | 2624 | if (GET_CODE (l) == SYMBOL_REF |
2625 | && CONSTANT_POOL_ADDRESS_P (l)) | |
cda612f5 | 2626 | { |
e48e460b | 2627 | rtx c = get_pool_constant (l); |
cda612f5 | 2628 | if (rtx_referenced_p (old_label, c)) |
2629 | { | |
2630 | rtx new_c, new_l; | |
2631 | replace_label_data *d = (replace_label_data *) data; | |
3ad4992f | 2632 | |
cda612f5 | 2633 | /* Create a copy of constant C; replace the label inside |
2634 | but do not update LABEL_NUSES because uses in constant pool | |
2635 | are not counted. */ | |
2636 | new_c = copy_rtx (c); | |
2637 | d->update_label_nuses = false; | |
2638 | for_each_rtx (&new_c, replace_label, data); | |
2639 | d->update_label_nuses = update_label_nuses; | |
2640 | ||
2641 | /* Add the new constant NEW_C to constant pool and replace | |
2642 | the old reference to constant by new reference. */ | |
e48e460b | 2643 | new_l = XEXP (force_const_mem (get_pool_mode (l), new_c), 0); |
cda612f5 | 2644 | *x = replace_rtx (l, l, new_l); |
2645 | } | |
2646 | return 0; | |
2647 | } | |
2648 | ||
f2756aab | 2649 | /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL |
2650 | field. This is not handled by for_each_rtx because it doesn't | |
2651 | handle unprinted ('0') fields. */ | |
6d7dc5b9 | 2652 | if (JUMP_P (l) && JUMP_LABEL (l) == old_label) |
f2756aab | 2653 | JUMP_LABEL (l) = new_label; |
f2756aab | 2654 | |
cda612f5 | 2655 | if ((GET_CODE (l) == LABEL_REF |
2656 | || GET_CODE (l) == INSN_LIST) | |
2657 | && XEXP (l, 0) == old_label) | |
2658 | { | |
2659 | XEXP (l, 0) = new_label; | |
2660 | if (update_label_nuses) | |
2661 | { | |
2662 | ++LABEL_NUSES (new_label); | |
2663 | --LABEL_NUSES (old_label); | |
2664 | } | |
2665 | return 0; | |
2666 | } | |
f2756aab | 2667 | |
2668 | return 0; | |
2669 | } | |
2670 | ||
cda612f5 | 2671 | /* When *BODY is equal to X or X is directly referenced by *BODY |
2672 | return nonzero, thus FOR_EACH_RTX stops traversing and returns nonzero | |
2673 | too, otherwise FOR_EACH_RTX continues traversing *BODY. */ | |
f2756aab | 2674 | |
2675 | static int | |
3ad4992f | 2676 | rtx_referenced_p_1 (rtx *body, void *x) |
f2756aab | 2677 | { |
cda612f5 | 2678 | rtx y = (rtx) x; |
2679 | ||
2680 | if (*body == NULL_RTX) | |
2681 | return y == NULL_RTX; | |
2682 | ||
2683 | /* Return true if a label_ref *BODY refers to label Y. */ | |
6d7dc5b9 | 2684 | if (GET_CODE (*body) == LABEL_REF && LABEL_P (y)) |
cda612f5 | 2685 | return XEXP (*body, 0) == y; |
2686 | ||
2687 | /* If *BODY is a reference to pool constant traverse the constant. */ | |
2688 | if (GET_CODE (*body) == SYMBOL_REF | |
2689 | && CONSTANT_POOL_ADDRESS_P (*body)) | |
2690 | return rtx_referenced_p (y, get_pool_constant (*body)); | |
2691 | ||
2692 | /* By default, compare the RTL expressions. */ | |
2693 | return rtx_equal_p (*body, y); | |
f2756aab | 2694 | } |
2695 | ||
cda612f5 | 2696 | /* Return true if X is referenced in BODY. */ |
f2756aab | 2697 | |
2698 | int | |
3ad4992f | 2699 | rtx_referenced_p (rtx x, rtx body) |
f2756aab | 2700 | { |
cda612f5 | 2701 | return for_each_rtx (&body, rtx_referenced_p_1, x); |
f2756aab | 2702 | } |
2703 | ||
afff715a | 2704 | /* If INSN is a tablejump return true and store the label (before jump table) to |
2705 | *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */ | |
f2756aab | 2706 | |
2707 | bool | |
dd9b9fc5 | 2708 | tablejump_p (const_rtx insn, rtx *labelp, rtx *tablep) |
f2756aab | 2709 | { |
afff715a | 2710 | rtx label, table; |
2711 | ||
4115ac36 | 2712 | if (!JUMP_P (insn)) |
2713 | return false; | |
2714 | ||
2715 | label = JUMP_LABEL (insn); | |
2716 | if (label != NULL_RTX && !ANY_RETURN_P (label) | |
afff715a | 2717 | && (table = next_active_insn (label)) != NULL_RTX |
971ba038 | 2718 | && JUMP_TABLE_DATA_P (table)) |
f2756aab | 2719 | { |
afff715a | 2720 | if (labelp) |
2721 | *labelp = label; | |
2722 | if (tablep) | |
2723 | *tablep = table; | |
f2756aab | 2724 | return true; |
2725 | } | |
2726 | return false; | |
2727 | } | |
2728 | ||
4e44a132 | 2729 | /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or |
2730 | constant that is not in the constant pool and not in the condition | |
2731 | of an IF_THEN_ELSE. */ | |
ca6d6e84 | 2732 | |
2733 | static int | |
dd9b9fc5 | 2734 | computed_jump_p_1 (const_rtx x) |
ca6d6e84 | 2735 | { |
dd9b9fc5 | 2736 | const enum rtx_code code = GET_CODE (x); |
ca6d6e84 | 2737 | int i, j; |
d2ca078f | 2738 | const char *fmt; |
ca6d6e84 | 2739 | |
2740 | switch (code) | |
2741 | { | |
ca6d6e84 | 2742 | case LABEL_REF: |
2743 | case PC: | |
2744 | return 0; | |
2745 | ||
4e44a132 | 2746 | case CONST: |
0349edce | 2747 | CASE_CONST_ANY: |
4e44a132 | 2748 | case SYMBOL_REF: |
ca6d6e84 | 2749 | case REG: |
2750 | return 1; | |
2751 | ||
2752 | case MEM: | |
2753 | return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF | |
2754 | && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))); | |
2755 | ||
2756 | case IF_THEN_ELSE: | |
4e44a132 | 2757 | return (computed_jump_p_1 (XEXP (x, 1)) |
2758 | || computed_jump_p_1 (XEXP (x, 2))); | |
99c14947 | 2759 | |
2760 | default: | |
2761 | break; | |
ca6d6e84 | 2762 | } |
2763 | ||
2764 | fmt = GET_RTX_FORMAT (code); | |
2765 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2766 | { | |
2767 | if (fmt[i] == 'e' | |
4e44a132 | 2768 | && computed_jump_p_1 (XEXP (x, i))) |
ca6d6e84 | 2769 | return 1; |
2770 | ||
1bd8ca86 | 2771 | else if (fmt[i] == 'E') |
ca6d6e84 | 2772 | for (j = 0; j < XVECLEN (x, i); j++) |
4e44a132 | 2773 | if (computed_jump_p_1 (XVECEXP (x, i, j))) |
ca6d6e84 | 2774 | return 1; |
2775 | } | |
2776 | ||
2777 | return 0; | |
2778 | } | |
2779 | ||
2780 | /* Return nonzero if INSN is an indirect jump (aka computed jump). | |
2781 | ||
2782 | Tablejumps and casesi insns are not considered indirect jumps; | |
9588521d | 2783 | we can recognize them by a (use (label_ref)). */ |
ca6d6e84 | 2784 | |
2785 | int | |
dd9b9fc5 | 2786 | computed_jump_p (const_rtx insn) |
ca6d6e84 | 2787 | { |
2788 | int i; | |
6d7dc5b9 | 2789 | if (JUMP_P (insn)) |
ca6d6e84 | 2790 | { |
2791 | rtx pat = PATTERN (insn); | |
ca6d6e84 | 2792 | |
19d2fe05 | 2793 | /* If we have a JUMP_LABEL set, we're not a computed jump. */ |
2794 | if (JUMP_LABEL (insn) != NULL) | |
d3ff0f75 | 2795 | return 0; |
19d2fe05 | 2796 | |
2797 | if (GET_CODE (pat) == PARALLEL) | |
ca6d6e84 | 2798 | { |
2799 | int len = XVECLEN (pat, 0); | |
2800 | int has_use_labelref = 0; | |
2801 | ||
2802 | for (i = len - 1; i >= 0; i--) | |
2803 | if (GET_CODE (XVECEXP (pat, 0, i)) == USE | |
2804 | && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0)) | |
2805 | == LABEL_REF)) | |
2806 | has_use_labelref = 1; | |
2807 | ||
2808 | if (! has_use_labelref) | |
2809 | for (i = len - 1; i >= 0; i--) | |
2810 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET | |
2811 | && SET_DEST (XVECEXP (pat, 0, i)) == pc_rtx | |
4e44a132 | 2812 | && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i)))) |
ca6d6e84 | 2813 | return 1; |
2814 | } | |
2815 | else if (GET_CODE (pat) == SET | |
2816 | && SET_DEST (pat) == pc_rtx | |
4e44a132 | 2817 | && computed_jump_p_1 (SET_SRC (pat))) |
ca6d6e84 | 2818 | return 1; |
2819 | } | |
2820 | return 0; | |
2821 | } | |
fb8acade | 2822 | |
a87cf6e5 | 2823 | /* Optimized loop of for_each_rtx, trying to avoid useless recursive |
2824 | calls. Processes the subexpressions of EXP and passes them to F. */ | |
2825 | static int | |
2826 | for_each_rtx_1 (rtx exp, int n, rtx_function f, void *data) | |
2827 | { | |
2828 | int result, i, j; | |
2829 | const char *format = GET_RTX_FORMAT (GET_CODE (exp)); | |
2830 | rtx *x; | |
2831 | ||
2832 | for (; format[n] != '\0'; n++) | |
2833 | { | |
2834 | switch (format[n]) | |
2835 | { | |
2836 | case 'e': | |
2837 | /* Call F on X. */ | |
2838 | x = &XEXP (exp, n); | |
2839 | result = (*f) (x, data); | |
2840 | if (result == -1) | |
2841 | /* Do not traverse sub-expressions. */ | |
2842 | continue; | |
2843 | else if (result != 0) | |
2844 | /* Stop the traversal. */ | |
2845 | return result; | |
48e1416a | 2846 | |
a87cf6e5 | 2847 | if (*x == NULL_RTX) |
2848 | /* There are no sub-expressions. */ | |
2849 | continue; | |
48e1416a | 2850 | |
a87cf6e5 | 2851 | i = non_rtx_starting_operands[GET_CODE (*x)]; |
2852 | if (i >= 0) | |
2853 | { | |
2854 | result = for_each_rtx_1 (*x, i, f, data); | |
2855 | if (result != 0) | |
2856 | return result; | |
2857 | } | |
2858 | break; | |
2859 | ||
2860 | case 'V': | |
2861 | case 'E': | |
2862 | if (XVEC (exp, n) == 0) | |
2863 | continue; | |
2864 | for (j = 0; j < XVECLEN (exp, n); ++j) | |
2865 | { | |
2866 | /* Call F on X. */ | |
2867 | x = &XVECEXP (exp, n, j); | |
2868 | result = (*f) (x, data); | |
2869 | if (result == -1) | |
2870 | /* Do not traverse sub-expressions. */ | |
2871 | continue; | |
2872 | else if (result != 0) | |
2873 | /* Stop the traversal. */ | |
2874 | return result; | |
48e1416a | 2875 | |
a87cf6e5 | 2876 | if (*x == NULL_RTX) |
2877 | /* There are no sub-expressions. */ | |
2878 | continue; | |
48e1416a | 2879 | |
a87cf6e5 | 2880 | i = non_rtx_starting_operands[GET_CODE (*x)]; |
2881 | if (i >= 0) | |
2882 | { | |
2883 | result = for_each_rtx_1 (*x, i, f, data); | |
2884 | if (result != 0) | |
2885 | return result; | |
2886 | } | |
2887 | } | |
2888 | break; | |
2889 | ||
2890 | default: | |
2891 | /* Nothing to do. */ | |
2892 | break; | |
2893 | } | |
2894 | } | |
2895 | ||
2896 | return 0; | |
2897 | } | |
2898 | ||
fb8acade | 2899 | /* Traverse X via depth-first search, calling F for each |
2900 | sub-expression (including X itself). F is also passed the DATA. | |
2901 | If F returns -1, do not traverse sub-expressions, but continue | |
2902 | traversing the rest of the tree. If F ever returns any other | |
7fd957fe | 2903 | nonzero value, stop the traversal, and return the value returned |
fb8acade | 2904 | by F. Otherwise, return 0. This function does not traverse inside |
2905 | tree structure that contains RTX_EXPRs, or into sub-expressions | |
2906 | whose format code is `0' since it is not known whether or not those | |
2907 | codes are actually RTL. | |
2908 | ||
2909 | This routine is very general, and could (should?) be used to | |
2910 | implement many of the other routines in this file. */ | |
2911 | ||
7cc785dd | 2912 | int |
3ad4992f | 2913 | for_each_rtx (rtx *x, rtx_function f, void *data) |
fb8acade | 2914 | { |
2915 | int result; | |
fb8acade | 2916 | int i; |
2917 | ||
2918 | /* Call F on X. */ | |
5ccb94d7 | 2919 | result = (*f) (x, data); |
fb8acade | 2920 | if (result == -1) |
2921 | /* Do not traverse sub-expressions. */ | |
2922 | return 0; | |
2923 | else if (result != 0) | |
2924 | /* Stop the traversal. */ | |
2925 | return result; | |
2926 | ||
2927 | if (*x == NULL_RTX) | |
2928 | /* There are no sub-expressions. */ | |
2929 | return 0; | |
2930 | ||
a87cf6e5 | 2931 | i = non_rtx_starting_operands[GET_CODE (*x)]; |
2932 | if (i < 0) | |
2933 | return 0; | |
fb8acade | 2934 | |
a87cf6e5 | 2935 | return for_each_rtx_1 (*x, i, f, data); |
fb8acade | 2936 | } |
8bd88b68 | 2937 | |
1f864115 | 2938 | \f |
2939 | ||
2940 | /* Data structure that holds the internal state communicated between | |
2941 | for_each_inc_dec, for_each_inc_dec_find_mem and | |
2942 | for_each_inc_dec_find_inc_dec. */ | |
2943 | ||
2944 | struct for_each_inc_dec_ops { | |
2945 | /* The function to be called for each autoinc operation found. */ | |
2946 | for_each_inc_dec_fn fn; | |
2947 | /* The opaque argument to be passed to it. */ | |
2948 | void *arg; | |
2949 | /* The MEM we're visiting, if any. */ | |
2950 | rtx mem; | |
2951 | }; | |
2952 | ||
2953 | static int for_each_inc_dec_find_mem (rtx *r, void *d); | |
2954 | ||
2955 | /* Find PRE/POST-INC/DEC/MODIFY operations within *R, extract the | |
2956 | operands of the equivalent add insn and pass the result to the | |
2957 | operator specified by *D. */ | |
2958 | ||
2959 | static int | |
2960 | for_each_inc_dec_find_inc_dec (rtx *r, void *d) | |
2961 | { | |
2962 | rtx x = *r; | |
2963 | struct for_each_inc_dec_ops *data = (struct for_each_inc_dec_ops *)d; | |
a87cf6e5 | 2964 | |
1f864115 | 2965 | switch (GET_CODE (x)) |
2966 | { | |
2967 | case PRE_INC: | |
2968 | case POST_INC: | |
2969 | { | |
2970 | int size = GET_MODE_SIZE (GET_MODE (data->mem)); | |
2971 | rtx r1 = XEXP (x, 0); | |
2972 | rtx c = gen_int_mode (size, GET_MODE (r1)); | |
2973 | return data->fn (data->mem, x, r1, r1, c, data->arg); | |
2974 | } | |
2975 | ||
2976 | case PRE_DEC: | |
2977 | case POST_DEC: | |
2978 | { | |
2979 | int size = GET_MODE_SIZE (GET_MODE (data->mem)); | |
2980 | rtx r1 = XEXP (x, 0); | |
2981 | rtx c = gen_int_mode (-size, GET_MODE (r1)); | |
2982 | return data->fn (data->mem, x, r1, r1, c, data->arg); | |
2983 | } | |
2984 | ||
2985 | case PRE_MODIFY: | |
2986 | case POST_MODIFY: | |
2987 | { | |
2988 | rtx r1 = XEXP (x, 0); | |
2989 | rtx add = XEXP (x, 1); | |
2990 | return data->fn (data->mem, x, r1, add, NULL, data->arg); | |
2991 | } | |
2992 | ||
2993 | case MEM: | |
2994 | { | |
2995 | rtx save = data->mem; | |
2996 | int ret = for_each_inc_dec_find_mem (r, d); | |
2997 | data->mem = save; | |
2998 | return ret; | |
2999 | } | |
3000 | ||
3001 | default: | |
3002 | return 0; | |
3003 | } | |
3004 | } | |
3005 | ||
3006 | /* If *R is a MEM, find PRE/POST-INC/DEC/MODIFY operations within its | |
3007 | address, extract the operands of the equivalent add insn and pass | |
3008 | the result to the operator specified by *D. */ | |
3009 | ||
3010 | static int | |
3011 | for_each_inc_dec_find_mem (rtx *r, void *d) | |
3012 | { | |
3013 | rtx x = *r; | |
3014 | if (x != NULL_RTX && MEM_P (x)) | |
3015 | { | |
3016 | struct for_each_inc_dec_ops *data = (struct for_each_inc_dec_ops *) d; | |
3017 | int result; | |
3018 | ||
3019 | data->mem = x; | |
3020 | ||
3021 | result = for_each_rtx (&XEXP (x, 0), for_each_inc_dec_find_inc_dec, | |
3022 | data); | |
3023 | if (result) | |
3024 | return result; | |
3025 | ||
3026 | return -1; | |
3027 | } | |
3028 | return 0; | |
3029 | } | |
3030 | ||
3031 | /* Traverse *X looking for MEMs, and for autoinc operations within | |
3032 | them. For each such autoinc operation found, call FN, passing it | |
3033 | the innermost enclosing MEM, the operation itself, the RTX modified | |
3034 | by the operation, two RTXs (the second may be NULL) that, once | |
3035 | added, represent the value to be held by the modified RTX | |
3036 | afterwards, and ARG. FN is to return -1 to skip looking for other | |
3037 | autoinc operations within the visited operation, 0 to continue the | |
3038 | traversal, or any other value to have it returned to the caller of | |
3039 | for_each_inc_dec. */ | |
3040 | ||
3041 | int | |
3042 | for_each_inc_dec (rtx *x, | |
3043 | for_each_inc_dec_fn fn, | |
3044 | void *arg) | |
3045 | { | |
3046 | struct for_each_inc_dec_ops data; | |
3047 | ||
3048 | data.fn = fn; | |
3049 | data.arg = arg; | |
3050 | data.mem = NULL; | |
3051 | ||
3052 | return for_each_rtx (x, for_each_inc_dec_find_mem, &data); | |
3053 | } | |
3054 | ||
3055 | \f | |
0919e10f | 3056 | /* Searches X for any reference to REGNO, returning the rtx of the |
3057 | reference found if any. Otherwise, returns NULL_RTX. */ | |
3058 | ||
3059 | rtx | |
3ad4992f | 3060 | regno_use_in (unsigned int regno, rtx x) |
0919e10f | 3061 | { |
19cb6b50 | 3062 | const char *fmt; |
0919e10f | 3063 | int i, j; |
3064 | rtx tem; | |
3065 | ||
8ad4c111 | 3066 | if (REG_P (x) && REGNO (x) == regno) |
0919e10f | 3067 | return x; |
3068 | ||
3069 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
3070 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
3071 | { | |
3072 | if (fmt[i] == 'e') | |
3073 | { | |
3074 | if ((tem = regno_use_in (regno, XEXP (x, i)))) | |
3075 | return tem; | |
3076 | } | |
3077 | else if (fmt[i] == 'E') | |
3078 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3079 | if ((tem = regno_use_in (regno , XVECEXP (x, i, j)))) | |
3080 | return tem; | |
3081 | } | |
3082 | ||
3083 | return NULL_RTX; | |
3084 | } | |
c4f0a530 | 3085 | |
09f800b9 | 3086 | /* Return a value indicating whether OP, an operand of a commutative |
3087 | operation, is preferred as the first or second operand. The higher | |
3088 | the value, the stronger the preference for being the first operand. | |
3089 | We use negative values to indicate a preference for the first operand | |
3090 | and positive values for the second operand. */ | |
3091 | ||
f4ad60b7 | 3092 | int |
3ad4992f | 3093 | commutative_operand_precedence (rtx op) |
09f800b9 | 3094 | { |
b147a3b4 | 3095 | enum rtx_code code = GET_CODE (op); |
48e1416a | 3096 | |
09f800b9 | 3097 | /* Constants always come the second operand. Prefer "nice" constants. */ |
b147a3b4 | 3098 | if (code == CONST_INT) |
1f3b83af | 3099 | return -8; |
b147a3b4 | 3100 | if (code == CONST_DOUBLE) |
1f3b83af | 3101 | return -7; |
e397ad8e | 3102 | if (code == CONST_FIXED) |
3103 | return -7; | |
efbc8128 | 3104 | op = avoid_constant_pool_reference (op); |
57260f80 | 3105 | code = GET_CODE (op); |
6720e96c | 3106 | |
3107 | switch (GET_RTX_CLASS (code)) | |
3108 | { | |
3109 | case RTX_CONST_OBJ: | |
3110 | if (code == CONST_INT) | |
1f3b83af | 3111 | return -6; |
6720e96c | 3112 | if (code == CONST_DOUBLE) |
1f3b83af | 3113 | return -5; |
e397ad8e | 3114 | if (code == CONST_FIXED) |
3115 | return -5; | |
1f3b83af | 3116 | return -4; |
6720e96c | 3117 | |
3118 | case RTX_EXTRA: | |
3119 | /* SUBREGs of objects should come second. */ | |
3120 | if (code == SUBREG && OBJECT_P (SUBREG_REG (op))) | |
1f3b83af | 3121 | return -3; |
3072d30e | 3122 | return 0; |
6720e96c | 3123 | |
3124 | case RTX_OBJ: | |
3125 | /* Complex expressions should be the first, so decrease priority | |
1f3b83af | 3126 | of objects. Prefer pointer objects over non pointer objects. */ |
3127 | if ((REG_P (op) && REG_POINTER (op)) | |
3128 | || (MEM_P (op) && MEM_POINTER (op))) | |
3129 | return -1; | |
3130 | return -2; | |
6720e96c | 3131 | |
3132 | case RTX_COMM_ARITH: | |
3133 | /* Prefer operands that are themselves commutative to be first. | |
3134 | This helps to make things linear. In particular, | |
3135 | (and (and (reg) (reg)) (not (reg))) is canonical. */ | |
3136 | return 4; | |
3137 | ||
3138 | case RTX_BIN_ARITH: | |
3139 | /* If only one operand is a binary expression, it will be the first | |
3140 | operand. In particular, (plus (minus (reg) (reg)) (neg (reg))) | |
3141 | is canonical, although it will usually be further simplified. */ | |
3142 | return 2; | |
48e1416a | 3143 | |
6720e96c | 3144 | case RTX_UNARY: |
3145 | /* Then prefer NEG and NOT. */ | |
3146 | if (code == NEG || code == NOT) | |
3147 | return 1; | |
09f800b9 | 3148 | |
6720e96c | 3149 | default: |
3150 | return 0; | |
3151 | } | |
09f800b9 | 3152 | } |
3153 | ||
dd5b4b36 | 3154 | /* Return 1 iff it is necessary to swap operands of commutative operation |
09f800b9 | 3155 | in order to canonicalize expression. */ |
3156 | ||
1f3b83af | 3157 | bool |
3ad4992f | 3158 | swap_commutative_operands_p (rtx x, rtx y) |
09f800b9 | 3159 | { |
f4ad60b7 | 3160 | return (commutative_operand_precedence (x) |
3161 | < commutative_operand_precedence (y)); | |
09f800b9 | 3162 | } |
c4f0a530 | 3163 | |
3164 | /* Return 1 if X is an autoincrement side effect and the register is | |
3165 | not the stack pointer. */ | |
3166 | int | |
dd9b9fc5 | 3167 | auto_inc_p (const_rtx x) |
c4f0a530 | 3168 | { |
3169 | switch (GET_CODE (x)) | |
3170 | { | |
3171 | case PRE_INC: | |
3172 | case POST_INC: | |
3173 | case PRE_DEC: | |
3174 | case POST_DEC: | |
3175 | case PRE_MODIFY: | |
3176 | case POST_MODIFY: | |
3177 | /* There are no REG_INC notes for SP. */ | |
3178 | if (XEXP (x, 0) != stack_pointer_rtx) | |
3179 | return 1; | |
3180 | default: | |
3181 | break; | |
3182 | } | |
3183 | return 0; | |
3184 | } | |
b067e925 | 3185 | |
2358393e | 3186 | /* Return nonzero if IN contains a piece of rtl that has the address LOC. */ |
2c663070 | 3187 | int |
dd9b9fc5 | 3188 | loc_mentioned_in_p (rtx *loc, const_rtx in) |
2c663070 | 3189 | { |
42a3a38b | 3190 | enum rtx_code code; |
3191 | const char *fmt; | |
2c663070 | 3192 | int i, j; |
3193 | ||
42a3a38b | 3194 | if (!in) |
3195 | return 0; | |
3196 | ||
3197 | code = GET_CODE (in); | |
3198 | fmt = GET_RTX_FORMAT (code); | |
2c663070 | 3199 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
3200 | { | |
2c663070 | 3201 | if (fmt[i] == 'e') |
3202 | { | |
c8707f08 | 3203 | if (loc == &XEXP (in, i) || loc_mentioned_in_p (loc, XEXP (in, i))) |
2c663070 | 3204 | return 1; |
3205 | } | |
3206 | else if (fmt[i] == 'E') | |
3207 | for (j = XVECLEN (in, i) - 1; j >= 0; j--) | |
c8707f08 | 3208 | if (loc == &XVECEXP (in, i, j) |
3209 | || loc_mentioned_in_p (loc, XVECEXP (in, i, j))) | |
2c663070 | 3210 | return 1; |
3211 | } | |
3212 | return 0; | |
3213 | } | |
701e46d0 | 3214 | |
f36eb1e9 | 3215 | /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE, |
3216 | and SUBREG_BYTE, return the bit offset where the subreg begins | |
3217 | (counting from the least significant bit of the operand). */ | |
ef4e6755 | 3218 | |
3219 | unsigned int | |
f36eb1e9 | 3220 | subreg_lsb_1 (enum machine_mode outer_mode, |
3221 | enum machine_mode inner_mode, | |
3222 | unsigned int subreg_byte) | |
ef4e6755 | 3223 | { |
ef4e6755 | 3224 | unsigned int bitpos; |
3225 | unsigned int byte; | |
3226 | unsigned int word; | |
3227 | ||
3228 | /* A paradoxical subreg begins at bit position 0. */ | |
ded805e6 | 3229 | if (GET_MODE_PRECISION (outer_mode) > GET_MODE_PRECISION (inner_mode)) |
ef4e6755 | 3230 | return 0; |
3231 | ||
3232 | if (WORDS_BIG_ENDIAN != BYTES_BIG_ENDIAN) | |
3233 | /* If the subreg crosses a word boundary ensure that | |
3234 | it also begins and ends on a word boundary. */ | |
04e579b6 | 3235 | gcc_assert (!((subreg_byte % UNITS_PER_WORD |
3236 | + GET_MODE_SIZE (outer_mode)) > UNITS_PER_WORD | |
3237 | && (subreg_byte % UNITS_PER_WORD | |
3238 | || GET_MODE_SIZE (outer_mode) % UNITS_PER_WORD))); | |
ef4e6755 | 3239 | |
3240 | if (WORDS_BIG_ENDIAN) | |
3241 | word = (GET_MODE_SIZE (inner_mode) | |
f36eb1e9 | 3242 | - (subreg_byte + GET_MODE_SIZE (outer_mode))) / UNITS_PER_WORD; |
ef4e6755 | 3243 | else |
f36eb1e9 | 3244 | word = subreg_byte / UNITS_PER_WORD; |
ef4e6755 | 3245 | bitpos = word * BITS_PER_WORD; |
3246 | ||
3247 | if (BYTES_BIG_ENDIAN) | |
3248 | byte = (GET_MODE_SIZE (inner_mode) | |
f36eb1e9 | 3249 | - (subreg_byte + GET_MODE_SIZE (outer_mode))) % UNITS_PER_WORD; |
ef4e6755 | 3250 | else |
f36eb1e9 | 3251 | byte = subreg_byte % UNITS_PER_WORD; |
ef4e6755 | 3252 | bitpos += byte * BITS_PER_UNIT; |
3253 | ||
3254 | return bitpos; | |
3255 | } | |
3256 | ||
f36eb1e9 | 3257 | /* Given a subreg X, return the bit offset where the subreg begins |
3258 | (counting from the least significant bit of the reg). */ | |
3259 | ||
3260 | unsigned int | |
dd9b9fc5 | 3261 | subreg_lsb (const_rtx x) |
f36eb1e9 | 3262 | { |
3263 | return subreg_lsb_1 (GET_MODE (x), GET_MODE (SUBREG_REG (x)), | |
3264 | SUBREG_BYTE (x)); | |
3265 | } | |
3266 | ||
fe2ebfc8 | 3267 | /* Fill in information about a subreg of a hard register. |
701e46d0 | 3268 | xregno - A regno of an inner hard subreg_reg (or what will become one). |
3269 | xmode - The mode of xregno. | |
3270 | offset - The byte offset. | |
3271 | ymode - The mode of a top level SUBREG (or what may become one). | |
fe2ebfc8 | 3272 | info - Pointer to structure to fill in. */ |
9680c846 | 3273 | void |
fe2ebfc8 | 3274 | subreg_get_info (unsigned int xregno, enum machine_mode xmode, |
3275 | unsigned int offset, enum machine_mode ymode, | |
3276 | struct subreg_info *info) | |
d9b3752c | 3277 | { |
695595bc | 3278 | int nregs_xmode, nregs_ymode; |
d9b3752c | 3279 | int mode_multiple, nregs_multiple; |
fe2ebfc8 | 3280 | int offset_adj, y_offset, y_offset_adj; |
695595bc | 3281 | int regsize_xmode, regsize_ymode; |
fe2ebfc8 | 3282 | bool rknown; |
d9b3752c | 3283 | |
04e579b6 | 3284 | gcc_assert (xregno < FIRST_PSEUDO_REGISTER); |
d9b3752c | 3285 | |
fe2ebfc8 | 3286 | rknown = false; |
3287 | ||
ed21e7ff | 3288 | /* If there are holes in a non-scalar mode in registers, we expect |
3289 | that it is made up of its units concatenated together. */ | |
695595bc | 3290 | if (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)) |
ed21e7ff | 3291 | { |
695595bc | 3292 | enum machine_mode xmode_unit; |
3293 | ||
3294 | nregs_xmode = HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode); | |
3295 | if (GET_MODE_INNER (xmode) == VOIDmode) | |
3296 | xmode_unit = xmode; | |
3297 | else | |
3298 | xmode_unit = GET_MODE_INNER (xmode); | |
3299 | gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode_unit)); | |
3300 | gcc_assert (nregs_xmode | |
3301 | == (GET_MODE_NUNITS (xmode) | |
3302 | * HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode_unit))); | |
3303 | gcc_assert (hard_regno_nregs[xregno][xmode] | |
3304 | == (hard_regno_nregs[xregno][xmode_unit] | |
3305 | * GET_MODE_NUNITS (xmode))); | |
ed21e7ff | 3306 | |
3307 | /* You can only ask for a SUBREG of a value with holes in the middle | |
3308 | if you don't cross the holes. (Such a SUBREG should be done by | |
3309 | picking a different register class, or doing it in memory if | |
3310 | necessary.) An example of a value with holes is XCmode on 32-bit | |
3311 | x86 with -m128bit-long-double; it's represented in 6 32-bit registers, | |
48e1416a | 3312 | 3 for each part, but in memory it's two 128-bit parts. |
ed21e7ff | 3313 | Padding is assumed to be at the end (not necessarily the 'high part') |
3314 | of each unit. */ | |
48e1416a | 3315 | if ((offset / GET_MODE_SIZE (xmode_unit) + 1 |
695595bc | 3316 | < GET_MODE_NUNITS (xmode)) |
3317 | && (offset / GET_MODE_SIZE (xmode_unit) | |
ed21e7ff | 3318 | != ((offset + GET_MODE_SIZE (ymode) - 1) |
695595bc | 3319 | / GET_MODE_SIZE (xmode_unit)))) |
fe2ebfc8 | 3320 | { |
3321 | info->representable_p = false; | |
3322 | rknown = true; | |
3323 | } | |
ed21e7ff | 3324 | } |
3325 | else | |
3326 | nregs_xmode = hard_regno_nregs[xregno][xmode]; | |
48e1416a | 3327 | |
67d6c12b | 3328 | nregs_ymode = hard_regno_nregs[xregno][ymode]; |
d9b3752c | 3329 | |
ed21e7ff | 3330 | /* Paradoxical subregs are otherwise valid. */ |
fe2ebfc8 | 3331 | if (!rknown |
3332 | && offset == 0 | |
ded805e6 | 3333 | && GET_MODE_PRECISION (ymode) > GET_MODE_PRECISION (xmode)) |
fe2ebfc8 | 3334 | { |
3335 | info->representable_p = true; | |
3336 | /* If this is a big endian paradoxical subreg, which uses more | |
3337 | actual hard registers than the original register, we must | |
3338 | return a negative offset so that we find the proper highpart | |
3339 | of the register. */ | |
3340 | if (GET_MODE_SIZE (ymode) > UNITS_PER_WORD | |
76c64076 | 3341 | ? REG_WORDS_BIG_ENDIAN : BYTES_BIG_ENDIAN) |
fe2ebfc8 | 3342 | info->offset = nregs_xmode - nregs_ymode; |
3343 | else | |
3344 | info->offset = 0; | |
3345 | info->nregs = nregs_ymode; | |
3346 | return; | |
3347 | } | |
d9b3752c | 3348 | |
695595bc | 3349 | /* If registers store different numbers of bits in the different |
3350 | modes, we cannot generally form this subreg. */ | |
fe2ebfc8 | 3351 | if (!HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode) |
a100ece7 | 3352 | && !HARD_REGNO_NREGS_HAS_PADDING (xregno, ymode) |
3353 | && (GET_MODE_SIZE (xmode) % nregs_xmode) == 0 | |
3354 | && (GET_MODE_SIZE (ymode) % nregs_ymode) == 0) | |
fe2ebfc8 | 3355 | { |
3356 | regsize_xmode = GET_MODE_SIZE (xmode) / nregs_xmode; | |
fe2ebfc8 | 3357 | regsize_ymode = GET_MODE_SIZE (ymode) / nregs_ymode; |
fe2ebfc8 | 3358 | if (!rknown && regsize_xmode > regsize_ymode && nregs_ymode > 1) |
3359 | { | |
3360 | info->representable_p = false; | |
3361 | info->nregs | |
3362 | = (GET_MODE_SIZE (ymode) + regsize_xmode - 1) / regsize_xmode; | |
3363 | info->offset = offset / regsize_xmode; | |
3364 | return; | |
3365 | } | |
3366 | if (!rknown && regsize_ymode > regsize_xmode && nregs_xmode > 1) | |
3367 | { | |
3368 | info->representable_p = false; | |
3369 | info->nregs | |
3370 | = (GET_MODE_SIZE (ymode) + regsize_xmode - 1) / regsize_xmode; | |
3371 | info->offset = offset / regsize_xmode; | |
3372 | return; | |
3373 | } | |
3374 | } | |
695595bc | 3375 | |
ed21e7ff | 3376 | /* Lowpart subregs are otherwise valid. */ |
fe2ebfc8 | 3377 | if (!rknown && offset == subreg_lowpart_offset (ymode, xmode)) |
3378 | { | |
3379 | info->representable_p = true; | |
3380 | rknown = true; | |
8ef3d190 | 3381 | |
3382 | if (offset == 0 || nregs_xmode == nregs_ymode) | |
3383 | { | |
3384 | info->offset = 0; | |
3385 | info->nregs = nregs_ymode; | |
3386 | return; | |
3387 | } | |
fe2ebfc8 | 3388 | } |
d9b3752c | 3389 | |
ed21e7ff | 3390 | /* This should always pass, otherwise we don't know how to verify |
3391 | the constraint. These conditions may be relaxed but | |
3392 | subreg_regno_offset would need to be redesigned. */ | |
04e579b6 | 3393 | gcc_assert ((GET_MODE_SIZE (xmode) % GET_MODE_SIZE (ymode)) == 0); |
04e579b6 | 3394 | gcc_assert ((nregs_xmode % nregs_ymode) == 0); |
d9b3752c | 3395 | |
76c64076 | 3396 | if (WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN |
3397 | && GET_MODE_SIZE (xmode) > UNITS_PER_WORD) | |
3398 | { | |
3399 | HOST_WIDE_INT xsize = GET_MODE_SIZE (xmode); | |
3400 | HOST_WIDE_INT ysize = GET_MODE_SIZE (ymode); | |
3401 | HOST_WIDE_INT off_low = offset & (ysize - 1); | |
3402 | HOST_WIDE_INT off_high = offset & ~(ysize - 1); | |
3403 | offset = (xsize - ysize - off_high) | off_low; | |
3404 | } | |
df07c3ae | 3405 | /* The XMODE value can be seen as a vector of NREGS_XMODE |
845bebef | 3406 | values. The subreg must represent a lowpart of given field. |
d9b3752c | 3407 | Compute what field it is. */ |
fe2ebfc8 | 3408 | offset_adj = offset; |
3409 | offset_adj -= subreg_lowpart_offset (ymode, | |
3410 | mode_for_size (GET_MODE_BITSIZE (xmode) | |
3411 | / nregs_xmode, | |
3412 | MODE_INT, 0)); | |
d9b3752c | 3413 | |
ed21e7ff | 3414 | /* Size of ymode must not be greater than the size of xmode. */ |
d9b3752c | 3415 | mode_multiple = GET_MODE_SIZE (xmode) / GET_MODE_SIZE (ymode); |
04e579b6 | 3416 | gcc_assert (mode_multiple != 0); |
d9b3752c | 3417 | |
3418 | y_offset = offset / GET_MODE_SIZE (ymode); | |
fe2ebfc8 | 3419 | y_offset_adj = offset_adj / GET_MODE_SIZE (ymode); |
3420 | nregs_multiple = nregs_xmode / nregs_ymode; | |
04e579b6 | 3421 | |
fe2ebfc8 | 3422 | gcc_assert ((offset_adj % GET_MODE_SIZE (ymode)) == 0); |
04e579b6 | 3423 | gcc_assert ((mode_multiple % nregs_multiple) == 0); |
3424 | ||
fe2ebfc8 | 3425 | if (!rknown) |
3426 | { | |
3427 | info->representable_p = (!(y_offset_adj % (mode_multiple / nregs_multiple))); | |
3428 | rknown = true; | |
3429 | } | |
3430 | info->offset = (y_offset / (mode_multiple / nregs_multiple)) * nregs_ymode; | |
3431 | info->nregs = nregs_ymode; | |
3432 | } | |
3433 | ||
3434 | /* This function returns the regno offset of a subreg expression. | |
3435 | xregno - A regno of an inner hard subreg_reg (or what will become one). | |
3436 | xmode - The mode of xregno. | |
3437 | offset - The byte offset. | |
3438 | ymode - The mode of a top level SUBREG (or what may become one). | |
3439 | RETURN - The regno offset which would be used. */ | |
3440 | unsigned int | |
3441 | subreg_regno_offset (unsigned int xregno, enum machine_mode xmode, | |
3442 | unsigned int offset, enum machine_mode ymode) | |
3443 | { | |
3444 | struct subreg_info info; | |
3445 | subreg_get_info (xregno, xmode, offset, ymode, &info); | |
3446 | return info.offset; | |
3447 | } | |
3448 | ||
3449 | /* This function returns true when the offset is representable via | |
3450 | subreg_offset in the given regno. | |
3451 | xregno - A regno of an inner hard subreg_reg (or what will become one). | |
3452 | xmode - The mode of xregno. | |
3453 | offset - The byte offset. | |
3454 | ymode - The mode of a top level SUBREG (or what may become one). | |
3455 | RETURN - Whether the offset is representable. */ | |
3456 | bool | |
3457 | subreg_offset_representable_p (unsigned int xregno, enum machine_mode xmode, | |
3458 | unsigned int offset, enum machine_mode ymode) | |
3459 | { | |
3460 | struct subreg_info info; | |
3461 | subreg_get_info (xregno, xmode, offset, ymode, &info); | |
949bf6a9 | 3462 | return info.representable_p; |
d9b3752c | 3463 | } |
3464 | ||
5992d16a | 3465 | /* Return the number of a YMODE register to which |
3466 | ||
3467 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET) | |
3468 | ||
3469 | can be simplified. Return -1 if the subreg can't be simplified. | |
3470 | ||
3471 | XREGNO is a hard register number. */ | |
3472 | ||
3473 | int | |
3474 | simplify_subreg_regno (unsigned int xregno, enum machine_mode xmode, | |
3475 | unsigned int offset, enum machine_mode ymode) | |
3476 | { | |
3477 | struct subreg_info info; | |
3478 | unsigned int yregno; | |
3479 | ||
3480 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
3481 | /* Give the backend a chance to disallow the mode change. */ | |
3482 | if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT | |
3483 | && GET_MODE_CLASS (xmode) != MODE_COMPLEX_FLOAT | |
c6a6cdaa | 3484 | && REG_CANNOT_CHANGE_MODE_P (xregno, xmode, ymode) |
3485 | /* We can use mode change in LRA for some transformations. */ | |
3486 | && ! lra_in_progress) | |
5992d16a | 3487 | return -1; |
3488 | #endif | |
3489 | ||
3490 | /* We shouldn't simplify stack-related registers. */ | |
3491 | if ((!reload_completed || frame_pointer_needed) | |
c461d390 | 3492 | && xregno == FRAME_POINTER_REGNUM) |
5992d16a | 3493 | return -1; |
3494 | ||
3495 | if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
c6a6cdaa | 3496 | /* We should convert arg register in LRA after the elimination |
3497 | if it is possible. */ | |
3498 | && xregno == ARG_POINTER_REGNUM | |
3499 | && ! lra_in_progress) | |
5992d16a | 3500 | return -1; |
3501 | ||
c6a6cdaa | 3502 | if (xregno == STACK_POINTER_REGNUM |
3503 | /* We should convert hard stack register in LRA if it is | |
3504 | possible. */ | |
3505 | && ! lra_in_progress) | |
5992d16a | 3506 | return -1; |
3507 | ||
3508 | /* Try to get the register offset. */ | |
3509 | subreg_get_info (xregno, xmode, offset, ymode, &info); | |
3510 | if (!info.representable_p) | |
3511 | return -1; | |
3512 | ||
3513 | /* Make sure that the offsetted register value is in range. */ | |
3514 | yregno = xregno + info.offset; | |
3515 | if (!HARD_REGISTER_NUM_P (yregno)) | |
3516 | return -1; | |
3517 | ||
3518 | /* See whether (reg:YMODE YREGNO) is valid. | |
3519 | ||
3520 | ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid. | |
7cb63246 | 3521 | This is a kludge to work around how complex FP arguments are passed |
3522 | on IA-64 and should be fixed. See PR target/49226. */ | |
5992d16a | 3523 | if (!HARD_REGNO_MODE_OK (yregno, ymode) |
3524 | && HARD_REGNO_MODE_OK (xregno, xmode)) | |
3525 | return -1; | |
3526 | ||
3527 | return (int) yregno; | |
3528 | } | |
3529 | ||
aa40f561 | 3530 | /* Return the final regno that a subreg expression refers to. */ |
2617fe26 | 3531 | unsigned int |
dd9b9fc5 | 3532 | subreg_regno (const_rtx x) |
701e46d0 | 3533 | { |
3534 | unsigned int ret; | |
3535 | rtx subreg = SUBREG_REG (x); | |
3536 | int regno = REGNO (subreg); | |
3537 | ||
2617fe26 | 3538 | ret = regno + subreg_regno_offset (regno, |
3539 | GET_MODE (subreg), | |
701e46d0 | 3540 | SUBREG_BYTE (x), |
3541 | GET_MODE (x)); | |
3542 | return ret; | |
3543 | ||
3544 | } | |
fe2ebfc8 | 3545 | |
3546 | /* Return the number of registers that a subreg expression refers | |
3547 | to. */ | |
3548 | unsigned int | |
dd9b9fc5 | 3549 | subreg_nregs (const_rtx x) |
dea7b504 | 3550 | { |
3551 | return subreg_nregs_with_regno (REGNO (SUBREG_REG (x)), x); | |
3552 | } | |
3553 | ||
3554 | /* Return the number of registers that a subreg REG with REGNO | |
3555 | expression refers to. This is a copy of the rtlanal.c:subreg_nregs | |
3556 | changed so that the regno can be passed in. */ | |
3557 | ||
3558 | unsigned int | |
3559 | subreg_nregs_with_regno (unsigned int regno, const_rtx x) | |
fe2ebfc8 | 3560 | { |
3561 | struct subreg_info info; | |
3562 | rtx subreg = SUBREG_REG (x); | |
fe2ebfc8 | 3563 | |
3564 | subreg_get_info (regno, GET_MODE (subreg), SUBREG_BYTE (x), GET_MODE (x), | |
3565 | &info); | |
3566 | return info.nregs; | |
3567 | } | |
3568 | ||
dea7b504 | 3569 | |
7c2cc97e | 3570 | struct parms_set_data |
3571 | { | |
3572 | int nregs; | |
3573 | HARD_REG_SET regs; | |
3574 | }; | |
3575 | ||
3576 | /* Helper function for noticing stores to parameter registers. */ | |
3577 | static void | |
81a410b1 | 3578 | parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
7c2cc97e | 3579 | { |
f7f3687c | 3580 | struct parms_set_data *const d = (struct parms_set_data *) data; |
7c2cc97e | 3581 | if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER |
3582 | && TEST_HARD_REG_BIT (d->regs, REGNO (x))) | |
3583 | { | |
3584 | CLEAR_HARD_REG_BIT (d->regs, REGNO (x)); | |
3585 | d->nregs--; | |
3586 | } | |
3587 | } | |
3588 | ||
2617fe26 | 3589 | /* Look backward for first parameter to be loaded. |
a6971e98 | 3590 | Note that loads of all parameters will not necessarily be |
3591 | found if CSE has eliminated some of them (e.g., an argument | |
3592 | to the outer function is passed down as a parameter). | |
7c2cc97e | 3593 | Do not skip BOUNDARY. */ |
3594 | rtx | |
3ad4992f | 3595 | find_first_parameter_load (rtx call_insn, rtx boundary) |
7c2cc97e | 3596 | { |
3597 | struct parms_set_data parm; | |
a6971e98 | 3598 | rtx p, before, first_set; |
7c2cc97e | 3599 | |
3600 | /* Since different machines initialize their parameter registers | |
3601 | in different orders, assume nothing. Collect the set of all | |
3602 | parameter registers. */ | |
3603 | CLEAR_HARD_REG_SET (parm.regs); | |
3604 | parm.nregs = 0; | |
3605 | for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1)) | |
3606 | if (GET_CODE (XEXP (p, 0)) == USE | |
8ad4c111 | 3607 | && REG_P (XEXP (XEXP (p, 0), 0))) |
7c2cc97e | 3608 | { |
04e579b6 | 3609 | gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER); |
7c2cc97e | 3610 | |
3611 | /* We only care about registers which can hold function | |
3612 | arguments. */ | |
3613 | if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0)))) | |
3614 | continue; | |
3615 | ||
3616 | SET_HARD_REG_BIT (parm.regs, REGNO (XEXP (XEXP (p, 0), 0))); | |
3617 | parm.nregs++; | |
3618 | } | |
3619 | before = call_insn; | |
a6971e98 | 3620 | first_set = call_insn; |
7c2cc97e | 3621 | |
3622 | /* Search backward for the first set of a register in this set. */ | |
3623 | while (parm.nregs && before != boundary) | |
3624 | { | |
3625 | before = PREV_INSN (before); | |
3626 | ||
3627 | /* It is possible that some loads got CSEed from one call to | |
3628 | another. Stop in that case. */ | |
6d7dc5b9 | 3629 | if (CALL_P (before)) |
7c2cc97e | 3630 | break; |
3631 | ||
26551efd | 3632 | /* Our caller needs either ensure that we will find all sets |
7c2cc97e | 3633 | (in case code has not been optimized yet), or take care |
4a82352a | 3634 | for possible labels in a way by setting boundary to preceding |
7c2cc97e | 3635 | CODE_LABEL. */ |
6d7dc5b9 | 3636 | if (LABEL_P (before)) |
26551efd | 3637 | { |
04e579b6 | 3638 | gcc_assert (before == boundary); |
26551efd | 3639 | break; |
3640 | } | |
7c2cc97e | 3641 | |
bd10a7cd | 3642 | if (INSN_P (before)) |
a6971e98 | 3643 | { |
3644 | int nregs_old = parm.nregs; | |
3645 | note_stores (PATTERN (before), parms_set, &parm); | |
3646 | /* If we found something that did not set a parameter reg, | |
3647 | we're done. Do not keep going, as that might result | |
3648 | in hoisting an insn before the setting of a pseudo | |
3649 | that is used by the hoisted insn. */ | |
3650 | if (nregs_old != parm.nregs) | |
3651 | first_set = before; | |
3652 | else | |
3653 | break; | |
3654 | } | |
7c2cc97e | 3655 | } |
a6971e98 | 3656 | return first_set; |
7c2cc97e | 3657 | } |
fb20d6fa | 3658 | |
de132707 | 3659 | /* Return true if we should avoid inserting code between INSN and preceding |
fb20d6fa | 3660 | call instruction. */ |
3661 | ||
3662 | bool | |
5493cb9a | 3663 | keep_with_call_p (const_rtx insn) |
fb20d6fa | 3664 | { |
3665 | rtx set; | |
3666 | ||
3667 | if (INSN_P (insn) && (set = single_set (insn)) != NULL) | |
3668 | { | |
8ad4c111 | 3669 | if (REG_P (SET_DEST (set)) |
0c08cb26 | 3670 | && REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER |
fb20d6fa | 3671 | && fixed_regs[REGNO (SET_DEST (set))] |
3672 | && general_operand (SET_SRC (set), VOIDmode)) | |
3673 | return true; | |
8ad4c111 | 3674 | if (REG_P (SET_SRC (set)) |
e1ce1485 | 3675 | && targetm.calls.function_value_regno_p (REGNO (SET_SRC (set))) |
8ad4c111 | 3676 | && REG_P (SET_DEST (set)) |
fb20d6fa | 3677 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) |
3678 | return true; | |
aee989f5 | 3679 | /* There may be a stack pop just after the call and before the store |
3680 | of the return register. Search for the actual store when deciding | |
3681 | if we can break or not. */ | |
fb20d6fa | 3682 | if (SET_DEST (set) == stack_pointer_rtx) |
3683 | { | |
ce4469fa | 3684 | /* This CONST_CAST is okay because next_nonnote_insn just |
5ca94202 | 3685 | returns its argument and we assign it to a const_rtx |
ce4469fa | 3686 | variable. */ |
e47a6f81 | 3687 | const_rtx i2 = next_nonnote_insn (CONST_CAST_RTX(insn)); |
aee989f5 | 3688 | if (i2 && keep_with_call_p (i2)) |
fb20d6fa | 3689 | return true; |
3690 | } | |
3691 | } | |
3692 | return false; | |
3693 | } | |
fa3cb24d | 3694 | |
b9de5542 | 3695 | /* Return true if LABEL is a target of JUMP_INSN. This applies only |
3696 | to non-complex jumps. That is, direct unconditional, conditional, | |
3697 | and tablejumps, but not computed jumps or returns. It also does | |
3698 | not apply to the fallthru case of a conditional jump. */ | |
3699 | ||
3700 | bool | |
dd9b9fc5 | 3701 | label_is_jump_target_p (const_rtx label, const_rtx jump_insn) |
b9de5542 | 3702 | { |
3703 | rtx tmp = JUMP_LABEL (jump_insn); | |
3704 | ||
3705 | if (label == tmp) | |
3706 | return true; | |
3707 | ||
3708 | if (tablejump_p (jump_insn, NULL, &tmp)) | |
3709 | { | |
3710 | rtvec vec = XVEC (PATTERN (tmp), | |
3711 | GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC); | |
3712 | int i, veclen = GET_NUM_ELEM (vec); | |
3713 | ||
3714 | for (i = 0; i < veclen; ++i) | |
3715 | if (XEXP (RTVEC_ELT (vec, i), 0) == label) | |
3716 | return true; | |
3717 | } | |
3718 | ||
a8d1dae0 | 3719 | if (find_reg_note (jump_insn, REG_LABEL_TARGET, label)) |
3720 | return true; | |
3721 | ||
b9de5542 | 3722 | return false; |
3723 | } | |
3724 | ||
26619827 | 3725 | \f |
3726 | /* Return an estimate of the cost of computing rtx X. | |
3727 | One use is in cse, to decide which expression to keep in the hash table. | |
3728 | Another is in rtl generation, to pick the cheapest way to multiply. | |
48e1416a | 3729 | Other uses like the latter are expected in the future. |
f529eb25 | 3730 | |
20d892d1 | 3731 | X appears as operand OPNO in an expression with code OUTER_CODE. |
3732 | SPEED specifies whether costs optimized for speed or size should | |
f529eb25 | 3733 | be returned. */ |
26619827 | 3734 | |
3735 | int | |
20d892d1 | 3736 | rtx_cost (rtx x, enum rtx_code outer_code, int opno, bool speed) |
26619827 | 3737 | { |
3738 | int i, j; | |
3739 | enum rtx_code code; | |
3740 | const char *fmt; | |
3741 | int total; | |
3b3b530a | 3742 | int factor; |
26619827 | 3743 | |
3744 | if (x == 0) | |
3745 | return 0; | |
3746 | ||
3b3b530a | 3747 | /* A size N times larger than UNITS_PER_WORD likely needs N times as |
3748 | many insns, taking N times as long. */ | |
3749 | factor = GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD; | |
3750 | if (factor == 0) | |
3751 | factor = 1; | |
3752 | ||
26619827 | 3753 | /* Compute the default costs of certain things. |
3754 | Note that targetm.rtx_costs can override the defaults. */ | |
3755 | ||
3756 | code = GET_CODE (x); | |
3757 | switch (code) | |
3758 | { | |
3759 | case MULT: | |
3b3b530a | 3760 | /* Multiplication has time-complexity O(N*N), where N is the |
3761 | number of units (translated from digits) when using | |
3762 | schoolbook long multiplication. */ | |
3763 | total = factor * factor * COSTS_N_INSNS (5); | |
26619827 | 3764 | break; |
3765 | case DIV: | |
3766 | case UDIV: | |
3767 | case MOD: | |
3768 | case UMOD: | |
3b3b530a | 3769 | /* Similarly, complexity for schoolbook long division. */ |
3770 | total = factor * factor * COSTS_N_INSNS (7); | |
26619827 | 3771 | break; |
3772 | case USE: | |
67a5e20a | 3773 | /* Used in combine.c as a marker. */ |
26619827 | 3774 | total = 0; |
3775 | break; | |
3b3b530a | 3776 | case SET: |
3777 | /* A SET doesn't have a mode, so let's look at the SET_DEST to get | |
3778 | the mode for the factor. */ | |
3779 | factor = GET_MODE_SIZE (GET_MODE (SET_DEST (x))) / UNITS_PER_WORD; | |
3780 | if (factor == 0) | |
3781 | factor = 1; | |
3782 | /* Pass through. */ | |
26619827 | 3783 | default: |
3b3b530a | 3784 | total = factor * COSTS_N_INSNS (1); |
26619827 | 3785 | } |
3786 | ||
3787 | switch (code) | |
3788 | { | |
3789 | case REG: | |
3790 | return 0; | |
3791 | ||
3792 | case SUBREG: | |
8eb9bb0e | 3793 | total = 0; |
26619827 | 3794 | /* If we can't tie these modes, make this expensive. The larger |
3795 | the mode, the more expensive it is. */ | |
3796 | if (! MODES_TIEABLE_P (GET_MODE (x), GET_MODE (SUBREG_REG (x)))) | |
3b3b530a | 3797 | return COSTS_N_INSNS (2 + factor); |
26619827 | 3798 | break; |
3799 | ||
3800 | default: | |
20d892d1 | 3801 | if (targetm.rtx_costs (x, code, outer_code, opno, &total, speed)) |
26619827 | 3802 | return total; |
3803 | break; | |
3804 | } | |
3805 | ||
3806 | /* Sum the costs of the sub-rtx's, plus cost of this operation, | |
3807 | which is already in total. */ | |
3808 | ||
3809 | fmt = GET_RTX_FORMAT (code); | |
3810 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3811 | if (fmt[i] == 'e') | |
20d892d1 | 3812 | total += rtx_cost (XEXP (x, i), code, i, speed); |
26619827 | 3813 | else if (fmt[i] == 'E') |
3814 | for (j = 0; j < XVECLEN (x, i); j++) | |
20d892d1 | 3815 | total += rtx_cost (XVECEXP (x, i, j), code, i, speed); |
26619827 | 3816 | |
3817 | return total; | |
3818 | } | |
c9a03487 | 3819 | |
3820 | /* Fill in the structure C with information about both speed and size rtx | |
20d892d1 | 3821 | costs for X, which is operand OPNO in an expression with code OUTER. */ |
c9a03487 | 3822 | |
3823 | void | |
20d892d1 | 3824 | get_full_rtx_cost (rtx x, enum rtx_code outer, int opno, |
3825 | struct full_rtx_costs *c) | |
c9a03487 | 3826 | { |
20d892d1 | 3827 | c->speed = rtx_cost (x, outer, opno, true); |
3828 | c->size = rtx_cost (x, outer, opno, false); | |
c9a03487 | 3829 | } |
3830 | ||
26619827 | 3831 | \f |
3832 | /* Return cost of address expression X. | |
48e1416a | 3833 | Expect that X is properly formed address reference. |
f529eb25 | 3834 | |
3835 | SPEED parameter specify whether costs optimized for speed or size should | |
3836 | be returned. */ | |
26619827 | 3837 | |
3838 | int | |
bd1a81f7 | 3839 | address_cost (rtx x, enum machine_mode mode, addr_space_t as, bool speed) |
26619827 | 3840 | { |
26619827 | 3841 | /* We may be asked for cost of various unusual addresses, such as operands |
3842 | of push instruction. It is not worthwhile to complicate writing | |
3843 | of the target hook by such cases. */ | |
3844 | ||
bd1a81f7 | 3845 | if (!memory_address_addr_space_p (mode, x, as)) |
26619827 | 3846 | return 1000; |
3847 | ||
d9c5e5f4 | 3848 | return targetm.address_cost (x, mode, as, speed); |
26619827 | 3849 | } |
3850 | ||
3851 | /* If the target doesn't override, compute the cost as with arithmetic. */ | |
3852 | ||
3853 | int | |
d9c5e5f4 | 3854 | default_address_cost (rtx x, enum machine_mode, addr_space_t, bool speed) |
26619827 | 3855 | { |
20d892d1 | 3856 | return rtx_cost (x, MEM, 0, speed); |
26619827 | 3857 | } |
d263732c | 3858 | \f |
3859 | ||
3860 | unsigned HOST_WIDE_INT | |
b7bf20db | 3861 | nonzero_bits (const_rtx x, enum machine_mode mode) |
d263732c | 3862 | { |
3863 | return cached_nonzero_bits (x, mode, NULL_RTX, VOIDmode, 0); | |
3864 | } | |
3865 | ||
3866 | unsigned int | |
b7bf20db | 3867 | num_sign_bit_copies (const_rtx x, enum machine_mode mode) |
d263732c | 3868 | { |
3869 | return cached_num_sign_bit_copies (x, mode, NULL_RTX, VOIDmode, 0); | |
3870 | } | |
3871 | ||
3872 | /* The function cached_nonzero_bits is a wrapper around nonzero_bits1. | |
3873 | It avoids exponential behavior in nonzero_bits1 when X has | |
3874 | identical subexpressions on the first or the second level. */ | |
3875 | ||
3876 | static unsigned HOST_WIDE_INT | |
b7bf20db | 3877 | cached_nonzero_bits (const_rtx x, enum machine_mode mode, const_rtx known_x, |
d263732c | 3878 | enum machine_mode known_mode, |
3879 | unsigned HOST_WIDE_INT known_ret) | |
3880 | { | |
3881 | if (x == known_x && mode == known_mode) | |
3882 | return known_ret; | |
3883 | ||
3884 | /* Try to find identical subexpressions. If found call | |
3885 | nonzero_bits1 on X with the subexpressions as KNOWN_X and the | |
3886 | precomputed value for the subexpression as KNOWN_RET. */ | |
3887 | ||
3888 | if (ARITHMETIC_P (x)) | |
3889 | { | |
3890 | rtx x0 = XEXP (x, 0); | |
3891 | rtx x1 = XEXP (x, 1); | |
3892 | ||
3893 | /* Check the first level. */ | |
3894 | if (x0 == x1) | |
3895 | return nonzero_bits1 (x, mode, x0, mode, | |
3896 | cached_nonzero_bits (x0, mode, known_x, | |
3897 | known_mode, known_ret)); | |
3898 | ||
3899 | /* Check the second level. */ | |
3900 | if (ARITHMETIC_P (x0) | |
3901 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
3902 | return nonzero_bits1 (x, mode, x1, mode, | |
3903 | cached_nonzero_bits (x1, mode, known_x, | |
3904 | known_mode, known_ret)); | |
3905 | ||
3906 | if (ARITHMETIC_P (x1) | |
3907 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
3908 | return nonzero_bits1 (x, mode, x0, mode, | |
3909 | cached_nonzero_bits (x0, mode, known_x, | |
3910 | known_mode, known_ret)); | |
3911 | } | |
3912 | ||
3913 | return nonzero_bits1 (x, mode, known_x, known_mode, known_ret); | |
3914 | } | |
3915 | ||
3916 | /* We let num_sign_bit_copies recur into nonzero_bits as that is useful. | |
3917 | We don't let nonzero_bits recur into num_sign_bit_copies, because that | |
3918 | is less useful. We can't allow both, because that results in exponential | |
3919 | run time recursion. There is a nullstone testcase that triggered | |
3920 | this. This macro avoids accidental uses of num_sign_bit_copies. */ | |
3921 | #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior | |
3922 | ||
3923 | /* Given an expression, X, compute which bits in X can be nonzero. | |
3924 | We don't care about bits outside of those defined in MODE. | |
3925 | ||
3926 | For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
3927 | an arithmetic operation, we can do better. */ | |
3928 | ||
3929 | static unsigned HOST_WIDE_INT | |
b7bf20db | 3930 | nonzero_bits1 (const_rtx x, enum machine_mode mode, const_rtx known_x, |
d263732c | 3931 | enum machine_mode known_mode, |
3932 | unsigned HOST_WIDE_INT known_ret) | |
3933 | { | |
3934 | unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); | |
3935 | unsigned HOST_WIDE_INT inner_nz; | |
3936 | enum rtx_code code; | |
f92430e0 | 3937 | enum machine_mode inner_mode; |
ded805e6 | 3938 | unsigned int mode_width = GET_MODE_PRECISION (mode); |
d263732c | 3939 | |
6d5136ab | 3940 | /* For floating-point and vector values, assume all bits are needed. */ |
3941 | if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode) | |
3942 | || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode)) | |
d263732c | 3943 | return nonzero; |
3944 | ||
3945 | /* If X is wider than MODE, use its mode instead. */ | |
ded805e6 | 3946 | if (GET_MODE_PRECISION (GET_MODE (x)) > mode_width) |
d263732c | 3947 | { |
3948 | mode = GET_MODE (x); | |
3949 | nonzero = GET_MODE_MASK (mode); | |
ded805e6 | 3950 | mode_width = GET_MODE_PRECISION (mode); |
d263732c | 3951 | } |
3952 | ||
3953 | if (mode_width > HOST_BITS_PER_WIDE_INT) | |
3954 | /* Our only callers in this case look for single bit values. So | |
3955 | just return the mode mask. Those tests will then be false. */ | |
3956 | return nonzero; | |
3957 | ||
3958 | #ifndef WORD_REGISTER_OPERATIONS | |
3959 | /* If MODE is wider than X, but both are a single word for both the host | |
3960 | and target machines, we can compute this from which bits of the | |
3961 | object might be nonzero in its own mode, taking into account the fact | |
3962 | that on many CISC machines, accessing an object in a wider mode | |
3963 | causes the high-order bits to become undefined. So they are | |
3964 | not known to be zero. */ | |
3965 | ||
3966 | if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode | |
ded805e6 | 3967 | && GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD |
3968 | && GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
3969 | && GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x))) | |
d263732c | 3970 | { |
3971 | nonzero &= cached_nonzero_bits (x, GET_MODE (x), | |
3972 | known_x, known_mode, known_ret); | |
3973 | nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)); | |
3974 | return nonzero; | |
3975 | } | |
3976 | #endif | |
3977 | ||
3978 | code = GET_CODE (x); | |
3979 | switch (code) | |
3980 | { | |
3981 | case REG: | |
3982 | #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) | |
3983 | /* If pointers extend unsigned and this is a pointer in Pmode, say that | |
3984 | all the bits above ptr_mode are known to be zero. */ | |
04ec15fa | 3985 | /* As we do not know which address space the pointer is referring to, |
98155838 | 3986 | we can do this only if the target does not support different pointer |
3987 | or address modes depending on the address space. */ | |
3988 | if (target_default_pointer_address_modes_p () | |
3989 | && POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode | |
d263732c | 3990 | && REG_POINTER (x)) |
3991 | nonzero &= GET_MODE_MASK (ptr_mode); | |
3992 | #endif | |
3993 | ||
3994 | /* Include declared information about alignment of pointers. */ | |
3995 | /* ??? We don't properly preserve REG_POINTER changes across | |
3996 | pointer-to-integer casts, so we can't trust it except for | |
3997 | things that we know must be pointers. See execute/960116-1.c. */ | |
3998 | if ((x == stack_pointer_rtx | |
3999 | || x == frame_pointer_rtx | |
4000 | || x == arg_pointer_rtx) | |
4001 | && REGNO_POINTER_ALIGN (REGNO (x))) | |
4002 | { | |
4003 | unsigned HOST_WIDE_INT alignment | |
4004 | = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT; | |
4005 | ||
4006 | #ifdef PUSH_ROUNDING | |
4007 | /* If PUSH_ROUNDING is defined, it is possible for the | |
4008 | stack to be momentarily aligned only to that amount, | |
4009 | so we pick the least alignment. */ | |
4010 | if (x == stack_pointer_rtx && PUSH_ARGS) | |
4011 | alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1), | |
4012 | alignment); | |
4013 | #endif | |
4014 | ||
4015 | nonzero &= ~(alignment - 1); | |
4016 | } | |
4017 | ||
4018 | { | |
4019 | unsigned HOST_WIDE_INT nonzero_for_hook = nonzero; | |
47cfb7f4 | 4020 | rtx new_rtx = rtl_hooks.reg_nonzero_bits (x, mode, known_x, |
d263732c | 4021 | known_mode, known_ret, |
4022 | &nonzero_for_hook); | |
4023 | ||
47cfb7f4 | 4024 | if (new_rtx) |
4025 | nonzero_for_hook &= cached_nonzero_bits (new_rtx, mode, known_x, | |
d263732c | 4026 | known_mode, known_ret); |
4027 | ||
4028 | return nonzero_for_hook; | |
4029 | } | |
4030 | ||
4031 | case CONST_INT: | |
4032 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
4033 | /* If X is negative in MODE, sign-extend the value. */ | |
9d8859f1 | 4034 | if (INTVAL (x) > 0 |
4035 | && mode_width < BITS_PER_WORD | |
4036 | && (UINTVAL (x) & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) | |
4037 | != 0) | |
4038 | return UINTVAL (x) | ((unsigned HOST_WIDE_INT) (-1) << mode_width); | |
d263732c | 4039 | #endif |
4040 | ||
9d8859f1 | 4041 | return UINTVAL (x); |
d263732c | 4042 | |
4043 | case MEM: | |
4044 | #ifdef LOAD_EXTEND_OP | |
4045 | /* In many, if not most, RISC machines, reading a byte from memory | |
4046 | zeros the rest of the register. Noticing that fact saves a lot | |
4047 | of extra zero-extends. */ | |
4048 | if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) | |
4049 | nonzero &= GET_MODE_MASK (GET_MODE (x)); | |
4050 | #endif | |
4051 | break; | |
4052 | ||
4053 | case EQ: case NE: | |
4054 | case UNEQ: case LTGT: | |
4055 | case GT: case GTU: case UNGT: | |
4056 | case LT: case LTU: case UNLT: | |
4057 | case GE: case GEU: case UNGE: | |
4058 | case LE: case LEU: case UNLE: | |
4059 | case UNORDERED: case ORDERED: | |
d263732c | 4060 | /* If this produces an integer result, we know which bits are set. |
4061 | Code here used to clear bits outside the mode of X, but that is | |
4062 | now done above. */ | |
48e1416a | 4063 | /* Mind that MODE is the mode the caller wants to look at this |
4064 | operation in, and not the actual operation mode. We can wind | |
8850c3db | 4065 | up with (subreg:DI (gt:V4HI x y)), and we don't have anything |
4066 | that describes the results of a vector compare. */ | |
4067 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT | |
d263732c | 4068 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
4069 | nonzero = STORE_FLAG_VALUE; | |
4070 | break; | |
4071 | ||
4072 | case NEG: | |
4073 | #if 0 | |
4074 | /* Disabled to avoid exponential mutual recursion between nonzero_bits | |
4075 | and num_sign_bit_copies. */ | |
4076 | if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) | |
ded805e6 | 4077 | == GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4078 | nonzero = 1; |
4079 | #endif | |
4080 | ||
b0676cad | 4081 | if (GET_MODE_PRECISION (GET_MODE (x)) < mode_width) |
d263732c | 4082 | nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x))); |
4083 | break; | |
4084 | ||
4085 | case ABS: | |
4086 | #if 0 | |
4087 | /* Disabled to avoid exponential mutual recursion between nonzero_bits | |
4088 | and num_sign_bit_copies. */ | |
4089 | if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) | |
ded805e6 | 4090 | == GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4091 | nonzero = 1; |
4092 | #endif | |
4093 | break; | |
4094 | ||
4095 | case TRUNCATE: | |
4096 | nonzero &= (cached_nonzero_bits (XEXP (x, 0), mode, | |
4097 | known_x, known_mode, known_ret) | |
4098 | & GET_MODE_MASK (mode)); | |
4099 | break; | |
4100 | ||
4101 | case ZERO_EXTEND: | |
4102 | nonzero &= cached_nonzero_bits (XEXP (x, 0), mode, | |
4103 | known_x, known_mode, known_ret); | |
4104 | if (GET_MODE (XEXP (x, 0)) != VOIDmode) | |
4105 | nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); | |
4106 | break; | |
4107 | ||
4108 | case SIGN_EXTEND: | |
4109 | /* If the sign bit is known clear, this is the same as ZERO_EXTEND. | |
4110 | Otherwise, show all the bits in the outer mode but not the inner | |
4111 | may be nonzero. */ | |
4112 | inner_nz = cached_nonzero_bits (XEXP (x, 0), mode, | |
4113 | known_x, known_mode, known_ret); | |
4114 | if (GET_MODE (XEXP (x, 0)) != VOIDmode) | |
4115 | { | |
4116 | inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); | |
f92430e0 | 4117 | if (val_signbit_known_set_p (GET_MODE (XEXP (x, 0)), inner_nz)) |
d263732c | 4118 | inner_nz |= (GET_MODE_MASK (mode) |
4119 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); | |
4120 | } | |
4121 | ||
4122 | nonzero &= inner_nz; | |
4123 | break; | |
4124 | ||
4125 | case AND: | |
4126 | nonzero &= cached_nonzero_bits (XEXP (x, 0), mode, | |
4127 | known_x, known_mode, known_ret) | |
4128 | & cached_nonzero_bits (XEXP (x, 1), mode, | |
4129 | known_x, known_mode, known_ret); | |
4130 | break; | |
4131 | ||
4132 | case XOR: case IOR: | |
4133 | case UMIN: case UMAX: case SMIN: case SMAX: | |
4134 | { | |
9d8859f1 | 4135 | unsigned HOST_WIDE_INT nonzero0 |
4136 | = cached_nonzero_bits (XEXP (x, 0), mode, | |
4137 | known_x, known_mode, known_ret); | |
d263732c | 4138 | |
4139 | /* Don't call nonzero_bits for the second time if it cannot change | |
4140 | anything. */ | |
4141 | if ((nonzero & nonzero0) != nonzero) | |
4142 | nonzero &= nonzero0 | |
4143 | | cached_nonzero_bits (XEXP (x, 1), mode, | |
4144 | known_x, known_mode, known_ret); | |
4145 | } | |
4146 | break; | |
4147 | ||
4148 | case PLUS: case MINUS: | |
4149 | case MULT: | |
4150 | case DIV: case UDIV: | |
4151 | case MOD: case UMOD: | |
4152 | /* We can apply the rules of arithmetic to compute the number of | |
4153 | high- and low-order zero bits of these operations. We start by | |
4154 | computing the width (position of the highest-order nonzero bit) | |
4155 | and the number of low-order zero bits for each value. */ | |
4156 | { | |
9d8859f1 | 4157 | unsigned HOST_WIDE_INT nz0 |
4158 | = cached_nonzero_bits (XEXP (x, 0), mode, | |
4159 | known_x, known_mode, known_ret); | |
4160 | unsigned HOST_WIDE_INT nz1 | |
4161 | = cached_nonzero_bits (XEXP (x, 1), mode, | |
4162 | known_x, known_mode, known_ret); | |
ded805e6 | 4163 | int sign_index = GET_MODE_PRECISION (GET_MODE (x)) - 1; |
d263732c | 4164 | int width0 = floor_log2 (nz0) + 1; |
4165 | int width1 = floor_log2 (nz1) + 1; | |
4166 | int low0 = floor_log2 (nz0 & -nz0); | |
4167 | int low1 = floor_log2 (nz1 & -nz1); | |
9d8859f1 | 4168 | unsigned HOST_WIDE_INT op0_maybe_minusp |
4169 | = nz0 & ((unsigned HOST_WIDE_INT) 1 << sign_index); | |
4170 | unsigned HOST_WIDE_INT op1_maybe_minusp | |
4171 | = nz1 & ((unsigned HOST_WIDE_INT) 1 << sign_index); | |
d263732c | 4172 | unsigned int result_width = mode_width; |
4173 | int result_low = 0; | |
4174 | ||
4175 | switch (code) | |
4176 | { | |
4177 | case PLUS: | |
4178 | result_width = MAX (width0, width1) + 1; | |
4179 | result_low = MIN (low0, low1); | |
4180 | break; | |
4181 | case MINUS: | |
4182 | result_low = MIN (low0, low1); | |
4183 | break; | |
4184 | case MULT: | |
4185 | result_width = width0 + width1; | |
4186 | result_low = low0 + low1; | |
4187 | break; | |
4188 | case DIV: | |
4189 | if (width1 == 0) | |
4190 | break; | |
9d8859f1 | 4191 | if (!op0_maybe_minusp && !op1_maybe_minusp) |
d263732c | 4192 | result_width = width0; |
4193 | break; | |
4194 | case UDIV: | |
4195 | if (width1 == 0) | |
4196 | break; | |
4197 | result_width = width0; | |
4198 | break; | |
4199 | case MOD: | |
4200 | if (width1 == 0) | |
4201 | break; | |
9d8859f1 | 4202 | if (!op0_maybe_minusp && !op1_maybe_minusp) |
d263732c | 4203 | result_width = MIN (width0, width1); |
4204 | result_low = MIN (low0, low1); | |
4205 | break; | |
4206 | case UMOD: | |
4207 | if (width1 == 0) | |
4208 | break; | |
4209 | result_width = MIN (width0, width1); | |
4210 | result_low = MIN (low0, low1); | |
4211 | break; | |
4212 | default: | |
04e579b6 | 4213 | gcc_unreachable (); |
d263732c | 4214 | } |
4215 | ||
4216 | if (result_width < mode_width) | |
9d8859f1 | 4217 | nonzero &= ((unsigned HOST_WIDE_INT) 1 << result_width) - 1; |
d263732c | 4218 | |
4219 | if (result_low > 0) | |
9d8859f1 | 4220 | nonzero &= ~(((unsigned HOST_WIDE_INT) 1 << result_low) - 1); |
d263732c | 4221 | } |
4222 | break; | |
4223 | ||
4224 | case ZERO_EXTRACT: | |
971ba038 | 4225 | if (CONST_INT_P (XEXP (x, 1)) |
d263732c | 4226 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) |
9d8859f1 | 4227 | nonzero &= ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; |
d263732c | 4228 | break; |
4229 | ||
4230 | case SUBREG: | |
4231 | /* If this is a SUBREG formed for a promoted variable that has | |
4232 | been zero-extended, we know that at least the high-order bits | |
4233 | are zero, though others might be too. */ | |
4234 | ||
4235 | if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0) | |
4236 | nonzero = GET_MODE_MASK (GET_MODE (x)) | |
4237 | & cached_nonzero_bits (SUBREG_REG (x), GET_MODE (x), | |
4238 | known_x, known_mode, known_ret); | |
4239 | ||
f92430e0 | 4240 | inner_mode = GET_MODE (SUBREG_REG (x)); |
d263732c | 4241 | /* If the inner mode is a single word for both the host and target |
4242 | machines, we can compute this from which bits of the inner | |
4243 | object might be nonzero. */ | |
ded805e6 | 4244 | if (GET_MODE_PRECISION (inner_mode) <= BITS_PER_WORD |
4245 | && (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT)) | |
d263732c | 4246 | { |
4247 | nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, | |
4248 | known_x, known_mode, known_ret); | |
4249 | ||
4250 | #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) | |
4251 | /* If this is a typical RISC machine, we only have to worry | |
4252 | about the way loads are extended. */ | |
f92430e0 | 4253 | if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND |
4254 | ? val_signbit_known_set_p (inner_mode, nonzero) | |
4255 | : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) | |
e16ceb8e | 4256 | || !MEM_P (SUBREG_REG (x))) |
d263732c | 4257 | #endif |
4258 | { | |
4259 | /* On many CISC machines, accessing an object in a wider mode | |
4260 | causes the high-order bits to become undefined. So they are | |
4261 | not known to be zero. */ | |
ded805e6 | 4262 | if (GET_MODE_PRECISION (GET_MODE (x)) |
4263 | > GET_MODE_PRECISION (inner_mode)) | |
d263732c | 4264 | nonzero |= (GET_MODE_MASK (GET_MODE (x)) |
f92430e0 | 4265 | & ~GET_MODE_MASK (inner_mode)); |
d263732c | 4266 | } |
4267 | } | |
4268 | break; | |
4269 | ||
4270 | case ASHIFTRT: | |
4271 | case LSHIFTRT: | |
4272 | case ASHIFT: | |
4273 | case ROTATE: | |
4274 | /* The nonzero bits are in two classes: any bits within MODE | |
4275 | that aren't in GET_MODE (x) are always significant. The rest of the | |
4276 | nonzero bits are those that are significant in the operand of | |
4277 | the shift when shifted the appropriate number of bits. This | |
4278 | shows that high-order bits are cleared by the right shift and | |
4279 | low-order bits by left shifts. */ | |
971ba038 | 4280 | if (CONST_INT_P (XEXP (x, 1)) |
d263732c | 4281 | && INTVAL (XEXP (x, 1)) >= 0 |
6026d749 | 4282 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
ded805e6 | 4283 | && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4284 | { |
4285 | enum machine_mode inner_mode = GET_MODE (x); | |
ded805e6 | 4286 | unsigned int width = GET_MODE_PRECISION (inner_mode); |
d263732c | 4287 | int count = INTVAL (XEXP (x, 1)); |
4288 | unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); | |
9d8859f1 | 4289 | unsigned HOST_WIDE_INT op_nonzero |
4290 | = cached_nonzero_bits (XEXP (x, 0), mode, | |
4291 | known_x, known_mode, known_ret); | |
d263732c | 4292 | unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; |
4293 | unsigned HOST_WIDE_INT outer = 0; | |
4294 | ||
4295 | if (mode_width > width) | |
4296 | outer = (op_nonzero & nonzero & ~mode_mask); | |
4297 | ||
4298 | if (code == LSHIFTRT) | |
4299 | inner >>= count; | |
4300 | else if (code == ASHIFTRT) | |
4301 | { | |
4302 | inner >>= count; | |
4303 | ||
4304 | /* If the sign bit may have been nonzero before the shift, we | |
4305 | need to mark all the places it could have been copied to | |
4306 | by the shift as possibly nonzero. */ | |
9d8859f1 | 4307 | if (inner & ((unsigned HOST_WIDE_INT) 1 << (width - 1 - count))) |
4308 | inner |= (((unsigned HOST_WIDE_INT) 1 << count) - 1) | |
4309 | << (width - count); | |
d263732c | 4310 | } |
4311 | else if (code == ASHIFT) | |
4312 | inner <<= count; | |
4313 | else | |
4314 | inner = ((inner << (count % width) | |
4315 | | (inner >> (width - (count % width)))) & mode_mask); | |
4316 | ||
4317 | nonzero &= (outer | inner); | |
4318 | } | |
4319 | break; | |
4320 | ||
4321 | case FFS: | |
4322 | case POPCOUNT: | |
4323 | /* This is at most the number of bits in the mode. */ | |
9d8859f1 | 4324 | nonzero = ((unsigned HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1; |
d263732c | 4325 | break; |
4326 | ||
4327 | case CLZ: | |
4328 | /* If CLZ has a known value at zero, then the nonzero bits are | |
4329 | that value, plus the number of bits in the mode minus one. */ | |
4330 | if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)) | |
9d8859f1 | 4331 | nonzero |
4332 | |= ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1; | |
d263732c | 4333 | else |
4334 | nonzero = -1; | |
4335 | break; | |
4336 | ||
4337 | case CTZ: | |
4338 | /* If CTZ has a known value at zero, then the nonzero bits are | |
4339 | that value, plus the number of bits in the mode minus one. */ | |
4340 | if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)) | |
9d8859f1 | 4341 | nonzero |
4342 | |= ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1; | |
d263732c | 4343 | else |
4344 | nonzero = -1; | |
4345 | break; | |
4346 | ||
3b23b4cc | 4347 | case CLRSB: |
4348 | /* This is at most the number of bits in the mode minus 1. */ | |
4349 | nonzero = ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1; | |
4350 | break; | |
4351 | ||
d263732c | 4352 | case PARITY: |
4353 | nonzero = 1; | |
4354 | break; | |
4355 | ||
4356 | case IF_THEN_ELSE: | |
4357 | { | |
9d8859f1 | 4358 | unsigned HOST_WIDE_INT nonzero_true |
4359 | = cached_nonzero_bits (XEXP (x, 1), mode, | |
4360 | known_x, known_mode, known_ret); | |
d263732c | 4361 | |
4362 | /* Don't call nonzero_bits for the second time if it cannot change | |
4363 | anything. */ | |
4364 | if ((nonzero & nonzero_true) != nonzero) | |
4365 | nonzero &= nonzero_true | |
4366 | | cached_nonzero_bits (XEXP (x, 2), mode, | |
4367 | known_x, known_mode, known_ret); | |
4368 | } | |
4369 | break; | |
4370 | ||
4371 | default: | |
4372 | break; | |
4373 | } | |
4374 | ||
4375 | return nonzero; | |
4376 | } | |
4377 | ||
4378 | /* See the macro definition above. */ | |
4379 | #undef cached_num_sign_bit_copies | |
4380 | ||
4381 | \f | |
4382 | /* The function cached_num_sign_bit_copies is a wrapper around | |
4383 | num_sign_bit_copies1. It avoids exponential behavior in | |
4384 | num_sign_bit_copies1 when X has identical subexpressions on the | |
4385 | first or the second level. */ | |
4386 | ||
4387 | static unsigned int | |
b7bf20db | 4388 | cached_num_sign_bit_copies (const_rtx x, enum machine_mode mode, const_rtx known_x, |
d263732c | 4389 | enum machine_mode known_mode, |
4390 | unsigned int known_ret) | |
4391 | { | |
4392 | if (x == known_x && mode == known_mode) | |
4393 | return known_ret; | |
4394 | ||
4395 | /* Try to find identical subexpressions. If found call | |
4396 | num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and | |
4397 | the precomputed value for the subexpression as KNOWN_RET. */ | |
4398 | ||
4399 | if (ARITHMETIC_P (x)) | |
4400 | { | |
4401 | rtx x0 = XEXP (x, 0); | |
4402 | rtx x1 = XEXP (x, 1); | |
4403 | ||
4404 | /* Check the first level. */ | |
4405 | if (x0 == x1) | |
4406 | return | |
4407 | num_sign_bit_copies1 (x, mode, x0, mode, | |
4408 | cached_num_sign_bit_copies (x0, mode, known_x, | |
4409 | known_mode, | |
4410 | known_ret)); | |
4411 | ||
4412 | /* Check the second level. */ | |
4413 | if (ARITHMETIC_P (x0) | |
4414 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
4415 | return | |
4416 | num_sign_bit_copies1 (x, mode, x1, mode, | |
4417 | cached_num_sign_bit_copies (x1, mode, known_x, | |
4418 | known_mode, | |
4419 | known_ret)); | |
4420 | ||
4421 | if (ARITHMETIC_P (x1) | |
4422 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
4423 | return | |
4424 | num_sign_bit_copies1 (x, mode, x0, mode, | |
4425 | cached_num_sign_bit_copies (x0, mode, known_x, | |
4426 | known_mode, | |
4427 | known_ret)); | |
4428 | } | |
4429 | ||
4430 | return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret); | |
4431 | } | |
4432 | ||
4433 | /* Return the number of bits at the high-order end of X that are known to | |
4434 | be equal to the sign bit. X will be used in mode MODE; if MODE is | |
4435 | VOIDmode, X will be used in its own mode. The returned value will always | |
4436 | be between 1 and the number of bits in MODE. */ | |
4437 | ||
4438 | static unsigned int | |
b7bf20db | 4439 | num_sign_bit_copies1 (const_rtx x, enum machine_mode mode, const_rtx known_x, |
d263732c | 4440 | enum machine_mode known_mode, |
4441 | unsigned int known_ret) | |
4442 | { | |
4443 | enum rtx_code code = GET_CODE (x); | |
ded805e6 | 4444 | unsigned int bitwidth = GET_MODE_PRECISION (mode); |
d263732c | 4445 | int num0, num1, result; |
4446 | unsigned HOST_WIDE_INT nonzero; | |
4447 | ||
4448 | /* If we weren't given a mode, use the mode of X. If the mode is still | |
4449 | VOIDmode, we don't know anything. Likewise if one of the modes is | |
4450 | floating-point. */ | |
4451 | ||
4452 | if (mode == VOIDmode) | |
4453 | mode = GET_MODE (x); | |
4454 | ||
6d5136ab | 4455 | if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)) |
4456 | || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode)) | |
d263732c | 4457 | return 1; |
4458 | ||
4459 | /* For a smaller object, just ignore the high bits. */ | |
ded805e6 | 4460 | if (bitwidth < GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4461 | { |
4462 | num0 = cached_num_sign_bit_copies (x, GET_MODE (x), | |
4463 | known_x, known_mode, known_ret); | |
4464 | return MAX (1, | |
ded805e6 | 4465 | num0 - (int) (GET_MODE_PRECISION (GET_MODE (x)) - bitwidth)); |
d263732c | 4466 | } |
4467 | ||
ded805e6 | 4468 | if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4469 | { |
4470 | #ifndef WORD_REGISTER_OPERATIONS | |
ded805e6 | 4471 | /* If this machine does not do all register operations on the entire |
4472 | register and MODE is wider than the mode of X, we can say nothing | |
4473 | at all about the high-order bits. */ | |
d263732c | 4474 | return 1; |
4475 | #else | |
4476 | /* Likewise on machines that do, if the mode of the object is smaller | |
4477 | than a word and loads of that size don't sign extend, we can say | |
4478 | nothing about the high order bits. */ | |
ded805e6 | 4479 | if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD |
d263732c | 4480 | #ifdef LOAD_EXTEND_OP |
4481 | && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND | |
4482 | #endif | |
4483 | ) | |
4484 | return 1; | |
4485 | #endif | |
4486 | } | |
4487 | ||
4488 | switch (code) | |
4489 | { | |
4490 | case REG: | |
4491 | ||
4492 | #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) | |
4493 | /* If pointers extend signed and this is a pointer in Pmode, say that | |
4494 | all the bits above ptr_mode are known to be sign bit copies. */ | |
04ec15fa | 4495 | /* As we do not know which address space the pointer is referring to, |
98155838 | 4496 | we can do this only if the target does not support different pointer |
4497 | or address modes depending on the address space. */ | |
4498 | if (target_default_pointer_address_modes_p () | |
4499 | && ! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode | |
4500 | && mode == Pmode && REG_POINTER (x)) | |
ded805e6 | 4501 | return GET_MODE_PRECISION (Pmode) - GET_MODE_PRECISION (ptr_mode) + 1; |
d263732c | 4502 | #endif |
4503 | ||
4504 | { | |
4505 | unsigned int copies_for_hook = 1, copies = 1; | |
47cfb7f4 | 4506 | rtx new_rtx = rtl_hooks.reg_num_sign_bit_copies (x, mode, known_x, |
d263732c | 4507 | known_mode, known_ret, |
4508 | &copies_for_hook); | |
4509 | ||
47cfb7f4 | 4510 | if (new_rtx) |
4511 | copies = cached_num_sign_bit_copies (new_rtx, mode, known_x, | |
d263732c | 4512 | known_mode, known_ret); |
4513 | ||
4514 | if (copies > 1 || copies_for_hook > 1) | |
4515 | return MAX (copies, copies_for_hook); | |
4516 | ||
4517 | /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */ | |
4518 | } | |
4519 | break; | |
4520 | ||
4521 | case MEM: | |
4522 | #ifdef LOAD_EXTEND_OP | |
4523 | /* Some RISC machines sign-extend all loads of smaller than a word. */ | |
4524 | if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) | |
4525 | return MAX (1, ((int) bitwidth | |
ded805e6 | 4526 | - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1)); |
d263732c | 4527 | #endif |
4528 | break; | |
4529 | ||
4530 | case CONST_INT: | |
4531 | /* If the constant is negative, take its 1's complement and remask. | |
4532 | Then see how many zero bits we have. */ | |
9d8859f1 | 4533 | nonzero = UINTVAL (x) & GET_MODE_MASK (mode); |
d263732c | 4534 | if (bitwidth <= HOST_BITS_PER_WIDE_INT |
9d8859f1 | 4535 | && (nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) |
d263732c | 4536 | nonzero = (~nonzero) & GET_MODE_MASK (mode); |
4537 | ||
4538 | return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); | |
4539 | ||
4540 | case SUBREG: | |
4541 | /* If this is a SUBREG for a promoted object that is sign-extended | |
4542 | and we are looking at it in a wider mode, we know that at least the | |
4543 | high-order bits are known to be sign bit copies. */ | |
4544 | ||
4545 | if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) | |
4546 | { | |
4547 | num0 = cached_num_sign_bit_copies (SUBREG_REG (x), mode, | |
4548 | known_x, known_mode, known_ret); | |
4549 | return MAX ((int) bitwidth | |
ded805e6 | 4550 | - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1, |
d263732c | 4551 | num0); |
4552 | } | |
4553 | ||
4554 | /* For a smaller object, just ignore the high bits. */ | |
ded805e6 | 4555 | if (bitwidth <= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x)))) |
d263732c | 4556 | { |
4557 | num0 = cached_num_sign_bit_copies (SUBREG_REG (x), VOIDmode, | |
4558 | known_x, known_mode, known_ret); | |
4559 | return MAX (1, (num0 | |
ded805e6 | 4560 | - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x))) |
d263732c | 4561 | - bitwidth))); |
4562 | } | |
4563 | ||
4564 | #ifdef WORD_REGISTER_OPERATIONS | |
4565 | #ifdef LOAD_EXTEND_OP | |
4566 | /* For paradoxical SUBREGs on machines where all register operations | |
4567 | affect the entire register, just look inside. Note that we are | |
4568 | passing MODE to the recursive call, so the number of sign bit copies | |
4569 | will remain relative to that mode, not the inner mode. */ | |
4570 | ||
4571 | /* This works only if loads sign extend. Otherwise, if we get a | |
4572 | reload for the inner part, it may be loaded from the stack, and | |
4573 | then we lose all sign bit copies that existed before the store | |
4574 | to the stack. */ | |
4575 | ||
b537bfdb | 4576 | if (paradoxical_subreg_p (x) |
d263732c | 4577 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND |
e16ceb8e | 4578 | && MEM_P (SUBREG_REG (x))) |
d263732c | 4579 | return cached_num_sign_bit_copies (SUBREG_REG (x), mode, |
4580 | known_x, known_mode, known_ret); | |
4581 | #endif | |
4582 | #endif | |
4583 | break; | |
4584 | ||
4585 | case SIGN_EXTRACT: | |
971ba038 | 4586 | if (CONST_INT_P (XEXP (x, 1))) |
d263732c | 4587 | return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1))); |
4588 | break; | |
4589 | ||
4590 | case SIGN_EXTEND: | |
ded805e6 | 4591 | return (bitwidth - GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) |
d263732c | 4592 | + cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode, |
4593 | known_x, known_mode, known_ret)); | |
4594 | ||
4595 | case TRUNCATE: | |
4596 | /* For a smaller object, just ignore the high bits. */ | |
4597 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode, | |
4598 | known_x, known_mode, known_ret); | |
ded805e6 | 4599 | return MAX (1, (num0 - (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) |
d263732c | 4600 | - bitwidth))); |
4601 | ||
4602 | case NOT: | |
4603 | return cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4604 | known_x, known_mode, known_ret); | |
4605 | ||
4606 | case ROTATE: case ROTATERT: | |
4607 | /* If we are rotating left by a number of bits less than the number | |
4608 | of sign bit copies, we can just subtract that amount from the | |
4609 | number. */ | |
971ba038 | 4610 | if (CONST_INT_P (XEXP (x, 1)) |
d263732c | 4611 | && INTVAL (XEXP (x, 1)) >= 0 |
4612 | && INTVAL (XEXP (x, 1)) < (int) bitwidth) | |
4613 | { | |
4614 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4615 | known_x, known_mode, known_ret); | |
4616 | return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) | |
4617 | : (int) bitwidth - INTVAL (XEXP (x, 1)))); | |
4618 | } | |
4619 | break; | |
4620 | ||
4621 | case NEG: | |
4622 | /* In general, this subtracts one sign bit copy. But if the value | |
4623 | is known to be positive, the number of sign bit copies is the | |
4624 | same as that of the input. Finally, if the input has just one bit | |
4625 | that might be nonzero, all the bits are copies of the sign bit. */ | |
4626 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4627 | known_x, known_mode, known_ret); | |
4628 | if (bitwidth > HOST_BITS_PER_WIDE_INT) | |
4629 | return num0 > 1 ? num0 - 1 : 1; | |
4630 | ||
4631 | nonzero = nonzero_bits (XEXP (x, 0), mode); | |
4632 | if (nonzero == 1) | |
4633 | return bitwidth; | |
4634 | ||
4635 | if (num0 > 1 | |
9d8859f1 | 4636 | && (((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) |
d263732c | 4637 | num0--; |
4638 | ||
4639 | return num0; | |
4640 | ||
4641 | case IOR: case AND: case XOR: | |
4642 | case SMIN: case SMAX: case UMIN: case UMAX: | |
4643 | /* Logical operations will preserve the number of sign-bit copies. | |
4644 | MIN and MAX operations always return one of the operands. */ | |
4645 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4646 | known_x, known_mode, known_ret); | |
4647 | num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode, | |
4648 | known_x, known_mode, known_ret); | |
c07054e9 | 4649 | |
4650 | /* If num1 is clearing some of the top bits then regardless of | |
4651 | the other term, we are guaranteed to have at least that many | |
4652 | high-order zero bits. */ | |
4653 | if (code == AND | |
4654 | && num1 > 1 | |
4655 | && bitwidth <= HOST_BITS_PER_WIDE_INT | |
971ba038 | 4656 | && CONST_INT_P (XEXP (x, 1)) |
9d8859f1 | 4657 | && (UINTVAL (XEXP (x, 1)) |
4658 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) == 0) | |
c07054e9 | 4659 | return num1; |
4660 | ||
4661 | /* Similarly for IOR when setting high-order bits. */ | |
4662 | if (code == IOR | |
4663 | && num1 > 1 | |
4664 | && bitwidth <= HOST_BITS_PER_WIDE_INT | |
971ba038 | 4665 | && CONST_INT_P (XEXP (x, 1)) |
9d8859f1 | 4666 | && (UINTVAL (XEXP (x, 1)) |
4667 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) | |
c07054e9 | 4668 | return num1; |
4669 | ||
d263732c | 4670 | return MIN (num0, num1); |
4671 | ||
4672 | case PLUS: case MINUS: | |
4673 | /* For addition and subtraction, we can have a 1-bit carry. However, | |
4674 | if we are subtracting 1 from a positive number, there will not | |
4675 | be such a carry. Furthermore, if the positive number is known to | |
4676 | be 0 or 1, we know the result is either -1 or 0. */ | |
4677 | ||
4678 | if (code == PLUS && XEXP (x, 1) == constm1_rtx | |
4679 | && bitwidth <= HOST_BITS_PER_WIDE_INT) | |
4680 | { | |
4681 | nonzero = nonzero_bits (XEXP (x, 0), mode); | |
9d8859f1 | 4682 | if ((((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) |
d263732c | 4683 | return (nonzero == 1 || nonzero == 0 ? bitwidth |
4684 | : bitwidth - floor_log2 (nonzero) - 1); | |
4685 | } | |
4686 | ||
4687 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4688 | known_x, known_mode, known_ret); | |
4689 | num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode, | |
4690 | known_x, known_mode, known_ret); | |
4691 | result = MAX (1, MIN (num0, num1) - 1); | |
4692 | ||
d263732c | 4693 | return result; |
4694 | ||
4695 | case MULT: | |
4696 | /* The number of bits of the product is the sum of the number of | |
4697 | bits of both terms. However, unless one of the terms if known | |
4698 | to be positive, we must allow for an additional bit since negating | |
4699 | a negative number can remove one sign bit copy. */ | |
4700 | ||
4701 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4702 | known_x, known_mode, known_ret); | |
4703 | num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode, | |
4704 | known_x, known_mode, known_ret); | |
4705 | ||
4706 | result = bitwidth - (bitwidth - num0) - (bitwidth - num1); | |
4707 | if (result > 0 | |
4708 | && (bitwidth > HOST_BITS_PER_WIDE_INT | |
4709 | || (((nonzero_bits (XEXP (x, 0), mode) | |
9d8859f1 | 4710 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) |
d263732c | 4711 | && ((nonzero_bits (XEXP (x, 1), mode) |
9d8859f1 | 4712 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) |
4713 | != 0)))) | |
d263732c | 4714 | result--; |
4715 | ||
4716 | return MAX (1, result); | |
4717 | ||
4718 | case UDIV: | |
4719 | /* The result must be <= the first operand. If the first operand | |
4720 | has the high bit set, we know nothing about the number of sign | |
4721 | bit copies. */ | |
4722 | if (bitwidth > HOST_BITS_PER_WIDE_INT) | |
4723 | return 1; | |
4724 | else if ((nonzero_bits (XEXP (x, 0), mode) | |
9d8859f1 | 4725 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) |
d263732c | 4726 | return 1; |
4727 | else | |
4728 | return cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4729 | known_x, known_mode, known_ret); | |
4730 | ||
4731 | case UMOD: | |
3c2a960d | 4732 | /* The result must be <= the second operand. If the second operand |
4733 | has (or just might have) the high bit set, we know nothing about | |
4734 | the number of sign bit copies. */ | |
4735 | if (bitwidth > HOST_BITS_PER_WIDE_INT) | |
4736 | return 1; | |
4737 | else if ((nonzero_bits (XEXP (x, 1), mode) | |
9d8859f1 | 4738 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) |
3c2a960d | 4739 | return 1; |
4740 | else | |
4741 | return cached_num_sign_bit_copies (XEXP (x, 1), mode, | |
d263732c | 4742 | known_x, known_mode, known_ret); |
4743 | ||
4744 | case DIV: | |
4745 | /* Similar to unsigned division, except that we have to worry about | |
4746 | the case where the divisor is negative, in which case we have | |
4747 | to add 1. */ | |
4748 | result = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4749 | known_x, known_mode, known_ret); | |
4750 | if (result > 1 | |
4751 | && (bitwidth > HOST_BITS_PER_WIDE_INT | |
4752 | || (nonzero_bits (XEXP (x, 1), mode) | |
9d8859f1 | 4753 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) |
d263732c | 4754 | result--; |
4755 | ||
4756 | return result; | |
4757 | ||
4758 | case MOD: | |
4759 | result = cached_num_sign_bit_copies (XEXP (x, 1), mode, | |
4760 | known_x, known_mode, known_ret); | |
4761 | if (result > 1 | |
4762 | && (bitwidth > HOST_BITS_PER_WIDE_INT | |
4763 | || (nonzero_bits (XEXP (x, 1), mode) | |
9d8859f1 | 4764 | & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) |
d263732c | 4765 | result--; |
4766 | ||
4767 | return result; | |
4768 | ||
4769 | case ASHIFTRT: | |
4770 | /* Shifts by a constant add to the number of bits equal to the | |
4771 | sign bit. */ | |
4772 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4773 | known_x, known_mode, known_ret); | |
971ba038 | 4774 | if (CONST_INT_P (XEXP (x, 1)) |
6026d749 | 4775 | && INTVAL (XEXP (x, 1)) > 0 |
ded805e6 | 4776 | && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4777 | num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1))); |
4778 | ||
4779 | return num0; | |
4780 | ||
4781 | case ASHIFT: | |
4782 | /* Left shifts destroy copies. */ | |
971ba038 | 4783 | if (!CONST_INT_P (XEXP (x, 1)) |
d263732c | 4784 | || INTVAL (XEXP (x, 1)) < 0 |
6026d749 | 4785 | || INTVAL (XEXP (x, 1)) >= (int) bitwidth |
ded805e6 | 4786 | || INTVAL (XEXP (x, 1)) >= GET_MODE_PRECISION (GET_MODE (x))) |
d263732c | 4787 | return 1; |
4788 | ||
4789 | num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, | |
4790 | known_x, known_mode, known_ret); | |
4791 | return MAX (1, num0 - INTVAL (XEXP (x, 1))); | |
4792 | ||
4793 | case IF_THEN_ELSE: | |
4794 | num0 = cached_num_sign_bit_copies (XEXP (x, 1), mode, | |
4795 | known_x, known_mode, known_ret); | |
4796 | num1 = cached_num_sign_bit_copies (XEXP (x, 2), mode, | |
4797 | known_x, known_mode, known_ret); | |
4798 | return MIN (num0, num1); | |
4799 | ||
4800 | case EQ: case NE: case GE: case GT: case LE: case LT: | |
4801 | case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT: | |
4802 | case GEU: case GTU: case LEU: case LTU: | |
4803 | case UNORDERED: case ORDERED: | |
4804 | /* If the constant is negative, take its 1's complement and remask. | |
4805 | Then see how many zero bits we have. */ | |
4806 | nonzero = STORE_FLAG_VALUE; | |
4807 | if (bitwidth <= HOST_BITS_PER_WIDE_INT | |
9d8859f1 | 4808 | && (nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) |
d263732c | 4809 | nonzero = (~nonzero) & GET_MODE_MASK (mode); |
4810 | ||
4811 | return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); | |
4812 | ||
4813 | default: | |
4814 | break; | |
4815 | } | |
4816 | ||
4817 | /* If we haven't been able to figure it out by one of the above rules, | |
4818 | see if some of the high-order bits are known to be zero. If so, | |
4819 | count those bits and return one less than that amount. If we can't | |
4820 | safely compute the mask for this mode, always return BITWIDTH. */ | |
4821 | ||
ded805e6 | 4822 | bitwidth = GET_MODE_PRECISION (mode); |
d263732c | 4823 | if (bitwidth > HOST_BITS_PER_WIDE_INT) |
4824 | return 1; | |
4825 | ||
4826 | nonzero = nonzero_bits (x, mode); | |
9d8859f1 | 4827 | return nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) |
d263732c | 4828 | ? 1 : bitwidth - floor_log2 (nonzero) - 1; |
4829 | } | |
0a8a047c | 4830 | |
4831 | /* Calculate the rtx_cost of a single instruction. A return value of | |
4832 | zero indicates an instruction pattern without a known cost. */ | |
4833 | ||
4834 | int | |
f529eb25 | 4835 | insn_rtx_cost (rtx pat, bool speed) |
0a8a047c | 4836 | { |
4837 | int i, cost; | |
4838 | rtx set; | |
4839 | ||
4840 | /* Extract the single set rtx from the instruction pattern. | |
4841 | We can't use single_set since we only have the pattern. */ | |
4842 | if (GET_CODE (pat) == SET) | |
4843 | set = pat; | |
4844 | else if (GET_CODE (pat) == PARALLEL) | |
4845 | { | |
4846 | set = NULL_RTX; | |
4847 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
4848 | { | |
4849 | rtx x = XVECEXP (pat, 0, i); | |
4850 | if (GET_CODE (x) == SET) | |
4851 | { | |
4852 | if (set) | |
4853 | return 0; | |
4854 | set = x; | |
4855 | } | |
4856 | } | |
4857 | if (!set) | |
4858 | return 0; | |
4859 | } | |
4860 | else | |
4861 | return 0; | |
4862 | ||
7013e87c | 4863 | cost = set_src_cost (SET_SRC (set), speed); |
0a8a047c | 4864 | return cost > 0 ? cost : COSTS_N_INSNS (1); |
4865 | } | |
ea92ba80 | 4866 | |
4867 | /* Given an insn INSN and condition COND, return the condition in a | |
4868 | canonical form to simplify testing by callers. Specifically: | |
4869 | ||
4870 | (1) The code will always be a comparison operation (EQ, NE, GT, etc.). | |
4871 | (2) Both operands will be machine operands; (cc0) will have been replaced. | |
4872 | (3) If an operand is a constant, it will be the second operand. | |
4873 | (4) (LE x const) will be replaced with (LT x <const+1>) and similarly | |
4874 | for GE, GEU, and LEU. | |
4875 | ||
4876 | If the condition cannot be understood, or is an inequality floating-point | |
4877 | comparison which needs to be reversed, 0 will be returned. | |
4878 | ||
4879 | If REVERSE is nonzero, then reverse the condition prior to canonizing it. | |
4880 | ||
4881 | If EARLIEST is nonzero, it is a pointer to a place where the earliest | |
4882 | insn used in locating the condition was found. If a replacement test | |
4883 | of the condition is desired, it should be placed in front of that | |
4884 | insn and we will be sure that the inputs are still valid. | |
4885 | ||
4886 | If WANT_REG is nonzero, we wish the condition to be relative to that | |
4887 | register, if possible. Therefore, do not canonicalize the condition | |
48e1416a | 4888 | further. If ALLOW_CC_MODE is nonzero, allow the condition returned |
ea92ba80 | 4889 | to be a compare to a CC mode register. |
4890 | ||
4891 | If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST | |
4892 | and at INSN. */ | |
4893 | ||
4894 | rtx | |
4895 | canonicalize_condition (rtx insn, rtx cond, int reverse, rtx *earliest, | |
4896 | rtx want_reg, int allow_cc_mode, int valid_at_insn_p) | |
4897 | { | |
4898 | enum rtx_code code; | |
4899 | rtx prev = insn; | |
dd9b9fc5 | 4900 | const_rtx set; |
ea92ba80 | 4901 | rtx tem; |
4902 | rtx op0, op1; | |
4903 | int reverse_code = 0; | |
4904 | enum machine_mode mode; | |
64685a89 | 4905 | basic_block bb = BLOCK_FOR_INSN (insn); |
ea92ba80 | 4906 | |
4907 | code = GET_CODE (cond); | |
4908 | mode = GET_MODE (cond); | |
4909 | op0 = XEXP (cond, 0); | |
4910 | op1 = XEXP (cond, 1); | |
4911 | ||
4912 | if (reverse) | |
4913 | code = reversed_comparison_code (cond, insn); | |
4914 | if (code == UNKNOWN) | |
4915 | return 0; | |
4916 | ||
4917 | if (earliest) | |
4918 | *earliest = insn; | |
4919 | ||
4920 | /* If we are comparing a register with zero, see if the register is set | |
4921 | in the previous insn to a COMPARE or a comparison operation. Perform | |
4922 | the same tests as a function of STORE_FLAG_VALUE as find_comparison_args | |
4923 | in cse.c */ | |
4924 | ||
4925 | while ((GET_RTX_CLASS (code) == RTX_COMPARE | |
4926 | || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) | |
4927 | && op1 == CONST0_RTX (GET_MODE (op0)) | |
4928 | && op0 != want_reg) | |
4929 | { | |
4930 | /* Set nonzero when we find something of interest. */ | |
4931 | rtx x = 0; | |
4932 | ||
4933 | #ifdef HAVE_cc0 | |
4934 | /* If comparison with cc0, import actual comparison from compare | |
4935 | insn. */ | |
4936 | if (op0 == cc0_rtx) | |
4937 | { | |
4938 | if ((prev = prev_nonnote_insn (prev)) == 0 | |
4939 | || !NONJUMP_INSN_P (prev) | |
4940 | || (set = single_set (prev)) == 0 | |
4941 | || SET_DEST (set) != cc0_rtx) | |
4942 | return 0; | |
4943 | ||
4944 | op0 = SET_SRC (set); | |
4945 | op1 = CONST0_RTX (GET_MODE (op0)); | |
4946 | if (earliest) | |
4947 | *earliest = prev; | |
4948 | } | |
4949 | #endif | |
4950 | ||
4951 | /* If this is a COMPARE, pick up the two things being compared. */ | |
4952 | if (GET_CODE (op0) == COMPARE) | |
4953 | { | |
4954 | op1 = XEXP (op0, 1); | |
4955 | op0 = XEXP (op0, 0); | |
4956 | continue; | |
4957 | } | |
4958 | else if (!REG_P (op0)) | |
4959 | break; | |
4960 | ||
4961 | /* Go back to the previous insn. Stop if it is not an INSN. We also | |
4962 | stop if it isn't a single set or if it has a REG_INC note because | |
4963 | we don't want to bother dealing with it. */ | |
4964 | ||
5b8537a8 | 4965 | prev = prev_nonnote_nondebug_insn (prev); |
9845d120 | 4966 | |
4967 | if (prev == 0 | |
ea92ba80 | 4968 | || !NONJUMP_INSN_P (prev) |
64685a89 | 4969 | || FIND_REG_INC_NOTE (prev, NULL_RTX) |
4970 | /* In cfglayout mode, there do not have to be labels at the | |
4971 | beginning of a block, or jumps at the end, so the previous | |
4972 | conditions would not stop us when we reach bb boundary. */ | |
4973 | || BLOCK_FOR_INSN (prev) != bb) | |
ea92ba80 | 4974 | break; |
4975 | ||
4976 | set = set_of (op0, prev); | |
4977 | ||
4978 | if (set | |
4979 | && (GET_CODE (set) != SET | |
4980 | || !rtx_equal_p (SET_DEST (set), op0))) | |
4981 | break; | |
4982 | ||
4983 | /* If this is setting OP0, get what it sets it to if it looks | |
4984 | relevant. */ | |
4985 | if (set) | |
4986 | { | |
4987 | enum machine_mode inner_mode = GET_MODE (SET_DEST (set)); | |
4988 | #ifdef FLOAT_STORE_FLAG_VALUE | |
4989 | REAL_VALUE_TYPE fsfv; | |
4990 | #endif | |
4991 | ||
4992 | /* ??? We may not combine comparisons done in a CCmode with | |
4993 | comparisons not done in a CCmode. This is to aid targets | |
4994 | like Alpha that have an IEEE compliant EQ instruction, and | |
4995 | a non-IEEE compliant BEQ instruction. The use of CCmode is | |
4996 | actually artificial, simply to prevent the combination, but | |
4997 | should not affect other platforms. | |
4998 | ||
4999 | However, we must allow VOIDmode comparisons to match either | |
5000 | CCmode or non-CCmode comparison, because some ports have | |
5001 | modeless comparisons inside branch patterns. | |
5002 | ||
5003 | ??? This mode check should perhaps look more like the mode check | |
5004 | in simplify_comparison in combine. */ | |
5005 | ||
5006 | if ((GET_CODE (SET_SRC (set)) == COMPARE | |
5007 | || (((code == NE | |
5008 | || (code == LT | |
f92430e0 | 5009 | && val_signbit_known_set_p (inner_mode, |
5010 | STORE_FLAG_VALUE)) | |
ea92ba80 | 5011 | #ifdef FLOAT_STORE_FLAG_VALUE |
5012 | || (code == LT | |
cee7491d | 5013 | && SCALAR_FLOAT_MODE_P (inner_mode) |
ea92ba80 | 5014 | && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode), |
5015 | REAL_VALUE_NEGATIVE (fsfv))) | |
5016 | #endif | |
5017 | )) | |
5018 | && COMPARISON_P (SET_SRC (set)))) | |
5019 | && (((GET_MODE_CLASS (mode) == MODE_CC) | |
5020 | == (GET_MODE_CLASS (inner_mode) == MODE_CC)) | |
5021 | || mode == VOIDmode || inner_mode == VOIDmode)) | |
5022 | x = SET_SRC (set); | |
5023 | else if (((code == EQ | |
5024 | || (code == GE | |
f92430e0 | 5025 | && val_signbit_known_set_p (inner_mode, |
5026 | STORE_FLAG_VALUE)) | |
ea92ba80 | 5027 | #ifdef FLOAT_STORE_FLAG_VALUE |
5028 | || (code == GE | |
cee7491d | 5029 | && SCALAR_FLOAT_MODE_P (inner_mode) |
ea92ba80 | 5030 | && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode), |
5031 | REAL_VALUE_NEGATIVE (fsfv))) | |
5032 | #endif | |
5033 | )) | |
5034 | && COMPARISON_P (SET_SRC (set)) | |
5035 | && (((GET_MODE_CLASS (mode) == MODE_CC) | |
5036 | == (GET_MODE_CLASS (inner_mode) == MODE_CC)) | |
5037 | || mode == VOIDmode || inner_mode == VOIDmode)) | |
5038 | ||
5039 | { | |
5040 | reverse_code = 1; | |
5041 | x = SET_SRC (set); | |
5042 | } | |
5043 | else | |
5044 | break; | |
5045 | } | |
5046 | ||
5047 | else if (reg_set_p (op0, prev)) | |
5048 | /* If this sets OP0, but not directly, we have to give up. */ | |
5049 | break; | |
5050 | ||
5051 | if (x) | |
5052 | { | |
5053 | /* If the caller is expecting the condition to be valid at INSN, | |
5054 | make sure X doesn't change before INSN. */ | |
5055 | if (valid_at_insn_p) | |
5056 | if (modified_in_p (x, prev) || modified_between_p (x, prev, insn)) | |
5057 | break; | |
5058 | if (COMPARISON_P (x)) | |
5059 | code = GET_CODE (x); | |
5060 | if (reverse_code) | |
5061 | { | |
5062 | code = reversed_comparison_code (x, prev); | |
5063 | if (code == UNKNOWN) | |
5064 | return 0; | |
5065 | reverse_code = 0; | |
5066 | } | |
5067 | ||
5068 | op0 = XEXP (x, 0), op1 = XEXP (x, 1); | |
5069 | if (earliest) | |
5070 | *earliest = prev; | |
5071 | } | |
5072 | } | |
5073 | ||
5074 | /* If constant is first, put it last. */ | |
5075 | if (CONSTANT_P (op0)) | |
5076 | code = swap_condition (code), tem = op0, op0 = op1, op1 = tem; | |
5077 | ||
5078 | /* If OP0 is the result of a comparison, we weren't able to find what | |
5079 | was really being compared, so fail. */ | |
5080 | if (!allow_cc_mode | |
5081 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) | |
5082 | return 0; | |
5083 | ||
5084 | /* Canonicalize any ordered comparison with integers involving equality | |
5085 | if we can do computations in the relevant mode and we do not | |
5086 | overflow. */ | |
5087 | ||
5088 | if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_CC | |
971ba038 | 5089 | && CONST_INT_P (op1) |
ea92ba80 | 5090 | && GET_MODE (op0) != VOIDmode |
ded805e6 | 5091 | && GET_MODE_PRECISION (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT) |
ea92ba80 | 5092 | { |
5093 | HOST_WIDE_INT const_val = INTVAL (op1); | |
5094 | unsigned HOST_WIDE_INT uconst_val = const_val; | |
5095 | unsigned HOST_WIDE_INT max_val | |
5096 | = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0)); | |
5097 | ||
5098 | switch (code) | |
5099 | { | |
5100 | case LE: | |
5101 | if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) | |
5102 | code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); | |
5103 | break; | |
5104 | ||
5105 | /* When cross-compiling, const_val might be sign-extended from | |
5106 | BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ | |
5107 | case GE: | |
9d8859f1 | 5108 | if ((const_val & max_val) |
5109 | != ((unsigned HOST_WIDE_INT) 1 | |
ded805e6 | 5110 | << (GET_MODE_PRECISION (GET_MODE (op0)) - 1))) |
ea92ba80 | 5111 | code = GT, op1 = gen_int_mode (const_val - 1, GET_MODE (op0)); |
5112 | break; | |
5113 | ||
5114 | case LEU: | |
5115 | if (uconst_val < max_val) | |
5116 | code = LTU, op1 = gen_int_mode (uconst_val + 1, GET_MODE (op0)); | |
5117 | break; | |
5118 | ||
5119 | case GEU: | |
5120 | if (uconst_val != 0) | |
5121 | code = GTU, op1 = gen_int_mode (uconst_val - 1, GET_MODE (op0)); | |
5122 | break; | |
5123 | ||
5124 | default: | |
5125 | break; | |
5126 | } | |
5127 | } | |
5128 | ||
5129 | /* Never return CC0; return zero instead. */ | |
5130 | if (CC0_P (op0)) | |
5131 | return 0; | |
5132 | ||
5133 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); | |
5134 | } | |
5135 | ||
5136 | /* Given a jump insn JUMP, return the condition that will cause it to branch | |
5137 | to its JUMP_LABEL. If the condition cannot be understood, or is an | |
5138 | inequality floating-point comparison which needs to be reversed, 0 will | |
5139 | be returned. | |
5140 | ||
5141 | If EARLIEST is nonzero, it is a pointer to a place where the earliest | |
5142 | insn used in locating the condition was found. If a replacement test | |
5143 | of the condition is desired, it should be placed in front of that | |
5144 | insn and we will be sure that the inputs are still valid. If EARLIEST | |
5145 | is null, the returned condition will be valid at INSN. | |
5146 | ||
5147 | If ALLOW_CC_MODE is nonzero, allow the condition returned to be a | |
5148 | compare CC mode register. | |
5149 | ||
5150 | VALID_AT_INSN_P is the same as for canonicalize_condition. */ | |
5151 | ||
5152 | rtx | |
5153 | get_condition (rtx jump, rtx *earliest, int allow_cc_mode, int valid_at_insn_p) | |
5154 | { | |
5155 | rtx cond; | |
5156 | int reverse; | |
5157 | rtx set; | |
5158 | ||
5159 | /* If this is not a standard conditional jump, we can't parse it. */ | |
5160 | if (!JUMP_P (jump) | |
5161 | || ! any_condjump_p (jump)) | |
5162 | return 0; | |
5163 | set = pc_set (jump); | |
5164 | ||
5165 | cond = XEXP (SET_SRC (set), 0); | |
5166 | ||
5167 | /* If this branches to JUMP_LABEL when the condition is false, reverse | |
5168 | the condition. */ | |
5169 | reverse | |
5170 | = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF | |
5171 | && XEXP (XEXP (SET_SRC (set), 2), 0) == JUMP_LABEL (jump); | |
5172 | ||
5173 | return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX, | |
5174 | allow_cc_mode, valid_at_insn_p); | |
5175 | } | |
5176 | ||
4956440a | 5177 | /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on |
5178 | TARGET_MODE_REP_EXTENDED. | |
5179 | ||
5180 | Note that we assume that the property of | |
5181 | TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes | |
5182 | narrower than mode B. I.e., if A is a mode narrower than B then in | |
5183 | order to be able to operate on it in mode B, mode A needs to | |
5184 | satisfy the requirements set by the representation of mode B. */ | |
5185 | ||
5186 | static void | |
5187 | init_num_sign_bit_copies_in_rep (void) | |
5188 | { | |
5189 | enum machine_mode mode, in_mode; | |
5190 | ||
5191 | for (in_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); in_mode != VOIDmode; | |
5192 | in_mode = GET_MODE_WIDER_MODE (mode)) | |
5193 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != in_mode; | |
5194 | mode = GET_MODE_WIDER_MODE (mode)) | |
5195 | { | |
5196 | enum machine_mode i; | |
5197 | ||
5198 | /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED | |
5199 | extends to the next widest mode. */ | |
5200 | gcc_assert (targetm.mode_rep_extended (mode, in_mode) == UNKNOWN | |
5201 | || GET_MODE_WIDER_MODE (mode) == in_mode); | |
5202 | ||
5203 | /* We are in in_mode. Count how many bits outside of mode | |
5204 | have to be copies of the sign-bit. */ | |
5205 | for (i = mode; i != in_mode; i = GET_MODE_WIDER_MODE (i)) | |
5206 | { | |
5207 | enum machine_mode wider = GET_MODE_WIDER_MODE (i); | |
5208 | ||
5209 | if (targetm.mode_rep_extended (i, wider) == SIGN_EXTEND | |
5210 | /* We can only check sign-bit copies starting from the | |
5211 | top-bit. In order to be able to check the bits we | |
5212 | have already seen we pretend that subsequent bits | |
5213 | have to be sign-bit copies too. */ | |
5214 | || num_sign_bit_copies_in_rep [in_mode][mode]) | |
5215 | num_sign_bit_copies_in_rep [in_mode][mode] | |
ded805e6 | 5216 | += GET_MODE_PRECISION (wider) - GET_MODE_PRECISION (i); |
4956440a | 5217 | } |
5218 | } | |
5219 | } | |
5220 | ||
fd95fba4 | 5221 | /* Suppose that truncation from the machine mode of X to MODE is not a |
5222 | no-op. See if there is anything special about X so that we can | |
5223 | assume it already contains a truncated value of MODE. */ | |
5224 | ||
5225 | bool | |
b7bf20db | 5226 | truncated_to_mode (enum machine_mode mode, const_rtx x) |
fd95fba4 | 5227 | { |
4956440a | 5228 | /* This register has already been used in MODE without explicit |
5229 | truncation. */ | |
5230 | if (REG_P (x) && rtl_hooks.reg_truncated_to_mode (mode, x)) | |
5231 | return true; | |
5232 | ||
5233 | /* See if we already satisfy the requirements of MODE. If yes we | |
5234 | can just switch to MODE. */ | |
5235 | if (num_sign_bit_copies_in_rep[GET_MODE (x)][mode] | |
5236 | && (num_sign_bit_copies (x, GET_MODE (x)) | |
5237 | >= num_sign_bit_copies_in_rep[GET_MODE (x)][mode] + 1)) | |
5238 | return true; | |
fd95fba4 | 5239 | |
4956440a | 5240 | return false; |
5241 | } | |
a87cf6e5 | 5242 | \f |
5243 | /* Initialize non_rtx_starting_operands, which is used to speed up | |
5244 | for_each_rtx. */ | |
5245 | void | |
5246 | init_rtlanal (void) | |
5247 | { | |
5248 | int i; | |
5249 | for (i = 0; i < NUM_RTX_CODE; i++) | |
5250 | { | |
5251 | const char *format = GET_RTX_FORMAT (i); | |
5252 | const char *first = strpbrk (format, "eEV"); | |
5253 | non_rtx_starting_operands[i] = first ? first - format : -1; | |
5254 | } | |
4956440a | 5255 | |
5256 | init_num_sign_bit_copies_in_rep (); | |
a87cf6e5 | 5257 | } |
e207fd7a | 5258 | \f |
5259 | /* Check whether this is a constant pool constant. */ | |
5260 | bool | |
5261 | constant_pool_constant_p (rtx x) | |
5262 | { | |
5263 | x = avoid_constant_pool_reference (x); | |
78f1962f | 5264 | return CONST_DOUBLE_P (x); |
e207fd7a | 5265 | } |
d16b48d5 | 5266 | \f |
5267 | /* If M is a bitmask that selects a field of low-order bits within an item but | |
5268 | not the entire word, return the length of the field. Return -1 otherwise. | |
5269 | M is used in machine mode MODE. */ | |
5270 | ||
5271 | int | |
5272 | low_bitmask_len (enum machine_mode mode, unsigned HOST_WIDE_INT m) | |
5273 | { | |
5274 | if (mode != VOIDmode) | |
5275 | { | |
ded805e6 | 5276 | if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT) |
d16b48d5 | 5277 | return -1; |
5278 | m &= GET_MODE_MASK (mode); | |
5279 | } | |
5280 | ||
5281 | return exact_log2 (m + 1); | |
5282 | } | |
87cf5753 | 5283 | |
5284 | /* Return the mode of MEM's address. */ | |
5285 | ||
5286 | enum machine_mode | |
5287 | get_address_mode (rtx mem) | |
5288 | { | |
5289 | enum machine_mode mode; | |
5290 | ||
5291 | gcc_assert (MEM_P (mem)); | |
5292 | mode = GET_MODE (XEXP (mem, 0)); | |
5293 | if (mode != VOIDmode) | |
5294 | return mode; | |
5295 | return targetm.addr_space.address_mode (MEM_ADDR_SPACE (mem)); | |
5296 | } | |
21eb4639 | 5297 | \f |
5298 | /* Split up a CONST_DOUBLE or integer constant rtx | |
5299 | into two rtx's for single words, | |
5300 | storing in *FIRST the word that comes first in memory in the target | |
5301 | and in *SECOND the other. */ | |
5302 | ||
5303 | void | |
5304 | split_double (rtx value, rtx *first, rtx *second) | |
5305 | { | |
5306 | if (CONST_INT_P (value)) | |
5307 | { | |
5308 | if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD)) | |
5309 | { | |
5310 | /* In this case the CONST_INT holds both target words. | |
5311 | Extract the bits from it into two word-sized pieces. | |
5312 | Sign extend each half to HOST_WIDE_INT. */ | |
5313 | unsigned HOST_WIDE_INT low, high; | |
5314 | unsigned HOST_WIDE_INT mask, sign_bit, sign_extend; | |
5315 | unsigned bits_per_word = BITS_PER_WORD; | |
5316 | ||
5317 | /* Set sign_bit to the most significant bit of a word. */ | |
5318 | sign_bit = 1; | |
5319 | sign_bit <<= bits_per_word - 1; | |
5320 | ||
5321 | /* Set mask so that all bits of the word are set. We could | |
5322 | have used 1 << BITS_PER_WORD instead of basing the | |
5323 | calculation on sign_bit. However, on machines where | |
5324 | HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a | |
5325 | compiler warning, even though the code would never be | |
5326 | executed. */ | |
5327 | mask = sign_bit << 1; | |
5328 | mask--; | |
5329 | ||
5330 | /* Set sign_extend as any remaining bits. */ | |
5331 | sign_extend = ~mask; | |
5332 | ||
5333 | /* Pick the lower word and sign-extend it. */ | |
5334 | low = INTVAL (value); | |
5335 | low &= mask; | |
5336 | if (low & sign_bit) | |
5337 | low |= sign_extend; | |
5338 | ||
5339 | /* Pick the higher word, shifted to the least significant | |
5340 | bits, and sign-extend it. */ | |
5341 | high = INTVAL (value); | |
5342 | high >>= bits_per_word - 1; | |
5343 | high >>= 1; | |
5344 | high &= mask; | |
5345 | if (high & sign_bit) | |
5346 | high |= sign_extend; | |
5347 | ||
5348 | /* Store the words in the target machine order. */ | |
5349 | if (WORDS_BIG_ENDIAN) | |
5350 | { | |
5351 | *first = GEN_INT (high); | |
5352 | *second = GEN_INT (low); | |
5353 | } | |
5354 | else | |
5355 | { | |
5356 | *first = GEN_INT (low); | |
5357 | *second = GEN_INT (high); | |
5358 | } | |
5359 | } | |
5360 | else | |
5361 | { | |
5362 | /* The rule for using CONST_INT for a wider mode | |
5363 | is that we regard the value as signed. | |
5364 | So sign-extend it. */ | |
5365 | rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx); | |
5366 | if (WORDS_BIG_ENDIAN) | |
5367 | { | |
5368 | *first = high; | |
5369 | *second = value; | |
5370 | } | |
5371 | else | |
5372 | { | |
5373 | *first = value; | |
5374 | *second = high; | |
5375 | } | |
5376 | } | |
5377 | } | |
78f1962f | 5378 | else if (!CONST_DOUBLE_P (value)) |
21eb4639 | 5379 | { |
5380 | if (WORDS_BIG_ENDIAN) | |
5381 | { | |
5382 | *first = const0_rtx; | |
5383 | *second = value; | |
5384 | } | |
5385 | else | |
5386 | { | |
5387 | *first = value; | |
5388 | *second = const0_rtx; | |
5389 | } | |
5390 | } | |
5391 | else if (GET_MODE (value) == VOIDmode | |
5392 | /* This is the old way we did CONST_DOUBLE integers. */ | |
5393 | || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT) | |
5394 | { | |
5395 | /* In an integer, the words are defined as most and least significant. | |
5396 | So order them by the target's convention. */ | |
5397 | if (WORDS_BIG_ENDIAN) | |
5398 | { | |
5399 | *first = GEN_INT (CONST_DOUBLE_HIGH (value)); | |
5400 | *second = GEN_INT (CONST_DOUBLE_LOW (value)); | |
5401 | } | |
5402 | else | |
5403 | { | |
5404 | *first = GEN_INT (CONST_DOUBLE_LOW (value)); | |
5405 | *second = GEN_INT (CONST_DOUBLE_HIGH (value)); | |
5406 | } | |
5407 | } | |
5408 | else | |
5409 | { | |
5410 | REAL_VALUE_TYPE r; | |
5411 | long l[2]; | |
5412 | REAL_VALUE_FROM_CONST_DOUBLE (r, value); | |
5413 | ||
5414 | /* Note, this converts the REAL_VALUE_TYPE to the target's | |
5415 | format, splits up the floating point double and outputs | |
5416 | exactly 32 bits of it into each of l[0] and l[1] -- | |
5417 | not necessarily BITS_PER_WORD bits. */ | |
5418 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
5419 | ||
5420 | /* If 32 bits is an entire word for the target, but not for the host, | |
5421 | then sign-extend on the host so that the number will look the same | |
5422 | way on the host that it would on the target. See for instance | |
5423 | simplify_unary_operation. The #if is needed to avoid compiler | |
5424 | warnings. */ | |
5425 | ||
5426 | #if HOST_BITS_PER_LONG > 32 | |
5427 | if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32) | |
5428 | { | |
5429 | if (l[0] & ((long) 1 << 31)) | |
5430 | l[0] |= ((long) (-1) << 32); | |
5431 | if (l[1] & ((long) 1 << 31)) | |
5432 | l[1] |= ((long) (-1) << 32); | |
5433 | } | |
5434 | #endif | |
5435 | ||
5436 | *first = GEN_INT (l[0]); | |
5437 | *second = GEN_INT (l[1]); | |
5438 | } | |
5439 | } | |
5440 |