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6adce0fb | 1 | /* Instruction scheduling pass. This file computes dependencies between |
2 | instructions. | |
aad93da1 | 3 | Copyright (C) 1992-2017 Free Software Foundation, Inc. |
6adce0fb | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
5 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
6 | ||
f12b58b3 | 7 | This file is part of GCC. |
6adce0fb | 8 | |
f12b58b3 | 9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 11 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 12 | version. |
6adce0fb | 13 | |
f12b58b3 | 14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
6adce0fb | 16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
17 | for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
6adce0fb | 22 | \f |
23 | #include "config.h" | |
24 | #include "system.h" | |
805e22b2 | 25 | #include "coretypes.h" |
9ef16211 | 26 | #include "backend.h" |
7c29e30e | 27 | #include "target.h" |
6adce0fb | 28 | #include "rtl.h" |
7c29e30e | 29 | #include "tree.h" |
9ef16211 | 30 | #include "df.h" |
7c29e30e | 31 | #include "insn-config.h" |
6adce0fb | 32 | #include "regs.h" |
ad7b10a2 | 33 | #include "memmodel.h" |
7c29e30e | 34 | #include "ira.h" |
35 | #include "ira-int.h" | |
6adce0fb | 36 | #include "insn-attr.h" |
94ea8568 | 37 | #include "cfgbuild.h" |
6adce0fb | 38 | #include "sched-int.h" |
85de291e | 39 | #include "params.h" |
503f2817 | 40 | #include "cselib.h" |
6adce0fb | 41 | |
db982eeb | 42 | #ifdef INSN_SCHEDULING |
43 | ||
e1ab7874 | 44 | /* Holds current parameters for the dependency analyzer. */ |
45 | struct sched_deps_info_def *sched_deps_info; | |
46 | ||
47 | /* The data is specific to the Haifa scheduler. */ | |
f1f41a6c | 48 | vec<haifa_deps_insn_data_def> |
1e094109 | 49 | h_d_i_d = vNULL; |
e1ab7874 | 50 | |
9997bd27 | 51 | /* Return the major type present in the DS. */ |
52 | enum reg_note | |
53 | ds_to_dk (ds_t ds) | |
54 | { | |
55 | if (ds & DEP_TRUE) | |
56 | return REG_DEP_TRUE; | |
57 | ||
58 | if (ds & DEP_OUTPUT) | |
59 | return REG_DEP_OUTPUT; | |
60 | ||
effd1640 | 61 | if (ds & DEP_CONTROL) |
62 | return REG_DEP_CONTROL; | |
63 | ||
9997bd27 | 64 | gcc_assert (ds & DEP_ANTI); |
65 | ||
66 | return REG_DEP_ANTI; | |
67 | } | |
68 | ||
69 | /* Return equivalent dep_status. */ | |
70 | ds_t | |
71 | dk_to_ds (enum reg_note dk) | |
72 | { | |
73 | switch (dk) | |
74 | { | |
75 | case REG_DEP_TRUE: | |
76 | return DEP_TRUE; | |
77 | ||
78 | case REG_DEP_OUTPUT: | |
79 | return DEP_OUTPUT; | |
80 | ||
effd1640 | 81 | case REG_DEP_CONTROL: |
82 | return DEP_CONTROL; | |
83 | ||
9997bd27 | 84 | default: |
85 | gcc_assert (dk == REG_DEP_ANTI); | |
86 | return DEP_ANTI; | |
87 | } | |
88 | } | |
89 | ||
90 | /* Functions to operate with dependence information container - dep_t. */ | |
91 | ||
92 | /* Init DEP with the arguments. */ | |
93f6b030 | 93 | void |
fc5ad70a | 94 | init_dep_1 (dep_t dep, rtx_insn *pro, rtx_insn *con, enum reg_note type, ds_t ds) |
9997bd27 | 95 | { |
fc5ad70a | 96 | DEP_PRO (dep) = pro; |
97 | DEP_CON (dep) = con; | |
93f6b030 | 98 | DEP_TYPE (dep) = type; |
9997bd27 | 99 | DEP_STATUS (dep) = ds; |
38354bb6 | 100 | DEP_COST (dep) = UNKNOWN_DEP_COST; |
d452a169 | 101 | DEP_NONREG (dep) = 0; |
102 | DEP_MULTIPLE (dep) = 0; | |
103 | DEP_REPLACE (dep) = NULL; | |
9997bd27 | 104 | } |
105 | ||
106 | /* Init DEP with the arguments. | |
107 | While most of the scheduler (including targets) only need the major type | |
f2b32076 | 108 | of the dependency, it is convenient to hide full dep_status from them. */ |
9997bd27 | 109 | void |
fc5ad70a | 110 | init_dep (dep_t dep, rtx_insn *pro, rtx_insn *con, enum reg_note kind) |
9997bd27 | 111 | { |
112 | ds_t ds; | |
113 | ||
93f6b030 | 114 | if ((current_sched_info->flags & USE_DEPS_LIST)) |
9997bd27 | 115 | ds = dk_to_ds (kind); |
116 | else | |
2261c559 | 117 | ds = 0; |
9997bd27 | 118 | |
119 | init_dep_1 (dep, pro, con, kind, ds); | |
120 | } | |
121 | ||
122 | /* Make a copy of FROM in TO. */ | |
123 | static void | |
124 | copy_dep (dep_t to, dep_t from) | |
125 | { | |
126 | memcpy (to, from, sizeof (*to)); | |
127 | } | |
128 | ||
93f6b030 | 129 | static void dump_ds (FILE *, ds_t); |
9997bd27 | 130 | |
93f6b030 | 131 | /* Define flags for dump_dep (). */ |
132 | ||
133 | /* Dump producer of the dependence. */ | |
134 | #define DUMP_DEP_PRO (2) | |
135 | ||
136 | /* Dump consumer of the dependence. */ | |
137 | #define DUMP_DEP_CON (4) | |
138 | ||
139 | /* Dump type of the dependence. */ | |
140 | #define DUMP_DEP_TYPE (8) | |
141 | ||
142 | /* Dump status of the dependence. */ | |
143 | #define DUMP_DEP_STATUS (16) | |
144 | ||
145 | /* Dump all information about the dependence. */ | |
146 | #define DUMP_DEP_ALL (DUMP_DEP_PRO | DUMP_DEP_CON | DUMP_DEP_TYPE \ | |
147 | |DUMP_DEP_STATUS) | |
148 | ||
149 | /* Dump DEP to DUMP. | |
150 | FLAGS is a bit mask specifying what information about DEP needs | |
151 | to be printed. | |
152 | If FLAGS has the very first bit set, then dump all information about DEP | |
153 | and propagate this bit into the callee dump functions. */ | |
154 | static void | |
155 | dump_dep (FILE *dump, dep_t dep, int flags) | |
9997bd27 | 156 | { |
93f6b030 | 157 | if (flags & 1) |
158 | flags |= DUMP_DEP_ALL; | |
159 | ||
160 | fprintf (dump, "<"); | |
161 | ||
162 | if (flags & DUMP_DEP_PRO) | |
163 | fprintf (dump, "%d; ", INSN_UID (DEP_PRO (dep))); | |
164 | ||
165 | if (flags & DUMP_DEP_CON) | |
166 | fprintf (dump, "%d; ", INSN_UID (DEP_CON (dep))); | |
167 | ||
168 | if (flags & DUMP_DEP_TYPE) | |
169 | { | |
170 | char t; | |
171 | enum reg_note type = DEP_TYPE (dep); | |
172 | ||
173 | switch (type) | |
174 | { | |
175 | case REG_DEP_TRUE: | |
176 | t = 't'; | |
177 | break; | |
178 | ||
179 | case REG_DEP_OUTPUT: | |
180 | t = 'o'; | |
181 | break; | |
9997bd27 | 182 | |
effd1640 | 183 | case REG_DEP_CONTROL: |
184 | t = 'c'; | |
185 | break; | |
186 | ||
93f6b030 | 187 | case REG_DEP_ANTI: |
188 | t = 'a'; | |
189 | break; | |
190 | ||
191 | default: | |
192 | gcc_unreachable (); | |
193 | break; | |
194 | } | |
195 | ||
196 | fprintf (dump, "%c; ", t); | |
197 | } | |
198 | ||
199 | if (flags & DUMP_DEP_STATUS) | |
200 | { | |
201 | if (current_sched_info->flags & USE_DEPS_LIST) | |
202 | dump_ds (dump, DEP_STATUS (dep)); | |
203 | } | |
204 | ||
205 | fprintf (dump, ">"); | |
206 | } | |
207 | ||
208 | /* Default flags for dump_dep (). */ | |
209 | static int dump_dep_flags = (DUMP_DEP_PRO | DUMP_DEP_CON); | |
210 | ||
211 | /* Dump all fields of DEP to STDERR. */ | |
212 | void | |
213 | sd_debug_dep (dep_t dep) | |
214 | { | |
215 | dump_dep (stderr, dep, 1); | |
216 | fprintf (stderr, "\n"); | |
9997bd27 | 217 | } |
218 | ||
c971b445 | 219 | /* Determine whether DEP is a dependency link of a non-debug insn on a |
220 | debug insn. */ | |
221 | ||
222 | static inline bool | |
223 | depl_on_debug_p (dep_link_t dep) | |
224 | { | |
225 | return (DEBUG_INSN_P (DEP_LINK_PRO (dep)) | |
226 | && !DEBUG_INSN_P (DEP_LINK_CON (dep))); | |
227 | } | |
228 | ||
93f6b030 | 229 | /* Functions to operate with a single link from the dependencies lists - |
230 | dep_link_t. */ | |
231 | ||
9997bd27 | 232 | /* Attach L to appear after link X whose &DEP_LINK_NEXT (X) is given by |
233 | PREV_NEXT_P. */ | |
234 | static void | |
235 | attach_dep_link (dep_link_t l, dep_link_t *prev_nextp) | |
236 | { | |
237 | dep_link_t next = *prev_nextp; | |
238 | ||
239 | gcc_assert (DEP_LINK_PREV_NEXTP (l) == NULL | |
240 | && DEP_LINK_NEXT (l) == NULL); | |
241 | ||
242 | /* Init node being inserted. */ | |
243 | DEP_LINK_PREV_NEXTP (l) = prev_nextp; | |
244 | DEP_LINK_NEXT (l) = next; | |
245 | ||
246 | /* Fix next node. */ | |
247 | if (next != NULL) | |
248 | { | |
249 | gcc_assert (DEP_LINK_PREV_NEXTP (next) == prev_nextp); | |
250 | ||
251 | DEP_LINK_PREV_NEXTP (next) = &DEP_LINK_NEXT (l); | |
252 | } | |
253 | ||
254 | /* Fix prev node. */ | |
255 | *prev_nextp = l; | |
256 | } | |
257 | ||
258 | /* Add dep_link LINK to deps_list L. */ | |
259 | static void | |
260 | add_to_deps_list (dep_link_t link, deps_list_t l) | |
261 | { | |
262 | attach_dep_link (link, &DEPS_LIST_FIRST (l)); | |
93f6b030 | 263 | |
c971b445 | 264 | /* Don't count debug deps. */ |
265 | if (!depl_on_debug_p (link)) | |
266 | ++DEPS_LIST_N_LINKS (l); | |
9997bd27 | 267 | } |
268 | ||
269 | /* Detach dep_link L from the list. */ | |
270 | static void | |
271 | detach_dep_link (dep_link_t l) | |
272 | { | |
273 | dep_link_t *prev_nextp = DEP_LINK_PREV_NEXTP (l); | |
274 | dep_link_t next = DEP_LINK_NEXT (l); | |
275 | ||
276 | *prev_nextp = next; | |
277 | ||
278 | if (next != NULL) | |
279 | DEP_LINK_PREV_NEXTP (next) = prev_nextp; | |
280 | ||
9997bd27 | 281 | DEP_LINK_PREV_NEXTP (l) = NULL; |
282 | DEP_LINK_NEXT (l) = NULL; | |
283 | } | |
284 | ||
93f6b030 | 285 | /* Remove link LINK from list LIST. */ |
286 | static void | |
287 | remove_from_deps_list (dep_link_t link, deps_list_t list) | |
9997bd27 | 288 | { |
289 | detach_dep_link (link); | |
9997bd27 | 290 | |
c971b445 | 291 | /* Don't count debug deps. */ |
292 | if (!depl_on_debug_p (link)) | |
293 | --DEPS_LIST_N_LINKS (list); | |
9997bd27 | 294 | } |
295 | ||
93f6b030 | 296 | /* Move link LINK from list FROM to list TO. */ |
9997bd27 | 297 | static void |
93f6b030 | 298 | move_dep_link (dep_link_t link, deps_list_t from, deps_list_t to) |
9997bd27 | 299 | { |
93f6b030 | 300 | remove_from_deps_list (link, from); |
301 | add_to_deps_list (link, to); | |
9997bd27 | 302 | } |
303 | ||
93f6b030 | 304 | /* Return true of LINK is not attached to any list. */ |
305 | static bool | |
306 | dep_link_is_detached_p (dep_link_t link) | |
9997bd27 | 307 | { |
93f6b030 | 308 | return DEP_LINK_PREV_NEXTP (link) == NULL; |
9997bd27 | 309 | } |
310 | ||
93f6b030 | 311 | /* Pool to hold all dependency nodes (dep_node_t). */ |
e16712b1 | 312 | static object_allocator<_dep_node> *dn_pool; |
9997bd27 | 313 | |
93f6b030 | 314 | /* Number of dep_nodes out there. */ |
315 | static int dn_pool_diff = 0; | |
9997bd27 | 316 | |
93f6b030 | 317 | /* Create a dep_node. */ |
318 | static dep_node_t | |
319 | create_dep_node (void) | |
320 | { | |
3da86c6b | 321 | dep_node_t n = dn_pool->allocate (); |
93f6b030 | 322 | dep_link_t back = DEP_NODE_BACK (n); |
323 | dep_link_t forw = DEP_NODE_FORW (n); | |
9997bd27 | 324 | |
93f6b030 | 325 | DEP_LINK_NODE (back) = n; |
326 | DEP_LINK_NEXT (back) = NULL; | |
327 | DEP_LINK_PREV_NEXTP (back) = NULL; | |
9997bd27 | 328 | |
93f6b030 | 329 | DEP_LINK_NODE (forw) = n; |
330 | DEP_LINK_NEXT (forw) = NULL; | |
331 | DEP_LINK_PREV_NEXTP (forw) = NULL; | |
9997bd27 | 332 | |
93f6b030 | 333 | ++dn_pool_diff; |
9997bd27 | 334 | |
93f6b030 | 335 | return n; |
9997bd27 | 336 | } |
337 | ||
93f6b030 | 338 | /* Delete dep_node N. N must not be connected to any deps_list. */ |
9997bd27 | 339 | static void |
93f6b030 | 340 | delete_dep_node (dep_node_t n) |
9997bd27 | 341 | { |
93f6b030 | 342 | gcc_assert (dep_link_is_detached_p (DEP_NODE_BACK (n)) |
343 | && dep_link_is_detached_p (DEP_NODE_FORW (n))); | |
9997bd27 | 344 | |
a776325f | 345 | XDELETE (DEP_REPLACE (DEP_NODE_DEP (n))); |
346 | ||
93f6b030 | 347 | --dn_pool_diff; |
9997bd27 | 348 | |
3da86c6b | 349 | dn_pool->remove (n); |
9997bd27 | 350 | } |
351 | ||
93f6b030 | 352 | /* Pool to hold dependencies lists (deps_list_t). */ |
e16712b1 | 353 | static object_allocator<_deps_list> *dl_pool; |
9997bd27 | 354 | |
93f6b030 | 355 | /* Number of deps_lists out there. */ |
356 | static int dl_pool_diff = 0; | |
9997bd27 | 357 | |
93f6b030 | 358 | /* Functions to operate with dependences lists - deps_list_t. */ |
9997bd27 | 359 | |
93f6b030 | 360 | /* Return true if list L is empty. */ |
9997bd27 | 361 | static bool |
93f6b030 | 362 | deps_list_empty_p (deps_list_t l) |
9997bd27 | 363 | { |
93f6b030 | 364 | return DEPS_LIST_N_LINKS (l) == 0; |
9997bd27 | 365 | } |
366 | ||
93f6b030 | 367 | /* Create a new deps_list. */ |
368 | static deps_list_t | |
369 | create_deps_list (void) | |
9997bd27 | 370 | { |
3da86c6b | 371 | deps_list_t l = dl_pool->allocate (); |
9997bd27 | 372 | |
93f6b030 | 373 | DEPS_LIST_FIRST (l) = NULL; |
374 | DEPS_LIST_N_LINKS (l) = 0; | |
9997bd27 | 375 | |
93f6b030 | 376 | ++dl_pool_diff; |
377 | return l; | |
9997bd27 | 378 | } |
379 | ||
93f6b030 | 380 | /* Free deps_list L. */ |
381 | static void | |
382 | free_deps_list (deps_list_t l) | |
9997bd27 | 383 | { |
93f6b030 | 384 | gcc_assert (deps_list_empty_p (l)); |
9997bd27 | 385 | |
93f6b030 | 386 | --dl_pool_diff; |
9997bd27 | 387 | |
3da86c6b | 388 | dl_pool->remove (l); |
9997bd27 | 389 | } |
390 | ||
93f6b030 | 391 | /* Return true if there is no dep_nodes and deps_lists out there. |
becfaa62 | 392 | After the region is scheduled all the dependency nodes and lists |
93f6b030 | 393 | should [generally] be returned to pool. */ |
394 | bool | |
395 | deps_pools_are_empty_p (void) | |
9997bd27 | 396 | { |
93f6b030 | 397 | return dn_pool_diff == 0 && dl_pool_diff == 0; |
9997bd27 | 398 | } |
399 | ||
93f6b030 | 400 | /* Remove all elements from L. */ |
401 | static void | |
402 | clear_deps_list (deps_list_t l) | |
9997bd27 | 403 | { |
93f6b030 | 404 | do |
405 | { | |
406 | dep_link_t link = DEPS_LIST_FIRST (l); | |
9997bd27 | 407 | |
93f6b030 | 408 | if (link == NULL) |
409 | break; | |
9997bd27 | 410 | |
93f6b030 | 411 | remove_from_deps_list (link, l); |
9997bd27 | 412 | } |
93f6b030 | 413 | while (1); |
9997bd27 | 414 | } |
6adce0fb | 415 | |
2261c559 | 416 | /* Decide whether a dependency should be treated as a hard or a speculative |
417 | dependency. */ | |
418 | static bool | |
419 | dep_spec_p (dep_t dep) | |
420 | { | |
421 | if (current_sched_info->flags & DO_SPECULATION) | |
effd1640 | 422 | { |
423 | if (DEP_STATUS (dep) & SPECULATIVE) | |
424 | return true; | |
425 | } | |
426 | if (current_sched_info->flags & DO_PREDICATION) | |
427 | { | |
428 | if (DEP_TYPE (dep) == REG_DEP_CONTROL) | |
429 | return true; | |
430 | } | |
d452a169 | 431 | if (DEP_REPLACE (dep) != NULL) |
432 | return true; | |
2261c559 | 433 | return false; |
434 | } | |
435 | ||
6adce0fb | 436 | static regset reg_pending_sets; |
437 | static regset reg_pending_clobbers; | |
5deaeb50 | 438 | static regset reg_pending_uses; |
effd1640 | 439 | static regset reg_pending_control_uses; |
c14a239f | 440 | static enum reg_pending_barrier_mode reg_pending_barrier; |
6adce0fb | 441 | |
a7dcf969 | 442 | /* Hard registers implicitly clobbered or used (or may be implicitly |
443 | clobbered or used) by the currently analyzed insn. For example, | |
444 | insn in its constraint has one register class. Even if there is | |
445 | currently no hard register in the insn, the particular hard | |
446 | register will be in the insn after reload pass because the | |
447 | constraint requires it. */ | |
448 | static HARD_REG_SET implicit_reg_pending_clobbers; | |
449 | static HARD_REG_SET implicit_reg_pending_uses; | |
450 | ||
6adce0fb | 451 | /* To speed up the test for duplicate dependency links we keep a |
452 | record of dependencies created by add_dependence when the average | |
453 | number of instructions in a basic block is very large. | |
454 | ||
455 | Studies have shown that there is typically around 5 instructions between | |
456 | branches for typical C code. So we can make a guess that the average | |
457 | basic block is approximately 5 instructions long; we will choose 100X | |
458 | the average size as a very large basic block. | |
459 | ||
460 | Each insn has associated bitmaps for its dependencies. Each bitmap | |
461 | has enough entries to represent a dependency on any other insn in | |
462 | the insn chain. All bitmap for true dependencies cache is | |
1be87b72 | 463 | allocated then the rest two ones are also allocated. */ |
e1ab7874 | 464 | static bitmap_head *true_dependency_cache = NULL; |
465 | static bitmap_head *output_dependency_cache = NULL; | |
466 | static bitmap_head *anti_dependency_cache = NULL; | |
effd1640 | 467 | static bitmap_head *control_dependency_cache = NULL; |
e1ab7874 | 468 | static bitmap_head *spec_dependency_cache = NULL; |
f4b6f424 | 469 | static int cache_size; |
6adce0fb | 470 | |
d452a169 | 471 | /* True if we should mark added dependencies as a non-register deps. */ |
472 | static bool mark_as_hard; | |
473 | ||
5493cb9a | 474 | static int deps_may_trap_p (const_rtx); |
b24ef467 | 475 | static void add_dependence_1 (rtx_insn *, rtx_insn *, enum reg_note); |
54267fdf | 476 | static void add_dependence_list (rtx_insn *, rtx_insn_list *, int, |
477 | enum reg_note, bool); | |
b24ef467 | 478 | static void add_dependence_list_and_free (struct deps_desc *, rtx_insn *, |
54267fdf | 479 | rtx_insn_list **, int, enum reg_note, |
480 | bool); | |
71ce7f59 | 481 | static void delete_all_dependences (rtx_insn *); |
b24ef467 | 482 | static void chain_to_prev_insn (rtx_insn *); |
6adce0fb | 483 | |
b24ef467 | 484 | static void flush_pending_lists (struct deps_desc *, rtx_insn *, int, int); |
485 | static void sched_analyze_1 (struct deps_desc *, rtx, rtx_insn *); | |
486 | static void sched_analyze_2 (struct deps_desc *, rtx, rtx_insn *); | |
487 | static void sched_analyze_insn (struct deps_desc *, rtx, rtx_insn *); | |
4164e76b | 488 | |
355af201 | 489 | static bool sched_has_condition_p (const rtx_insn *); |
e1ab7874 | 490 | static int conditions_mutex_p (const_rtx, const_rtx, bool, bool); |
4d64d9a4 | 491 | |
93f6b030 | 492 | static enum DEPS_ADJUST_RESULT maybe_add_or_update_dep_1 (dep_t, bool, |
493 | rtx, rtx); | |
494 | static enum DEPS_ADJUST_RESULT add_or_update_dep_1 (dep_t, bool, rtx, rtx); | |
4d64d9a4 | 495 | |
93f6b030 | 496 | static void check_dep (dep_t, bool); |
382ecba7 | 497 | |
6adce0fb | 498 | \f |
970c0c06 | 499 | /* Return nonzero if a load of the memory reference MEM can cause a trap. */ |
500 | ||
501 | static int | |
5493cb9a | 502 | deps_may_trap_p (const_rtx mem) |
970c0c06 | 503 | { |
5493cb9a | 504 | const_rtx addr = XEXP (mem, 0); |
970c0c06 | 505 | |
12cb06ad | 506 | if (REG_P (addr) && REGNO (addr) >= FIRST_PSEUDO_REGISTER) |
507 | { | |
5493cb9a | 508 | const_rtx t = get_reg_known_value (REGNO (addr)); |
12cb06ad | 509 | if (t) |
510 | addr = t; | |
511 | } | |
970c0c06 | 512 | return rtx_addr_can_trap_p (addr); |
513 | } | |
514 | \f | |
4164e76b | 515 | |
e1ab7874 | 516 | /* Find the condition under which INSN is executed. If REV is not NULL, |
517 | it is set to TRUE when the returned comparison should be reversed | |
60ba0654 | 518 | to get the actual condition. */ |
4164e76b | 519 | static rtx |
355af201 | 520 | sched_get_condition_with_rev_uncached (const rtx_insn *insn, bool *rev) |
4164e76b | 521 | { |
522 | rtx pat = PATTERN (insn); | |
d87bddc5 | 523 | rtx src; |
4164e76b | 524 | |
e1ab7874 | 525 | if (rev) |
526 | *rev = false; | |
527 | ||
4164e76b | 528 | if (GET_CODE (pat) == COND_EXEC) |
60ba0654 | 529 | return COND_EXEC_TEST (pat); |
bbb82bbf | 530 | |
531 | if (!any_condjump_p (insn) || !onlyjump_p (insn)) | |
4164e76b | 532 | return 0; |
bbb82bbf | 533 | |
d87bddc5 | 534 | src = SET_SRC (pc_set (insn)); |
e6a25dc9 | 535 | |
d87bddc5 | 536 | if (XEXP (src, 2) == pc_rtx) |
60ba0654 | 537 | return XEXP (src, 0); |
d87bddc5 | 538 | else if (XEXP (src, 1) == pc_rtx) |
bbb82bbf | 539 | { |
d87bddc5 | 540 | rtx cond = XEXP (src, 0); |
bbb82bbf | 541 | enum rtx_code revcode = reversed_comparison_code (cond, insn); |
542 | ||
543 | if (revcode == UNKNOWN) | |
544 | return 0; | |
e1ab7874 | 545 | |
546 | if (rev) | |
547 | *rev = true; | |
548 | return cond; | |
bbb82bbf | 549 | } |
af4ff459 | 550 | |
551 | return 0; | |
4164e76b | 552 | } |
553 | ||
effd1640 | 554 | /* Return the condition under which INSN does not execute (i.e. the |
555 | not-taken condition for a conditional branch), or NULL if we cannot | |
556 | find such a condition. The caller should make a copy of the condition | |
557 | before using it. */ | |
558 | rtx | |
355af201 | 559 | sched_get_reverse_condition_uncached (const rtx_insn *insn) |
effd1640 | 560 | { |
561 | bool rev; | |
562 | rtx cond = sched_get_condition_with_rev_uncached (insn, &rev); | |
563 | if (cond == NULL_RTX) | |
564 | return cond; | |
565 | if (!rev) | |
566 | { | |
567 | enum rtx_code revcode = reversed_comparison_code (cond, insn); | |
568 | cond = gen_rtx_fmt_ee (revcode, GET_MODE (cond), | |
569 | XEXP (cond, 0), | |
570 | XEXP (cond, 1)); | |
571 | } | |
572 | return cond; | |
573 | } | |
574 | ||
60ba0654 | 575 | /* Caching variant of sched_get_condition_with_rev_uncached. |
576 | We only do actual work the first time we come here for an insn; the | |
577 | results are cached in INSN_CACHED_COND and INSN_REVERSE_COND. */ | |
578 | static rtx | |
355af201 | 579 | sched_get_condition_with_rev (const rtx_insn *insn, bool *rev) |
60ba0654 | 580 | { |
581 | bool tmp; | |
582 | ||
583 | if (INSN_LUID (insn) == 0) | |
584 | return sched_get_condition_with_rev_uncached (insn, rev); | |
585 | ||
586 | if (INSN_CACHED_COND (insn) == const_true_rtx) | |
587 | return NULL_RTX; | |
588 | ||
589 | if (INSN_CACHED_COND (insn) != NULL_RTX) | |
590 | { | |
591 | if (rev) | |
592 | *rev = INSN_REVERSE_COND (insn); | |
593 | return INSN_CACHED_COND (insn); | |
594 | } | |
595 | ||
596 | INSN_CACHED_COND (insn) = sched_get_condition_with_rev_uncached (insn, &tmp); | |
597 | INSN_REVERSE_COND (insn) = tmp; | |
598 | ||
599 | if (INSN_CACHED_COND (insn) == NULL_RTX) | |
600 | { | |
601 | INSN_CACHED_COND (insn) = const_true_rtx; | |
602 | return NULL_RTX; | |
603 | } | |
604 | ||
605 | if (rev) | |
606 | *rev = INSN_REVERSE_COND (insn); | |
607 | return INSN_CACHED_COND (insn); | |
608 | } | |
609 | ||
e1ab7874 | 610 | /* True when we can find a condition under which INSN is executed. */ |
611 | static bool | |
355af201 | 612 | sched_has_condition_p (const rtx_insn *insn) |
e1ab7874 | 613 | { |
614 | return !! sched_get_condition_with_rev (insn, NULL); | |
615 | } | |
616 | ||
e6a25dc9 | 617 | \f |
4164e76b | 618 | |
e1ab7874 | 619 | /* Return nonzero if conditions COND1 and COND2 can never be both true. */ |
4164e76b | 620 | static int |
e1ab7874 | 621 | conditions_mutex_p (const_rtx cond1, const_rtx cond2, bool rev1, bool rev2) |
4164e76b | 622 | { |
6720e96c | 623 | if (COMPARISON_P (cond1) |
624 | && COMPARISON_P (cond2) | |
e1ab7874 | 625 | && GET_CODE (cond1) == |
626 | (rev1==rev2 | |
627 | ? reversed_comparison_code (cond2, NULL) | |
628 | : GET_CODE (cond2)) | |
6aed13f1 | 629 | && rtx_equal_p (XEXP (cond1, 0), XEXP (cond2, 0)) |
4164e76b | 630 | && XEXP (cond1, 1) == XEXP (cond2, 1)) |
631 | return 1; | |
632 | return 0; | |
633 | } | |
e6a25dc9 | 634 | |
635 | /* Return true if insn1 and insn2 can never depend on one another because | |
636 | the conditions under which they are executed are mutually exclusive. */ | |
637 | bool | |
355af201 | 638 | sched_insns_conditions_mutex_p (const rtx_insn *insn1, const rtx_insn *insn2) |
e6a25dc9 | 639 | { |
640 | rtx cond1, cond2; | |
da7f8ea0 | 641 | bool rev1 = false, rev2 = false; |
e6a25dc9 | 642 | |
3072d30e | 643 | /* df doesn't handle conditional lifetimes entirely correctly; |
e6a25dc9 | 644 | calls mess up the conditional lifetimes. */ |
645 | if (!CALL_P (insn1) && !CALL_P (insn2)) | |
646 | { | |
e1ab7874 | 647 | cond1 = sched_get_condition_with_rev (insn1, &rev1); |
648 | cond2 = sched_get_condition_with_rev (insn2, &rev2); | |
e6a25dc9 | 649 | if (cond1 && cond2 |
e1ab7874 | 650 | && conditions_mutex_p (cond1, cond2, rev1, rev2) |
e6a25dc9 | 651 | /* Make sure first instruction doesn't affect condition of second |
652 | instruction if switched. */ | |
653 | && !modified_in_p (cond1, insn2) | |
654 | /* Make sure second instruction doesn't affect condition of first | |
655 | instruction if switched. */ | |
656 | && !modified_in_p (cond2, insn1)) | |
657 | return true; | |
658 | } | |
659 | return false; | |
660 | } | |
4164e76b | 661 | \f |
4d64d9a4 | 662 | |
86265ed0 | 663 | /* Return true if INSN can potentially be speculated with type DS. */ |
664 | bool | |
355af201 | 665 | sched_insn_is_legitimate_for_speculation_p (const rtx_insn *insn, ds_t ds) |
86265ed0 | 666 | { |
667 | if (HAS_INTERNAL_DEP (insn)) | |
668 | return false; | |
669 | ||
670 | if (!NONJUMP_INSN_P (insn)) | |
671 | return false; | |
672 | ||
673 | if (SCHED_GROUP_P (insn)) | |
674 | return false; | |
675 | ||
355af201 | 676 | if (IS_SPECULATION_CHECK_P (CONST_CAST_RTX_INSN (insn))) |
86265ed0 | 677 | return false; |
678 | ||
679 | if (side_effects_p (PATTERN (insn))) | |
680 | return false; | |
681 | ||
682 | if (ds & BE_IN_SPEC) | |
683 | /* The following instructions, which depend on a speculatively scheduled | |
684 | instruction, cannot be speculatively scheduled along. */ | |
685 | { | |
a67e70de | 686 | if (may_trap_or_fault_p (PATTERN (insn))) |
687 | /* If instruction might fault, it cannot be speculatively scheduled. | |
86265ed0 | 688 | For control speculation it's obvious why and for data speculation |
689 | it's because the insn might get wrong input if speculation | |
690 | wasn't successful. */ | |
691 | return false; | |
692 | ||
693 | if ((ds & BE_IN_DATA) | |
e1ab7874 | 694 | && sched_has_condition_p (insn)) |
86265ed0 | 695 | /* If this is a predicated instruction, then it cannot be |
696 | speculatively scheduled. See PR35659. */ | |
697 | return false; | |
698 | } | |
699 | ||
700 | return true; | |
701 | } | |
702 | ||
93f6b030 | 703 | /* Initialize LIST_PTR to point to one of the lists present in TYPES_PTR, |
704 | initialize RESOLVED_P_PTR with true if that list consists of resolved deps, | |
705 | and remove the type of returned [through LIST_PTR] list from TYPES_PTR. | |
706 | This function is used to switch sd_iterator to the next list. | |
707 | !!! For internal use only. Might consider moving it to sched-int.h. */ | |
708 | void | |
5493cb9a | 709 | sd_next_list (const_rtx insn, sd_list_types_def *types_ptr, |
93f6b030 | 710 | deps_list_t *list_ptr, bool *resolved_p_ptr) |
711 | { | |
712 | sd_list_types_def types = *types_ptr; | |
713 | ||
714 | if (types & SD_LIST_HARD_BACK) | |
715 | { | |
716 | *list_ptr = INSN_HARD_BACK_DEPS (insn); | |
717 | *resolved_p_ptr = false; | |
718 | *types_ptr = types & ~SD_LIST_HARD_BACK; | |
719 | } | |
720 | else if (types & SD_LIST_SPEC_BACK) | |
721 | { | |
722 | *list_ptr = INSN_SPEC_BACK_DEPS (insn); | |
723 | *resolved_p_ptr = false; | |
724 | *types_ptr = types & ~SD_LIST_SPEC_BACK; | |
725 | } | |
726 | else if (types & SD_LIST_FORW) | |
727 | { | |
728 | *list_ptr = INSN_FORW_DEPS (insn); | |
729 | *resolved_p_ptr = false; | |
730 | *types_ptr = types & ~SD_LIST_FORW; | |
731 | } | |
732 | else if (types & SD_LIST_RES_BACK) | |
733 | { | |
734 | *list_ptr = INSN_RESOLVED_BACK_DEPS (insn); | |
735 | *resolved_p_ptr = true; | |
736 | *types_ptr = types & ~SD_LIST_RES_BACK; | |
737 | } | |
738 | else if (types & SD_LIST_RES_FORW) | |
739 | { | |
740 | *list_ptr = INSN_RESOLVED_FORW_DEPS (insn); | |
741 | *resolved_p_ptr = true; | |
742 | *types_ptr = types & ~SD_LIST_RES_FORW; | |
743 | } | |
744 | else | |
745 | { | |
746 | *list_ptr = NULL; | |
747 | *resolved_p_ptr = false; | |
748 | *types_ptr = SD_LIST_NONE; | |
749 | } | |
750 | } | |
751 | ||
752 | /* Return the summary size of INSN's lists defined by LIST_TYPES. */ | |
753 | int | |
5493cb9a | 754 | sd_lists_size (const_rtx insn, sd_list_types_def list_types) |
93f6b030 | 755 | { |
756 | int size = 0; | |
757 | ||
758 | while (list_types != SD_LIST_NONE) | |
759 | { | |
760 | deps_list_t list; | |
761 | bool resolved_p; | |
762 | ||
763 | sd_next_list (insn, &list_types, &list, &resolved_p); | |
9845d120 | 764 | if (list) |
765 | size += DEPS_LIST_N_LINKS (list); | |
93f6b030 | 766 | } |
767 | ||
768 | return size; | |
769 | } | |
770 | ||
771 | /* Return true if INSN's lists defined by LIST_TYPES are all empty. */ | |
c971b445 | 772 | |
93f6b030 | 773 | bool |
5493cb9a | 774 | sd_lists_empty_p (const_rtx insn, sd_list_types_def list_types) |
93f6b030 | 775 | { |
c971b445 | 776 | while (list_types != SD_LIST_NONE) |
777 | { | |
778 | deps_list_t list; | |
779 | bool resolved_p; | |
780 | ||
781 | sd_next_list (insn, &list_types, &list, &resolved_p); | |
782 | if (!deps_list_empty_p (list)) | |
783 | return false; | |
784 | } | |
785 | ||
786 | return true; | |
93f6b030 | 787 | } |
788 | ||
789 | /* Initialize data for INSN. */ | |
790 | void | |
a1db0f0f | 791 | sd_init_insn (rtx_insn *insn) |
93f6b030 | 792 | { |
793 | INSN_HARD_BACK_DEPS (insn) = create_deps_list (); | |
794 | INSN_SPEC_BACK_DEPS (insn) = create_deps_list (); | |
795 | INSN_RESOLVED_BACK_DEPS (insn) = create_deps_list (); | |
796 | INSN_FORW_DEPS (insn) = create_deps_list (); | |
797 | INSN_RESOLVED_FORW_DEPS (insn) = create_deps_list (); | |
798 | ||
799 | /* ??? It would be nice to allocate dependency caches here. */ | |
800 | } | |
801 | ||
802 | /* Free data for INSN. */ | |
803 | void | |
a1db0f0f | 804 | sd_finish_insn (rtx_insn *insn) |
93f6b030 | 805 | { |
806 | /* ??? It would be nice to deallocate dependency caches here. */ | |
807 | ||
808 | free_deps_list (INSN_HARD_BACK_DEPS (insn)); | |
809 | INSN_HARD_BACK_DEPS (insn) = NULL; | |
810 | ||
811 | free_deps_list (INSN_SPEC_BACK_DEPS (insn)); | |
812 | INSN_SPEC_BACK_DEPS (insn) = NULL; | |
813 | ||
814 | free_deps_list (INSN_RESOLVED_BACK_DEPS (insn)); | |
815 | INSN_RESOLVED_BACK_DEPS (insn) = NULL; | |
816 | ||
817 | free_deps_list (INSN_FORW_DEPS (insn)); | |
818 | INSN_FORW_DEPS (insn) = NULL; | |
819 | ||
820 | free_deps_list (INSN_RESOLVED_FORW_DEPS (insn)); | |
821 | INSN_RESOLVED_FORW_DEPS (insn) = NULL; | |
822 | } | |
823 | ||
824 | /* Find a dependency between producer PRO and consumer CON. | |
825 | Search through resolved dependency lists if RESOLVED_P is true. | |
826 | If no such dependency is found return NULL, | |
becfaa62 | 827 | otherwise return the dependency and initialize SD_IT_PTR [if it is nonnull] |
93f6b030 | 828 | with an iterator pointing to it. */ |
829 | static dep_t | |
830 | sd_find_dep_between_no_cache (rtx pro, rtx con, bool resolved_p, | |
831 | sd_iterator_def *sd_it_ptr) | |
832 | { | |
833 | sd_list_types_def pro_list_type; | |
834 | sd_list_types_def con_list_type; | |
835 | sd_iterator_def sd_it; | |
836 | dep_t dep; | |
837 | bool found_p = false; | |
838 | ||
839 | if (resolved_p) | |
840 | { | |
841 | pro_list_type = SD_LIST_RES_FORW; | |
842 | con_list_type = SD_LIST_RES_BACK; | |
843 | } | |
844 | else | |
845 | { | |
846 | pro_list_type = SD_LIST_FORW; | |
847 | con_list_type = SD_LIST_BACK; | |
848 | } | |
849 | ||
850 | /* Walk through either back list of INSN or forw list of ELEM | |
851 | depending on which one is shorter. */ | |
852 | if (sd_lists_size (con, con_list_type) < sd_lists_size (pro, pro_list_type)) | |
853 | { | |
854 | /* Find the dep_link with producer PRO in consumer's back_deps. */ | |
855 | FOR_EACH_DEP (con, con_list_type, sd_it, dep) | |
856 | if (DEP_PRO (dep) == pro) | |
857 | { | |
858 | found_p = true; | |
859 | break; | |
860 | } | |
861 | } | |
862 | else | |
863 | { | |
864 | /* Find the dep_link with consumer CON in producer's forw_deps. */ | |
865 | FOR_EACH_DEP (pro, pro_list_type, sd_it, dep) | |
866 | if (DEP_CON (dep) == con) | |
867 | { | |
868 | found_p = true; | |
869 | break; | |
870 | } | |
871 | } | |
872 | ||
873 | if (found_p) | |
874 | { | |
875 | if (sd_it_ptr != NULL) | |
876 | *sd_it_ptr = sd_it; | |
877 | ||
878 | return dep; | |
879 | } | |
880 | ||
881 | return NULL; | |
882 | } | |
883 | ||
884 | /* Find a dependency between producer PRO and consumer CON. | |
885 | Use dependency [if available] to check if dependency is present at all. | |
886 | Search through resolved dependency lists if RESOLVED_P is true. | |
887 | If the dependency or NULL if none found. */ | |
888 | dep_t | |
889 | sd_find_dep_between (rtx pro, rtx con, bool resolved_p) | |
890 | { | |
891 | if (true_dependency_cache != NULL) | |
892 | /* Avoiding the list walk below can cut compile times dramatically | |
893 | for some code. */ | |
894 | { | |
895 | int elem_luid = INSN_LUID (pro); | |
896 | int insn_luid = INSN_LUID (con); | |
897 | ||
93f6b030 | 898 | if (!bitmap_bit_p (&true_dependency_cache[insn_luid], elem_luid) |
899 | && !bitmap_bit_p (&output_dependency_cache[insn_luid], elem_luid) | |
effd1640 | 900 | && !bitmap_bit_p (&anti_dependency_cache[insn_luid], elem_luid) |
901 | && !bitmap_bit_p (&control_dependency_cache[insn_luid], elem_luid)) | |
93f6b030 | 902 | return NULL; |
903 | } | |
904 | ||
905 | return sd_find_dep_between_no_cache (pro, con, resolved_p, NULL); | |
906 | } | |
907 | ||
908 | /* Add or update a dependence described by DEP. | |
909 | MEM1 and MEM2, if non-null, correspond to memory locations in case of | |
910 | data speculation. | |
911 | ||
912 | The function returns a value indicating if an old entry has been changed | |
913 | or a new entry has been added to insn's backward deps. | |
914 | ||
915 | This function merely checks if producer and consumer is the same insn | |
916 | and doesn't create a dep in this case. Actual manipulation of | |
917 | dependence data structures is performed in add_or_update_dep_1. */ | |
4d64d9a4 | 918 | static enum DEPS_ADJUST_RESULT |
93f6b030 | 919 | maybe_add_or_update_dep_1 (dep_t dep, bool resolved_p, rtx mem1, rtx mem2) |
6adce0fb | 920 | { |
9d8bf733 | 921 | rtx_insn *elem = DEP_PRO (dep); |
922 | rtx_insn *insn = DEP_CON (dep); | |
93f6b030 | 923 | |
4d64d9a4 | 924 | gcc_assert (INSN_P (insn) && INSN_P (elem)); |
6adce0fb | 925 | |
926 | /* Don't depend an insn on itself. */ | |
927 | if (insn == elem) | |
4d64d9a4 | 928 | { |
e1ab7874 | 929 | if (sched_deps_info->generate_spec_deps) |
4d64d9a4 | 930 | /* INSN has an internal dependence, which we can't overcome. */ |
931 | HAS_INTERNAL_DEP (insn) = 1; | |
93f6b030 | 932 | |
933 | return DEP_NODEP; | |
4d64d9a4 | 934 | } |
6adce0fb | 935 | |
93f6b030 | 936 | return add_or_update_dep_1 (dep, resolved_p, mem1, mem2); |
4d64d9a4 | 937 | } |
6adce0fb | 938 | |
93f6b030 | 939 | /* Ask dependency caches what needs to be done for dependence DEP. |
940 | Return DEP_CREATED if new dependence should be created and there is no | |
941 | need to try to find one searching the dependencies lists. | |
942 | Return DEP_PRESENT if there already is a dependence described by DEP and | |
943 | hence nothing is to be done. | |
944 | Return DEP_CHANGED if there already is a dependence, but it should be | |
945 | updated to incorporate additional information from DEP. */ | |
4d64d9a4 | 946 | static enum DEPS_ADJUST_RESULT |
93f6b030 | 947 | ask_dependency_caches (dep_t dep) |
4d64d9a4 | 948 | { |
93f6b030 | 949 | int elem_luid = INSN_LUID (DEP_PRO (dep)); |
950 | int insn_luid = INSN_LUID (DEP_CON (dep)); | |
4d64d9a4 | 951 | |
93f6b030 | 952 | gcc_assert (true_dependency_cache != NULL |
953 | && output_dependency_cache != NULL | |
effd1640 | 954 | && anti_dependency_cache != NULL |
955 | && control_dependency_cache != NULL); | |
4d64d9a4 | 956 | |
93f6b030 | 957 | if (!(current_sched_info->flags & USE_DEPS_LIST)) |
48e1416a | 958 | { |
93f6b030 | 959 | enum reg_note present_dep_type; |
960 | ||
961 | if (bitmap_bit_p (&true_dependency_cache[insn_luid], elem_luid)) | |
962 | present_dep_type = REG_DEP_TRUE; | |
963 | else if (bitmap_bit_p (&output_dependency_cache[insn_luid], elem_luid)) | |
964 | present_dep_type = REG_DEP_OUTPUT; | |
965 | else if (bitmap_bit_p (&anti_dependency_cache[insn_luid], elem_luid)) | |
966 | present_dep_type = REG_DEP_ANTI; | |
effd1640 | 967 | else if (bitmap_bit_p (&control_dependency_cache[insn_luid], elem_luid)) |
968 | present_dep_type = REG_DEP_CONTROL; | |
93f6b030 | 969 | else |
970 | /* There is no existing dep so it should be created. */ | |
971 | return DEP_CREATED; | |
972 | ||
973 | if ((int) DEP_TYPE (dep) >= (int) present_dep_type) | |
974 | /* DEP does not add anything to the existing dependence. */ | |
975 | return DEP_PRESENT; | |
976 | } | |
977 | else | |
48e1416a | 978 | { |
93f6b030 | 979 | ds_t present_dep_types = 0; |
48e1416a | 980 | |
93f6b030 | 981 | if (bitmap_bit_p (&true_dependency_cache[insn_luid], elem_luid)) |
982 | present_dep_types |= DEP_TRUE; | |
983 | if (bitmap_bit_p (&output_dependency_cache[insn_luid], elem_luid)) | |
984 | present_dep_types |= DEP_OUTPUT; | |
985 | if (bitmap_bit_p (&anti_dependency_cache[insn_luid], elem_luid)) | |
986 | present_dep_types |= DEP_ANTI; | |
effd1640 | 987 | if (bitmap_bit_p (&control_dependency_cache[insn_luid], elem_luid)) |
988 | present_dep_types |= DEP_CONTROL; | |
93f6b030 | 989 | |
990 | if (present_dep_types == 0) | |
991 | /* There is no existing dep so it should be created. */ | |
992 | return DEP_CREATED; | |
993 | ||
994 | if (!(current_sched_info->flags & DO_SPECULATION) | |
995 | || !bitmap_bit_p (&spec_dependency_cache[insn_luid], elem_luid)) | |
996 | { | |
997 | if ((present_dep_types | (DEP_STATUS (dep) & DEP_TYPES)) | |
998 | == present_dep_types) | |
999 | /* DEP does not add anything to the existing dependence. */ | |
1000 | return DEP_PRESENT; | |
1001 | } | |
1002 | else | |
1003 | { | |
1004 | /* Only true dependencies can be data speculative and | |
1005 | only anti dependencies can be control speculative. */ | |
1006 | gcc_assert ((present_dep_types & (DEP_TRUE | DEP_ANTI)) | |
1007 | == present_dep_types); | |
1008 | ||
1009 | /* if (DEP is SPECULATIVE) then | |
1010 | ..we should update DEP_STATUS | |
1011 | else | |
1012 | ..we should reset existing dep to non-speculative. */ | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | return DEP_CHANGED; | |
1017 | } | |
1018 | ||
1019 | /* Set dependency caches according to DEP. */ | |
1020 | static void | |
1021 | set_dependency_caches (dep_t dep) | |
1022 | { | |
1023 | int elem_luid = INSN_LUID (DEP_PRO (dep)); | |
1024 | int insn_luid = INSN_LUID (DEP_CON (dep)); | |
1025 | ||
1026 | if (!(current_sched_info->flags & USE_DEPS_LIST)) | |
1027 | { | |
1028 | switch (DEP_TYPE (dep)) | |
1029 | { | |
1030 | case REG_DEP_TRUE: | |
1031 | bitmap_set_bit (&true_dependency_cache[insn_luid], elem_luid); | |
1032 | break; | |
1033 | ||
1034 | case REG_DEP_OUTPUT: | |
1035 | bitmap_set_bit (&output_dependency_cache[insn_luid], elem_luid); | |
1036 | break; | |
1037 | ||
1038 | case REG_DEP_ANTI: | |
1039 | bitmap_set_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
1040 | break; | |
1041 | ||
effd1640 | 1042 | case REG_DEP_CONTROL: |
1043 | bitmap_set_bit (&control_dependency_cache[insn_luid], elem_luid); | |
1044 | break; | |
1045 | ||
93f6b030 | 1046 | default: |
1047 | gcc_unreachable (); | |
1048 | } | |
1049 | } | |
1050 | else | |
1051 | { | |
1052 | ds_t ds = DEP_STATUS (dep); | |
1053 | ||
1054 | if (ds & DEP_TRUE) | |
1055 | bitmap_set_bit (&true_dependency_cache[insn_luid], elem_luid); | |
1056 | if (ds & DEP_OUTPUT) | |
1057 | bitmap_set_bit (&output_dependency_cache[insn_luid], elem_luid); | |
1058 | if (ds & DEP_ANTI) | |
1059 | bitmap_set_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
effd1640 | 1060 | if (ds & DEP_CONTROL) |
1061 | bitmap_set_bit (&control_dependency_cache[insn_luid], elem_luid); | |
93f6b030 | 1062 | |
1063 | if (ds & SPECULATIVE) | |
1064 | { | |
1065 | gcc_assert (current_sched_info->flags & DO_SPECULATION); | |
1066 | bitmap_set_bit (&spec_dependency_cache[insn_luid], elem_luid); | |
1067 | } | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | /* Type of dependence DEP have changed from OLD_TYPE. Update dependency | |
1072 | caches accordingly. */ | |
1073 | static void | |
1074 | update_dependency_caches (dep_t dep, enum reg_note old_type) | |
1075 | { | |
1076 | int elem_luid = INSN_LUID (DEP_PRO (dep)); | |
1077 | int insn_luid = INSN_LUID (DEP_CON (dep)); | |
1078 | ||
1079 | /* Clear corresponding cache entry because type of the link | |
1080 | may have changed. Keep them if we use_deps_list. */ | |
1081 | if (!(current_sched_info->flags & USE_DEPS_LIST)) | |
1082 | { | |
1083 | switch (old_type) | |
1084 | { | |
1085 | case REG_DEP_OUTPUT: | |
1086 | bitmap_clear_bit (&output_dependency_cache[insn_luid], elem_luid); | |
1087 | break; | |
1088 | ||
1089 | case REG_DEP_ANTI: | |
1090 | bitmap_clear_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
1091 | break; | |
1092 | ||
effd1640 | 1093 | case REG_DEP_CONTROL: |
1094 | bitmap_clear_bit (&control_dependency_cache[insn_luid], elem_luid); | |
1095 | break; | |
1096 | ||
93f6b030 | 1097 | default: |
48e1416a | 1098 | gcc_unreachable (); |
93f6b030 | 1099 | } |
1100 | } | |
1101 | ||
1102 | set_dependency_caches (dep); | |
1103 | } | |
1104 | ||
1105 | /* Convert a dependence pointed to by SD_IT to be non-speculative. */ | |
1106 | static void | |
1107 | change_spec_dep_to_hard (sd_iterator_def sd_it) | |
1108 | { | |
1109 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
1110 | dep_link_t link = DEP_NODE_BACK (node); | |
1111 | dep_t dep = DEP_NODE_DEP (node); | |
9d8bf733 | 1112 | rtx_insn *elem = DEP_PRO (dep); |
1113 | rtx_insn *insn = DEP_CON (dep); | |
93f6b030 | 1114 | |
1115 | move_dep_link (link, INSN_SPEC_BACK_DEPS (insn), INSN_HARD_BACK_DEPS (insn)); | |
1116 | ||
1117 | DEP_STATUS (dep) &= ~SPECULATIVE; | |
6adce0fb | 1118 | |
6adce0fb | 1119 | if (true_dependency_cache != NULL) |
93f6b030 | 1120 | /* Clear the cache entry. */ |
1121 | bitmap_clear_bit (&spec_dependency_cache[INSN_LUID (insn)], | |
1122 | INSN_LUID (elem)); | |
1123 | } | |
93f6b030 | 1124 | |
1125 | /* Update DEP to incorporate information from NEW_DEP. | |
1126 | SD_IT points to DEP in case it should be moved to another list. | |
1127 | MEM1 and MEM2, if nonnull, correspond to memory locations in case if | |
1128 | data-speculative dependence should be updated. */ | |
1129 | static enum DEPS_ADJUST_RESULT | |
1130 | update_dep (dep_t dep, dep_t new_dep, | |
c407d287 | 1131 | sd_iterator_def sd_it ATTRIBUTE_UNUSED, |
1132 | rtx mem1 ATTRIBUTE_UNUSED, | |
1133 | rtx mem2 ATTRIBUTE_UNUSED) | |
93f6b030 | 1134 | { |
1135 | enum DEPS_ADJUST_RESULT res = DEP_PRESENT; | |
1136 | enum reg_note old_type = DEP_TYPE (dep); | |
2261c559 | 1137 | bool was_spec = dep_spec_p (dep); |
93f6b030 | 1138 | |
d452a169 | 1139 | DEP_NONREG (dep) |= DEP_NONREG (new_dep); |
1140 | DEP_MULTIPLE (dep) = 1; | |
1141 | ||
93f6b030 | 1142 | /* If this is a more restrictive type of dependence than the |
1143 | existing one, then change the existing dependence to this | |
1144 | type. */ | |
1145 | if ((int) DEP_TYPE (new_dep) < (int) old_type) | |
6adce0fb | 1146 | { |
93f6b030 | 1147 | DEP_TYPE (dep) = DEP_TYPE (new_dep); |
1148 | res = DEP_CHANGED; | |
1149 | } | |
1150 | ||
93f6b030 | 1151 | if (current_sched_info->flags & USE_DEPS_LIST) |
1152 | /* Update DEP_STATUS. */ | |
1153 | { | |
1154 | ds_t dep_status = DEP_STATUS (dep); | |
1155 | ds_t ds = DEP_STATUS (new_dep); | |
1156 | ds_t new_status = ds | dep_status; | |
1157 | ||
1158 | if (new_status & SPECULATIVE) | |
93f6b030 | 1159 | { |
2261c559 | 1160 | /* Either existing dep or a dep we're adding or both are |
1161 | speculative. */ | |
93f6b030 | 1162 | if (!(ds & SPECULATIVE) |
1163 | || !(dep_status & SPECULATIVE)) | |
1164 | /* The new dep can't be speculative. */ | |
2261c559 | 1165 | new_status &= ~SPECULATIVE; |
93f6b030 | 1166 | else |
4d64d9a4 | 1167 | { |
93f6b030 | 1168 | /* Both are speculative. Merge probabilities. */ |
1169 | if (mem1 != NULL) | |
4d64d9a4 | 1170 | { |
93f6b030 | 1171 | dw_t dw; |
1172 | ||
1173 | dw = estimate_dep_weak (mem1, mem2); | |
1174 | ds = set_dep_weak (ds, BEGIN_DATA, dw); | |
4d64d9a4 | 1175 | } |
48e1416a | 1176 | |
93f6b030 | 1177 | new_status = ds_merge (dep_status, ds); |
4d64d9a4 | 1178 | } |
93f6b030 | 1179 | } |
1180 | ||
1181 | ds = new_status; | |
1182 | ||
1183 | if (dep_status != ds) | |
1184 | { | |
1185 | DEP_STATUS (dep) = ds; | |
1186 | res = DEP_CHANGED; | |
1187 | } | |
1188 | } | |
1189 | ||
2261c559 | 1190 | if (was_spec && !dep_spec_p (dep)) |
1191 | /* The old dep was speculative, but now it isn't. */ | |
1192 | change_spec_dep_to_hard (sd_it); | |
1193 | ||
93f6b030 | 1194 | if (true_dependency_cache != NULL |
1195 | && res == DEP_CHANGED) | |
1196 | update_dependency_caches (dep, old_type); | |
93f6b030 | 1197 | |
1198 | return res; | |
1199 | } | |
1200 | ||
1201 | /* Add or update a dependence described by DEP. | |
1202 | MEM1 and MEM2, if non-null, correspond to memory locations in case of | |
1203 | data speculation. | |
1204 | ||
1205 | The function returns a value indicating if an old entry has been changed | |
1206 | or a new entry has been added to insn's backward deps or nothing has | |
1207 | been updated at all. */ | |
1208 | static enum DEPS_ADJUST_RESULT | |
1209 | add_or_update_dep_1 (dep_t new_dep, bool resolved_p, | |
1210 | rtx mem1 ATTRIBUTE_UNUSED, rtx mem2 ATTRIBUTE_UNUSED) | |
1211 | { | |
1212 | bool maybe_present_p = true; | |
1213 | bool present_p = false; | |
1214 | ||
1215 | gcc_assert (INSN_P (DEP_PRO (new_dep)) && INSN_P (DEP_CON (new_dep)) | |
1216 | && DEP_PRO (new_dep) != DEP_CON (new_dep)); | |
48e1416a | 1217 | |
382ecba7 | 1218 | if (flag_checking) |
1219 | check_dep (new_dep, mem1 != NULL); | |
93f6b030 | 1220 | |
1221 | if (true_dependency_cache != NULL) | |
1222 | { | |
1223 | switch (ask_dependency_caches (new_dep)) | |
1224 | { | |
1225 | case DEP_PRESENT: | |
c07ddae4 | 1226 | dep_t present_dep; |
1227 | sd_iterator_def sd_it; | |
1228 | ||
1229 | present_dep = sd_find_dep_between_no_cache (DEP_PRO (new_dep), | |
1230 | DEP_CON (new_dep), | |
1231 | resolved_p, &sd_it); | |
1232 | DEP_MULTIPLE (present_dep) = 1; | |
93f6b030 | 1233 | return DEP_PRESENT; |
1234 | ||
1235 | case DEP_CHANGED: | |
1236 | maybe_present_p = true; | |
1237 | present_p = true; | |
1238 | break; | |
1239 | ||
1240 | case DEP_CREATED: | |
1241 | maybe_present_p = false; | |
1242 | present_p = false; | |
1243 | break; | |
1244 | ||
1245 | default: | |
1246 | gcc_unreachable (); | |
1247 | break; | |
1248 | } | |
6adce0fb | 1249 | } |
6adce0fb | 1250 | |
1251 | /* Check that we don't already have this dependence. */ | |
4d64d9a4 | 1252 | if (maybe_present_p) |
1253 | { | |
93f6b030 | 1254 | dep_t present_dep; |
1255 | sd_iterator_def sd_it; | |
4d64d9a4 | 1256 | |
93f6b030 | 1257 | gcc_assert (true_dependency_cache == NULL || present_p); |
60b8c5b3 | 1258 | |
93f6b030 | 1259 | present_dep = sd_find_dep_between_no_cache (DEP_PRO (new_dep), |
1260 | DEP_CON (new_dep), | |
1261 | resolved_p, &sd_it); | |
40734805 | 1262 | |
93f6b030 | 1263 | if (present_dep != NULL) |
1264 | /* We found an existing dependency between ELEM and INSN. */ | |
1265 | return update_dep (present_dep, new_dep, sd_it, mem1, mem2); | |
1266 | else | |
1267 | /* We didn't find a dep, it shouldn't present in the cache. */ | |
1268 | gcc_assert (!present_p); | |
4d64d9a4 | 1269 | } |
6adce0fb | 1270 | |
4d64d9a4 | 1271 | /* Might want to check one level of transitivity to save conses. |
93f6b030 | 1272 | This check should be done in maybe_add_or_update_dep_1. |
1273 | Since we made it to add_or_update_dep_1, we must create | |
4d64d9a4 | 1274 | (or update) a link. */ |
6adce0fb | 1275 | |
93f6b030 | 1276 | if (mem1 != NULL_RTX) |
4d64d9a4 | 1277 | { |
e1ab7874 | 1278 | gcc_assert (sched_deps_info->generate_spec_deps); |
93f6b030 | 1279 | DEP_STATUS (new_dep) = set_dep_weak (DEP_STATUS (new_dep), BEGIN_DATA, |
1280 | estimate_dep_weak (mem1, mem2)); | |
4d64d9a4 | 1281 | } |
93f6b030 | 1282 | |
1283 | sd_add_dep (new_dep, resolved_p); | |
48e1416a | 1284 | |
4d64d9a4 | 1285 | return DEP_CREATED; |
1286 | } | |
6adce0fb | 1287 | |
93f6b030 | 1288 | /* Initialize BACK_LIST_PTR with consumer's backward list and |
1289 | FORW_LIST_PTR with producer's forward list. If RESOLVED_P is true | |
1290 | initialize with lists that hold resolved deps. */ | |
4d64d9a4 | 1291 | static void |
93f6b030 | 1292 | get_back_and_forw_lists (dep_t dep, bool resolved_p, |
1293 | deps_list_t *back_list_ptr, | |
1294 | deps_list_t *forw_list_ptr) | |
4d64d9a4 | 1295 | { |
9d8bf733 | 1296 | rtx_insn *con = DEP_CON (dep); |
9997bd27 | 1297 | |
93f6b030 | 1298 | if (!resolved_p) |
1299 | { | |
2261c559 | 1300 | if (dep_spec_p (dep)) |
93f6b030 | 1301 | *back_list_ptr = INSN_SPEC_BACK_DEPS (con); |
1302 | else | |
1303 | *back_list_ptr = INSN_HARD_BACK_DEPS (con); | |
4d64d9a4 | 1304 | |
93f6b030 | 1305 | *forw_list_ptr = INSN_FORW_DEPS (DEP_PRO (dep)); |
1306 | } | |
4d64d9a4 | 1307 | else |
93f6b030 | 1308 | { |
1309 | *back_list_ptr = INSN_RESOLVED_BACK_DEPS (con); | |
1310 | *forw_list_ptr = INSN_RESOLVED_FORW_DEPS (DEP_PRO (dep)); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | /* Add dependence described by DEP. | |
1315 | If RESOLVED_P is true treat the dependence as a resolved one. */ | |
1316 | void | |
1317 | sd_add_dep (dep_t dep, bool resolved_p) | |
1318 | { | |
1319 | dep_node_t n = create_dep_node (); | |
1320 | deps_list_t con_back_deps; | |
1321 | deps_list_t pro_forw_deps; | |
9d8bf733 | 1322 | rtx_insn *elem = DEP_PRO (dep); |
1323 | rtx_insn *insn = DEP_CON (dep); | |
93f6b030 | 1324 | |
1325 | gcc_assert (INSN_P (insn) && INSN_P (elem) && insn != elem); | |
1326 | ||
2261c559 | 1327 | if ((current_sched_info->flags & DO_SPECULATION) == 0 |
1328 | || !sched_insn_is_legitimate_for_speculation_p (insn, DEP_STATUS (dep))) | |
93f6b030 | 1329 | DEP_STATUS (dep) &= ~SPECULATIVE; |
1330 | ||
1331 | copy_dep (DEP_NODE_DEP (n), dep); | |
1332 | ||
1333 | get_back_and_forw_lists (dep, resolved_p, &con_back_deps, &pro_forw_deps); | |
9997bd27 | 1334 | |
93f6b030 | 1335 | add_to_deps_list (DEP_NODE_BACK (n), con_back_deps); |
9997bd27 | 1336 | |
382ecba7 | 1337 | if (flag_checking) |
1338 | check_dep (dep, false); | |
4d64d9a4 | 1339 | |
93f6b030 | 1340 | add_to_deps_list (DEP_NODE_FORW (n), pro_forw_deps); |
1341 | ||
6adce0fb | 1342 | /* If we are adding a dependency to INSN's LOG_LINKs, then note that |
1be87b72 | 1343 | in the bitmap caches of dependency information. */ |
6adce0fb | 1344 | if (true_dependency_cache != NULL) |
93f6b030 | 1345 | set_dependency_caches (dep); |
93f6b030 | 1346 | } |
1347 | ||
1348 | /* Add or update backward dependence between INSN and ELEM | |
1349 | with given type DEP_TYPE and dep_status DS. | |
1350 | This function is a convenience wrapper. */ | |
1351 | enum DEPS_ADJUST_RESULT | |
1352 | sd_add_or_update_dep (dep_t dep, bool resolved_p) | |
1353 | { | |
1354 | return add_or_update_dep_1 (dep, resolved_p, NULL_RTX, NULL_RTX); | |
1355 | } | |
1356 | ||
1357 | /* Resolved dependence pointed to by SD_IT. | |
1358 | SD_IT will advance to the next element. */ | |
1359 | void | |
1360 | sd_resolve_dep (sd_iterator_def sd_it) | |
1361 | { | |
1362 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
1363 | dep_t dep = DEP_NODE_DEP (node); | |
9d8bf733 | 1364 | rtx_insn *pro = DEP_PRO (dep); |
1365 | rtx_insn *con = DEP_CON (dep); | |
93f6b030 | 1366 | |
2261c559 | 1367 | if (dep_spec_p (dep)) |
93f6b030 | 1368 | move_dep_link (DEP_NODE_BACK (node), INSN_SPEC_BACK_DEPS (con), |
1369 | INSN_RESOLVED_BACK_DEPS (con)); | |
1370 | else | |
1371 | move_dep_link (DEP_NODE_BACK (node), INSN_HARD_BACK_DEPS (con), | |
1372 | INSN_RESOLVED_BACK_DEPS (con)); | |
1373 | ||
1374 | move_dep_link (DEP_NODE_FORW (node), INSN_FORW_DEPS (pro), | |
1375 | INSN_RESOLVED_FORW_DEPS (pro)); | |
1376 | } | |
1377 | ||
e2f4a6ff | 1378 | /* Perform the inverse operation of sd_resolve_dep. Restore the dependence |
1379 | pointed to by SD_IT to unresolved state. */ | |
1380 | void | |
1381 | sd_unresolve_dep (sd_iterator_def sd_it) | |
1382 | { | |
1383 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
1384 | dep_t dep = DEP_NODE_DEP (node); | |
9d8bf733 | 1385 | rtx_insn *pro = DEP_PRO (dep); |
1386 | rtx_insn *con = DEP_CON (dep); | |
e2f4a6ff | 1387 | |
effd1640 | 1388 | if (dep_spec_p (dep)) |
e2f4a6ff | 1389 | move_dep_link (DEP_NODE_BACK (node), INSN_RESOLVED_BACK_DEPS (con), |
1390 | INSN_SPEC_BACK_DEPS (con)); | |
1391 | else | |
1392 | move_dep_link (DEP_NODE_BACK (node), INSN_RESOLVED_BACK_DEPS (con), | |
1393 | INSN_HARD_BACK_DEPS (con)); | |
1394 | ||
1395 | move_dep_link (DEP_NODE_FORW (node), INSN_RESOLVED_FORW_DEPS (pro), | |
1396 | INSN_FORW_DEPS (pro)); | |
1397 | } | |
1398 | ||
93f6b030 | 1399 | /* Make TO depend on all the FROM's producers. |
1400 | If RESOLVED_P is true add dependencies to the resolved lists. */ | |
1401 | void | |
fc5ad70a | 1402 | sd_copy_back_deps (rtx_insn *to, rtx_insn *from, bool resolved_p) |
93f6b030 | 1403 | { |
1404 | sd_list_types_def list_type; | |
1405 | sd_iterator_def sd_it; | |
1406 | dep_t dep; | |
1407 | ||
1408 | list_type = resolved_p ? SD_LIST_RES_BACK : SD_LIST_BACK; | |
1409 | ||
1410 | FOR_EACH_DEP (from, list_type, sd_it, dep) | |
6adce0fb | 1411 | { |
93f6b030 | 1412 | dep_def _new_dep, *new_dep = &_new_dep; |
1413 | ||
1414 | copy_dep (new_dep, dep); | |
fc5ad70a | 1415 | DEP_CON (new_dep) = to; |
93f6b030 | 1416 | sd_add_dep (new_dep, resolved_p); |
6adce0fb | 1417 | } |
93f6b030 | 1418 | } |
1419 | ||
1420 | /* Remove a dependency referred to by SD_IT. | |
1421 | SD_IT will point to the next dependence after removal. */ | |
1422 | void | |
1423 | sd_delete_dep (sd_iterator_def sd_it) | |
1424 | { | |
1425 | dep_node_t n = DEP_LINK_NODE (*sd_it.linkp); | |
1426 | dep_t dep = DEP_NODE_DEP (n); | |
9d8bf733 | 1427 | rtx_insn *pro = DEP_PRO (dep); |
1428 | rtx_insn *con = DEP_CON (dep); | |
93f6b030 | 1429 | deps_list_t con_back_deps; |
1430 | deps_list_t pro_forw_deps; | |
1431 | ||
1432 | if (true_dependency_cache != NULL) | |
1433 | { | |
1434 | int elem_luid = INSN_LUID (pro); | |
1435 | int insn_luid = INSN_LUID (con); | |
1436 | ||
1437 | bitmap_clear_bit (&true_dependency_cache[insn_luid], elem_luid); | |
1438 | bitmap_clear_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
effd1640 | 1439 | bitmap_clear_bit (&control_dependency_cache[insn_luid], elem_luid); |
93f6b030 | 1440 | bitmap_clear_bit (&output_dependency_cache[insn_luid], elem_luid); |
1441 | ||
1442 | if (current_sched_info->flags & DO_SPECULATION) | |
1443 | bitmap_clear_bit (&spec_dependency_cache[insn_luid], elem_luid); | |
1444 | } | |
1445 | ||
1446 | get_back_and_forw_lists (dep, sd_it.resolved_p, | |
1447 | &con_back_deps, &pro_forw_deps); | |
1448 | ||
1449 | remove_from_deps_list (DEP_NODE_BACK (n), con_back_deps); | |
1450 | remove_from_deps_list (DEP_NODE_FORW (n), pro_forw_deps); | |
1451 | ||
1452 | delete_dep_node (n); | |
1453 | } | |
1454 | ||
1455 | /* Dump size of the lists. */ | |
1456 | #define DUMP_LISTS_SIZE (2) | |
1457 | ||
1458 | /* Dump dependencies of the lists. */ | |
1459 | #define DUMP_LISTS_DEPS (4) | |
1460 | ||
1461 | /* Dump all information about the lists. */ | |
1462 | #define DUMP_LISTS_ALL (DUMP_LISTS_SIZE | DUMP_LISTS_DEPS) | |
1463 | ||
1464 | /* Dump deps_lists of INSN specified by TYPES to DUMP. | |
1465 | FLAGS is a bit mask specifying what information about the lists needs | |
1466 | to be printed. | |
1467 | If FLAGS has the very first bit set, then dump all information about | |
1468 | the lists and propagate this bit into the callee dump functions. */ | |
1469 | static void | |
1470 | dump_lists (FILE *dump, rtx insn, sd_list_types_def types, int flags) | |
1471 | { | |
1472 | sd_iterator_def sd_it; | |
1473 | dep_t dep; | |
1474 | int all; | |
1475 | ||
1476 | all = (flags & 1); | |
1477 | ||
1478 | if (all) | |
1479 | flags |= DUMP_LISTS_ALL; | |
1480 | ||
1481 | fprintf (dump, "["); | |
1482 | ||
1483 | if (flags & DUMP_LISTS_SIZE) | |
1484 | fprintf (dump, "%d; ", sd_lists_size (insn, types)); | |
1485 | ||
1486 | if (flags & DUMP_LISTS_DEPS) | |
1487 | { | |
1488 | FOR_EACH_DEP (insn, types, sd_it, dep) | |
1489 | { | |
1490 | dump_dep (dump, dep, dump_dep_flags | all); | |
1491 | fprintf (dump, " "); | |
1492 | } | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | /* Dump all information about deps_lists of INSN specified by TYPES | |
1497 | to STDERR. */ | |
1498 | void | |
1499 | sd_debug_lists (rtx insn, sd_list_types_def types) | |
1500 | { | |
1501 | dump_lists (stderr, insn, types, 1); | |
1502 | fprintf (stderr, "\n"); | |
6adce0fb | 1503 | } |
1504 | ||
effd1640 | 1505 | /* A wrapper around add_dependence_1, to add a dependence of CON on |
1506 | PRO, with type DEP_TYPE. This function implements special handling | |
1507 | for REG_DEP_CONTROL dependencies. For these, we optionally promote | |
1508 | the type to REG_DEP_ANTI if we can determine that predication is | |
1509 | impossible; otherwise we add additional true dependencies on the | |
1510 | INSN_COND_DEPS list of the jump (which PRO must be). */ | |
1511 | void | |
b24ef467 | 1512 | add_dependence (rtx_insn *con, rtx_insn *pro, enum reg_note dep_type) |
effd1640 | 1513 | { |
754e815f | 1514 | if (dep_type == REG_DEP_CONTROL |
1515 | && !(current_sched_info->flags & DO_PREDICATION)) | |
1516 | dep_type = REG_DEP_ANTI; | |
1517 | ||
effd1640 | 1518 | /* A REG_DEP_CONTROL dependence may be eliminated through predication, |
1519 | so we must also make the insn dependent on the setter of the | |
1520 | condition. */ | |
1521 | if (dep_type == REG_DEP_CONTROL) | |
1522 | { | |
73e15687 | 1523 | rtx_insn *real_pro = pro; |
1524 | rtx_insn *other = real_insn_for_shadow (real_pro); | |
effd1640 | 1525 | rtx cond; |
1526 | ||
1527 | if (other != NULL_RTX) | |
1528 | real_pro = other; | |
1529 | cond = sched_get_reverse_condition_uncached (real_pro); | |
1530 | /* Verify that the insn does not use a different value in | |
1531 | the condition register than the one that was present at | |
1532 | the jump. */ | |
1533 | if (cond == NULL_RTX) | |
1534 | dep_type = REG_DEP_ANTI; | |
1535 | else if (INSN_CACHED_COND (real_pro) == const_true_rtx) | |
1536 | { | |
1537 | HARD_REG_SET uses; | |
1538 | CLEAR_HARD_REG_SET (uses); | |
1539 | note_uses (&PATTERN (con), record_hard_reg_uses, &uses); | |
1540 | if (TEST_HARD_REG_BIT (uses, REGNO (XEXP (cond, 0)))) | |
1541 | dep_type = REG_DEP_ANTI; | |
1542 | } | |
1543 | if (dep_type == REG_DEP_CONTROL) | |
1544 | { | |
1545 | if (sched_verbose >= 5) | |
1546 | fprintf (sched_dump, "making DEP_CONTROL for %d\n", | |
1547 | INSN_UID (real_pro)); | |
1548 | add_dependence_list (con, INSN_COND_DEPS (real_pro), 0, | |
d452a169 | 1549 | REG_DEP_TRUE, false); |
effd1640 | 1550 | } |
1551 | } | |
1552 | ||
1553 | add_dependence_1 (con, pro, dep_type); | |
1554 | } | |
1555 | ||
d452a169 | 1556 | /* A convenience wrapper to operate on an entire list. HARD should be |
1557 | true if DEP_NONREG should be set on newly created dependencies. */ | |
5deaeb50 | 1558 | |
1559 | static void | |
54267fdf | 1560 | add_dependence_list (rtx_insn *insn, rtx_insn_list *list, int uncond, |
1561 | enum reg_note dep_type, bool hard) | |
5deaeb50 | 1562 | { |
d452a169 | 1563 | mark_as_hard = hard; |
54267fdf | 1564 | for (; list; list = list->next ()) |
e6a25dc9 | 1565 | { |
54267fdf | 1566 | if (uncond || ! sched_insns_conditions_mutex_p (insn, list->insn ())) |
1567 | add_dependence (insn, list->insn (), dep_type); | |
e6a25dc9 | 1568 | } |
d452a169 | 1569 | mark_as_hard = false; |
5deaeb50 | 1570 | } |
1571 | ||
48e1416a | 1572 | /* Similar, but free *LISTP at the same time, when the context |
d452a169 | 1573 | is not readonly. HARD should be true if DEP_NONREG should be set on |
1574 | newly created dependencies. */ | |
5deaeb50 | 1575 | |
1576 | static void | |
54267fdf | 1577 | add_dependence_list_and_free (struct deps_desc *deps, rtx_insn *insn, |
1578 | rtx_insn_list **listp, | |
d452a169 | 1579 | int uncond, enum reg_note dep_type, bool hard) |
5deaeb50 | 1580 | { |
d452a169 | 1581 | add_dependence_list (insn, *listp, uncond, dep_type, hard); |
e1ab7874 | 1582 | |
3e0431fe | 1583 | /* We don't want to short-circuit dependencies involving debug |
1584 | insns, because they may cause actual dependencies to be | |
1585 | disregarded. */ | |
1586 | if (deps->readonly || DEBUG_INSN_P (insn)) | |
a7a503a5 | 1587 | return; |
e1ab7874 | 1588 | |
a7a503a5 | 1589 | free_INSN_LIST_list (listp); |
5deaeb50 | 1590 | } |
1591 | ||
9d75589a | 1592 | /* Remove all occurrences of INSN from LIST. Return the number of |
1593 | occurrences removed. */ | |
e1ab7874 | 1594 | |
1595 | static int | |
71ce7f59 | 1596 | remove_from_dependence_list (rtx_insn *insn, rtx_insn_list **listp) |
e1ab7874 | 1597 | { |
1598 | int removed = 0; | |
48e1416a | 1599 | |
e1ab7874 | 1600 | while (*listp) |
1601 | { | |
54267fdf | 1602 | if ((*listp)->insn () == insn) |
e1ab7874 | 1603 | { |
1604 | remove_free_INSN_LIST_node (listp); | |
1605 | removed++; | |
1606 | continue; | |
1607 | } | |
48e1416a | 1608 | |
54267fdf | 1609 | listp = (rtx_insn_list **)&XEXP (*listp, 1); |
e1ab7874 | 1610 | } |
48e1416a | 1611 | |
e1ab7874 | 1612 | return removed; |
1613 | } | |
1614 | ||
1615 | /* Same as above, but process two lists at once. */ | |
48e1416a | 1616 | static int |
71ce7f59 | 1617 | remove_from_both_dependence_lists (rtx_insn *insn, |
54267fdf | 1618 | rtx_insn_list **listp, |
8e56831f | 1619 | rtx_expr_list **exprp) |
e1ab7874 | 1620 | { |
1621 | int removed = 0; | |
48e1416a | 1622 | |
e1ab7874 | 1623 | while (*listp) |
1624 | { | |
1625 | if (XEXP (*listp, 0) == insn) | |
1626 | { | |
1627 | remove_free_INSN_LIST_node (listp); | |
1628 | remove_free_EXPR_LIST_node (exprp); | |
1629 | removed++; | |
1630 | continue; | |
1631 | } | |
48e1416a | 1632 | |
54267fdf | 1633 | listp = (rtx_insn_list **)&XEXP (*listp, 1); |
8e56831f | 1634 | exprp = (rtx_expr_list **)&XEXP (*exprp, 1); |
e1ab7874 | 1635 | } |
48e1416a | 1636 | |
e1ab7874 | 1637 | return removed; |
1638 | } | |
1639 | ||
828f2394 | 1640 | /* Clear all dependencies for an insn. */ |
6adce0fb | 1641 | static void |
71ce7f59 | 1642 | delete_all_dependences (rtx_insn *insn) |
6adce0fb | 1643 | { |
93f6b030 | 1644 | sd_iterator_def sd_it; |
1645 | dep_t dep; | |
6adce0fb | 1646 | |
93f6b030 | 1647 | /* The below cycle can be optimized to clear the caches and back_deps |
1648 | in one call but that would provoke duplication of code from | |
1649 | delete_dep (). */ | |
6adce0fb | 1650 | |
93f6b030 | 1651 | for (sd_it = sd_iterator_start (insn, SD_LIST_BACK); |
1652 | sd_iterator_cond (&sd_it, &dep);) | |
1653 | sd_delete_dep (sd_it); | |
828f2394 | 1654 | } |
1655 | ||
1656 | /* All insns in a scheduling group except the first should only have | |
1657 | dependencies on the previous insn in the group. So we find the | |
1658 | first instruction in the scheduling group by walking the dependence | |
1659 | chains backwards. Then we add the dependencies for the group to | |
1660 | the previous nonnote insn. */ | |
1661 | ||
1662 | static void | |
b24ef467 | 1663 | chain_to_prev_insn (rtx_insn *insn) |
828f2394 | 1664 | { |
93f6b030 | 1665 | sd_iterator_def sd_it; |
1666 | dep_t dep; | |
b24ef467 | 1667 | rtx_insn *prev_nonnote; |
828f2394 | 1668 | |
93f6b030 | 1669 | FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep) |
828f2394 | 1670 | { |
b24ef467 | 1671 | rtx_insn *i = insn; |
9d8bf733 | 1672 | rtx_insn *pro = DEP_PRO (dep); |
9997bd27 | 1673 | |
828f2394 | 1674 | do |
1675 | { | |
1676 | i = prev_nonnote_insn (i); | |
1677 | ||
9997bd27 | 1678 | if (pro == i) |
828f2394 | 1679 | goto next_link; |
9845d120 | 1680 | } while (SCHED_GROUP_P (i) || DEBUG_INSN_P (i)); |
9997bd27 | 1681 | |
1682 | if (! sched_insns_conditions_mutex_p (i, pro)) | |
93f6b030 | 1683 | add_dependence (i, pro, DEP_TYPE (dep)); |
828f2394 | 1684 | next_link:; |
1685 | } | |
1686 | ||
1687 | delete_all_dependences (insn); | |
1688 | ||
5b8537a8 | 1689 | prev_nonnote = prev_nonnote_nondebug_insn (insn); |
e6a25dc9 | 1690 | if (BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (prev_nonnote) |
1691 | && ! sched_insns_conditions_mutex_p (insn, prev_nonnote)) | |
1692 | add_dependence (insn, prev_nonnote, REG_DEP_ANTI); | |
6adce0fb | 1693 | } |
1694 | \f | |
1695 | /* Process an insn's memory dependencies. There are four kinds of | |
1696 | dependencies: | |
1697 | ||
1698 | (0) read dependence: read follows read | |
1699 | (1) true dependence: read follows write | |
4d64d9a4 | 1700 | (2) output dependence: write follows write |
1701 | (3) anti dependence: write follows read | |
6adce0fb | 1702 | |
1703 | We are careful to build only dependencies which actually exist, and | |
1704 | use transitivity to avoid building too many links. */ | |
1705 | ||
1706 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
1707 | The MEM is a memory reference contained within INSN, which we are saving | |
1708 | so that we can do memory aliasing on it. */ | |
1709 | ||
2749f808 | 1710 | static void |
68e419a1 | 1711 | add_insn_mem_dependence (struct deps_desc *deps, bool read_p, |
e722456b | 1712 | rtx_insn *insn, rtx mem) |
6adce0fb | 1713 | { |
54267fdf | 1714 | rtx_insn_list **insn_list; |
1715 | rtx_insn_list *insn_node; | |
8e56831f | 1716 | rtx_expr_list **mem_list; |
1717 | rtx_expr_list *mem_node; | |
6adce0fb | 1718 | |
e1ab7874 | 1719 | gcc_assert (!deps->readonly); |
c5947ab7 | 1720 | if (read_p) |
1721 | { | |
1722 | insn_list = &deps->pending_read_insns; | |
1723 | mem_list = &deps->pending_read_mems; | |
c971b445 | 1724 | if (!DEBUG_INSN_P (insn)) |
1725 | deps->pending_read_list_length++; | |
c5947ab7 | 1726 | } |
1727 | else | |
1728 | { | |
1729 | insn_list = &deps->pending_write_insns; | |
1730 | mem_list = &deps->pending_write_mems; | |
1731 | deps->pending_write_list_length++; | |
1732 | } | |
1733 | ||
54267fdf | 1734 | insn_node = alloc_INSN_LIST (insn, *insn_list); |
1735 | *insn_list = insn_node; | |
6adce0fb | 1736 | |
e1ab7874 | 1737 | if (sched_deps_info->use_cselib) |
503f2817 | 1738 | { |
1739 | mem = shallow_copy_rtx (mem); | |
2af89801 | 1740 | XEXP (mem, 0) = cselib_subst_to_values_from_insn (XEXP (mem, 0), |
1741 | GET_MODE (mem), insn); | |
503f2817 | 1742 | } |
54267fdf | 1743 | mem_node = alloc_EXPR_LIST (VOIDmode, canon_rtx (mem), *mem_list); |
1744 | *mem_list = mem_node; | |
6adce0fb | 1745 | } |
1746 | ||
1747 | /* Make a dependency between every memory reference on the pending lists | |
5deaeb50 | 1748 | and INSN, thus flushing the pending lists. FOR_READ is true if emitting |
1749 | dependencies for a read operation, similarly with FOR_WRITE. */ | |
6adce0fb | 1750 | |
1751 | static void | |
b24ef467 | 1752 | flush_pending_lists (struct deps_desc *deps, rtx_insn *insn, int for_read, |
60b8c5b3 | 1753 | int for_write) |
6adce0fb | 1754 | { |
5deaeb50 | 1755 | if (for_write) |
6adce0fb | 1756 | { |
48e1416a | 1757 | add_dependence_list_and_free (deps, insn, &deps->pending_read_insns, |
d452a169 | 1758 | 1, REG_DEP_ANTI, true); |
e1ab7874 | 1759 | if (!deps->readonly) |
1760 | { | |
1761 | free_EXPR_LIST_list (&deps->pending_read_mems); | |
1762 | deps->pending_read_list_length = 0; | |
1763 | } | |
6adce0fb | 1764 | } |
6adce0fb | 1765 | |
e1ab7874 | 1766 | add_dependence_list_and_free (deps, insn, &deps->pending_write_insns, 1, |
d452a169 | 1767 | for_read ? REG_DEP_ANTI : REG_DEP_OUTPUT, |
1768 | true); | |
6adce0fb | 1769 | |
48e1416a | 1770 | add_dependence_list_and_free (deps, insn, |
e1ab7874 | 1771 | &deps->last_pending_memory_flush, 1, |
d452a169 | 1772 | for_read ? REG_DEP_ANTI : REG_DEP_OUTPUT, |
1773 | true); | |
effd1640 | 1774 | |
1775 | add_dependence_list_and_free (deps, insn, &deps->pending_jump_insns, 1, | |
d452a169 | 1776 | REG_DEP_ANTI, true); |
effd1640 | 1777 | |
a7a503a5 | 1778 | if (DEBUG_INSN_P (insn)) |
1779 | { | |
1780 | if (for_write) | |
1781 | free_INSN_LIST_list (&deps->pending_read_insns); | |
1782 | free_INSN_LIST_list (&deps->pending_write_insns); | |
1783 | free_INSN_LIST_list (&deps->last_pending_memory_flush); | |
1784 | free_INSN_LIST_list (&deps->pending_jump_insns); | |
1785 | } | |
1786 | ||
e1ab7874 | 1787 | if (!deps->readonly) |
1788 | { | |
1789 | free_EXPR_LIST_list (&deps->pending_write_mems); | |
1790 | deps->pending_write_list_length = 0; | |
1791 | ||
1792 | deps->last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); | |
1793 | deps->pending_flush_length = 1; | |
1794 | } | |
d452a169 | 1795 | mark_as_hard = false; |
e1ab7874 | 1796 | } |
1797 | \f | |
1798 | /* Instruction which dependencies we are analyzing. */ | |
b24ef467 | 1799 | static rtx_insn *cur_insn = NULL; |
e1ab7874 | 1800 | |
1801 | /* Implement hooks for haifa scheduler. */ | |
1802 | ||
1803 | static void | |
2f3c9801 | 1804 | haifa_start_insn (rtx_insn *insn) |
e1ab7874 | 1805 | { |
1806 | gcc_assert (insn && !cur_insn); | |
1807 | ||
2f3c9801 | 1808 | cur_insn = insn; |
e1ab7874 | 1809 | } |
1810 | ||
1811 | static void | |
1812 | haifa_finish_insn (void) | |
1813 | { | |
1814 | cur_insn = NULL; | |
1815 | } | |
1816 | ||
1817 | void | |
1818 | haifa_note_reg_set (int regno) | |
1819 | { | |
1820 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
1821 | } | |
1822 | ||
1823 | void | |
1824 | haifa_note_reg_clobber (int regno) | |
1825 | { | |
1826 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
1827 | } | |
1828 | ||
1829 | void | |
1830 | haifa_note_reg_use (int regno) | |
1831 | { | |
1832 | SET_REGNO_REG_SET (reg_pending_uses, regno); | |
1833 | } | |
1834 | ||
1835 | static void | |
2f3c9801 | 1836 | haifa_note_mem_dep (rtx mem, rtx pending_mem, rtx_insn *pending_insn, ds_t ds) |
e1ab7874 | 1837 | { |
1838 | if (!(ds & SPECULATIVE)) | |
1839 | { | |
1840 | mem = NULL_RTX; | |
1841 | pending_mem = NULL_RTX; | |
1842 | } | |
1843 | else | |
1844 | gcc_assert (ds & BEGIN_DATA); | |
1845 | ||
1846 | { | |
1847 | dep_def _dep, *dep = &_dep; | |
48e1416a | 1848 | |
a7dcf969 | 1849 | init_dep_1 (dep, pending_insn, cur_insn, ds_to_dt (ds), |
2261c559 | 1850 | current_sched_info->flags & USE_DEPS_LIST ? ds : 0); |
d452a169 | 1851 | DEP_NONREG (dep) = 1; |
e1ab7874 | 1852 | maybe_add_or_update_dep_1 (dep, false, pending_mem, mem); |
1853 | } | |
1854 | ||
1855 | } | |
1856 | ||
1857 | static void | |
2f3c9801 | 1858 | haifa_note_dep (rtx_insn *elem, ds_t ds) |
e1ab7874 | 1859 | { |
1860 | dep_def _dep; | |
1861 | dep_t dep = &_dep; | |
1862 | ||
1863 | init_dep (dep, elem, cur_insn, ds_to_dt (ds)); | |
d452a169 | 1864 | if (mark_as_hard) |
1865 | DEP_NONREG (dep) = 1; | |
e1ab7874 | 1866 | maybe_add_or_update_dep_1 (dep, false, NULL_RTX, NULL_RTX); |
1867 | } | |
1868 | ||
1869 | static void | |
1870 | note_reg_use (int r) | |
1871 | { | |
1872 | if (sched_deps_info->note_reg_use) | |
1873 | sched_deps_info->note_reg_use (r); | |
1874 | } | |
1875 | ||
1876 | static void | |
1877 | note_reg_set (int r) | |
1878 | { | |
1879 | if (sched_deps_info->note_reg_set) | |
1880 | sched_deps_info->note_reg_set (r); | |
1881 | } | |
1882 | ||
1883 | static void | |
1884 | note_reg_clobber (int r) | |
1885 | { | |
1886 | if (sched_deps_info->note_reg_clobber) | |
1887 | sched_deps_info->note_reg_clobber (r); | |
1888 | } | |
1889 | ||
1890 | static void | |
2f3c9801 | 1891 | note_mem_dep (rtx m1, rtx m2, rtx_insn *e, ds_t ds) |
e1ab7874 | 1892 | { |
1893 | if (sched_deps_info->note_mem_dep) | |
1894 | sched_deps_info->note_mem_dep (m1, m2, e, ds); | |
1895 | } | |
1896 | ||
1897 | static void | |
b24ef467 | 1898 | note_dep (rtx_insn *e, ds_t ds) |
e1ab7874 | 1899 | { |
1900 | if (sched_deps_info->note_dep) | |
1901 | sched_deps_info->note_dep (e, ds); | |
1902 | } | |
1903 | ||
1904 | /* Return corresponding to DS reg_note. */ | |
1905 | enum reg_note | |
1906 | ds_to_dt (ds_t ds) | |
1907 | { | |
1908 | if (ds & DEP_TRUE) | |
1909 | return REG_DEP_TRUE; | |
1910 | else if (ds & DEP_OUTPUT) | |
1911 | return REG_DEP_OUTPUT; | |
effd1640 | 1912 | else if (ds & DEP_ANTI) |
1913 | return REG_DEP_ANTI; | |
e1ab7874 | 1914 | else |
1915 | { | |
effd1640 | 1916 | gcc_assert (ds & DEP_CONTROL); |
1917 | return REG_DEP_CONTROL; | |
e1ab7874 | 1918 | } |
6adce0fb | 1919 | } |
a7dcf969 | 1920 | |
1921 | \f | |
1922 | ||
1923 | /* Functions for computation of info needed for register pressure | |
1924 | sensitive insn scheduling. */ | |
1925 | ||
1926 | ||
1927 | /* Allocate and return reg_use_data structure for REGNO and INSN. */ | |
1928 | static struct reg_use_data * | |
73e15687 | 1929 | create_insn_reg_use (int regno, rtx_insn *insn) |
a7dcf969 | 1930 | { |
1931 | struct reg_use_data *use; | |
1932 | ||
1933 | use = (struct reg_use_data *) xmalloc (sizeof (struct reg_use_data)); | |
1934 | use->regno = regno; | |
1935 | use->insn = insn; | |
1936 | use->next_insn_use = INSN_REG_USE_LIST (insn); | |
1937 | INSN_REG_USE_LIST (insn) = use; | |
1938 | return use; | |
1939 | } | |
1940 | ||
57a8bf1b | 1941 | /* Allocate reg_set_data structure for REGNO and INSN. */ |
1942 | static void | |
a7dcf969 | 1943 | create_insn_reg_set (int regno, rtx insn) |
1944 | { | |
1945 | struct reg_set_data *set; | |
1946 | ||
1947 | set = (struct reg_set_data *) xmalloc (sizeof (struct reg_set_data)); | |
1948 | set->regno = regno; | |
1949 | set->insn = insn; | |
1950 | set->next_insn_set = INSN_REG_SET_LIST (insn); | |
1951 | INSN_REG_SET_LIST (insn) = set; | |
a7dcf969 | 1952 | } |
1953 | ||
1954 | /* Set up insn register uses for INSN and dependency context DEPS. */ | |
1955 | static void | |
73e15687 | 1956 | setup_insn_reg_uses (struct deps_desc *deps, rtx_insn *insn) |
a7dcf969 | 1957 | { |
1958 | unsigned i; | |
1959 | reg_set_iterator rsi; | |
a7dcf969 | 1960 | struct reg_use_data *use, *use2, *next; |
1961 | struct deps_reg *reg_last; | |
1962 | ||
1963 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_uses, 0, i, rsi) | |
1964 | { | |
1965 | if (i < FIRST_PSEUDO_REGISTER | |
1966 | && TEST_HARD_REG_BIT (ira_no_alloc_regs, i)) | |
1967 | continue; | |
1968 | ||
1969 | if (find_regno_note (insn, REG_DEAD, i) == NULL_RTX | |
1970 | && ! REGNO_REG_SET_P (reg_pending_sets, i) | |
1971 | && ! REGNO_REG_SET_P (reg_pending_clobbers, i)) | |
1972 | /* Ignore use which is not dying. */ | |
1973 | continue; | |
1974 | ||
1975 | use = create_insn_reg_use (i, insn); | |
1976 | use->next_regno_use = use; | |
1977 | reg_last = &deps->reg_last[i]; | |
48e1416a | 1978 | |
a7dcf969 | 1979 | /* Create the cycle list of uses. */ |
355af201 | 1980 | for (rtx_insn_list *list = reg_last->uses; list; list = list->next ()) |
a7dcf969 | 1981 | { |
355af201 | 1982 | use2 = create_insn_reg_use (i, list->insn ()); |
a7dcf969 | 1983 | next = use->next_regno_use; |
1984 | use->next_regno_use = use2; | |
1985 | use2->next_regno_use = next; | |
1986 | } | |
1987 | } | |
1988 | } | |
1989 | ||
1990 | /* Register pressure info for the currently processed insn. */ | |
1991 | static struct reg_pressure_data reg_pressure_info[N_REG_CLASSES]; | |
1992 | ||
1993 | /* Return TRUE if INSN has the use structure for REGNO. */ | |
1994 | static bool | |
1995 | insn_use_p (rtx insn, int regno) | |
1996 | { | |
1997 | struct reg_use_data *use; | |
1998 | ||
1999 | for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use) | |
2000 | if (use->regno == regno) | |
2001 | return true; | |
2002 | return false; | |
2003 | } | |
2004 | ||
2005 | /* Update the register pressure info after birth of pseudo register REGNO | |
2006 | in INSN. Arguments CLOBBER_P and UNUSED_P say correspondingly that | |
2007 | the register is in clobber or unused after the insn. */ | |
2008 | static void | |
2009 | mark_insn_pseudo_birth (rtx insn, int regno, bool clobber_p, bool unused_p) | |
2010 | { | |
2011 | int incr, new_incr; | |
2012 | enum reg_class cl; | |
2013 | ||
2014 | gcc_assert (regno >= FIRST_PSEUDO_REGISTER); | |
66d9a7b9 | 2015 | cl = sched_regno_pressure_class[regno]; |
a7dcf969 | 2016 | if (cl != NO_REGS) |
2017 | { | |
66d9a7b9 | 2018 | incr = ira_reg_class_max_nregs[cl][PSEUDO_REGNO_MODE (regno)]; |
a7dcf969 | 2019 | if (clobber_p) |
2020 | { | |
2021 | new_incr = reg_pressure_info[cl].clobber_increase + incr; | |
2022 | reg_pressure_info[cl].clobber_increase = new_incr; | |
2023 | } | |
2024 | else if (unused_p) | |
2025 | { | |
2026 | new_incr = reg_pressure_info[cl].unused_set_increase + incr; | |
2027 | reg_pressure_info[cl].unused_set_increase = new_incr; | |
2028 | } | |
2029 | else | |
2030 | { | |
2031 | new_incr = reg_pressure_info[cl].set_increase + incr; | |
2032 | reg_pressure_info[cl].set_increase = new_incr; | |
2033 | if (! insn_use_p (insn, regno)) | |
2034 | reg_pressure_info[cl].change += incr; | |
2035 | create_insn_reg_set (regno, insn); | |
2036 | } | |
2037 | gcc_assert (new_incr < (1 << INCREASE_BITS)); | |
2038 | } | |
2039 | } | |
2040 | ||
2041 | /* Like mark_insn_pseudo_regno_birth except that NREGS saying how many | |
2042 | hard registers involved in the birth. */ | |
2043 | static void | |
2044 | mark_insn_hard_regno_birth (rtx insn, int regno, int nregs, | |
2045 | bool clobber_p, bool unused_p) | |
2046 | { | |
2047 | enum reg_class cl; | |
2048 | int new_incr, last = regno + nregs; | |
48e1416a | 2049 | |
a7dcf969 | 2050 | while (regno < last) |
2051 | { | |
2052 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
2053 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
2054 | { | |
66d9a7b9 | 2055 | cl = sched_regno_pressure_class[regno]; |
a7dcf969 | 2056 | if (cl != NO_REGS) |
2057 | { | |
2058 | if (clobber_p) | |
2059 | { | |
2060 | new_incr = reg_pressure_info[cl].clobber_increase + 1; | |
2061 | reg_pressure_info[cl].clobber_increase = new_incr; | |
2062 | } | |
2063 | else if (unused_p) | |
2064 | { | |
2065 | new_incr = reg_pressure_info[cl].unused_set_increase + 1; | |
2066 | reg_pressure_info[cl].unused_set_increase = new_incr; | |
2067 | } | |
2068 | else | |
2069 | { | |
2070 | new_incr = reg_pressure_info[cl].set_increase + 1; | |
2071 | reg_pressure_info[cl].set_increase = new_incr; | |
2072 | if (! insn_use_p (insn, regno)) | |
2073 | reg_pressure_info[cl].change += 1; | |
2074 | create_insn_reg_set (regno, insn); | |
2075 | } | |
2076 | gcc_assert (new_incr < (1 << INCREASE_BITS)); | |
2077 | } | |
2078 | } | |
2079 | regno++; | |
2080 | } | |
2081 | } | |
2082 | ||
2083 | /* Update the register pressure info after birth of pseudo or hard | |
2084 | register REG in INSN. Arguments CLOBBER_P and UNUSED_P say | |
2085 | correspondingly that the register is in clobber or unused after the | |
2086 | insn. */ | |
2087 | static void | |
2088 | mark_insn_reg_birth (rtx insn, rtx reg, bool clobber_p, bool unused_p) | |
2089 | { | |
2090 | int regno; | |
2091 | ||
2092 | if (GET_CODE (reg) == SUBREG) | |
2093 | reg = SUBREG_REG (reg); | |
2094 | ||
2095 | if (! REG_P (reg)) | |
2096 | return; | |
2097 | ||
2098 | regno = REGNO (reg); | |
2099 | if (regno < FIRST_PSEUDO_REGISTER) | |
0933f1d9 | 2100 | mark_insn_hard_regno_birth (insn, regno, REG_NREGS (reg), |
a7dcf969 | 2101 | clobber_p, unused_p); |
2102 | else | |
2103 | mark_insn_pseudo_birth (insn, regno, clobber_p, unused_p); | |
2104 | } | |
2105 | ||
2106 | /* Update the register pressure info after death of pseudo register | |
2107 | REGNO. */ | |
2108 | static void | |
2109 | mark_pseudo_death (int regno) | |
2110 | { | |
2111 | int incr; | |
2112 | enum reg_class cl; | |
2113 | ||
2114 | gcc_assert (regno >= FIRST_PSEUDO_REGISTER); | |
66d9a7b9 | 2115 | cl = sched_regno_pressure_class[regno]; |
a7dcf969 | 2116 | if (cl != NO_REGS) |
2117 | { | |
66d9a7b9 | 2118 | incr = ira_reg_class_max_nregs[cl][PSEUDO_REGNO_MODE (regno)]; |
a7dcf969 | 2119 | reg_pressure_info[cl].change -= incr; |
2120 | } | |
2121 | } | |
2122 | ||
2123 | /* Like mark_pseudo_death except that NREGS saying how many hard | |
2124 | registers involved in the death. */ | |
2125 | static void | |
2126 | mark_hard_regno_death (int regno, int nregs) | |
2127 | { | |
2128 | enum reg_class cl; | |
2129 | int last = regno + nregs; | |
48e1416a | 2130 | |
a7dcf969 | 2131 | while (regno < last) |
2132 | { | |
2133 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
2134 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
2135 | { | |
66d9a7b9 | 2136 | cl = sched_regno_pressure_class[regno]; |
a7dcf969 | 2137 | if (cl != NO_REGS) |
2138 | reg_pressure_info[cl].change -= 1; | |
2139 | } | |
2140 | regno++; | |
2141 | } | |
2142 | } | |
2143 | ||
2144 | /* Update the register pressure info after death of pseudo or hard | |
2145 | register REG. */ | |
2146 | static void | |
2147 | mark_reg_death (rtx reg) | |
2148 | { | |
2149 | int regno; | |
2150 | ||
2151 | if (GET_CODE (reg) == SUBREG) | |
2152 | reg = SUBREG_REG (reg); | |
2153 | ||
2154 | if (! REG_P (reg)) | |
2155 | return; | |
2156 | ||
2157 | regno = REGNO (reg); | |
2158 | if (regno < FIRST_PSEUDO_REGISTER) | |
0933f1d9 | 2159 | mark_hard_regno_death (regno, REG_NREGS (reg)); |
a7dcf969 | 2160 | else |
2161 | mark_pseudo_death (regno); | |
2162 | } | |
2163 | ||
2164 | /* Process SETTER of REG. DATA is an insn containing the setter. */ | |
2165 | static void | |
2166 | mark_insn_reg_store (rtx reg, const_rtx setter, void *data) | |
2167 | { | |
2168 | if (setter != NULL_RTX && GET_CODE (setter) != SET) | |
2169 | return; | |
2170 | mark_insn_reg_birth | |
2171 | ((rtx) data, reg, false, | |
2172 | find_reg_note ((const_rtx) data, REG_UNUSED, reg) != NULL_RTX); | |
2173 | } | |
2174 | ||
2175 | /* Like mark_insn_reg_store except notice just CLOBBERs; ignore SETs. */ | |
2176 | static void | |
2177 | mark_insn_reg_clobber (rtx reg, const_rtx setter, void *data) | |
2178 | { | |
2179 | if (GET_CODE (setter) == CLOBBER) | |
2180 | mark_insn_reg_birth ((rtx) data, reg, true, false); | |
2181 | } | |
2182 | ||
2183 | /* Set up reg pressure info related to INSN. */ | |
c15d7785 | 2184 | void |
71ce7f59 | 2185 | init_insn_reg_pressure_info (rtx_insn *insn) |
a7dcf969 | 2186 | { |
2187 | int i, len; | |
2188 | enum reg_class cl; | |
2189 | static struct reg_pressure_data *pressure_info; | |
2190 | rtx link; | |
2191 | ||
b30b031c | 2192 | gcc_assert (sched_pressure != SCHED_PRESSURE_NONE); |
a7dcf969 | 2193 | |
2194 | if (! INSN_P (insn)) | |
2195 | return; | |
2196 | ||
66d9a7b9 | 2197 | for (i = 0; i < ira_pressure_classes_num; i++) |
a7dcf969 | 2198 | { |
66d9a7b9 | 2199 | cl = ira_pressure_classes[i]; |
a7dcf969 | 2200 | reg_pressure_info[cl].clobber_increase = 0; |
2201 | reg_pressure_info[cl].set_increase = 0; | |
2202 | reg_pressure_info[cl].unused_set_increase = 0; | |
2203 | reg_pressure_info[cl].change = 0; | |
2204 | } | |
48e1416a | 2205 | |
a7dcf969 | 2206 | note_stores (PATTERN (insn), mark_insn_reg_clobber, insn); |
48e1416a | 2207 | |
a7dcf969 | 2208 | note_stores (PATTERN (insn), mark_insn_reg_store, insn); |
48e1416a | 2209 | |
32aa77d9 | 2210 | if (AUTO_INC_DEC) |
2211 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2212 | if (REG_NOTE_KIND (link) == REG_INC) | |
2213 | mark_insn_reg_store (XEXP (link, 0), NULL_RTX, insn); | |
a7dcf969 | 2214 | |
2215 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2216 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
2217 | mark_reg_death (XEXP (link, 0)); | |
48e1416a | 2218 | |
66d9a7b9 | 2219 | len = sizeof (struct reg_pressure_data) * ira_pressure_classes_num; |
a7dcf969 | 2220 | pressure_info |
2221 | = INSN_REG_PRESSURE (insn) = (struct reg_pressure_data *) xmalloc (len); | |
b30b031c | 2222 | if (sched_pressure == SCHED_PRESSURE_WEIGHTED) |
2223 | INSN_MAX_REG_PRESSURE (insn) = (int *) xcalloc (ira_pressure_classes_num | |
2224 | * sizeof (int), 1); | |
66d9a7b9 | 2225 | for (i = 0; i < ira_pressure_classes_num; i++) |
a7dcf969 | 2226 | { |
66d9a7b9 | 2227 | cl = ira_pressure_classes[i]; |
a7dcf969 | 2228 | pressure_info[i].clobber_increase |
2229 | = reg_pressure_info[cl].clobber_increase; | |
2230 | pressure_info[i].set_increase = reg_pressure_info[cl].set_increase; | |
2231 | pressure_info[i].unused_set_increase | |
2232 | = reg_pressure_info[cl].unused_set_increase; | |
2233 | pressure_info[i].change = reg_pressure_info[cl].change; | |
2234 | } | |
2235 | } | |
2236 | ||
2237 | ||
6adce0fb | 2238 | \f |
e1ab7874 | 2239 | |
2240 | /* Internal variable for sched_analyze_[12] () functions. | |
2241 | If it is nonzero, this means that sched_analyze_[12] looks | |
2242 | at the most toplevel SET. */ | |
2243 | static bool can_start_lhs_rhs_p; | |
2244 | ||
48e1416a | 2245 | /* Extend reg info for the deps context DEPS given that |
e1ab7874 | 2246 | we have just generated a register numbered REGNO. */ |
2247 | static void | |
68e419a1 | 2248 | extend_deps_reg_info (struct deps_desc *deps, int regno) |
e1ab7874 | 2249 | { |
2250 | int max_regno = regno + 1; | |
2251 | ||
2252 | gcc_assert (!reload_completed); | |
2253 | ||
2254 | /* In a readonly context, it would not hurt to extend info, | |
2255 | but it should not be needed. */ | |
2256 | if (reload_completed && deps->readonly) | |
2257 | { | |
2258 | deps->max_reg = max_regno; | |
2259 | return; | |
2260 | } | |
2261 | ||
2262 | if (max_regno > deps->max_reg) | |
2263 | { | |
48e1416a | 2264 | deps->reg_last = XRESIZEVEC (struct deps_reg, deps->reg_last, |
e1ab7874 | 2265 | max_regno); |
2266 | memset (&deps->reg_last[deps->max_reg], | |
48e1416a | 2267 | 0, (max_regno - deps->max_reg) |
e1ab7874 | 2268 | * sizeof (struct deps_reg)); |
2269 | deps->max_reg = max_regno; | |
2270 | } | |
2271 | } | |
2272 | ||
2273 | /* Extends REG_INFO_P if needed. */ | |
2274 | void | |
2275 | maybe_extend_reg_info_p (void) | |
2276 | { | |
2277 | /* Extend REG_INFO_P, if needed. */ | |
2278 | if ((unsigned int)max_regno - 1 >= reg_info_p_size) | |
2279 | { | |
2280 | size_t new_reg_info_p_size = max_regno + 128; | |
2281 | ||
2282 | gcc_assert (!reload_completed && sel_sched_p ()); | |
2283 | ||
2284 | reg_info_p = (struct reg_info_t *) xrecalloc (reg_info_p, | |
2285 | new_reg_info_p_size, | |
2286 | reg_info_p_size, | |
2287 | sizeof (*reg_info_p)); | |
2288 | reg_info_p_size = new_reg_info_p_size; | |
2289 | } | |
2290 | } | |
2291 | ||
8ad6f16d | 2292 | /* Analyze a single reference to register (reg:MODE REGNO) in INSN. |
2293 | The type of the reference is specified by REF and can be SET, | |
2294 | CLOBBER, PRE_DEC, POST_DEC, PRE_INC, POST_INC or USE. */ | |
2295 | ||
2296 | static void | |
3754d046 | 2297 | sched_analyze_reg (struct deps_desc *deps, int regno, machine_mode mode, |
b24ef467 | 2298 | enum rtx_code ref, rtx_insn *insn) |
8ad6f16d | 2299 | { |
e1ab7874 | 2300 | /* We could emit new pseudos in renaming. Extend the reg structures. */ |
2301 | if (!reload_completed && sel_sched_p () | |
2302 | && (regno >= max_reg_num () - 1 || regno >= deps->max_reg)) | |
2303 | extend_deps_reg_info (deps, regno); | |
2304 | ||
2305 | maybe_extend_reg_info_p (); | |
2306 | ||
8ad6f16d | 2307 | /* A hard reg in a wide mode may really be multiple registers. |
2308 | If so, mark all of them just like the first. */ | |
2309 | if (regno < FIRST_PSEUDO_REGISTER) | |
2310 | { | |
2311 | int i = hard_regno_nregs[regno][mode]; | |
2312 | if (ref == SET) | |
2313 | { | |
2314 | while (--i >= 0) | |
e1ab7874 | 2315 | note_reg_set (regno + i); |
8ad6f16d | 2316 | } |
2317 | else if (ref == USE) | |
2318 | { | |
2319 | while (--i >= 0) | |
e1ab7874 | 2320 | note_reg_use (regno + i); |
8ad6f16d | 2321 | } |
2322 | else | |
2323 | { | |
2324 | while (--i >= 0) | |
e1ab7874 | 2325 | note_reg_clobber (regno + i); |
8ad6f16d | 2326 | } |
2327 | } | |
2328 | ||
2329 | /* ??? Reload sometimes emits USEs and CLOBBERs of pseudos that | |
2330 | it does not reload. Ignore these as they have served their | |
2331 | purpose already. */ | |
2332 | else if (regno >= deps->max_reg) | |
2333 | { | |
2334 | enum rtx_code code = GET_CODE (PATTERN (insn)); | |
2335 | gcc_assert (code == USE || code == CLOBBER); | |
2336 | } | |
2337 | ||
2338 | else | |
2339 | { | |
2340 | if (ref == SET) | |
e1ab7874 | 2341 | note_reg_set (regno); |
8ad6f16d | 2342 | else if (ref == USE) |
e1ab7874 | 2343 | note_reg_use (regno); |
8ad6f16d | 2344 | else |
e1ab7874 | 2345 | note_reg_clobber (regno); |
8ad6f16d | 2346 | |
2347 | /* Pseudos that are REG_EQUIV to something may be replaced | |
2348 | by that during reloading. We need only add dependencies for | |
2349 | the address in the REG_EQUIV note. */ | |
2350 | if (!reload_completed && get_reg_known_equiv_p (regno)) | |
2351 | { | |
2352 | rtx t = get_reg_known_value (regno); | |
2353 | if (MEM_P (t)) | |
2354 | sched_analyze_2 (deps, XEXP (t, 0), insn); | |
2355 | } | |
2356 | ||
2357 | /* Don't let it cross a call after scheduling if it doesn't | |
2358 | already cross one. */ | |
2359 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
2360 | { | |
9845d120 | 2361 | if (!deps->readonly && ref == USE && !DEBUG_INSN_P (insn)) |
8ad6f16d | 2362 | deps->sched_before_next_call |
2363 | = alloc_INSN_LIST (insn, deps->sched_before_next_call); | |
2364 | else | |
2365 | add_dependence_list (insn, deps->last_function_call, 1, | |
d452a169 | 2366 | REG_DEP_ANTI, false); |
8ad6f16d | 2367 | } |
2368 | } | |
2369 | } | |
2370 | ||
6adce0fb | 2371 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
2372 | rtx, X, creating all dependencies generated by the write to the | |
2373 | destination of X, and reads of everything mentioned. */ | |
2374 | ||
2375 | static void | |
b24ef467 | 2376 | sched_analyze_1 (struct deps_desc *deps, rtx x, rtx_insn *insn) |
6adce0fb | 2377 | { |
19cb6b50 | 2378 | rtx dest = XEXP (x, 0); |
6adce0fb | 2379 | enum rtx_code code = GET_CODE (x); |
e1ab7874 | 2380 | bool cslr_p = can_start_lhs_rhs_p; |
6adce0fb | 2381 | |
e1ab7874 | 2382 | can_start_lhs_rhs_p = false; |
2383 | ||
2384 | gcc_assert (dest); | |
6adce0fb | 2385 | if (dest == 0) |
2386 | return; | |
2387 | ||
e1ab7874 | 2388 | if (cslr_p && sched_deps_info->start_lhs) |
2389 | sched_deps_info->start_lhs (dest); | |
2390 | ||
4b303227 | 2391 | if (GET_CODE (dest) == PARALLEL) |
6adce0fb | 2392 | { |
19cb6b50 | 2393 | int i; |
216b2683 | 2394 | |
6adce0fb | 2395 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) |
4b303227 | 2396 | if (XEXP (XVECEXP (dest, 0, i), 0) != 0) |
2397 | sched_analyze_1 (deps, | |
2398 | gen_rtx_CLOBBER (VOIDmode, | |
2399 | XEXP (XVECEXP (dest, 0, i), 0)), | |
2400 | insn); | |
216b2683 | 2401 | |
e1ab7874 | 2402 | if (cslr_p && sched_deps_info->finish_lhs) |
2403 | sched_deps_info->finish_lhs (); | |
2404 | ||
2405 | if (code == SET) | |
2406 | { | |
2407 | can_start_lhs_rhs_p = cslr_p; | |
2408 | ||
2409 | sched_analyze_2 (deps, SET_SRC (x), insn); | |
2410 | ||
2411 | can_start_lhs_rhs_p = false; | |
2412 | } | |
2413 | ||
6adce0fb | 2414 | return; |
2415 | } | |
2416 | ||
2417 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG | |
476d094d | 2418 | || GET_CODE (dest) == ZERO_EXTRACT) |
6adce0fb | 2419 | { |
b69139c7 | 2420 | if (GET_CODE (dest) == STRICT_LOW_PART |
2421 | || GET_CODE (dest) == ZERO_EXTRACT | |
5a462df3 | 2422 | || read_modify_subreg_p (dest)) |
b69139c7 | 2423 | { |
60b8c5b3 | 2424 | /* These both read and modify the result. We must handle |
b69139c7 | 2425 | them as writes to get proper dependencies for following |
2426 | instructions. We must handle them as reads to get proper | |
2427 | dependencies from this to previous instructions. | |
6473f3f4 | 2428 | Thus we need to call sched_analyze_2. */ |
b69139c7 | 2429 | |
60b8c5b3 | 2430 | sched_analyze_2 (deps, XEXP (dest, 0), insn); |
b69139c7 | 2431 | } |
476d094d | 2432 | if (GET_CODE (dest) == ZERO_EXTRACT) |
6adce0fb | 2433 | { |
2434 | /* The second and third arguments are values read by this insn. */ | |
2435 | sched_analyze_2 (deps, XEXP (dest, 1), insn); | |
2436 | sched_analyze_2 (deps, XEXP (dest, 2), insn); | |
2437 | } | |
2438 | dest = XEXP (dest, 0); | |
2439 | } | |
2440 | ||
8ad4c111 | 2441 | if (REG_P (dest)) |
6adce0fb | 2442 | { |
8ad6f16d | 2443 | int regno = REGNO (dest); |
3754d046 | 2444 | machine_mode mode = GET_MODE (dest); |
8ad6f16d | 2445 | |
2446 | sched_analyze_reg (deps, regno, mode, code, insn); | |
6adce0fb | 2447 | |
1541bfd5 | 2448 | #ifdef STACK_REGS |
2449 | /* Treat all writes to a stack register as modifying the TOS. */ | |
2450 | if (regno >= FIRST_STACK_REG && regno <= LAST_STACK_REG) | |
2451 | { | |
8ad6f16d | 2452 | /* Avoid analyzing the same register twice. */ |
2453 | if (regno != FIRST_STACK_REG) | |
2454 | sched_analyze_reg (deps, FIRST_STACK_REG, mode, code, insn); | |
a7dcf969 | 2455 | |
d82cf2b2 | 2456 | add_to_hard_reg_set (&implicit_reg_pending_uses, mode, |
2457 | FIRST_STACK_REG); | |
1541bfd5 | 2458 | } |
2459 | #endif | |
6adce0fb | 2460 | } |
e16ceb8e | 2461 | else if (MEM_P (dest)) |
6adce0fb | 2462 | { |
2463 | /* Writing memory. */ | |
503f2817 | 2464 | rtx t = dest; |
2465 | ||
e1ab7874 | 2466 | if (sched_deps_info->use_cselib) |
503f2817 | 2467 | { |
3754d046 | 2468 | machine_mode address_mode = get_address_mode (dest); |
98155838 | 2469 | |
503f2817 | 2470 | t = shallow_copy_rtx (dest); |
1f864115 | 2471 | cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, |
2472 | GET_MODE (t), insn); | |
2af89801 | 2473 | XEXP (t, 0) |
2474 | = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), | |
2475 | insn); | |
503f2817 | 2476 | } |
faa80ce8 | 2477 | t = canon_rtx (t); |
6adce0fb | 2478 | |
e1ab7874 | 2479 | /* Pending lists can't get larger with a readonly context. */ |
2480 | if (!deps->readonly | |
2481 | && ((deps->pending_read_list_length + deps->pending_write_list_length) | |
1deb811a | 2482 | >= MAX_PENDING_LIST_LENGTH)) |
6adce0fb | 2483 | { |
2484 | /* Flush all pending reads and writes to prevent the pending lists | |
2485 | from getting any larger. Insn scheduling runs too slowly when | |
85de291e | 2486 | these lists get long. When compiling GCC with itself, |
6adce0fb | 2487 | this flush occurs 8 times for sparc, and 10 times for m88k using |
85de291e | 2488 | the default value of 32. */ |
5deaeb50 | 2489 | flush_pending_lists (deps, insn, false, true); |
6adce0fb | 2490 | } |
2491 | else | |
2492 | { | |
355af201 | 2493 | rtx_insn_list *pending; |
2494 | rtx_expr_list *pending_mem; | |
6adce0fb | 2495 | |
2496 | pending = deps->pending_read_insns; | |
2497 | pending_mem = deps->pending_read_mems; | |
2498 | while (pending) | |
2499 | { | |
355af201 | 2500 | if (anti_dependence (pending_mem->element (), t) |
2501 | && ! sched_insns_conditions_mutex_p (insn, pending->insn ())) | |
2502 | note_mem_dep (t, pending_mem->element (), pending->insn (), | |
e1ab7874 | 2503 | DEP_ANTI); |
6adce0fb | 2504 | |
355af201 | 2505 | pending = pending->next (); |
2506 | pending_mem = pending_mem->next (); | |
6adce0fb | 2507 | } |
2508 | ||
2509 | pending = deps->pending_write_insns; | |
2510 | pending_mem = deps->pending_write_mems; | |
2511 | while (pending) | |
2512 | { | |
355af201 | 2513 | if (output_dependence (pending_mem->element (), t) |
2514 | && ! sched_insns_conditions_mutex_p (insn, pending->insn ())) | |
2515 | note_mem_dep (t, pending_mem->element (), | |
2516 | pending->insn (), | |
e1ab7874 | 2517 | DEP_OUTPUT); |
6adce0fb | 2518 | |
355af201 | 2519 | pending = pending->next (); |
2520 | pending_mem = pending_mem-> next (); | |
6adce0fb | 2521 | } |
2522 | ||
e228dd5d | 2523 | add_dependence_list (insn, deps->last_pending_memory_flush, 1, |
d452a169 | 2524 | REG_DEP_ANTI, true); |
effd1640 | 2525 | add_dependence_list (insn, deps->pending_jump_insns, 1, |
d452a169 | 2526 | REG_DEP_CONTROL, true); |
6adce0fb | 2527 | |
e1ab7874 | 2528 | if (!deps->readonly) |
2529 | add_insn_mem_dependence (deps, false, insn, dest); | |
6adce0fb | 2530 | } |
2531 | sched_analyze_2 (deps, XEXP (dest, 0), insn); | |
2532 | } | |
2533 | ||
e1ab7874 | 2534 | if (cslr_p && sched_deps_info->finish_lhs) |
2535 | sched_deps_info->finish_lhs (); | |
2536 | ||
6adce0fb | 2537 | /* Analyze reads. */ |
2538 | if (GET_CODE (x) == SET) | |
e1ab7874 | 2539 | { |
2540 | can_start_lhs_rhs_p = cslr_p; | |
2541 | ||
2542 | sched_analyze_2 (deps, SET_SRC (x), insn); | |
2543 | ||
2544 | can_start_lhs_rhs_p = false; | |
2545 | } | |
6adce0fb | 2546 | } |
2547 | ||
2548 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
6adce0fb | 2549 | static void |
b24ef467 | 2550 | sched_analyze_2 (struct deps_desc *deps, rtx x, rtx_insn *insn) |
6adce0fb | 2551 | { |
19cb6b50 | 2552 | int i; |
2553 | int j; | |
2554 | enum rtx_code code; | |
2555 | const char *fmt; | |
e1ab7874 | 2556 | bool cslr_p = can_start_lhs_rhs_p; |
2557 | ||
2558 | can_start_lhs_rhs_p = false; | |
6adce0fb | 2559 | |
e1ab7874 | 2560 | gcc_assert (x); |
6adce0fb | 2561 | if (x == 0) |
2562 | return; | |
2563 | ||
e1ab7874 | 2564 | if (cslr_p && sched_deps_info->start_rhs) |
2565 | sched_deps_info->start_rhs (x); | |
2566 | ||
6adce0fb | 2567 | code = GET_CODE (x); |
2568 | ||
2569 | switch (code) | |
2570 | { | |
0349edce | 2571 | CASE_CONST_ANY: |
6adce0fb | 2572 | case SYMBOL_REF: |
2573 | case CONST: | |
2574 | case LABEL_REF: | |
8990536a | 2575 | /* Ignore constants. */ |
e1ab7874 | 2576 | if (cslr_p && sched_deps_info->finish_rhs) |
2577 | sched_deps_info->finish_rhs (); | |
2578 | ||
6adce0fb | 2579 | return; |
2580 | ||
6adce0fb | 2581 | case CC0: |
693c9f42 | 2582 | if (!HAVE_cc0) |
2583 | gcc_unreachable (); | |
2584 | ||
6adce0fb | 2585 | /* User of CC0 depends on immediately preceding insn. */ |
828f2394 | 2586 | SCHED_GROUP_P (insn) = 1; |
f61f0d0c | 2587 | /* Don't move CC0 setter to another block (it can set up the |
2588 | same flag for previous CC0 users which is safe). */ | |
2589 | CANT_MOVE (prev_nonnote_insn (insn)) = 1; | |
e1ab7874 | 2590 | |
2591 | if (cslr_p && sched_deps_info->finish_rhs) | |
2592 | sched_deps_info->finish_rhs (); | |
2593 | ||
6adce0fb | 2594 | return; |
6adce0fb | 2595 | |
2596 | case REG: | |
2597 | { | |
6adce0fb | 2598 | int regno = REGNO (x); |
3754d046 | 2599 | machine_mode mode = GET_MODE (x); |
8ad6f16d | 2600 | |
2601 | sched_analyze_reg (deps, regno, mode, USE, insn); | |
1541bfd5 | 2602 | |
2603 | #ifdef STACK_REGS | |
2604 | /* Treat all reads of a stack register as modifying the TOS. */ | |
2605 | if (regno >= FIRST_STACK_REG && regno <= LAST_STACK_REG) | |
2606 | { | |
8ad6f16d | 2607 | /* Avoid analyzing the same register twice. */ |
2608 | if (regno != FIRST_STACK_REG) | |
2609 | sched_analyze_reg (deps, FIRST_STACK_REG, mode, USE, insn); | |
2610 | sched_analyze_reg (deps, FIRST_STACK_REG, mode, SET, insn); | |
1541bfd5 | 2611 | } |
2612 | #endif | |
e1ab7874 | 2613 | |
2614 | if (cslr_p && sched_deps_info->finish_rhs) | |
2615 | sched_deps_info->finish_rhs (); | |
2616 | ||
6adce0fb | 2617 | return; |
2618 | } | |
2619 | ||
2620 | case MEM: | |
2621 | { | |
2622 | /* Reading memory. */ | |
f9a00e9e | 2623 | rtx_insn_list *u; |
355af201 | 2624 | rtx_insn_list *pending; |
2625 | rtx_expr_list *pending_mem; | |
503f2817 | 2626 | rtx t = x; |
6adce0fb | 2627 | |
e1ab7874 | 2628 | if (sched_deps_info->use_cselib) |
503f2817 | 2629 | { |
3754d046 | 2630 | machine_mode address_mode = get_address_mode (t); |
98155838 | 2631 | |
503f2817 | 2632 | t = shallow_copy_rtx (t); |
1f864115 | 2633 | cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, |
2634 | GET_MODE (t), insn); | |
2af89801 | 2635 | XEXP (t, 0) |
2636 | = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), | |
2637 | insn); | |
503f2817 | 2638 | } |
6adce0fb | 2639 | |
c971b445 | 2640 | if (!DEBUG_INSN_P (insn)) |
6adce0fb | 2641 | { |
c971b445 | 2642 | t = canon_rtx (t); |
2643 | pending = deps->pending_read_insns; | |
2644 | pending_mem = deps->pending_read_mems; | |
2645 | while (pending) | |
2646 | { | |
355af201 | 2647 | if (read_dependence (pending_mem->element (), t) |
c971b445 | 2648 | && ! sched_insns_conditions_mutex_p (insn, |
355af201 | 2649 | pending->insn ())) |
2650 | note_mem_dep (t, pending_mem->element (), | |
2651 | pending->insn (), | |
c971b445 | 2652 | DEP_ANTI); |
2653 | ||
355af201 | 2654 | pending = pending->next (); |
2655 | pending_mem = pending_mem->next (); | |
c971b445 | 2656 | } |
6adce0fb | 2657 | |
c971b445 | 2658 | pending = deps->pending_write_insns; |
2659 | pending_mem = deps->pending_write_mems; | |
2660 | while (pending) | |
e1ab7874 | 2661 | { |
355af201 | 2662 | if (true_dependence (pending_mem->element (), VOIDmode, t) |
c971b445 | 2663 | && ! sched_insns_conditions_mutex_p (insn, |
355af201 | 2664 | pending->insn ())) |
2665 | note_mem_dep (t, pending_mem->element (), | |
2666 | pending->insn (), | |
c971b445 | 2667 | sched_deps_info->generate_spec_deps |
2668 | ? BEGIN_DATA | DEP_TRUE : DEP_TRUE); | |
2669 | ||
355af201 | 2670 | pending = pending->next (); |
2671 | pending_mem = pending_mem->next (); | |
c971b445 | 2672 | } |
e1ab7874 | 2673 | |
f9a00e9e | 2674 | for (u = deps->last_pending_memory_flush; u; u = u->next ()) |
2675 | add_dependence (insn, u->insn (), REG_DEP_ANTI); | |
effd1640 | 2676 | |
f9a00e9e | 2677 | for (u = deps->pending_jump_insns; u; u = u->next ()) |
effd1640 | 2678 | if (deps_may_trap_p (x)) |
2679 | { | |
2680 | if ((sched_deps_info->generate_spec_deps) | |
2681 | && sel_sched_p () && (spec_info->mask & BEGIN_CONTROL)) | |
2682 | { | |
2683 | ds_t ds = set_dep_weak (DEP_ANTI, BEGIN_CONTROL, | |
2684 | MAX_DEP_WEAK); | |
2685 | ||
f9a00e9e | 2686 | note_dep (u->insn (), ds); |
effd1640 | 2687 | } |
2688 | else | |
f9a00e9e | 2689 | add_dependence (insn, u->insn (), REG_DEP_CONTROL); |
effd1640 | 2690 | } |
e1ab7874 | 2691 | } |
6adce0fb | 2692 | |
2693 | /* Always add these dependencies to pending_reads, since | |
2694 | this insn may be followed by a write. */ | |
c2066d40 | 2695 | if (!deps->readonly) |
2696 | { | |
2697 | if ((deps->pending_read_list_length | |
2698 | + deps->pending_write_list_length) | |
1deb811a | 2699 | >= MAX_PENDING_LIST_LENGTH |
c2066d40 | 2700 | && !DEBUG_INSN_P (insn)) |
2701 | flush_pending_lists (deps, insn, true, true); | |
2702 | add_insn_mem_dependence (deps, true, insn, x); | |
2703 | } | |
6adce0fb | 2704 | |
6adce0fb | 2705 | sched_analyze_2 (deps, XEXP (x, 0), insn); |
e1ab7874 | 2706 | |
2707 | if (cslr_p && sched_deps_info->finish_rhs) | |
2708 | sched_deps_info->finish_rhs (); | |
2709 | ||
6adce0fb | 2710 | return; |
2711 | } | |
2712 | ||
1a542f97 | 2713 | /* Force pending stores to memory in case a trap handler needs them. |
2714 | Also force pending loads from memory; loads and stores can segfault | |
2715 | and the signal handler won't be triggered if the trap insn was moved | |
2716 | above load or store insn. */ | |
6adce0fb | 2717 | case TRAP_IF: |
1a542f97 | 2718 | flush_pending_lists (deps, insn, true, true); |
6adce0fb | 2719 | break; |
2720 | ||
6540132c | 2721 | case PREFETCH: |
2722 | if (PREFETCH_SCHEDULE_BARRIER_P (x)) | |
2723 | reg_pending_barrier = TRUE_BARRIER; | |
42fb263f | 2724 | /* Prefetch insn contains addresses only. So if the prefetch |
2725 | address has no registers, there will be no dependencies on | |
2726 | the prefetch insn. This is wrong with result code | |
2727 | correctness point of view as such prefetch can be moved below | |
2728 | a jump insn which usually generates MOVE_BARRIER preventing | |
2729 | to move insns containing registers or memories through the | |
2730 | barrier. It is also wrong with generated code performance | |
2731 | point of view as prefetch withouth dependecies will have a | |
2732 | tendency to be issued later instead of earlier. It is hard | |
2733 | to generate accurate dependencies for prefetch insns as | |
2734 | prefetch has only the start address but it is better to have | |
2735 | something than nothing. */ | |
a2e20fd2 | 2736 | if (!deps->readonly) |
12e51a1d | 2737 | { |
2738 | rtx x = gen_rtx_MEM (Pmode, XEXP (PATTERN (insn), 0)); | |
2739 | if (sched_deps_info->use_cselib) | |
2740 | cselib_lookup_from_insn (x, Pmode, true, VOIDmode, insn); | |
2741 | add_insn_mem_dependence (deps, true, insn, x); | |
2742 | } | |
6540132c | 2743 | break; |
2744 | ||
e5e67ff9 | 2745 | case UNSPEC_VOLATILE: |
2746 | flush_pending_lists (deps, insn, true, true); | |
2747 | /* FALLTHRU */ | |
2748 | ||
6adce0fb | 2749 | case ASM_OPERANDS: |
2750 | case ASM_INPUT: | |
6adce0fb | 2751 | { |
6adce0fb | 2752 | /* Traditional and volatile asm instructions must be considered to use |
2753 | and clobber all hard registers, all pseudo-registers and all of | |
2754 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
2755 | ||
2756 | Consider for instance a volatile asm that changes the fpu rounding | |
2757 | mode. An insn should not be moved across this even if it only uses | |
2758 | pseudo-regs because it might give an incorrectly rounded result. */ | |
5185189e | 2759 | if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x)) |
2760 | && !DEBUG_INSN_P (insn)) | |
c14a239f | 2761 | reg_pending_barrier = TRUE_BARRIER; |
6adce0fb | 2762 | |
2763 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
2764 | We can not just fall through here since then we would be confused | |
2765 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
2766 | traditional asms unlike their normal usage. */ | |
2767 | ||
2768 | if (code == ASM_OPERANDS) | |
2769 | { | |
2770 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
2771 | sched_analyze_2 (deps, ASM_OPERANDS_INPUT (x, j), insn); | |
e1ab7874 | 2772 | |
2773 | if (cslr_p && sched_deps_info->finish_rhs) | |
2774 | sched_deps_info->finish_rhs (); | |
2775 | ||
6adce0fb | 2776 | return; |
2777 | } | |
2778 | break; | |
2779 | } | |
2780 | ||
2781 | case PRE_DEC: | |
2782 | case POST_DEC: | |
2783 | case PRE_INC: | |
2784 | case POST_INC: | |
2785 | /* These both read and modify the result. We must handle them as writes | |
2786 | to get proper dependencies for following instructions. We must handle | |
2787 | them as reads to get proper dependencies from this to previous | |
2788 | instructions. Thus we need to pass them to both sched_analyze_1 | |
2789 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
2790 | to get the proper antecedent for the read. */ | |
2791 | sched_analyze_2 (deps, XEXP (x, 0), insn); | |
2792 | sched_analyze_1 (deps, x, insn); | |
e1ab7874 | 2793 | |
2794 | if (cslr_p && sched_deps_info->finish_rhs) | |
2795 | sched_deps_info->finish_rhs (); | |
2796 | ||
6adce0fb | 2797 | return; |
2798 | ||
2799 | case POST_MODIFY: | |
2800 | case PRE_MODIFY: | |
2801 | /* op0 = op0 + op1 */ | |
2802 | sched_analyze_2 (deps, XEXP (x, 0), insn); | |
2803 | sched_analyze_2 (deps, XEXP (x, 1), insn); | |
2804 | sched_analyze_1 (deps, x, insn); | |
e1ab7874 | 2805 | |
2806 | if (cslr_p && sched_deps_info->finish_rhs) | |
2807 | sched_deps_info->finish_rhs (); | |
2808 | ||
6adce0fb | 2809 | return; |
2810 | ||
2811 | default: | |
2812 | break; | |
2813 | } | |
2814 | ||
2815 | /* Other cases: walk the insn. */ | |
2816 | fmt = GET_RTX_FORMAT (code); | |
2817 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2818 | { | |
2819 | if (fmt[i] == 'e') | |
2820 | sched_analyze_2 (deps, XEXP (x, i), insn); | |
2821 | else if (fmt[i] == 'E') | |
2822 | for (j = 0; j < XVECLEN (x, i); j++) | |
2823 | sched_analyze_2 (deps, XVECEXP (x, i, j), insn); | |
2824 | } | |
e1ab7874 | 2825 | |
2826 | if (cslr_p && sched_deps_info->finish_rhs) | |
2827 | sched_deps_info->finish_rhs (); | |
6adce0fb | 2828 | } |
2829 | ||
6da3491c | 2830 | /* Try to group two fusible insns together to prevent scheduler |
b0aa049b | 2831 | from scheduling them apart. */ |
55e7138c | 2832 | |
2833 | static void | |
18282db0 | 2834 | sched_macro_fuse_insns (rtx_insn *insn) |
55e7138c | 2835 | { |
18282db0 | 2836 | rtx_insn *prev; |
b920c9b1 | 2837 | prev = prev_nonnote_nondebug_insn (insn); |
2838 | if (!prev) | |
2839 | return; | |
2840 | ||
b0aa049b | 2841 | if (any_condjump_p (insn)) |
2842 | { | |
2843 | unsigned int condreg1, condreg2; | |
2844 | rtx cc_reg_1; | |
2845 | targetm.fixed_condition_code_regs (&condreg1, &condreg2); | |
2846 | cc_reg_1 = gen_rtx_REG (CCmode, condreg1); | |
b920c9b1 | 2847 | if (reg_referenced_p (cc_reg_1, PATTERN (insn)) |
2848 | && modified_in_p (cc_reg_1, prev)) | |
2849 | { | |
2850 | if (targetm.sched.macro_fusion_pair_p (prev, insn)) | |
2851 | SCHED_GROUP_P (insn) = 1; | |
2852 | return; | |
2853 | } | |
b0aa049b | 2854 | } |
55e7138c | 2855 | |
b920c9b1 | 2856 | if (single_set (insn) && single_set (prev)) |
2857 | { | |
2858 | if (targetm.sched.macro_fusion_pair_p (prev, insn)) | |
2859 | SCHED_GROUP_P (insn) = 1; | |
b0aa049b | 2860 | } |
55e7138c | 2861 | } |
2862 | ||
acf58115 | 2863 | /* Get the implicit reg pending clobbers for INSN and save them in TEMP. */ |
2864 | void | |
2865 | get_implicit_reg_pending_clobbers (HARD_REG_SET *temp, rtx_insn *insn) | |
2866 | { | |
2867 | extract_insn (insn); | |
2868 | preprocess_constraints (insn); | |
2869 | alternative_mask preferred = get_preferred_alternatives (insn); | |
2870 | ira_implicitly_set_insn_hard_regs (temp, preferred); | |
2871 | AND_COMPL_HARD_REG_SET (*temp, ira_no_alloc_regs); | |
2872 | } | |
2873 | ||
6adce0fb | 2874 | /* Analyze an INSN with pattern X to find all dependencies. */ |
6adce0fb | 2875 | static void |
b24ef467 | 2876 | sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) |
6adce0fb | 2877 | { |
19cb6b50 | 2878 | RTX_CODE code = GET_CODE (x); |
6adce0fb | 2879 | rtx link; |
4f917ffe | 2880 | unsigned i; |
8c97cf13 | 2881 | reg_set_iterator rsi; |
6adce0fb | 2882 | |
a7dcf969 | 2883 | if (! reload_completed) |
2884 | { | |
2885 | HARD_REG_SET temp; | |
acf58115 | 2886 | get_implicit_reg_pending_clobbers (&temp, insn); |
a7dcf969 | 2887 | IOR_HARD_REG_SET (implicit_reg_pending_clobbers, temp); |
2888 | } | |
2889 | ||
e1ab7874 | 2890 | can_start_lhs_rhs_p = (NONJUMP_INSN_P (insn) |
2891 | && code == SET); | |
2892 | ||
55e7138c | 2893 | /* Group compare and branch insns for macro-fusion. */ |
2894 | if (targetm.sched.macro_fusion_p | |
2895 | && targetm.sched.macro_fusion_p ()) | |
b0aa049b | 2896 | sched_macro_fuse_insns (insn); |
55e7138c | 2897 | |
326d0c19 | 2898 | if (may_trap_p (x)) |
9d75589a | 2899 | /* Avoid moving trapping instructions across function calls that might |
326d0c19 | 2900 | not always return. */ |
2901 | add_dependence_list (insn, deps->last_function_call_may_noreturn, | |
d452a169 | 2902 | 1, REG_DEP_ANTI, true); |
326d0c19 | 2903 | |
0741df1e | 2904 | /* We must avoid creating a situation in which two successors of the |
2905 | current block have different unwind info after scheduling. If at any | |
2906 | point the two paths re-join this leads to incorrect unwind info. */ | |
2907 | /* ??? There are certain situations involving a forced frame pointer in | |
2908 | which, with extra effort, we could fix up the unwind info at a later | |
2909 | CFG join. However, it seems better to notice these cases earlier | |
2910 | during prologue generation and avoid marking the frame pointer setup | |
2911 | as frame-related at all. */ | |
2912 | if (RTX_FRAME_RELATED_P (insn)) | |
420a9b66 | 2913 | { |
2914 | /* Make sure prologue insn is scheduled before next jump. */ | |
2915 | deps->sched_before_next_jump | |
2916 | = alloc_INSN_LIST (insn, deps->sched_before_next_jump); | |
2917 | ||
2918 | /* Make sure epilogue insn is scheduled after preceding jumps. */ | |
d452a169 | 2919 | add_dependence_list (insn, deps->pending_jump_insns, 1, REG_DEP_ANTI, |
2920 | true); | |
420a9b66 | 2921 | } |
0741df1e | 2922 | |
6adce0fb | 2923 | if (code == COND_EXEC) |
2924 | { | |
2925 | sched_analyze_2 (deps, COND_EXEC_TEST (x), insn); | |
2926 | ||
2927 | /* ??? Should be recording conditions so we reduce the number of | |
424da949 | 2928 | false dependencies. */ |
6adce0fb | 2929 | x = COND_EXEC_CODE (x); |
2930 | code = GET_CODE (x); | |
2931 | } | |
2932 | if (code == SET || code == CLOBBER) | |
a35ad173 | 2933 | { |
2934 | sched_analyze_1 (deps, x, insn); | |
2935 | ||
2936 | /* Bare clobber insns are used for letting life analysis, reg-stack | |
2937 | and others know that a value is dead. Depend on the last call | |
2938 | instruction so that reg-stack won't get confused. */ | |
2939 | if (code == CLOBBER) | |
a7dcf969 | 2940 | add_dependence_list (insn, deps->last_function_call, 1, |
d452a169 | 2941 | REG_DEP_OUTPUT, true); |
a35ad173 | 2942 | } |
6adce0fb | 2943 | else if (code == PARALLEL) |
2944 | { | |
4f917ffe | 2945 | for (i = XVECLEN (x, 0); i--;) |
6adce0fb | 2946 | { |
2947 | rtx sub = XVECEXP (x, 0, i); | |
2948 | code = GET_CODE (sub); | |
2949 | ||
2950 | if (code == COND_EXEC) | |
2951 | { | |
2952 | sched_analyze_2 (deps, COND_EXEC_TEST (sub), insn); | |
2953 | sub = COND_EXEC_CODE (sub); | |
2954 | code = GET_CODE (sub); | |
2955 | } | |
2956 | if (code == SET || code == CLOBBER) | |
2957 | sched_analyze_1 (deps, sub, insn); | |
2958 | else | |
2959 | sched_analyze_2 (deps, sub, insn); | |
2960 | } | |
2961 | } | |
2962 | else | |
2963 | sched_analyze_2 (deps, x, insn); | |
2964 | ||
2965 | /* Mark registers CLOBBERED or used by called function. */ | |
6d7dc5b9 | 2966 | if (CALL_P (insn)) |
9239aee6 | 2967 | { |
2968 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
2969 | { | |
2970 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
2971 | sched_analyze_1 (deps, XEXP (link, 0), insn); | |
c8010b80 | 2972 | else if (GET_CODE (XEXP (link, 0)) != SET) |
9239aee6 | 2973 | sched_analyze_2 (deps, XEXP (link, 0), insn); |
2974 | } | |
e703e1fc | 2975 | /* Don't schedule anything after a tail call, tail call needs |
2976 | to use at least all call-saved registers. */ | |
2977 | if (SIBLING_CALL_P (insn)) | |
2978 | reg_pending_barrier = TRUE_BARRIER; | |
2979 | else if (find_reg_note (insn, REG_SETJMP, NULL)) | |
c14a239f | 2980 | reg_pending_barrier = MOVE_BARRIER; |
9239aee6 | 2981 | } |
6adce0fb | 2982 | |
6d7dc5b9 | 2983 | if (JUMP_P (insn)) |
d6141c0c | 2984 | { |
9ed997be | 2985 | rtx_insn *next = next_nonnote_nondebug_insn (insn); |
6d7dc5b9 | 2986 | if (next && BARRIER_P (next)) |
ca93e19d | 2987 | reg_pending_barrier = MOVE_BARRIER; |
d6141c0c | 2988 | else |
2989 | { | |
355af201 | 2990 | rtx_insn_list *pending; |
2991 | rtx_expr_list *pending_mem; | |
31c5c470 | 2992 | |
e1ab7874 | 2993 | if (sched_deps_info->compute_jump_reg_dependencies) |
2994 | { | |
effd1640 | 2995 | (*sched_deps_info->compute_jump_reg_dependencies) |
2996 | (insn, reg_pending_control_uses); | |
e1ab7874 | 2997 | |
e1ab7874 | 2998 | /* Make latency of jump equal to 0 by using anti-dependence. */ |
effd1640 | 2999 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_control_uses, 0, i, rsi) |
e1ab7874 | 3000 | { |
3001 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3002 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_ANTI, |
3003 | false); | |
a7dcf969 | 3004 | add_dependence_list (insn, reg_last->implicit_sets, |
d452a169 | 3005 | 0, REG_DEP_ANTI, false); |
e1ab7874 | 3006 | add_dependence_list (insn, reg_last->clobbers, 0, |
d452a169 | 3007 | REG_DEP_ANTI, false); |
e1ab7874 | 3008 | } |
e1ab7874 | 3009 | } |
097ef0af | 3010 | |
9807cfe1 | 3011 | /* All memory writes and volatile reads must happen before the |
3012 | jump. Non-volatile reads must happen before the jump iff | |
3013 | the result is needed by the above register used mask. */ | |
3014 | ||
097ef0af | 3015 | pending = deps->pending_write_insns; |
3016 | pending_mem = deps->pending_write_mems; | |
3017 | while (pending) | |
3018 | { | |
355af201 | 3019 | if (! sched_insns_conditions_mutex_p (insn, pending->insn ())) |
3020 | add_dependence (insn, pending->insn (), | |
b24ef467 | 3021 | REG_DEP_OUTPUT); |
355af201 | 3022 | pending = pending->next (); |
3023 | pending_mem = pending_mem->next (); | |
9807cfe1 | 3024 | } |
097ef0af | 3025 | |
9807cfe1 | 3026 | pending = deps->pending_read_insns; |
3027 | pending_mem = deps->pending_read_mems; | |
3028 | while (pending) | |
3029 | { | |
355af201 | 3030 | if (MEM_VOLATILE_P (pending_mem->element ()) |
3031 | && ! sched_insns_conditions_mutex_p (insn, pending->insn ())) | |
3032 | add_dependence (insn, pending->insn (), | |
b24ef467 | 3033 | REG_DEP_OUTPUT); |
355af201 | 3034 | pending = pending->next (); |
3035 | pending_mem = pending_mem->next (); | |
097ef0af | 3036 | } |
3037 | ||
e228dd5d | 3038 | add_dependence_list (insn, deps->last_pending_memory_flush, 1, |
d452a169 | 3039 | REG_DEP_ANTI, true); |
effd1640 | 3040 | add_dependence_list (insn, deps->pending_jump_insns, 1, |
d452a169 | 3041 | REG_DEP_ANTI, true); |
d6141c0c | 3042 | } |
d6141c0c | 3043 | } |
3044 | ||
f787dd2b | 3045 | /* If this instruction can throw an exception, then moving it changes |
40734805 | 3046 | where block boundaries fall. This is mighty confusing elsewhere. |
88a00894 | 3047 | Therefore, prevent such an instruction from being moved. Same for |
3048 | non-jump instructions that define block boundaries. | |
3049 | ??? Unclear whether this is still necessary in EBB mode. If not, | |
3050 | add_branch_dependences should be adjusted for RGN mode instead. */ | |
3051 | if (((CALL_P (insn) || JUMP_P (insn)) && can_throw_internal (insn)) | |
3052 | || (NONJUMP_INSN_P (insn) && control_flow_insn_p (insn))) | |
c14a239f | 3053 | reg_pending_barrier = MOVE_BARRIER; |
f787dd2b | 3054 | |
b30b031c | 3055 | if (sched_pressure != SCHED_PRESSURE_NONE) |
a7dcf969 | 3056 | { |
3057 | setup_insn_reg_uses (deps, insn); | |
c15d7785 | 3058 | init_insn_reg_pressure_info (insn); |
a7dcf969 | 3059 | } |
3060 | ||
9845d120 | 3061 | /* Add register dependencies for insn. */ |
3062 | if (DEBUG_INSN_P (insn)) | |
3063 | { | |
b24ef467 | 3064 | rtx_insn *prev = deps->last_debug_insn; |
f9a00e9e | 3065 | rtx_insn_list *u; |
9845d120 | 3066 | |
3067 | if (!deps->readonly) | |
3068 | deps->last_debug_insn = insn; | |
3069 | ||
3070 | if (prev) | |
3071 | add_dependence (insn, prev, REG_DEP_ANTI); | |
3072 | ||
3073 | add_dependence_list (insn, deps->last_function_call, 1, | |
d452a169 | 3074 | REG_DEP_ANTI, false); |
9845d120 | 3075 | |
d452a169 | 3076 | if (!sel_sched_p ()) |
f9a00e9e | 3077 | for (u = deps->last_pending_memory_flush; u; u = u->next ()) |
3078 | add_dependence (insn, u->insn (), REG_DEP_ANTI); | |
9845d120 | 3079 | |
3080 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_uses, 0, i, rsi) | |
3081 | { | |
3082 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3083 | add_dependence_list (insn, reg_last->sets, 1, REG_DEP_ANTI, false); |
effd1640 | 3084 | /* There's no point in making REG_DEP_CONTROL dependencies for |
3085 | debug insns. */ | |
d452a169 | 3086 | add_dependence_list (insn, reg_last->clobbers, 1, REG_DEP_ANTI, |
3087 | false); | |
c971b445 | 3088 | |
3089 | if (!deps->readonly) | |
3090 | reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses); | |
9845d120 | 3091 | } |
3092 | CLEAR_REG_SET (reg_pending_uses); | |
3093 | ||
3094 | /* Quite often, a debug insn will refer to stuff in the | |
3095 | previous instruction, but the reason we want this | |
3096 | dependency here is to make sure the scheduler doesn't | |
3097 | gratuitously move a debug insn ahead. This could dirty | |
3098 | DF flags and cause additional analysis that wouldn't have | |
3099 | occurred in compilation without debug insns, and such | |
3100 | additional analysis can modify the generated code. */ | |
3101 | prev = PREV_INSN (insn); | |
3102 | ||
3103 | if (prev && NONDEBUG_INSN_P (prev)) | |
3104 | add_dependence (insn, prev, REG_DEP_ANTI); | |
3105 | } | |
ca93e19d | 3106 | else |
3107 | { | |
6c2d9e41 | 3108 | regset_head set_or_clobbered; |
3109 | ||
ca93e19d | 3110 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_uses, 0, i, rsi) |
a7dcf969 | 3111 | { |
3112 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3113 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false); |
3114 | add_dependence_list (insn, reg_last->implicit_sets, 0, REG_DEP_ANTI, | |
3115 | false); | |
3116 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE, | |
3117 | false); | |
48e1416a | 3118 | |
a7dcf969 | 3119 | if (!deps->readonly) |
3120 | { | |
3121 | reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses); | |
3122 | reg_last->uses_length++; | |
3123 | } | |
3124 | } | |
48e1416a | 3125 | |
a7dcf969 | 3126 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3127 | if (TEST_HARD_REG_BIT (implicit_reg_pending_uses, i)) | |
3128 | { | |
3129 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3130 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false); |
a7dcf969 | 3131 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
d452a169 | 3132 | REG_DEP_ANTI, false); |
3133 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE, | |
3134 | false); | |
48e1416a | 3135 | |
a7dcf969 | 3136 | if (!deps->readonly) |
3137 | { | |
3138 | reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses); | |
3139 | reg_last->uses_length++; | |
3140 | } | |
3141 | } | |
e1ab7874 | 3142 | |
6c2d9e41 | 3143 | if (targetm.sched.exposed_pipeline) |
3144 | { | |
3145 | INIT_REG_SET (&set_or_clobbered); | |
3146 | bitmap_ior (&set_or_clobbered, reg_pending_clobbers, | |
3147 | reg_pending_sets); | |
3148 | EXECUTE_IF_SET_IN_REG_SET (&set_or_clobbered, 0, i, rsi) | |
3149 | { | |
3150 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3151 | rtx list; | |
3152 | for (list = reg_last->uses; list; list = XEXP (list, 1)) | |
3153 | { | |
3154 | rtx other = XEXP (list, 0); | |
60ba0654 | 3155 | if (INSN_CACHED_COND (other) != const_true_rtx |
2ec77a7c | 3156 | && refers_to_regno_p (i, INSN_CACHED_COND (other))) |
60ba0654 | 3157 | INSN_CACHED_COND (other) = const_true_rtx; |
6c2d9e41 | 3158 | } |
3159 | } | |
3160 | } | |
3161 | ||
a7dcf969 | 3162 | /* If the current insn is conditional, we can't free any |
3163 | of the lists. */ | |
3164 | if (sched_has_condition_p (insn)) | |
3165 | { | |
3166 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, rsi) | |
3167 | { | |
3168 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3169 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_OUTPUT, |
3170 | false); | |
a7dcf969 | 3171 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
d452a169 | 3172 | REG_DEP_ANTI, false); |
3173 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, | |
3174 | false); | |
effd1640 | 3175 | add_dependence_list (insn, reg_last->control_uses, 0, |
d452a169 | 3176 | REG_DEP_CONTROL, false); |
48e1416a | 3177 | |
a7dcf969 | 3178 | if (!deps->readonly) |
3179 | { | |
3180 | reg_last->clobbers | |
3181 | = alloc_INSN_LIST (insn, reg_last->clobbers); | |
3182 | reg_last->clobbers_length++; | |
3183 | } | |
3184 | } | |
3185 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, rsi) | |
3186 | { | |
3187 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3188 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_OUTPUT, |
3189 | false); | |
a7dcf969 | 3190 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
d452a169 | 3191 | REG_DEP_ANTI, false); |
3192 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_OUTPUT, | |
3193 | false); | |
3194 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, | |
3195 | false); | |
effd1640 | 3196 | add_dependence_list (insn, reg_last->control_uses, 0, |
d452a169 | 3197 | REG_DEP_CONTROL, false); |
48e1416a | 3198 | |
a7dcf969 | 3199 | if (!deps->readonly) |
6aed13f1 | 3200 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); |
a7dcf969 | 3201 | } |
3202 | } | |
3203 | else | |
3204 | { | |
3205 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, rsi) | |
3206 | { | |
3207 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1deb811a | 3208 | if (reg_last->uses_length >= MAX_PENDING_LIST_LENGTH |
3209 | || reg_last->clobbers_length >= MAX_PENDING_LIST_LENGTH) | |
a7dcf969 | 3210 | { |
3211 | add_dependence_list_and_free (deps, insn, ®_last->sets, 0, | |
d452a169 | 3212 | REG_DEP_OUTPUT, false); |
a7dcf969 | 3213 | add_dependence_list_and_free (deps, insn, |
3214 | ®_last->implicit_sets, 0, | |
d452a169 | 3215 | REG_DEP_ANTI, false); |
a7dcf969 | 3216 | add_dependence_list_and_free (deps, insn, ®_last->uses, 0, |
d452a169 | 3217 | REG_DEP_ANTI, false); |
effd1640 | 3218 | add_dependence_list_and_free (deps, insn, |
3219 | ®_last->control_uses, 0, | |
d452a169 | 3220 | REG_DEP_ANTI, false); |
3221 | add_dependence_list_and_free (deps, insn, | |
3222 | ®_last->clobbers, 0, | |
3223 | REG_DEP_OUTPUT, false); | |
48e1416a | 3224 | |
a7dcf969 | 3225 | if (!deps->readonly) |
3226 | { | |
3227 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); | |
3228 | reg_last->clobbers_length = 0; | |
3229 | reg_last->uses_length = 0; | |
3230 | } | |
3231 | } | |
3232 | else | |
3233 | { | |
d452a169 | 3234 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_OUTPUT, |
3235 | false); | |
a7dcf969 | 3236 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
d452a169 | 3237 | REG_DEP_ANTI, false); |
3238 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, | |
3239 | false); | |
effd1640 | 3240 | add_dependence_list (insn, reg_last->control_uses, 0, |
d452a169 | 3241 | REG_DEP_CONTROL, false); |
a7dcf969 | 3242 | } |
48e1416a | 3243 | |
a7dcf969 | 3244 | if (!deps->readonly) |
3245 | { | |
3246 | reg_last->clobbers_length++; | |
3247 | reg_last->clobbers | |
3248 | = alloc_INSN_LIST (insn, reg_last->clobbers); | |
3249 | } | |
3250 | } | |
3251 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, rsi) | |
3252 | { | |
3253 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
48e1416a | 3254 | |
a7dcf969 | 3255 | add_dependence_list_and_free (deps, insn, ®_last->sets, 0, |
d452a169 | 3256 | REG_DEP_OUTPUT, false); |
a7dcf969 | 3257 | add_dependence_list_and_free (deps, insn, |
3258 | ®_last->implicit_sets, | |
d452a169 | 3259 | 0, REG_DEP_ANTI, false); |
a7dcf969 | 3260 | add_dependence_list_and_free (deps, insn, ®_last->clobbers, 0, |
d452a169 | 3261 | REG_DEP_OUTPUT, false); |
a7dcf969 | 3262 | add_dependence_list_and_free (deps, insn, ®_last->uses, 0, |
d452a169 | 3263 | REG_DEP_ANTI, false); |
effd1640 | 3264 | add_dependence_list (insn, reg_last->control_uses, 0, |
d452a169 | 3265 | REG_DEP_CONTROL, false); |
48e1416a | 3266 | |
a7dcf969 | 3267 | if (!deps->readonly) |
3268 | { | |
3269 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); | |
3270 | reg_last->uses_length = 0; | |
3271 | reg_last->clobbers_length = 0; | |
a7dcf969 | 3272 | } |
3273 | } | |
3274 | } | |
effd1640 | 3275 | if (!deps->readonly) |
3276 | { | |
3277 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_control_uses, 0, i, rsi) | |
3278 | { | |
3279 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3280 | reg_last->control_uses | |
3281 | = alloc_INSN_LIST (insn, reg_last->control_uses); | |
3282 | } | |
3283 | } | |
ca93e19d | 3284 | } |
3285 | ||
a7dcf969 | 3286 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3287 | if (TEST_HARD_REG_BIT (implicit_reg_pending_clobbers, i)) | |
3288 | { | |
3289 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3290 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_ANTI, false); |
3291 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_ANTI, false); | |
3292 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, false); | |
3293 | add_dependence_list (insn, reg_last->control_uses, 0, REG_DEP_ANTI, | |
3294 | false); | |
48e1416a | 3295 | |
a7dcf969 | 3296 | if (!deps->readonly) |
3297 | reg_last->implicit_sets | |
3298 | = alloc_INSN_LIST (insn, reg_last->implicit_sets); | |
3299 | } | |
3300 | ||
e1ab7874 | 3301 | if (!deps->readonly) |
3302 | { | |
3303 | IOR_REG_SET (&deps->reg_last_in_use, reg_pending_uses); | |
3304 | IOR_REG_SET (&deps->reg_last_in_use, reg_pending_clobbers); | |
3305 | IOR_REG_SET (&deps->reg_last_in_use, reg_pending_sets); | |
a7dcf969 | 3306 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3307 | if (TEST_HARD_REG_BIT (implicit_reg_pending_uses, i) | |
3308 | || TEST_HARD_REG_BIT (implicit_reg_pending_clobbers, i)) | |
3309 | SET_REGNO_REG_SET (&deps->reg_last_in_use, i); | |
e1ab7874 | 3310 | |
3311 | /* Set up the pending barrier found. */ | |
3312 | deps->last_reg_pending_barrier = reg_pending_barrier; | |
3313 | } | |
ca93e19d | 3314 | |
3315 | CLEAR_REG_SET (reg_pending_uses); | |
3316 | CLEAR_REG_SET (reg_pending_clobbers); | |
3317 | CLEAR_REG_SET (reg_pending_sets); | |
effd1640 | 3318 | CLEAR_REG_SET (reg_pending_control_uses); |
a7dcf969 | 3319 | CLEAR_HARD_REG_SET (implicit_reg_pending_clobbers); |
3320 | CLEAR_HARD_REG_SET (implicit_reg_pending_uses); | |
ca93e19d | 3321 | |
f787dd2b | 3322 | /* Add dependencies if a scheduling barrier was found. */ |
5deaeb50 | 3323 | if (reg_pending_barrier) |
f787dd2b | 3324 | { |
58ada791 | 3325 | /* In the case of barrier the most added dependencies are not |
3326 | real, so we use anti-dependence here. */ | |
e1ab7874 | 3327 | if (sched_has_condition_p (insn)) |
6adce0fb | 3328 | { |
8c97cf13 | 3329 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
5deaeb50 | 3330 | { |
3331 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
d452a169 | 3332 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, |
3333 | true); | |
a7dcf969 | 3334 | add_dependence_list (insn, reg_last->sets, 0, |
3335 | reg_pending_barrier == TRUE_BARRIER | |
d452a169 | 3336 | ? REG_DEP_TRUE : REG_DEP_ANTI, true); |
a7dcf969 | 3337 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
d452a169 | 3338 | REG_DEP_ANTI, true); |
a7dcf969 | 3339 | add_dependence_list (insn, reg_last->clobbers, 0, |
3340 | reg_pending_barrier == TRUE_BARRIER | |
d452a169 | 3341 | ? REG_DEP_TRUE : REG_DEP_ANTI, true); |
8c97cf13 | 3342 | } |
5deaeb50 | 3343 | } |
3344 | else | |
3345 | { | |
8c97cf13 | 3346 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
5deaeb50 | 3347 | { |
3348 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
e1ab7874 | 3349 | add_dependence_list_and_free (deps, insn, ®_last->uses, 0, |
d452a169 | 3350 | REG_DEP_ANTI, true); |
effd1640 | 3351 | add_dependence_list_and_free (deps, insn, |
3352 | ®_last->control_uses, 0, | |
d452a169 | 3353 | REG_DEP_CONTROL, true); |
a7dcf969 | 3354 | add_dependence_list_and_free (deps, insn, ®_last->sets, 0, |
3355 | reg_pending_barrier == TRUE_BARRIER | |
d452a169 | 3356 | ? REG_DEP_TRUE : REG_DEP_ANTI, |
3357 | true); | |
a7dcf969 | 3358 | add_dependence_list_and_free (deps, insn, |
3359 | ®_last->implicit_sets, 0, | |
d452a169 | 3360 | REG_DEP_ANTI, true); |
a7dcf969 | 3361 | add_dependence_list_and_free (deps, insn, ®_last->clobbers, 0, |
3362 | reg_pending_barrier == TRUE_BARRIER | |
d452a169 | 3363 | ? REG_DEP_TRUE : REG_DEP_ANTI, |
3364 | true); | |
6adce0fb | 3365 | |
e1ab7874 | 3366 | if (!deps->readonly) |
3367 | { | |
3368 | reg_last->uses_length = 0; | |
3369 | reg_last->clobbers_length = 0; | |
3370 | } | |
3371 | } | |
4164e76b | 3372 | } |
5deaeb50 | 3373 | |
e1ab7874 | 3374 | if (!deps->readonly) |
3375 | for (i = 0; i < (unsigned)deps->max_reg; i++) | |
3376 | { | |
3377 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3378 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); | |
3379 | SET_REGNO_REG_SET (&deps->reg_last_in_use, i); | |
3380 | } | |
3381 | ||
f22426d2 | 3382 | /* Don't flush pending lists on speculative checks for |
e965825b | 3383 | selective scheduling. */ |
3384 | if (!sel_sched_p () || !sel_insn_is_speculation_check (insn)) | |
e1ab7874 | 3385 | flush_pending_lists (deps, insn, true, true); |
48e1416a | 3386 | |
c14a239f | 3387 | reg_pending_barrier = NOT_A_BARRIER; |
749c6f58 | 3388 | } |
6adce0fb | 3389 | |
3390 | /* If a post-call group is still open, see if it should remain so. | |
3391 | This insn must be a simple move of a hard reg to a pseudo or | |
3392 | vice-versa. | |
3393 | ||
ed5527ca | 3394 | We must avoid moving these insns for correctness on targets |
3395 | with small register classes, and for special registers like | |
6adce0fb | 3396 | PIC_OFFSET_TABLE_REGNUM. For simplicity, extend this to all |
3397 | hard regs for all targets. */ | |
3398 | ||
3399 | if (deps->in_post_call_group_p) | |
3400 | { | |
3401 | rtx tmp, set = single_set (insn); | |
3402 | int src_regno, dest_regno; | |
3403 | ||
3404 | if (set == NULL) | |
9845d120 | 3405 | { |
3406 | if (DEBUG_INSN_P (insn)) | |
3407 | /* We don't want to mark debug insns as part of the same | |
3408 | sched group. We know they really aren't, but if we use | |
3409 | debug insns to tell that a call group is over, we'll | |
3410 | get different code if debug insns are not there and | |
3411 | instructions that follow seem like they should be part | |
3412 | of the call group. | |
3413 | ||
fdb1b2b1 | 3414 | Also, if we did, chain_to_prev_insn would move the |
9845d120 | 3415 | deps of the debug insn to the call insn, modifying |
3416 | non-debug post-dependency counts of the debug insn | |
3417 | dependencies and otherwise messing with the scheduling | |
3418 | order. | |
3419 | ||
3420 | Instead, let such debug insns be scheduled freely, but | |
3421 | keep the call group open in case there are insns that | |
3422 | should be part of it afterwards. Since we grant debug | |
3423 | insns higher priority than even sched group insns, it | |
3424 | will all turn out all right. */ | |
3425 | goto debug_dont_end_call_group; | |
3426 | else | |
3427 | goto end_call_group; | |
3428 | } | |
6adce0fb | 3429 | |
3430 | tmp = SET_DEST (set); | |
3431 | if (GET_CODE (tmp) == SUBREG) | |
3432 | tmp = SUBREG_REG (tmp); | |
8ad4c111 | 3433 | if (REG_P (tmp)) |
6adce0fb | 3434 | dest_regno = REGNO (tmp); |
3435 | else | |
3436 | goto end_call_group; | |
3437 | ||
3438 | tmp = SET_SRC (set); | |
3439 | if (GET_CODE (tmp) == SUBREG) | |
3440 | tmp = SUBREG_REG (tmp); | |
0cbad263 | 3441 | if ((GET_CODE (tmp) == PLUS |
3442 | || GET_CODE (tmp) == MINUS) | |
8ad4c111 | 3443 | && REG_P (XEXP (tmp, 0)) |
0cbad263 | 3444 | && REGNO (XEXP (tmp, 0)) == STACK_POINTER_REGNUM |
3445 | && dest_regno == STACK_POINTER_REGNUM) | |
3446 | src_regno = STACK_POINTER_REGNUM; | |
8ad4c111 | 3447 | else if (REG_P (tmp)) |
6adce0fb | 3448 | src_regno = REGNO (tmp); |
3449 | else | |
3450 | goto end_call_group; | |
3451 | ||
3452 | if (src_regno < FIRST_PSEUDO_REGISTER | |
3453 | || dest_regno < FIRST_PSEUDO_REGISTER) | |
3454 | { | |
e1ab7874 | 3455 | if (!deps->readonly |
3456 | && deps->in_post_call_group_p == post_call_initial) | |
828f2394 | 3457 | deps->in_post_call_group_p = post_call; |
3458 | ||
48e1416a | 3459 | if (!sel_sched_p () || sched_emulate_haifa_p) |
e1ab7874 | 3460 | { |
3461 | SCHED_GROUP_P (insn) = 1; | |
3462 | CANT_MOVE (insn) = 1; | |
3463 | } | |
6adce0fb | 3464 | } |
3465 | else | |
3466 | { | |
3467 | end_call_group: | |
e1ab7874 | 3468 | if (!deps->readonly) |
3469 | deps->in_post_call_group_p = not_post_call; | |
6adce0fb | 3470 | } |
3471 | } | |
828f2394 | 3472 | |
9845d120 | 3473 | debug_dont_end_call_group: |
93f6b030 | 3474 | if ((current_sched_info->flags & DO_SPECULATION) |
3475 | && !sched_insn_is_legitimate_for_speculation_p (insn, 0)) | |
3476 | /* INSN has an internal dependency (e.g. r14 = [r14]) and thus cannot | |
3477 | be speculated. */ | |
3478 | { | |
e1ab7874 | 3479 | if (sel_sched_p ()) |
3480 | sel_mark_hard_insn (insn); | |
3481 | else | |
3482 | { | |
3483 | sd_iterator_def sd_it; | |
3484 | dep_t dep; | |
48e1416a | 3485 | |
e1ab7874 | 3486 | for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK); |
3487 | sd_iterator_cond (&sd_it, &dep);) | |
3488 | change_spec_dep_to_hard (sd_it); | |
3489 | } | |
93f6b030 | 3490 | } |
617529e8 | 3491 | |
3492 | /* We do not yet have code to adjust REG_ARGS_SIZE, therefore we must | |
3493 | honor their original ordering. */ | |
3494 | if (find_reg_note (insn, REG_ARGS_SIZE, NULL)) | |
3495 | { | |
3496 | if (deps->last_args_size) | |
3497 | add_dependence (insn, deps->last_args_size, REG_DEP_OUTPUT); | |
b628775e | 3498 | if (!deps->readonly) |
3499 | deps->last_args_size = insn; | |
617529e8 | 3500 | } |
5a321af0 | 3501 | |
3502 | /* We must not mix prologue and epilogue insns. See PR78029. */ | |
3503 | if (prologue_contains (insn)) | |
3504 | { | |
3505 | add_dependence_list (insn, deps->last_epilogue, true, REG_DEP_ANTI, true); | |
3506 | if (!deps->readonly) | |
3507 | { | |
3508 | if (deps->last_logue_was_epilogue) | |
3509 | free_INSN_LIST_list (&deps->last_prologue); | |
3510 | deps->last_prologue = alloc_INSN_LIST (insn, deps->last_prologue); | |
3511 | deps->last_logue_was_epilogue = false; | |
3512 | } | |
3513 | } | |
3514 | ||
3515 | if (epilogue_contains (insn)) | |
3516 | { | |
3517 | add_dependence_list (insn, deps->last_prologue, true, REG_DEP_ANTI, true); | |
3518 | if (!deps->readonly) | |
3519 | { | |
3520 | if (!deps->last_logue_was_epilogue) | |
3521 | free_INSN_LIST_list (&deps->last_epilogue); | |
3522 | deps->last_epilogue = alloc_INSN_LIST (insn, deps->last_epilogue); | |
3523 | deps->last_logue_was_epilogue = true; | |
3524 | } | |
3525 | } | |
6adce0fb | 3526 | } |
3527 | ||
326d0c19 | 3528 | /* Return TRUE if INSN might not always return normally (e.g. call exit, |
3529 | longjmp, loop forever, ...). */ | |
4a020a8c | 3530 | /* FIXME: Why can't this function just use flags_from_decl_or_type and |
3531 | test for ECF_NORETURN? */ | |
326d0c19 | 3532 | static bool |
71ce7f59 | 3533 | call_may_noreturn_p (rtx_insn *insn) |
326d0c19 | 3534 | { |
3535 | rtx call; | |
3536 | ||
3537 | /* const or pure calls that aren't looping will always return. */ | |
3538 | if (RTL_CONST_OR_PURE_CALL_P (insn) | |
3539 | && !RTL_LOOPING_CONST_OR_PURE_CALL_P (insn)) | |
3540 | return false; | |
3541 | ||
cf7fb72d | 3542 | call = get_call_rtx_from (insn); |
3543 | if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF) | |
326d0c19 | 3544 | { |
3545 | rtx symbol = XEXP (XEXP (call, 0), 0); | |
3546 | if (SYMBOL_REF_DECL (symbol) | |
3547 | && TREE_CODE (SYMBOL_REF_DECL (symbol)) == FUNCTION_DECL) | |
3548 | { | |
3549 | if (DECL_BUILT_IN_CLASS (SYMBOL_REF_DECL (symbol)) | |
3550 | == BUILT_IN_NORMAL) | |
3551 | switch (DECL_FUNCTION_CODE (SYMBOL_REF_DECL (symbol))) | |
3552 | { | |
3553 | case BUILT_IN_BCMP: | |
3554 | case BUILT_IN_BCOPY: | |
3555 | case BUILT_IN_BZERO: | |
3556 | case BUILT_IN_INDEX: | |
3557 | case BUILT_IN_MEMCHR: | |
3558 | case BUILT_IN_MEMCMP: | |
3559 | case BUILT_IN_MEMCPY: | |
3560 | case BUILT_IN_MEMMOVE: | |
3561 | case BUILT_IN_MEMPCPY: | |
3562 | case BUILT_IN_MEMSET: | |
3563 | case BUILT_IN_RINDEX: | |
3564 | case BUILT_IN_STPCPY: | |
3565 | case BUILT_IN_STPNCPY: | |
3566 | case BUILT_IN_STRCAT: | |
3567 | case BUILT_IN_STRCHR: | |
3568 | case BUILT_IN_STRCMP: | |
3569 | case BUILT_IN_STRCPY: | |
3570 | case BUILT_IN_STRCSPN: | |
3571 | case BUILT_IN_STRLEN: | |
3572 | case BUILT_IN_STRNCAT: | |
3573 | case BUILT_IN_STRNCMP: | |
3574 | case BUILT_IN_STRNCPY: | |
3575 | case BUILT_IN_STRPBRK: | |
3576 | case BUILT_IN_STRRCHR: | |
3577 | case BUILT_IN_STRSPN: | |
3578 | case BUILT_IN_STRSTR: | |
3579 | /* Assume certain string/memory builtins always return. */ | |
3580 | return false; | |
3581 | default: | |
3582 | break; | |
3583 | } | |
3584 | } | |
3585 | } | |
3586 | ||
3587 | /* For all other calls assume that they might not always return. */ | |
3588 | return true; | |
3589 | } | |
3590 | ||
fdb1b2b1 | 3591 | /* Return true if INSN should be made dependent on the previous instruction |
3592 | group, and if all INSN's dependencies should be moved to the first | |
3593 | instruction of that group. */ | |
3594 | ||
3595 | static bool | |
71ce7f59 | 3596 | chain_to_prev_insn_p (rtx_insn *insn) |
fdb1b2b1 | 3597 | { |
fdb1b2b1 | 3598 | /* INSN forms a group with the previous instruction. */ |
3599 | if (SCHED_GROUP_P (insn)) | |
3600 | return true; | |
3601 | ||
3602 | /* If the previous instruction clobbers a register R and this one sets | |
3603 | part of R, the clobber was added specifically to help us track the | |
3604 | liveness of R. There's no point scheduling the clobber and leaving | |
3605 | INSN behind, especially if we move the clobber to another block. */ | |
9ed997be | 3606 | rtx_insn *prev = prev_nonnote_nondebug_insn (insn); |
fdb1b2b1 | 3607 | if (prev |
3608 | && INSN_P (prev) | |
3609 | && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn) | |
3610 | && GET_CODE (PATTERN (prev)) == CLOBBER) | |
3611 | { | |
9ed997be | 3612 | rtx x = XEXP (PATTERN (prev), 0); |
fdb1b2b1 | 3613 | if (set_of (x, insn)) |
3614 | return true; | |
3615 | } | |
3616 | ||
3617 | return false; | |
3618 | } | |
3619 | ||
e1ab7874 | 3620 | /* Analyze INSN with DEPS as a context. */ |
6adce0fb | 3621 | void |
b24ef467 | 3622 | deps_analyze_insn (struct deps_desc *deps, rtx_insn *insn) |
6adce0fb | 3623 | { |
e1ab7874 | 3624 | if (sched_deps_info->start_insn) |
3625 | sched_deps_info->start_insn (insn); | |
6adce0fb | 3626 | |
6c2d9e41 | 3627 | /* Record the condition for this insn. */ |
3628 | if (NONDEBUG_INSN_P (insn)) | |
effd1640 | 3629 | { |
3630 | rtx t; | |
3631 | sched_get_condition_with_rev (insn, NULL); | |
3632 | t = INSN_CACHED_COND (insn); | |
54267fdf | 3633 | INSN_COND_DEPS (insn) = NULL; |
effd1640 | 3634 | if (reload_completed |
3635 | && (current_sched_info->flags & DO_PREDICATION) | |
3636 | && COMPARISON_P (t) | |
3637 | && REG_P (XEXP (t, 0)) | |
3638 | && CONSTANT_P (XEXP (t, 1))) | |
3639 | { | |
3640 | unsigned int regno; | |
3641 | int nregs; | |
54267fdf | 3642 | rtx_insn_list *cond_deps = NULL; |
effd1640 | 3643 | t = XEXP (t, 0); |
3644 | regno = REGNO (t); | |
0933f1d9 | 3645 | nregs = REG_NREGS (t); |
effd1640 | 3646 | while (nregs-- > 0) |
3647 | { | |
3648 | struct deps_reg *reg_last = &deps->reg_last[regno + nregs]; | |
54267fdf | 3649 | cond_deps = concat_INSN_LIST (reg_last->sets, cond_deps); |
3650 | cond_deps = concat_INSN_LIST (reg_last->clobbers, cond_deps); | |
3651 | cond_deps = concat_INSN_LIST (reg_last->implicit_sets, cond_deps); | |
effd1640 | 3652 | } |
54267fdf | 3653 | INSN_COND_DEPS (insn) = cond_deps; |
effd1640 | 3654 | } |
3655 | } | |
6c2d9e41 | 3656 | |
0741df1e | 3657 | if (JUMP_P (insn)) |
e1ab7874 | 3658 | { |
48e1416a | 3659 | /* Make each JUMP_INSN (but not a speculative check) |
e1ab7874 | 3660 | a scheduling barrier for memory references. */ |
3661 | if (!deps->readonly | |
48e1416a | 3662 | && !(sel_sched_p () |
e1ab7874 | 3663 | && sel_insn_is_speculation_check (insn))) |
3664 | { | |
3665 | /* Keep the list a reasonable size. */ | |
1deb811a | 3666 | if (deps->pending_flush_length++ >= MAX_PENDING_LIST_LENGTH) |
e1ab7874 | 3667 | flush_pending_lists (deps, insn, true, true); |
3668 | else | |
effd1640 | 3669 | deps->pending_jump_insns |
3670 | = alloc_INSN_LIST (insn, deps->pending_jump_insns); | |
e1ab7874 | 3671 | } |
3672 | ||
0741df1e | 3673 | /* For each insn which shouldn't cross a jump, add a dependence. */ |
3674 | add_dependence_list_and_free (deps, insn, | |
3675 | &deps->sched_before_next_jump, 1, | |
d452a169 | 3676 | REG_DEP_ANTI, true); |
0741df1e | 3677 | |
3678 | sched_analyze_insn (deps, PATTERN (insn), insn); | |
3679 | } | |
3680 | else if (NONJUMP_INSN_P (insn) || DEBUG_INSN_P (insn)) | |
3681 | { | |
e1ab7874 | 3682 | sched_analyze_insn (deps, PATTERN (insn), insn); |
3683 | } | |
3684 | else if (CALL_P (insn)) | |
3685 | { | |
3686 | int i; | |
3687 | ||
3688 | CANT_MOVE (insn) = 1; | |
3689 | ||
3690 | if (find_reg_note (insn, REG_SETJMP, NULL)) | |
3691 | { | |
3692 | /* This is setjmp. Assume that all registers, not just | |
3693 | hard registers, may be clobbered by this call. */ | |
3694 | reg_pending_barrier = MOVE_BARRIER; | |
3695 | } | |
3696 | else | |
3697 | { | |
3698 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3699 | /* A call may read and modify global register variables. */ | |
3700 | if (global_regs[i]) | |
3701 | { | |
3702 | SET_REGNO_REG_SET (reg_pending_sets, i); | |
a7dcf969 | 3703 | SET_HARD_REG_BIT (implicit_reg_pending_uses, i); |
e1ab7874 | 3704 | } |
3705 | /* Other call-clobbered hard regs may be clobbered. | |
3706 | Since we only have a choice between 'might be clobbered' | |
3707 | and 'definitely not clobbered', we must include all | |
3708 | partly call-clobbered registers here. */ | |
5da94e60 | 3709 | else if (targetm.hard_regno_call_part_clobbered (i, |
3710 | reg_raw_mode[i]) | |
e1ab7874 | 3711 | || TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) |
3712 | SET_REGNO_REG_SET (reg_pending_clobbers, i); | |
3713 | /* We don't know what set of fixed registers might be used | |
3714 | by the function, but it is certain that the stack pointer | |
3715 | is among them, but be conservative. */ | |
3716 | else if (fixed_regs[i]) | |
a7dcf969 | 3717 | SET_HARD_REG_BIT (implicit_reg_pending_uses, i); |
e1ab7874 | 3718 | /* The frame pointer is normally not used by the function |
3719 | itself, but by the debugger. */ | |
3720 | /* ??? MIPS o32 is an exception. It uses the frame pointer | |
3721 | in the macro expansion of jal but does not represent this | |
3722 | fact in the call_insn rtl. */ | |
3723 | else if (i == FRAME_POINTER_REGNUM | |
3724 | || (i == HARD_FRAME_POINTER_REGNUM | |
3725 | && (! reload_completed || frame_pointer_needed))) | |
a7dcf969 | 3726 | SET_HARD_REG_BIT (implicit_reg_pending_uses, i); |
e1ab7874 | 3727 | } |
3728 | ||
3729 | /* For each insn which shouldn't cross a call, add a dependence | |
3730 | between that insn and this call insn. */ | |
48e1416a | 3731 | add_dependence_list_and_free (deps, insn, |
e1ab7874 | 3732 | &deps->sched_before_next_call, 1, |
d452a169 | 3733 | REG_DEP_ANTI, true); |
e1ab7874 | 3734 | |
3735 | sched_analyze_insn (deps, PATTERN (insn), insn); | |
3736 | ||
3737 | /* If CALL would be in a sched group, then this will violate | |
3738 | convention that sched group insns have dependencies only on the | |
3739 | previous instruction. | |
3740 | ||
3741 | Of course one can say: "Hey! What about head of the sched group?" | |
3742 | And I will answer: "Basic principles (one dep per insn) are always | |
3743 | the same." */ | |
3744 | gcc_assert (!SCHED_GROUP_P (insn)); | |
3745 | ||
3746 | /* In the absence of interprocedural alias analysis, we must flush | |
3747 | all pending reads and writes, and start new dependencies starting | |
3748 | from here. But only flush writes for constant calls (which may | |
3749 | be passed a pointer to something we haven't written yet). */ | |
3750 | flush_pending_lists (deps, insn, true, ! RTL_CONST_OR_PURE_CALL_P (insn)); | |
3751 | ||
3752 | if (!deps->readonly) | |
3753 | { | |
3754 | /* Remember the last function call for limiting lifetimes. */ | |
3755 | free_INSN_LIST_list (&deps->last_function_call); | |
3756 | deps->last_function_call = alloc_INSN_LIST (insn, NULL_RTX); | |
326d0c19 | 3757 | |
3758 | if (call_may_noreturn_p (insn)) | |
3759 | { | |
3760 | /* Remember the last function call that might not always return | |
3761 | normally for limiting moves of trapping insns. */ | |
3762 | free_INSN_LIST_list (&deps->last_function_call_may_noreturn); | |
3763 | deps->last_function_call_may_noreturn | |
3764 | = alloc_INSN_LIST (insn, NULL_RTX); | |
3765 | } | |
3766 | ||
e1ab7874 | 3767 | /* Before reload, begin a post-call group, so as to keep the |
3768 | lifetimes of hard registers correct. */ | |
3769 | if (! reload_completed) | |
3770 | deps->in_post_call_group_p = post_call; | |
3771 | } | |
3772 | } | |
3773 | ||
3774 | if (sched_deps_info->use_cselib) | |
3775 | cselib_process_insn (insn); | |
3776 | ||
e1ab7874 | 3777 | if (sched_deps_info->finish_insn) |
3778 | sched_deps_info->finish_insn (); | |
3779 | ||
3780 | /* Fixup the dependencies in the sched group. */ | |
48e1416a | 3781 | if ((NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
fdb1b2b1 | 3782 | && chain_to_prev_insn_p (insn) |
3783 | && !sel_sched_p ()) | |
3784 | chain_to_prev_insn (insn); | |
e1ab7874 | 3785 | } |
3786 | ||
3787 | /* Initialize DEPS for the new block beginning with HEAD. */ | |
3788 | void | |
e55e25f6 | 3789 | deps_start_bb (struct deps_desc *deps, rtx_insn *head) |
e1ab7874 | 3790 | { |
3791 | gcc_assert (!deps->readonly); | |
503f2817 | 3792 | |
865b3698 | 3793 | /* Before reload, if the previous block ended in a call, show that |
3794 | we are inside a post-call group, so as to keep the lifetimes of | |
3795 | hard registers correct. */ | |
6d7dc5b9 | 3796 | if (! reload_completed && !LABEL_P (head)) |
865b3698 | 3797 | { |
e55e25f6 | 3798 | rtx_insn *insn = prev_nonnote_nondebug_insn (head); |
e1ab7874 | 3799 | |
6d7dc5b9 | 3800 | if (insn && CALL_P (insn)) |
865b3698 | 3801 | deps->in_post_call_group_p = post_call_initial; |
3802 | } | |
e1ab7874 | 3803 | } |
3804 | ||
3805 | /* Analyze every insn between HEAD and TAIL inclusive, creating backward | |
3806 | dependencies for each insn. */ | |
3807 | void | |
b24ef467 | 3808 | sched_analyze (struct deps_desc *deps, rtx_insn *head, rtx_insn *tail) |
e1ab7874 | 3809 | { |
b24ef467 | 3810 | rtx_insn *insn; |
e1ab7874 | 3811 | |
3812 | if (sched_deps_info->use_cselib) | |
35af0188 | 3813 | cselib_init (CSELIB_RECORD_MEMORY); |
e1ab7874 | 3814 | |
3815 | deps_start_bb (deps, head); | |
3816 | ||
6adce0fb | 3817 | for (insn = head;; insn = NEXT_INSN (insn)) |
3818 | { | |
e1ab7874 | 3819 | |
9997bd27 | 3820 | if (INSN_P (insn)) |
6adce0fb | 3821 | { |
93f6b030 | 3822 | /* And initialize deps_lists. */ |
3823 | sd_init_insn (insn); | |
55e7138c | 3824 | /* Clean up SCHED_GROUP_P which may be set by last |
3825 | scheduler pass. */ | |
3826 | if (SCHED_GROUP_P (insn)) | |
3827 | SCHED_GROUP_P (insn) = 0; | |
9997bd27 | 3828 | } |
3829 | ||
e1ab7874 | 3830 | deps_analyze_insn (deps, insn); |
37cde9fb | 3831 | |
6adce0fb | 3832 | if (insn == tail) |
503f2817 | 3833 | { |
e1ab7874 | 3834 | if (sched_deps_info->use_cselib) |
503f2817 | 3835 | cselib_finish (); |
3836 | return; | |
3837 | } | |
6adce0fb | 3838 | } |
04e579b6 | 3839 | gcc_unreachable (); |
6adce0fb | 3840 | } |
9b7c6f02 | 3841 | |
93f6b030 | 3842 | /* Helper for sched_free_deps (). |
3843 | Delete INSN's (RESOLVED_P) backward dependencies. */ | |
3844 | static void | |
71ce7f59 | 3845 | delete_dep_nodes_in_back_deps (rtx_insn *insn, bool resolved_p) |
9b7c6f02 | 3846 | { |
93f6b030 | 3847 | sd_iterator_def sd_it; |
3848 | dep_t dep; | |
3849 | sd_list_types_def types; | |
9b7c6f02 | 3850 | |
93f6b030 | 3851 | if (resolved_p) |
3852 | types = SD_LIST_RES_BACK; | |
3853 | else | |
3854 | types = SD_LIST_BACK; | |
3855 | ||
3856 | for (sd_it = sd_iterator_start (insn, types); | |
3857 | sd_iterator_cond (&sd_it, &dep);) | |
4d64d9a4 | 3858 | { |
93f6b030 | 3859 | dep_link_t link = *sd_it.linkp; |
3860 | dep_node_t node = DEP_LINK_NODE (link); | |
3861 | deps_list_t back_list; | |
3862 | deps_list_t forw_list; | |
3863 | ||
3864 | get_back_and_forw_lists (dep, resolved_p, &back_list, &forw_list); | |
3865 | remove_from_deps_list (link, back_list); | |
3866 | delete_dep_node (node); | |
4d64d9a4 | 3867 | } |
9b7c6f02 | 3868 | } |
3869 | ||
93f6b030 | 3870 | /* Delete (RESOLVED_P) dependencies between HEAD and TAIL together with |
3871 | deps_lists. */ | |
6adce0fb | 3872 | void |
4cd001d5 | 3873 | sched_free_deps (rtx_insn *head, rtx_insn *tail, bool resolved_p) |
6adce0fb | 3874 | { |
4cd001d5 | 3875 | rtx_insn *insn; |
3876 | rtx_insn *next_tail = NEXT_INSN (tail); | |
6adce0fb | 3877 | |
2261c559 | 3878 | /* We make two passes since some insns may be scheduled before their |
3879 | dependencies are resolved. */ | |
6adce0fb | 3880 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) |
93f6b030 | 3881 | if (INSN_P (insn) && INSN_LUID (insn) > 0) |
3882 | { | |
93f6b030 | 3883 | /* Clear forward deps and leave the dep_nodes to the |
3884 | corresponding back_deps list. */ | |
3885 | if (resolved_p) | |
3886 | clear_deps_list (INSN_RESOLVED_FORW_DEPS (insn)); | |
3887 | else | |
3888 | clear_deps_list (INSN_FORW_DEPS (insn)); | |
2261c559 | 3889 | } |
3890 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
3891 | if (INSN_P (insn) && INSN_LUID (insn) > 0) | |
3892 | { | |
3893 | /* Clear resolved back deps together with its dep_nodes. */ | |
3894 | delete_dep_nodes_in_back_deps (insn, resolved_p); | |
6adce0fb | 3895 | |
93f6b030 | 3896 | sd_finish_insn (insn); |
3897 | } | |
6adce0fb | 3898 | } |
3899 | \f | |
3900 | /* Initialize variables for region data dependence analysis. | |
48e1416a | 3901 | When LAZY_REG_LAST is true, do not allocate reg_last array |
68e419a1 | 3902 | of struct deps_desc immediately. */ |
6adce0fb | 3903 | |
3904 | void | |
68e419a1 | 3905 | init_deps (struct deps_desc *deps, bool lazy_reg_last) |
6adce0fb | 3906 | { |
749c6f58 | 3907 | int max_reg = (reload_completed ? FIRST_PSEUDO_REGISTER : max_reg_num ()); |
3908 | ||
3909 | deps->max_reg = max_reg; | |
d9ab2038 | 3910 | if (lazy_reg_last) |
3911 | deps->reg_last = NULL; | |
3912 | else | |
3913 | deps->reg_last = XCNEWVEC (struct deps_reg, max_reg); | |
749c6f58 | 3914 | INIT_REG_SET (&deps->reg_last_in_use); |
6adce0fb | 3915 | |
3916 | deps->pending_read_insns = 0; | |
3917 | deps->pending_read_mems = 0; | |
3918 | deps->pending_write_insns = 0; | |
3919 | deps->pending_write_mems = 0; | |
effd1640 | 3920 | deps->pending_jump_insns = 0; |
c5947ab7 | 3921 | deps->pending_read_list_length = 0; |
3922 | deps->pending_write_list_length = 0; | |
85de291e | 3923 | deps->pending_flush_length = 0; |
6adce0fb | 3924 | deps->last_pending_memory_flush = 0; |
3925 | deps->last_function_call = 0; | |
326d0c19 | 3926 | deps->last_function_call_may_noreturn = 0; |
5deaeb50 | 3927 | deps->sched_before_next_call = 0; |
0741df1e | 3928 | deps->sched_before_next_jump = 0; |
865b3698 | 3929 | deps->in_post_call_group_p = not_post_call; |
9845d120 | 3930 | deps->last_debug_insn = 0; |
617529e8 | 3931 | deps->last_args_size = 0; |
5a321af0 | 3932 | deps->last_prologue = 0; |
3933 | deps->last_epilogue = 0; | |
3934 | deps->last_logue_was_epilogue = false; | |
e1ab7874 | 3935 | deps->last_reg_pending_barrier = NOT_A_BARRIER; |
3936 | deps->readonly = 0; | |
6adce0fb | 3937 | } |
3938 | ||
48e1416a | 3939 | /* Init only reg_last field of DEPS, which was not allocated before as |
d9ab2038 | 3940 | we inited DEPS lazily. */ |
3941 | void | |
68e419a1 | 3942 | init_deps_reg_last (struct deps_desc *deps) |
d9ab2038 | 3943 | { |
3944 | gcc_assert (deps && deps->max_reg > 0); | |
3945 | gcc_assert (deps->reg_last == NULL); | |
3946 | ||
3947 | deps->reg_last = XCNEWVEC (struct deps_reg, deps->max_reg); | |
3948 | } | |
3949 | ||
3950 | ||
6adce0fb | 3951 | /* Free insn lists found in DEPS. */ |
3952 | ||
3953 | void | |
68e419a1 | 3954 | free_deps (struct deps_desc *deps) |
6adce0fb | 3955 | { |
4f917ffe | 3956 | unsigned i; |
8c97cf13 | 3957 | reg_set_iterator rsi; |
6adce0fb | 3958 | |
d9ab2038 | 3959 | /* We set max_reg to 0 when this context was already freed. */ |
3960 | if (deps->max_reg == 0) | |
3961 | { | |
3962 | gcc_assert (deps->reg_last == NULL); | |
3963 | return; | |
3964 | } | |
3965 | deps->max_reg = 0; | |
48e1416a | 3966 | |
5deaeb50 | 3967 | free_INSN_LIST_list (&deps->pending_read_insns); |
3968 | free_EXPR_LIST_list (&deps->pending_read_mems); | |
3969 | free_INSN_LIST_list (&deps->pending_write_insns); | |
3970 | free_EXPR_LIST_list (&deps->pending_write_mems); | |
3971 | free_INSN_LIST_list (&deps->last_pending_memory_flush); | |
3972 | ||
749c6f58 | 3973 | /* Without the EXECUTE_IF_SET, this loop is executed max_reg * nr_regions |
de44dcb9 | 3974 | times. For a testcase with 42000 regs and 8000 small basic blocks, |
749c6f58 | 3975 | this loop accounted for nearly 60% (84 sec) of the total -O2 runtime. */ |
8c97cf13 | 3976 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
6adce0fb | 3977 | { |
749c6f58 | 3978 | struct deps_reg *reg_last = &deps->reg_last[i]; |
b479b8be | 3979 | if (reg_last->uses) |
3980 | free_INSN_LIST_list (®_last->uses); | |
3981 | if (reg_last->sets) | |
3982 | free_INSN_LIST_list (®_last->sets); | |
a7dcf969 | 3983 | if (reg_last->implicit_sets) |
3984 | free_INSN_LIST_list (®_last->implicit_sets); | |
effd1640 | 3985 | if (reg_last->control_uses) |
3986 | free_INSN_LIST_list (®_last->control_uses); | |
b479b8be | 3987 | if (reg_last->clobbers) |
3988 | free_INSN_LIST_list (®_last->clobbers); | |
8c97cf13 | 3989 | } |
749c6f58 | 3990 | CLEAR_REG_SET (&deps->reg_last_in_use); |
3991 | ||
48e1416a | 3992 | /* As we initialize reg_last lazily, it is possible that we didn't allocate |
d9ab2038 | 3993 | it at all. */ |
dd045aee | 3994 | free (deps->reg_last); |
e1ab7874 | 3995 | deps->reg_last = NULL; |
3996 | ||
3997 | deps = NULL; | |
6adce0fb | 3998 | } |
3999 | ||
6aed13f1 | 4000 | /* Remove INSN from dependence contexts DEPS. */ |
e1ab7874 | 4001 | void |
54267fdf | 4002 | remove_from_deps (struct deps_desc *deps, rtx_insn *insn) |
e1ab7874 | 4003 | { |
4004 | int removed; | |
4005 | unsigned i; | |
4006 | reg_set_iterator rsi; | |
48e1416a | 4007 | |
e1ab7874 | 4008 | removed = remove_from_both_dependence_lists (insn, &deps->pending_read_insns, |
4009 | &deps->pending_read_mems); | |
c971b445 | 4010 | if (!DEBUG_INSN_P (insn)) |
4011 | deps->pending_read_list_length -= removed; | |
e1ab7874 | 4012 | removed = remove_from_both_dependence_lists (insn, &deps->pending_write_insns, |
4013 | &deps->pending_write_mems); | |
4014 | deps->pending_write_list_length -= removed; | |
effd1640 | 4015 | |
4016 | removed = remove_from_dependence_list (insn, &deps->pending_jump_insns); | |
4017 | deps->pending_flush_length -= removed; | |
e1ab7874 | 4018 | removed = remove_from_dependence_list (insn, &deps->last_pending_memory_flush); |
4019 | deps->pending_flush_length -= removed; | |
6adce0fb | 4020 | |
f79643b7 | 4021 | unsigned to_clear = -1U; |
e1ab7874 | 4022 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
4023 | { | |
f79643b7 | 4024 | if (to_clear != -1U) |
4025 | { | |
4026 | CLEAR_REGNO_REG_SET (&deps->reg_last_in_use, to_clear); | |
4027 | to_clear = -1U; | |
4028 | } | |
e1ab7874 | 4029 | struct deps_reg *reg_last = &deps->reg_last[i]; |
4030 | if (reg_last->uses) | |
4031 | remove_from_dependence_list (insn, ®_last->uses); | |
4032 | if (reg_last->sets) | |
4033 | remove_from_dependence_list (insn, ®_last->sets); | |
a7dcf969 | 4034 | if (reg_last->implicit_sets) |
4035 | remove_from_dependence_list (insn, ®_last->implicit_sets); | |
e1ab7874 | 4036 | if (reg_last->clobbers) |
4037 | remove_from_dependence_list (insn, ®_last->clobbers); | |
a7dcf969 | 4038 | if (!reg_last->uses && !reg_last->sets && !reg_last->implicit_sets |
4039 | && !reg_last->clobbers) | |
f79643b7 | 4040 | to_clear = i; |
e1ab7874 | 4041 | } |
f79643b7 | 4042 | if (to_clear != -1U) |
4043 | CLEAR_REGNO_REG_SET (&deps->reg_last_in_use, to_clear); | |
e1ab7874 | 4044 | |
4045 | if (CALL_P (insn)) | |
326d0c19 | 4046 | { |
4047 | remove_from_dependence_list (insn, &deps->last_function_call); | |
48e1416a | 4048 | remove_from_dependence_list (insn, |
326d0c19 | 4049 | &deps->last_function_call_may_noreturn); |
4050 | } | |
e1ab7874 | 4051 | remove_from_dependence_list (insn, &deps->sched_before_next_call); |
4052 | } | |
4053 | ||
4054 | /* Init deps data vector. */ | |
4055 | static void | |
4056 | init_deps_data_vector (void) | |
4057 | { | |
f1f41a6c | 4058 | int reserve = (sched_max_luid + 1 - h_d_i_d.length ()); |
4059 | if (reserve > 0 && ! h_d_i_d.space (reserve)) | |
4060 | h_d_i_d.safe_grow_cleared (3 * sched_max_luid / 2); | |
e1ab7874 | 4061 | } |
4062 | ||
4063 | /* If it is profitable to use them, initialize or extend (depending on | |
4064 | GLOBAL_P) dependency data. */ | |
6adce0fb | 4065 | void |
e1ab7874 | 4066 | sched_deps_init (bool global_p) |
6adce0fb | 4067 | { |
93f6b030 | 4068 | /* Average number of insns in the basic block. |
4069 | '+ 1' is used to make it nonzero. */ | |
a28770e1 | 4070 | int insns_in_block = sched_max_luid / n_basic_blocks_for_fn (cfun) + 1; |
93f6b030 | 4071 | |
e1ab7874 | 4072 | init_deps_data_vector (); |
48e1416a | 4073 | |
4074 | /* We use another caching mechanism for selective scheduling, so | |
e1ab7874 | 4075 | we don't use this one. */ |
4076 | if (!sel_sched_p () && global_p && insns_in_block > 100 * 5) | |
4077 | { | |
4078 | /* ?!? We could save some memory by computing a per-region luid mapping | |
4079 | which could reduce both the number of vectors in the cache and the | |
4080 | size of each vector. Instead we just avoid the cache entirely unless | |
4081 | the average number of instructions in a basic block is very high. See | |
4082 | the comment before the declaration of true_dependency_cache for | |
4083 | what we consider "very high". */ | |
6a1cdb4d | 4084 | cache_size = 0; |
e1ab7874 | 4085 | extend_dependency_caches (sched_max_luid, true); |
6a1cdb4d | 4086 | } |
9997bd27 | 4087 | |
48e1416a | 4088 | if (global_p) |
e1ab7874 | 4089 | { |
1dc6c44d | 4090 | dl_pool = new object_allocator<_deps_list> ("deps_list"); |
4091 | /* Allocate lists for one block at a time. */ | |
4092 | dn_pool = new object_allocator<_dep_node> ("dep_node"); | |
4093 | /* Allocate nodes for one block at a time. */ | |
e1ab7874 | 4094 | } |
6a1cdb4d | 4095 | } |
4d64d9a4 | 4096 | |
e1ab7874 | 4097 | |
6a1cdb4d | 4098 | /* Create or extend (depending on CREATE_P) dependency caches to |
4099 | size N. */ | |
4100 | void | |
4101 | extend_dependency_caches (int n, bool create_p) | |
4102 | { | |
4103 | if (create_p || true_dependency_cache) | |
4104 | { | |
4105 | int i, luid = cache_size + n; | |
4106 | ||
4107 | true_dependency_cache = XRESIZEVEC (bitmap_head, true_dependency_cache, | |
4108 | luid); | |
4109 | output_dependency_cache = XRESIZEVEC (bitmap_head, | |
4110 | output_dependency_cache, luid); | |
4111 | anti_dependency_cache = XRESIZEVEC (bitmap_head, anti_dependency_cache, | |
4112 | luid); | |
effd1640 | 4113 | control_dependency_cache = XRESIZEVEC (bitmap_head, control_dependency_cache, |
4114 | luid); | |
93f6b030 | 4115 | |
4d64d9a4 | 4116 | if (current_sched_info->flags & DO_SPECULATION) |
4117 | spec_dependency_cache = XRESIZEVEC (bitmap_head, spec_dependency_cache, | |
4118 | luid); | |
4119 | ||
6a1cdb4d | 4120 | for (i = cache_size; i < luid; i++) |
d4f68afb | 4121 | { |
4122 | bitmap_initialize (&true_dependency_cache[i], 0); | |
d4f68afb | 4123 | bitmap_initialize (&output_dependency_cache[i], 0); |
4d64d9a4 | 4124 | bitmap_initialize (&anti_dependency_cache[i], 0); |
effd1640 | 4125 | bitmap_initialize (&control_dependency_cache[i], 0); |
93f6b030 | 4126 | |
4d64d9a4 | 4127 | if (current_sched_info->flags & DO_SPECULATION) |
4128 | bitmap_initialize (&spec_dependency_cache[i], 0); | |
d4f68afb | 4129 | } |
4130 | cache_size = luid; | |
6adce0fb | 4131 | } |
4132 | } | |
4133 | ||
e1ab7874 | 4134 | /* Finalize dependency information for the whole function. */ |
6adce0fb | 4135 | void |
e1ab7874 | 4136 | sched_deps_finish (void) |
6adce0fb | 4137 | { |
93f6b030 | 4138 | gcc_assert (deps_pools_are_empty_p ()); |
c45ca67d | 4139 | delete dn_pool; |
4140 | delete dl_pool; | |
3da86c6b | 4141 | dn_pool = NULL; |
3da86c6b | 4142 | dl_pool = NULL; |
9997bd27 | 4143 | |
f1f41a6c | 4144 | h_d_i_d.release (); |
e1ab7874 | 4145 | cache_size = 0; |
48e1416a | 4146 | |
6adce0fb | 4147 | if (true_dependency_cache) |
4148 | { | |
d4f68afb | 4149 | int i; |
4150 | ||
4151 | for (i = 0; i < cache_size; i++) | |
4152 | { | |
4153 | bitmap_clear (&true_dependency_cache[i]); | |
d4f68afb | 4154 | bitmap_clear (&output_dependency_cache[i]); |
4d64d9a4 | 4155 | bitmap_clear (&anti_dependency_cache[i]); |
effd1640 | 4156 | bitmap_clear (&control_dependency_cache[i]); |
93f6b030 | 4157 | |
e1ab7874 | 4158 | if (sched_deps_info->generate_spec_deps) |
4d64d9a4 | 4159 | bitmap_clear (&spec_dependency_cache[i]); |
d4f68afb | 4160 | } |
4161 | free (true_dependency_cache); | |
6adce0fb | 4162 | true_dependency_cache = NULL; |
d4f68afb | 4163 | free (output_dependency_cache); |
6adce0fb | 4164 | output_dependency_cache = NULL; |
4d64d9a4 | 4165 | free (anti_dependency_cache); |
4166 | anti_dependency_cache = NULL; | |
effd1640 | 4167 | free (control_dependency_cache); |
4168 | control_dependency_cache = NULL; | |
93f6b030 | 4169 | |
e1ab7874 | 4170 | if (sched_deps_info->generate_spec_deps) |
4d64d9a4 | 4171 | { |
4172 | free (spec_dependency_cache); | |
4173 | spec_dependency_cache = NULL; | |
4174 | } | |
e1ab7874 | 4175 | |
6adce0fb | 4176 | } |
4177 | } | |
4178 | ||
4179 | /* Initialize some global variables needed by the dependency analysis | |
4180 | code. */ | |
4181 | ||
4182 | void | |
60b8c5b3 | 4183 | init_deps_global (void) |
6adce0fb | 4184 | { |
a7dcf969 | 4185 | CLEAR_HARD_REG_SET (implicit_reg_pending_clobbers); |
4186 | CLEAR_HARD_REG_SET (implicit_reg_pending_uses); | |
ae85a37a | 4187 | reg_pending_sets = ALLOC_REG_SET (®_obstack); |
4188 | reg_pending_clobbers = ALLOC_REG_SET (®_obstack); | |
4189 | reg_pending_uses = ALLOC_REG_SET (®_obstack); | |
effd1640 | 4190 | reg_pending_control_uses = ALLOC_REG_SET (®_obstack); |
c14a239f | 4191 | reg_pending_barrier = NOT_A_BARRIER; |
e1ab7874 | 4192 | |
4193 | if (!sel_sched_p () || sched_emulate_haifa_p) | |
4194 | { | |
4195 | sched_deps_info->start_insn = haifa_start_insn; | |
4196 | sched_deps_info->finish_insn = haifa_finish_insn; | |
4197 | ||
4198 | sched_deps_info->note_reg_set = haifa_note_reg_set; | |
4199 | sched_deps_info->note_reg_clobber = haifa_note_reg_clobber; | |
4200 | sched_deps_info->note_reg_use = haifa_note_reg_use; | |
4201 | ||
4202 | sched_deps_info->note_mem_dep = haifa_note_mem_dep; | |
4203 | sched_deps_info->note_dep = haifa_note_dep; | |
4204 | } | |
6adce0fb | 4205 | } |
4206 | ||
4207 | /* Free everything used by the dependency analysis code. */ | |
4208 | ||
4209 | void | |
60b8c5b3 | 4210 | finish_deps_global (void) |
6adce0fb | 4211 | { |
4212 | FREE_REG_SET (reg_pending_sets); | |
4213 | FREE_REG_SET (reg_pending_clobbers); | |
5deaeb50 | 4214 | FREE_REG_SET (reg_pending_uses); |
effd1640 | 4215 | FREE_REG_SET (reg_pending_control_uses); |
6adce0fb | 4216 | } |
4d64d9a4 | 4217 | |
4d64d9a4 | 4218 | /* Estimate the weakness of dependence between MEM1 and MEM2. */ |
e1ab7874 | 4219 | dw_t |
4d64d9a4 | 4220 | estimate_dep_weak (rtx mem1, rtx mem2) |
4221 | { | |
4d64d9a4 | 4222 | if (mem1 == mem2) |
4223 | /* MEMs are the same - don't speculate. */ | |
4224 | return MIN_DEP_WEAK; | |
4225 | ||
56d8dd53 | 4226 | rtx r1 = XEXP (mem1, 0); |
4227 | rtx r2 = XEXP (mem2, 0); | |
4228 | ||
4229 | if (sched_deps_info->use_cselib) | |
4230 | { | |
4231 | /* We cannot call rtx_equal_for_cselib_p because the VALUEs might be | |
4232 | dangling at this point, since we never preserve them. Instead we | |
4233 | canonicalize manually to get stable VALUEs out of hashing. */ | |
4234 | if (GET_CODE (r1) == VALUE && CSELIB_VAL_PTR (r1)) | |
4235 | r1 = canonical_cselib_val (CSELIB_VAL_PTR (r1))->val_rtx; | |
4236 | if (GET_CODE (r2) == VALUE && CSELIB_VAL_PTR (r2)) | |
4237 | r2 = canonical_cselib_val (CSELIB_VAL_PTR (r2))->val_rtx; | |
4238 | } | |
4d64d9a4 | 4239 | |
4240 | if (r1 == r2 | |
56d8dd53 | 4241 | || (REG_P (r1) && REG_P (r2) && REGNO (r1) == REGNO (r2))) |
4d64d9a4 | 4242 | /* Again, MEMs are the same. */ |
4243 | return MIN_DEP_WEAK; | |
56d8dd53 | 4244 | else if ((REG_P (r1) && !REG_P (r2)) || (!REG_P (r1) && REG_P (r2))) |
4d64d9a4 | 4245 | /* Different addressing modes - reason to be more speculative, |
4246 | than usual. */ | |
4247 | return NO_DEP_WEAK - (NO_DEP_WEAK - UNCERTAIN_DEP_WEAK) / 2; | |
4248 | else | |
4249 | /* We can't say anything about the dependence. */ | |
4250 | return UNCERTAIN_DEP_WEAK; | |
4251 | } | |
4252 | ||
4253 | /* Add or update backward dependence between INSN and ELEM with type DEP_TYPE. | |
4254 | This function can handle same INSN and ELEM (INSN == ELEM). | |
4255 | It is a convenience wrapper. */ | |
effd1640 | 4256 | static void |
b24ef467 | 4257 | add_dependence_1 (rtx_insn *insn, rtx_insn *elem, enum reg_note dep_type) |
4d64d9a4 | 4258 | { |
e1ab7874 | 4259 | ds_t ds; |
4260 | bool internal; | |
4d64d9a4 | 4261 | |
e1ab7874 | 4262 | if (dep_type == REG_DEP_TRUE) |
4263 | ds = DEP_TRUE; | |
4264 | else if (dep_type == REG_DEP_OUTPUT) | |
4265 | ds = DEP_OUTPUT; | |
effd1640 | 4266 | else if (dep_type == REG_DEP_CONTROL) |
4267 | ds = DEP_CONTROL; | |
e1ab7874 | 4268 | else |
4269 | { | |
4270 | gcc_assert (dep_type == REG_DEP_ANTI); | |
4271 | ds = DEP_ANTI; | |
4272 | } | |
4273 | ||
4274 | /* When add_dependence is called from inside sched-deps.c, we expect | |
4275 | cur_insn to be non-null. */ | |
4276 | internal = cur_insn != NULL; | |
4277 | if (internal) | |
4278 | gcc_assert (insn == cur_insn); | |
4279 | else | |
4280 | cur_insn = insn; | |
48e1416a | 4281 | |
e1ab7874 | 4282 | note_dep (elem, ds); |
4283 | if (!internal) | |
4284 | cur_insn = NULL; | |
4d64d9a4 | 4285 | } |
4286 | ||
242d1ee6 | 4287 | /* Return weakness of speculative type TYPE in the dep_status DS, |
4288 | without checking to prevent ICEs on malformed input. */ | |
4289 | static dw_t | |
93f6b030 | 4290 | get_dep_weak_1 (ds_t ds, ds_t type) |
4d64d9a4 | 4291 | { |
4292 | ds = ds & type; | |
e1ab7874 | 4293 | |
4d64d9a4 | 4294 | switch (type) |
4295 | { | |
4296 | case BEGIN_DATA: ds >>= BEGIN_DATA_BITS_OFFSET; break; | |
4297 | case BE_IN_DATA: ds >>= BE_IN_DATA_BITS_OFFSET; break; | |
4298 | case BEGIN_CONTROL: ds >>= BEGIN_CONTROL_BITS_OFFSET; break; | |
4299 | case BE_IN_CONTROL: ds >>= BE_IN_CONTROL_BITS_OFFSET; break; | |
4300 | default: gcc_unreachable (); | |
4301 | } | |
4302 | ||
4d64d9a4 | 4303 | return (dw_t) ds; |
4304 | } | |
4305 | ||
242d1ee6 | 4306 | /* Return weakness of speculative type TYPE in the dep_status DS. */ |
93f6b030 | 4307 | dw_t |
4308 | get_dep_weak (ds_t ds, ds_t type) | |
4309 | { | |
4310 | dw_t dw = get_dep_weak_1 (ds, type); | |
4311 | ||
4312 | gcc_assert (MIN_DEP_WEAK <= dw && dw <= MAX_DEP_WEAK); | |
93f6b030 | 4313 | return dw; |
4314 | } | |
4315 | ||
4d64d9a4 | 4316 | /* Return the dep_status, which has the same parameters as DS, except for |
4317 | speculative type TYPE, that will have weakness DW. */ | |
4318 | ds_t | |
4319 | set_dep_weak (ds_t ds, ds_t type, dw_t dw) | |
4320 | { | |
4321 | gcc_assert (MIN_DEP_WEAK <= dw && dw <= MAX_DEP_WEAK); | |
4322 | ||
4323 | ds &= ~type; | |
4324 | switch (type) | |
4325 | { | |
4326 | case BEGIN_DATA: ds |= ((ds_t) dw) << BEGIN_DATA_BITS_OFFSET; break; | |
4327 | case BE_IN_DATA: ds |= ((ds_t) dw) << BE_IN_DATA_BITS_OFFSET; break; | |
4328 | case BEGIN_CONTROL: ds |= ((ds_t) dw) << BEGIN_CONTROL_BITS_OFFSET; break; | |
4329 | case BE_IN_CONTROL: ds |= ((ds_t) dw) << BE_IN_CONTROL_BITS_OFFSET; break; | |
4330 | default: gcc_unreachable (); | |
4331 | } | |
4332 | return ds; | |
4333 | } | |
4334 | ||
e1ab7874 | 4335 | /* Return the join of two dep_statuses DS1 and DS2. |
4336 | If MAX_P is true then choose the greater probability, | |
4337 | otherwise multiply probabilities. | |
4338 | This function assumes that both DS1 and DS2 contain speculative bits. */ | |
4339 | static ds_t | |
4340 | ds_merge_1 (ds_t ds1, ds_t ds2, bool max_p) | |
4d64d9a4 | 4341 | { |
4342 | ds_t ds, t; | |
4343 | ||
4344 | gcc_assert ((ds1 & SPECULATIVE) && (ds2 & SPECULATIVE)); | |
4345 | ||
4346 | ds = (ds1 & DEP_TYPES) | (ds2 & DEP_TYPES); | |
4347 | ||
4348 | t = FIRST_SPEC_TYPE; | |
4349 | do | |
4350 | { | |
4351 | if ((ds1 & t) && !(ds2 & t)) | |
4352 | ds |= ds1 & t; | |
4353 | else if (!(ds1 & t) && (ds2 & t)) | |
4354 | ds |= ds2 & t; | |
4355 | else if ((ds1 & t) && (ds2 & t)) | |
4356 | { | |
e1ab7874 | 4357 | dw_t dw1 = get_dep_weak (ds1, t); |
4358 | dw_t dw2 = get_dep_weak (ds2, t); | |
4d64d9a4 | 4359 | ds_t dw; |
4360 | ||
e1ab7874 | 4361 | if (!max_p) |
4362 | { | |
4363 | dw = ((ds_t) dw1) * ((ds_t) dw2); | |
4364 | dw /= MAX_DEP_WEAK; | |
4365 | if (dw < MIN_DEP_WEAK) | |
4366 | dw = MIN_DEP_WEAK; | |
4367 | } | |
4368 | else | |
4369 | { | |
4370 | if (dw1 >= dw2) | |
4371 | dw = dw1; | |
4372 | else | |
4373 | dw = dw2; | |
4374 | } | |
4d64d9a4 | 4375 | |
4376 | ds = set_dep_weak (ds, t, (dw_t) dw); | |
4377 | } | |
4378 | ||
4379 | if (t == LAST_SPEC_TYPE) | |
4380 | break; | |
4381 | t <<= SPEC_TYPE_SHIFT; | |
4382 | } | |
4383 | while (1); | |
4384 | ||
4385 | return ds; | |
4386 | } | |
4387 | ||
e1ab7874 | 4388 | /* Return the join of two dep_statuses DS1 and DS2. |
4389 | This function assumes that both DS1 and DS2 contain speculative bits. */ | |
4390 | ds_t | |
4391 | ds_merge (ds_t ds1, ds_t ds2) | |
4392 | { | |
4393 | return ds_merge_1 (ds1, ds2, false); | |
4394 | } | |
4395 | ||
4396 | /* Return the join of two dep_statuses DS1 and DS2. */ | |
4397 | ds_t | |
4398 | ds_full_merge (ds_t ds, ds_t ds2, rtx mem1, rtx mem2) | |
4399 | { | |
4400 | ds_t new_status = ds | ds2; | |
4401 | ||
4402 | if (new_status & SPECULATIVE) | |
4403 | { | |
4404 | if ((ds && !(ds & SPECULATIVE)) | |
4405 | || (ds2 && !(ds2 & SPECULATIVE))) | |
4406 | /* Then this dep can't be speculative. */ | |
4407 | new_status &= ~SPECULATIVE; | |
4408 | else | |
4409 | { | |
4410 | /* Both are speculative. Merging probabilities. */ | |
4411 | if (mem1) | |
4412 | { | |
4413 | dw_t dw; | |
4414 | ||
4415 | dw = estimate_dep_weak (mem1, mem2); | |
4416 | ds = set_dep_weak (ds, BEGIN_DATA, dw); | |
4417 | } | |
4418 | ||
4419 | if (!ds) | |
4420 | new_status = ds2; | |
4421 | else if (!ds2) | |
4422 | new_status = ds; | |
4423 | else | |
4424 | new_status = ds_merge (ds2, ds); | |
4425 | } | |
4426 | } | |
4427 | ||
4428 | return new_status; | |
4429 | } | |
4430 | ||
4431 | /* Return the join of DS1 and DS2. Use maximum instead of multiplying | |
4432 | probabilities. */ | |
4433 | ds_t | |
4434 | ds_max_merge (ds_t ds1, ds_t ds2) | |
4435 | { | |
4436 | if (ds1 == 0 && ds2 == 0) | |
4437 | return 0; | |
4438 | ||
4439 | if (ds1 == 0 && ds2 != 0) | |
4440 | return ds2; | |
4441 | ||
4442 | if (ds1 != 0 && ds2 == 0) | |
4443 | return ds1; | |
4444 | ||
4445 | return ds_merge_1 (ds1, ds2, true); | |
4446 | } | |
4447 | ||
4448 | /* Return the probability of speculation success for the speculation | |
4449 | status DS. */ | |
4450 | dw_t | |
4451 | ds_weak (ds_t ds) | |
4452 | { | |
4453 | ds_t res = 1, dt; | |
4454 | int n = 0; | |
4455 | ||
4456 | dt = FIRST_SPEC_TYPE; | |
4457 | do | |
4458 | { | |
4459 | if (ds & dt) | |
4460 | { | |
4461 | res *= (ds_t) get_dep_weak (ds, dt); | |
4462 | n++; | |
4463 | } | |
4464 | ||
4465 | if (dt == LAST_SPEC_TYPE) | |
4466 | break; | |
4467 | dt <<= SPEC_TYPE_SHIFT; | |
4468 | } | |
4469 | while (1); | |
4470 | ||
4471 | gcc_assert (n); | |
4472 | while (--n) | |
4473 | res /= MAX_DEP_WEAK; | |
4474 | ||
4475 | if (res < MIN_DEP_WEAK) | |
4476 | res = MIN_DEP_WEAK; | |
4477 | ||
4478 | gcc_assert (res <= MAX_DEP_WEAK); | |
4479 | ||
4480 | return (dw_t) res; | |
4481 | } | |
4482 | ||
4483 | /* Return a dep status that contains all speculation types of DS. */ | |
4484 | ds_t | |
4485 | ds_get_speculation_types (ds_t ds) | |
4486 | { | |
4487 | if (ds & BEGIN_DATA) | |
4488 | ds |= BEGIN_DATA; | |
4489 | if (ds & BE_IN_DATA) | |
4490 | ds |= BE_IN_DATA; | |
4491 | if (ds & BEGIN_CONTROL) | |
4492 | ds |= BEGIN_CONTROL; | |
4493 | if (ds & BE_IN_CONTROL) | |
4494 | ds |= BE_IN_CONTROL; | |
4495 | ||
4496 | return ds & SPECULATIVE; | |
4497 | } | |
4498 | ||
4499 | /* Return a dep status that contains maximal weakness for each speculation | |
4500 | type present in DS. */ | |
4501 | ds_t | |
4502 | ds_get_max_dep_weak (ds_t ds) | |
4503 | { | |
4504 | if (ds & BEGIN_DATA) | |
4505 | ds = set_dep_weak (ds, BEGIN_DATA, MAX_DEP_WEAK); | |
4506 | if (ds & BE_IN_DATA) | |
4507 | ds = set_dep_weak (ds, BE_IN_DATA, MAX_DEP_WEAK); | |
4508 | if (ds & BEGIN_CONTROL) | |
4509 | ds = set_dep_weak (ds, BEGIN_CONTROL, MAX_DEP_WEAK); | |
4510 | if (ds & BE_IN_CONTROL) | |
4511 | ds = set_dep_weak (ds, BE_IN_CONTROL, MAX_DEP_WEAK); | |
4512 | ||
4513 | return ds; | |
4514 | } | |
4515 | ||
93f6b030 | 4516 | /* Dump information about the dependence status S. */ |
4517 | static void | |
4518 | dump_ds (FILE *f, ds_t s) | |
4519 | { | |
4520 | fprintf (f, "{"); | |
4521 | ||
4522 | if (s & BEGIN_DATA) | |
4523 | fprintf (f, "BEGIN_DATA: %d; ", get_dep_weak_1 (s, BEGIN_DATA)); | |
4524 | if (s & BE_IN_DATA) | |
4525 | fprintf (f, "BE_IN_DATA: %d; ", get_dep_weak_1 (s, BE_IN_DATA)); | |
4526 | if (s & BEGIN_CONTROL) | |
4527 | fprintf (f, "BEGIN_CONTROL: %d; ", get_dep_weak_1 (s, BEGIN_CONTROL)); | |
4528 | if (s & BE_IN_CONTROL) | |
4529 | fprintf (f, "BE_IN_CONTROL: %d; ", get_dep_weak_1 (s, BE_IN_CONTROL)); | |
4530 | ||
4531 | if (s & HARD_DEP) | |
4532 | fprintf (f, "HARD_DEP; "); | |
4533 | ||
4534 | if (s & DEP_TRUE) | |
4535 | fprintf (f, "DEP_TRUE; "); | |
93f6b030 | 4536 | if (s & DEP_OUTPUT) |
4537 | fprintf (f, "DEP_OUTPUT; "); | |
effd1640 | 4538 | if (s & DEP_ANTI) |
4539 | fprintf (f, "DEP_ANTI; "); | |
4540 | if (s & DEP_CONTROL) | |
4541 | fprintf (f, "DEP_CONTROL; "); | |
93f6b030 | 4542 | |
4543 | fprintf (f, "}"); | |
4544 | } | |
4545 | ||
4b987fac | 4546 | DEBUG_FUNCTION void |
93f6b030 | 4547 | debug_ds (ds_t s) |
4548 | { | |
4549 | dump_ds (stderr, s); | |
4550 | fprintf (stderr, "\n"); | |
4551 | } | |
4552 | ||
4d64d9a4 | 4553 | /* Verify that dependence type and status are consistent. |
4554 | If RELAXED_P is true, then skip dep_weakness checks. */ | |
4555 | static void | |
93f6b030 | 4556 | check_dep (dep_t dep, bool relaxed_p) |
4d64d9a4 | 4557 | { |
93f6b030 | 4558 | enum reg_note dt = DEP_TYPE (dep); |
4559 | ds_t ds = DEP_STATUS (dep); | |
4560 | ||
4561 | gcc_assert (DEP_PRO (dep) != DEP_CON (dep)); | |
4562 | ||
4563 | if (!(current_sched_info->flags & USE_DEPS_LIST)) | |
4564 | { | |
2261c559 | 4565 | gcc_assert (ds == 0); |
93f6b030 | 4566 | return; |
4567 | } | |
4568 | ||
4d64d9a4 | 4569 | /* Check that dependence type contains the same bits as the status. */ |
4570 | if (dt == REG_DEP_TRUE) | |
4571 | gcc_assert (ds & DEP_TRUE); | |
4572 | else if (dt == REG_DEP_OUTPUT) | |
4573 | gcc_assert ((ds & DEP_OUTPUT) | |
48e1416a | 4574 | && !(ds & DEP_TRUE)); |
effd1640 | 4575 | else if (dt == REG_DEP_ANTI) |
4576 | gcc_assert ((ds & DEP_ANTI) | |
4d64d9a4 | 4577 | && !(ds & (DEP_OUTPUT | DEP_TRUE))); |
effd1640 | 4578 | else |
4579 | gcc_assert (dt == REG_DEP_CONTROL | |
4580 | && (ds & DEP_CONTROL) | |
4581 | && !(ds & (DEP_OUTPUT | DEP_ANTI | DEP_TRUE))); | |
4d64d9a4 | 4582 | |
4583 | /* HARD_DEP can not appear in dep_status of a link. */ | |
48e1416a | 4584 | gcc_assert (!(ds & HARD_DEP)); |
4d64d9a4 | 4585 | |
4586 | /* Check that dependence status is set correctly when speculation is not | |
4587 | supported. */ | |
e1ab7874 | 4588 | if (!sched_deps_info->generate_spec_deps) |
4d64d9a4 | 4589 | gcc_assert (!(ds & SPECULATIVE)); |
4590 | else if (ds & SPECULATIVE) | |
4591 | { | |
4592 | if (!relaxed_p) | |
4593 | { | |
4594 | ds_t type = FIRST_SPEC_TYPE; | |
4595 | ||
4596 | /* Check that dependence weakness is in proper range. */ | |
4597 | do | |
4598 | { | |
4599 | if (ds & type) | |
4600 | get_dep_weak (ds, type); | |
4601 | ||
4602 | if (type == LAST_SPEC_TYPE) | |
4603 | break; | |
4604 | type <<= SPEC_TYPE_SHIFT; | |
4605 | } | |
4606 | while (1); | |
4607 | } | |
4608 | ||
4609 | if (ds & BEGIN_SPEC) | |
4610 | { | |
4611 | /* Only true dependence can be data speculative. */ | |
4612 | if (ds & BEGIN_DATA) | |
4613 | gcc_assert (ds & DEP_TRUE); | |
4614 | ||
4615 | /* Control dependencies in the insn scheduler are represented by | |
4616 | anti-dependencies, therefore only anti dependence can be | |
4617 | control speculative. */ | |
4618 | if (ds & BEGIN_CONTROL) | |
4619 | gcc_assert (ds & DEP_ANTI); | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | /* Subsequent speculations should resolve true dependencies. */ | |
4624 | gcc_assert ((ds & DEP_TYPES) == DEP_TRUE); | |
4625 | } | |
48e1416a | 4626 | |
4627 | /* Check that true and anti dependencies can't have other speculative | |
4d64d9a4 | 4628 | statuses. */ |
4629 | if (ds & DEP_TRUE) | |
4630 | gcc_assert (ds & (BEGIN_DATA | BE_IN_SPEC)); | |
4631 | /* An output dependence can't be speculative at all. */ | |
4632 | gcc_assert (!(ds & DEP_OUTPUT)); | |
4633 | if (ds & DEP_ANTI) | |
4634 | gcc_assert (ds & BEGIN_CONTROL); | |
4635 | } | |
4636 | } | |
db982eeb | 4637 | |
d452a169 | 4638 | /* The following code discovers opportunities to switch a memory reference |
4639 | and an increment by modifying the address. We ensure that this is done | |
4640 | only for dependencies that are only used to show a single register | |
4641 | dependence (using DEP_NONREG and DEP_MULTIPLE), and so that every memory | |
4642 | instruction involved is subject to only one dep that can cause a pattern | |
4643 | change. | |
4644 | ||
4645 | When we discover a suitable dependency, we fill in the dep_replacement | |
4646 | structure to show how to modify the memory reference. */ | |
4647 | ||
4648 | /* Holds information about a pair of memory reference and register increment | |
4649 | insns which depend on each other, but could possibly be interchanged. */ | |
4650 | struct mem_inc_info | |
4651 | { | |
b24ef467 | 4652 | rtx_insn *inc_insn; |
4653 | rtx_insn *mem_insn; | |
d452a169 | 4654 | |
4655 | rtx *mem_loc; | |
4656 | /* A register occurring in the memory address for which we wish to break | |
4657 | the dependence. This must be identical to the destination register of | |
4658 | the increment. */ | |
4659 | rtx mem_reg0; | |
4660 | /* Any kind of index that is added to that register. */ | |
4661 | rtx mem_index; | |
4662 | /* The constant offset used in the memory address. */ | |
4663 | HOST_WIDE_INT mem_constant; | |
4664 | /* The constant added in the increment insn. Negated if the increment is | |
4665 | after the memory address. */ | |
4666 | HOST_WIDE_INT inc_constant; | |
4667 | /* The source register used in the increment. May be different from mem_reg0 | |
4668 | if the increment occurs before the memory address. */ | |
4669 | rtx inc_input; | |
4670 | }; | |
4671 | ||
4672 | /* Verify that the memory location described in MII can be replaced with | |
4673 | one using NEW_ADDR. Return the new memory reference or NULL_RTX. The | |
4674 | insn remains unchanged by this function. */ | |
4675 | ||
4676 | static rtx | |
4677 | attempt_change (struct mem_inc_info *mii, rtx new_addr) | |
4678 | { | |
4679 | rtx mem = *mii->mem_loc; | |
4680 | rtx new_mem; | |
4681 | ||
75de4aa2 | 4682 | /* Jump through a lot of hoops to keep the attributes up to date. We |
d452a169 | 4683 | do not want to call one of the change address variants that take |
4684 | an offset even though we know the offset in many cases. These | |
4685 | assume you are changing where the address is pointing by the | |
4686 | offset. */ | |
4687 | new_mem = replace_equiv_address_nv (mem, new_addr); | |
4688 | if (! validate_change (mii->mem_insn, mii->mem_loc, new_mem, 0)) | |
4689 | { | |
4690 | if (sched_verbose >= 5) | |
4691 | fprintf (sched_dump, "validation failure\n"); | |
4692 | return NULL_RTX; | |
4693 | } | |
4694 | ||
4695 | /* Put back the old one. */ | |
4696 | validate_change (mii->mem_insn, mii->mem_loc, mem, 0); | |
4697 | ||
4698 | return new_mem; | |
4699 | } | |
4700 | ||
4701 | /* Return true if INSN is of a form "a = b op c" where a and b are | |
4702 | regs. op is + if c is a reg and +|- if c is a const. Fill in | |
4703 | informantion in MII about what is found. | |
4704 | BEFORE_MEM indicates whether the increment is found before or after | |
4705 | a corresponding memory reference. */ | |
4706 | ||
4707 | static bool | |
b24ef467 | 4708 | parse_add_or_inc (struct mem_inc_info *mii, rtx_insn *insn, bool before_mem) |
d452a169 | 4709 | { |
4710 | rtx pat = single_set (insn); | |
4711 | rtx src, cst; | |
4712 | bool regs_equal; | |
4713 | ||
4714 | if (RTX_FRAME_RELATED_P (insn) || !pat) | |
4715 | return false; | |
4716 | ||
4717 | /* Result must be single reg. */ | |
4718 | if (!REG_P (SET_DEST (pat))) | |
4719 | return false; | |
4720 | ||
36faf01b | 4721 | if (GET_CODE (SET_SRC (pat)) != PLUS) |
d452a169 | 4722 | return false; |
4723 | ||
4724 | mii->inc_insn = insn; | |
4725 | src = SET_SRC (pat); | |
4726 | mii->inc_input = XEXP (src, 0); | |
4727 | ||
4728 | if (!REG_P (XEXP (src, 0))) | |
4729 | return false; | |
4730 | ||
4731 | if (!rtx_equal_p (SET_DEST (pat), mii->mem_reg0)) | |
4732 | return false; | |
4733 | ||
4734 | cst = XEXP (src, 1); | |
4735 | if (!CONST_INT_P (cst)) | |
4736 | return false; | |
4737 | mii->inc_constant = INTVAL (cst); | |
4738 | ||
4739 | regs_equal = rtx_equal_p (mii->inc_input, mii->mem_reg0); | |
4740 | ||
4741 | if (!before_mem) | |
4742 | { | |
4743 | mii->inc_constant = -mii->inc_constant; | |
4744 | if (!regs_equal) | |
4745 | return false; | |
4746 | } | |
4747 | ||
4748 | if (regs_equal && REGNO (SET_DEST (pat)) == STACK_POINTER_REGNUM) | |
36faf01b | 4749 | { |
4750 | /* Note that the sign has already been reversed for !before_mem. */ | |
3764c94e | 4751 | if (STACK_GROWS_DOWNWARD) |
4752 | return mii->inc_constant > 0; | |
4753 | else | |
4754 | return mii->inc_constant < 0; | |
36faf01b | 4755 | } |
d452a169 | 4756 | return true; |
4757 | } | |
4758 | ||
4759 | /* Once a suitable mem reference has been found and the corresponding data | |
4760 | in MII has been filled in, this function is called to find a suitable | |
4761 | add or inc insn involving the register we found in the memory | |
4762 | reference. */ | |
4763 | ||
4764 | static bool | |
4765 | find_inc (struct mem_inc_info *mii, bool backwards) | |
4766 | { | |
4767 | sd_iterator_def sd_it; | |
4768 | dep_t dep; | |
4769 | ||
4770 | sd_it = sd_iterator_start (mii->mem_insn, | |
4771 | backwards ? SD_LIST_HARD_BACK : SD_LIST_FORW); | |
4772 | while (sd_iterator_cond (&sd_it, &dep)) | |
4773 | { | |
4774 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
9d8bf733 | 4775 | rtx_insn *pro = DEP_PRO (dep); |
4776 | rtx_insn *con = DEP_CON (dep); | |
b24ef467 | 4777 | rtx_insn *inc_cand = backwards ? pro : con; |
d452a169 | 4778 | if (DEP_NONREG (dep) || DEP_MULTIPLE (dep)) |
4779 | goto next; | |
4780 | if (parse_add_or_inc (mii, inc_cand, backwards)) | |
4781 | { | |
4782 | struct dep_replacement *desc; | |
be10bb5a | 4783 | df_ref def; |
d452a169 | 4784 | rtx newaddr, newmem; |
4785 | ||
4786 | if (sched_verbose >= 5) | |
4787 | fprintf (sched_dump, "candidate mem/inc pair: %d %d\n", | |
4788 | INSN_UID (mii->mem_insn), INSN_UID (inc_cand)); | |
4789 | ||
4790 | /* Need to assure that none of the operands of the inc | |
4791 | instruction are assigned to by the mem insn. */ | |
be10bb5a | 4792 | FOR_EACH_INSN_DEF (def, mii->mem_insn) |
4793 | if (reg_overlap_mentioned_p (DF_REF_REG (def), mii->inc_input) | |
4794 | || reg_overlap_mentioned_p (DF_REF_REG (def), mii->mem_reg0)) | |
4795 | { | |
4796 | if (sched_verbose >= 5) | |
4797 | fprintf (sched_dump, | |
4798 | "inc conflicts with store failure.\n"); | |
4799 | goto next; | |
4800 | } | |
490aa3a5 | 4801 | |
d452a169 | 4802 | newaddr = mii->inc_input; |
4803 | if (mii->mem_index != NULL_RTX) | |
4804 | newaddr = gen_rtx_PLUS (GET_MODE (newaddr), newaddr, | |
4805 | mii->mem_index); | |
4806 | newaddr = plus_constant (GET_MODE (newaddr), newaddr, | |
4807 | mii->mem_constant + mii->inc_constant); | |
4808 | newmem = attempt_change (mii, newaddr); | |
4809 | if (newmem == NULL_RTX) | |
4810 | goto next; | |
4811 | if (sched_verbose >= 5) | |
4812 | fprintf (sched_dump, "successful address replacement\n"); | |
4813 | desc = XCNEW (struct dep_replacement); | |
4814 | DEP_REPLACE (dep) = desc; | |
4815 | desc->loc = mii->mem_loc; | |
4816 | desc->newval = newmem; | |
4817 | desc->orig = *desc->loc; | |
4818 | desc->insn = mii->mem_insn; | |
4819 | move_dep_link (DEP_NODE_BACK (node), INSN_HARD_BACK_DEPS (con), | |
4820 | INSN_SPEC_BACK_DEPS (con)); | |
4821 | if (backwards) | |
4822 | { | |
4823 | FOR_EACH_DEP (mii->inc_insn, SD_LIST_BACK, sd_it, dep) | |
f00069ed | 4824 | add_dependence_1 (mii->mem_insn, DEP_PRO (dep), |
4825 | REG_DEP_TRUE); | |
d452a169 | 4826 | } |
4827 | else | |
4828 | { | |
4829 | FOR_EACH_DEP (mii->inc_insn, SD_LIST_FORW, sd_it, dep) | |
f00069ed | 4830 | add_dependence_1 (DEP_CON (dep), mii->mem_insn, |
4831 | REG_DEP_ANTI); | |
d452a169 | 4832 | } |
4833 | return true; | |
4834 | } | |
4835 | next: | |
4836 | sd_iterator_next (&sd_it); | |
4837 | } | |
4838 | return false; | |
4839 | } | |
4840 | ||
4841 | /* A recursive function that walks ADDRESS_OF_X to find memory references | |
4842 | which could be modified during scheduling. We call find_inc for each | |
4843 | one we find that has a recognizable form. MII holds information about | |
4844 | the pair of memory/increment instructions. | |
4845 | We ensure that every instruction with a memory reference (which will be | |
4846 | the location of the replacement) is assigned at most one breakable | |
4847 | dependency. */ | |
4848 | ||
4849 | static bool | |
4850 | find_mem (struct mem_inc_info *mii, rtx *address_of_x) | |
4851 | { | |
4852 | rtx x = *address_of_x; | |
4853 | enum rtx_code code = GET_CODE (x); | |
4854 | const char *const fmt = GET_RTX_FORMAT (code); | |
4855 | int i; | |
4856 | ||
4857 | if (code == MEM) | |
4858 | { | |
4859 | rtx reg0 = XEXP (x, 0); | |
4860 | ||
4861 | mii->mem_loc = address_of_x; | |
4862 | mii->mem_index = NULL_RTX; | |
4863 | mii->mem_constant = 0; | |
4864 | if (GET_CODE (reg0) == PLUS && CONST_INT_P (XEXP (reg0, 1))) | |
4865 | { | |
4866 | mii->mem_constant = INTVAL (XEXP (reg0, 1)); | |
4867 | reg0 = XEXP (reg0, 0); | |
4868 | } | |
4869 | if (GET_CODE (reg0) == PLUS) | |
4870 | { | |
4871 | mii->mem_index = XEXP (reg0, 1); | |
4872 | reg0 = XEXP (reg0, 0); | |
4873 | } | |
4874 | if (REG_P (reg0)) | |
4875 | { | |
be10bb5a | 4876 | df_ref use; |
d452a169 | 4877 | int occurrences = 0; |
4878 | ||
4879 | /* Make sure this reg appears only once in this insn. Can't use | |
4880 | count_occurrences since that only works for pseudos. */ | |
be10bb5a | 4881 | FOR_EACH_INSN_USE (use, mii->mem_insn) |
4882 | if (reg_overlap_mentioned_p (reg0, DF_REF_REG (use))) | |
4883 | if (++occurrences > 1) | |
4884 | { | |
4885 | if (sched_verbose >= 5) | |
4886 | fprintf (sched_dump, "mem count failure\n"); | |
4887 | return false; | |
4888 | } | |
d452a169 | 4889 | |
4890 | mii->mem_reg0 = reg0; | |
4891 | return find_inc (mii, true) || find_inc (mii, false); | |
4892 | } | |
4893 | return false; | |
4894 | } | |
4895 | ||
4896 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
4897 | { | |
4898 | /* If REG occurs inside a MEM used in a bit-field reference, | |
4899 | that is unacceptable. */ | |
4900 | return false; | |
4901 | } | |
4902 | ||
4903 | /* Time for some deep diving. */ | |
4904 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4905 | { | |
4906 | if (fmt[i] == 'e') | |
4907 | { | |
4908 | if (find_mem (mii, &XEXP (x, i))) | |
4909 | return true; | |
4910 | } | |
4911 | else if (fmt[i] == 'E') | |
4912 | { | |
4913 | int j; | |
4914 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4915 | if (find_mem (mii, &XVECEXP (x, i, j))) | |
4916 | return true; | |
4917 | } | |
4918 | } | |
4919 | return false; | |
4920 | } | |
4921 | ||
4922 | ||
4923 | /* Examine the instructions between HEAD and TAIL and try to find | |
4924 | dependencies that can be broken by modifying one of the patterns. */ | |
4925 | ||
4926 | void | |
b24ef467 | 4927 | find_modifiable_mems (rtx_insn *head, rtx_insn *tail) |
d452a169 | 4928 | { |
b24ef467 | 4929 | rtx_insn *insn, *next_tail = NEXT_INSN (tail); |
d452a169 | 4930 | int success_in_block = 0; |
4931 | ||
1c5ae16e | 4932 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) |
d452a169 | 4933 | { |
4934 | struct mem_inc_info mii; | |
4935 | ||
4936 | if (!NONDEBUG_INSN_P (insn) || RTX_FRAME_RELATED_P (insn)) | |
4937 | continue; | |
4938 | ||
4939 | mii.mem_insn = insn; | |
4940 | if (find_mem (&mii, &PATTERN (insn))) | |
4941 | success_in_block++; | |
4942 | } | |
4943 | if (success_in_block && sched_verbose >= 5) | |
4944 | fprintf (sched_dump, "%d candidates for address modification found.\n", | |
4945 | success_in_block); | |
4946 | } | |
4947 | ||
db982eeb | 4948 | #endif /* INSN_SCHEDULING */ |