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8689682c AT |
1 | /* Common target dependent code for GDB on ARM systems. |
2 | ||
b811d2c2 | 3 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
8689682c AT |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
268a13a5 TT |
20 | #include "gdbsupport/common-defs.h" |
21 | #include "gdbsupport/common-regcache.h" | |
8689682c AT |
22 | #include "arm.h" |
23 | ||
f29ec966 AH |
24 | #include "../features/arm/arm-core.c" |
25 | #include "../features/arm/arm-vfpv2.c" | |
26 | #include "../features/arm/arm-vfpv3.c" | |
27 | #include "../features/arm/xscale-iwmmxt.c" | |
28 | #include "../features/arm/arm-m-profile.c" | |
29 | #include "../features/arm/arm-m-profile-with-fpa.c" | |
d105cce5 | 30 | |
cba7e83f | 31 | /* See arm.h. */ |
8689682c AT |
32 | |
33 | int | |
34 | thumb_insn_size (unsigned short inst1) | |
35 | { | |
36 | if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) | |
37 | return 4; | |
38 | else | |
39 | return 2; | |
40 | } | |
cba7e83f AT |
41 | |
42 | /* See arm.h. */ | |
43 | ||
44 | int | |
45 | bitcount (unsigned long val) | |
46 | { | |
47 | int nbits; | |
48 | for (nbits = 0; val != 0; nbits++) | |
49 | val &= val - 1; /* Delete rightmost 1-bit in val. */ | |
50 | return nbits; | |
51 | } | |
52 | ||
53 | /* See arm.h. */ | |
54 | ||
55 | int | |
56 | condition_true (unsigned long cond, unsigned long status_reg) | |
57 | { | |
58 | if (cond == INST_AL || cond == INST_NV) | |
59 | return 1; | |
60 | ||
61 | switch (cond) | |
62 | { | |
63 | case INST_EQ: | |
64 | return ((status_reg & FLAG_Z) != 0); | |
65 | case INST_NE: | |
66 | return ((status_reg & FLAG_Z) == 0); | |
67 | case INST_CS: | |
68 | return ((status_reg & FLAG_C) != 0); | |
69 | case INST_CC: | |
70 | return ((status_reg & FLAG_C) == 0); | |
71 | case INST_MI: | |
72 | return ((status_reg & FLAG_N) != 0); | |
73 | case INST_PL: | |
74 | return ((status_reg & FLAG_N) == 0); | |
75 | case INST_VS: | |
76 | return ((status_reg & FLAG_V) != 0); | |
77 | case INST_VC: | |
78 | return ((status_reg & FLAG_V) == 0); | |
79 | case INST_HI: | |
80 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
81 | case INST_LS: | |
82 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
83 | case INST_GE: | |
84 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
85 | case INST_LT: | |
86 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
87 | case INST_GT: | |
88 | return (((status_reg & FLAG_Z) == 0) | |
89 | && (((status_reg & FLAG_N) == 0) | |
90 | == ((status_reg & FLAG_V) == 0))); | |
91 | case INST_LE: | |
92 | return (((status_reg & FLAG_Z) != 0) | |
93 | || (((status_reg & FLAG_N) == 0) | |
94 | != ((status_reg & FLAG_V) == 0))); | |
95 | } | |
96 | return 1; | |
97 | } | |
d9311bfa AT |
98 | |
99 | ||
100 | /* See arm.h. */ | |
101 | ||
102 | int | |
103 | thumb_advance_itstate (unsigned int itstate) | |
104 | { | |
105 | /* Preserve IT[7:5], the first three bits of the condition. Shift | |
106 | the upcoming condition flags left by one bit. */ | |
107 | itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f); | |
108 | ||
109 | /* If we have finished the IT block, clear the state. */ | |
110 | if ((itstate & 0x0f) == 0) | |
111 | itstate = 0; | |
112 | ||
113 | return itstate; | |
114 | } | |
115 | ||
116 | /* See arm.h. */ | |
117 | ||
118 | int | |
119 | arm_instruction_changes_pc (uint32_t this_instr) | |
120 | { | |
121 | if (bits (this_instr, 28, 31) == INST_NV) | |
122 | /* Unconditional instructions. */ | |
123 | switch (bits (this_instr, 24, 27)) | |
124 | { | |
125 | case 0xa: | |
126 | case 0xb: | |
127 | /* Branch with Link and change to Thumb. */ | |
128 | return 1; | |
129 | case 0xc: | |
130 | case 0xd: | |
131 | case 0xe: | |
132 | /* Coprocessor register transfer. */ | |
133 | if (bits (this_instr, 12, 15) == 15) | |
134 | error (_("Invalid update to pc in instruction")); | |
135 | return 0; | |
136 | default: | |
137 | return 0; | |
138 | } | |
139 | else | |
140 | switch (bits (this_instr, 25, 27)) | |
141 | { | |
142 | case 0x0: | |
143 | if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0) | |
144 | { | |
145 | /* Multiplies and extra load/stores. */ | |
146 | if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1) | |
147 | /* Neither multiplies nor extension load/stores are allowed | |
148 | to modify PC. */ | |
149 | return 0; | |
150 | ||
151 | /* Otherwise, miscellaneous instructions. */ | |
152 | ||
153 | /* BX <reg>, BXJ <reg>, BLX <reg> */ | |
154 | if (bits (this_instr, 4, 27) == 0x12fff1 | |
155 | || bits (this_instr, 4, 27) == 0x12fff2 | |
156 | || bits (this_instr, 4, 27) == 0x12fff3) | |
157 | return 1; | |
158 | ||
159 | /* Other miscellaneous instructions are unpredictable if they | |
160 | modify PC. */ | |
161 | return 0; | |
162 | } | |
86a73007 TT |
163 | /* Data processing instruction. */ |
164 | /* Fall through. */ | |
d9311bfa AT |
165 | |
166 | case 0x1: | |
167 | if (bits (this_instr, 12, 15) == 15) | |
168 | return 1; | |
169 | else | |
170 | return 0; | |
171 | ||
172 | case 0x2: | |
173 | case 0x3: | |
174 | /* Media instructions and architecturally undefined instructions. */ | |
175 | if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1) | |
176 | return 0; | |
177 | ||
178 | /* Stores. */ | |
179 | if (bit (this_instr, 20) == 0) | |
180 | return 0; | |
181 | ||
182 | /* Loads. */ | |
183 | if (bits (this_instr, 12, 15) == ARM_PC_REGNUM) | |
184 | return 1; | |
185 | else | |
186 | return 0; | |
187 | ||
188 | case 0x4: | |
189 | /* Load/store multiple. */ | |
190 | if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1) | |
191 | return 1; | |
192 | else | |
193 | return 0; | |
194 | ||
195 | case 0x5: | |
196 | /* Branch and branch with link. */ | |
197 | return 1; | |
198 | ||
199 | case 0x6: | |
200 | case 0x7: | |
201 | /* Coprocessor transfers or SWIs can not affect PC. */ | |
202 | return 0; | |
203 | ||
204 | default: | |
205 | internal_error (__FILE__, __LINE__, _("bad value in switch")); | |
206 | } | |
207 | } | |
208 | ||
209 | /* See arm.h. */ | |
210 | ||
211 | int | |
212 | thumb_instruction_changes_pc (unsigned short inst) | |
213 | { | |
214 | if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
215 | return 1; | |
216 | ||
217 | if ((inst & 0xf000) == 0xd000) /* conditional branch */ | |
218 | return 1; | |
219 | ||
220 | if ((inst & 0xf800) == 0xe000) /* unconditional branch */ | |
221 | return 1; | |
222 | ||
223 | if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */ | |
224 | return 1; | |
225 | ||
226 | if ((inst & 0xff87) == 0x4687) /* mov pc, REG */ | |
227 | return 1; | |
228 | ||
229 | if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */ | |
230 | return 1; | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | ||
236 | /* See arm.h. */ | |
237 | ||
238 | int | |
239 | thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2) | |
240 | { | |
241 | if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) | |
242 | { | |
243 | /* Branches and miscellaneous control instructions. */ | |
244 | ||
245 | if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) | |
246 | { | |
247 | /* B, BL, BLX. */ | |
248 | return 1; | |
249 | } | |
250 | else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) | |
251 | { | |
252 | /* SUBS PC, LR, #imm8. */ | |
253 | return 1; | |
254 | } | |
255 | else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) | |
256 | { | |
257 | /* Conditional branch. */ | |
258 | return 1; | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | if ((inst1 & 0xfe50) == 0xe810) | |
265 | { | |
266 | /* Load multiple or RFE. */ | |
267 | ||
268 | if (bit (inst1, 7) && !bit (inst1, 8)) | |
269 | { | |
270 | /* LDMIA or POP */ | |
271 | if (bit (inst2, 15)) | |
272 | return 1; | |
273 | } | |
274 | else if (!bit (inst1, 7) && bit (inst1, 8)) | |
275 | { | |
276 | /* LDMDB */ | |
277 | if (bit (inst2, 15)) | |
278 | return 1; | |
279 | } | |
280 | else if (bit (inst1, 7) && bit (inst1, 8)) | |
281 | { | |
282 | /* RFEIA */ | |
283 | return 1; | |
284 | } | |
285 | else if (!bit (inst1, 7) && !bit (inst1, 8)) | |
286 | { | |
287 | /* RFEDB */ | |
288 | return 1; | |
289 | } | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) | |
295 | { | |
296 | /* MOV PC or MOVS PC. */ | |
297 | return 1; | |
298 | } | |
299 | ||
300 | if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) | |
301 | { | |
302 | /* LDR PC. */ | |
303 | if (bits (inst1, 0, 3) == 15) | |
304 | return 1; | |
305 | if (bit (inst1, 7)) | |
306 | return 1; | |
307 | if (bit (inst2, 11)) | |
308 | return 1; | |
309 | if ((inst2 & 0x0fc0) == 0x0000) | |
310 | return 1; | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) | |
316 | { | |
317 | /* TBB. */ | |
318 | return 1; | |
319 | } | |
320 | ||
321 | if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010) | |
322 | { | |
323 | /* TBH. */ | |
324 | return 1; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | /* See arm.h. */ | |
331 | ||
332 | unsigned long | |
333 | shifted_reg_val (struct regcache *regcache, unsigned long inst, | |
334 | int carry, unsigned long pc_val, unsigned long status_reg) | |
335 | { | |
336 | unsigned long res, shift; | |
337 | int rm = bits (inst, 0, 3); | |
338 | unsigned long shifttype = bits (inst, 5, 6); | |
339 | ||
340 | if (bit (inst, 4)) | |
341 | { | |
342 | int rs = bits (inst, 8, 11); | |
343 | shift = (rs == 15 | |
344 | ? pc_val + 8 | |
345 | : regcache_raw_get_unsigned (regcache, rs)) & 0xFF; | |
346 | } | |
347 | else | |
348 | shift = bits (inst, 7, 11); | |
349 | ||
350 | res = (rm == ARM_PC_REGNUM | |
351 | ? (pc_val + (bit (inst, 4) ? 12 : 8)) | |
352 | : regcache_raw_get_unsigned (regcache, rm)); | |
353 | ||
354 | switch (shifttype) | |
355 | { | |
356 | case 0: /* LSL */ | |
357 | res = shift >= 32 ? 0 : res << shift; | |
358 | break; | |
359 | ||
360 | case 1: /* LSR */ | |
361 | res = shift >= 32 ? 0 : res >> shift; | |
362 | break; | |
363 | ||
364 | case 2: /* ASR */ | |
365 | if (shift >= 32) | |
366 | shift = 31; | |
367 | res = ((res & 0x80000000L) | |
368 | ? ~((~res) >> shift) : res >> shift); | |
369 | break; | |
370 | ||
371 | case 3: /* ROR/RRX */ | |
372 | shift &= 31; | |
373 | if (shift == 0) | |
374 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
375 | else | |
376 | res = (res >> shift) | (res << (32 - shift)); | |
377 | break; | |
378 | } | |
379 | ||
380 | return res & 0xffffffff; | |
381 | } | |
d105cce5 AH |
382 | |
383 | /* See arch/arm.h. */ | |
384 | ||
385 | target_desc * | |
386 | arm_create_target_description (arm_fp_type fp_type) | |
387 | { | |
f29ec966 AH |
388 | target_desc *tdesc = allocate_target_description (); |
389 | ||
390 | #ifndef IN_PROCESS_AGENT | |
391 | if (fp_type == ARM_FP_TYPE_IWMMXT) | |
392 | set_tdesc_architecture (tdesc, "iwmmxt"); | |
393 | else | |
394 | set_tdesc_architecture (tdesc, "arm"); | |
395 | #endif | |
396 | ||
397 | long regnum = 0; | |
398 | ||
399 | regnum = create_feature_arm_arm_core (tdesc, regnum); | |
400 | ||
d105cce5 AH |
401 | switch (fp_type) |
402 | { | |
403 | case ARM_FP_TYPE_NONE: | |
f29ec966 AH |
404 | break; |
405 | ||
d105cce5 | 406 | case ARM_FP_TYPE_VFPV2: |
f29ec966 AH |
407 | regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum); |
408 | break; | |
d105cce5 AH |
409 | |
410 | case ARM_FP_TYPE_VFPV3: | |
f29ec966 AH |
411 | regnum = create_feature_arm_arm_vfpv3 (tdesc, regnum); |
412 | break; | |
d105cce5 AH |
413 | |
414 | case ARM_FP_TYPE_IWMMXT: | |
f29ec966 AH |
415 | regnum = create_feature_arm_xscale_iwmmxt (tdesc, regnum); |
416 | break; | |
417 | ||
d105cce5 AH |
418 | default: |
419 | error (_("Invalid Arm FP type: %d"), fp_type); | |
420 | } | |
f29ec966 AH |
421 | |
422 | return tdesc; | |
d105cce5 AH |
423 | } |
424 | ||
425 | /* See arch/arm.h. */ | |
426 | ||
427 | target_desc * | |
428 | arm_create_mprofile_target_description (arm_m_profile_type m_type) | |
429 | { | |
f29ec966 AH |
430 | target_desc *tdesc = allocate_target_description (); |
431 | ||
432 | #ifndef IN_PROCESS_AGENT | |
433 | set_tdesc_architecture (tdesc, "arm"); | |
434 | #endif | |
435 | ||
436 | long regnum = 0; | |
437 | ||
d105cce5 AH |
438 | switch (m_type) |
439 | { | |
d105cce5 | 440 | case ARM_M_TYPE_M_PROFILE: |
f29ec966 AH |
441 | regnum = create_feature_arm_arm_m_profile (tdesc, regnum); |
442 | break; | |
d105cce5 AH |
443 | |
444 | case ARM_M_TYPE_VFP_D16: | |
f29ec966 AH |
445 | regnum = create_feature_arm_arm_m_profile (tdesc, regnum); |
446 | regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum); | |
447 | break; | |
d105cce5 AH |
448 | |
449 | case ARM_M_TYPE_WITH_FPA: | |
f29ec966 AH |
450 | regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum); |
451 | break; | |
452 | ||
d105cce5 AH |
453 | default: |
454 | error (_("Invalid Arm M type: %d"), m_type); | |
455 | } | |
d105cce5 | 456 | |
f29ec966 AH |
457 | return tdesc; |
458 | } |