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9158fa54 LG |
1 | /* |
2 | * Allwinner A10 SoC emulation | |
3 | * | |
4 | * Copyright (C) 2013 Li Guang | |
5 | * Written by Li Guang <lig.fnst@cn.fujitsu.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | */ | |
17 | ||
12b16722 | 18 | #include "qemu/osdep.h" |
da34e65c | 19 | #include "qapi/error.h" |
9158fa54 LG |
20 | #include "hw/sysbus.h" |
21 | #include "hw/devices.h" | |
22 | #include "hw/arm/allwinner-a10.h" | |
23 | ||
24 | static void aw_a10_init(Object *obj) | |
25 | { | |
26 | AwA10State *s = AW_A10(obj); | |
27 | ||
28 | object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU); | |
29 | object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); | |
30 | ||
31 | object_initialize(&s->intc, sizeof(s->intc), TYPE_AW_A10_PIC); | |
32 | qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default()); | |
33 | ||
34 | object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT); | |
35 | qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); | |
db7dfd4c BG |
36 | |
37 | object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC); | |
38 | qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default()); | |
19f33f16 | 39 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
db7dfd4c BG |
40 | if (nd_table[0].used) { |
41 | qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); | |
42 | qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); | |
43 | } | |
dca62576 PC |
44 | |
45 | object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI); | |
46 | qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); | |
9158fa54 LG |
47 | } |
48 | ||
49 | static void aw_a10_realize(DeviceState *dev, Error **errp) | |
50 | { | |
51 | AwA10State *s = AW_A10(dev); | |
52 | SysBusDevice *sysbusdev; | |
53 | uint8_t i; | |
54 | qemu_irq fiq, irq; | |
55 | Error *err = NULL; | |
56 | ||
57 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | |
58 | if (err != NULL) { | |
59 | error_propagate(errp, err); | |
60 | return; | |
61 | } | |
62 | irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); | |
63 | fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); | |
64 | ||
65 | object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); | |
66 | if (err != NULL) { | |
67 | error_propagate(errp, err); | |
68 | return; | |
69 | } | |
70 | sysbusdev = SYS_BUS_DEVICE(&s->intc); | |
71 | sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); | |
72 | sysbus_connect_irq(sysbusdev, 0, irq); | |
73 | sysbus_connect_irq(sysbusdev, 1, fiq); | |
74 | for (i = 0; i < AW_A10_PIC_INT_NR; i++) { | |
75 | s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i); | |
76 | } | |
77 | ||
78 | object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); | |
79 | if (err != NULL) { | |
80 | error_propagate(errp, err); | |
81 | return; | |
82 | } | |
83 | sysbusdev = SYS_BUS_DEVICE(&s->timer); | |
84 | sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); | |
85 | sysbus_connect_irq(sysbusdev, 0, s->irq[22]); | |
86 | sysbus_connect_irq(sysbusdev, 1, s->irq[23]); | |
87 | sysbus_connect_irq(sysbusdev, 2, s->irq[24]); | |
88 | sysbus_connect_irq(sysbusdev, 3, s->irq[25]); | |
89 | sysbus_connect_irq(sysbusdev, 4, s->irq[67]); | |
90 | sysbus_connect_irq(sysbusdev, 5, s->irq[68]); | |
91 | ||
db7dfd4c BG |
92 | object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); |
93 | if (err != NULL) { | |
94 | error_propagate(errp, err); | |
95 | return; | |
96 | } | |
97 | sysbusdev = SYS_BUS_DEVICE(&s->emac); | |
98 | sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); | |
99 | sysbus_connect_irq(sysbusdev, 0, s->irq[55]); | |
100 | ||
dca62576 PC |
101 | object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); |
102 | if (err) { | |
103 | error_propagate(errp, err); | |
104 | return; | |
105 | } | |
106 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); | |
107 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); | |
108 | ||
d71b22bb | 109 | /* FIXME use a qdev chardev prop instead of serial_hds[] */ |
9158fa54 LG |
110 | serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], |
111 | 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
112 | } | |
113 | ||
114 | static void aw_a10_class_init(ObjectClass *oc, void *data) | |
115 | { | |
116 | DeviceClass *dc = DEVICE_CLASS(oc); | |
117 | ||
118 | dc->realize = aw_a10_realize; | |
4c315c27 MA |
119 | |
120 | /* | |
121 | * Reason: creates an ARM CPU, thus use after free(), see | |
122 | * arm_cpu_class_init() | |
123 | */ | |
124 | dc->cannot_destroy_with_object_finalize_yet = true; | |
9158fa54 LG |
125 | } |
126 | ||
127 | static const TypeInfo aw_a10_type_info = { | |
128 | .name = TYPE_AW_A10, | |
129 | .parent = TYPE_DEVICE, | |
130 | .instance_size = sizeof(AwA10State), | |
131 | .instance_init = aw_a10_init, | |
132 | .class_init = aw_a10_class_init, | |
133 | }; | |
134 | ||
135 | static void aw_a10_register_types(void) | |
136 | { | |
137 | type_register_static(&aw_a10_type_info); | |
138 | } | |
139 | ||
140 | type_init(aw_a10_register_types) |