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ec46eaa8 JCD |
1 | /* |
2 | * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> | |
3 | * | |
4 | * i.MX6 SOC emulation. | |
5 | * | |
6 | * Based on hw/arm/fsl-imx31.c | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "qemu/osdep.h" | |
23 | #include "qapi/error.h" | |
ec46eaa8 | 24 | #include "hw/arm/fsl-imx6.h" |
cc7d44c2 | 25 | #include "hw/boards.h" |
a27bd6c7 | 26 | #include "hw/qdev-properties.h" |
ec46eaa8 | 27 | #include "sysemu/sysemu.h" |
8228e353 | 28 | #include "chardev/char.h" |
ec46eaa8 | 29 | #include "qemu/error-report.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
ec46eaa8 | 31 | |
7f072603 PMD |
32 | #define IMX6_ESDHC_CAPABILITIES 0x057834b4 |
33 | ||
ec46eaa8 JCD |
34 | #define NAME_SIZE 20 |
35 | ||
36 | static void fsl_imx6_init(Object *obj) | |
37 | { | |
cc7d44c2 | 38 | MachineState *ms = MACHINE(qdev_get_machine()); |
ec46eaa8 JCD |
39 | FslIMX6State *s = FSL_IMX6(obj); |
40 | char name[NAME_SIZE]; | |
41 | int i; | |
42 | ||
cc7d44c2 | 43 | for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { |
ec46eaa8 | 44 | snprintf(name, NAME_SIZE, "cpu%d", i); |
e9e4d4d3 | 45 | object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), |
8a863c81 PMD |
46 | ARM_CPU_TYPE_NAME("cortex-a9"), |
47 | &error_abort, NULL); | |
ec46eaa8 JCD |
48 | } |
49 | ||
e9e4d4d3 TH |
50 | sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore), |
51 | TYPE_A9MPCORE_PRIV); | |
ec46eaa8 | 52 | |
e9e4d4d3 | 53 | sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM); |
ec46eaa8 | 54 | |
e9e4d4d3 | 55 | sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC); |
ec46eaa8 JCD |
56 | |
57 | for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { | |
ec46eaa8 | 58 | snprintf(name, NAME_SIZE, "uart%d", i + 1); |
e9e4d4d3 TH |
59 | sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]), |
60 | TYPE_IMX_SERIAL); | |
ec46eaa8 JCD |
61 | } |
62 | ||
e9e4d4d3 | 63 | sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT); |
ec46eaa8 JCD |
64 | |
65 | for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { | |
ec46eaa8 | 66 | snprintf(name, NAME_SIZE, "epit%d", i + 1); |
e9e4d4d3 TH |
67 | sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]), |
68 | TYPE_IMX_EPIT); | |
ec46eaa8 JCD |
69 | } |
70 | ||
71 | for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { | |
ec46eaa8 | 72 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); |
e9e4d4d3 TH |
73 | sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]), |
74 | TYPE_IMX_I2C); | |
ec46eaa8 JCD |
75 | } |
76 | ||
77 | for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { | |
ec46eaa8 | 78 | snprintf(name, NAME_SIZE, "gpio%d", i + 1); |
e9e4d4d3 TH |
79 | sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]), |
80 | TYPE_IMX_GPIO); | |
ec46eaa8 JCD |
81 | } |
82 | ||
83 | for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { | |
ec46eaa8 | 84 | snprintf(name, NAME_SIZE, "sdhc%d", i + 1); |
e9e4d4d3 TH |
85 | sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]), |
86 | TYPE_IMX_USDHC); | |
ec46eaa8 JCD |
87 | } |
88 | ||
89 | for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { | |
ec46eaa8 | 90 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
e9e4d4d3 TH |
91 | sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), |
92 | TYPE_IMX_SPI); | |
ec46eaa8 | 93 | } |
517b5e9a | 94 | |
e9e4d4d3 | 95 | sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET); |
ec46eaa8 JCD |
96 | } |
97 | ||
98 | static void fsl_imx6_realize(DeviceState *dev, Error **errp) | |
99 | { | |
cc7d44c2 | 100 | MachineState *ms = MACHINE(qdev_get_machine()); |
ec46eaa8 JCD |
101 | FslIMX6State *s = FSL_IMX6(dev); |
102 | uint16_t i; | |
103 | Error *err = NULL; | |
cc7d44c2 | 104 | unsigned int smp_cpus = ms->smp.cpus; |
ec46eaa8 | 105 | |
f640a591 TH |
106 | if (smp_cpus > FSL_IMX6_NUM_CPUS) { |
107 | error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", | |
108 | TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); | |
109 | return; | |
110 | } | |
111 | ||
ec46eaa8 JCD |
112 | for (i = 0; i < smp_cpus; i++) { |
113 | ||
114 | /* On uniprocessor, the CBAR is set to 0 */ | |
115 | if (smp_cpus > 1) { | |
116 | object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, | |
117 | "reset-cbar", &error_abort); | |
118 | } | |
119 | ||
120 | /* All CPU but CPU 0 start in power off mode */ | |
121 | if (i) { | |
122 | object_property_set_bool(OBJECT(&s->cpu[i]), true, | |
123 | "start-powered-off", &error_abort); | |
124 | } | |
125 | ||
126 | object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); | |
127 | if (err) { | |
128 | error_propagate(errp, err); | |
129 | return; | |
130 | } | |
131 | } | |
132 | ||
133 | object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", | |
134 | &error_abort); | |
135 | ||
136 | object_property_set_int(OBJECT(&s->a9mpcore), | |
137 | FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", | |
138 | &error_abort); | |
139 | ||
140 | object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err); | |
141 | if (err) { | |
142 | error_propagate(errp, err); | |
143 | return; | |
144 | } | |
145 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); | |
146 | ||
147 | for (i = 0; i < smp_cpus; i++) { | |
148 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, | |
149 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); | |
150 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, | |
151 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); | |
152 | } | |
153 | ||
154 | object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); | |
155 | if (err) { | |
156 | error_propagate(errp, err); | |
157 | return; | |
158 | } | |
159 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); | |
160 | ||
161 | object_property_set_bool(OBJECT(&s->src), true, "realized", &err); | |
162 | if (err) { | |
163 | error_propagate(errp, err); | |
164 | return; | |
165 | } | |
166 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); | |
167 | ||
168 | /* Initialize all UARTs */ | |
169 | for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { | |
170 | static const struct { | |
171 | hwaddr addr; | |
172 | unsigned int irq; | |
173 | } serial_table[FSL_IMX6_NUM_UARTS] = { | |
174 | { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, | |
175 | { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, | |
176 | { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, | |
177 | { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, | |
178 | { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, | |
179 | }; | |
180 | ||
fc38a112 | 181 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
ec46eaa8 JCD |
182 | |
183 | object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); | |
184 | if (err) { | |
185 | error_propagate(errp, err); | |
186 | return; | |
187 | } | |
188 | ||
189 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); | |
190 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, | |
191 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
192 | serial_table[i].irq)); | |
193 | } | |
194 | ||
195 | s->gpt.ccm = IMX_CCM(&s->ccm); | |
196 | ||
197 | object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); | |
198 | if (err) { | |
199 | error_propagate(errp, err); | |
200 | return; | |
201 | } | |
202 | ||
203 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); | |
204 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, | |
205 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
206 | FSL_IMX6_GPT_IRQ)); | |
207 | ||
208 | /* Initialize all EPIT timers */ | |
209 | for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { | |
210 | static const struct { | |
211 | hwaddr addr; | |
212 | unsigned int irq; | |
213 | } epit_table[FSL_IMX6_NUM_EPITS] = { | |
214 | { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, | |
215 | { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, | |
216 | }; | |
217 | ||
218 | s->epit[i].ccm = IMX_CCM(&s->ccm); | |
219 | ||
220 | object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); | |
221 | if (err) { | |
222 | error_propagate(errp, err); | |
223 | return; | |
224 | } | |
225 | ||
226 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); | |
227 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, | |
228 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
229 | epit_table[i].irq)); | |
230 | } | |
231 | ||
232 | /* Initialize all I2C */ | |
233 | for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { | |
234 | static const struct { | |
235 | hwaddr addr; | |
236 | unsigned int irq; | |
237 | } i2c_table[FSL_IMX6_NUM_I2CS] = { | |
238 | { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, | |
239 | { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, | |
240 | { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } | |
241 | }; | |
242 | ||
243 | object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); | |
244 | if (err) { | |
245 | error_propagate(errp, err); | |
246 | return; | |
247 | } | |
248 | ||
249 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); | |
250 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, | |
251 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
252 | i2c_table[i].irq)); | |
253 | } | |
254 | ||
255 | /* Initialize all GPIOs */ | |
256 | for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { | |
257 | static const struct { | |
258 | hwaddr addr; | |
259 | unsigned int irq_low; | |
260 | unsigned int irq_high; | |
261 | } gpio_table[FSL_IMX6_NUM_GPIOS] = { | |
262 | { | |
263 | FSL_IMX6_GPIO1_ADDR, | |
264 | FSL_IMX6_GPIO1_LOW_IRQ, | |
265 | FSL_IMX6_GPIO1_HIGH_IRQ | |
266 | }, | |
267 | { | |
268 | FSL_IMX6_GPIO2_ADDR, | |
269 | FSL_IMX6_GPIO2_LOW_IRQ, | |
270 | FSL_IMX6_GPIO2_HIGH_IRQ | |
271 | }, | |
272 | { | |
273 | FSL_IMX6_GPIO3_ADDR, | |
274 | FSL_IMX6_GPIO3_LOW_IRQ, | |
275 | FSL_IMX6_GPIO3_HIGH_IRQ | |
276 | }, | |
277 | { | |
278 | FSL_IMX6_GPIO4_ADDR, | |
279 | FSL_IMX6_GPIO4_LOW_IRQ, | |
280 | FSL_IMX6_GPIO4_HIGH_IRQ | |
281 | }, | |
282 | { | |
283 | FSL_IMX6_GPIO5_ADDR, | |
284 | FSL_IMX6_GPIO5_LOW_IRQ, | |
285 | FSL_IMX6_GPIO5_HIGH_IRQ | |
286 | }, | |
287 | { | |
288 | FSL_IMX6_GPIO6_ADDR, | |
289 | FSL_IMX6_GPIO6_LOW_IRQ, | |
290 | FSL_IMX6_GPIO6_HIGH_IRQ | |
291 | }, | |
292 | { | |
293 | FSL_IMX6_GPIO7_ADDR, | |
294 | FSL_IMX6_GPIO7_LOW_IRQ, | |
295 | FSL_IMX6_GPIO7_HIGH_IRQ | |
296 | }, | |
297 | }; | |
298 | ||
299 | object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", | |
300 | &error_abort); | |
301 | object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", | |
302 | &error_abort); | |
303 | object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); | |
304 | if (err) { | |
305 | error_propagate(errp, err); | |
306 | return; | |
307 | } | |
308 | ||
309 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); | |
310 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, | |
311 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
312 | gpio_table[i].irq_low)); | |
313 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, | |
314 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
315 | gpio_table[i].irq_high)); | |
316 | } | |
317 | ||
318 | /* Initialize all SDHC */ | |
319 | for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { | |
320 | static const struct { | |
321 | hwaddr addr; | |
322 | unsigned int irq; | |
323 | } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { | |
324 | { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, | |
325 | { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, | |
326 | { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, | |
327 | { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, | |
328 | }; | |
329 | ||
7f072603 PMD |
330 | /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ |
331 | object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version", | |
332 | &err); | |
333 | object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, | |
334 | "capareg", &err); | |
ec46eaa8 JCD |
335 | object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); |
336 | if (err) { | |
337 | error_propagate(errp, err); | |
338 | return; | |
339 | } | |
340 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); | |
341 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, | |
342 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
343 | esdhc_table[i].irq)); | |
344 | } | |
345 | ||
346 | /* Initialize all ECSPI */ | |
347 | for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { | |
348 | static const struct { | |
349 | hwaddr addr; | |
350 | unsigned int irq; | |
351 | } spi_table[FSL_IMX6_NUM_ECSPIS] = { | |
352 | { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, | |
353 | { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, | |
354 | { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, | |
355 | { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, | |
356 | { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, | |
357 | }; | |
358 | ||
359 | /* Initialize the SPI */ | |
360 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); | |
361 | if (err) { | |
362 | error_propagate(errp, err); | |
363 | return; | |
364 | } | |
365 | ||
366 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); | |
367 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
368 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
369 | spi_table[i].irq)); | |
370 | } | |
371 | ||
1fdde653 | 372 | qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); |
517b5e9a JCD |
373 | object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); |
374 | if (err) { | |
375 | error_propagate(errp, err); | |
376 | return; | |
377 | } | |
378 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); | |
379 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, | |
380 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
381 | FSL_IMX6_ENET_MAC_IRQ)); | |
382 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, | |
383 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), | |
384 | FSL_IMX6_ENET_MAC_1588_IRQ)); | |
385 | ||
ec46eaa8 | 386 | /* ROM memory */ |
eda40cc1 | 387 | memory_region_init_rom(&s->rom, NULL, "imx6.rom", |
a7aeb5f7 | 388 | FSL_IMX6_ROM_SIZE, &err); |
ec46eaa8 JCD |
389 | if (err) { |
390 | error_propagate(errp, err); | |
391 | return; | |
392 | } | |
393 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, | |
394 | &s->rom); | |
395 | ||
396 | /* CAAM memory */ | |
eda40cc1 | 397 | memory_region_init_rom(&s->caam, NULL, "imx6.caam", |
a7aeb5f7 | 398 | FSL_IMX6_CAAM_MEM_SIZE, &err); |
ec46eaa8 JCD |
399 | if (err) { |
400 | error_propagate(errp, err); | |
401 | return; | |
402 | } | |
403 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, | |
404 | &s->caam); | |
405 | ||
406 | /* OCRAM memory */ | |
98a99ce0 | 407 | memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, |
ec46eaa8 JCD |
408 | &err); |
409 | if (err) { | |
410 | error_propagate(errp, err); | |
411 | return; | |
412 | } | |
413 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, | |
414 | &s->ocram); | |
ec46eaa8 JCD |
415 | |
416 | /* internal OCRAM (256 KB) is aliased over 1 MB */ | |
417 | memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias", | |
418 | &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); | |
419 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, | |
420 | &s->ocram_alias); | |
421 | } | |
422 | ||
423 | static void fsl_imx6_class_init(ObjectClass *oc, void *data) | |
424 | { | |
425 | DeviceClass *dc = DEVICE_CLASS(oc); | |
426 | ||
427 | dc->realize = fsl_imx6_realize; | |
ec46eaa8 | 428 | dc->desc = "i.MX6 SOC"; |
9bca0edb | 429 | /* Reason: Uses serial_hd() in the realize() function */ |
70fbd3c4 | 430 | dc->user_creatable = false; |
ec46eaa8 JCD |
431 | } |
432 | ||
433 | static const TypeInfo fsl_imx6_type_info = { | |
434 | .name = TYPE_FSL_IMX6, | |
435 | .parent = TYPE_DEVICE, | |
436 | .instance_size = sizeof(FslIMX6State), | |
437 | .instance_init = fsl_imx6_init, | |
438 | .class_init = fsl_imx6_class_init, | |
439 | }; | |
440 | ||
441 | static void fsl_imx6_register_types(void) | |
442 | { | |
443 | type_register_static(&fsl_imx6_type_info); | |
444 | } | |
445 | ||
446 | type_init(fsl_imx6_register_types) |