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Commit | Line | Data |
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24859b68 AZ |
1 | /* |
2 | * Marvell MV88W8618 / Freecom MusicPal emulation. | |
3 | * | |
4 | * Copyright (c) 2008 Jan Kiszka | |
5 | * | |
8e31bf38 | 6 | * This code is licensed under the GNU GPL v2. |
6b620ca3 PB |
7 | * |
8 | * Contributions after 2012-01-13 are licensed under the terms of the | |
9 | * GNU GPL, version 2 or (at your option) any later version. | |
24859b68 AZ |
10 | */ |
11 | ||
12b16722 | 12 | #include "qemu/osdep.h" |
da34e65c | 13 | #include "qapi/error.h" |
4771d756 | 14 | #include "cpu.h" |
83c9f4ca | 15 | #include "hw/sysbus.h" |
12ec8bd5 | 16 | #include "hw/arm/boot.h" |
1422e32d | 17 | #include "net/net.h" |
9c17d615 | 18 | #include "sysemu/sysemu.h" |
83c9f4ca | 19 | #include "hw/boards.h" |
0d09e41a | 20 | #include "hw/char/serial.h" |
1de7afc9 | 21 | #include "qemu/timer.h" |
83c9f4ca | 22 | #include "hw/ptimer.h" |
0d09e41a | 23 | #include "hw/block/flash.h" |
28ecbaee | 24 | #include "ui/console.h" |
0d09e41a | 25 | #include "hw/i2c/i2c.h" |
7ab14c5a | 26 | #include "hw/audio/wm8750.h" |
fa1d36df | 27 | #include "sysemu/block-backend.h" |
022c62cb | 28 | #include "exec/address-spaces.h" |
28ecbaee | 29 | #include "ui/pixel_ops.h" |
24859b68 | 30 | |
718ec0be | 31 | #define MP_MISC_BASE 0x80002000 |
32 | #define MP_MISC_SIZE 0x00001000 | |
33 | ||
24859b68 AZ |
34 | #define MP_ETH_BASE 0x80008000 |
35 | #define MP_ETH_SIZE 0x00001000 | |
36 | ||
718ec0be | 37 | #define MP_WLAN_BASE 0x8000C000 |
38 | #define MP_WLAN_SIZE 0x00000800 | |
39 | ||
24859b68 AZ |
40 | #define MP_UART1_BASE 0x8000C840 |
41 | #define MP_UART2_BASE 0x8000C940 | |
42 | ||
718ec0be | 43 | #define MP_GPIO_BASE 0x8000D000 |
44 | #define MP_GPIO_SIZE 0x00001000 | |
45 | ||
24859b68 AZ |
46 | #define MP_FLASHCFG_BASE 0x90006000 |
47 | #define MP_FLASHCFG_SIZE 0x00001000 | |
48 | ||
49 | #define MP_AUDIO_BASE 0x90007000 | |
24859b68 AZ |
50 | |
51 | #define MP_PIC_BASE 0x90008000 | |
52 | #define MP_PIC_SIZE 0x00001000 | |
53 | ||
54 | #define MP_PIT_BASE 0x90009000 | |
55 | #define MP_PIT_SIZE 0x00001000 | |
56 | ||
57 | #define MP_LCD_BASE 0x9000c000 | |
58 | #define MP_LCD_SIZE 0x00001000 | |
59 | ||
60 | #define MP_SRAM_BASE 0xC0000000 | |
61 | #define MP_SRAM_SIZE 0x00020000 | |
62 | ||
63 | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 | |
64 | #define MP_FLASH_SIZE_MAX 32*1024*1024 | |
65 | ||
66 | #define MP_TIMER1_IRQ 4 | |
b47b50fa PB |
67 | #define MP_TIMER2_IRQ 5 |
68 | #define MP_TIMER3_IRQ 6 | |
24859b68 AZ |
69 | #define MP_TIMER4_IRQ 7 |
70 | #define MP_EHCI_IRQ 8 | |
71 | #define MP_ETH_IRQ 9 | |
72 | #define MP_UART1_IRQ 11 | |
73 | #define MP_UART2_IRQ 11 | |
74 | #define MP_GPIO_IRQ 12 | |
75 | #define MP_RTC_IRQ 28 | |
76 | #define MP_AUDIO_IRQ 30 | |
77 | ||
24859b68 | 78 | /* Wolfson 8750 I2C address */ |
64258229 | 79 | #define MP_WM_ADDR 0x1A |
24859b68 | 80 | |
24859b68 AZ |
81 | /* Ethernet register offsets */ |
82 | #define MP_ETH_SMIR 0x010 | |
83 | #define MP_ETH_PCXR 0x408 | |
84 | #define MP_ETH_SDCMR 0x448 | |
85 | #define MP_ETH_ICR 0x450 | |
86 | #define MP_ETH_IMR 0x458 | |
87 | #define MP_ETH_FRDP0 0x480 | |
88 | #define MP_ETH_FRDP1 0x484 | |
89 | #define MP_ETH_FRDP2 0x488 | |
90 | #define MP_ETH_FRDP3 0x48C | |
91 | #define MP_ETH_CRDP0 0x4A0 | |
92 | #define MP_ETH_CRDP1 0x4A4 | |
93 | #define MP_ETH_CRDP2 0x4A8 | |
94 | #define MP_ETH_CRDP3 0x4AC | |
95 | #define MP_ETH_CTDP0 0x4E0 | |
96 | #define MP_ETH_CTDP1 0x4E4 | |
24859b68 AZ |
97 | |
98 | /* MII PHY access */ | |
99 | #define MP_ETH_SMIR_DATA 0x0000FFFF | |
100 | #define MP_ETH_SMIR_ADDR 0x03FF0000 | |
101 | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ | |
102 | #define MP_ETH_SMIR_RDVALID (1 << 27) | |
103 | ||
104 | /* PHY registers */ | |
105 | #define MP_ETH_PHY1_BMSR 0x00210000 | |
106 | #define MP_ETH_PHY1_PHYSID1 0x00410000 | |
107 | #define MP_ETH_PHY1_PHYSID2 0x00610000 | |
108 | ||
109 | #define MP_PHY_BMSR_LINK 0x0004 | |
110 | #define MP_PHY_BMSR_AUTONEG 0x0008 | |
111 | ||
112 | #define MP_PHY_88E3015 0x01410E20 | |
113 | ||
114 | /* TX descriptor status */ | |
2b194951 | 115 | #define MP_ETH_TX_OWN (1U << 31) |
24859b68 AZ |
116 | |
117 | /* RX descriptor status */ | |
2b194951 | 118 | #define MP_ETH_RX_OWN (1U << 31) |
24859b68 AZ |
119 | |
120 | /* Interrupt cause/mask bits */ | |
121 | #define MP_ETH_IRQ_RX_BIT 0 | |
122 | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) | |
123 | #define MP_ETH_IRQ_TXHI_BIT 2 | |
124 | #define MP_ETH_IRQ_TXLO_BIT 3 | |
125 | ||
126 | /* Port config bits */ | |
127 | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ | |
128 | ||
129 | /* SDMA command bits */ | |
130 | #define MP_ETH_CMD_TXHI (1 << 23) | |
131 | #define MP_ETH_CMD_TXLO (1 << 22) | |
132 | ||
133 | typedef struct mv88w8618_tx_desc { | |
134 | uint32_t cmdstat; | |
135 | uint16_t res; | |
136 | uint16_t bytes; | |
137 | uint32_t buffer; | |
138 | uint32_t next; | |
139 | } mv88w8618_tx_desc; | |
140 | ||
141 | typedef struct mv88w8618_rx_desc { | |
142 | uint32_t cmdstat; | |
143 | uint16_t bytes; | |
144 | uint16_t buffer_size; | |
145 | uint32_t buffer; | |
146 | uint32_t next; | |
147 | } mv88w8618_rx_desc; | |
148 | ||
a77d90e6 AF |
149 | #define TYPE_MV88W8618_ETH "mv88w8618_eth" |
150 | #define MV88W8618_ETH(obj) \ | |
151 | OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH) | |
152 | ||
24859b68 | 153 | typedef struct mv88w8618_eth_state { |
a77d90e6 AF |
154 | /*< private >*/ |
155 | SysBusDevice parent_obj; | |
156 | /*< public >*/ | |
157 | ||
19b4a424 | 158 | MemoryRegion iomem; |
24859b68 AZ |
159 | qemu_irq irq; |
160 | uint32_t smir; | |
161 | uint32_t icr; | |
162 | uint32_t imr; | |
b946a153 | 163 | int mmio_index; |
d5b61ddd | 164 | uint32_t vlan_header; |
930c8682 PB |
165 | uint32_t tx_queue[2]; |
166 | uint32_t rx_queue[4]; | |
167 | uint32_t frx_queue[4]; | |
168 | uint32_t cur_rx[4]; | |
3a94dd18 | 169 | NICState *nic; |
4c91cd28 | 170 | NICConf conf; |
24859b68 AZ |
171 | } mv88w8618_eth_state; |
172 | ||
930c8682 PB |
173 | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
174 | { | |
175 | cpu_to_le32s(&desc->cmdstat); | |
176 | cpu_to_le16s(&desc->bytes); | |
177 | cpu_to_le16s(&desc->buffer_size); | |
178 | cpu_to_le32s(&desc->buffer); | |
179 | cpu_to_le32s(&desc->next); | |
e1fe50dc | 180 | cpu_physical_memory_write(addr, desc, sizeof(*desc)); |
930c8682 PB |
181 | } |
182 | ||
183 | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) | |
184 | { | |
e1fe50dc | 185 | cpu_physical_memory_read(addr, desc, sizeof(*desc)); |
930c8682 PB |
186 | le32_to_cpus(&desc->cmdstat); |
187 | le16_to_cpus(&desc->bytes); | |
188 | le16_to_cpus(&desc->buffer_size); | |
189 | le32_to_cpus(&desc->buffer); | |
190 | le32_to_cpus(&desc->next); | |
191 | } | |
192 | ||
4e68f7a0 | 193 | static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
24859b68 | 194 | { |
cc1f0f45 | 195 | mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); |
930c8682 PB |
196 | uint32_t desc_addr; |
197 | mv88w8618_rx_desc desc; | |
24859b68 AZ |
198 | int i; |
199 | ||
200 | for (i = 0; i < 4; i++) { | |
930c8682 | 201 | desc_addr = s->cur_rx[i]; |
49fedd0d | 202 | if (!desc_addr) { |
24859b68 | 203 | continue; |
49fedd0d | 204 | } |
24859b68 | 205 | do { |
930c8682 PB |
206 | eth_rx_desc_get(desc_addr, &desc); |
207 | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { | |
208 | cpu_physical_memory_write(desc.buffer + s->vlan_header, | |
209 | buf, size); | |
210 | desc.bytes = size + s->vlan_header; | |
211 | desc.cmdstat &= ~MP_ETH_RX_OWN; | |
212 | s->cur_rx[i] = desc.next; | |
24859b68 AZ |
213 | |
214 | s->icr |= MP_ETH_IRQ_RX; | |
49fedd0d | 215 | if (s->icr & s->imr) { |
24859b68 | 216 | qemu_irq_raise(s->irq); |
49fedd0d | 217 | } |
930c8682 | 218 | eth_rx_desc_put(desc_addr, &desc); |
4f1c942b | 219 | return size; |
24859b68 | 220 | } |
930c8682 PB |
221 | desc_addr = desc.next; |
222 | } while (desc_addr != s->rx_queue[i]); | |
24859b68 | 223 | } |
4f1c942b | 224 | return size; |
24859b68 AZ |
225 | } |
226 | ||
930c8682 PB |
227 | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
228 | { | |
229 | cpu_to_le32s(&desc->cmdstat); | |
230 | cpu_to_le16s(&desc->res); | |
231 | cpu_to_le16s(&desc->bytes); | |
232 | cpu_to_le32s(&desc->buffer); | |
233 | cpu_to_le32s(&desc->next); | |
e1fe50dc | 234 | cpu_physical_memory_write(addr, desc, sizeof(*desc)); |
930c8682 PB |
235 | } |
236 | ||
237 | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) | |
238 | { | |
e1fe50dc | 239 | cpu_physical_memory_read(addr, desc, sizeof(*desc)); |
930c8682 PB |
240 | le32_to_cpus(&desc->cmdstat); |
241 | le16_to_cpus(&desc->res); | |
242 | le16_to_cpus(&desc->bytes); | |
243 | le32_to_cpus(&desc->buffer); | |
244 | le32_to_cpus(&desc->next); | |
245 | } | |
246 | ||
24859b68 AZ |
247 | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
248 | { | |
930c8682 PB |
249 | uint32_t desc_addr = s->tx_queue[queue_index]; |
250 | mv88w8618_tx_desc desc; | |
07b064e9 | 251 | uint32_t next_desc; |
930c8682 PB |
252 | uint8_t buf[2048]; |
253 | int len; | |
254 | ||
24859b68 | 255 | do { |
930c8682 | 256 | eth_tx_desc_get(desc_addr, &desc); |
07b064e9 | 257 | next_desc = desc.next; |
930c8682 PB |
258 | if (desc.cmdstat & MP_ETH_TX_OWN) { |
259 | len = desc.bytes; | |
260 | if (len < 2048) { | |
261 | cpu_physical_memory_read(desc.buffer, buf, len); | |
b356f76d | 262 | qemu_send_packet(qemu_get_queue(s->nic), buf, len); |
930c8682 PB |
263 | } |
264 | desc.cmdstat &= ~MP_ETH_TX_OWN; | |
24859b68 | 265 | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); |
930c8682 | 266 | eth_tx_desc_put(desc_addr, &desc); |
24859b68 | 267 | } |
07b064e9 | 268 | desc_addr = next_desc; |
930c8682 | 269 | } while (desc_addr != s->tx_queue[queue_index]); |
24859b68 AZ |
270 | } |
271 | ||
a8170e5e | 272 | static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, |
19b4a424 | 273 | unsigned size) |
24859b68 AZ |
274 | { |
275 | mv88w8618_eth_state *s = opaque; | |
276 | ||
24859b68 AZ |
277 | switch (offset) { |
278 | case MP_ETH_SMIR: | |
279 | if (s->smir & MP_ETH_SMIR_OPCODE) { | |
280 | switch (s->smir & MP_ETH_SMIR_ADDR) { | |
281 | case MP_ETH_PHY1_BMSR: | |
282 | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | | |
283 | MP_ETH_SMIR_RDVALID; | |
284 | case MP_ETH_PHY1_PHYSID1: | |
285 | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; | |
286 | case MP_ETH_PHY1_PHYSID2: | |
287 | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; | |
288 | default: | |
289 | return MP_ETH_SMIR_RDVALID; | |
290 | } | |
291 | } | |
292 | return 0; | |
293 | ||
294 | case MP_ETH_ICR: | |
295 | return s->icr; | |
296 | ||
297 | case MP_ETH_IMR: | |
298 | return s->imr; | |
299 | ||
300 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 301 | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
24859b68 AZ |
302 | |
303 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
930c8682 | 304 | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
24859b68 | 305 | |
cf143ad3 | 306 | case MP_ETH_CTDP0 ... MP_ETH_CTDP1: |
930c8682 | 307 | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
24859b68 AZ |
308 | |
309 | default: | |
310 | return 0; | |
311 | } | |
312 | } | |
313 | ||
a8170e5e | 314 | static void mv88w8618_eth_write(void *opaque, hwaddr offset, |
19b4a424 | 315 | uint64_t value, unsigned size) |
24859b68 AZ |
316 | { |
317 | mv88w8618_eth_state *s = opaque; | |
318 | ||
24859b68 AZ |
319 | switch (offset) { |
320 | case MP_ETH_SMIR: | |
321 | s->smir = value; | |
322 | break; | |
323 | ||
324 | case MP_ETH_PCXR: | |
325 | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; | |
326 | break; | |
327 | ||
328 | case MP_ETH_SDCMR: | |
49fedd0d | 329 | if (value & MP_ETH_CMD_TXHI) { |
24859b68 | 330 | eth_send(s, 1); |
49fedd0d JK |
331 | } |
332 | if (value & MP_ETH_CMD_TXLO) { | |
24859b68 | 333 | eth_send(s, 0); |
49fedd0d JK |
334 | } |
335 | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { | |
24859b68 | 336 | qemu_irq_raise(s->irq); |
49fedd0d | 337 | } |
24859b68 AZ |
338 | break; |
339 | ||
340 | case MP_ETH_ICR: | |
341 | s->icr &= value; | |
342 | break; | |
343 | ||
344 | case MP_ETH_IMR: | |
345 | s->imr = value; | |
49fedd0d | 346 | if (s->icr & s->imr) { |
24859b68 | 347 | qemu_irq_raise(s->irq); |
49fedd0d | 348 | } |
24859b68 AZ |
349 | break; |
350 | ||
351 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 352 | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; |
24859b68 AZ |
353 | break; |
354 | ||
355 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
356 | s->rx_queue[(offset - MP_ETH_CRDP0)/4] = | |
930c8682 | 357 | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; |
24859b68 AZ |
358 | break; |
359 | ||
cf143ad3 | 360 | case MP_ETH_CTDP0 ... MP_ETH_CTDP1: |
930c8682 | 361 | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; |
24859b68 AZ |
362 | break; |
363 | } | |
364 | } | |
365 | ||
19b4a424 AK |
366 | static const MemoryRegionOps mv88w8618_eth_ops = { |
367 | .read = mv88w8618_eth_read, | |
368 | .write = mv88w8618_eth_write, | |
369 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
370 | }; |
371 | ||
4e68f7a0 | 372 | static void eth_cleanup(NetClientState *nc) |
b946a153 | 373 | { |
cc1f0f45 | 374 | mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); |
b946a153 | 375 | |
3a94dd18 | 376 | s->nic = NULL; |
b946a153 AL |
377 | } |
378 | ||
3a94dd18 | 379 | static NetClientInfo net_mv88w8618_info = { |
f394b2e2 | 380 | .type = NET_CLIENT_DRIVER_NIC, |
3a94dd18 | 381 | .size = sizeof(NICState), |
3a94dd18 MM |
382 | .receive = eth_receive, |
383 | .cleanup = eth_cleanup, | |
384 | }; | |
385 | ||
ece71994 | 386 | static void mv88w8618_eth_init(Object *obj) |
24859b68 | 387 | { |
ece71994 | 388 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
a77d90e6 AF |
389 | DeviceState *dev = DEVICE(sbd); |
390 | mv88w8618_eth_state *s = MV88W8618_ETH(dev); | |
0ae18cee | 391 | |
a77d90e6 | 392 | sysbus_init_irq(sbd, &s->irq); |
ece71994 | 393 | memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s, |
64bde0f3 | 394 | "mv88w8618-eth", MP_ETH_SIZE); |
a77d90e6 | 395 | sysbus_init_mmio(sbd, &s->iomem); |
ece71994 XZ |
396 | } |
397 | ||
398 | static void mv88w8618_eth_realize(DeviceState *dev, Error **errp) | |
399 | { | |
400 | mv88w8618_eth_state *s = MV88W8618_ETH(dev); | |
401 | ||
402 | s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, | |
403 | object_get_typename(OBJECT(dev)), dev->id, s); | |
24859b68 AZ |
404 | } |
405 | ||
d5b61ddd JK |
406 | static const VMStateDescription mv88w8618_eth_vmsd = { |
407 | .name = "mv88w8618_eth", | |
408 | .version_id = 1, | |
409 | .minimum_version_id = 1, | |
d5b61ddd JK |
410 | .fields = (VMStateField[]) { |
411 | VMSTATE_UINT32(smir, mv88w8618_eth_state), | |
412 | VMSTATE_UINT32(icr, mv88w8618_eth_state), | |
413 | VMSTATE_UINT32(imr, mv88w8618_eth_state), | |
414 | VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), | |
415 | VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), | |
416 | VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), | |
417 | VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), | |
418 | VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), | |
419 | VMSTATE_END_OF_LIST() | |
420 | } | |
421 | }; | |
422 | ||
999e12bb AL |
423 | static Property mv88w8618_eth_properties[] = { |
424 | DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), | |
425 | DEFINE_PROP_END_OF_LIST(), | |
426 | }; | |
427 | ||
428 | static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) | |
429 | { | |
39bffca2 | 430 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 431 | |
39bffca2 AL |
432 | dc->vmsd = &mv88w8618_eth_vmsd; |
433 | dc->props = mv88w8618_eth_properties; | |
ece71994 | 434 | dc->realize = mv88w8618_eth_realize; |
999e12bb AL |
435 | } |
436 | ||
8c43a6f0 | 437 | static const TypeInfo mv88w8618_eth_info = { |
a77d90e6 | 438 | .name = TYPE_MV88W8618_ETH, |
39bffca2 AL |
439 | .parent = TYPE_SYS_BUS_DEVICE, |
440 | .instance_size = sizeof(mv88w8618_eth_state), | |
ece71994 | 441 | .instance_init = mv88w8618_eth_init, |
39bffca2 | 442 | .class_init = mv88w8618_eth_class_init, |
d5b61ddd JK |
443 | }; |
444 | ||
24859b68 AZ |
445 | /* LCD register offsets */ |
446 | #define MP_LCD_IRQCTRL 0x180 | |
447 | #define MP_LCD_IRQSTAT 0x184 | |
448 | #define MP_LCD_SPICTRL 0x1ac | |
449 | #define MP_LCD_INST 0x1bc | |
450 | #define MP_LCD_DATA 0x1c0 | |
451 | ||
452 | /* Mode magics */ | |
453 | #define MP_LCD_SPI_DATA 0x00100011 | |
454 | #define MP_LCD_SPI_CMD 0x00104011 | |
455 | #define MP_LCD_SPI_INVALID 0x00000000 | |
456 | ||
457 | /* Commmands */ | |
458 | #define MP_LCD_INST_SETPAGE0 0xB0 | |
459 | /* ... */ | |
460 | #define MP_LCD_INST_SETPAGE7 0xB7 | |
461 | ||
462 | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ | |
463 | ||
2cca58fd AF |
464 | #define TYPE_MUSICPAL_LCD "musicpal_lcd" |
465 | #define MUSICPAL_LCD(obj) \ | |
466 | OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD) | |
467 | ||
24859b68 | 468 | typedef struct musicpal_lcd_state { |
2cca58fd AF |
469 | /*< private >*/ |
470 | SysBusDevice parent_obj; | |
471 | /*< public >*/ | |
472 | ||
19b4a424 | 473 | MemoryRegion iomem; |
343ec8e4 | 474 | uint32_t brightness; |
24859b68 AZ |
475 | uint32_t mode; |
476 | uint32_t irqctrl; | |
d5b61ddd JK |
477 | uint32_t page; |
478 | uint32_t page_off; | |
c78f7137 | 479 | QemuConsole *con; |
24859b68 AZ |
480 | uint8_t video_ram[128*64/8]; |
481 | } musicpal_lcd_state; | |
482 | ||
343ec8e4 | 483 | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) |
24859b68 | 484 | { |
343ec8e4 BC |
485 | switch (s->brightness) { |
486 | case 7: | |
487 | return col; | |
488 | case 0: | |
24859b68 | 489 | return 0; |
24859b68 | 490 | default: |
343ec8e4 | 491 | return (col * s->brightness) / 7; |
24859b68 AZ |
492 | } |
493 | } | |
494 | ||
0266f2c7 AZ |
495 | #define SET_LCD_PIXEL(depth, type) \ |
496 | static inline void glue(set_lcd_pixel, depth) \ | |
497 | (musicpal_lcd_state *s, int x, int y, type col) \ | |
498 | { \ | |
499 | int dx, dy; \ | |
c78f7137 GH |
500 | DisplaySurface *surface = qemu_console_surface(s->con); \ |
501 | type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ | |
0266f2c7 AZ |
502 | \ |
503 | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ | |
504 | for (dx = 0; dx < 3; dx++, pixel++) \ | |
505 | *pixel = col; \ | |
24859b68 | 506 | } |
0266f2c7 AZ |
507 | SET_LCD_PIXEL(8, uint8_t) |
508 | SET_LCD_PIXEL(16, uint16_t) | |
509 | SET_LCD_PIXEL(32, uint32_t) | |
510 | ||
24859b68 AZ |
511 | static void lcd_refresh(void *opaque) |
512 | { | |
513 | musicpal_lcd_state *s = opaque; | |
c78f7137 | 514 | DisplaySurface *surface = qemu_console_surface(s->con); |
0266f2c7 | 515 | int x, y, col; |
24859b68 | 516 | |
c78f7137 | 517 | switch (surface_bits_per_pixel(surface)) { |
0266f2c7 AZ |
518 | case 0: |
519 | return; | |
520 | #define LCD_REFRESH(depth, func) \ | |
521 | case depth: \ | |
343ec8e4 BC |
522 | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
523 | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ | |
524 | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ | |
49fedd0d JK |
525 | for (x = 0; x < 128; x++) { \ |
526 | for (y = 0; y < 64; y++) { \ | |
527 | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ | |
0266f2c7 | 528 | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
49fedd0d | 529 | } else { \ |
0266f2c7 | 530 | glue(set_lcd_pixel, depth)(s, x, y, 0); \ |
49fedd0d JK |
531 | } \ |
532 | } \ | |
533 | } \ | |
0266f2c7 AZ |
534 | break; |
535 | LCD_REFRESH(8, rgb_to_pixel8) | |
536 | LCD_REFRESH(16, rgb_to_pixel16) | |
c78f7137 | 537 | LCD_REFRESH(32, (is_surface_bgr(surface) ? |
bf9b48af | 538 | rgb_to_pixel32bgr : rgb_to_pixel32)) |
0266f2c7 | 539 | default: |
2ac71179 | 540 | hw_error("unsupported colour depth %i\n", |
c78f7137 | 541 | surface_bits_per_pixel(surface)); |
0266f2c7 | 542 | } |
24859b68 | 543 | |
c78f7137 | 544 | dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); |
24859b68 AZ |
545 | } |
546 | ||
167bc3d2 AZ |
547 | static void lcd_invalidate(void *opaque) |
548 | { | |
167bc3d2 AZ |
549 | } |
550 | ||
2c79fed3 | 551 | static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) |
343ec8e4 | 552 | { |
243cd13c | 553 | musicpal_lcd_state *s = opaque; |
343ec8e4 BC |
554 | s->brightness &= ~(1 << irq); |
555 | s->brightness |= level << irq; | |
556 | } | |
557 | ||
a8170e5e | 558 | static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, |
19b4a424 | 559 | unsigned size) |
24859b68 AZ |
560 | { |
561 | musicpal_lcd_state *s = opaque; | |
562 | ||
24859b68 AZ |
563 | switch (offset) { |
564 | case MP_LCD_IRQCTRL: | |
565 | return s->irqctrl; | |
566 | ||
567 | default: | |
568 | return 0; | |
569 | } | |
570 | } | |
571 | ||
a8170e5e | 572 | static void musicpal_lcd_write(void *opaque, hwaddr offset, |
19b4a424 | 573 | uint64_t value, unsigned size) |
24859b68 AZ |
574 | { |
575 | musicpal_lcd_state *s = opaque; | |
576 | ||
24859b68 AZ |
577 | switch (offset) { |
578 | case MP_LCD_IRQCTRL: | |
579 | s->irqctrl = value; | |
580 | break; | |
581 | ||
582 | case MP_LCD_SPICTRL: | |
49fedd0d | 583 | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { |
24859b68 | 584 | s->mode = value; |
49fedd0d | 585 | } else { |
24859b68 | 586 | s->mode = MP_LCD_SPI_INVALID; |
49fedd0d | 587 | } |
24859b68 AZ |
588 | break; |
589 | ||
590 | case MP_LCD_INST: | |
591 | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { | |
592 | s->page = value - MP_LCD_INST_SETPAGE0; | |
593 | s->page_off = 0; | |
594 | } | |
595 | break; | |
596 | ||
597 | case MP_LCD_DATA: | |
598 | if (s->mode == MP_LCD_SPI_CMD) { | |
599 | if (value >= MP_LCD_INST_SETPAGE0 && | |
600 | value <= MP_LCD_INST_SETPAGE7) { | |
601 | s->page = value - MP_LCD_INST_SETPAGE0; | |
602 | s->page_off = 0; | |
603 | } | |
604 | } else if (s->mode == MP_LCD_SPI_DATA) { | |
605 | s->video_ram[s->page*128 + s->page_off] = value; | |
606 | s->page_off = (s->page_off + 1) & 127; | |
607 | } | |
608 | break; | |
609 | } | |
610 | } | |
611 | ||
19b4a424 AK |
612 | static const MemoryRegionOps musicpal_lcd_ops = { |
613 | .read = musicpal_lcd_read, | |
614 | .write = musicpal_lcd_write, | |
615 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
616 | }; |
617 | ||
380cd056 GH |
618 | static const GraphicHwOps musicpal_gfx_ops = { |
619 | .invalidate = lcd_invalidate, | |
620 | .gfx_update = lcd_refresh, | |
621 | }; | |
622 | ||
ece71994 XZ |
623 | static void musicpal_lcd_realize(DeviceState *dev, Error **errp) |
624 | { | |
625 | musicpal_lcd_state *s = MUSICPAL_LCD(dev); | |
626 | s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s); | |
627 | qemu_console_resize(s->con, 128 * 3, 64 * 3); | |
628 | } | |
629 | ||
630 | static void musicpal_lcd_init(Object *obj) | |
24859b68 | 631 | { |
ece71994 | 632 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
2cca58fd AF |
633 | DeviceState *dev = DEVICE(sbd); |
634 | musicpal_lcd_state *s = MUSICPAL_LCD(dev); | |
24859b68 | 635 | |
343ec8e4 BC |
636 | s->brightness = 7; |
637 | ||
ece71994 | 638 | memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s, |
19b4a424 | 639 | "musicpal-lcd", MP_LCD_SIZE); |
2cca58fd | 640 | sysbus_init_mmio(sbd, &s->iomem); |
24859b68 | 641 | |
2cca58fd | 642 | qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); |
24859b68 AZ |
643 | } |
644 | ||
d5b61ddd JK |
645 | static const VMStateDescription musicpal_lcd_vmsd = { |
646 | .name = "musicpal_lcd", | |
647 | .version_id = 1, | |
648 | .minimum_version_id = 1, | |
d5b61ddd JK |
649 | .fields = (VMStateField[]) { |
650 | VMSTATE_UINT32(brightness, musicpal_lcd_state), | |
651 | VMSTATE_UINT32(mode, musicpal_lcd_state), | |
652 | VMSTATE_UINT32(irqctrl, musicpal_lcd_state), | |
653 | VMSTATE_UINT32(page, musicpal_lcd_state), | |
654 | VMSTATE_UINT32(page_off, musicpal_lcd_state), | |
655 | VMSTATE_BUFFER(video_ram, musicpal_lcd_state), | |
656 | VMSTATE_END_OF_LIST() | |
657 | } | |
658 | }; | |
659 | ||
999e12bb AL |
660 | static void musicpal_lcd_class_init(ObjectClass *klass, void *data) |
661 | { | |
39bffca2 | 662 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 663 | |
39bffca2 | 664 | dc->vmsd = &musicpal_lcd_vmsd; |
ece71994 | 665 | dc->realize = musicpal_lcd_realize; |
999e12bb AL |
666 | } |
667 | ||
8c43a6f0 | 668 | static const TypeInfo musicpal_lcd_info = { |
2cca58fd | 669 | .name = TYPE_MUSICPAL_LCD, |
39bffca2 AL |
670 | .parent = TYPE_SYS_BUS_DEVICE, |
671 | .instance_size = sizeof(musicpal_lcd_state), | |
ece71994 | 672 | .instance_init = musicpal_lcd_init, |
39bffca2 | 673 | .class_init = musicpal_lcd_class_init, |
d5b61ddd JK |
674 | }; |
675 | ||
24859b68 AZ |
676 | /* PIC register offsets */ |
677 | #define MP_PIC_STATUS 0x00 | |
678 | #define MP_PIC_ENABLE_SET 0x08 | |
679 | #define MP_PIC_ENABLE_CLR 0x0C | |
680 | ||
c7bd0fd9 AF |
681 | #define TYPE_MV88W8618_PIC "mv88w8618_pic" |
682 | #define MV88W8618_PIC(obj) \ | |
683 | OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC) | |
684 | ||
685 | typedef struct mv88w8618_pic_state { | |
686 | /*< private >*/ | |
687 | SysBusDevice parent_obj; | |
688 | /*< public >*/ | |
689 | ||
19b4a424 | 690 | MemoryRegion iomem; |
24859b68 AZ |
691 | uint32_t level; |
692 | uint32_t enabled; | |
693 | qemu_irq parent_irq; | |
694 | } mv88w8618_pic_state; | |
695 | ||
696 | static void mv88w8618_pic_update(mv88w8618_pic_state *s) | |
697 | { | |
698 | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); | |
699 | } | |
700 | ||
701 | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) | |
702 | { | |
703 | mv88w8618_pic_state *s = opaque; | |
704 | ||
49fedd0d | 705 | if (level) { |
24859b68 | 706 | s->level |= 1 << irq; |
49fedd0d | 707 | } else { |
24859b68 | 708 | s->level &= ~(1 << irq); |
49fedd0d | 709 | } |
24859b68 AZ |
710 | mv88w8618_pic_update(s); |
711 | } | |
712 | ||
a8170e5e | 713 | static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, |
19b4a424 | 714 | unsigned size) |
24859b68 AZ |
715 | { |
716 | mv88w8618_pic_state *s = opaque; | |
717 | ||
24859b68 AZ |
718 | switch (offset) { |
719 | case MP_PIC_STATUS: | |
720 | return s->level & s->enabled; | |
721 | ||
722 | default: | |
723 | return 0; | |
724 | } | |
725 | } | |
726 | ||
a8170e5e | 727 | static void mv88w8618_pic_write(void *opaque, hwaddr offset, |
19b4a424 | 728 | uint64_t value, unsigned size) |
24859b68 AZ |
729 | { |
730 | mv88w8618_pic_state *s = opaque; | |
731 | ||
24859b68 AZ |
732 | switch (offset) { |
733 | case MP_PIC_ENABLE_SET: | |
734 | s->enabled |= value; | |
735 | break; | |
736 | ||
737 | case MP_PIC_ENABLE_CLR: | |
738 | s->enabled &= ~value; | |
739 | s->level &= ~value; | |
740 | break; | |
741 | } | |
742 | mv88w8618_pic_update(s); | |
743 | } | |
744 | ||
d5b61ddd | 745 | static void mv88w8618_pic_reset(DeviceState *d) |
24859b68 | 746 | { |
c7bd0fd9 | 747 | mv88w8618_pic_state *s = MV88W8618_PIC(d); |
24859b68 AZ |
748 | |
749 | s->level = 0; | |
750 | s->enabled = 0; | |
751 | } | |
752 | ||
19b4a424 AK |
753 | static const MemoryRegionOps mv88w8618_pic_ops = { |
754 | .read = mv88w8618_pic_read, | |
755 | .write = mv88w8618_pic_write, | |
756 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
757 | }; |
758 | ||
ece71994 | 759 | static void mv88w8618_pic_init(Object *obj) |
24859b68 | 760 | { |
ece71994 | 761 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
c7bd0fd9 | 762 | mv88w8618_pic_state *s = MV88W8618_PIC(dev); |
24859b68 | 763 | |
c7bd0fd9 | 764 | qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); |
b47b50fa | 765 | sysbus_init_irq(dev, &s->parent_irq); |
ece71994 | 766 | memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s, |
19b4a424 | 767 | "musicpal-pic", MP_PIC_SIZE); |
750ecd44 | 768 | sysbus_init_mmio(dev, &s->iomem); |
24859b68 AZ |
769 | } |
770 | ||
d5b61ddd JK |
771 | static const VMStateDescription mv88w8618_pic_vmsd = { |
772 | .name = "mv88w8618_pic", | |
773 | .version_id = 1, | |
774 | .minimum_version_id = 1, | |
d5b61ddd JK |
775 | .fields = (VMStateField[]) { |
776 | VMSTATE_UINT32(level, mv88w8618_pic_state), | |
777 | VMSTATE_UINT32(enabled, mv88w8618_pic_state), | |
778 | VMSTATE_END_OF_LIST() | |
779 | } | |
780 | }; | |
781 | ||
999e12bb AL |
782 | static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) |
783 | { | |
39bffca2 | 784 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 785 | |
39bffca2 AL |
786 | dc->reset = mv88w8618_pic_reset; |
787 | dc->vmsd = &mv88w8618_pic_vmsd; | |
999e12bb AL |
788 | } |
789 | ||
8c43a6f0 | 790 | static const TypeInfo mv88w8618_pic_info = { |
c7bd0fd9 | 791 | .name = TYPE_MV88W8618_PIC, |
39bffca2 AL |
792 | .parent = TYPE_SYS_BUS_DEVICE, |
793 | .instance_size = sizeof(mv88w8618_pic_state), | |
ece71994 | 794 | .instance_init = mv88w8618_pic_init, |
39bffca2 | 795 | .class_init = mv88w8618_pic_class_init, |
d5b61ddd JK |
796 | }; |
797 | ||
24859b68 AZ |
798 | /* PIT register offsets */ |
799 | #define MP_PIT_TIMER1_LENGTH 0x00 | |
800 | /* ... */ | |
801 | #define MP_PIT_TIMER4_LENGTH 0x0C | |
802 | #define MP_PIT_CONTROL 0x10 | |
803 | #define MP_PIT_TIMER1_VALUE 0x14 | |
804 | /* ... */ | |
805 | #define MP_PIT_TIMER4_VALUE 0x20 | |
806 | #define MP_BOARD_RESET 0x34 | |
807 | ||
808 | /* Magic board reset value (probably some watchdog behind it) */ | |
809 | #define MP_BOARD_RESET_MAGIC 0x10000 | |
810 | ||
811 | typedef struct mv88w8618_timer_state { | |
b47b50fa | 812 | ptimer_state *ptimer; |
24859b68 AZ |
813 | uint32_t limit; |
814 | int freq; | |
815 | qemu_irq irq; | |
816 | } mv88w8618_timer_state; | |
817 | ||
4adc8541 AF |
818 | #define TYPE_MV88W8618_PIT "mv88w8618_pit" |
819 | #define MV88W8618_PIT(obj) \ | |
820 | OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT) | |
821 | ||
24859b68 | 822 | typedef struct mv88w8618_pit_state { |
4adc8541 AF |
823 | /*< private >*/ |
824 | SysBusDevice parent_obj; | |
825 | /*< public >*/ | |
826 | ||
19b4a424 | 827 | MemoryRegion iomem; |
b47b50fa | 828 | mv88w8618_timer_state timer[4]; |
24859b68 AZ |
829 | } mv88w8618_pit_state; |
830 | ||
831 | static void mv88w8618_timer_tick(void *opaque) | |
832 | { | |
833 | mv88w8618_timer_state *s = opaque; | |
834 | ||
835 | qemu_irq_raise(s->irq); | |
836 | } | |
837 | ||
b47b50fa PB |
838 | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
839 | uint32_t freq) | |
24859b68 | 840 | { |
24859b68 AZ |
841 | QEMUBH *bh; |
842 | ||
b47b50fa | 843 | sysbus_init_irq(dev, &s->irq); |
24859b68 AZ |
844 | s->freq = freq; |
845 | ||
846 | bh = qemu_bh_new(mv88w8618_timer_tick, s); | |
e7ea81c3 | 847 | s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
24859b68 AZ |
848 | } |
849 | ||
a8170e5e | 850 | static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, |
19b4a424 | 851 | unsigned size) |
24859b68 AZ |
852 | { |
853 | mv88w8618_pit_state *s = opaque; | |
854 | mv88w8618_timer_state *t; | |
855 | ||
24859b68 AZ |
856 | switch (offset) { |
857 | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: | |
b47b50fa PB |
858 | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; |
859 | return ptimer_get_count(t->ptimer); | |
24859b68 AZ |
860 | |
861 | default: | |
862 | return 0; | |
863 | } | |
864 | } | |
865 | ||
a8170e5e | 866 | static void mv88w8618_pit_write(void *opaque, hwaddr offset, |
19b4a424 | 867 | uint64_t value, unsigned size) |
24859b68 AZ |
868 | { |
869 | mv88w8618_pit_state *s = opaque; | |
870 | mv88w8618_timer_state *t; | |
871 | int i; | |
872 | ||
24859b68 AZ |
873 | switch (offset) { |
874 | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: | |
b47b50fa | 875 | t = &s->timer[offset >> 2]; |
24859b68 | 876 | t->limit = value; |
c88d6bde JK |
877 | if (t->limit > 0) { |
878 | ptimer_set_limit(t->ptimer, t->limit, 1); | |
879 | } else { | |
880 | ptimer_stop(t->ptimer); | |
881 | } | |
24859b68 AZ |
882 | break; |
883 | ||
884 | case MP_PIT_CONTROL: | |
885 | for (i = 0; i < 4; i++) { | |
c88d6bde JK |
886 | t = &s->timer[i]; |
887 | if (value & 0xf && t->limit > 0) { | |
b47b50fa PB |
888 | ptimer_set_limit(t->ptimer, t->limit, 0); |
889 | ptimer_set_freq(t->ptimer, t->freq); | |
890 | ptimer_run(t->ptimer, 0); | |
c88d6bde JK |
891 | } else { |
892 | ptimer_stop(t->ptimer); | |
24859b68 AZ |
893 | } |
894 | value >>= 4; | |
895 | } | |
896 | break; | |
897 | ||
898 | case MP_BOARD_RESET: | |
49fedd0d | 899 | if (value == MP_BOARD_RESET_MAGIC) { |
cf83f140 | 900 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
49fedd0d | 901 | } |
24859b68 AZ |
902 | break; |
903 | } | |
904 | } | |
905 | ||
d5b61ddd | 906 | static void mv88w8618_pit_reset(DeviceState *d) |
c88d6bde | 907 | { |
4adc8541 | 908 | mv88w8618_pit_state *s = MV88W8618_PIT(d); |
c88d6bde JK |
909 | int i; |
910 | ||
911 | for (i = 0; i < 4; i++) { | |
912 | ptimer_stop(s->timer[i].ptimer); | |
913 | s->timer[i].limit = 0; | |
914 | } | |
915 | } | |
916 | ||
19b4a424 AK |
917 | static const MemoryRegionOps mv88w8618_pit_ops = { |
918 | .read = mv88w8618_pit_read, | |
919 | .write = mv88w8618_pit_write, | |
920 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
921 | }; |
922 | ||
ece71994 | 923 | static void mv88w8618_pit_init(Object *obj) |
24859b68 | 924 | { |
ece71994 | 925 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
4adc8541 | 926 | mv88w8618_pit_state *s = MV88W8618_PIT(dev); |
b47b50fa | 927 | int i; |
24859b68 | 928 | |
24859b68 AZ |
929 | /* Letting them all run at 1 MHz is likely just a pragmatic |
930 | * simplification. */ | |
b47b50fa PB |
931 | for (i = 0; i < 4; i++) { |
932 | mv88w8618_timer_init(dev, &s->timer[i], 1000000); | |
933 | } | |
24859b68 | 934 | |
ece71994 | 935 | memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s, |
19b4a424 | 936 | "musicpal-pit", MP_PIT_SIZE); |
750ecd44 | 937 | sysbus_init_mmio(dev, &s->iomem); |
24859b68 AZ |
938 | } |
939 | ||
d5b61ddd JK |
940 | static const VMStateDescription mv88w8618_timer_vmsd = { |
941 | .name = "timer", | |
942 | .version_id = 1, | |
943 | .minimum_version_id = 1, | |
d5b61ddd JK |
944 | .fields = (VMStateField[]) { |
945 | VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), | |
946 | VMSTATE_UINT32(limit, mv88w8618_timer_state), | |
947 | VMSTATE_END_OF_LIST() | |
948 | } | |
949 | }; | |
950 | ||
951 | static const VMStateDescription mv88w8618_pit_vmsd = { | |
952 | .name = "mv88w8618_pit", | |
953 | .version_id = 1, | |
954 | .minimum_version_id = 1, | |
d5b61ddd JK |
955 | .fields = (VMStateField[]) { |
956 | VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, | |
957 | mv88w8618_timer_vmsd, mv88w8618_timer_state), | |
958 | VMSTATE_END_OF_LIST() | |
959 | } | |
960 | }; | |
961 | ||
999e12bb AL |
962 | static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) |
963 | { | |
39bffca2 | 964 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 965 | |
39bffca2 AL |
966 | dc->reset = mv88w8618_pit_reset; |
967 | dc->vmsd = &mv88w8618_pit_vmsd; | |
999e12bb AL |
968 | } |
969 | ||
8c43a6f0 | 970 | static const TypeInfo mv88w8618_pit_info = { |
4adc8541 | 971 | .name = TYPE_MV88W8618_PIT, |
39bffca2 AL |
972 | .parent = TYPE_SYS_BUS_DEVICE, |
973 | .instance_size = sizeof(mv88w8618_pit_state), | |
ece71994 | 974 | .instance_init = mv88w8618_pit_init, |
39bffca2 | 975 | .class_init = mv88w8618_pit_class_init, |
c88d6bde JK |
976 | }; |
977 | ||
24859b68 AZ |
978 | /* Flash config register offsets */ |
979 | #define MP_FLASHCFG_CFGR0 0x04 | |
980 | ||
5952b01c AF |
981 | #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" |
982 | #define MV88W8618_FLASHCFG(obj) \ | |
983 | OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG) | |
984 | ||
24859b68 | 985 | typedef struct mv88w8618_flashcfg_state { |
5952b01c AF |
986 | /*< private >*/ |
987 | SysBusDevice parent_obj; | |
988 | /*< public >*/ | |
989 | ||
19b4a424 | 990 | MemoryRegion iomem; |
24859b68 AZ |
991 | uint32_t cfgr0; |
992 | } mv88w8618_flashcfg_state; | |
993 | ||
19b4a424 | 994 | static uint64_t mv88w8618_flashcfg_read(void *opaque, |
a8170e5e | 995 | hwaddr offset, |
19b4a424 | 996 | unsigned size) |
24859b68 AZ |
997 | { |
998 | mv88w8618_flashcfg_state *s = opaque; | |
999 | ||
24859b68 AZ |
1000 | switch (offset) { |
1001 | case MP_FLASHCFG_CFGR0: | |
1002 | return s->cfgr0; | |
1003 | ||
1004 | default: | |
1005 | return 0; | |
1006 | } | |
1007 | } | |
1008 | ||
a8170e5e | 1009 | static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, |
19b4a424 | 1010 | uint64_t value, unsigned size) |
24859b68 AZ |
1011 | { |
1012 | mv88w8618_flashcfg_state *s = opaque; | |
1013 | ||
24859b68 AZ |
1014 | switch (offset) { |
1015 | case MP_FLASHCFG_CFGR0: | |
1016 | s->cfgr0 = value; | |
1017 | break; | |
1018 | } | |
1019 | } | |
1020 | ||
19b4a424 AK |
1021 | static const MemoryRegionOps mv88w8618_flashcfg_ops = { |
1022 | .read = mv88w8618_flashcfg_read, | |
1023 | .write = mv88w8618_flashcfg_write, | |
1024 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
1025 | }; |
1026 | ||
ece71994 | 1027 | static void mv88w8618_flashcfg_init(Object *obj) |
24859b68 | 1028 | { |
ece71994 | 1029 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
5952b01c | 1030 | mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); |
24859b68 | 1031 | |
24859b68 | 1032 | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
ece71994 | 1033 | memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s, |
19b4a424 | 1034 | "musicpal-flashcfg", MP_FLASHCFG_SIZE); |
750ecd44 | 1035 | sysbus_init_mmio(dev, &s->iomem); |
24859b68 AZ |
1036 | } |
1037 | ||
d5b61ddd JK |
1038 | static const VMStateDescription mv88w8618_flashcfg_vmsd = { |
1039 | .name = "mv88w8618_flashcfg", | |
1040 | .version_id = 1, | |
1041 | .minimum_version_id = 1, | |
d5b61ddd JK |
1042 | .fields = (VMStateField[]) { |
1043 | VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), | |
1044 | VMSTATE_END_OF_LIST() | |
1045 | } | |
1046 | }; | |
1047 | ||
999e12bb AL |
1048 | static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) |
1049 | { | |
39bffca2 | 1050 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1051 | |
39bffca2 | 1052 | dc->vmsd = &mv88w8618_flashcfg_vmsd; |
999e12bb AL |
1053 | } |
1054 | ||
8c43a6f0 | 1055 | static const TypeInfo mv88w8618_flashcfg_info = { |
5952b01c | 1056 | .name = TYPE_MV88W8618_FLASHCFG, |
39bffca2 AL |
1057 | .parent = TYPE_SYS_BUS_DEVICE, |
1058 | .instance_size = sizeof(mv88w8618_flashcfg_state), | |
ece71994 | 1059 | .instance_init = mv88w8618_flashcfg_init, |
39bffca2 | 1060 | .class_init = mv88w8618_flashcfg_class_init, |
d5b61ddd JK |
1061 | }; |
1062 | ||
718ec0be | 1063 | /* Misc register offsets */ |
1064 | #define MP_MISC_BOARD_REVISION 0x18 | |
1065 | ||
1066 | #define MP_BOARD_REVISION 0x31 | |
1067 | ||
a86f200a PM |
1068 | typedef struct { |
1069 | SysBusDevice parent_obj; | |
1070 | MemoryRegion iomem; | |
1071 | } MusicPalMiscState; | |
1072 | ||
1073 | #define TYPE_MUSICPAL_MISC "musicpal-misc" | |
1074 | #define MUSICPAL_MISC(obj) \ | |
1075 | OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC) | |
1076 | ||
a8170e5e | 1077 | static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, |
19b4a424 | 1078 | unsigned size) |
718ec0be | 1079 | { |
1080 | switch (offset) { | |
1081 | case MP_MISC_BOARD_REVISION: | |
1082 | return MP_BOARD_REVISION; | |
1083 | ||
1084 | default: | |
1085 | return 0; | |
1086 | } | |
1087 | } | |
1088 | ||
a8170e5e | 1089 | static void musicpal_misc_write(void *opaque, hwaddr offset, |
19b4a424 | 1090 | uint64_t value, unsigned size) |
718ec0be | 1091 | { |
1092 | } | |
1093 | ||
19b4a424 AK |
1094 | static const MemoryRegionOps musicpal_misc_ops = { |
1095 | .read = musicpal_misc_read, | |
1096 | .write = musicpal_misc_write, | |
1097 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718ec0be | 1098 | }; |
1099 | ||
a86f200a | 1100 | static void musicpal_misc_init(Object *obj) |
718ec0be | 1101 | { |
a86f200a PM |
1102 | SysBusDevice *sd = SYS_BUS_DEVICE(obj); |
1103 | MusicPalMiscState *s = MUSICPAL_MISC(obj); | |
718ec0be | 1104 | |
64bde0f3 | 1105 | memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, |
19b4a424 | 1106 | "musicpal-misc", MP_MISC_SIZE); |
a86f200a | 1107 | sysbus_init_mmio(sd, &s->iomem); |
718ec0be | 1108 | } |
1109 | ||
a86f200a PM |
1110 | static const TypeInfo musicpal_misc_info = { |
1111 | .name = TYPE_MUSICPAL_MISC, | |
1112 | .parent = TYPE_SYS_BUS_DEVICE, | |
1113 | .instance_init = musicpal_misc_init, | |
1114 | .instance_size = sizeof(MusicPalMiscState), | |
1115 | }; | |
1116 | ||
718ec0be | 1117 | /* WLAN register offsets */ |
1118 | #define MP_WLAN_MAGIC1 0x11c | |
1119 | #define MP_WLAN_MAGIC2 0x124 | |
1120 | ||
a8170e5e | 1121 | static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, |
19b4a424 | 1122 | unsigned size) |
718ec0be | 1123 | { |
1124 | switch (offset) { | |
1125 | /* Workaround to allow loading the binary-only wlandrv.ko crap | |
1126 | * from the original Freecom firmware. */ | |
1127 | case MP_WLAN_MAGIC1: | |
1128 | return ~3; | |
1129 | case MP_WLAN_MAGIC2: | |
1130 | return -1; | |
1131 | ||
1132 | default: | |
1133 | return 0; | |
1134 | } | |
1135 | } | |
1136 | ||
a8170e5e | 1137 | static void mv88w8618_wlan_write(void *opaque, hwaddr offset, |
19b4a424 | 1138 | uint64_t value, unsigned size) |
718ec0be | 1139 | { |
1140 | } | |
1141 | ||
19b4a424 AK |
1142 | static const MemoryRegionOps mv88w8618_wlan_ops = { |
1143 | .read = mv88w8618_wlan_read, | |
1144 | .write =mv88w8618_wlan_write, | |
1145 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718ec0be | 1146 | }; |
1147 | ||
7f7420a0 | 1148 | static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) |
718ec0be | 1149 | { |
19b4a424 | 1150 | MemoryRegion *iomem = g_new(MemoryRegion, 1); |
24859b68 | 1151 | |
64bde0f3 | 1152 | memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, |
19b4a424 | 1153 | "musicpal-wlan", MP_WLAN_SIZE); |
7f7420a0 | 1154 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); |
718ec0be | 1155 | } |
24859b68 | 1156 | |
718ec0be | 1157 | /* GPIO register offsets */ |
1158 | #define MP_GPIO_OE_LO 0x008 | |
1159 | #define MP_GPIO_OUT_LO 0x00c | |
1160 | #define MP_GPIO_IN_LO 0x010 | |
708afdf3 JK |
1161 | #define MP_GPIO_IER_LO 0x014 |
1162 | #define MP_GPIO_IMR_LO 0x018 | |
718ec0be | 1163 | #define MP_GPIO_ISR_LO 0x020 |
1164 | #define MP_GPIO_OE_HI 0x508 | |
1165 | #define MP_GPIO_OUT_HI 0x50c | |
1166 | #define MP_GPIO_IN_HI 0x510 | |
708afdf3 JK |
1167 | #define MP_GPIO_IER_HI 0x514 |
1168 | #define MP_GPIO_IMR_HI 0x518 | |
718ec0be | 1169 | #define MP_GPIO_ISR_HI 0x520 |
24859b68 AZ |
1170 | |
1171 | /* GPIO bits & masks */ | |
24859b68 | 1172 | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
24859b68 | 1173 | #define MP_GPIO_I2C_DATA_BIT 29 |
24859b68 AZ |
1174 | #define MP_GPIO_I2C_CLOCK_BIT 30 |
1175 | ||
1176 | /* LCD brightness bits in GPIO_OE_HI */ | |
1177 | #define MP_OE_LCD_BRIGHTNESS 0x0007 | |
1178 | ||
7012d4b4 AF |
1179 | #define TYPE_MUSICPAL_GPIO "musicpal_gpio" |
1180 | #define MUSICPAL_GPIO(obj) \ | |
1181 | OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO) | |
1182 | ||
343ec8e4 | 1183 | typedef struct musicpal_gpio_state { |
7012d4b4 AF |
1184 | /*< private >*/ |
1185 | SysBusDevice parent_obj; | |
1186 | /*< public >*/ | |
1187 | ||
19b4a424 | 1188 | MemoryRegion iomem; |
343ec8e4 BC |
1189 | uint32_t lcd_brightness; |
1190 | uint32_t out_state; | |
1191 | uint32_t in_state; | |
708afdf3 JK |
1192 | uint32_t ier; |
1193 | uint32_t imr; | |
343ec8e4 | 1194 | uint32_t isr; |
343ec8e4 | 1195 | qemu_irq irq; |
708afdf3 | 1196 | qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
343ec8e4 BC |
1197 | } musicpal_gpio_state; |
1198 | ||
1199 | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { | |
1200 | int i; | |
1201 | uint32_t brightness; | |
1202 | ||
1203 | /* compute brightness ratio */ | |
1204 | switch (s->lcd_brightness) { | |
1205 | case 0x00000007: | |
1206 | brightness = 0; | |
1207 | break; | |
1208 | ||
1209 | case 0x00020000: | |
1210 | brightness = 1; | |
1211 | break; | |
1212 | ||
1213 | case 0x00020001: | |
1214 | brightness = 2; | |
1215 | break; | |
1216 | ||
1217 | case 0x00040000: | |
1218 | brightness = 3; | |
1219 | break; | |
1220 | ||
1221 | case 0x00010006: | |
1222 | brightness = 4; | |
1223 | break; | |
1224 | ||
1225 | case 0x00020005: | |
1226 | brightness = 5; | |
1227 | break; | |
1228 | ||
1229 | case 0x00040003: | |
1230 | brightness = 6; | |
1231 | break; | |
1232 | ||
1233 | case 0x00030004: | |
1234 | default: | |
1235 | brightness = 7; | |
1236 | } | |
1237 | ||
1238 | /* set lcd brightness GPIOs */ | |
49fedd0d | 1239 | for (i = 0; i <= 2; i++) { |
343ec8e4 | 1240 | qemu_set_irq(s->out[i], (brightness >> i) & 1); |
49fedd0d | 1241 | } |
343ec8e4 BC |
1242 | } |
1243 | ||
708afdf3 | 1244 | static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
343ec8e4 | 1245 | { |
243cd13c | 1246 | musicpal_gpio_state *s = opaque; |
708afdf3 JK |
1247 | uint32_t mask = 1 << pin; |
1248 | uint32_t delta = level << pin; | |
1249 | uint32_t old = s->in_state & mask; | |
343ec8e4 | 1250 | |
708afdf3 JK |
1251 | s->in_state &= ~mask; |
1252 | s->in_state |= delta; | |
343ec8e4 | 1253 | |
708afdf3 JK |
1254 | if ((old ^ delta) && |
1255 | ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { | |
1256 | s->isr = mask; | |
1257 | qemu_irq_raise(s->irq); | |
343ec8e4 | 1258 | } |
343ec8e4 BC |
1259 | } |
1260 | ||
a8170e5e | 1261 | static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, |
19b4a424 | 1262 | unsigned size) |
24859b68 | 1263 | { |
243cd13c | 1264 | musicpal_gpio_state *s = opaque; |
343ec8e4 | 1265 | |
24859b68 | 1266 | switch (offset) { |
24859b68 | 1267 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
343ec8e4 | 1268 | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; |
24859b68 AZ |
1269 | |
1270 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1271 | return s->out_state & 0xFFFF; |
24859b68 | 1272 | case MP_GPIO_OUT_HI: |
343ec8e4 | 1273 | return s->out_state >> 16; |
24859b68 AZ |
1274 | |
1275 | case MP_GPIO_IN_LO: | |
343ec8e4 | 1276 | return s->in_state & 0xFFFF; |
24859b68 | 1277 | case MP_GPIO_IN_HI: |
343ec8e4 | 1278 | return s->in_state >> 16; |
24859b68 | 1279 | |
708afdf3 JK |
1280 | case MP_GPIO_IER_LO: |
1281 | return s->ier & 0xFFFF; | |
1282 | case MP_GPIO_IER_HI: | |
1283 | return s->ier >> 16; | |
1284 | ||
1285 | case MP_GPIO_IMR_LO: | |
1286 | return s->imr & 0xFFFF; | |
1287 | case MP_GPIO_IMR_HI: | |
1288 | return s->imr >> 16; | |
1289 | ||
24859b68 | 1290 | case MP_GPIO_ISR_LO: |
343ec8e4 | 1291 | return s->isr & 0xFFFF; |
24859b68 | 1292 | case MP_GPIO_ISR_HI: |
343ec8e4 | 1293 | return s->isr >> 16; |
24859b68 | 1294 | |
24859b68 AZ |
1295 | default: |
1296 | return 0; | |
1297 | } | |
1298 | } | |
1299 | ||
a8170e5e | 1300 | static void musicpal_gpio_write(void *opaque, hwaddr offset, |
19b4a424 | 1301 | uint64_t value, unsigned size) |
24859b68 | 1302 | { |
243cd13c | 1303 | musicpal_gpio_state *s = opaque; |
24859b68 AZ |
1304 | switch (offset) { |
1305 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ | |
343ec8e4 | 1306 | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
24859b68 | 1307 | (value & MP_OE_LCD_BRIGHTNESS); |
343ec8e4 | 1308 | musicpal_gpio_brightness_update(s); |
24859b68 AZ |
1309 | break; |
1310 | ||
1311 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1312 | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
24859b68 AZ |
1313 | break; |
1314 | case MP_GPIO_OUT_HI: | |
343ec8e4 BC |
1315 | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1316 | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | | |
1317 | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); | |
1318 | musicpal_gpio_brightness_update(s); | |
d074769c AZ |
1319 | qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1320 | qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); | |
24859b68 AZ |
1321 | break; |
1322 | ||
708afdf3 JK |
1323 | case MP_GPIO_IER_LO: |
1324 | s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); | |
1325 | break; | |
1326 | case MP_GPIO_IER_HI: | |
1327 | s->ier = (s->ier & 0xFFFF) | (value << 16); | |
1328 | break; | |
1329 | ||
1330 | case MP_GPIO_IMR_LO: | |
1331 | s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); | |
1332 | break; | |
1333 | case MP_GPIO_IMR_HI: | |
1334 | s->imr = (s->imr & 0xFFFF) | (value << 16); | |
1335 | break; | |
24859b68 AZ |
1336 | } |
1337 | } | |
1338 | ||
19b4a424 AK |
1339 | static const MemoryRegionOps musicpal_gpio_ops = { |
1340 | .read = musicpal_gpio_read, | |
1341 | .write = musicpal_gpio_write, | |
1342 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718ec0be | 1343 | }; |
1344 | ||
d5b61ddd | 1345 | static void musicpal_gpio_reset(DeviceState *d) |
718ec0be | 1346 | { |
7012d4b4 | 1347 | musicpal_gpio_state *s = MUSICPAL_GPIO(d); |
30624c92 JK |
1348 | |
1349 | s->lcd_brightness = 0; | |
1350 | s->out_state = 0; | |
343ec8e4 | 1351 | s->in_state = 0xffffffff; |
708afdf3 JK |
1352 | s->ier = 0; |
1353 | s->imr = 0; | |
343ec8e4 BC |
1354 | s->isr = 0; |
1355 | } | |
1356 | ||
ece71994 | 1357 | static void musicpal_gpio_init(Object *obj) |
343ec8e4 | 1358 | { |
ece71994 | 1359 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
7012d4b4 AF |
1360 | DeviceState *dev = DEVICE(sbd); |
1361 | musicpal_gpio_state *s = MUSICPAL_GPIO(dev); | |
718ec0be | 1362 | |
7012d4b4 | 1363 | sysbus_init_irq(sbd, &s->irq); |
343ec8e4 | 1364 | |
ece71994 | 1365 | memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s, |
19b4a424 | 1366 | "musicpal-gpio", MP_GPIO_SIZE); |
7012d4b4 | 1367 | sysbus_init_mmio(sbd, &s->iomem); |
343ec8e4 | 1368 | |
7012d4b4 | 1369 | qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); |
708afdf3 | 1370 | |
7012d4b4 | 1371 | qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); |
718ec0be | 1372 | } |
1373 | ||
d5b61ddd JK |
1374 | static const VMStateDescription musicpal_gpio_vmsd = { |
1375 | .name = "musicpal_gpio", | |
1376 | .version_id = 1, | |
1377 | .minimum_version_id = 1, | |
d5b61ddd JK |
1378 | .fields = (VMStateField[]) { |
1379 | VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), | |
1380 | VMSTATE_UINT32(out_state, musicpal_gpio_state), | |
1381 | VMSTATE_UINT32(in_state, musicpal_gpio_state), | |
1382 | VMSTATE_UINT32(ier, musicpal_gpio_state), | |
1383 | VMSTATE_UINT32(imr, musicpal_gpio_state), | |
1384 | VMSTATE_UINT32(isr, musicpal_gpio_state), | |
1385 | VMSTATE_END_OF_LIST() | |
1386 | } | |
1387 | }; | |
1388 | ||
999e12bb AL |
1389 | static void musicpal_gpio_class_init(ObjectClass *klass, void *data) |
1390 | { | |
39bffca2 | 1391 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1392 | |
39bffca2 AL |
1393 | dc->reset = musicpal_gpio_reset; |
1394 | dc->vmsd = &musicpal_gpio_vmsd; | |
999e12bb AL |
1395 | } |
1396 | ||
8c43a6f0 | 1397 | static const TypeInfo musicpal_gpio_info = { |
7012d4b4 | 1398 | .name = TYPE_MUSICPAL_GPIO, |
39bffca2 AL |
1399 | .parent = TYPE_SYS_BUS_DEVICE, |
1400 | .instance_size = sizeof(musicpal_gpio_state), | |
ece71994 | 1401 | .instance_init = musicpal_gpio_init, |
39bffca2 | 1402 | .class_init = musicpal_gpio_class_init, |
30624c92 JK |
1403 | }; |
1404 | ||
24859b68 | 1405 | /* Keyboard codes & masks */ |
7c6ce4ba | 1406 | #define KEY_RELEASED 0x80 |
24859b68 AZ |
1407 | #define KEY_CODE 0x7f |
1408 | ||
1409 | #define KEYCODE_TAB 0x0f | |
1410 | #define KEYCODE_ENTER 0x1c | |
1411 | #define KEYCODE_F 0x21 | |
1412 | #define KEYCODE_M 0x32 | |
1413 | ||
1414 | #define KEYCODE_EXTENDED 0xe0 | |
1415 | #define KEYCODE_UP 0x48 | |
1416 | #define KEYCODE_DOWN 0x50 | |
1417 | #define KEYCODE_LEFT 0x4b | |
1418 | #define KEYCODE_RIGHT 0x4d | |
1419 | ||
708afdf3 | 1420 | #define MP_KEY_WHEEL_VOL (1 << 0) |
343ec8e4 BC |
1421 | #define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1422 | #define MP_KEY_WHEEL_NAV (1 << 2) | |
1423 | #define MP_KEY_WHEEL_NAV_INV (1 << 3) | |
1424 | #define MP_KEY_BTN_FAVORITS (1 << 4) | |
1425 | #define MP_KEY_BTN_MENU (1 << 5) | |
1426 | #define MP_KEY_BTN_VOLUME (1 << 6) | |
1427 | #define MP_KEY_BTN_NAVIGATION (1 << 7) | |
1428 | ||
3bdf5327 AF |
1429 | #define TYPE_MUSICPAL_KEY "musicpal_key" |
1430 | #define MUSICPAL_KEY(obj) \ | |
1431 | OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY) | |
1432 | ||
343ec8e4 | 1433 | typedef struct musicpal_key_state { |
3bdf5327 AF |
1434 | /*< private >*/ |
1435 | SysBusDevice parent_obj; | |
1436 | /*< public >*/ | |
1437 | ||
4f5c9479 | 1438 | MemoryRegion iomem; |
343ec8e4 | 1439 | uint32_t kbd_extended; |
708afdf3 JK |
1440 | uint32_t pressed_keys; |
1441 | qemu_irq out[8]; | |
343ec8e4 BC |
1442 | } musicpal_key_state; |
1443 | ||
24859b68 AZ |
1444 | static void musicpal_key_event(void *opaque, int keycode) |
1445 | { | |
243cd13c | 1446 | musicpal_key_state *s = opaque; |
24859b68 | 1447 | uint32_t event = 0; |
343ec8e4 | 1448 | int i; |
24859b68 AZ |
1449 | |
1450 | if (keycode == KEYCODE_EXTENDED) { | |
343ec8e4 | 1451 | s->kbd_extended = 1; |
24859b68 AZ |
1452 | return; |
1453 | } | |
1454 | ||
49fedd0d | 1455 | if (s->kbd_extended) { |
24859b68 AZ |
1456 | switch (keycode & KEY_CODE) { |
1457 | case KEYCODE_UP: | |
343ec8e4 | 1458 | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
24859b68 AZ |
1459 | break; |
1460 | ||
1461 | case KEYCODE_DOWN: | |
343ec8e4 | 1462 | event = MP_KEY_WHEEL_NAV; |
24859b68 AZ |
1463 | break; |
1464 | ||
1465 | case KEYCODE_LEFT: | |
343ec8e4 | 1466 | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
24859b68 AZ |
1467 | break; |
1468 | ||
1469 | case KEYCODE_RIGHT: | |
343ec8e4 | 1470 | event = MP_KEY_WHEEL_VOL; |
24859b68 AZ |
1471 | break; |
1472 | } | |
49fedd0d | 1473 | } else { |
24859b68 AZ |
1474 | switch (keycode & KEY_CODE) { |
1475 | case KEYCODE_F: | |
343ec8e4 | 1476 | event = MP_KEY_BTN_FAVORITS; |
24859b68 AZ |
1477 | break; |
1478 | ||
1479 | case KEYCODE_TAB: | |
343ec8e4 | 1480 | event = MP_KEY_BTN_VOLUME; |
24859b68 AZ |
1481 | break; |
1482 | ||
1483 | case KEYCODE_ENTER: | |
343ec8e4 | 1484 | event = MP_KEY_BTN_NAVIGATION; |
24859b68 AZ |
1485 | break; |
1486 | ||
1487 | case KEYCODE_M: | |
343ec8e4 | 1488 | event = MP_KEY_BTN_MENU; |
24859b68 AZ |
1489 | break; |
1490 | } | |
7c6ce4ba | 1491 | /* Do not repeat already pressed buttons */ |
708afdf3 | 1492 | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { |
7c6ce4ba | 1493 | event = 0; |
708afdf3 | 1494 | } |
7c6ce4ba | 1495 | } |
24859b68 | 1496 | |
7c6ce4ba | 1497 | if (event) { |
708afdf3 JK |
1498 | /* Raise GPIO pin first if repeating a key */ |
1499 | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { | |
1500 | for (i = 0; i <= 7; i++) { | |
1501 | if (event & (1 << i)) { | |
1502 | qemu_set_irq(s->out[i], 1); | |
1503 | } | |
1504 | } | |
1505 | } | |
1506 | for (i = 0; i <= 7; i++) { | |
1507 | if (event & (1 << i)) { | |
1508 | qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); | |
1509 | } | |
1510 | } | |
7c6ce4ba | 1511 | if (keycode & KEY_RELEASED) { |
708afdf3 | 1512 | s->pressed_keys &= ~event; |
7c6ce4ba | 1513 | } else { |
708afdf3 | 1514 | s->pressed_keys |= event; |
7c6ce4ba | 1515 | } |
24859b68 AZ |
1516 | } |
1517 | ||
343ec8e4 BC |
1518 | s->kbd_extended = 0; |
1519 | } | |
1520 | ||
ece71994 | 1521 | static void musicpal_key_init(Object *obj) |
343ec8e4 | 1522 | { |
ece71994 | 1523 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
3bdf5327 AF |
1524 | DeviceState *dev = DEVICE(sbd); |
1525 | musicpal_key_state *s = MUSICPAL_KEY(dev); | |
343ec8e4 | 1526 | |
ece71994 | 1527 | memory_region_init(&s->iomem, obj, "dummy", 0); |
3bdf5327 | 1528 | sysbus_init_mmio(sbd, &s->iomem); |
343ec8e4 BC |
1529 | |
1530 | s->kbd_extended = 0; | |
708afdf3 | 1531 | s->pressed_keys = 0; |
343ec8e4 | 1532 | |
3bdf5327 | 1533 | qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); |
343ec8e4 BC |
1534 | |
1535 | qemu_add_kbd_event_handler(musicpal_key_event, s); | |
24859b68 AZ |
1536 | } |
1537 | ||
d5b61ddd JK |
1538 | static const VMStateDescription musicpal_key_vmsd = { |
1539 | .name = "musicpal_key", | |
1540 | .version_id = 1, | |
1541 | .minimum_version_id = 1, | |
d5b61ddd JK |
1542 | .fields = (VMStateField[]) { |
1543 | VMSTATE_UINT32(kbd_extended, musicpal_key_state), | |
1544 | VMSTATE_UINT32(pressed_keys, musicpal_key_state), | |
1545 | VMSTATE_END_OF_LIST() | |
1546 | } | |
1547 | }; | |
1548 | ||
999e12bb AL |
1549 | static void musicpal_key_class_init(ObjectClass *klass, void *data) |
1550 | { | |
39bffca2 | 1551 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1552 | |
39bffca2 | 1553 | dc->vmsd = &musicpal_key_vmsd; |
999e12bb AL |
1554 | } |
1555 | ||
8c43a6f0 | 1556 | static const TypeInfo musicpal_key_info = { |
3bdf5327 | 1557 | .name = TYPE_MUSICPAL_KEY, |
39bffca2 AL |
1558 | .parent = TYPE_SYS_BUS_DEVICE, |
1559 | .instance_size = sizeof(musicpal_key_state), | |
ece71994 | 1560 | .instance_init = musicpal_key_init, |
39bffca2 | 1561 | .class_init = musicpal_key_class_init, |
d5b61ddd JK |
1562 | }; |
1563 | ||
24859b68 AZ |
1564 | static struct arm_boot_info musicpal_binfo = { |
1565 | .loader_start = 0x0, | |
1566 | .board_id = 0x20e, | |
1567 | }; | |
1568 | ||
3ef96221 | 1569 | static void musicpal_init(MachineState *machine) |
24859b68 | 1570 | { |
3ef96221 MA |
1571 | const char *kernel_filename = machine->kernel_filename; |
1572 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1573 | const char *initrd_filename = machine->initrd_filename; | |
f25608e9 | 1574 | ARMCPU *cpu; |
b47b50fa PB |
1575 | qemu_irq pic[32]; |
1576 | DeviceState *dev; | |
d074769c | 1577 | DeviceState *i2c_dev; |
343ec8e4 BC |
1578 | DeviceState *lcd_dev; |
1579 | DeviceState *key_dev; | |
d074769c AZ |
1580 | DeviceState *wm8750_dev; |
1581 | SysBusDevice *s; | |
a5c82852 | 1582 | I2CBus *i2c; |
b47b50fa | 1583 | int i; |
24859b68 | 1584 | unsigned long flash_size; |
751c6a17 | 1585 | DriveInfo *dinfo; |
19b4a424 AK |
1586 | MemoryRegion *address_space_mem = get_system_memory(); |
1587 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
1588 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
24859b68 | 1589 | |
ba1ba5cc | 1590 | cpu = ARM_CPU(cpu_create(machine->cpu_type)); |
24859b68 AZ |
1591 | |
1592 | /* For now we use a fixed - the original - RAM size */ | |
c8623c02 DM |
1593 | memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", |
1594 | MP_RAM_DEFAULT_SIZE); | |
19b4a424 | 1595 | memory_region_add_subregion(address_space_mem, 0, ram); |
24859b68 | 1596 | |
98a99ce0 | 1597 | memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, |
f8ed85ac | 1598 | &error_fatal); |
19b4a424 | 1599 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); |
24859b68 | 1600 | |
c7bd0fd9 | 1601 | dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, |
fcef61ec | 1602 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
b47b50fa | 1603 | for (i = 0; i < 32; i++) { |
067a3ddc | 1604 | pic[i] = qdev_get_gpio_in(dev, i); |
b47b50fa | 1605 | } |
4adc8541 | 1606 | sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], |
b47b50fa PB |
1607 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1608 | pic[MP_TIMER4_IRQ], NULL); | |
24859b68 | 1609 | |
9bca0edb | 1610 | if (serial_hd(0)) { |
39186d8a | 1611 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], |
9bca0edb | 1612 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); |
49fedd0d | 1613 | } |
9bca0edb | 1614 | if (serial_hd(1)) { |
39186d8a | 1615 | serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], |
9bca0edb | 1616 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); |
49fedd0d | 1617 | } |
24859b68 AZ |
1618 | |
1619 | /* Register flash */ | |
751c6a17 GH |
1620 | dinfo = drive_get(IF_PFLASH, 0, 0); |
1621 | if (dinfo) { | |
4be74634 | 1622 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); |
fa1d36df | 1623 | |
4be74634 | 1624 | flash_size = blk_getlength(blk); |
24859b68 AZ |
1625 | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1626 | flash_size != 32*1024*1024) { | |
c0dbca36 | 1627 | error_report("Invalid flash image size"); |
24859b68 AZ |
1628 | exit(1); |
1629 | } | |
1630 | ||
1631 | /* | |
1632 | * The original U-Boot accesses the flash at 0xFE000000 instead of | |
1633 | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the | |
1634 | * image is smaller than 32 MB. | |
1635 | */ | |
5f9fc5ad | 1636 | #ifdef TARGET_WORDS_BIGENDIAN |
940d5b13 | 1637 | pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, |
cfe5f011 | 1638 | "musicpal.flash", flash_size, |
ce14710f | 1639 | blk, 0x10000, |
24859b68 AZ |
1640 | MP_FLASH_SIZE_MAX / flash_size, |
1641 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | |
01e0451a | 1642 | 0x5555, 0x2AAA, 1); |
5f9fc5ad | 1643 | #else |
940d5b13 | 1644 | pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, |
cfe5f011 | 1645 | "musicpal.flash", flash_size, |
ce14710f | 1646 | blk, 0x10000, |
5f9fc5ad BS |
1647 | MP_FLASH_SIZE_MAX / flash_size, |
1648 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | |
01e0451a | 1649 | 0x5555, 0x2AAA, 0); |
5f9fc5ad BS |
1650 | #endif |
1651 | ||
24859b68 | 1652 | } |
5952b01c | 1653 | sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); |
24859b68 | 1654 | |
b47b50fa | 1655 | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
a77d90e6 | 1656 | dev = qdev_create(NULL, TYPE_MV88W8618_ETH); |
4c91cd28 | 1657 | qdev_set_nic_properties(dev, &nd_table[0]); |
e23a1b33 | 1658 | qdev_init_nofail(dev); |
1356b98d AF |
1659 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); |
1660 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | |
24859b68 | 1661 | |
b47b50fa | 1662 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
718ec0be | 1663 | |
a86f200a | 1664 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); |
343ec8e4 | 1665 | |
7012d4b4 AF |
1666 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, |
1667 | pic[MP_GPIO_IRQ]); | |
d04fba94 | 1668 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); |
a5c82852 | 1669 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); |
d074769c | 1670 | |
2cca58fd | 1671 | lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); |
3bdf5327 | 1672 | key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); |
343ec8e4 | 1673 | |
d074769c | 1674 | /* I2C read data */ |
708afdf3 JK |
1675 | qdev_connect_gpio_out(i2c_dev, 0, |
1676 | qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); | |
d074769c AZ |
1677 | /* I2C data */ |
1678 | qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); | |
1679 | /* I2C clock */ | |
1680 | qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); | |
1681 | ||
49fedd0d | 1682 | for (i = 0; i < 3; i++) { |
343ec8e4 | 1683 | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
49fedd0d | 1684 | } |
708afdf3 JK |
1685 | for (i = 0; i < 4; i++) { |
1686 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); | |
1687 | } | |
1688 | for (i = 4; i < 8; i++) { | |
1689 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); | |
1690 | } | |
24859b68 | 1691 | |
7ab14c5a | 1692 | wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR); |
d436d4e7 | 1693 | dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO); |
1356b98d | 1694 | s = SYS_BUS_DEVICE(dev); |
a8299ec1 | 1695 | object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), |
bd02b014 | 1696 | "wm8750", NULL); |
e23a1b33 | 1697 | qdev_init_nofail(dev); |
d074769c AZ |
1698 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); |
1699 | sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | |
d074769c | 1700 | |
24859b68 AZ |
1701 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1702 | musicpal_binfo.kernel_filename = kernel_filename; | |
1703 | musicpal_binfo.kernel_cmdline = kernel_cmdline; | |
1704 | musicpal_binfo.initrd_filename = initrd_filename; | |
3aaa8dfa | 1705 | arm_load_kernel(cpu, &musicpal_binfo); |
24859b68 AZ |
1706 | } |
1707 | ||
e264d29d | 1708 | static void musicpal_machine_init(MachineClass *mc) |
f80f9ec9 | 1709 | { |
e264d29d EH |
1710 | mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; |
1711 | mc->init = musicpal_init; | |
4672cbd7 | 1712 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 1713 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
f80f9ec9 AL |
1714 | } |
1715 | ||
e264d29d | 1716 | DEFINE_MACHINE("musicpal", musicpal_machine_init) |
f80f9ec9 | 1717 | |
999e12bb AL |
1718 | static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) |
1719 | { | |
7f7420a0 | 1720 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1721 | |
7f7420a0 | 1722 | dc->realize = mv88w8618_wlan_realize; |
999e12bb AL |
1723 | } |
1724 | ||
8c43a6f0 | 1725 | static const TypeInfo mv88w8618_wlan_info = { |
39bffca2 AL |
1726 | .name = "mv88w8618_wlan", |
1727 | .parent = TYPE_SYS_BUS_DEVICE, | |
1728 | .instance_size = sizeof(SysBusDevice), | |
1729 | .class_init = mv88w8618_wlan_class_init, | |
999e12bb AL |
1730 | }; |
1731 | ||
83f7d43a | 1732 | static void musicpal_register_types(void) |
b47b50fa | 1733 | { |
39bffca2 AL |
1734 | type_register_static(&mv88w8618_pic_info); |
1735 | type_register_static(&mv88w8618_pit_info); | |
1736 | type_register_static(&mv88w8618_flashcfg_info); | |
1737 | type_register_static(&mv88w8618_eth_info); | |
1738 | type_register_static(&mv88w8618_wlan_info); | |
1739 | type_register_static(&musicpal_lcd_info); | |
1740 | type_register_static(&musicpal_gpio_info); | |
1741 | type_register_static(&musicpal_key_info); | |
a86f200a | 1742 | type_register_static(&musicpal_misc_info); |
b47b50fa PB |
1743 | } |
1744 | ||
83f7d43a | 1745 | type_init(musicpal_register_types) |