]>
Commit | Line | Data |
---|---|---|
c3d2689d AZ |
1 | /* |
2 | * TI OMAP processors emulation. | |
3 | * | |
b4e3104b | 4 | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
c3d2689d AZ |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
827df9f3 AZ |
8 | * published by the Free Software Foundation; either version 2 or |
9 | * (at your option) version 3 of the License. | |
c3d2689d AZ |
10 | * |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
fad6cb1a | 16 | * You should have received a copy of the GNU General Public License along |
8167ee88 | 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
c3d2689d | 18 | */ |
c8623c02 | 19 | |
12b16722 | 20 | #include "qemu/osdep.h" |
da34e65c | 21 | #include "qapi/error.h" |
c8623c02 | 22 | #include "hw/boards.h" |
83c9f4ca | 23 | #include "hw/hw.h" |
bd2be150 | 24 | #include "hw/arm/arm.h" |
0d09e41a | 25 | #include "hw/arm/omap.h" |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
0d09e41a | 27 | #include "hw/arm/soc_dma.h" |
fa1d36df | 28 | #include "sysemu/block-backend.h" |
9c17d615 | 29 | #include "sysemu/blockdev.h" |
1de7afc9 | 30 | #include "qemu/range.h" |
83c9f4ca | 31 | #include "hw/sysbus.h" |
c3d2689d | 32 | |
827df9f3 | 33 | /* Should signal the TCMI/GPMC */ |
a8170e5e | 34 | uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) |
66450b15 | 35 | { |
02645926 AZ |
36 | uint8_t ret; |
37 | ||
66450b15 | 38 | OMAP_8B_REG(addr); |
e1fe50dc | 39 | cpu_physical_memory_read(addr, &ret, 1); |
02645926 | 40 | return ret; |
66450b15 AZ |
41 | } |
42 | ||
a8170e5e | 43 | void omap_badwidth_write8(void *opaque, hwaddr addr, |
66450b15 AZ |
44 | uint32_t value) |
45 | { | |
b854bc19 AZ |
46 | uint8_t val8 = value; |
47 | ||
66450b15 | 48 | OMAP_8B_REG(addr); |
e1fe50dc | 49 | cpu_physical_memory_write(addr, &val8, 1); |
66450b15 AZ |
50 | } |
51 | ||
a8170e5e | 52 | uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) |
c3d2689d | 53 | { |
b854bc19 AZ |
54 | uint16_t ret; |
55 | ||
c3d2689d | 56 | OMAP_16B_REG(addr); |
e1fe50dc | 57 | cpu_physical_memory_read(addr, &ret, 2); |
b854bc19 | 58 | return ret; |
c3d2689d AZ |
59 | } |
60 | ||
a8170e5e | 61 | void omap_badwidth_write16(void *opaque, hwaddr addr, |
c3d2689d AZ |
62 | uint32_t value) |
63 | { | |
b854bc19 AZ |
64 | uint16_t val16 = value; |
65 | ||
c3d2689d | 66 | OMAP_16B_REG(addr); |
e1fe50dc | 67 | cpu_physical_memory_write(addr, &val16, 2); |
c3d2689d AZ |
68 | } |
69 | ||
a8170e5e | 70 | uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) |
c3d2689d | 71 | { |
b854bc19 AZ |
72 | uint32_t ret; |
73 | ||
c3d2689d | 74 | OMAP_32B_REG(addr); |
e1fe50dc | 75 | cpu_physical_memory_read(addr, &ret, 4); |
b854bc19 | 76 | return ret; |
c3d2689d AZ |
77 | } |
78 | ||
a8170e5e | 79 | void omap_badwidth_write32(void *opaque, hwaddr addr, |
c3d2689d AZ |
80 | uint32_t value) |
81 | { | |
82 | OMAP_32B_REG(addr); | |
e1fe50dc | 83 | cpu_physical_memory_write(addr, &value, 4); |
c3d2689d AZ |
84 | } |
85 | ||
c3d2689d AZ |
86 | /* MPU OS timers */ |
87 | struct omap_mpu_timer_s { | |
4b3fedf3 | 88 | MemoryRegion iomem; |
c3d2689d AZ |
89 | qemu_irq irq; |
90 | omap_clk clk; | |
c3d2689d AZ |
91 | uint32_t val; |
92 | int64_t time; | |
93 | QEMUTimer *timer; | |
e856f2ad | 94 | QEMUBH *tick; |
c3d2689d AZ |
95 | int64_t rate; |
96 | int it_ena; | |
97 | ||
98 | int enable; | |
99 | int ptv; | |
100 | int ar; | |
101 | int st; | |
102 | uint32_t reset_val; | |
103 | }; | |
104 | ||
105 | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) | |
106 | { | |
bc72ad67 | 107 | uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; |
c3d2689d AZ |
108 | |
109 | if (timer->st && timer->enable && timer->rate) | |
110 | return timer->val - muldiv64(distance >> (timer->ptv + 1), | |
6ee093c9 | 111 | timer->rate, get_ticks_per_sec()); |
c3d2689d AZ |
112 | else |
113 | return timer->val; | |
114 | } | |
115 | ||
116 | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) | |
117 | { | |
118 | timer->val = omap_timer_read(timer); | |
bc72ad67 | 119 | timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
c3d2689d AZ |
120 | } |
121 | ||
122 | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) | |
123 | { | |
124 | int64_t expires; | |
125 | ||
126 | if (timer->enable && timer->st && timer->rate) { | |
127 | timer->val = timer->reset_val; /* Should skip this on clk enable */ | |
b8b137d6 | 128 | expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), |
6ee093c9 | 129 | get_ticks_per_sec(), timer->rate); |
b854bc19 AZ |
130 | |
131 | /* If timer expiry would be sooner than in about 1 ms and | |
132 | * auto-reload isn't set, then fire immediately. This is a hack | |
133 | * to make systems like PalmOS run in acceptable time. PalmOS | |
134 | * sets the interval to a very low value and polls the status bit | |
135 | * in a busy loop when it wants to sleep just a couple of CPU | |
136 | * ticks. */ | |
6ee093c9 | 137 | if (expires > (get_ticks_per_sec() >> 10) || timer->ar) |
bc72ad67 | 138 | timer_mod(timer->timer, timer->time + expires); |
e856f2ad AZ |
139 | else |
140 | qemu_bh_schedule(timer->tick); | |
c3d2689d | 141 | } else |
bc72ad67 | 142 | timer_del(timer->timer); |
c3d2689d AZ |
143 | } |
144 | ||
e856f2ad | 145 | static void omap_timer_fire(void *opaque) |
c3d2689d | 146 | { |
e856f2ad | 147 | struct omap_mpu_timer_s *timer = opaque; |
c3d2689d AZ |
148 | |
149 | if (!timer->ar) { | |
150 | timer->val = 0; | |
151 | timer->st = 0; | |
152 | } | |
153 | ||
154 | if (timer->it_ena) | |
106627d0 AZ |
155 | /* Edge-triggered irq */ |
156 | qemu_irq_pulse(timer->irq); | |
e856f2ad AZ |
157 | } |
158 | ||
159 | static void omap_timer_tick(void *opaque) | |
160 | { | |
161 | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; | |
162 | ||
163 | omap_timer_sync(timer); | |
164 | omap_timer_fire(timer); | |
c3d2689d AZ |
165 | omap_timer_update(timer); |
166 | } | |
167 | ||
168 | static void omap_timer_clk_update(void *opaque, int line, int on) | |
169 | { | |
170 | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; | |
171 | ||
172 | omap_timer_sync(timer); | |
173 | timer->rate = on ? omap_clk_getrate(timer->clk) : 0; | |
174 | omap_timer_update(timer); | |
175 | } | |
176 | ||
177 | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) | |
178 | { | |
179 | omap_clk_adduser(timer->clk, | |
f3c7d038 | 180 | qemu_allocate_irq(omap_timer_clk_update, timer, 0)); |
c3d2689d AZ |
181 | timer->rate = omap_clk_getrate(timer->clk); |
182 | } | |
183 | ||
a8170e5e | 184 | static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, |
4b3fedf3 | 185 | unsigned size) |
c3d2689d AZ |
186 | { |
187 | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; | |
c3d2689d | 188 | |
4b3fedf3 AK |
189 | if (size != 4) { |
190 | return omap_badwidth_read32(opaque, addr); | |
191 | } | |
192 | ||
8da3ff18 | 193 | switch (addr) { |
c3d2689d AZ |
194 | case 0x00: /* CNTL_TIMER */ |
195 | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; | |
196 | ||
197 | case 0x04: /* LOAD_TIM */ | |
198 | break; | |
199 | ||
200 | case 0x08: /* READ_TIM */ | |
201 | return omap_timer_read(s); | |
202 | } | |
203 | ||
204 | OMAP_BAD_REG(addr); | |
205 | return 0; | |
206 | } | |
207 | ||
a8170e5e | 208 | static void omap_mpu_timer_write(void *opaque, hwaddr addr, |
4b3fedf3 | 209 | uint64_t value, unsigned size) |
c3d2689d AZ |
210 | { |
211 | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; | |
c3d2689d | 212 | |
4b3fedf3 | 213 | if (size != 4) { |
77a8257e SW |
214 | omap_badwidth_write32(opaque, addr, value); |
215 | return; | |
4b3fedf3 AK |
216 | } |
217 | ||
8da3ff18 | 218 | switch (addr) { |
c3d2689d AZ |
219 | case 0x00: /* CNTL_TIMER */ |
220 | omap_timer_sync(s); | |
221 | s->enable = (value >> 5) & 1; | |
222 | s->ptv = (value >> 2) & 7; | |
223 | s->ar = (value >> 1) & 1; | |
224 | s->st = value & 1; | |
225 | omap_timer_update(s); | |
226 | return; | |
227 | ||
228 | case 0x04: /* LOAD_TIM */ | |
229 | s->reset_val = value; | |
230 | return; | |
231 | ||
232 | case 0x08: /* READ_TIM */ | |
233 | OMAP_RO_REG(addr); | |
234 | break; | |
235 | ||
236 | default: | |
237 | OMAP_BAD_REG(addr); | |
238 | } | |
239 | } | |
240 | ||
4b3fedf3 AK |
241 | static const MemoryRegionOps omap_mpu_timer_ops = { |
242 | .read = omap_mpu_timer_read, | |
243 | .write = omap_mpu_timer_write, | |
244 | .endianness = DEVICE_LITTLE_ENDIAN, | |
c3d2689d AZ |
245 | }; |
246 | ||
247 | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) | |
248 | { | |
bc72ad67 | 249 | timer_del(s->timer); |
c3d2689d AZ |
250 | s->enable = 0; |
251 | s->reset_val = 31337; | |
252 | s->val = 0; | |
253 | s->ptv = 0; | |
254 | s->ar = 0; | |
255 | s->st = 0; | |
256 | s->it_ena = 1; | |
257 | } | |
258 | ||
4b3fedf3 | 259 | static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, |
a8170e5e | 260 | hwaddr base, |
c3d2689d AZ |
261 | qemu_irq irq, omap_clk clk) |
262 | { | |
b45c03f5 | 263 | struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); |
c3d2689d AZ |
264 | |
265 | s->irq = irq; | |
266 | s->clk = clk; | |
bc72ad67 | 267 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); |
e856f2ad | 268 | s->tick = qemu_bh_new(omap_timer_fire, s); |
c3d2689d AZ |
269 | omap_mpu_timer_reset(s); |
270 | omap_timer_clk_setup(s); | |
271 | ||
2c9b15ca | 272 | memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, |
4b3fedf3 AK |
273 | "omap-mpu-timer", 0x100); |
274 | ||
275 | memory_region_add_subregion(system_memory, base, &s->iomem); | |
c3d2689d AZ |
276 | |
277 | return s; | |
278 | } | |
279 | ||
280 | /* Watchdog timer */ | |
281 | struct omap_watchdog_timer_s { | |
282 | struct omap_mpu_timer_s timer; | |
4b3fedf3 | 283 | MemoryRegion iomem; |
c3d2689d AZ |
284 | uint8_t last_wr; |
285 | int mode; | |
286 | int free; | |
287 | int reset; | |
288 | }; | |
289 | ||
a8170e5e | 290 | static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, |
4b3fedf3 | 291 | unsigned size) |
c3d2689d AZ |
292 | { |
293 | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; | |
c3d2689d | 294 | |
4b3fedf3 AK |
295 | if (size != 2) { |
296 | return omap_badwidth_read16(opaque, addr); | |
297 | } | |
298 | ||
8da3ff18 | 299 | switch (addr) { |
c3d2689d AZ |
300 | case 0x00: /* CNTL_TIMER */ |
301 | return (s->timer.ptv << 9) | (s->timer.ar << 8) | | |
302 | (s->timer.st << 7) | (s->free << 1); | |
303 | ||
304 | case 0x04: /* READ_TIMER */ | |
305 | return omap_timer_read(&s->timer); | |
306 | ||
307 | case 0x08: /* TIMER_MODE */ | |
308 | return s->mode << 15; | |
309 | } | |
310 | ||
311 | OMAP_BAD_REG(addr); | |
312 | return 0; | |
313 | } | |
314 | ||
a8170e5e | 315 | static void omap_wd_timer_write(void *opaque, hwaddr addr, |
4b3fedf3 | 316 | uint64_t value, unsigned size) |
c3d2689d AZ |
317 | { |
318 | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; | |
c3d2689d | 319 | |
4b3fedf3 | 320 | if (size != 2) { |
77a8257e SW |
321 | omap_badwidth_write16(opaque, addr, value); |
322 | return; | |
4b3fedf3 AK |
323 | } |
324 | ||
8da3ff18 | 325 | switch (addr) { |
c3d2689d AZ |
326 | case 0x00: /* CNTL_TIMER */ |
327 | omap_timer_sync(&s->timer); | |
328 | s->timer.ptv = (value >> 9) & 7; | |
329 | s->timer.ar = (value >> 8) & 1; | |
330 | s->timer.st = (value >> 7) & 1; | |
331 | s->free = (value >> 1) & 1; | |
332 | omap_timer_update(&s->timer); | |
333 | break; | |
334 | ||
335 | case 0x04: /* LOAD_TIMER */ | |
336 | s->timer.reset_val = value & 0xffff; | |
337 | break; | |
338 | ||
339 | case 0x08: /* TIMER_MODE */ | |
340 | if (!s->mode && ((value >> 15) & 1)) | |
341 | omap_clk_get(s->timer.clk); | |
342 | s->mode |= (value >> 15) & 1; | |
343 | if (s->last_wr == 0xf5) { | |
344 | if ((value & 0xff) == 0xa0) { | |
d8f699cb AZ |
345 | if (s->mode) { |
346 | s->mode = 0; | |
347 | omap_clk_put(s->timer.clk); | |
348 | } | |
c3d2689d AZ |
349 | } else { |
350 | /* XXX: on T|E hardware somehow this has no effect, | |
351 | * on Zire 71 it works as specified. */ | |
352 | s->reset = 1; | |
353 | qemu_system_reset_request(); | |
354 | } | |
355 | } | |
356 | s->last_wr = value & 0xff; | |
357 | break; | |
358 | ||
359 | default: | |
360 | OMAP_BAD_REG(addr); | |
361 | } | |
362 | } | |
363 | ||
4b3fedf3 AK |
364 | static const MemoryRegionOps omap_wd_timer_ops = { |
365 | .read = omap_wd_timer_read, | |
366 | .write = omap_wd_timer_write, | |
367 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
368 | }; |
369 | ||
370 | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) | |
371 | { | |
bc72ad67 | 372 | timer_del(s->timer.timer); |
c3d2689d AZ |
373 | if (!s->mode) |
374 | omap_clk_get(s->timer.clk); | |
375 | s->mode = 1; | |
376 | s->free = 1; | |
377 | s->reset = 0; | |
378 | s->timer.enable = 1; | |
379 | s->timer.it_ena = 1; | |
380 | s->timer.reset_val = 0xffff; | |
381 | s->timer.val = 0; | |
382 | s->timer.st = 0; | |
383 | s->timer.ptv = 0; | |
384 | s->timer.ar = 0; | |
385 | omap_timer_update(&s->timer); | |
386 | } | |
387 | ||
4b3fedf3 | 388 | static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, |
a8170e5e | 389 | hwaddr base, |
c3d2689d AZ |
390 | qemu_irq irq, omap_clk clk) |
391 | { | |
b45c03f5 | 392 | struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); |
c3d2689d AZ |
393 | |
394 | s->timer.irq = irq; | |
395 | s->timer.clk = clk; | |
bc72ad67 | 396 | s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); |
c3d2689d AZ |
397 | omap_wd_timer_reset(s); |
398 | omap_timer_clk_setup(&s->timer); | |
399 | ||
2c9b15ca | 400 | memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, |
4b3fedf3 AK |
401 | "omap-wd-timer", 0x100); |
402 | memory_region_add_subregion(memory, base, &s->iomem); | |
c3d2689d AZ |
403 | |
404 | return s; | |
405 | } | |
406 | ||
407 | /* 32-kHz timer */ | |
408 | struct omap_32khz_timer_s { | |
409 | struct omap_mpu_timer_s timer; | |
4b3fedf3 | 410 | MemoryRegion iomem; |
c3d2689d AZ |
411 | }; |
412 | ||
a8170e5e | 413 | static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, |
4b3fedf3 | 414 | unsigned size) |
c3d2689d AZ |
415 | { |
416 | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; | |
cf965d24 | 417 | int offset = addr & OMAP_MPUI_REG_MASK; |
c3d2689d | 418 | |
4b3fedf3 AK |
419 | if (size != 4) { |
420 | return omap_badwidth_read32(opaque, addr); | |
421 | } | |
422 | ||
c3d2689d AZ |
423 | switch (offset) { |
424 | case 0x00: /* TVR */ | |
425 | return s->timer.reset_val; | |
426 | ||
427 | case 0x04: /* TCR */ | |
428 | return omap_timer_read(&s->timer); | |
429 | ||
430 | case 0x08: /* CR */ | |
431 | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; | |
432 | ||
433 | default: | |
434 | break; | |
435 | } | |
436 | OMAP_BAD_REG(addr); | |
437 | return 0; | |
438 | } | |
439 | ||
a8170e5e | 440 | static void omap_os_timer_write(void *opaque, hwaddr addr, |
4b3fedf3 | 441 | uint64_t value, unsigned size) |
c3d2689d AZ |
442 | { |
443 | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; | |
cf965d24 | 444 | int offset = addr & OMAP_MPUI_REG_MASK; |
c3d2689d | 445 | |
4b3fedf3 | 446 | if (size != 4) { |
77a8257e SW |
447 | omap_badwidth_write32(opaque, addr, value); |
448 | return; | |
4b3fedf3 AK |
449 | } |
450 | ||
c3d2689d AZ |
451 | switch (offset) { |
452 | case 0x00: /* TVR */ | |
453 | s->timer.reset_val = value & 0x00ffffff; | |
454 | break; | |
455 | ||
456 | case 0x04: /* TCR */ | |
457 | OMAP_RO_REG(addr); | |
458 | break; | |
459 | ||
460 | case 0x08: /* CR */ | |
461 | s->timer.ar = (value >> 3) & 1; | |
462 | s->timer.it_ena = (value >> 2) & 1; | |
463 | if (s->timer.st != (value & 1) || (value & 2)) { | |
464 | omap_timer_sync(&s->timer); | |
465 | s->timer.enable = value & 1; | |
466 | s->timer.st = value & 1; | |
467 | omap_timer_update(&s->timer); | |
468 | } | |
469 | break; | |
470 | ||
471 | default: | |
472 | OMAP_BAD_REG(addr); | |
473 | } | |
474 | } | |
475 | ||
4b3fedf3 AK |
476 | static const MemoryRegionOps omap_os_timer_ops = { |
477 | .read = omap_os_timer_read, | |
478 | .write = omap_os_timer_write, | |
479 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
480 | }; |
481 | ||
482 | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) | |
483 | { | |
bc72ad67 | 484 | timer_del(s->timer.timer); |
c3d2689d AZ |
485 | s->timer.enable = 0; |
486 | s->timer.it_ena = 0; | |
487 | s->timer.reset_val = 0x00ffffff; | |
488 | s->timer.val = 0; | |
489 | s->timer.st = 0; | |
490 | s->timer.ptv = 0; | |
491 | s->timer.ar = 1; | |
492 | } | |
493 | ||
4b3fedf3 | 494 | static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, |
a8170e5e | 495 | hwaddr base, |
c3d2689d AZ |
496 | qemu_irq irq, omap_clk clk) |
497 | { | |
b45c03f5 | 498 | struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); |
c3d2689d AZ |
499 | |
500 | s->timer.irq = irq; | |
501 | s->timer.clk = clk; | |
bc72ad67 | 502 | s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); |
c3d2689d AZ |
503 | omap_os_timer_reset(s); |
504 | omap_timer_clk_setup(&s->timer); | |
505 | ||
2c9b15ca | 506 | memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, |
4b3fedf3 AK |
507 | "omap-os-timer", 0x800); |
508 | memory_region_add_subregion(memory, base, &s->iomem); | |
c3d2689d AZ |
509 | |
510 | return s; | |
511 | } | |
512 | ||
513 | /* Ultra Low-Power Device Module */ | |
a8170e5e | 514 | static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, |
4b3fedf3 | 515 | unsigned size) |
c3d2689d AZ |
516 | { |
517 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
518 | uint16_t ret; |
519 | ||
4b3fedf3 AK |
520 | if (size != 2) { |
521 | return omap_badwidth_read16(opaque, addr); | |
522 | } | |
523 | ||
8da3ff18 | 524 | switch (addr) { |
c3d2689d | 525 | case 0x14: /* IT_STATUS */ |
8da3ff18 PB |
526 | ret = s->ulpd_pm_regs[addr >> 2]; |
527 | s->ulpd_pm_regs[addr >> 2] = 0; | |
0919ac78 | 528 | qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); |
c3d2689d AZ |
529 | return ret; |
530 | ||
531 | case 0x18: /* Reserved */ | |
532 | case 0x1c: /* Reserved */ | |
533 | case 0x20: /* Reserved */ | |
534 | case 0x28: /* Reserved */ | |
535 | case 0x2c: /* Reserved */ | |
536 | OMAP_BAD_REG(addr); | |
139bd956 | 537 | /* fall through */ |
c3d2689d AZ |
538 | case 0x00: /* COUNTER_32_LSB */ |
539 | case 0x04: /* COUNTER_32_MSB */ | |
540 | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ | |
541 | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ | |
542 | case 0x10: /* GAUGING_CTRL */ | |
543 | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ | |
544 | case 0x30: /* CLOCK_CTRL */ | |
545 | case 0x34: /* SOFT_REQ */ | |
546 | case 0x38: /* COUNTER_32_FIQ */ | |
547 | case 0x3c: /* DPLL_CTRL */ | |
548 | case 0x40: /* STATUS_REQ */ | |
549 | /* XXX: check clk::usecount state for every clock */ | |
550 | case 0x48: /* LOCL_TIME */ | |
551 | case 0x4c: /* APLL_CTRL */ | |
552 | case 0x50: /* POWER_CTRL */ | |
8da3ff18 | 553 | return s->ulpd_pm_regs[addr >> 2]; |
c3d2689d AZ |
554 | } |
555 | ||
556 | OMAP_BAD_REG(addr); | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, | |
561 | uint16_t diff, uint16_t value) | |
562 | { | |
563 | if (diff & (1 << 4)) /* USB_MCLK_EN */ | |
564 | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); | |
565 | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ | |
566 | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); | |
567 | } | |
568 | ||
569 | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, | |
570 | uint16_t diff, uint16_t value) | |
571 | { | |
572 | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ | |
573 | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); | |
574 | if (diff & (1 << 1)) /* SOFT_COM_REQ */ | |
575 | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); | |
576 | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ | |
577 | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); | |
578 | if (diff & (1 << 3)) /* SOFT_USB_REQ */ | |
579 | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); | |
580 | } | |
581 | ||
a8170e5e | 582 | static void omap_ulpd_pm_write(void *opaque, hwaddr addr, |
4b3fedf3 | 583 | uint64_t value, unsigned size) |
c3d2689d AZ |
584 | { |
585 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
586 | int64_t now, ticks; |
587 | int div, mult; | |
588 | static const int bypass_div[4] = { 1, 2, 4, 4 }; | |
589 | uint16_t diff; | |
590 | ||
4b3fedf3 | 591 | if (size != 2) { |
77a8257e SW |
592 | omap_badwidth_write16(opaque, addr, value); |
593 | return; | |
4b3fedf3 AK |
594 | } |
595 | ||
8da3ff18 | 596 | switch (addr) { |
c3d2689d AZ |
597 | case 0x00: /* COUNTER_32_LSB */ |
598 | case 0x04: /* COUNTER_32_MSB */ | |
599 | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ | |
600 | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ | |
601 | case 0x14: /* IT_STATUS */ | |
602 | case 0x40: /* STATUS_REQ */ | |
603 | OMAP_RO_REG(addr); | |
604 | break; | |
605 | ||
606 | case 0x10: /* GAUGING_CTRL */ | |
607 | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ | |
8da3ff18 | 608 | if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { |
bc72ad67 | 609 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
c3d2689d AZ |
610 | |
611 | if (value & 1) | |
612 | s->ulpd_gauge_start = now; | |
613 | else { | |
614 | now -= s->ulpd_gauge_start; | |
615 | ||
616 | /* 32-kHz ticks */ | |
6ee093c9 | 617 | ticks = muldiv64(now, 32768, get_ticks_per_sec()); |
c3d2689d AZ |
618 | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
619 | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; | |
620 | if (ticks >> 32) /* OVERFLOW_32K */ | |
621 | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; | |
622 | ||
623 | /* High frequency ticks */ | |
6ee093c9 | 624 | ticks = muldiv64(now, 12000000, get_ticks_per_sec()); |
c3d2689d AZ |
625 | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
626 | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; | |
627 | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ | |
628 | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; | |
629 | ||
630 | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ | |
0919ac78 | 631 | qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); |
c3d2689d AZ |
632 | } |
633 | } | |
8da3ff18 | 634 | s->ulpd_pm_regs[addr >> 2] = value; |
c3d2689d AZ |
635 | break; |
636 | ||
637 | case 0x18: /* Reserved */ | |
638 | case 0x1c: /* Reserved */ | |
639 | case 0x20: /* Reserved */ | |
640 | case 0x28: /* Reserved */ | |
641 | case 0x2c: /* Reserved */ | |
642 | OMAP_BAD_REG(addr); | |
139bd956 | 643 | /* fall through */ |
c3d2689d AZ |
644 | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
645 | case 0x38: /* COUNTER_32_FIQ */ | |
646 | case 0x48: /* LOCL_TIME */ | |
647 | case 0x50: /* POWER_CTRL */ | |
8da3ff18 | 648 | s->ulpd_pm_regs[addr >> 2] = value; |
c3d2689d AZ |
649 | break; |
650 | ||
651 | case 0x30: /* CLOCK_CTRL */ | |
8da3ff18 PB |
652 | diff = s->ulpd_pm_regs[addr >> 2] ^ value; |
653 | s->ulpd_pm_regs[addr >> 2] = value & 0x3f; | |
c3d2689d AZ |
654 | omap_ulpd_clk_update(s, diff, value); |
655 | break; | |
656 | ||
657 | case 0x34: /* SOFT_REQ */ | |
8da3ff18 PB |
658 | diff = s->ulpd_pm_regs[addr >> 2] ^ value; |
659 | s->ulpd_pm_regs[addr >> 2] = value & 0x1f; | |
c3d2689d AZ |
660 | omap_ulpd_req_update(s, diff, value); |
661 | break; | |
662 | ||
663 | case 0x3c: /* DPLL_CTRL */ | |
664 | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is | |
665 | * omitted altogether, probably a typo. */ | |
666 | /* This register has identical semantics with DPLL(1:3) control | |
667 | * registers, see omap_dpll_write() */ | |
8da3ff18 PB |
668 | diff = s->ulpd_pm_regs[addr >> 2] & value; |
669 | s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; | |
c3d2689d AZ |
670 | if (diff & (0x3ff << 2)) { |
671 | if (value & (1 << 4)) { /* PLL_ENABLE */ | |
672 | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ | |
673 | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ | |
674 | } else { | |
675 | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ | |
676 | mult = 1; | |
677 | } | |
678 | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); | |
679 | } | |
680 | ||
681 | /* Enter the desired mode. */ | |
8da3ff18 PB |
682 | s->ulpd_pm_regs[addr >> 2] = |
683 | (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | | |
684 | ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); | |
c3d2689d AZ |
685 | |
686 | /* Act as if the lock is restored. */ | |
8da3ff18 | 687 | s->ulpd_pm_regs[addr >> 2] |= 2; |
c3d2689d AZ |
688 | break; |
689 | ||
690 | case 0x4c: /* APLL_CTRL */ | |
8da3ff18 PB |
691 | diff = s->ulpd_pm_regs[addr >> 2] & value; |
692 | s->ulpd_pm_regs[addr >> 2] = value & 0xf; | |
c3d2689d AZ |
693 | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
694 | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, | |
695 | (value & (1 << 0)) ? "apll" : "dpll4")); | |
696 | break; | |
697 | ||
698 | default: | |
699 | OMAP_BAD_REG(addr); | |
700 | } | |
701 | } | |
702 | ||
4b3fedf3 AK |
703 | static const MemoryRegionOps omap_ulpd_pm_ops = { |
704 | .read = omap_ulpd_pm_read, | |
705 | .write = omap_ulpd_pm_write, | |
706 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
707 | }; |
708 | ||
709 | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) | |
710 | { | |
711 | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; | |
712 | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; | |
713 | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; | |
714 | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; | |
715 | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; | |
716 | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; | |
717 | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; | |
718 | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; | |
719 | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; | |
720 | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; | |
721 | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; | |
722 | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); | |
723 | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; | |
724 | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); | |
725 | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; | |
726 | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; | |
727 | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; | |
728 | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ | |
729 | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; | |
730 | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; | |
731 | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; | |
732 | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); | |
733 | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); | |
734 | } | |
735 | ||
4b3fedf3 | 736 | static void omap_ulpd_pm_init(MemoryRegion *system_memory, |
a8170e5e | 737 | hwaddr base, |
c3d2689d AZ |
738 | struct omap_mpu_state_s *mpu) |
739 | { | |
2c9b15ca | 740 | memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, |
4b3fedf3 AK |
741 | "omap-ulpd-pm", 0x800); |
742 | memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); | |
c3d2689d AZ |
743 | omap_ulpd_pm_reset(mpu); |
744 | } | |
745 | ||
746 | /* OMAP Pin Configuration */ | |
a8170e5e | 747 | static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, |
4b3fedf3 | 748 | unsigned size) |
c3d2689d AZ |
749 | { |
750 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 751 | |
4b3fedf3 AK |
752 | if (size != 4) { |
753 | return omap_badwidth_read32(opaque, addr); | |
754 | } | |
755 | ||
8da3ff18 | 756 | switch (addr) { |
c3d2689d AZ |
757 | case 0x00: /* FUNC_MUX_CTRL_0 */ |
758 | case 0x04: /* FUNC_MUX_CTRL_1 */ | |
759 | case 0x08: /* FUNC_MUX_CTRL_2 */ | |
8da3ff18 | 760 | return s->func_mux_ctrl[addr >> 2]; |
c3d2689d AZ |
761 | |
762 | case 0x0c: /* COMP_MODE_CTRL_0 */ | |
763 | return s->comp_mode_ctrl[0]; | |
764 | ||
765 | case 0x10: /* FUNC_MUX_CTRL_3 */ | |
766 | case 0x14: /* FUNC_MUX_CTRL_4 */ | |
767 | case 0x18: /* FUNC_MUX_CTRL_5 */ | |
768 | case 0x1c: /* FUNC_MUX_CTRL_6 */ | |
769 | case 0x20: /* FUNC_MUX_CTRL_7 */ | |
770 | case 0x24: /* FUNC_MUX_CTRL_8 */ | |
771 | case 0x28: /* FUNC_MUX_CTRL_9 */ | |
772 | case 0x2c: /* FUNC_MUX_CTRL_A */ | |
773 | case 0x30: /* FUNC_MUX_CTRL_B */ | |
774 | case 0x34: /* FUNC_MUX_CTRL_C */ | |
775 | case 0x38: /* FUNC_MUX_CTRL_D */ | |
8da3ff18 | 776 | return s->func_mux_ctrl[(addr >> 2) - 1]; |
c3d2689d AZ |
777 | |
778 | case 0x40: /* PULL_DWN_CTRL_0 */ | |
779 | case 0x44: /* PULL_DWN_CTRL_1 */ | |
780 | case 0x48: /* PULL_DWN_CTRL_2 */ | |
781 | case 0x4c: /* PULL_DWN_CTRL_3 */ | |
8da3ff18 | 782 | return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; |
c3d2689d AZ |
783 | |
784 | case 0x50: /* GATE_INH_CTRL_0 */ | |
785 | return s->gate_inh_ctrl[0]; | |
786 | ||
787 | case 0x60: /* VOLTAGE_CTRL_0 */ | |
788 | return s->voltage_ctrl[0]; | |
789 | ||
790 | case 0x70: /* TEST_DBG_CTRL_0 */ | |
791 | return s->test_dbg_ctrl[0]; | |
792 | ||
793 | case 0x80: /* MOD_CONF_CTRL_0 */ | |
794 | return s->mod_conf_ctrl[0]; | |
795 | } | |
796 | ||
797 | OMAP_BAD_REG(addr); | |
798 | return 0; | |
799 | } | |
800 | ||
801 | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, | |
802 | uint32_t diff, uint32_t value) | |
803 | { | |
804 | if (s->compat1509) { | |
805 | if (diff & (1 << 9)) /* BLUETOOTH */ | |
806 | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), | |
807 | (~value >> 9) & 1); | |
808 | if (diff & (1 << 7)) /* USB.CLKO */ | |
809 | omap_clk_onoff(omap_findclk(s, "usb.clko"), | |
810 | (value >> 7) & 1); | |
811 | } | |
812 | } | |
813 | ||
814 | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, | |
815 | uint32_t diff, uint32_t value) | |
816 | { | |
817 | if (s->compat1509) { | |
d2f41a11 PM |
818 | if (diff & (1U << 31)) { |
819 | /* MCBSP3_CLK_HIZ_DI */ | |
820 | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); | |
821 | } | |
822 | if (diff & (1 << 1)) { | |
823 | /* CLK32K */ | |
824 | omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); | |
825 | } | |
c3d2689d AZ |
826 | } |
827 | } | |
828 | ||
829 | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, | |
830 | uint32_t diff, uint32_t value) | |
831 | { | |
d2f41a11 PM |
832 | if (diff & (1U << 31)) { |
833 | /* CONF_MOD_UART3_CLK_MODE_R */ | |
834 | omap_clk_reparent(omap_findclk(s, "uart3_ck"), | |
835 | omap_findclk(s, ((value >> 31) & 1) ? | |
836 | "ck_48m" : "armper_ck")); | |
837 | } | |
c3d2689d AZ |
838 | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
839 | omap_clk_reparent(omap_findclk(s, "uart2_ck"), | |
840 | omap_findclk(s, ((value >> 30) & 1) ? | |
841 | "ck_48m" : "armper_ck")); | |
842 | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ | |
843 | omap_clk_reparent(omap_findclk(s, "uart1_ck"), | |
844 | omap_findclk(s, ((value >> 29) & 1) ? | |
845 | "ck_48m" : "armper_ck")); | |
846 | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ | |
847 | omap_clk_reparent(omap_findclk(s, "mmc_ck"), | |
848 | omap_findclk(s, ((value >> 23) & 1) ? | |
849 | "ck_48m" : "armper_ck")); | |
850 | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ | |
851 | omap_clk_reparent(omap_findclk(s, "com_mclk_out"), | |
852 | omap_findclk(s, ((value >> 12) & 1) ? | |
853 | "ck_48m" : "armper_ck")); | |
854 | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ | |
855 | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); | |
856 | } | |
857 | ||
a8170e5e | 858 | static void omap_pin_cfg_write(void *opaque, hwaddr addr, |
4b3fedf3 | 859 | uint64_t value, unsigned size) |
c3d2689d AZ |
860 | { |
861 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
862 | uint32_t diff; |
863 | ||
4b3fedf3 | 864 | if (size != 4) { |
77a8257e SW |
865 | omap_badwidth_write32(opaque, addr, value); |
866 | return; | |
4b3fedf3 AK |
867 | } |
868 | ||
8da3ff18 | 869 | switch (addr) { |
c3d2689d | 870 | case 0x00: /* FUNC_MUX_CTRL_0 */ |
8da3ff18 PB |
871 | diff = s->func_mux_ctrl[addr >> 2] ^ value; |
872 | s->func_mux_ctrl[addr >> 2] = value; | |
c3d2689d AZ |
873 | omap_pin_funcmux0_update(s, diff, value); |
874 | return; | |
875 | ||
876 | case 0x04: /* FUNC_MUX_CTRL_1 */ | |
8da3ff18 PB |
877 | diff = s->func_mux_ctrl[addr >> 2] ^ value; |
878 | s->func_mux_ctrl[addr >> 2] = value; | |
c3d2689d AZ |
879 | omap_pin_funcmux1_update(s, diff, value); |
880 | return; | |
881 | ||
882 | case 0x08: /* FUNC_MUX_CTRL_2 */ | |
8da3ff18 | 883 | s->func_mux_ctrl[addr >> 2] = value; |
c3d2689d AZ |
884 | return; |
885 | ||
886 | case 0x0c: /* COMP_MODE_CTRL_0 */ | |
887 | s->comp_mode_ctrl[0] = value; | |
888 | s->compat1509 = (value != 0x0000eaef); | |
889 | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); | |
890 | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); | |
891 | return; | |
892 | ||
893 | case 0x10: /* FUNC_MUX_CTRL_3 */ | |
894 | case 0x14: /* FUNC_MUX_CTRL_4 */ | |
895 | case 0x18: /* FUNC_MUX_CTRL_5 */ | |
896 | case 0x1c: /* FUNC_MUX_CTRL_6 */ | |
897 | case 0x20: /* FUNC_MUX_CTRL_7 */ | |
898 | case 0x24: /* FUNC_MUX_CTRL_8 */ | |
899 | case 0x28: /* FUNC_MUX_CTRL_9 */ | |
900 | case 0x2c: /* FUNC_MUX_CTRL_A */ | |
901 | case 0x30: /* FUNC_MUX_CTRL_B */ | |
902 | case 0x34: /* FUNC_MUX_CTRL_C */ | |
903 | case 0x38: /* FUNC_MUX_CTRL_D */ | |
8da3ff18 | 904 | s->func_mux_ctrl[(addr >> 2) - 1] = value; |
c3d2689d AZ |
905 | return; |
906 | ||
907 | case 0x40: /* PULL_DWN_CTRL_0 */ | |
908 | case 0x44: /* PULL_DWN_CTRL_1 */ | |
909 | case 0x48: /* PULL_DWN_CTRL_2 */ | |
910 | case 0x4c: /* PULL_DWN_CTRL_3 */ | |
8da3ff18 | 911 | s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; |
c3d2689d AZ |
912 | return; |
913 | ||
914 | case 0x50: /* GATE_INH_CTRL_0 */ | |
915 | s->gate_inh_ctrl[0] = value; | |
916 | return; | |
917 | ||
918 | case 0x60: /* VOLTAGE_CTRL_0 */ | |
919 | s->voltage_ctrl[0] = value; | |
920 | return; | |
921 | ||
922 | case 0x70: /* TEST_DBG_CTRL_0 */ | |
923 | s->test_dbg_ctrl[0] = value; | |
924 | return; | |
925 | ||
926 | case 0x80: /* MOD_CONF_CTRL_0 */ | |
927 | diff = s->mod_conf_ctrl[0] ^ value; | |
928 | s->mod_conf_ctrl[0] = value; | |
929 | omap_pin_modconf1_update(s, diff, value); | |
930 | return; | |
931 | ||
932 | default: | |
933 | OMAP_BAD_REG(addr); | |
934 | } | |
935 | } | |
936 | ||
4b3fedf3 AK |
937 | static const MemoryRegionOps omap_pin_cfg_ops = { |
938 | .read = omap_pin_cfg_read, | |
939 | .write = omap_pin_cfg_write, | |
940 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
941 | }; |
942 | ||
943 | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) | |
944 | { | |
945 | /* Start in Compatibility Mode. */ | |
946 | mpu->compat1509 = 1; | |
947 | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); | |
948 | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); | |
949 | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); | |
950 | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); | |
951 | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); | |
952 | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); | |
953 | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); | |
954 | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); | |
955 | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); | |
956 | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); | |
957 | } | |
958 | ||
4b3fedf3 | 959 | static void omap_pin_cfg_init(MemoryRegion *system_memory, |
a8170e5e | 960 | hwaddr base, |
c3d2689d AZ |
961 | struct omap_mpu_state_s *mpu) |
962 | { | |
2c9b15ca | 963 | memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, |
4b3fedf3 AK |
964 | "omap-pin-cfg", 0x800); |
965 | memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); | |
c3d2689d AZ |
966 | omap_pin_cfg_reset(mpu); |
967 | } | |
968 | ||
969 | /* Device Identification, Die Identification */ | |
a8170e5e | 970 | static uint64_t omap_id_read(void *opaque, hwaddr addr, |
4b3fedf3 | 971 | unsigned size) |
c3d2689d AZ |
972 | { |
973 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
974 | ||
4b3fedf3 AK |
975 | if (size != 4) { |
976 | return omap_badwidth_read32(opaque, addr); | |
977 | } | |
978 | ||
c3d2689d AZ |
979 | switch (addr) { |
980 | case 0xfffe1800: /* DIE_ID_LSB */ | |
981 | return 0xc9581f0e; | |
982 | case 0xfffe1804: /* DIE_ID_MSB */ | |
983 | return 0xa8858bfa; | |
984 | ||
985 | case 0xfffe2000: /* PRODUCT_ID_LSB */ | |
986 | return 0x00aaaafc; | |
987 | case 0xfffe2004: /* PRODUCT_ID_MSB */ | |
988 | return 0xcafeb574; | |
989 | ||
990 | case 0xfffed400: /* JTAG_ID_LSB */ | |
991 | switch (s->mpu_model) { | |
992 | case omap310: | |
993 | return 0x03310315; | |
994 | case omap1510: | |
995 | return 0x03310115; | |
827df9f3 | 996 | default: |
2ac71179 | 997 | hw_error("%s: bad mpu model\n", __FUNCTION__); |
c3d2689d AZ |
998 | } |
999 | break; | |
1000 | ||
1001 | case 0xfffed404: /* JTAG_ID_MSB */ | |
1002 | switch (s->mpu_model) { | |
1003 | case omap310: | |
1004 | return 0xfb57402f; | |
1005 | case omap1510: | |
1006 | return 0xfb47002f; | |
827df9f3 | 1007 | default: |
2ac71179 | 1008 | hw_error("%s: bad mpu model\n", __FUNCTION__); |
c3d2689d AZ |
1009 | } |
1010 | break; | |
1011 | } | |
1012 | ||
1013 | OMAP_BAD_REG(addr); | |
1014 | return 0; | |
1015 | } | |
1016 | ||
a8170e5e | 1017 | static void omap_id_write(void *opaque, hwaddr addr, |
4b3fedf3 | 1018 | uint64_t value, unsigned size) |
c3d2689d | 1019 | { |
4b3fedf3 | 1020 | if (size != 4) { |
77a8257e SW |
1021 | omap_badwidth_write32(opaque, addr, value); |
1022 | return; | |
4b3fedf3 AK |
1023 | } |
1024 | ||
c3d2689d AZ |
1025 | OMAP_BAD_REG(addr); |
1026 | } | |
1027 | ||
4b3fedf3 AK |
1028 | static const MemoryRegionOps omap_id_ops = { |
1029 | .read = omap_id_read, | |
1030 | .write = omap_id_write, | |
1031 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1032 | }; |
1033 | ||
4b3fedf3 | 1034 | static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) |
c3d2689d | 1035 | { |
2c9b15ca | 1036 | memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, |
4b3fedf3 | 1037 | "omap-id", 0x100000000ULL); |
2c9b15ca | 1038 | memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, |
4b3fedf3 AK |
1039 | 0xfffe1800, 0x800); |
1040 | memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); | |
2c9b15ca | 1041 | memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, |
4b3fedf3 AK |
1042 | 0xfffed400, 0x100); |
1043 | memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); | |
1044 | if (!cpu_is_omap15xx(mpu)) { | |
2c9b15ca | 1045 | memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", |
4b3fedf3 AK |
1046 | &mpu->id_iomem, 0xfffe2000, 0x800); |
1047 | memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); | |
1048 | } | |
c3d2689d AZ |
1049 | } |
1050 | ||
1051 | /* MPUI Control (Dummy) */ | |
a8170e5e | 1052 | static uint64_t omap_mpui_read(void *opaque, hwaddr addr, |
4b3fedf3 | 1053 | unsigned size) |
c3d2689d AZ |
1054 | { |
1055 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1056 | |
4b3fedf3 AK |
1057 | if (size != 4) { |
1058 | return omap_badwidth_read32(opaque, addr); | |
1059 | } | |
1060 | ||
8da3ff18 | 1061 | switch (addr) { |
c3d2689d AZ |
1062 | case 0x00: /* CTRL */ |
1063 | return s->mpui_ctrl; | |
1064 | case 0x04: /* DEBUG_ADDR */ | |
1065 | return 0x01ffffff; | |
1066 | case 0x08: /* DEBUG_DATA */ | |
1067 | return 0xffffffff; | |
1068 | case 0x0c: /* DEBUG_FLAG */ | |
1069 | return 0x00000800; | |
1070 | case 0x10: /* STATUS */ | |
1071 | return 0x00000000; | |
1072 | ||
1073 | /* Not in OMAP310 */ | |
1074 | case 0x14: /* DSP_STATUS */ | |
1075 | case 0x18: /* DSP_BOOT_CONFIG */ | |
1076 | return 0x00000000; | |
1077 | case 0x1c: /* DSP_MPUI_CONFIG */ | |
1078 | return 0x0000ffff; | |
1079 | } | |
1080 | ||
1081 | OMAP_BAD_REG(addr); | |
1082 | return 0; | |
1083 | } | |
1084 | ||
a8170e5e | 1085 | static void omap_mpui_write(void *opaque, hwaddr addr, |
4b3fedf3 | 1086 | uint64_t value, unsigned size) |
c3d2689d AZ |
1087 | { |
1088 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1089 | |
4b3fedf3 | 1090 | if (size != 4) { |
77a8257e SW |
1091 | omap_badwidth_write32(opaque, addr, value); |
1092 | return; | |
4b3fedf3 AK |
1093 | } |
1094 | ||
8da3ff18 | 1095 | switch (addr) { |
c3d2689d AZ |
1096 | case 0x00: /* CTRL */ |
1097 | s->mpui_ctrl = value & 0x007fffff; | |
1098 | break; | |
1099 | ||
1100 | case 0x04: /* DEBUG_ADDR */ | |
1101 | case 0x08: /* DEBUG_DATA */ | |
1102 | case 0x0c: /* DEBUG_FLAG */ | |
1103 | case 0x10: /* STATUS */ | |
1104 | /* Not in OMAP310 */ | |
1105 | case 0x14: /* DSP_STATUS */ | |
1106 | OMAP_RO_REG(addr); | |
139bd956 | 1107 | break; |
c3d2689d AZ |
1108 | case 0x18: /* DSP_BOOT_CONFIG */ |
1109 | case 0x1c: /* DSP_MPUI_CONFIG */ | |
1110 | break; | |
1111 | ||
1112 | default: | |
1113 | OMAP_BAD_REG(addr); | |
1114 | } | |
1115 | } | |
1116 | ||
4b3fedf3 AK |
1117 | static const MemoryRegionOps omap_mpui_ops = { |
1118 | .read = omap_mpui_read, | |
1119 | .write = omap_mpui_write, | |
1120 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1121 | }; |
1122 | ||
1123 | static void omap_mpui_reset(struct omap_mpu_state_s *s) | |
1124 | { | |
1125 | s->mpui_ctrl = 0x0003ff1b; | |
1126 | } | |
1127 | ||
a8170e5e | 1128 | static void omap_mpui_init(MemoryRegion *memory, hwaddr base, |
c3d2689d AZ |
1129 | struct omap_mpu_state_s *mpu) |
1130 | { | |
2c9b15ca | 1131 | memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, |
4b3fedf3 AK |
1132 | "omap-mpui", 0x100); |
1133 | memory_region_add_subregion(memory, base, &mpu->mpui_iomem); | |
c3d2689d AZ |
1134 | |
1135 | omap_mpui_reset(mpu); | |
1136 | } | |
1137 | ||
1138 | /* TIPB Bridges */ | |
1139 | struct omap_tipb_bridge_s { | |
c3d2689d | 1140 | qemu_irq abort; |
4b3fedf3 | 1141 | MemoryRegion iomem; |
c3d2689d AZ |
1142 | |
1143 | int width_intr; | |
1144 | uint16_t control; | |
1145 | uint16_t alloc; | |
1146 | uint16_t buffer; | |
1147 | uint16_t enh_control; | |
1148 | }; | |
1149 | ||
a8170e5e | 1150 | static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, |
4b3fedf3 | 1151 | unsigned size) |
c3d2689d AZ |
1152 | { |
1153 | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; | |
c3d2689d | 1154 | |
4b3fedf3 AK |
1155 | if (size < 2) { |
1156 | return omap_badwidth_read16(opaque, addr); | |
1157 | } | |
1158 | ||
8da3ff18 | 1159 | switch (addr) { |
c3d2689d AZ |
1160 | case 0x00: /* TIPB_CNTL */ |
1161 | return s->control; | |
1162 | case 0x04: /* TIPB_BUS_ALLOC */ | |
1163 | return s->alloc; | |
1164 | case 0x08: /* MPU_TIPB_CNTL */ | |
1165 | return s->buffer; | |
1166 | case 0x0c: /* ENHANCED_TIPB_CNTL */ | |
1167 | return s->enh_control; | |
1168 | case 0x10: /* ADDRESS_DBG */ | |
1169 | case 0x14: /* DATA_DEBUG_LOW */ | |
1170 | case 0x18: /* DATA_DEBUG_HIGH */ | |
1171 | return 0xffff; | |
1172 | case 0x1c: /* DEBUG_CNTR_SIG */ | |
1173 | return 0x00f8; | |
1174 | } | |
1175 | ||
1176 | OMAP_BAD_REG(addr); | |
1177 | return 0; | |
1178 | } | |
1179 | ||
a8170e5e | 1180 | static void omap_tipb_bridge_write(void *opaque, hwaddr addr, |
4b3fedf3 | 1181 | uint64_t value, unsigned size) |
c3d2689d AZ |
1182 | { |
1183 | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; | |
c3d2689d | 1184 | |
4b3fedf3 | 1185 | if (size < 2) { |
77a8257e SW |
1186 | omap_badwidth_write16(opaque, addr, value); |
1187 | return; | |
4b3fedf3 AK |
1188 | } |
1189 | ||
8da3ff18 | 1190 | switch (addr) { |
c3d2689d AZ |
1191 | case 0x00: /* TIPB_CNTL */ |
1192 | s->control = value & 0xffff; | |
1193 | break; | |
1194 | ||
1195 | case 0x04: /* TIPB_BUS_ALLOC */ | |
1196 | s->alloc = value & 0x003f; | |
1197 | break; | |
1198 | ||
1199 | case 0x08: /* MPU_TIPB_CNTL */ | |
1200 | s->buffer = value & 0x0003; | |
1201 | break; | |
1202 | ||
1203 | case 0x0c: /* ENHANCED_TIPB_CNTL */ | |
1204 | s->width_intr = !(value & 2); | |
1205 | s->enh_control = value & 0x000f; | |
1206 | break; | |
1207 | ||
1208 | case 0x10: /* ADDRESS_DBG */ | |
1209 | case 0x14: /* DATA_DEBUG_LOW */ | |
1210 | case 0x18: /* DATA_DEBUG_HIGH */ | |
1211 | case 0x1c: /* DEBUG_CNTR_SIG */ | |
1212 | OMAP_RO_REG(addr); | |
1213 | break; | |
1214 | ||
1215 | default: | |
1216 | OMAP_BAD_REG(addr); | |
1217 | } | |
1218 | } | |
1219 | ||
4b3fedf3 AK |
1220 | static const MemoryRegionOps omap_tipb_bridge_ops = { |
1221 | .read = omap_tipb_bridge_read, | |
1222 | .write = omap_tipb_bridge_write, | |
1223 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1224 | }; |
1225 | ||
1226 | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) | |
1227 | { | |
1228 | s->control = 0xffff; | |
1229 | s->alloc = 0x0009; | |
1230 | s->buffer = 0x0000; | |
1231 | s->enh_control = 0x000f; | |
1232 | } | |
1233 | ||
4b3fedf3 | 1234 | static struct omap_tipb_bridge_s *omap_tipb_bridge_init( |
a8170e5e | 1235 | MemoryRegion *memory, hwaddr base, |
4b3fedf3 | 1236 | qemu_irq abort_irq, omap_clk clk) |
c3d2689d | 1237 | { |
b45c03f5 | 1238 | struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); |
c3d2689d AZ |
1239 | |
1240 | s->abort = abort_irq; | |
c3d2689d AZ |
1241 | omap_tipb_bridge_reset(s); |
1242 | ||
2c9b15ca | 1243 | memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, |
4b3fedf3 AK |
1244 | "omap-tipb-bridge", 0x100); |
1245 | memory_region_add_subregion(memory, base, &s->iomem); | |
c3d2689d AZ |
1246 | |
1247 | return s; | |
1248 | } | |
1249 | ||
1250 | /* Dummy Traffic Controller's Memory Interface */ | |
a8170e5e | 1251 | static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1252 | unsigned size) |
c3d2689d AZ |
1253 | { |
1254 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
1255 | uint32_t ret; |
1256 | ||
e7aa0ae0 AK |
1257 | if (size != 4) { |
1258 | return omap_badwidth_read32(opaque, addr); | |
1259 | } | |
1260 | ||
8da3ff18 | 1261 | switch (addr) { |
d8f699cb AZ |
1262 | case 0x00: /* IMIF_PRIO */ |
1263 | case 0x04: /* EMIFS_PRIO */ | |
1264 | case 0x08: /* EMIFF_PRIO */ | |
1265 | case 0x0c: /* EMIFS_CONFIG */ | |
1266 | case 0x10: /* EMIFS_CS0_CONFIG */ | |
1267 | case 0x14: /* EMIFS_CS1_CONFIG */ | |
1268 | case 0x18: /* EMIFS_CS2_CONFIG */ | |
1269 | case 0x1c: /* EMIFS_CS3_CONFIG */ | |
1270 | case 0x24: /* EMIFF_MRS */ | |
1271 | case 0x28: /* TIMEOUT1 */ | |
1272 | case 0x2c: /* TIMEOUT2 */ | |
1273 | case 0x30: /* TIMEOUT3 */ | |
1274 | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ | |
1275 | case 0x40: /* EMIFS_CFG_DYN_WAIT */ | |
8da3ff18 | 1276 | return s->tcmi_regs[addr >> 2]; |
c3d2689d | 1277 | |
d8f699cb | 1278 | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
8da3ff18 PB |
1279 | ret = s->tcmi_regs[addr >> 2]; |
1280 | s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ | |
c3d2689d AZ |
1281 | /* XXX: We can try using the VGA_DIRTY flag for this */ |
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | OMAP_BAD_REG(addr); | |
1286 | return 0; | |
1287 | } | |
1288 | ||
a8170e5e | 1289 | static void omap_tcmi_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1290 | uint64_t value, unsigned size) |
c3d2689d AZ |
1291 | { |
1292 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1293 | |
e7aa0ae0 | 1294 | if (size != 4) { |
77a8257e SW |
1295 | omap_badwidth_write32(opaque, addr, value); |
1296 | return; | |
e7aa0ae0 AK |
1297 | } |
1298 | ||
8da3ff18 | 1299 | switch (addr) { |
d8f699cb AZ |
1300 | case 0x00: /* IMIF_PRIO */ |
1301 | case 0x04: /* EMIFS_PRIO */ | |
1302 | case 0x08: /* EMIFF_PRIO */ | |
1303 | case 0x10: /* EMIFS_CS0_CONFIG */ | |
1304 | case 0x14: /* EMIFS_CS1_CONFIG */ | |
1305 | case 0x18: /* EMIFS_CS2_CONFIG */ | |
1306 | case 0x1c: /* EMIFS_CS3_CONFIG */ | |
1307 | case 0x20: /* EMIFF_SDRAM_CONFIG */ | |
1308 | case 0x24: /* EMIFF_MRS */ | |
1309 | case 0x28: /* TIMEOUT1 */ | |
1310 | case 0x2c: /* TIMEOUT2 */ | |
1311 | case 0x30: /* TIMEOUT3 */ | |
1312 | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ | |
1313 | case 0x40: /* EMIFS_CFG_DYN_WAIT */ | |
8da3ff18 | 1314 | s->tcmi_regs[addr >> 2] = value; |
c3d2689d | 1315 | break; |
d8f699cb | 1316 | case 0x0c: /* EMIFS_CONFIG */ |
8da3ff18 | 1317 | s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); |
c3d2689d AZ |
1318 | break; |
1319 | ||
1320 | default: | |
1321 | OMAP_BAD_REG(addr); | |
1322 | } | |
1323 | } | |
1324 | ||
e7aa0ae0 AK |
1325 | static const MemoryRegionOps omap_tcmi_ops = { |
1326 | .read = omap_tcmi_read, | |
1327 | .write = omap_tcmi_write, | |
1328 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1329 | }; |
1330 | ||
1331 | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) | |
1332 | { | |
1333 | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; | |
1334 | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; | |
1335 | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; | |
1336 | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; | |
1337 | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; | |
1338 | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; | |
1339 | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; | |
1340 | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; | |
1341 | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; | |
1342 | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; | |
1343 | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; | |
1344 | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; | |
1345 | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; | |
1346 | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; | |
1347 | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; | |
1348 | } | |
1349 | ||
a8170e5e | 1350 | static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, |
c3d2689d AZ |
1351 | struct omap_mpu_state_s *mpu) |
1352 | { | |
2c9b15ca | 1353 | memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, |
e7aa0ae0 AK |
1354 | "omap-tcmi", 0x100); |
1355 | memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); | |
c3d2689d AZ |
1356 | omap_tcmi_reset(mpu); |
1357 | } | |
1358 | ||
1359 | /* Digital phase-locked loops control */ | |
b9f7bc40 JR |
1360 | struct dpll_ctl_s { |
1361 | MemoryRegion iomem; | |
1362 | uint16_t mode; | |
1363 | omap_clk dpll; | |
1364 | }; | |
1365 | ||
a8170e5e | 1366 | static uint64_t omap_dpll_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1367 | unsigned size) |
c3d2689d AZ |
1368 | { |
1369 | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; | |
c3d2689d | 1370 | |
e7aa0ae0 AK |
1371 | if (size != 2) { |
1372 | return omap_badwidth_read16(opaque, addr); | |
1373 | } | |
1374 | ||
8da3ff18 | 1375 | if (addr == 0x00) /* CTL_REG */ |
c3d2689d AZ |
1376 | return s->mode; |
1377 | ||
1378 | OMAP_BAD_REG(addr); | |
1379 | return 0; | |
1380 | } | |
1381 | ||
a8170e5e | 1382 | static void omap_dpll_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1383 | uint64_t value, unsigned size) |
c3d2689d AZ |
1384 | { |
1385 | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; | |
1386 | uint16_t diff; | |
c3d2689d AZ |
1387 | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1388 | int div, mult; | |
1389 | ||
e7aa0ae0 | 1390 | if (size != 2) { |
77a8257e SW |
1391 | omap_badwidth_write16(opaque, addr, value); |
1392 | return; | |
e7aa0ae0 AK |
1393 | } |
1394 | ||
8da3ff18 | 1395 | if (addr == 0x00) { /* CTL_REG */ |
c3d2689d AZ |
1396 | /* See omap_ulpd_pm_write() too */ |
1397 | diff = s->mode & value; | |
1398 | s->mode = value & 0x2fff; | |
1399 | if (diff & (0x3ff << 2)) { | |
1400 | if (value & (1 << 4)) { /* PLL_ENABLE */ | |
1401 | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ | |
1402 | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ | |
1403 | } else { | |
1404 | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ | |
1405 | mult = 1; | |
1406 | } | |
1407 | omap_clk_setrate(s->dpll, div, mult); | |
1408 | } | |
1409 | ||
1410 | /* Enter the desired mode. */ | |
1411 | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); | |
1412 | ||
1413 | /* Act as if the lock is restored. */ | |
1414 | s->mode |= 2; | |
1415 | } else { | |
1416 | OMAP_BAD_REG(addr); | |
1417 | } | |
1418 | } | |
1419 | ||
e7aa0ae0 AK |
1420 | static const MemoryRegionOps omap_dpll_ops = { |
1421 | .read = omap_dpll_read, | |
1422 | .write = omap_dpll_write, | |
1423 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1424 | }; |
1425 | ||
1426 | static void omap_dpll_reset(struct dpll_ctl_s *s) | |
1427 | { | |
1428 | s->mode = 0x2002; | |
1429 | omap_clk_setrate(s->dpll, 1, 1); | |
1430 | } | |
1431 | ||
b9f7bc40 | 1432 | static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, |
a8170e5e | 1433 | hwaddr base, omap_clk clk) |
c3d2689d | 1434 | { |
b9f7bc40 | 1435 | struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); |
2c9b15ca | 1436 | memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); |
c3d2689d | 1437 | |
c3d2689d AZ |
1438 | s->dpll = clk; |
1439 | omap_dpll_reset(s); | |
1440 | ||
e7aa0ae0 | 1441 | memory_region_add_subregion(memory, base, &s->iomem); |
b9f7bc40 | 1442 | return s; |
c3d2689d AZ |
1443 | } |
1444 | ||
c3d2689d | 1445 | /* MPU Clock/Reset/Power Mode Control */ |
a8170e5e | 1446 | static uint64_t omap_clkm_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1447 | unsigned size) |
c3d2689d AZ |
1448 | { |
1449 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1450 | |
e7aa0ae0 AK |
1451 | if (size != 2) { |
1452 | return omap_badwidth_read16(opaque, addr); | |
1453 | } | |
1454 | ||
8da3ff18 | 1455 | switch (addr) { |
c3d2689d AZ |
1456 | case 0x00: /* ARM_CKCTL */ |
1457 | return s->clkm.arm_ckctl; | |
1458 | ||
1459 | case 0x04: /* ARM_IDLECT1 */ | |
1460 | return s->clkm.arm_idlect1; | |
1461 | ||
1462 | case 0x08: /* ARM_IDLECT2 */ | |
1463 | return s->clkm.arm_idlect2; | |
1464 | ||
1465 | case 0x0c: /* ARM_EWUPCT */ | |
1466 | return s->clkm.arm_ewupct; | |
1467 | ||
1468 | case 0x10: /* ARM_RSTCT1 */ | |
1469 | return s->clkm.arm_rstct1; | |
1470 | ||
1471 | case 0x14: /* ARM_RSTCT2 */ | |
1472 | return s->clkm.arm_rstct2; | |
1473 | ||
1474 | case 0x18: /* ARM_SYSST */ | |
d8f699cb | 1475 | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
c3d2689d AZ |
1476 | |
1477 | case 0x1c: /* ARM_CKOUT1 */ | |
1478 | return s->clkm.arm_ckout1; | |
1479 | ||
1480 | case 0x20: /* ARM_CKOUT2 */ | |
1481 | break; | |
1482 | } | |
1483 | ||
1484 | OMAP_BAD_REG(addr); | |
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, | |
1489 | uint16_t diff, uint16_t value) | |
1490 | { | |
1491 | omap_clk clk; | |
1492 | ||
1493 | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ | |
1494 | if (value & (1 << 14)) | |
1495 | /* Reserved */; | |
1496 | else { | |
1497 | clk = omap_findclk(s, "arminth_ck"); | |
1498 | omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); | |
1499 | } | |
1500 | } | |
1501 | if (diff & (1 << 12)) { /* ARM_TIMXO */ | |
1502 | clk = omap_findclk(s, "armtim_ck"); | |
1503 | if (value & (1 << 12)) | |
1504 | omap_clk_reparent(clk, omap_findclk(s, "clkin")); | |
1505 | else | |
1506 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); | |
1507 | } | |
1508 | /* XXX: en_dspck */ | |
1509 | if (diff & (3 << 10)) { /* DSPMMUDIV */ | |
1510 | clk = omap_findclk(s, "dspmmu_ck"); | |
1511 | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); | |
1512 | } | |
1513 | if (diff & (3 << 8)) { /* TCDIV */ | |
1514 | clk = omap_findclk(s, "tc_ck"); | |
1515 | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); | |
1516 | } | |
1517 | if (diff & (3 << 6)) { /* DSPDIV */ | |
1518 | clk = omap_findclk(s, "dsp_ck"); | |
1519 | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); | |
1520 | } | |
1521 | if (diff & (3 << 4)) { /* ARMDIV */ | |
1522 | clk = omap_findclk(s, "arm_ck"); | |
1523 | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); | |
1524 | } | |
1525 | if (diff & (3 << 2)) { /* LCDDIV */ | |
1526 | clk = omap_findclk(s, "lcd_ck"); | |
1527 | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); | |
1528 | } | |
1529 | if (diff & (3 << 0)) { /* PERDIV */ | |
1530 | clk = omap_findclk(s, "armper_ck"); | |
1531 | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); | |
1532 | } | |
1533 | } | |
1534 | ||
1535 | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, | |
1536 | uint16_t diff, uint16_t value) | |
1537 | { | |
1538 | omap_clk clk; | |
1539 | ||
5f4ef08b | 1540 | if (value & (1 << 11)) { /* SETARM_IDLE */ |
c3affe56 | 1541 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); |
5f4ef08b | 1542 | } |
c3d2689d AZ |
1543 | if (!(value & (1 << 10))) /* WKUP_MODE */ |
1544 | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ | |
1545 | ||
1546 | #define SET_CANIDLE(clock, bit) \ | |
1547 | if (diff & (1 << bit)) { \ | |
1548 | clk = omap_findclk(s, clock); \ | |
1549 | omap_clk_canidle(clk, (value >> bit) & 1); \ | |
1550 | } | |
1551 | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ | |
1552 | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ | |
1553 | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ | |
1554 | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ | |
1555 | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ | |
1556 | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ | |
1557 | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ | |
1558 | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ | |
1559 | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ | |
1560 | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ | |
1561 | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ | |
1562 | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ | |
1563 | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ | |
1564 | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ | |
1565 | } | |
1566 | ||
1567 | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, | |
1568 | uint16_t diff, uint16_t value) | |
1569 | { | |
1570 | omap_clk clk; | |
1571 | ||
1572 | #define SET_ONOFF(clock, bit) \ | |
1573 | if (diff & (1 << bit)) { \ | |
1574 | clk = omap_findclk(s, clock); \ | |
1575 | omap_clk_onoff(clk, (value >> bit) & 1); \ | |
1576 | } | |
1577 | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ | |
1578 | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ | |
1579 | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ | |
1580 | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ | |
1581 | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ | |
1582 | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ | |
1583 | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ | |
1584 | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ | |
1585 | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ | |
1586 | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ | |
1587 | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ | |
1588 | } | |
1589 | ||
1590 | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, | |
1591 | uint16_t diff, uint16_t value) | |
1592 | { | |
1593 | omap_clk clk; | |
1594 | ||
1595 | if (diff & (3 << 4)) { /* TCLKOUT */ | |
1596 | clk = omap_findclk(s, "tclk_out"); | |
1597 | switch ((value >> 4) & 3) { | |
1598 | case 1: | |
1599 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); | |
1600 | omap_clk_onoff(clk, 1); | |
1601 | break; | |
1602 | case 2: | |
1603 | omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); | |
1604 | omap_clk_onoff(clk, 1); | |
1605 | break; | |
1606 | default: | |
1607 | omap_clk_onoff(clk, 0); | |
1608 | } | |
1609 | } | |
1610 | if (diff & (3 << 2)) { /* DCLKOUT */ | |
1611 | clk = omap_findclk(s, "dclk_out"); | |
1612 | switch ((value >> 2) & 3) { | |
1613 | case 0: | |
1614 | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); | |
1615 | break; | |
1616 | case 1: | |
1617 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); | |
1618 | break; | |
1619 | case 2: | |
1620 | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); | |
1621 | break; | |
1622 | case 3: | |
1623 | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); | |
1624 | break; | |
1625 | } | |
1626 | } | |
1627 | if (diff & (3 << 0)) { /* ACLKOUT */ | |
1628 | clk = omap_findclk(s, "aclk_out"); | |
1629 | switch ((value >> 0) & 3) { | |
1630 | case 1: | |
1631 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); | |
1632 | omap_clk_onoff(clk, 1); | |
1633 | break; | |
1634 | case 2: | |
1635 | omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); | |
1636 | omap_clk_onoff(clk, 1); | |
1637 | break; | |
1638 | case 3: | |
1639 | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); | |
1640 | omap_clk_onoff(clk, 1); | |
1641 | break; | |
1642 | default: | |
1643 | omap_clk_onoff(clk, 0); | |
1644 | } | |
1645 | } | |
1646 | } | |
1647 | ||
a8170e5e | 1648 | static void omap_clkm_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1649 | uint64_t value, unsigned size) |
c3d2689d AZ |
1650 | { |
1651 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
1652 | uint16_t diff; |
1653 | omap_clk clk; | |
1654 | static const char *clkschemename[8] = { | |
1655 | "fully synchronous", "fully asynchronous", "synchronous scalable", | |
1656 | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", | |
1657 | }; | |
1658 | ||
e7aa0ae0 | 1659 | if (size != 2) { |
77a8257e SW |
1660 | omap_badwidth_write16(opaque, addr, value); |
1661 | return; | |
e7aa0ae0 AK |
1662 | } |
1663 | ||
8da3ff18 | 1664 | switch (addr) { |
c3d2689d AZ |
1665 | case 0x00: /* ARM_CKCTL */ |
1666 | diff = s->clkm.arm_ckctl ^ value; | |
1667 | s->clkm.arm_ckctl = value & 0x7fff; | |
1668 | omap_clkm_ckctl_update(s, diff, value); | |
1669 | return; | |
1670 | ||
1671 | case 0x04: /* ARM_IDLECT1 */ | |
1672 | diff = s->clkm.arm_idlect1 ^ value; | |
1673 | s->clkm.arm_idlect1 = value & 0x0fff; | |
1674 | omap_clkm_idlect1_update(s, diff, value); | |
1675 | return; | |
1676 | ||
1677 | case 0x08: /* ARM_IDLECT2 */ | |
1678 | diff = s->clkm.arm_idlect2 ^ value; | |
1679 | s->clkm.arm_idlect2 = value & 0x07ff; | |
1680 | omap_clkm_idlect2_update(s, diff, value); | |
1681 | return; | |
1682 | ||
1683 | case 0x0c: /* ARM_EWUPCT */ | |
c3d2689d AZ |
1684 | s->clkm.arm_ewupct = value & 0x003f; |
1685 | return; | |
1686 | ||
1687 | case 0x10: /* ARM_RSTCT1 */ | |
1688 | diff = s->clkm.arm_rstct1 ^ value; | |
1689 | s->clkm.arm_rstct1 = value & 0x0007; | |
1690 | if (value & 9) { | |
1691 | qemu_system_reset_request(); | |
1692 | s->clkm.cold_start = 0xa; | |
1693 | } | |
1694 | if (diff & ~value & 4) { /* DSP_RST */ | |
1695 | omap_mpui_reset(s); | |
1696 | omap_tipb_bridge_reset(s->private_tipb); | |
1697 | omap_tipb_bridge_reset(s->public_tipb); | |
1698 | } | |
1699 | if (diff & 2) { /* DSP_EN */ | |
1700 | clk = omap_findclk(s, "dsp_ck"); | |
1701 | omap_clk_canidle(clk, (~value >> 1) & 1); | |
1702 | } | |
1703 | return; | |
1704 | ||
1705 | case 0x14: /* ARM_RSTCT2 */ | |
1706 | s->clkm.arm_rstct2 = value & 0x0001; | |
1707 | return; | |
1708 | ||
1709 | case 0x18: /* ARM_SYSST */ | |
1710 | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { | |
1711 | s->clkm.clocking_scheme = (value >> 11) & 7; | |
1712 | printf("%s: clocking scheme set to %s\n", __FUNCTION__, | |
1713 | clkschemename[s->clkm.clocking_scheme]); | |
1714 | } | |
1715 | s->clkm.cold_start &= value & 0x3f; | |
1716 | return; | |
1717 | ||
1718 | case 0x1c: /* ARM_CKOUT1 */ | |
1719 | diff = s->clkm.arm_ckout1 ^ value; | |
1720 | s->clkm.arm_ckout1 = value & 0x003f; | |
1721 | omap_clkm_ckout1_update(s, diff, value); | |
1722 | return; | |
1723 | ||
1724 | case 0x20: /* ARM_CKOUT2 */ | |
1725 | default: | |
1726 | OMAP_BAD_REG(addr); | |
1727 | } | |
1728 | } | |
1729 | ||
e7aa0ae0 AK |
1730 | static const MemoryRegionOps omap_clkm_ops = { |
1731 | .read = omap_clkm_read, | |
1732 | .write = omap_clkm_write, | |
1733 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1734 | }; |
1735 | ||
a8170e5e | 1736 | static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1737 | unsigned size) |
c3d2689d AZ |
1738 | { |
1739 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
259186a7 | 1740 | CPUState *cpu = CPU(s->cpu); |
c3d2689d | 1741 | |
e7aa0ae0 AK |
1742 | if (size != 2) { |
1743 | return omap_badwidth_read16(opaque, addr); | |
1744 | } | |
1745 | ||
8da3ff18 | 1746 | switch (addr) { |
c3d2689d AZ |
1747 | case 0x04: /* DSP_IDLECT1 */ |
1748 | return s->clkm.dsp_idlect1; | |
1749 | ||
1750 | case 0x08: /* DSP_IDLECT2 */ | |
1751 | return s->clkm.dsp_idlect2; | |
1752 | ||
1753 | case 0x14: /* DSP_RSTCT2 */ | |
1754 | return s->clkm.dsp_rstct2; | |
1755 | ||
1756 | case 0x18: /* DSP_SYSST */ | |
259186a7 | 1757 | cpu = CPU(s->cpu); |
d8f699cb | 1758 | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
259186a7 | 1759 | (cpu->halted << 6); /* Quite useless... */ |
c3d2689d AZ |
1760 | } |
1761 | ||
1762 | OMAP_BAD_REG(addr); | |
1763 | return 0; | |
1764 | } | |
1765 | ||
1766 | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, | |
1767 | uint16_t diff, uint16_t value) | |
1768 | { | |
1769 | omap_clk clk; | |
1770 | ||
1771 | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ | |
1772 | } | |
1773 | ||
1774 | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, | |
1775 | uint16_t diff, uint16_t value) | |
1776 | { | |
1777 | omap_clk clk; | |
1778 | ||
1779 | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ | |
1780 | } | |
1781 | ||
a8170e5e | 1782 | static void omap_clkdsp_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1783 | uint64_t value, unsigned size) |
c3d2689d AZ |
1784 | { |
1785 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
1786 | uint16_t diff; |
1787 | ||
e7aa0ae0 | 1788 | if (size != 2) { |
77a8257e SW |
1789 | omap_badwidth_write16(opaque, addr, value); |
1790 | return; | |
e7aa0ae0 AK |
1791 | } |
1792 | ||
8da3ff18 | 1793 | switch (addr) { |
c3d2689d AZ |
1794 | case 0x04: /* DSP_IDLECT1 */ |
1795 | diff = s->clkm.dsp_idlect1 ^ value; | |
1796 | s->clkm.dsp_idlect1 = value & 0x01f7; | |
1797 | omap_clkdsp_idlect1_update(s, diff, value); | |
1798 | break; | |
1799 | ||
1800 | case 0x08: /* DSP_IDLECT2 */ | |
1801 | s->clkm.dsp_idlect2 = value & 0x0037; | |
1802 | diff = s->clkm.dsp_idlect1 ^ value; | |
1803 | omap_clkdsp_idlect2_update(s, diff, value); | |
1804 | break; | |
1805 | ||
1806 | case 0x14: /* DSP_RSTCT2 */ | |
1807 | s->clkm.dsp_rstct2 = value & 0x0001; | |
1808 | break; | |
1809 | ||
1810 | case 0x18: /* DSP_SYSST */ | |
1811 | s->clkm.cold_start &= value & 0x3f; | |
1812 | break; | |
1813 | ||
1814 | default: | |
1815 | OMAP_BAD_REG(addr); | |
1816 | } | |
1817 | } | |
1818 | ||
e7aa0ae0 AK |
1819 | static const MemoryRegionOps omap_clkdsp_ops = { |
1820 | .read = omap_clkdsp_read, | |
1821 | .write = omap_clkdsp_write, | |
1822 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1823 | }; |
1824 | ||
1825 | static void omap_clkm_reset(struct omap_mpu_state_s *s) | |
1826 | { | |
1827 | if (s->wdt && s->wdt->reset) | |
1828 | s->clkm.cold_start = 0x6; | |
1829 | s->clkm.clocking_scheme = 0; | |
1830 | omap_clkm_ckctl_update(s, ~0, 0x3000); | |
1831 | s->clkm.arm_ckctl = 0x3000; | |
d8f699cb | 1832 | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
c3d2689d | 1833 | s->clkm.arm_idlect1 = 0x0400; |
d8f699cb | 1834 | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
c3d2689d AZ |
1835 | s->clkm.arm_idlect2 = 0x0100; |
1836 | s->clkm.arm_ewupct = 0x003f; | |
1837 | s->clkm.arm_rstct1 = 0x0000; | |
1838 | s->clkm.arm_rstct2 = 0x0000; | |
1839 | s->clkm.arm_ckout1 = 0x0015; | |
1840 | s->clkm.dpll1_mode = 0x2002; | |
1841 | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); | |
1842 | s->clkm.dsp_idlect1 = 0x0040; | |
1843 | omap_clkdsp_idlect2_update(s, ~0, 0x0000); | |
1844 | s->clkm.dsp_idlect2 = 0x0000; | |
1845 | s->clkm.dsp_rstct2 = 0x0000; | |
1846 | } | |
1847 | ||
a8170e5e AK |
1848 | static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, |
1849 | hwaddr dsp_base, struct omap_mpu_state_s *s) | |
c3d2689d | 1850 | { |
2c9b15ca | 1851 | memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, |
e7aa0ae0 | 1852 | "omap-clkm", 0x100); |
2c9b15ca | 1853 | memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, |
e7aa0ae0 | 1854 | "omap-clkdsp", 0x1000); |
c3d2689d | 1855 | |
d8f699cb AZ |
1856 | s->clkm.arm_idlect1 = 0x03ff; |
1857 | s->clkm.arm_idlect2 = 0x0100; | |
1858 | s->clkm.dsp_idlect1 = 0x0002; | |
c3d2689d | 1859 | omap_clkm_reset(s); |
d8f699cb | 1860 | s->clkm.cold_start = 0x3a; |
c3d2689d | 1861 | |
e7aa0ae0 AK |
1862 | memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); |
1863 | memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); | |
c3d2689d AZ |
1864 | } |
1865 | ||
fe71e81a AZ |
1866 | /* MPU I/O */ |
1867 | struct omap_mpuio_s { | |
fe71e81a AZ |
1868 | qemu_irq irq; |
1869 | qemu_irq kbd_irq; | |
1870 | qemu_irq *in; | |
1871 | qemu_irq handler[16]; | |
1872 | qemu_irq wakeup; | |
e7aa0ae0 | 1873 | MemoryRegion iomem; |
fe71e81a AZ |
1874 | |
1875 | uint16_t inputs; | |
1876 | uint16_t outputs; | |
1877 | uint16_t dir; | |
1878 | uint16_t edge; | |
1879 | uint16_t mask; | |
1880 | uint16_t ints; | |
1881 | ||
1882 | uint16_t debounce; | |
1883 | uint16_t latch; | |
1884 | uint8_t event; | |
1885 | ||
1886 | uint8_t buttons[5]; | |
1887 | uint8_t row_latch; | |
1888 | uint8_t cols; | |
1889 | int kbd_mask; | |
1890 | int clk; | |
1891 | }; | |
1892 | ||
1893 | static void omap_mpuio_set(void *opaque, int line, int level) | |
1894 | { | |
1895 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
1896 | uint16_t prev = s->inputs; | |
1897 | ||
1898 | if (level) | |
1899 | s->inputs |= 1 << line; | |
1900 | else | |
1901 | s->inputs &= ~(1 << line); | |
1902 | ||
1903 | if (((1 << line) & s->dir & ~s->mask) && s->clk) { | |
1904 | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { | |
1905 | s->ints |= 1 << line; | |
1906 | qemu_irq_raise(s->irq); | |
1907 | /* TODO: wakeup */ | |
1908 | } | |
1909 | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ | |
1910 | (s->event >> 1) == line) /* PIN_SELECT */ | |
1911 | s->latch = s->inputs; | |
1912 | } | |
1913 | } | |
1914 | ||
1915 | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) | |
1916 | { | |
1917 | int i; | |
1918 | uint8_t *row, rows = 0, cols = ~s->cols; | |
1919 | ||
38a34e1d | 1920 | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
fe71e81a | 1921 | if (*row & cols) |
38a34e1d | 1922 | rows |= i; |
fe71e81a | 1923 | |
cf6d9118 AZ |
1924 | qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
1925 | s->row_latch = ~rows; | |
fe71e81a AZ |
1926 | } |
1927 | ||
a8170e5e | 1928 | static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1929 | unsigned size) |
fe71e81a AZ |
1930 | { |
1931 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
cf965d24 | 1932 | int offset = addr & OMAP_MPUI_REG_MASK; |
fe71e81a AZ |
1933 | uint16_t ret; |
1934 | ||
e7aa0ae0 AK |
1935 | if (size != 2) { |
1936 | return omap_badwidth_read16(opaque, addr); | |
1937 | } | |
1938 | ||
fe71e81a AZ |
1939 | switch (offset) { |
1940 | case 0x00: /* INPUT_LATCH */ | |
1941 | return s->inputs; | |
1942 | ||
1943 | case 0x04: /* OUTPUT_REG */ | |
1944 | return s->outputs; | |
1945 | ||
1946 | case 0x08: /* IO_CNTL */ | |
1947 | return s->dir; | |
1948 | ||
1949 | case 0x10: /* KBR_LATCH */ | |
1950 | return s->row_latch; | |
1951 | ||
1952 | case 0x14: /* KBC_REG */ | |
1953 | return s->cols; | |
1954 | ||
1955 | case 0x18: /* GPIO_EVENT_MODE_REG */ | |
1956 | return s->event; | |
1957 | ||
1958 | case 0x1c: /* GPIO_INT_EDGE_REG */ | |
1959 | return s->edge; | |
1960 | ||
1961 | case 0x20: /* KBD_INT */ | |
cf6d9118 | 1962 | return (~s->row_latch & 0x1f) && !s->kbd_mask; |
fe71e81a AZ |
1963 | |
1964 | case 0x24: /* GPIO_INT */ | |
1965 | ret = s->ints; | |
8e129e07 AZ |
1966 | s->ints &= s->mask; |
1967 | if (ret) | |
1968 | qemu_irq_lower(s->irq); | |
fe71e81a AZ |
1969 | return ret; |
1970 | ||
1971 | case 0x28: /* KBD_MASKIT */ | |
1972 | return s->kbd_mask; | |
1973 | ||
1974 | case 0x2c: /* GPIO_MASKIT */ | |
1975 | return s->mask; | |
1976 | ||
1977 | case 0x30: /* GPIO_DEBOUNCING_REG */ | |
1978 | return s->debounce; | |
1979 | ||
1980 | case 0x34: /* GPIO_LATCH_REG */ | |
1981 | return s->latch; | |
1982 | } | |
1983 | ||
1984 | OMAP_BAD_REG(addr); | |
1985 | return 0; | |
1986 | } | |
1987 | ||
a8170e5e | 1988 | static void omap_mpuio_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1989 | uint64_t value, unsigned size) |
fe71e81a AZ |
1990 | { |
1991 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
cf965d24 | 1992 | int offset = addr & OMAP_MPUI_REG_MASK; |
fe71e81a AZ |
1993 | uint16_t diff; |
1994 | int ln; | |
1995 | ||
e7aa0ae0 | 1996 | if (size != 2) { |
77a8257e SW |
1997 | omap_badwidth_write16(opaque, addr, value); |
1998 | return; | |
e7aa0ae0 AK |
1999 | } |
2000 | ||
fe71e81a AZ |
2001 | switch (offset) { |
2002 | case 0x04: /* OUTPUT_REG */ | |
d8f699cb | 2003 | diff = (s->outputs ^ value) & ~s->dir; |
fe71e81a | 2004 | s->outputs = value; |
bd2a8884 | 2005 | while ((ln = ctz32(diff)) != 32) { |
fe71e81a AZ |
2006 | if (s->handler[ln]) |
2007 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); | |
2008 | diff &= ~(1 << ln); | |
2009 | } | |
2010 | break; | |
2011 | ||
2012 | case 0x08: /* IO_CNTL */ | |
2013 | diff = s->outputs & (s->dir ^ value); | |
2014 | s->dir = value; | |
2015 | ||
2016 | value = s->outputs & ~s->dir; | |
bd2a8884 | 2017 | while ((ln = ctz32(diff)) != 32) { |
fe71e81a AZ |
2018 | if (s->handler[ln]) |
2019 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); | |
2020 | diff &= ~(1 << ln); | |
2021 | } | |
2022 | break; | |
2023 | ||
2024 | case 0x14: /* KBC_REG */ | |
2025 | s->cols = value; | |
2026 | omap_mpuio_kbd_update(s); | |
2027 | break; | |
2028 | ||
2029 | case 0x18: /* GPIO_EVENT_MODE_REG */ | |
2030 | s->event = value & 0x1f; | |
2031 | break; | |
2032 | ||
2033 | case 0x1c: /* GPIO_INT_EDGE_REG */ | |
2034 | s->edge = value; | |
2035 | break; | |
2036 | ||
2037 | case 0x28: /* KBD_MASKIT */ | |
2038 | s->kbd_mask = value & 1; | |
2039 | omap_mpuio_kbd_update(s); | |
2040 | break; | |
2041 | ||
2042 | case 0x2c: /* GPIO_MASKIT */ | |
2043 | s->mask = value; | |
2044 | break; | |
2045 | ||
2046 | case 0x30: /* GPIO_DEBOUNCING_REG */ | |
2047 | s->debounce = value & 0x1ff; | |
2048 | break; | |
2049 | ||
2050 | case 0x00: /* INPUT_LATCH */ | |
2051 | case 0x10: /* KBR_LATCH */ | |
2052 | case 0x20: /* KBD_INT */ | |
2053 | case 0x24: /* GPIO_INT */ | |
2054 | case 0x34: /* GPIO_LATCH_REG */ | |
2055 | OMAP_RO_REG(addr); | |
2056 | return; | |
2057 | ||
2058 | default: | |
2059 | OMAP_BAD_REG(addr); | |
2060 | return; | |
2061 | } | |
2062 | } | |
2063 | ||
e7aa0ae0 AK |
2064 | static const MemoryRegionOps omap_mpuio_ops = { |
2065 | .read = omap_mpuio_read, | |
2066 | .write = omap_mpuio_write, | |
2067 | .endianness = DEVICE_NATIVE_ENDIAN, | |
fe71e81a AZ |
2068 | }; |
2069 | ||
9596ebb7 | 2070 | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
fe71e81a AZ |
2071 | { |
2072 | s->inputs = 0; | |
2073 | s->outputs = 0; | |
2074 | s->dir = ~0; | |
2075 | s->event = 0; | |
2076 | s->edge = 0; | |
2077 | s->kbd_mask = 0; | |
2078 | s->mask = 0; | |
2079 | s->debounce = 0; | |
2080 | s->latch = 0; | |
2081 | s->ints = 0; | |
2082 | s->row_latch = 0x1f; | |
38a34e1d | 2083 | s->clk = 1; |
fe71e81a AZ |
2084 | } |
2085 | ||
2086 | static void omap_mpuio_onoff(void *opaque, int line, int on) | |
2087 | { | |
2088 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
2089 | ||
2090 | s->clk = on; | |
2091 | if (on) | |
2092 | omap_mpuio_kbd_update(s); | |
2093 | } | |
2094 | ||
3b204c81 | 2095 | static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, |
a8170e5e | 2096 | hwaddr base, |
fe71e81a AZ |
2097 | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
2098 | omap_clk clk) | |
2099 | { | |
b45c03f5 | 2100 | struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); |
fe71e81a | 2101 | |
fe71e81a AZ |
2102 | s->irq = gpio_int; |
2103 | s->kbd_irq = kbd_int; | |
2104 | s->wakeup = wakeup; | |
2105 | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); | |
2106 | omap_mpuio_reset(s); | |
2107 | ||
2c9b15ca | 2108 | memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, |
e7aa0ae0 AK |
2109 | "omap-mpuio", 0x800); |
2110 | memory_region_add_subregion(memory, base, &s->iomem); | |
fe71e81a | 2111 | |
f3c7d038 | 2112 | omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); |
fe71e81a AZ |
2113 | |
2114 | return s; | |
2115 | } | |
2116 | ||
2117 | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) | |
2118 | { | |
2119 | return s->in; | |
2120 | } | |
2121 | ||
2122 | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) | |
2123 | { | |
2124 | if (line >= 16 || line < 0) | |
2ac71179 | 2125 | hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); |
fe71e81a AZ |
2126 | s->handler[line] = handler; |
2127 | } | |
2128 | ||
2129 | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) | |
2130 | { | |
2131 | if (row >= 5 || row < 0) | |
2ac71179 | 2132 | hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); |
fe71e81a AZ |
2133 | |
2134 | if (down) | |
38a34e1d | 2135 | s->buttons[row] |= 1 << col; |
fe71e81a | 2136 | else |
38a34e1d | 2137 | s->buttons[row] &= ~(1 << col); |
fe71e81a AZ |
2138 | |
2139 | omap_mpuio_kbd_update(s); | |
2140 | } | |
2141 | ||
d951f6ff AZ |
2142 | /* MicroWire Interface */ |
2143 | struct omap_uwire_s { | |
a4ebbd18 | 2144 | MemoryRegion iomem; |
d951f6ff AZ |
2145 | qemu_irq txirq; |
2146 | qemu_irq rxirq; | |
2147 | qemu_irq txdrq; | |
2148 | ||
2149 | uint16_t txbuf; | |
2150 | uint16_t rxbuf; | |
2151 | uint16_t control; | |
2152 | uint16_t setup[5]; | |
2153 | ||
bc24a225 | 2154 | uWireSlave *chip[4]; |
d951f6ff AZ |
2155 | }; |
2156 | ||
2157 | static void omap_uwire_transfer_start(struct omap_uwire_s *s) | |
2158 | { | |
2159 | int chipselect = (s->control >> 10) & 3; /* INDEX */ | |
bc24a225 | 2160 | uWireSlave *slave = s->chip[chipselect]; |
d951f6ff AZ |
2161 | |
2162 | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ | |
2163 | if (s->control & (1 << 12)) /* CS_CMD */ | |
2164 | if (slave && slave->send) | |
2165 | slave->send(slave->opaque, | |
2166 | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); | |
2167 | s->control &= ~(1 << 14); /* CSRB */ | |
2168 | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or | |
2169 | * a DRQ. When is the level IRQ supposed to be reset? */ | |
2170 | } | |
2171 | ||
2172 | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ | |
2173 | if (s->control & (1 << 12)) /* CS_CMD */ | |
2174 | if (slave && slave->receive) | |
2175 | s->rxbuf = slave->receive(slave->opaque); | |
2176 | s->control |= 1 << 15; /* RDRB */ | |
2177 | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or | |
2178 | * a DRQ. When is the level IRQ supposed to be reset? */ | |
2179 | } | |
2180 | } | |
2181 | ||
a8170e5e | 2182 | static uint64_t omap_uwire_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2183 | unsigned size) |
d951f6ff AZ |
2184 | { |
2185 | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; | |
cf965d24 | 2186 | int offset = addr & OMAP_MPUI_REG_MASK; |
d951f6ff | 2187 | |
a4ebbd18 AK |
2188 | if (size != 2) { |
2189 | return omap_badwidth_read16(opaque, addr); | |
2190 | } | |
2191 | ||
d951f6ff AZ |
2192 | switch (offset) { |
2193 | case 0x00: /* RDR */ | |
2194 | s->control &= ~(1 << 15); /* RDRB */ | |
2195 | return s->rxbuf; | |
2196 | ||
2197 | case 0x04: /* CSR */ | |
2198 | return s->control; | |
2199 | ||
2200 | case 0x08: /* SR1 */ | |
2201 | return s->setup[0]; | |
2202 | case 0x0c: /* SR2 */ | |
2203 | return s->setup[1]; | |
2204 | case 0x10: /* SR3 */ | |
2205 | return s->setup[2]; | |
2206 | case 0x14: /* SR4 */ | |
2207 | return s->setup[3]; | |
2208 | case 0x18: /* SR5 */ | |
2209 | return s->setup[4]; | |
2210 | } | |
2211 | ||
2212 | OMAP_BAD_REG(addr); | |
2213 | return 0; | |
2214 | } | |
2215 | ||
a8170e5e | 2216 | static void omap_uwire_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2217 | uint64_t value, unsigned size) |
d951f6ff AZ |
2218 | { |
2219 | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; | |
cf965d24 | 2220 | int offset = addr & OMAP_MPUI_REG_MASK; |
d951f6ff | 2221 | |
a4ebbd18 | 2222 | if (size != 2) { |
77a8257e SW |
2223 | omap_badwidth_write16(opaque, addr, value); |
2224 | return; | |
a4ebbd18 AK |
2225 | } |
2226 | ||
d951f6ff AZ |
2227 | switch (offset) { |
2228 | case 0x00: /* TDR */ | |
2229 | s->txbuf = value; /* TD */ | |
d951f6ff AZ |
2230 | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
2231 | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ | |
cf965d24 AZ |
2232 | (s->control & (1 << 12)))) { /* CS_CMD */ |
2233 | s->control |= 1 << 14; /* CSRB */ | |
d951f6ff | 2234 | omap_uwire_transfer_start(s); |
cf965d24 | 2235 | } |
d951f6ff AZ |
2236 | break; |
2237 | ||
2238 | case 0x04: /* CSR */ | |
2239 | s->control = value & 0x1fff; | |
2240 | if (value & (1 << 13)) /* START */ | |
2241 | omap_uwire_transfer_start(s); | |
2242 | break; | |
2243 | ||
2244 | case 0x08: /* SR1 */ | |
2245 | s->setup[0] = value & 0x003f; | |
2246 | break; | |
2247 | ||
2248 | case 0x0c: /* SR2 */ | |
2249 | s->setup[1] = value & 0x0fc0; | |
2250 | break; | |
2251 | ||
2252 | case 0x10: /* SR3 */ | |
2253 | s->setup[2] = value & 0x0003; | |
2254 | break; | |
2255 | ||
2256 | case 0x14: /* SR4 */ | |
2257 | s->setup[3] = value & 0x0001; | |
2258 | break; | |
2259 | ||
2260 | case 0x18: /* SR5 */ | |
2261 | s->setup[4] = value & 0x000f; | |
2262 | break; | |
2263 | ||
2264 | default: | |
2265 | OMAP_BAD_REG(addr); | |
2266 | return; | |
2267 | } | |
2268 | } | |
2269 | ||
a4ebbd18 AK |
2270 | static const MemoryRegionOps omap_uwire_ops = { |
2271 | .read = omap_uwire_read, | |
2272 | .write = omap_uwire_write, | |
2273 | .endianness = DEVICE_NATIVE_ENDIAN, | |
d951f6ff AZ |
2274 | }; |
2275 | ||
9596ebb7 | 2276 | static void omap_uwire_reset(struct omap_uwire_s *s) |
d951f6ff | 2277 | { |
66450b15 | 2278 | s->control = 0; |
d951f6ff AZ |
2279 | s->setup[0] = 0; |
2280 | s->setup[1] = 0; | |
2281 | s->setup[2] = 0; | |
2282 | s->setup[3] = 0; | |
2283 | s->setup[4] = 0; | |
2284 | } | |
2285 | ||
0919ac78 | 2286 | static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, |
a8170e5e | 2287 | hwaddr base, |
0919ac78 PM |
2288 | qemu_irq txirq, qemu_irq rxirq, |
2289 | qemu_irq dma, | |
2290 | omap_clk clk) | |
d951f6ff | 2291 | { |
b45c03f5 | 2292 | struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); |
d951f6ff | 2293 | |
0919ac78 PM |
2294 | s->txirq = txirq; |
2295 | s->rxirq = rxirq; | |
d951f6ff AZ |
2296 | s->txdrq = dma; |
2297 | omap_uwire_reset(s); | |
2298 | ||
2c9b15ca | 2299 | memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); |
a4ebbd18 | 2300 | memory_region_add_subregion(system_memory, base, &s->iomem); |
d951f6ff AZ |
2301 | |
2302 | return s; | |
2303 | } | |
2304 | ||
2305 | void omap_uwire_attach(struct omap_uwire_s *s, | |
bc24a225 | 2306 | uWireSlave *slave, int chipselect) |
d951f6ff | 2307 | { |
827df9f3 AZ |
2308 | if (chipselect < 0 || chipselect > 3) { |
2309 | fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); | |
2310 | exit(-1); | |
2311 | } | |
d951f6ff AZ |
2312 | |
2313 | s->chip[chipselect] = slave; | |
2314 | } | |
2315 | ||
66450b15 | 2316 | /* Pseudonoise Pulse-Width Light Modulator */ |
8717d88a JR |
2317 | struct omap_pwl_s { |
2318 | MemoryRegion iomem; | |
2319 | uint8_t output; | |
2320 | uint8_t level; | |
2321 | uint8_t enable; | |
2322 | int clk; | |
2323 | }; | |
2324 | ||
2325 | static void omap_pwl_update(struct omap_pwl_s *s) | |
66450b15 | 2326 | { |
8717d88a | 2327 | int output = (s->clk && s->enable) ? s->level : 0; |
66450b15 | 2328 | |
8717d88a JR |
2329 | if (output != s->output) { |
2330 | s->output = output; | |
66450b15 AZ |
2331 | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); |
2332 | } | |
2333 | } | |
2334 | ||
a8170e5e | 2335 | static uint64_t omap_pwl_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2336 | unsigned size) |
66450b15 | 2337 | { |
8717d88a | 2338 | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
cf965d24 | 2339 | int offset = addr & OMAP_MPUI_REG_MASK; |
66450b15 | 2340 | |
a4ebbd18 AK |
2341 | if (size != 1) { |
2342 | return omap_badwidth_read8(opaque, addr); | |
2343 | } | |
2344 | ||
66450b15 AZ |
2345 | switch (offset) { |
2346 | case 0x00: /* PWL_LEVEL */ | |
8717d88a | 2347 | return s->level; |
66450b15 | 2348 | case 0x04: /* PWL_CTRL */ |
8717d88a | 2349 | return s->enable; |
66450b15 AZ |
2350 | } |
2351 | OMAP_BAD_REG(addr); | |
2352 | return 0; | |
2353 | } | |
2354 | ||
a8170e5e | 2355 | static void omap_pwl_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2356 | uint64_t value, unsigned size) |
66450b15 | 2357 | { |
8717d88a | 2358 | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
cf965d24 | 2359 | int offset = addr & OMAP_MPUI_REG_MASK; |
66450b15 | 2360 | |
a4ebbd18 | 2361 | if (size != 1) { |
77a8257e SW |
2362 | omap_badwidth_write8(opaque, addr, value); |
2363 | return; | |
a4ebbd18 AK |
2364 | } |
2365 | ||
66450b15 AZ |
2366 | switch (offset) { |
2367 | case 0x00: /* PWL_LEVEL */ | |
8717d88a | 2368 | s->level = value; |
66450b15 AZ |
2369 | omap_pwl_update(s); |
2370 | break; | |
2371 | case 0x04: /* PWL_CTRL */ | |
8717d88a | 2372 | s->enable = value & 1; |
66450b15 AZ |
2373 | omap_pwl_update(s); |
2374 | break; | |
2375 | default: | |
2376 | OMAP_BAD_REG(addr); | |
2377 | return; | |
2378 | } | |
2379 | } | |
2380 | ||
a4ebbd18 AK |
2381 | static const MemoryRegionOps omap_pwl_ops = { |
2382 | .read = omap_pwl_read, | |
2383 | .write = omap_pwl_write, | |
2384 | .endianness = DEVICE_NATIVE_ENDIAN, | |
66450b15 AZ |
2385 | }; |
2386 | ||
8717d88a | 2387 | static void omap_pwl_reset(struct omap_pwl_s *s) |
66450b15 | 2388 | { |
8717d88a JR |
2389 | s->output = 0; |
2390 | s->level = 0; | |
2391 | s->enable = 0; | |
2392 | s->clk = 1; | |
66450b15 AZ |
2393 | omap_pwl_update(s); |
2394 | } | |
2395 | ||
2396 | static void omap_pwl_clk_update(void *opaque, int line, int on) | |
2397 | { | |
8717d88a | 2398 | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
66450b15 | 2399 | |
8717d88a | 2400 | s->clk = on; |
66450b15 AZ |
2401 | omap_pwl_update(s); |
2402 | } | |
2403 | ||
8717d88a | 2404 | static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, |
a8170e5e | 2405 | hwaddr base, |
8717d88a | 2406 | omap_clk clk) |
66450b15 | 2407 | { |
8717d88a JR |
2408 | struct omap_pwl_s *s = g_malloc0(sizeof(*s)); |
2409 | ||
66450b15 AZ |
2410 | omap_pwl_reset(s); |
2411 | ||
2c9b15ca | 2412 | memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, |
a4ebbd18 | 2413 | "omap-pwl", 0x800); |
8717d88a | 2414 | memory_region_add_subregion(system_memory, base, &s->iomem); |
66450b15 | 2415 | |
f3c7d038 | 2416 | omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); |
8717d88a | 2417 | return s; |
66450b15 AZ |
2418 | } |
2419 | ||
f34c417b | 2420 | /* Pulse-Width Tone module */ |
03759534 JR |
2421 | struct omap_pwt_s { |
2422 | MemoryRegion iomem; | |
2423 | uint8_t frc; | |
2424 | uint8_t vrc; | |
2425 | uint8_t gcr; | |
2426 | omap_clk clk; | |
2427 | }; | |
2428 | ||
a8170e5e | 2429 | static uint64_t omap_pwt_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2430 | unsigned size) |
f34c417b | 2431 | { |
03759534 | 2432 | struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; |
cf965d24 | 2433 | int offset = addr & OMAP_MPUI_REG_MASK; |
f34c417b | 2434 | |
a4ebbd18 AK |
2435 | if (size != 1) { |
2436 | return omap_badwidth_read8(opaque, addr); | |
2437 | } | |
2438 | ||
f34c417b AZ |
2439 | switch (offset) { |
2440 | case 0x00: /* FRC */ | |
03759534 | 2441 | return s->frc; |
f34c417b | 2442 | case 0x04: /* VCR */ |
03759534 | 2443 | return s->vrc; |
f34c417b | 2444 | case 0x08: /* GCR */ |
03759534 | 2445 | return s->gcr; |
f34c417b AZ |
2446 | } |
2447 | OMAP_BAD_REG(addr); | |
2448 | return 0; | |
2449 | } | |
2450 | ||
a8170e5e | 2451 | static void omap_pwt_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2452 | uint64_t value, unsigned size) |
f34c417b | 2453 | { |
03759534 | 2454 | struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; |
cf965d24 | 2455 | int offset = addr & OMAP_MPUI_REG_MASK; |
f34c417b | 2456 | |
a4ebbd18 | 2457 | if (size != 1) { |
77a8257e SW |
2458 | omap_badwidth_write8(opaque, addr, value); |
2459 | return; | |
a4ebbd18 AK |
2460 | } |
2461 | ||
f34c417b AZ |
2462 | switch (offset) { |
2463 | case 0x00: /* FRC */ | |
03759534 | 2464 | s->frc = value & 0x3f; |
f34c417b AZ |
2465 | break; |
2466 | case 0x04: /* VRC */ | |
03759534 | 2467 | if ((value ^ s->vrc) & 1) { |
f34c417b AZ |
2468 | if (value & 1) |
2469 | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) | |
2470 | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ | |
03759534 | 2471 | ((omap_clk_getrate(s->clk) >> 3) / |
f34c417b | 2472 | /* Pre-multiplexer divider */ |
03759534 | 2473 | ((s->gcr & 2) ? 1 : 154) / |
f34c417b AZ |
2474 | /* Octave multiplexer */ |
2475 | (2 << (value & 3)) * | |
2476 | /* 101/107 divider */ | |
2477 | ((value & (1 << 2)) ? 101 : 107) * | |
2478 | /* 49/55 divider */ | |
2479 | ((value & (1 << 3)) ? 49 : 55) * | |
2480 | /* 50/63 divider */ | |
2481 | ((value & (1 << 4)) ? 50 : 63) * | |
2482 | /* 80/127 divider */ | |
2483 | ((value & (1 << 5)) ? 80 : 127) / | |
2484 | (107 * 55 * 63 * 127))); | |
2485 | else | |
2486 | printf("%s: silence!\n", __FUNCTION__); | |
2487 | } | |
03759534 | 2488 | s->vrc = value & 0x7f; |
f34c417b AZ |
2489 | break; |
2490 | case 0x08: /* GCR */ | |
03759534 | 2491 | s->gcr = value & 3; |
f34c417b AZ |
2492 | break; |
2493 | default: | |
2494 | OMAP_BAD_REG(addr); | |
2495 | return; | |
2496 | } | |
2497 | } | |
2498 | ||
a4ebbd18 AK |
2499 | static const MemoryRegionOps omap_pwt_ops = { |
2500 | .read =omap_pwt_read, | |
2501 | .write = omap_pwt_write, | |
2502 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f34c417b AZ |
2503 | }; |
2504 | ||
03759534 | 2505 | static void omap_pwt_reset(struct omap_pwt_s *s) |
f34c417b | 2506 | { |
03759534 JR |
2507 | s->frc = 0; |
2508 | s->vrc = 0; | |
2509 | s->gcr = 0; | |
f34c417b AZ |
2510 | } |
2511 | ||
03759534 | 2512 | static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, |
a8170e5e | 2513 | hwaddr base, |
03759534 | 2514 | omap_clk clk) |
f34c417b | 2515 | { |
03759534 JR |
2516 | struct omap_pwt_s *s = g_malloc0(sizeof(*s)); |
2517 | s->clk = clk; | |
f34c417b AZ |
2518 | omap_pwt_reset(s); |
2519 | ||
2c9b15ca | 2520 | memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, |
a4ebbd18 | 2521 | "omap-pwt", 0x800); |
03759534 JR |
2522 | memory_region_add_subregion(system_memory, base, &s->iomem); |
2523 | return s; | |
f34c417b AZ |
2524 | } |
2525 | ||
5c1c390f AZ |
2526 | /* Real-time Clock module */ |
2527 | struct omap_rtc_s { | |
a4ebbd18 | 2528 | MemoryRegion iomem; |
5c1c390f AZ |
2529 | qemu_irq irq; |
2530 | qemu_irq alarm; | |
2531 | QEMUTimer *clk; | |
2532 | ||
2533 | uint8_t interrupts; | |
2534 | uint8_t status; | |
2535 | int16_t comp_reg; | |
2536 | int running; | |
2537 | int pm_am; | |
2538 | int auto_comp; | |
2539 | int round; | |
5c1c390f AZ |
2540 | struct tm alarm_tm; |
2541 | time_t alarm_ti; | |
2542 | ||
2543 | struct tm current_tm; | |
2544 | time_t ti; | |
2545 | uint64_t tick; | |
2546 | }; | |
2547 | ||
2548 | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) | |
2549 | { | |
106627d0 | 2550 | /* s->alarm is level-triggered */ |
5c1c390f AZ |
2551 | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
2552 | } | |
2553 | ||
2554 | static void omap_rtc_alarm_update(struct omap_rtc_s *s) | |
2555 | { | |
0cd2df75 | 2556 | s->alarm_ti = mktimegm(&s->alarm_tm); |
5c1c390f AZ |
2557 | if (s->alarm_ti == -1) |
2558 | printf("%s: conversion failed\n", __FUNCTION__); | |
2559 | } | |
2560 | ||
a8170e5e | 2561 | static uint64_t omap_rtc_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2562 | unsigned size) |
5c1c390f AZ |
2563 | { |
2564 | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; | |
cf965d24 | 2565 | int offset = addr & OMAP_MPUI_REG_MASK; |
5c1c390f AZ |
2566 | uint8_t i; |
2567 | ||
a4ebbd18 AK |
2568 | if (size != 1) { |
2569 | return omap_badwidth_read8(opaque, addr); | |
2570 | } | |
2571 | ||
5c1c390f AZ |
2572 | switch (offset) { |
2573 | case 0x00: /* SECONDS_REG */ | |
abd0c6bd | 2574 | return to_bcd(s->current_tm.tm_sec); |
5c1c390f AZ |
2575 | |
2576 | case 0x04: /* MINUTES_REG */ | |
abd0c6bd | 2577 | return to_bcd(s->current_tm.tm_min); |
5c1c390f AZ |
2578 | |
2579 | case 0x08: /* HOURS_REG */ | |
2580 | if (s->pm_am) | |
2581 | return ((s->current_tm.tm_hour > 11) << 7) | | |
abd0c6bd | 2582 | to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
5c1c390f | 2583 | else |
abd0c6bd | 2584 | return to_bcd(s->current_tm.tm_hour); |
5c1c390f AZ |
2585 | |
2586 | case 0x0c: /* DAYS_REG */ | |
abd0c6bd | 2587 | return to_bcd(s->current_tm.tm_mday); |
5c1c390f AZ |
2588 | |
2589 | case 0x10: /* MONTHS_REG */ | |
abd0c6bd | 2590 | return to_bcd(s->current_tm.tm_mon + 1); |
5c1c390f AZ |
2591 | |
2592 | case 0x14: /* YEARS_REG */ | |
abd0c6bd | 2593 | return to_bcd(s->current_tm.tm_year % 100); |
5c1c390f AZ |
2594 | |
2595 | case 0x18: /* WEEK_REG */ | |
2596 | return s->current_tm.tm_wday; | |
2597 | ||
2598 | case 0x20: /* ALARM_SECONDS_REG */ | |
abd0c6bd | 2599 | return to_bcd(s->alarm_tm.tm_sec); |
5c1c390f AZ |
2600 | |
2601 | case 0x24: /* ALARM_MINUTES_REG */ | |
abd0c6bd | 2602 | return to_bcd(s->alarm_tm.tm_min); |
5c1c390f AZ |
2603 | |
2604 | case 0x28: /* ALARM_HOURS_REG */ | |
2605 | if (s->pm_am) | |
2606 | return ((s->alarm_tm.tm_hour > 11) << 7) | | |
abd0c6bd | 2607 | to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
5c1c390f | 2608 | else |
abd0c6bd | 2609 | return to_bcd(s->alarm_tm.tm_hour); |
5c1c390f AZ |
2610 | |
2611 | case 0x2c: /* ALARM_DAYS_REG */ | |
abd0c6bd | 2612 | return to_bcd(s->alarm_tm.tm_mday); |
5c1c390f AZ |
2613 | |
2614 | case 0x30: /* ALARM_MONTHS_REG */ | |
abd0c6bd | 2615 | return to_bcd(s->alarm_tm.tm_mon + 1); |
5c1c390f AZ |
2616 | |
2617 | case 0x34: /* ALARM_YEARS_REG */ | |
abd0c6bd | 2618 | return to_bcd(s->alarm_tm.tm_year % 100); |
5c1c390f AZ |
2619 | |
2620 | case 0x40: /* RTC_CTRL_REG */ | |
2621 | return (s->pm_am << 3) | (s->auto_comp << 2) | | |
2622 | (s->round << 1) | s->running; | |
2623 | ||
2624 | case 0x44: /* RTC_STATUS_REG */ | |
2625 | i = s->status; | |
2626 | s->status &= ~0x3d; | |
2627 | return i; | |
2628 | ||
2629 | case 0x48: /* RTC_INTERRUPTS_REG */ | |
2630 | return s->interrupts; | |
2631 | ||
2632 | case 0x4c: /* RTC_COMP_LSB_REG */ | |
2633 | return ((uint16_t) s->comp_reg) & 0xff; | |
2634 | ||
2635 | case 0x50: /* RTC_COMP_MSB_REG */ | |
2636 | return ((uint16_t) s->comp_reg) >> 8; | |
2637 | } | |
2638 | ||
2639 | OMAP_BAD_REG(addr); | |
2640 | return 0; | |
2641 | } | |
2642 | ||
a8170e5e | 2643 | static void omap_rtc_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2644 | uint64_t value, unsigned size) |
5c1c390f AZ |
2645 | { |
2646 | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; | |
cf965d24 | 2647 | int offset = addr & OMAP_MPUI_REG_MASK; |
5c1c390f AZ |
2648 | struct tm new_tm; |
2649 | time_t ti[2]; | |
2650 | ||
a4ebbd18 | 2651 | if (size != 1) { |
77a8257e SW |
2652 | omap_badwidth_write8(opaque, addr, value); |
2653 | return; | |
a4ebbd18 AK |
2654 | } |
2655 | ||
5c1c390f AZ |
2656 | switch (offset) { |
2657 | case 0x00: /* SECONDS_REG */ | |
eb38c52c | 2658 | #ifdef ALMDEBUG |
5c1c390f AZ |
2659 | printf("RTC SEC_REG <-- %02x\n", value); |
2660 | #endif | |
2661 | s->ti -= s->current_tm.tm_sec; | |
abd0c6bd | 2662 | s->ti += from_bcd(value); |
5c1c390f AZ |
2663 | return; |
2664 | ||
2665 | case 0x04: /* MINUTES_REG */ | |
eb38c52c | 2666 | #ifdef ALMDEBUG |
5c1c390f AZ |
2667 | printf("RTC MIN_REG <-- %02x\n", value); |
2668 | #endif | |
2669 | s->ti -= s->current_tm.tm_min * 60; | |
abd0c6bd | 2670 | s->ti += from_bcd(value) * 60; |
5c1c390f AZ |
2671 | return; |
2672 | ||
2673 | case 0x08: /* HOURS_REG */ | |
eb38c52c | 2674 | #ifdef ALMDEBUG |
5c1c390f AZ |
2675 | printf("RTC HRS_REG <-- %02x\n", value); |
2676 | #endif | |
2677 | s->ti -= s->current_tm.tm_hour * 3600; | |
2678 | if (s->pm_am) { | |
abd0c6bd | 2679 | s->ti += (from_bcd(value & 0x3f) & 12) * 3600; |
5c1c390f AZ |
2680 | s->ti += ((value >> 7) & 1) * 43200; |
2681 | } else | |
abd0c6bd | 2682 | s->ti += from_bcd(value & 0x3f) * 3600; |
5c1c390f AZ |
2683 | return; |
2684 | ||
2685 | case 0x0c: /* DAYS_REG */ | |
eb38c52c | 2686 | #ifdef ALMDEBUG |
5c1c390f AZ |
2687 | printf("RTC DAY_REG <-- %02x\n", value); |
2688 | #endif | |
2689 | s->ti -= s->current_tm.tm_mday * 86400; | |
abd0c6bd | 2690 | s->ti += from_bcd(value) * 86400; |
5c1c390f AZ |
2691 | return; |
2692 | ||
2693 | case 0x10: /* MONTHS_REG */ | |
eb38c52c | 2694 | #ifdef ALMDEBUG |
5c1c390f AZ |
2695 | printf("RTC MTH_REG <-- %02x\n", value); |
2696 | #endif | |
2697 | memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); | |
abd0c6bd | 2698 | new_tm.tm_mon = from_bcd(value); |
0cd2df75 AJ |
2699 | ti[0] = mktimegm(&s->current_tm); |
2700 | ti[1] = mktimegm(&new_tm); | |
5c1c390f AZ |
2701 | |
2702 | if (ti[0] != -1 && ti[1] != -1) { | |
2703 | s->ti -= ti[0]; | |
2704 | s->ti += ti[1]; | |
2705 | } else { | |
2706 | /* A less accurate version */ | |
2707 | s->ti -= s->current_tm.tm_mon * 2592000; | |
abd0c6bd | 2708 | s->ti += from_bcd(value) * 2592000; |
5c1c390f AZ |
2709 | } |
2710 | return; | |
2711 | ||
2712 | case 0x14: /* YEARS_REG */ | |
eb38c52c | 2713 | #ifdef ALMDEBUG |
5c1c390f AZ |
2714 | printf("RTC YRS_REG <-- %02x\n", value); |
2715 | #endif | |
2716 | memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); | |
abd0c6bd | 2717 | new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); |
0cd2df75 AJ |
2718 | ti[0] = mktimegm(&s->current_tm); |
2719 | ti[1] = mktimegm(&new_tm); | |
5c1c390f AZ |
2720 | |
2721 | if (ti[0] != -1 && ti[1] != -1) { | |
2722 | s->ti -= ti[0]; | |
2723 | s->ti += ti[1]; | |
2724 | } else { | |
2725 | /* A less accurate version */ | |
7e7e5858 PM |
2726 | s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; |
2727 | s->ti += (time_t)from_bcd(value) * 31536000; | |
5c1c390f AZ |
2728 | } |
2729 | return; | |
2730 | ||
2731 | case 0x18: /* WEEK_REG */ | |
2732 | return; /* Ignored */ | |
2733 | ||
2734 | case 0x20: /* ALARM_SECONDS_REG */ | |
eb38c52c | 2735 | #ifdef ALMDEBUG |
5c1c390f AZ |
2736 | printf("ALM SEC_REG <-- %02x\n", value); |
2737 | #endif | |
abd0c6bd | 2738 | s->alarm_tm.tm_sec = from_bcd(value); |
5c1c390f AZ |
2739 | omap_rtc_alarm_update(s); |
2740 | return; | |
2741 | ||
2742 | case 0x24: /* ALARM_MINUTES_REG */ | |
eb38c52c | 2743 | #ifdef ALMDEBUG |
5c1c390f AZ |
2744 | printf("ALM MIN_REG <-- %02x\n", value); |
2745 | #endif | |
abd0c6bd | 2746 | s->alarm_tm.tm_min = from_bcd(value); |
5c1c390f AZ |
2747 | omap_rtc_alarm_update(s); |
2748 | return; | |
2749 | ||
2750 | case 0x28: /* ALARM_HOURS_REG */ | |
eb38c52c | 2751 | #ifdef ALMDEBUG |
5c1c390f AZ |
2752 | printf("ALM HRS_REG <-- %02x\n", value); |
2753 | #endif | |
2754 | if (s->pm_am) | |
2755 | s->alarm_tm.tm_hour = | |
abd0c6bd | 2756 | ((from_bcd(value & 0x3f)) % 12) + |
5c1c390f AZ |
2757 | ((value >> 7) & 1) * 12; |
2758 | else | |
abd0c6bd | 2759 | s->alarm_tm.tm_hour = from_bcd(value); |
5c1c390f AZ |
2760 | omap_rtc_alarm_update(s); |
2761 | return; | |
2762 | ||
2763 | case 0x2c: /* ALARM_DAYS_REG */ | |
eb38c52c | 2764 | #ifdef ALMDEBUG |
5c1c390f AZ |
2765 | printf("ALM DAY_REG <-- %02x\n", value); |
2766 | #endif | |
abd0c6bd | 2767 | s->alarm_tm.tm_mday = from_bcd(value); |
5c1c390f AZ |
2768 | omap_rtc_alarm_update(s); |
2769 | return; | |
2770 | ||
2771 | case 0x30: /* ALARM_MONTHS_REG */ | |
eb38c52c | 2772 | #ifdef ALMDEBUG |
5c1c390f AZ |
2773 | printf("ALM MON_REG <-- %02x\n", value); |
2774 | #endif | |
abd0c6bd | 2775 | s->alarm_tm.tm_mon = from_bcd(value); |
5c1c390f AZ |
2776 | omap_rtc_alarm_update(s); |
2777 | return; | |
2778 | ||
2779 | case 0x34: /* ALARM_YEARS_REG */ | |
eb38c52c | 2780 | #ifdef ALMDEBUG |
5c1c390f AZ |
2781 | printf("ALM YRS_REG <-- %02x\n", value); |
2782 | #endif | |
abd0c6bd | 2783 | s->alarm_tm.tm_year = from_bcd(value); |
5c1c390f AZ |
2784 | omap_rtc_alarm_update(s); |
2785 | return; | |
2786 | ||
2787 | case 0x40: /* RTC_CTRL_REG */ | |
eb38c52c | 2788 | #ifdef ALMDEBUG |
5c1c390f AZ |
2789 | printf("RTC CONTROL <-- %02x\n", value); |
2790 | #endif | |
2791 | s->pm_am = (value >> 3) & 1; | |
2792 | s->auto_comp = (value >> 2) & 1; | |
2793 | s->round = (value >> 1) & 1; | |
2794 | s->running = value & 1; | |
2795 | s->status &= 0xfd; | |
2796 | s->status |= s->running << 1; | |
2797 | return; | |
2798 | ||
2799 | case 0x44: /* RTC_STATUS_REG */ | |
eb38c52c | 2800 | #ifdef ALMDEBUG |
5c1c390f AZ |
2801 | printf("RTC STATUSL <-- %02x\n", value); |
2802 | #endif | |
2803 | s->status &= ~((value & 0xc0) ^ 0x80); | |
2804 | omap_rtc_interrupts_update(s); | |
2805 | return; | |
2806 | ||
2807 | case 0x48: /* RTC_INTERRUPTS_REG */ | |
eb38c52c | 2808 | #ifdef ALMDEBUG |
5c1c390f AZ |
2809 | printf("RTC INTRS <-- %02x\n", value); |
2810 | #endif | |
2811 | s->interrupts = value; | |
2812 | return; | |
2813 | ||
2814 | case 0x4c: /* RTC_COMP_LSB_REG */ | |
eb38c52c | 2815 | #ifdef ALMDEBUG |
5c1c390f AZ |
2816 | printf("RTC COMPLSB <-- %02x\n", value); |
2817 | #endif | |
2818 | s->comp_reg &= 0xff00; | |
2819 | s->comp_reg |= 0x00ff & value; | |
2820 | return; | |
2821 | ||
2822 | case 0x50: /* RTC_COMP_MSB_REG */ | |
eb38c52c | 2823 | #ifdef ALMDEBUG |
5c1c390f AZ |
2824 | printf("RTC COMPMSB <-- %02x\n", value); |
2825 | #endif | |
2826 | s->comp_reg &= 0x00ff; | |
2827 | s->comp_reg |= 0xff00 & (value << 8); | |
2828 | return; | |
2829 | ||
2830 | default: | |
2831 | OMAP_BAD_REG(addr); | |
2832 | return; | |
2833 | } | |
2834 | } | |
2835 | ||
a4ebbd18 AK |
2836 | static const MemoryRegionOps omap_rtc_ops = { |
2837 | .read = omap_rtc_read, | |
2838 | .write = omap_rtc_write, | |
2839 | .endianness = DEVICE_NATIVE_ENDIAN, | |
5c1c390f AZ |
2840 | }; |
2841 | ||
2842 | static void omap_rtc_tick(void *opaque) | |
2843 | { | |
2844 | struct omap_rtc_s *s = opaque; | |
2845 | ||
2846 | if (s->round) { | |
2847 | /* Round to nearest full minute. */ | |
2848 | if (s->current_tm.tm_sec < 30) | |
2849 | s->ti -= s->current_tm.tm_sec; | |
2850 | else | |
2851 | s->ti += 60 - s->current_tm.tm_sec; | |
2852 | ||
2853 | s->round = 0; | |
2854 | } | |
2855 | ||
eb7ff6fb | 2856 | localtime_r(&s->ti, &s->current_tm); |
5c1c390f AZ |
2857 | |
2858 | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { | |
2859 | s->status |= 0x40; | |
2860 | omap_rtc_interrupts_update(s); | |
2861 | } | |
2862 | ||
2863 | if (s->interrupts & 0x04) | |
2864 | switch (s->interrupts & 3) { | |
2865 | case 0: | |
2866 | s->status |= 0x04; | |
106627d0 | 2867 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2868 | break; |
2869 | case 1: | |
2870 | if (s->current_tm.tm_sec) | |
2871 | break; | |
2872 | s->status |= 0x08; | |
106627d0 | 2873 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2874 | break; |
2875 | case 2: | |
2876 | if (s->current_tm.tm_sec || s->current_tm.tm_min) | |
2877 | break; | |
2878 | s->status |= 0x10; | |
106627d0 | 2879 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2880 | break; |
2881 | case 3: | |
2882 | if (s->current_tm.tm_sec || | |
2883 | s->current_tm.tm_min || s->current_tm.tm_hour) | |
2884 | break; | |
2885 | s->status |= 0x20; | |
106627d0 | 2886 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2887 | break; |
2888 | } | |
2889 | ||
2890 | /* Move on */ | |
2891 | if (s->running) | |
2892 | s->ti ++; | |
2893 | s->tick += 1000; | |
2894 | ||
2895 | /* | |
2896 | * Every full hour add a rough approximation of the compensation | |
2897 | * register to the 32kHz Timer (which drives the RTC) value. | |
2898 | */ | |
2899 | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) | |
2900 | s->tick += s->comp_reg * 1000 / 32768; | |
2901 | ||
bc72ad67 | 2902 | timer_mod(s->clk, s->tick); |
5c1c390f AZ |
2903 | } |
2904 | ||
9596ebb7 | 2905 | static void omap_rtc_reset(struct omap_rtc_s *s) |
5c1c390f | 2906 | { |
f6503059 AZ |
2907 | struct tm tm; |
2908 | ||
5c1c390f AZ |
2909 | s->interrupts = 0; |
2910 | s->comp_reg = 0; | |
2911 | s->running = 0; | |
2912 | s->pm_am = 0; | |
2913 | s->auto_comp = 0; | |
2914 | s->round = 0; | |
884f17c2 | 2915 | s->tick = qemu_clock_get_ms(rtc_clock); |
5c1c390f AZ |
2916 | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
2917 | s->alarm_tm.tm_mday = 0x01; | |
2918 | s->status = 1 << 7; | |
f6503059 | 2919 | qemu_get_timedate(&tm, 0); |
0cd2df75 | 2920 | s->ti = mktimegm(&tm); |
5c1c390f AZ |
2921 | |
2922 | omap_rtc_alarm_update(s); | |
2923 | omap_rtc_tick(s); | |
2924 | } | |
2925 | ||
a4ebbd18 | 2926 | static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, |
a8170e5e | 2927 | hwaddr base, |
0919ac78 PM |
2928 | qemu_irq timerirq, qemu_irq alarmirq, |
2929 | omap_clk clk) | |
5c1c390f | 2930 | { |
b45c03f5 | 2931 | struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); |
5c1c390f | 2932 | |
0919ac78 PM |
2933 | s->irq = timerirq; |
2934 | s->alarm = alarmirq; | |
884f17c2 | 2935 | s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); |
5c1c390f AZ |
2936 | |
2937 | omap_rtc_reset(s); | |
2938 | ||
2c9b15ca | 2939 | memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, |
a4ebbd18 AK |
2940 | "omap-rtc", 0x800); |
2941 | memory_region_add_subregion(system_memory, base, &s->iomem); | |
5c1c390f AZ |
2942 | |
2943 | return s; | |
2944 | } | |
2945 | ||
d8f699cb AZ |
2946 | /* Multi-channel Buffered Serial Port interfaces */ |
2947 | struct omap_mcbsp_s { | |
a4ebbd18 | 2948 | MemoryRegion iomem; |
d8f699cb AZ |
2949 | qemu_irq txirq; |
2950 | qemu_irq rxirq; | |
2951 | qemu_irq txdrq; | |
2952 | qemu_irq rxdrq; | |
2953 | ||
2954 | uint16_t spcr[2]; | |
2955 | uint16_t rcr[2]; | |
2956 | uint16_t xcr[2]; | |
2957 | uint16_t srgr[2]; | |
2958 | uint16_t mcr[2]; | |
2959 | uint16_t pcr; | |
2960 | uint16_t rcer[8]; | |
2961 | uint16_t xcer[8]; | |
2962 | int tx_rate; | |
2963 | int rx_rate; | |
2964 | int tx_req; | |
73560bc8 | 2965 | int rx_req; |
d8f699cb | 2966 | |
bc24a225 | 2967 | I2SCodec *codec; |
73560bc8 AZ |
2968 | QEMUTimer *source_timer; |
2969 | QEMUTimer *sink_timer; | |
d8f699cb AZ |
2970 | }; |
2971 | ||
2972 | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) | |
2973 | { | |
2974 | int irq; | |
2975 | ||
2976 | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ | |
2977 | case 0: | |
2978 | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ | |
2979 | break; | |
2980 | case 3: | |
2981 | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ | |
2982 | break; | |
2983 | default: | |
2984 | irq = 0; | |
2985 | break; | |
2986 | } | |
2987 | ||
106627d0 AZ |
2988 | if (irq) |
2989 | qemu_irq_pulse(s->rxirq); | |
d8f699cb AZ |
2990 | |
2991 | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ | |
2992 | case 0: | |
2993 | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ | |
2994 | break; | |
2995 | case 3: | |
2996 | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ | |
2997 | break; | |
2998 | default: | |
2999 | irq = 0; | |
3000 | break; | |
3001 | } | |
3002 | ||
106627d0 AZ |
3003 | if (irq) |
3004 | qemu_irq_pulse(s->txirq); | |
d8f699cb AZ |
3005 | } |
3006 | ||
73560bc8 | 3007 | static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
d8f699cb | 3008 | { |
73560bc8 AZ |
3009 | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
3010 | s->spcr[0] |= 1 << 2; /* RFULL */ | |
3011 | s->spcr[0] |= 1 << 1; /* RRDY */ | |
3012 | qemu_irq_raise(s->rxdrq); | |
3013 | omap_mcbsp_intr_update(s); | |
d8f699cb AZ |
3014 | } |
3015 | ||
73560bc8 | 3016 | static void omap_mcbsp_source_tick(void *opaque) |
d8f699cb | 3017 | { |
73560bc8 AZ |
3018 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3019 | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; | |
3020 | ||
3021 | if (!s->rx_rate) | |
d8f699cb | 3022 | return; |
73560bc8 AZ |
3023 | if (s->rx_req) |
3024 | printf("%s: Rx FIFO overrun\n", __FUNCTION__); | |
d8f699cb | 3025 | |
73560bc8 | 3026 | s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
d8f699cb | 3027 | |
73560bc8 | 3028 | omap_mcbsp_rx_newdata(s); |
bc72ad67 | 3029 | timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
6ee093c9 | 3030 | get_ticks_per_sec()); |
d8f699cb AZ |
3031 | } |
3032 | ||
3033 | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) | |
3034 | { | |
73560bc8 AZ |
3035 | if (!s->codec || !s->codec->rts) |
3036 | omap_mcbsp_source_tick(s); | |
3037 | else if (s->codec->in.len) { | |
3038 | s->rx_req = s->codec->in.len; | |
3039 | omap_mcbsp_rx_newdata(s); | |
d8f699cb | 3040 | } |
d8f699cb AZ |
3041 | } |
3042 | ||
3043 | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) | |
73560bc8 | 3044 | { |
bc72ad67 | 3045 | timer_del(s->source_timer); |
73560bc8 AZ |
3046 | } |
3047 | ||
3048 | static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) | |
d8f699cb AZ |
3049 | { |
3050 | s->spcr[0] &= ~(1 << 1); /* RRDY */ | |
3051 | qemu_irq_lower(s->rxdrq); | |
3052 | omap_mcbsp_intr_update(s); | |
3053 | } | |
3054 | ||
73560bc8 AZ |
3055 | static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
3056 | { | |
3057 | s->spcr[1] |= 1 << 1; /* XRDY */ | |
3058 | qemu_irq_raise(s->txdrq); | |
3059 | omap_mcbsp_intr_update(s); | |
3060 | } | |
3061 | ||
3062 | static void omap_mcbsp_sink_tick(void *opaque) | |
d8f699cb | 3063 | { |
73560bc8 AZ |
3064 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3065 | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; | |
3066 | ||
3067 | if (!s->tx_rate) | |
d8f699cb | 3068 | return; |
73560bc8 AZ |
3069 | if (s->tx_req) |
3070 | printf("%s: Tx FIFO underrun\n", __FUNCTION__); | |
3071 | ||
3072 | s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; | |
3073 | ||
3074 | omap_mcbsp_tx_newdata(s); | |
bc72ad67 | 3075 | timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
6ee093c9 | 3076 | get_ticks_per_sec()); |
73560bc8 AZ |
3077 | } |
3078 | ||
3079 | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) | |
3080 | { | |
3081 | if (!s->codec || !s->codec->cts) | |
3082 | omap_mcbsp_sink_tick(s); | |
3083 | else if (s->codec->out.size) { | |
3084 | s->tx_req = s->codec->out.size; | |
3085 | omap_mcbsp_tx_newdata(s); | |
3086 | } | |
3087 | } | |
3088 | ||
3089 | static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) | |
3090 | { | |
3091 | s->spcr[1] &= ~(1 << 1); /* XRDY */ | |
3092 | qemu_irq_lower(s->txdrq); | |
3093 | omap_mcbsp_intr_update(s); | |
3094 | if (s->codec && s->codec->cts) | |
3095 | s->codec->tx_swallow(s->codec->opaque); | |
d8f699cb AZ |
3096 | } |
3097 | ||
3098 | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) | |
3099 | { | |
73560bc8 AZ |
3100 | s->tx_req = 0; |
3101 | omap_mcbsp_tx_done(s); | |
bc72ad67 | 3102 | timer_del(s->sink_timer); |
73560bc8 AZ |
3103 | } |
3104 | ||
3105 | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) | |
3106 | { | |
3107 | int prev_rx_rate, prev_tx_rate; | |
3108 | int rx_rate = 0, tx_rate = 0; | |
3109 | int cpu_rate = 1500000; /* XXX */ | |
3110 | ||
3111 | /* TODO: check CLKSTP bit */ | |
3112 | if (s->spcr[1] & (1 << 6)) { /* GRST */ | |
3113 | if (s->spcr[0] & (1 << 0)) { /* RRST */ | |
3114 | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ | |
3115 | (s->pcr & (1 << 8))) { /* CLKRM */ | |
3116 | if (~s->pcr & (1 << 7)) /* SCLKME */ | |
3117 | rx_rate = cpu_rate / | |
3118 | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ | |
3119 | } else | |
3120 | if (s->codec) | |
3121 | rx_rate = s->codec->rx_rate; | |
3122 | } | |
3123 | ||
3124 | if (s->spcr[1] & (1 << 0)) { /* XRST */ | |
3125 | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ | |
3126 | (s->pcr & (1 << 9))) { /* CLKXM */ | |
3127 | if (~s->pcr & (1 << 7)) /* SCLKME */ | |
3128 | tx_rate = cpu_rate / | |
3129 | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ | |
3130 | } else | |
3131 | if (s->codec) | |
3132 | tx_rate = s->codec->tx_rate; | |
3133 | } | |
3134 | } | |
3135 | prev_tx_rate = s->tx_rate; | |
3136 | prev_rx_rate = s->rx_rate; | |
3137 | s->tx_rate = tx_rate; | |
3138 | s->rx_rate = rx_rate; | |
3139 | ||
3140 | if (s->codec) | |
3141 | s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); | |
3142 | ||
3143 | if (!prev_tx_rate && tx_rate) | |
3144 | omap_mcbsp_tx_start(s); | |
3145 | else if (s->tx_rate && !tx_rate) | |
3146 | omap_mcbsp_tx_stop(s); | |
3147 | ||
3148 | if (!prev_rx_rate && rx_rate) | |
3149 | omap_mcbsp_rx_start(s); | |
3150 | else if (prev_tx_rate && !tx_rate) | |
3151 | omap_mcbsp_rx_stop(s); | |
d8f699cb AZ |
3152 | } |
3153 | ||
a8170e5e | 3154 | static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, |
a4ebbd18 | 3155 | unsigned size) |
d8f699cb AZ |
3156 | { |
3157 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3158 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3159 | uint16_t ret; | |
3160 | ||
a4ebbd18 AK |
3161 | if (size != 2) { |
3162 | return omap_badwidth_read16(opaque, addr); | |
3163 | } | |
3164 | ||
d8f699cb AZ |
3165 | switch (offset) { |
3166 | case 0x00: /* DRR2 */ | |
3167 | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ | |
3168 | return 0x0000; | |
3169 | /* Fall through. */ | |
3170 | case 0x02: /* DRR1 */ | |
73560bc8 | 3171 | if (s->rx_req < 2) { |
d8f699cb | 3172 | printf("%s: Rx FIFO underrun\n", __FUNCTION__); |
73560bc8 | 3173 | omap_mcbsp_rx_done(s); |
d8f699cb | 3174 | } else { |
73560bc8 AZ |
3175 | s->tx_req -= 2; |
3176 | if (s->codec && s->codec->in.len >= 2) { | |
3177 | ret = s->codec->in.fifo[s->codec->in.start ++] << 8; | |
3178 | ret |= s->codec->in.fifo[s->codec->in.start ++]; | |
3179 | s->codec->in.len -= 2; | |
3180 | } else | |
3181 | ret = 0x0000; | |
3182 | if (!s->tx_req) | |
3183 | omap_mcbsp_rx_done(s); | |
d8f699cb AZ |
3184 | return ret; |
3185 | } | |
3186 | return 0x0000; | |
3187 | ||
3188 | case 0x04: /* DXR2 */ | |
3189 | case 0x06: /* DXR1 */ | |
3190 | return 0x0000; | |
3191 | ||
3192 | case 0x08: /* SPCR2 */ | |
3193 | return s->spcr[1]; | |
3194 | case 0x0a: /* SPCR1 */ | |
3195 | return s->spcr[0]; | |
3196 | case 0x0c: /* RCR2 */ | |
3197 | return s->rcr[1]; | |
3198 | case 0x0e: /* RCR1 */ | |
3199 | return s->rcr[0]; | |
3200 | case 0x10: /* XCR2 */ | |
3201 | return s->xcr[1]; | |
3202 | case 0x12: /* XCR1 */ | |
3203 | return s->xcr[0]; | |
3204 | case 0x14: /* SRGR2 */ | |
3205 | return s->srgr[1]; | |
3206 | case 0x16: /* SRGR1 */ | |
3207 | return s->srgr[0]; | |
3208 | case 0x18: /* MCR2 */ | |
3209 | return s->mcr[1]; | |
3210 | case 0x1a: /* MCR1 */ | |
3211 | return s->mcr[0]; | |
3212 | case 0x1c: /* RCERA */ | |
3213 | return s->rcer[0]; | |
3214 | case 0x1e: /* RCERB */ | |
3215 | return s->rcer[1]; | |
3216 | case 0x20: /* XCERA */ | |
3217 | return s->xcer[0]; | |
3218 | case 0x22: /* XCERB */ | |
3219 | return s->xcer[1]; | |
3220 | case 0x24: /* PCR0 */ | |
3221 | return s->pcr; | |
3222 | case 0x26: /* RCERC */ | |
3223 | return s->rcer[2]; | |
3224 | case 0x28: /* RCERD */ | |
3225 | return s->rcer[3]; | |
3226 | case 0x2a: /* XCERC */ | |
3227 | return s->xcer[2]; | |
3228 | case 0x2c: /* XCERD */ | |
3229 | return s->xcer[3]; | |
3230 | case 0x2e: /* RCERE */ | |
3231 | return s->rcer[4]; | |
3232 | case 0x30: /* RCERF */ | |
3233 | return s->rcer[5]; | |
3234 | case 0x32: /* XCERE */ | |
3235 | return s->xcer[4]; | |
3236 | case 0x34: /* XCERF */ | |
3237 | return s->xcer[5]; | |
3238 | case 0x36: /* RCERG */ | |
3239 | return s->rcer[6]; | |
3240 | case 0x38: /* RCERH */ | |
3241 | return s->rcer[7]; | |
3242 | case 0x3a: /* XCERG */ | |
3243 | return s->xcer[6]; | |
3244 | case 0x3c: /* XCERH */ | |
3245 | return s->xcer[7]; | |
3246 | } | |
3247 | ||
3248 | OMAP_BAD_REG(addr); | |
3249 | return 0; | |
3250 | } | |
3251 | ||
a8170e5e | 3252 | static void omap_mcbsp_writeh(void *opaque, hwaddr addr, |
d8f699cb AZ |
3253 | uint32_t value) |
3254 | { | |
3255 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3256 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3257 | ||
3258 | switch (offset) { | |
3259 | case 0x00: /* DRR2 */ | |
3260 | case 0x02: /* DRR1 */ | |
3261 | OMAP_RO_REG(addr); | |
3262 | return; | |
3263 | ||
3264 | case 0x04: /* DXR2 */ | |
3265 | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ | |
3266 | return; | |
3267 | /* Fall through. */ | |
3268 | case 0x06: /* DXR1 */ | |
73560bc8 AZ |
3269 | if (s->tx_req > 1) { |
3270 | s->tx_req -= 2; | |
3271 | if (s->codec && s->codec->cts) { | |
d8f699cb AZ |
3272 | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
3273 | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; | |
d8f699cb | 3274 | } |
73560bc8 AZ |
3275 | if (s->tx_req < 2) |
3276 | omap_mcbsp_tx_done(s); | |
d8f699cb AZ |
3277 | } else |
3278 | printf("%s: Tx FIFO overrun\n", __FUNCTION__); | |
3279 | return; | |
3280 | ||
3281 | case 0x08: /* SPCR2 */ | |
3282 | s->spcr[1] &= 0x0002; | |
3283 | s->spcr[1] |= 0x03f9 & value; | |
3284 | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ | |
73560bc8 | 3285 | if (~value & 1) /* XRST */ |
d8f699cb | 3286 | s->spcr[1] &= ~6; |
d8f699cb AZ |
3287 | omap_mcbsp_req_update(s); |
3288 | return; | |
3289 | case 0x0a: /* SPCR1 */ | |
3290 | s->spcr[0] &= 0x0006; | |
3291 | s->spcr[0] |= 0xf8f9 & value; | |
3292 | if (value & (1 << 15)) /* DLB */ | |
3293 | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); | |
3294 | if (~value & 1) { /* RRST */ | |
3295 | s->spcr[0] &= ~6; | |
73560bc8 AZ |
3296 | s->rx_req = 0; |
3297 | omap_mcbsp_rx_done(s); | |
d8f699cb | 3298 | } |
d8f699cb AZ |
3299 | omap_mcbsp_req_update(s); |
3300 | return; | |
3301 | ||
3302 | case 0x0c: /* RCR2 */ | |
3303 | s->rcr[1] = value & 0xffff; | |
3304 | return; | |
3305 | case 0x0e: /* RCR1 */ | |
3306 | s->rcr[0] = value & 0x7fe0; | |
3307 | return; | |
3308 | case 0x10: /* XCR2 */ | |
3309 | s->xcr[1] = value & 0xffff; | |
3310 | return; | |
3311 | case 0x12: /* XCR1 */ | |
3312 | s->xcr[0] = value & 0x7fe0; | |
3313 | return; | |
3314 | case 0x14: /* SRGR2 */ | |
3315 | s->srgr[1] = value & 0xffff; | |
73560bc8 | 3316 | omap_mcbsp_req_update(s); |
d8f699cb AZ |
3317 | return; |
3318 | case 0x16: /* SRGR1 */ | |
3319 | s->srgr[0] = value & 0xffff; | |
73560bc8 | 3320 | omap_mcbsp_req_update(s); |
d8f699cb AZ |
3321 | return; |
3322 | case 0x18: /* MCR2 */ | |
3323 | s->mcr[1] = value & 0x03e3; | |
3324 | if (value & 3) /* XMCM */ | |
3325 | printf("%s: Tx channel selection mode enable attempt\n", | |
3326 | __FUNCTION__); | |
3327 | return; | |
3328 | case 0x1a: /* MCR1 */ | |
3329 | s->mcr[0] = value & 0x03e1; | |
3330 | if (value & 1) /* RMCM */ | |
3331 | printf("%s: Rx channel selection mode enable attempt\n", | |
3332 | __FUNCTION__); | |
3333 | return; | |
3334 | case 0x1c: /* RCERA */ | |
3335 | s->rcer[0] = value & 0xffff; | |
3336 | return; | |
3337 | case 0x1e: /* RCERB */ | |
3338 | s->rcer[1] = value & 0xffff; | |
3339 | return; | |
3340 | case 0x20: /* XCERA */ | |
3341 | s->xcer[0] = value & 0xffff; | |
3342 | return; | |
3343 | case 0x22: /* XCERB */ | |
3344 | s->xcer[1] = value & 0xffff; | |
3345 | return; | |
3346 | case 0x24: /* PCR0 */ | |
3347 | s->pcr = value & 0x7faf; | |
3348 | return; | |
3349 | case 0x26: /* RCERC */ | |
3350 | s->rcer[2] = value & 0xffff; | |
3351 | return; | |
3352 | case 0x28: /* RCERD */ | |
3353 | s->rcer[3] = value & 0xffff; | |
3354 | return; | |
3355 | case 0x2a: /* XCERC */ | |
3356 | s->xcer[2] = value & 0xffff; | |
3357 | return; | |
3358 | case 0x2c: /* XCERD */ | |
3359 | s->xcer[3] = value & 0xffff; | |
3360 | return; | |
3361 | case 0x2e: /* RCERE */ | |
3362 | s->rcer[4] = value & 0xffff; | |
3363 | return; | |
3364 | case 0x30: /* RCERF */ | |
3365 | s->rcer[5] = value & 0xffff; | |
3366 | return; | |
3367 | case 0x32: /* XCERE */ | |
3368 | s->xcer[4] = value & 0xffff; | |
3369 | return; | |
3370 | case 0x34: /* XCERF */ | |
3371 | s->xcer[5] = value & 0xffff; | |
3372 | return; | |
3373 | case 0x36: /* RCERG */ | |
3374 | s->rcer[6] = value & 0xffff; | |
3375 | return; | |
3376 | case 0x38: /* RCERH */ | |
3377 | s->rcer[7] = value & 0xffff; | |
3378 | return; | |
3379 | case 0x3a: /* XCERG */ | |
3380 | s->xcer[6] = value & 0xffff; | |
3381 | return; | |
3382 | case 0x3c: /* XCERH */ | |
3383 | s->xcer[7] = value & 0xffff; | |
3384 | return; | |
3385 | } | |
3386 | ||
3387 | OMAP_BAD_REG(addr); | |
3388 | } | |
3389 | ||
a8170e5e | 3390 | static void omap_mcbsp_writew(void *opaque, hwaddr addr, |
73560bc8 AZ |
3391 | uint32_t value) |
3392 | { | |
3393 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3394 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3395 | ||
3396 | if (offset == 0x04) { /* DXR */ | |
3397 | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ | |
3398 | return; | |
3399 | if (s->tx_req > 3) { | |
3400 | s->tx_req -= 4; | |
3401 | if (s->codec && s->codec->cts) { | |
3402 | s->codec->out.fifo[s->codec->out.len ++] = | |
3403 | (value >> 24) & 0xff; | |
3404 | s->codec->out.fifo[s->codec->out.len ++] = | |
3405 | (value >> 16) & 0xff; | |
3406 | s->codec->out.fifo[s->codec->out.len ++] = | |
3407 | (value >> 8) & 0xff; | |
3408 | s->codec->out.fifo[s->codec->out.len ++] = | |
3409 | (value >> 0) & 0xff; | |
3410 | } | |
3411 | if (s->tx_req < 4) | |
3412 | omap_mcbsp_tx_done(s); | |
3413 | } else | |
3414 | printf("%s: Tx FIFO overrun\n", __FUNCTION__); | |
3415 | return; | |
3416 | } | |
3417 | ||
3418 | omap_badwidth_write16(opaque, addr, value); | |
3419 | } | |
3420 | ||
a8170e5e | 3421 | static void omap_mcbsp_write(void *opaque, hwaddr addr, |
a4ebbd18 AK |
3422 | uint64_t value, unsigned size) |
3423 | { | |
3424 | switch (size) { | |
77a8257e SW |
3425 | case 2: |
3426 | omap_mcbsp_writeh(opaque, addr, value); | |
3427 | break; | |
3428 | case 4: | |
3429 | omap_mcbsp_writew(opaque, addr, value); | |
3430 | break; | |
3431 | default: | |
3432 | omap_badwidth_write16(opaque, addr, value); | |
a4ebbd18 AK |
3433 | } |
3434 | } | |
d8f699cb | 3435 | |
a4ebbd18 AK |
3436 | static const MemoryRegionOps omap_mcbsp_ops = { |
3437 | .read = omap_mcbsp_read, | |
3438 | .write = omap_mcbsp_write, | |
3439 | .endianness = DEVICE_NATIVE_ENDIAN, | |
d8f699cb AZ |
3440 | }; |
3441 | ||
3442 | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) | |
3443 | { | |
3444 | memset(&s->spcr, 0, sizeof(s->spcr)); | |
3445 | memset(&s->rcr, 0, sizeof(s->rcr)); | |
3446 | memset(&s->xcr, 0, sizeof(s->xcr)); | |
3447 | s->srgr[0] = 0x0001; | |
3448 | s->srgr[1] = 0x2000; | |
3449 | memset(&s->mcr, 0, sizeof(s->mcr)); | |
3450 | memset(&s->pcr, 0, sizeof(s->pcr)); | |
3451 | memset(&s->rcer, 0, sizeof(s->rcer)); | |
3452 | memset(&s->xcer, 0, sizeof(s->xcer)); | |
3453 | s->tx_req = 0; | |
73560bc8 | 3454 | s->rx_req = 0; |
d8f699cb AZ |
3455 | s->tx_rate = 0; |
3456 | s->rx_rate = 0; | |
bc72ad67 AB |
3457 | timer_del(s->source_timer); |
3458 | timer_del(s->sink_timer); | |
d8f699cb AZ |
3459 | } |
3460 | ||
0919ac78 | 3461 | static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, |
a8170e5e | 3462 | hwaddr base, |
0919ac78 PM |
3463 | qemu_irq txirq, qemu_irq rxirq, |
3464 | qemu_irq *dma, omap_clk clk) | |
d8f699cb | 3465 | { |
b45c03f5 | 3466 | struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); |
d8f699cb | 3467 | |
0919ac78 PM |
3468 | s->txirq = txirq; |
3469 | s->rxirq = rxirq; | |
d8f699cb AZ |
3470 | s->txdrq = dma[0]; |
3471 | s->rxdrq = dma[1]; | |
bc72ad67 AB |
3472 | s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); |
3473 | s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); | |
d8f699cb AZ |
3474 | omap_mcbsp_reset(s); |
3475 | ||
2c9b15ca | 3476 | memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); |
a4ebbd18 | 3477 | memory_region_add_subregion(system_memory, base, &s->iomem); |
d8f699cb AZ |
3478 | |
3479 | return s; | |
3480 | } | |
3481 | ||
9596ebb7 | 3482 | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
d8f699cb AZ |
3483 | { |
3484 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3485 | ||
73560bc8 AZ |
3486 | if (s->rx_rate) { |
3487 | s->rx_req = s->codec->in.len; | |
3488 | omap_mcbsp_rx_newdata(s); | |
3489 | } | |
d8f699cb AZ |
3490 | } |
3491 | ||
9596ebb7 | 3492 | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
d8f699cb AZ |
3493 | { |
3494 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3495 | ||
73560bc8 AZ |
3496 | if (s->tx_rate) { |
3497 | s->tx_req = s->codec->out.size; | |
3498 | omap_mcbsp_tx_newdata(s); | |
3499 | } | |
d8f699cb AZ |
3500 | } |
3501 | ||
bc24a225 | 3502 | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) |
d8f699cb AZ |
3503 | { |
3504 | s->codec = slave; | |
f3c7d038 AF |
3505 | slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); |
3506 | slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); | |
d8f699cb AZ |
3507 | } |
3508 | ||
f9d43072 AZ |
3509 | /* LED Pulse Generators */ |
3510 | struct omap_lpg_s { | |
60fe76e3 | 3511 | MemoryRegion iomem; |
f9d43072 AZ |
3512 | QEMUTimer *tm; |
3513 | ||
3514 | uint8_t control; | |
3515 | uint8_t power; | |
3516 | int64_t on; | |
3517 | int64_t period; | |
3518 | int clk; | |
3519 | int cycle; | |
3520 | }; | |
3521 | ||
3522 | static void omap_lpg_tick(void *opaque) | |
3523 | { | |
3524 | struct omap_lpg_s *s = opaque; | |
3525 | ||
3526 | if (s->cycle) | |
bc72ad67 | 3527 | timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); |
f9d43072 | 3528 | else |
bc72ad67 | 3529 | timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); |
f9d43072 AZ |
3530 | |
3531 | s->cycle = !s->cycle; | |
3532 | printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); | |
3533 | } | |
3534 | ||
3535 | static void omap_lpg_update(struct omap_lpg_s *s) | |
3536 | { | |
3537 | int64_t on, period = 1, ticks = 1000; | |
3538 | static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; | |
3539 | ||
3540 | if (~s->control & (1 << 6)) /* LPGRES */ | |
3541 | on = 0; | |
3542 | else if (s->control & (1 << 7)) /* PERM_ON */ | |
3543 | on = period; | |
3544 | else { | |
3545 | period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ | |
3546 | 256 / 32); | |
3547 | on = (s->clk && s->power) ? muldiv64(ticks, | |
3548 | per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ | |
3549 | } | |
3550 | ||
bc72ad67 | 3551 | timer_del(s->tm); |
f9d43072 AZ |
3552 | if (on == period && s->on < s->period) |
3553 | printf("%s: LED is on\n", __FUNCTION__); | |
3554 | else if (on == 0 && s->on) | |
3555 | printf("%s: LED is off\n", __FUNCTION__); | |
3556 | else if (on && (on != s->on || period != s->period)) { | |
3557 | s->cycle = 0; | |
3558 | s->on = on; | |
3559 | s->period = period; | |
3560 | omap_lpg_tick(s); | |
3561 | return; | |
3562 | } | |
3563 | ||
3564 | s->on = on; | |
3565 | s->period = period; | |
3566 | } | |
3567 | ||
3568 | static void omap_lpg_reset(struct omap_lpg_s *s) | |
3569 | { | |
3570 | s->control = 0x00; | |
3571 | s->power = 0x00; | |
3572 | s->clk = 1; | |
3573 | omap_lpg_update(s); | |
3574 | } | |
3575 | ||
a8170e5e | 3576 | static uint64_t omap_lpg_read(void *opaque, hwaddr addr, |
60fe76e3 | 3577 | unsigned size) |
f9d43072 AZ |
3578 | { |
3579 | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | |
3580 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3581 | ||
60fe76e3 AK |
3582 | if (size != 1) { |
3583 | return omap_badwidth_read8(opaque, addr); | |
3584 | } | |
3585 | ||
f9d43072 AZ |
3586 | switch (offset) { |
3587 | case 0x00: /* LCR */ | |
3588 | return s->control; | |
3589 | ||
3590 | case 0x04: /* PMR */ | |
3591 | return s->power; | |
3592 | } | |
3593 | ||
3594 | OMAP_BAD_REG(addr); | |
3595 | return 0; | |
3596 | } | |
3597 | ||
a8170e5e | 3598 | static void omap_lpg_write(void *opaque, hwaddr addr, |
60fe76e3 | 3599 | uint64_t value, unsigned size) |
f9d43072 AZ |
3600 | { |
3601 | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | |
3602 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3603 | ||
60fe76e3 | 3604 | if (size != 1) { |
77a8257e SW |
3605 | omap_badwidth_write8(opaque, addr, value); |
3606 | return; | |
60fe76e3 AK |
3607 | } |
3608 | ||
f9d43072 AZ |
3609 | switch (offset) { |
3610 | case 0x00: /* LCR */ | |
3611 | if (~value & (1 << 6)) /* LPGRES */ | |
3612 | omap_lpg_reset(s); | |
3613 | s->control = value & 0xff; | |
3614 | omap_lpg_update(s); | |
3615 | return; | |
3616 | ||
3617 | case 0x04: /* PMR */ | |
3618 | s->power = value & 0x01; | |
3619 | omap_lpg_update(s); | |
3620 | return; | |
3621 | ||
3622 | default: | |
3623 | OMAP_BAD_REG(addr); | |
3624 | return; | |
3625 | } | |
3626 | } | |
3627 | ||
60fe76e3 AK |
3628 | static const MemoryRegionOps omap_lpg_ops = { |
3629 | .read = omap_lpg_read, | |
3630 | .write = omap_lpg_write, | |
3631 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f9d43072 AZ |
3632 | }; |
3633 | ||
3634 | static void omap_lpg_clk_update(void *opaque, int line, int on) | |
3635 | { | |
3636 | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | |
3637 | ||
3638 | s->clk = on; | |
3639 | omap_lpg_update(s); | |
3640 | } | |
3641 | ||
60fe76e3 | 3642 | static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, |
a8170e5e | 3643 | hwaddr base, omap_clk clk) |
f9d43072 | 3644 | { |
b45c03f5 | 3645 | struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); |
f9d43072 | 3646 | |
bc72ad67 | 3647 | s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); |
f9d43072 AZ |
3648 | |
3649 | omap_lpg_reset(s); | |
3650 | ||
2c9b15ca | 3651 | memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); |
60fe76e3 | 3652 | memory_region_add_subregion(system_memory, base, &s->iomem); |
f9d43072 | 3653 | |
f3c7d038 | 3654 | omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); |
f9d43072 AZ |
3655 | |
3656 | return s; | |
3657 | } | |
3658 | ||
3659 | /* MPUI Peripheral Bridge configuration */ | |
a8170e5e | 3660 | static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, |
60fe76e3 | 3661 | unsigned size) |
f9d43072 | 3662 | { |
60fe76e3 AK |
3663 | if (size != 2) { |
3664 | return omap_badwidth_read16(opaque, addr); | |
3665 | } | |
3666 | ||
f9d43072 AZ |
3667 | if (addr == OMAP_MPUI_BASE) /* CMR */ |
3668 | return 0xfe4d; | |
3669 | ||
3670 | OMAP_BAD_REG(addr); | |
3671 | return 0; | |
3672 | } | |
3673 | ||
a8170e5e | 3674 | static void omap_mpui_io_write(void *opaque, hwaddr addr, |
60fe76e3 AK |
3675 | uint64_t value, unsigned size) |
3676 | { | |
3677 | /* FIXME: infinite loop */ | |
3678 | omap_badwidth_write16(opaque, addr, value); | |
3679 | } | |
f9d43072 | 3680 | |
60fe76e3 AK |
3681 | static const MemoryRegionOps omap_mpui_io_ops = { |
3682 | .read = omap_mpui_io_read, | |
3683 | .write = omap_mpui_io_write, | |
3684 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f9d43072 AZ |
3685 | }; |
3686 | ||
60fe76e3 AK |
3687 | static void omap_setup_mpui_io(MemoryRegion *system_memory, |
3688 | struct omap_mpu_state_s *mpu) | |
f9d43072 | 3689 | { |
2c9b15ca | 3690 | memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, |
60fe76e3 AK |
3691 | "omap-mpui-io", 0x7fff); |
3692 | memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, | |
3693 | &mpu->mpui_io_iomem); | |
f9d43072 AZ |
3694 | } |
3695 | ||
c3d2689d | 3696 | /* General chip reset */ |
827df9f3 | 3697 | static void omap1_mpu_reset(void *opaque) |
c3d2689d AZ |
3698 | { |
3699 | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | |
3700 | ||
c3d2689d AZ |
3701 | omap_dma_reset(mpu->dma); |
3702 | omap_mpu_timer_reset(mpu->timer[0]); | |
3703 | omap_mpu_timer_reset(mpu->timer[1]); | |
3704 | omap_mpu_timer_reset(mpu->timer[2]); | |
3705 | omap_wd_timer_reset(mpu->wdt); | |
3706 | omap_os_timer_reset(mpu->os_timer); | |
3707 | omap_lcdc_reset(mpu->lcd); | |
3708 | omap_ulpd_pm_reset(mpu); | |
3709 | omap_pin_cfg_reset(mpu); | |
3710 | omap_mpui_reset(mpu); | |
3711 | omap_tipb_bridge_reset(mpu->private_tipb); | |
3712 | omap_tipb_bridge_reset(mpu->public_tipb); | |
b9f7bc40 JR |
3713 | omap_dpll_reset(mpu->dpll[0]); |
3714 | omap_dpll_reset(mpu->dpll[1]); | |
3715 | omap_dpll_reset(mpu->dpll[2]); | |
d951f6ff AZ |
3716 | omap_uart_reset(mpu->uart[0]); |
3717 | omap_uart_reset(mpu->uart[1]); | |
3718 | omap_uart_reset(mpu->uart[2]); | |
b30bb3a2 | 3719 | omap_mmc_reset(mpu->mmc); |
fe71e81a | 3720 | omap_mpuio_reset(mpu->mpuio); |
d951f6ff | 3721 | omap_uwire_reset(mpu->microwire); |
8717d88a | 3722 | omap_pwl_reset(mpu->pwl); |
03759534 | 3723 | omap_pwt_reset(mpu->pwt); |
5c1c390f | 3724 | omap_rtc_reset(mpu->rtc); |
d8f699cb AZ |
3725 | omap_mcbsp_reset(mpu->mcbsp1); |
3726 | omap_mcbsp_reset(mpu->mcbsp2); | |
3727 | omap_mcbsp_reset(mpu->mcbsp3); | |
f9d43072 AZ |
3728 | omap_lpg_reset(mpu->led[0]); |
3729 | omap_lpg_reset(mpu->led[1]); | |
8ef6367e | 3730 | omap_clkm_reset(mpu); |
5f4ef08b | 3731 | cpu_reset(CPU(mpu->cpu)); |
c3d2689d AZ |
3732 | } |
3733 | ||
cf965d24 | 3734 | static const struct omap_map_s { |
a8170e5e AK |
3735 | hwaddr phys_dsp; |
3736 | hwaddr phys_mpu; | |
cf965d24 AZ |
3737 | uint32_t size; |
3738 | const char *name; | |
3739 | } omap15xx_dsp_mm[] = { | |
3740 | /* Strobe 0 */ | |
3741 | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ | |
3742 | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ | |
3743 | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ | |
3744 | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ | |
3745 | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ | |
3746 | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ | |
3747 | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ | |
3748 | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ | |
3749 | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ | |
3750 | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ | |
3751 | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ | |
3752 | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ | |
3753 | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ | |
3754 | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ | |
3755 | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ | |
3756 | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ | |
3757 | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ | |
3758 | /* Strobe 1 */ | |
3759 | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ | |
3760 | ||
3761 | { 0 } | |
3762 | }; | |
3763 | ||
763b946c AK |
3764 | static void omap_setup_dsp_mapping(MemoryRegion *system_memory, |
3765 | const struct omap_map_s *map) | |
cf965d24 | 3766 | { |
763b946c | 3767 | MemoryRegion *io; |
cf965d24 AZ |
3768 | |
3769 | for (; map->phys_dsp; map ++) { | |
763b946c | 3770 | io = g_new(MemoryRegion, 1); |
2c9b15ca | 3771 | memory_region_init_alias(io, NULL, map->name, |
763b946c AK |
3772 | system_memory, map->phys_mpu, map->size); |
3773 | memory_region_add_subregion(system_memory, map->phys_dsp, io); | |
cf965d24 AZ |
3774 | } |
3775 | } | |
3776 | ||
827df9f3 | 3777 | void omap_mpu_wakeup(void *opaque, int irq, int req) |
c3d2689d AZ |
3778 | { |
3779 | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | |
259186a7 | 3780 | CPUState *cpu = CPU(mpu->cpu); |
c3d2689d | 3781 | |
259186a7 | 3782 | if (cpu->halted) { |
c3affe56 | 3783 | cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); |
5f4ef08b | 3784 | } |
c3d2689d AZ |
3785 | } |
3786 | ||
827df9f3 | 3787 | static const struct dma_irq_map omap1_dma_irq_map[] = { |
089b7c0a AZ |
3788 | { 0, OMAP_INT_DMA_CH0_6 }, |
3789 | { 0, OMAP_INT_DMA_CH1_7 }, | |
3790 | { 0, OMAP_INT_DMA_CH2_8 }, | |
3791 | { 0, OMAP_INT_DMA_CH3 }, | |
3792 | { 0, OMAP_INT_DMA_CH4 }, | |
3793 | { 0, OMAP_INT_DMA_CH5 }, | |
3794 | { 1, OMAP_INT_1610_DMA_CH6 }, | |
3795 | { 1, OMAP_INT_1610_DMA_CH7 }, | |
3796 | { 1, OMAP_INT_1610_DMA_CH8 }, | |
3797 | { 1, OMAP_INT_1610_DMA_CH9 }, | |
3798 | { 1, OMAP_INT_1610_DMA_CH10 }, | |
3799 | { 1, OMAP_INT_1610_DMA_CH11 }, | |
3800 | { 1, OMAP_INT_1610_DMA_CH12 }, | |
3801 | { 1, OMAP_INT_1610_DMA_CH13 }, | |
3802 | { 1, OMAP_INT_1610_DMA_CH14 }, | |
3803 | { 1, OMAP_INT_1610_DMA_CH15 } | |
3804 | }; | |
3805 | ||
b4e3104b AZ |
3806 | /* DMA ports for OMAP1 */ |
3807 | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3808 | hwaddr addr) |
b4e3104b | 3809 | { |
45416789 | 3810 | return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); |
b4e3104b AZ |
3811 | } |
3812 | ||
3813 | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3814 | hwaddr addr) |
b4e3104b | 3815 | { |
45416789 BS |
3816 | return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, |
3817 | addr); | |
b4e3104b AZ |
3818 | } |
3819 | ||
3820 | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3821 | hwaddr addr) |
b4e3104b | 3822 | { |
45416789 | 3823 | return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); |
b4e3104b AZ |
3824 | } |
3825 | ||
3826 | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3827 | hwaddr addr) |
b4e3104b | 3828 | { |
45416789 | 3829 | return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); |
b4e3104b AZ |
3830 | } |
3831 | ||
3832 | static int omap_validate_local_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3833 | hwaddr addr) |
b4e3104b | 3834 | { |
45416789 | 3835 | return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); |
b4e3104b AZ |
3836 | } |
3837 | ||
3838 | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3839 | hwaddr addr) |
b4e3104b | 3840 | { |
45416789 | 3841 | return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); |
b4e3104b AZ |
3842 | } |
3843 | ||
4b3fedf3 AK |
3844 | struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, |
3845 | unsigned long sdram_size, | |
3023f332 | 3846 | const char *core) |
c3d2689d | 3847 | { |
089b7c0a | 3848 | int i; |
b45c03f5 | 3849 | struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); |
089b7c0a | 3850 | qemu_irq dma_irqs[6]; |
751c6a17 | 3851 | DriveInfo *dinfo; |
0919ac78 | 3852 | SysBusDevice *busdev; |
106627d0 | 3853 | |
aaed909a FB |
3854 | if (!core) |
3855 | core = "ti925t"; | |
c3d2689d AZ |
3856 | |
3857 | /* Core */ | |
3858 | s->mpu_model = omap310; | |
5f4ef08b AF |
3859 | s->cpu = cpu_arm_init(core); |
3860 | if (s->cpu == NULL) { | |
aaed909a FB |
3861 | fprintf(stderr, "Unable to find CPU definition\n"); |
3862 | exit(1); | |
3863 | } | |
c3d2689d AZ |
3864 | s->sdram_size = sdram_size; |
3865 | s->sram_size = OMAP15XX_SRAM_SIZE; | |
3866 | ||
f3c7d038 | 3867 | s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); |
fe71e81a | 3868 | |
c3d2689d AZ |
3869 | /* Clocks */ |
3870 | omap_clk_init(s); | |
3871 | ||
3872 | /* Memory-mapped stuff */ | |
c8623c02 DM |
3873 | memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", |
3874 | s->sdram_size); | |
2654c962 | 3875 | memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); |
49946538 | 3876 | memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, |
f8ed85ac | 3877 | &error_fatal); |
c5705a77 | 3878 | vmstate_register_ram_global(&s->imif_ram); |
2654c962 | 3879 | memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); |
c3d2689d | 3880 | |
e7aa0ae0 | 3881 | omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); |
c3d2689d | 3882 | |
0919ac78 PM |
3883 | s->ih[0] = qdev_create(NULL, "omap-intc"); |
3884 | qdev_prop_set_uint32(s->ih[0], "size", 0x100); | |
3885 | qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); | |
3886 | qdev_init_nofail(s->ih[0]); | |
1356b98d | 3887 | busdev = SYS_BUS_DEVICE(s->ih[0]); |
437f0f10 PM |
3888 | sysbus_connect_irq(busdev, 0, |
3889 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); | |
3890 | sysbus_connect_irq(busdev, 1, | |
3891 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); | |
0919ac78 PM |
3892 | sysbus_mmio_map(busdev, 0, 0xfffecb00); |
3893 | s->ih[1] = qdev_create(NULL, "omap-intc"); | |
3894 | qdev_prop_set_uint32(s->ih[1], "size", 0x800); | |
3895 | qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); | |
3896 | qdev_init_nofail(s->ih[1]); | |
1356b98d | 3897 | busdev = SYS_BUS_DEVICE(s->ih[1]); |
0919ac78 PM |
3898 | sysbus_connect_irq(busdev, 0, |
3899 | qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); | |
3900 | /* The second interrupt controller's FIQ output is not wired up */ | |
3901 | sysbus_mmio_map(busdev, 0, 0xfffe0000); | |
3902 | ||
3903 | for (i = 0; i < 6; i++) { | |
3904 | dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], | |
3905 | omap1_dma_irq_map[i].intr); | |
3906 | } | |
7405165e | 3907 | s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, |
0919ac78 | 3908 | qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), |
089b7c0a AZ |
3909 | s, omap_findclk(s, "dma_ck"), omap_dma_3_1); |
3910 | ||
c3d2689d AZ |
3911 | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
3912 | s->port[emifs ].addr_valid = omap_validate_emifs_addr; | |
3913 | s->port[imif ].addr_valid = omap_validate_imif_addr; | |
3914 | s->port[tipb ].addr_valid = omap_validate_tipb_addr; | |
3915 | s->port[local ].addr_valid = omap_validate_local_addr; | |
3916 | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; | |
3917 | ||
afbb5194 | 3918 | /* Register SDRAM and SRAM DMA ports for fast transfers. */ |
2654c962 AK |
3919 | soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), |
3920 | OMAP_EMIFF_BASE, s->sdram_size); | |
3921 | soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), | |
90aeba9d | 3922 | OMAP_IMIF_BASE, s->sram_size); |
afbb5194 | 3923 | |
4b3fedf3 | 3924 | s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, |
0919ac78 | 3925 | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), |
c3d2689d | 3926 | omap_findclk(s, "mputim_ck")); |
4b3fedf3 | 3927 | s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, |
0919ac78 | 3928 | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), |
c3d2689d | 3929 | omap_findclk(s, "mputim_ck")); |
4b3fedf3 | 3930 | s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, |
0919ac78 | 3931 | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), |
c3d2689d AZ |
3932 | omap_findclk(s, "mputim_ck")); |
3933 | ||
4b3fedf3 | 3934 | s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, |
0919ac78 | 3935 | qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), |
c3d2689d AZ |
3936 | omap_findclk(s, "armwdt_ck")); |
3937 | ||
4b3fedf3 | 3938 | s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, |
0919ac78 | 3939 | qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), |
c3d2689d AZ |
3940 | omap_findclk(s, "clk32-kHz")); |
3941 | ||
30af1ec7 | 3942 | s->lcd = omap_lcdc_init(system_memory, 0xfffec000, |
0919ac78 PM |
3943 | qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), |
3944 | omap_dma_get_lcdch(s->dma), | |
3945 | omap_findclk(s, "lcd_ck")); | |
c3d2689d | 3946 | |
4b3fedf3 AK |
3947 | omap_ulpd_pm_init(system_memory, 0xfffe0800, s); |
3948 | omap_pin_cfg_init(system_memory, 0xfffe1000, s); | |
3949 | omap_id_init(system_memory, s); | |
c3d2689d | 3950 | |
4b3fedf3 | 3951 | omap_mpui_init(system_memory, 0xfffec900, s); |
c3d2689d | 3952 | |
4b3fedf3 | 3953 | s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, |
0919ac78 | 3954 | qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), |
c3d2689d | 3955 | omap_findclk(s, "tipb_ck")); |
4b3fedf3 | 3956 | s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, |
0919ac78 | 3957 | qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), |
c3d2689d AZ |
3958 | omap_findclk(s, "tipb_ck")); |
3959 | ||
e7aa0ae0 | 3960 | omap_tcmi_init(system_memory, 0xfffecc00, s); |
c3d2689d | 3961 | |
0919ac78 PM |
3962 | s->uart[0] = omap_uart_init(0xfffb0000, |
3963 | qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), | |
c3d2689d | 3964 | omap_findclk(s, "uart1_ck"), |
827df9f3 AZ |
3965 | omap_findclk(s, "uart1_ck"), |
3966 | s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], | |
6a8aabd3 | 3967 | "uart1", |
c3d2689d | 3968 | serial_hds[0]); |
0919ac78 PM |
3969 | s->uart[1] = omap_uart_init(0xfffb0800, |
3970 | qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), | |
c3d2689d | 3971 | omap_findclk(s, "uart2_ck"), |
827df9f3 AZ |
3972 | omap_findclk(s, "uart2_ck"), |
3973 | s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], | |
6a8aabd3 | 3974 | "uart2", |
b9d38e95 | 3975 | serial_hds[0] ? serial_hds[1] : NULL); |
0919ac78 PM |
3976 | s->uart[2] = omap_uart_init(0xfffb9800, |
3977 | qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), | |
c3d2689d | 3978 | omap_findclk(s, "uart3_ck"), |
827df9f3 AZ |
3979 | omap_findclk(s, "uart3_ck"), |
3980 | s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], | |
6a8aabd3 | 3981 | "uart3", |
b9d38e95 | 3982 | serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
c3d2689d | 3983 | |
b9f7bc40 JR |
3984 | s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, |
3985 | omap_findclk(s, "dpll1")); | |
3986 | s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, | |
3987 | omap_findclk(s, "dpll2")); | |
3988 | s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, | |
3989 | omap_findclk(s, "dpll3")); | |
c3d2689d | 3990 | |
751c6a17 GH |
3991 | dinfo = drive_get(IF_SD, 0, 0); |
3992 | if (!dinfo) { | |
e4bcb14c TS |
3993 | fprintf(stderr, "qemu: missing SecureDigital device\n"); |
3994 | exit(1); | |
3995 | } | |
fa1d36df | 3996 | s->mmc = omap_mmc_init(0xfffb7800, system_memory, |
4be74634 | 3997 | blk_by_legacy_dinfo(dinfo), |
0919ac78 PM |
3998 | qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), |
3999 | &s->drq[OMAP_DMA_MMC_TX], | |
9d413d1d | 4000 | omap_findclk(s, "mmc_ck")); |
b30bb3a2 | 4001 | |
e7aa0ae0 | 4002 | s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, |
0919ac78 PM |
4003 | qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), |
4004 | qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), | |
4005 | s->wakeup, omap_findclk(s, "clk32-kHz")); | |
fe71e81a | 4006 | |
77831c20 JR |
4007 | s->gpio = qdev_create(NULL, "omap-gpio"); |
4008 | qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); | |
bdbc1b3c | 4009 | qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); |
77831c20 | 4010 | qdev_init_nofail(s->gpio); |
1356b98d | 4011 | sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, |
0919ac78 | 4012 | qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); |
1356b98d | 4013 | sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); |
64330148 | 4014 | |
0919ac78 PM |
4015 | s->microwire = omap_uwire_init(system_memory, 0xfffb3000, |
4016 | qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), | |
4017 | qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), | |
d951f6ff AZ |
4018 | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); |
4019 | ||
8717d88a JR |
4020 | s->pwl = omap_pwl_init(system_memory, 0xfffb5800, |
4021 | omap_findclk(s, "armxor_ck")); | |
03759534 JR |
4022 | s->pwt = omap_pwt_init(system_memory, 0xfffb6000, |
4023 | omap_findclk(s, "armxor_ck")); | |
66450b15 | 4024 | |
54e17933 JR |
4025 | s->i2c[0] = qdev_create(NULL, "omap_i2c"); |
4026 | qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); | |
4027 | qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); | |
4028 | qdev_init_nofail(s->i2c[0]); | |
1356b98d | 4029 | busdev = SYS_BUS_DEVICE(s->i2c[0]); |
54e17933 JR |
4030 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); |
4031 | sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); | |
4032 | sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); | |
4033 | sysbus_mmio_map(busdev, 0, 0xfffb3800); | |
4a2c8ac2 | 4034 | |
a4ebbd18 | 4035 | s->rtc = omap_rtc_init(system_memory, 0xfffb4800, |
0919ac78 PM |
4036 | qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), |
4037 | qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), | |
5c1c390f | 4038 | omap_findclk(s, "clk32-kHz")); |
02645926 | 4039 | |
0919ac78 PM |
4040 | s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, |
4041 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), | |
4042 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), | |
d8f699cb | 4043 | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); |
0919ac78 PM |
4044 | s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, |
4045 | qdev_get_gpio_in(s->ih[0], | |
4046 | OMAP_INT_310_McBSP2_TX), | |
4047 | qdev_get_gpio_in(s->ih[0], | |
4048 | OMAP_INT_310_McBSP2_RX), | |
d8f699cb | 4049 | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); |
0919ac78 PM |
4050 | s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, |
4051 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), | |
4052 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), | |
d8f699cb AZ |
4053 | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); |
4054 | ||
60fe76e3 AK |
4055 | s->led[0] = omap_lpg_init(system_memory, |
4056 | 0xfffbd000, omap_findclk(s, "clk32-kHz")); | |
4057 | s->led[1] = omap_lpg_init(system_memory, | |
4058 | 0xfffbd800, omap_findclk(s, "clk32-kHz")); | |
f9d43072 | 4059 | |
02645926 | 4060 | /* Register mappings not currenlty implemented: |
02645926 AZ |
4061 | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) |
4062 | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) | |
4063 | * USB W2FC fffb4000 - fffb47ff | |
4064 | * Camera Interface fffb6800 - fffb6fff | |
02645926 AZ |
4065 | * USB Host fffba000 - fffba7ff |
4066 | * FAC fffba800 - fffbafff | |
4067 | * HDQ/1-Wire fffbc000 - fffbc7ff | |
b854bc19 | 4068 | * TIPB switches fffbc800 - fffbcfff |
02645926 AZ |
4069 | * Mailbox fffcf000 - fffcf7ff |
4070 | * Local bus IF fffec100 - fffec1ff | |
4071 | * Local bus MMU fffec200 - fffec2ff | |
4072 | * DSP MMU fffed200 - fffed2ff | |
4073 | */ | |
4074 | ||
763b946c | 4075 | omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); |
60fe76e3 | 4076 | omap_setup_mpui_io(system_memory, s); |
cf965d24 | 4077 | |
a08d4367 | 4078 | qemu_register_reset(omap1_mpu_reset, s); |
c3d2689d AZ |
4079 | |
4080 | return s; | |
4081 | } |