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f5fdcd6e PM |
1 | /* |
2 | * ARM mach-virt emulation | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Emulate a virtual board which works by passing Linux all the information | |
19 | * it needs about what devices are present via the device tree. | |
20 | * There are some restrictions about what we can do here: | |
21 | * + we can only present devices whose Linux drivers will work based | |
22 | * purely on the device tree with no platform data at all | |
23 | * + we want to present a very stripped-down minimalist platform, | |
24 | * both because this reduces the security attack surface from the guest | |
25 | * and also because it reduces our exposure to being broken when | |
26 | * the kernel updates its device tree bindings and requires further | |
27 | * information in a device binding that we aren't providing. | |
28 | * This is essentially the same approach kvmtool uses. | |
29 | */ | |
30 | ||
12b16722 | 31 | #include "qemu/osdep.h" |
a8d25326 | 32 | #include "qemu-common.h" |
350a9c9e | 33 | #include "qemu/units.h" |
e0561e60 | 34 | #include "qemu/option.h" |
da34e65c | 35 | #include "qapi/error.h" |
f5fdcd6e | 36 | #include "hw/sysbus.h" |
12e9493d | 37 | #include "hw/boards.h" |
12ec8bd5 | 38 | #include "hw/arm/boot.h" |
f5fdcd6e | 39 | #include "hw/arm/primecell.h" |
afe0b380 | 40 | #include "hw/arm/virt.h" |
81c7db72 | 41 | #include "hw/block/flash.h" |
6f2062b9 EH |
42 | #include "hw/vfio/vfio-calxeda-xgmac.h" |
43 | #include "hw/vfio/vfio-amd-xgbe.h" | |
94692dcd | 44 | #include "hw/display/ramfb.h" |
f5fdcd6e PM |
45 | #include "net/net.h" |
46 | #include "sysemu/device_tree.h" | |
9695200a | 47 | #include "sysemu/numa.h" |
54d31236 | 48 | #include "sysemu/runstate.h" |
f5fdcd6e PM |
49 | #include "sysemu/sysemu.h" |
50 | #include "sysemu/kvm.h" | |
acf82361 | 51 | #include "hw/loader.h" |
f5fdcd6e PM |
52 | #include "exec/address-spaces.h" |
53 | #include "qemu/bitops.h" | |
54 | #include "qemu/error-report.h" | |
0b8fa32f | 55 | #include "qemu/module.h" |
4ab29b82 | 56 | #include "hw/pci-host/gpex.h" |
5f7a5a0e EA |
57 | #include "hw/arm/sysbus-fdt.h" |
58 | #include "hw/platform-bus.h" | |
a27bd6c7 | 59 | #include "hw/qdev-properties.h" |
decf4f80 | 60 | #include "hw/arm/fdt.h" |
95eb49c8 AJ |
61 | #include "hw/intc/arm_gic.h" |
62 | #include "hw/intc/arm_gicv3_common.h" | |
64552b6b | 63 | #include "hw/irq.h" |
e6fbcbc4 | 64 | #include "kvm_arm.h" |
a2eb5c0c | 65 | #include "hw/firmware/smbios.h" |
b92ad394 | 66 | #include "qapi/visitor.h" |
3e6ebb64 | 67 | #include "standard-headers/linux/input.h" |
584105ea | 68 | #include "hw/arm/smmuv3.h" |
957e32cf | 69 | #include "hw/acpi/acpi.h" |
2ba956cc | 70 | #include "target/arm/internals.h" |
f5fdcd6e | 71 | |
3356ebce | 72 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ |
ab093c3c AJ |
73 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ |
74 | void *data) \ | |
75 | { \ | |
76 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
77 | virt_machine_##major##_##minor##_options(mc); \ | |
78 | mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ | |
3356ebce AJ |
79 | if (latest) { \ |
80 | mc->alias = "virt"; \ | |
81 | } \ | |
ab093c3c AJ |
82 | } \ |
83 | static const TypeInfo machvirt_##major##_##minor##_info = { \ | |
84 | .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ | |
85 | .parent = TYPE_VIRT_MACHINE, \ | |
ab093c3c AJ |
86 | .class_init = virt_##major##_##minor##_class_init, \ |
87 | }; \ | |
88 | static void machvirt_machine_##major##_##minor##_init(void) \ | |
89 | { \ | |
90 | type_register_static(&machvirt_##major##_##minor##_info); \ | |
91 | } \ | |
92 | type_init(machvirt_machine_##major##_##minor##_init); | |
93 | ||
3356ebce AJ |
94 | #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ |
95 | DEFINE_VIRT_MACHINE_LATEST(major, minor, true) | |
96 | #define DEFINE_VIRT_MACHINE(major, minor) \ | |
97 | DEFINE_VIRT_MACHINE_LATEST(major, minor, false) | |
98 | ||
ab093c3c | 99 | |
a72d4363 AJ |
100 | /* Number of external interrupt lines to configure the GIC with */ |
101 | #define NUM_IRQS 256 | |
102 | ||
103 | #define PLATFORM_BUS_NUM_IRQS 64 | |
104 | ||
50a17297 | 105 | /* Legacy RAM limit in GB (< version 4.0) */ |
957e32cf EA |
106 | #define LEGACY_RAMLIMIT_GB 255 |
107 | #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) | |
71c27684 | 108 | |
f5fdcd6e PM |
109 | /* Addresses and sizes of our components. |
110 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | |
111 | * 128MB..256MB is used for miscellaneous device I/O. | |
112 | * 256MB..1GB is reserved for possible future PCI support (ie where the | |
113 | * PCI memory window will go if we add a PCI host controller). | |
114 | * 1GB and up is RAM (which may happily spill over into the | |
115 | * high memory region beyond 4GB). | |
116 | * This represents a compromise between how much RAM can be given to | |
117 | * a 32 bit VM and leaving space for expansion and in particular for PCI. | |
6e411af9 PM |
118 | * Note that devices should generally be placed at multiples of 0x10000, |
119 | * to accommodate guests using 64K pages. | |
f5fdcd6e | 120 | */ |
350a9c9e | 121 | static const MemMapEntry base_memmap[] = { |
f5fdcd6e | 122 | /* Space up to 0x8000000 is reserved for a boot ROM */ |
94edf02c EA |
123 | [VIRT_FLASH] = { 0, 0x08000000 }, |
124 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | |
f5fdcd6e | 125 | /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ |
94edf02c EA |
126 | [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, |
127 | [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, | |
128 | [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, | |
55ef3233 LM |
129 | [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, |
130 | [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, | |
b92ad394 PF |
131 | /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ |
132 | [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, | |
133 | /* This redistributor space allows up to 2*64kB*123 CPUs */ | |
134 | [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, | |
94edf02c EA |
135 | [VIRT_UART] = { 0x09000000, 0x00001000 }, |
136 | [VIRT_RTC] = { 0x09010000, 0x00001000 }, | |
0b341a85 | 137 | [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, |
b0a3721e | 138 | [VIRT_GPIO] = { 0x09030000, 0x00001000 }, |
3df708eb | 139 | [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, |
584105ea | 140 | [VIRT_SMMU] = { 0x09050000, 0x00020000 }, |
94edf02c | 141 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, |
f5fdcd6e | 142 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ |
94edf02c | 143 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, |
83ec1923 | 144 | [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, |
94edf02c EA |
145 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, |
146 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | |
147 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | |
957e32cf EA |
148 | /* Actual RAM size depends on initial RAM and device memory settings */ |
149 | [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, | |
350a9c9e EA |
150 | }; |
151 | ||
152 | /* | |
153 | * Highmem IO Regions: This memory map is floating, located after the RAM. | |
154 | * Each MemMapEntry base (GPA) will be dynamically computed, depending on the | |
155 | * top of the RAM, so that its base get the same alignment as the size, | |
156 | * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is | |
157 | * less than 256GiB of RAM, the floating area starts at the 256GiB mark. | |
158 | * Note the extended_memmap is sized so that it eventually also includes the | |
159 | * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last | |
160 | * index of base_memmap). | |
161 | */ | |
162 | static MemMapEntry extended_memmap[] = { | |
f90747c4 | 163 | /* Additional 64 MB redist region (can contain up to 512 redistributors) */ |
350a9c9e EA |
164 | [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, |
165 | [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, | |
166 | /* Second PCIe window */ | |
167 | [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, | |
f5fdcd6e PM |
168 | }; |
169 | ||
170 | static const int a15irqmap[] = { | |
171 | [VIRT_UART] = 1, | |
6e411af9 | 172 | [VIRT_RTC] = 2, |
4ab29b82 | 173 | [VIRT_PCIE] = 3, /* ... to 6 */ |
b0a3721e | 174 | [VIRT_GPIO] = 7, |
3df708eb | 175 | [VIRT_SECURE_UART] = 8, |
f5fdcd6e | 176 | [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ |
bd204e63 | 177 | [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ |
584105ea | 178 | [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ |
5f7a5a0e | 179 | [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ |
f5fdcd6e PM |
180 | }; |
181 | ||
9ac4ef77 | 182 | static const char *valid_cpus[] = { |
4414942e | 183 | ARM_CPU_TYPE_NAME("cortex-a7"), |
ba1ba5cc IM |
184 | ARM_CPU_TYPE_NAME("cortex-a15"), |
185 | ARM_CPU_TYPE_NAME("cortex-a53"), | |
186 | ARM_CPU_TYPE_NAME("cortex-a57"), | |
2264faa5 | 187 | ARM_CPU_TYPE_NAME("cortex-a72"), |
ba1ba5cc | 188 | ARM_CPU_TYPE_NAME("host"), |
9076ddb3 | 189 | ARM_CPU_TYPE_NAME("max"), |
f5fdcd6e PM |
190 | }; |
191 | ||
ba1ba5cc | 192 | static bool cpu_type_valid(const char *cpu) |
f5fdcd6e PM |
193 | { |
194 | int i; | |
195 | ||
9ac4ef77 PM |
196 | for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { |
197 | if (strcmp(cpu, valid_cpus[i]) == 0) { | |
198 | return true; | |
f5fdcd6e PM |
199 | } |
200 | } | |
9ac4ef77 | 201 | return false; |
f5fdcd6e PM |
202 | } |
203 | ||
c8ef2bda | 204 | static void create_fdt(VirtMachineState *vms) |
f5fdcd6e | 205 | { |
c8ef2bda | 206 | void *fdt = create_device_tree(&vms->fdt_size); |
f5fdcd6e PM |
207 | |
208 | if (!fdt) { | |
209 | error_report("create_device_tree() failed"); | |
210 | exit(1); | |
211 | } | |
212 | ||
c8ef2bda | 213 | vms->fdt = fdt; |
f5fdcd6e PM |
214 | |
215 | /* Header */ | |
5a4348d1 PC |
216 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); |
217 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
218 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
f5fdcd6e | 219 | |
e2eb3d29 | 220 | /* /chosen must exist for load_dtb to fill in necessary properties later */ |
5a4348d1 | 221 | qemu_fdt_add_subnode(fdt, "/chosen"); |
f5fdcd6e PM |
222 | |
223 | /* Clock node, for the benefit of the UART. The kernel device tree | |
224 | * binding documentation claims the PL011 node clock properties are | |
225 | * optional but in practice if you omit them the kernel refuses to | |
226 | * probe for the device. | |
227 | */ | |
c8ef2bda | 228 | vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); |
5a4348d1 PC |
229 | qemu_fdt_add_subnode(fdt, "/apb-pclk"); |
230 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); | |
231 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); | |
232 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); | |
233 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", | |
f5fdcd6e | 234 | "clk24mhz"); |
c8ef2bda | 235 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); |
f5fdcd6e | 236 | |
c7637c04 AJ |
237 | if (have_numa_distance) { |
238 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | |
239 | uint32_t *matrix = g_malloc0(size); | |
240 | int idx, i, j; | |
241 | ||
242 | for (i = 0; i < nb_numa_nodes; i++) { | |
243 | for (j = 0; j < nb_numa_nodes; j++) { | |
244 | idx = (i * nb_numa_nodes + j) * 3; | |
245 | matrix[idx + 0] = cpu_to_be32(i); | |
246 | matrix[idx + 1] = cpu_to_be32(j); | |
247 | matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); | |
248 | } | |
249 | } | |
250 | ||
251 | qemu_fdt_add_subnode(fdt, "/distance-map"); | |
252 | qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", | |
253 | "numa-distance-map-v1"); | |
254 | qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | |
255 | matrix, size); | |
256 | g_free(matrix); | |
257 | } | |
06955739 PS |
258 | } |
259 | ||
055a7f2b | 260 | static void fdt_add_timer_nodes(const VirtMachineState *vms) |
f5fdcd6e | 261 | { |
156bc9a5 PM |
262 | /* On real hardware these interrupts are level-triggered. |
263 | * On KVM they were edge-triggered before host kernel version 4.4, | |
264 | * and level-triggered afterwards. | |
265 | * On emulated QEMU they are level-triggered. | |
266 | * | |
267 | * Getting the DTB info about them wrong is awkward for some | |
268 | * guest kernels: | |
269 | * pre-4.8 ignore the DT and leave the interrupt configured | |
270 | * with whatever the GIC reset value (or the bootloader) left it at | |
271 | * 4.8 before rc6 honour the incorrect data by programming it back | |
272 | * into the GIC, causing problems | |
273 | * 4.8rc6 and later ignore the DT and always write "level triggered" | |
274 | * into the GIC | |
275 | * | |
276 | * For backwards-compatibility, virt-2.8 and earlier will continue | |
277 | * to say these are edge-triggered, but later machines will report | |
278 | * the correct information. | |
f5fdcd6e | 279 | */ |
b32a9509 | 280 | ARMCPU *armcpu; |
156bc9a5 PM |
281 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
282 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
283 | ||
284 | if (vmc->claim_edge_triggered_timers) { | |
285 | irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; | |
286 | } | |
f5fdcd6e | 287 | |
055a7f2b | 288 | if (vms->gic_version == 2) { |
b92ad394 PF |
289 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, |
290 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
c8ef2bda | 291 | (1 << vms->smp_cpus) - 1); |
b92ad394 | 292 | } |
f5fdcd6e | 293 | |
c8ef2bda | 294 | qemu_fdt_add_subnode(vms->fdt, "/timer"); |
b32a9509 CF |
295 | |
296 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
297 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
298 | const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; | |
c8ef2bda | 299 | qemu_fdt_setprop(vms->fdt, "/timer", "compatible", |
b32a9509 CF |
300 | compat, sizeof(compat)); |
301 | } else { | |
c8ef2bda | 302 | qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", |
b32a9509 CF |
303 | "arm,armv7-timer"); |
304 | } | |
c8ef2bda PM |
305 | qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); |
306 | qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", | |
ee246400 SZ |
307 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, |
308 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, | |
309 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, | |
310 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); | |
f5fdcd6e PM |
311 | } |
312 | ||
c8ef2bda | 313 | static void fdt_add_cpu_nodes(const VirtMachineState *vms) |
f5fdcd6e PM |
314 | { |
315 | int cpu; | |
8d45c54d | 316 | int addr_cells = 1; |
4ccf5826 | 317 | const MachineState *ms = MACHINE(vms); |
8d45c54d PF |
318 | |
319 | /* | |
320 | * From Documentation/devicetree/bindings/arm/cpus.txt | |
321 | * On ARM v8 64-bit systems value should be set to 2, | |
322 | * that corresponds to the MPIDR_EL1 register size. | |
323 | * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
324 | * in the system, #address-cells can be set to 1, since | |
325 | * MPIDR_EL1[63:32] bits are not used for CPUs | |
326 | * identification. | |
327 | * | |
328 | * Here we actually don't know whether our system is 32- or 64-bit one. | |
329 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | |
330 | * at least one of them has Aff3 populated, we set #address-cells to 2. | |
331 | */ | |
c8ef2bda | 332 | for (cpu = 0; cpu < vms->smp_cpus; cpu++) { |
8d45c54d PF |
333 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); |
334 | ||
335 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | |
336 | addr_cells = 2; | |
337 | break; | |
338 | } | |
339 | } | |
f5fdcd6e | 340 | |
c8ef2bda PM |
341 | qemu_fdt_add_subnode(vms->fdt, "/cpus"); |
342 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); | |
343 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); | |
f5fdcd6e | 344 | |
c8ef2bda | 345 | for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { |
f5fdcd6e PM |
346 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
347 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
4ccf5826 | 348 | CPUState *cs = CPU(armcpu); |
f5fdcd6e | 349 | |
c8ef2bda PM |
350 | qemu_fdt_add_subnode(vms->fdt, nodename); |
351 | qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); | |
352 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | |
f5fdcd6e PM |
353 | armcpu->dtb_compatible); |
354 | ||
2013c566 PM |
355 | if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED |
356 | && vms->smp_cpus > 1) { | |
c8ef2bda | 357 | qemu_fdt_setprop_string(vms->fdt, nodename, |
f5fdcd6e PM |
358 | "enable-method", "psci"); |
359 | } | |
360 | ||
8d45c54d | 361 | if (addr_cells == 2) { |
c8ef2bda | 362 | qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", |
8d45c54d PF |
363 | armcpu->mp_affinity); |
364 | } else { | |
c8ef2bda | 365 | qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", |
8d45c54d PF |
366 | armcpu->mp_affinity); |
367 | } | |
368 | ||
4ccf5826 IM |
369 | if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { |
370 | qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", | |
371 | ms->possible_cpus->cpus[cs->cpu_index].props.node_id); | |
9695200a SZ |
372 | } |
373 | ||
f5fdcd6e PM |
374 | g_free(nodename); |
375 | } | |
376 | } | |
377 | ||
c8ef2bda | 378 | static void fdt_add_its_gic_node(VirtMachineState *vms) |
02f98731 | 379 | { |
bb2a3348 EA |
380 | char *nodename; |
381 | ||
c8ef2bda | 382 | vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); |
bb2a3348 EA |
383 | nodename = g_strdup_printf("/intc/its@%" PRIx64, |
384 | vms->memmap[VIRT_GIC_ITS].base); | |
385 | qemu_fdt_add_subnode(vms->fdt, nodename); | |
386 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | |
02f98731 | 387 | "arm,gic-v3-its"); |
bb2a3348 EA |
388 | qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); |
389 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
c8ef2bda PM |
390 | 2, vms->memmap[VIRT_GIC_ITS].base, |
391 | 2, vms->memmap[VIRT_GIC_ITS].size); | |
bb2a3348 EA |
392 | qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); |
393 | g_free(nodename); | |
02f98731 PF |
394 | } |
395 | ||
c8ef2bda | 396 | static void fdt_add_v2m_gic_node(VirtMachineState *vms) |
f5fdcd6e | 397 | { |
bb2a3348 EA |
398 | char *nodename; |
399 | ||
400 | nodename = g_strdup_printf("/intc/v2m@%" PRIx64, | |
401 | vms->memmap[VIRT_GIC_V2M].base); | |
c8ef2bda | 402 | vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); |
bb2a3348 EA |
403 | qemu_fdt_add_subnode(vms->fdt, nodename); |
404 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | |
bd204e63 | 405 | "arm,gic-v2m-frame"); |
bb2a3348 EA |
406 | qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); |
407 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
c8ef2bda PM |
408 | 2, vms->memmap[VIRT_GIC_V2M].base, |
409 | 2, vms->memmap[VIRT_GIC_V2M].size); | |
bb2a3348 EA |
410 | qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); |
411 | g_free(nodename); | |
bd204e63 | 412 | } |
f5fdcd6e | 413 | |
055a7f2b | 414 | static void fdt_add_gic_node(VirtMachineState *vms) |
bd204e63 | 415 | { |
bb2a3348 EA |
416 | char *nodename; |
417 | ||
c8ef2bda PM |
418 | vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); |
419 | qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); | |
420 | ||
bb2a3348 EA |
421 | nodename = g_strdup_printf("/intc@%" PRIx64, |
422 | vms->memmap[VIRT_GIC_DIST].base); | |
423 | qemu_fdt_add_subnode(vms->fdt, nodename); | |
424 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); | |
425 | qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); | |
426 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); | |
427 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); | |
428 | qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); | |
055a7f2b | 429 | if (vms->gic_version == 3) { |
f90747c4 EA |
430 | int nb_redist_regions = virt_gicv3_redist_region_count(vms); |
431 | ||
bb2a3348 | 432 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", |
b92ad394 | 433 | "arm,gic-v3"); |
f90747c4 | 434 | |
bb2a3348 | 435 | qemu_fdt_setprop_cell(vms->fdt, nodename, |
f90747c4 EA |
436 | "#redistributor-regions", nb_redist_regions); |
437 | ||
438 | if (nb_redist_regions == 1) { | |
bb2a3348 | 439 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
f90747c4 EA |
440 | 2, vms->memmap[VIRT_GIC_DIST].base, |
441 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
442 | 2, vms->memmap[VIRT_GIC_REDIST].base, | |
443 | 2, vms->memmap[VIRT_GIC_REDIST].size); | |
444 | } else { | |
bb2a3348 | 445 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
bf424a12 EA |
446 | 2, vms->memmap[VIRT_GIC_DIST].base, |
447 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
448 | 2, vms->memmap[VIRT_GIC_REDIST].base, | |
449 | 2, vms->memmap[VIRT_GIC_REDIST].size, | |
450 | 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, | |
451 | 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); | |
f90747c4 EA |
452 | } |
453 | ||
f29cacfb | 454 | if (vms->virt) { |
bb2a3348 | 455 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
55ef3233 | 456 | GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, |
f29cacfb PM |
457 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
458 | } | |
b92ad394 PF |
459 | } else { |
460 | /* 'cortex-a15-gic' means 'GIC v2' */ | |
bb2a3348 | 461 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", |
b92ad394 | 462 | "arm,cortex-a15-gic"); |
55ef3233 LM |
463 | if (!vms->virt) { |
464 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
465 | 2, vms->memmap[VIRT_GIC_DIST].base, | |
466 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
467 | 2, vms->memmap[VIRT_GIC_CPU].base, | |
468 | 2, vms->memmap[VIRT_GIC_CPU].size); | |
469 | } else { | |
470 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
471 | 2, vms->memmap[VIRT_GIC_DIST].base, | |
472 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
473 | 2, vms->memmap[VIRT_GIC_CPU].base, | |
474 | 2, vms->memmap[VIRT_GIC_CPU].size, | |
475 | 2, vms->memmap[VIRT_GIC_HYP].base, | |
476 | 2, vms->memmap[VIRT_GIC_HYP].size, | |
477 | 2, vms->memmap[VIRT_GIC_VCPU].base, | |
478 | 2, vms->memmap[VIRT_GIC_VCPU].size); | |
479 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", | |
480 | GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, | |
481 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
482 | } | |
b92ad394 PF |
483 | } |
484 | ||
bb2a3348 EA |
485 | qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); |
486 | g_free(nodename); | |
f5fdcd6e PM |
487 | } |
488 | ||
055a7f2b | 489 | static void fdt_add_pmu_nodes(const VirtMachineState *vms) |
01fe6b60 SZ |
490 | { |
491 | CPUState *cpu; | |
492 | ARMCPU *armcpu; | |
493 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
494 | ||
495 | CPU_FOREACH(cpu) { | |
496 | armcpu = ARM_CPU(cpu); | |
3f07cb2a | 497 | if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { |
01fe6b60 SZ |
498 | return; |
499 | } | |
3f07cb2a | 500 | if (kvm_enabled()) { |
b2bfe9f7 AJ |
501 | if (kvm_irqchip_in_kernel()) { |
502 | kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); | |
3f07cb2a | 503 | } |
b2bfe9f7 | 504 | kvm_arm_pmu_init(cpu); |
3f07cb2a | 505 | } |
01fe6b60 SZ |
506 | } |
507 | ||
055a7f2b | 508 | if (vms->gic_version == 2) { |
01fe6b60 SZ |
509 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, |
510 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
c8ef2bda | 511 | (1 << vms->smp_cpus) - 1); |
01fe6b60 SZ |
512 | } |
513 | ||
514 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
c8ef2bda | 515 | qemu_fdt_add_subnode(vms->fdt, "/pmu"); |
01fe6b60 SZ |
516 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { |
517 | const char compat[] = "arm,armv8-pmuv3"; | |
c8ef2bda | 518 | qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", |
01fe6b60 | 519 | compat, sizeof(compat)); |
c8ef2bda | 520 | qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", |
01fe6b60 SZ |
521 | GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); |
522 | } | |
523 | } | |
524 | ||
c8ef2bda | 525 | static void create_its(VirtMachineState *vms, DeviceState *gicdev) |
02f98731 PF |
526 | { |
527 | const char *itsclass = its_class_name(); | |
528 | DeviceState *dev; | |
529 | ||
530 | if (!itsclass) { | |
531 | /* Do nothing if not supported */ | |
532 | return; | |
533 | } | |
534 | ||
535 | dev = qdev_create(NULL, itsclass); | |
536 | ||
537 | object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", | |
538 | &error_abort); | |
539 | qdev_init_nofail(dev); | |
c8ef2bda | 540 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); |
02f98731 | 541 | |
c8ef2bda | 542 | fdt_add_its_gic_node(vms); |
02f98731 PF |
543 | } |
544 | ||
c8ef2bda | 545 | static void create_v2m(VirtMachineState *vms, qemu_irq *pic) |
bd204e63 CD |
546 | { |
547 | int i; | |
c8ef2bda | 548 | int irq = vms->irqmap[VIRT_GIC_V2M]; |
bd204e63 CD |
549 | DeviceState *dev; |
550 | ||
551 | dev = qdev_create(NULL, "arm-gicv2m"); | |
c8ef2bda | 552 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); |
bd204e63 CD |
553 | qdev_prop_set_uint32(dev, "base-spi", irq); |
554 | qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); | |
555 | qdev_init_nofail(dev); | |
556 | ||
557 | for (i = 0; i < NUM_GICV2M_SPIS; i++) { | |
558 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
559 | } | |
560 | ||
c8ef2bda | 561 | fdt_add_v2m_gic_node(vms); |
bd204e63 CD |
562 | } |
563 | ||
055a7f2b | 564 | static void create_gic(VirtMachineState *vms, qemu_irq *pic) |
64204743 | 565 | { |
cc7d44c2 | 566 | MachineState *ms = MACHINE(vms); |
b92ad394 | 567 | /* We create a standalone GIC */ |
64204743 PM |
568 | DeviceState *gicdev; |
569 | SysBusDevice *gicbusdev; | |
e6fbcbc4 | 570 | const char *gictype; |
055a7f2b | 571 | int type = vms->gic_version, i; |
cc7d44c2 | 572 | unsigned int smp_cpus = ms->smp.cpus; |
03d72fa1 | 573 | uint32_t nb_redist_regions = 0; |
64204743 | 574 | |
b92ad394 | 575 | gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); |
64204743 PM |
576 | |
577 | gicdev = qdev_create(NULL, gictype); | |
b92ad394 | 578 | qdev_prop_set_uint32(gicdev, "revision", type); |
64204743 PM |
579 | qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); |
580 | /* Note that the num-irq property counts both internal and external | |
581 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
582 | */ | |
583 | qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); | |
0e21f183 | 584 | if (!kvm_irqchip_in_kernel()) { |
0127937b | 585 | qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); |
0e21f183 | 586 | } |
1e575b66 EA |
587 | |
588 | if (type == 3) { | |
589 | uint32_t redist0_capacity = | |
590 | vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; | |
591 | uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); | |
592 | ||
03d72fa1 EA |
593 | nb_redist_regions = virt_gicv3_redist_region_count(vms); |
594 | ||
595 | qdev_prop_set_uint32(gicdev, "len-redist-region-count", | |
596 | nb_redist_regions); | |
1e575b66 | 597 | qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); |
03d72fa1 EA |
598 | |
599 | if (nb_redist_regions == 2) { | |
600 | uint32_t redist1_capacity = | |
bf424a12 | 601 | vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; |
03d72fa1 EA |
602 | |
603 | qdev_prop_set_uint32(gicdev, "redist-region-count[1]", | |
604 | MIN(smp_cpus - redist0_count, redist1_capacity)); | |
605 | } | |
55ef3233 LM |
606 | } else { |
607 | if (!kvm_irqchip_in_kernel()) { | |
608 | qdev_prop_set_bit(gicdev, "has-virtualization-extensions", | |
609 | vms->virt); | |
610 | } | |
1e575b66 | 611 | } |
64204743 PM |
612 | qdev_init_nofail(gicdev); |
613 | gicbusdev = SYS_BUS_DEVICE(gicdev); | |
c8ef2bda | 614 | sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); |
b92ad394 | 615 | if (type == 3) { |
c8ef2bda | 616 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); |
03d72fa1 | 617 | if (nb_redist_regions == 2) { |
bf424a12 EA |
618 | sysbus_mmio_map(gicbusdev, 2, |
619 | vms->memmap[VIRT_HIGH_GIC_REDIST2].base); | |
03d72fa1 | 620 | } |
b92ad394 | 621 | } else { |
c8ef2bda | 622 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); |
55ef3233 LM |
623 | if (vms->virt) { |
624 | sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); | |
625 | sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); | |
626 | } | |
b92ad394 | 627 | } |
64204743 | 628 | |
5454006a PM |
629 | /* Wire the outputs from each CPU's generic timer and the GICv3 |
630 | * maintenance interrupt signal to the appropriate GIC PPI inputs, | |
631 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | |
64204743 PM |
632 | */ |
633 | for (i = 0; i < smp_cpus; i++) { | |
634 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
0e3e858f | 635 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
a007b1f8 PM |
636 | int irq; |
637 | /* Mapping from the output timer irq lines from the CPU to the | |
638 | * GIC PPI inputs we use for the virt board. | |
64204743 | 639 | */ |
a007b1f8 PM |
640 | const int timer_irq[] = { |
641 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
642 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
643 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
644 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
645 | }; | |
646 | ||
647 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
648 | qdev_connect_gpio_out(cpudev, irq, | |
649 | qdev_get_gpio_in(gicdev, | |
650 | ppibase + timer_irq[irq])); | |
651 | } | |
64204743 | 652 | |
55ef3233 LM |
653 | if (type == 3) { |
654 | qemu_irq irq = qdev_get_gpio_in(gicdev, | |
655 | ppibase + ARCH_GIC_MAINT_IRQ); | |
656 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", | |
657 | 0, irq); | |
658 | } else if (vms->virt) { | |
659 | qemu_irq irq = qdev_get_gpio_in(gicdev, | |
660 | ppibase + ARCH_GIC_MAINT_IRQ); | |
661 | sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); | |
662 | } | |
663 | ||
07f48730 AJ |
664 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, |
665 | qdev_get_gpio_in(gicdev, ppibase | |
666 | + VIRTUAL_PMU_IRQ)); | |
5454006a | 667 | |
64204743 | 668 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
8e7b4ca0 GB |
669 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
670 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
5454006a PM |
671 | sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, |
672 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
673 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | |
674 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
64204743 PM |
675 | } |
676 | ||
677 | for (i = 0; i < NUM_IRQS; i++) { | |
678 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
679 | } | |
680 | ||
055a7f2b | 681 | fdt_add_gic_node(vms); |
bd204e63 | 682 | |
ccc11b02 | 683 | if (type == 3 && vms->its) { |
c8ef2bda | 684 | create_its(vms, gicdev); |
2231f69b | 685 | } else if (type == 2) { |
c8ef2bda | 686 | create_v2m(vms, pic); |
b92ad394 | 687 | } |
64204743 PM |
688 | } |
689 | ||
c8ef2bda | 690 | static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, |
0ec7b3e7 | 691 | MemoryRegion *mem, Chardev *chr) |
f5fdcd6e PM |
692 | { |
693 | char *nodename; | |
c8ef2bda PM |
694 | hwaddr base = vms->memmap[uart].base; |
695 | hwaddr size = vms->memmap[uart].size; | |
696 | int irq = vms->irqmap[uart]; | |
f5fdcd6e PM |
697 | const char compat[] = "arm,pl011\0arm,primecell"; |
698 | const char clocknames[] = "uartclk\0apb_pclk"; | |
3df708eb PM |
699 | DeviceState *dev = qdev_create(NULL, "pl011"); |
700 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
f5fdcd6e | 701 | |
9bbbf649 | 702 | qdev_prop_set_chr(dev, "chardev", chr); |
3df708eb PM |
703 | qdev_init_nofail(dev); |
704 | memory_region_add_subregion(mem, base, | |
705 | sysbus_mmio_get_region(s, 0)); | |
706 | sysbus_connect_irq(s, 0, pic[irq]); | |
f5fdcd6e PM |
707 | |
708 | nodename = g_strdup_printf("/pl011@%" PRIx64, base); | |
c8ef2bda | 709 | qemu_fdt_add_subnode(vms->fdt, nodename); |
f5fdcd6e | 710 | /* Note that we can't use setprop_string because of the embedded NUL */ |
c8ef2bda | 711 | qemu_fdt_setprop(vms->fdt, nodename, "compatible", |
f5fdcd6e | 712 | compat, sizeof(compat)); |
c8ef2bda | 713 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
f5fdcd6e | 714 | 2, base, 2, size); |
c8ef2bda | 715 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
f5fdcd6e | 716 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 717 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
c8ef2bda PM |
718 | qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", |
719 | vms->clock_phandle, vms->clock_phandle); | |
720 | qemu_fdt_setprop(vms->fdt, nodename, "clock-names", | |
f5fdcd6e | 721 | clocknames, sizeof(clocknames)); |
f022b8e9 | 722 | |
3df708eb | 723 | if (uart == VIRT_UART) { |
c8ef2bda | 724 | qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); |
3df708eb PM |
725 | } else { |
726 | /* Mark as not usable by the normal world */ | |
c8ef2bda PM |
727 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); |
728 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | |
fb23d693 JF |
729 | |
730 | qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); | |
731 | qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", | |
732 | nodename); | |
3df708eb PM |
733 | } |
734 | ||
f5fdcd6e PM |
735 | g_free(nodename); |
736 | } | |
737 | ||
c8ef2bda | 738 | static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) |
6e411af9 PM |
739 | { |
740 | char *nodename; | |
c8ef2bda PM |
741 | hwaddr base = vms->memmap[VIRT_RTC].base; |
742 | hwaddr size = vms->memmap[VIRT_RTC].size; | |
743 | int irq = vms->irqmap[VIRT_RTC]; | |
6e411af9 PM |
744 | const char compat[] = "arm,pl031\0arm,primecell"; |
745 | ||
746 | sysbus_create_simple("pl031", base, pic[irq]); | |
747 | ||
748 | nodename = g_strdup_printf("/pl031@%" PRIx64, base); | |
c8ef2bda PM |
749 | qemu_fdt_add_subnode(vms->fdt, nodename); |
750 | qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); | |
751 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
6e411af9 | 752 | 2, base, 2, size); |
c8ef2bda | 753 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
6e411af9 | 754 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 755 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
c8ef2bda PM |
756 | qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); |
757 | qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); | |
6e411af9 PM |
758 | g_free(nodename); |
759 | } | |
760 | ||
94f02c5e | 761 | static DeviceState *gpio_key_dev; |
4bedd849 SZ |
762 | static void virt_powerdown_req(Notifier *n, void *opaque) |
763 | { | |
764 | /* use gpio Pin 3 for power button event */ | |
94f02c5e | 765 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); |
4bedd849 SZ |
766 | } |
767 | ||
768 | static Notifier virt_system_powerdown_notifier = { | |
769 | .notify = virt_powerdown_req | |
770 | }; | |
771 | ||
c8ef2bda | 772 | static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) |
b0a3721e SZ |
773 | { |
774 | char *nodename; | |
94f02c5e | 775 | DeviceState *pl061_dev; |
c8ef2bda PM |
776 | hwaddr base = vms->memmap[VIRT_GPIO].base; |
777 | hwaddr size = vms->memmap[VIRT_GPIO].size; | |
778 | int irq = vms->irqmap[VIRT_GPIO]; | |
b0a3721e SZ |
779 | const char compat[] = "arm,pl061\0arm,primecell"; |
780 | ||
4bedd849 | 781 | pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); |
b0a3721e | 782 | |
c8ef2bda | 783 | uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); |
b0a3721e | 784 | nodename = g_strdup_printf("/pl061@%" PRIx64, base); |
c8ef2bda PM |
785 | qemu_fdt_add_subnode(vms->fdt, nodename); |
786 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
b0a3721e | 787 | 2, base, 2, size); |
c8ef2bda PM |
788 | qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); |
789 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); | |
790 | qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); | |
791 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", | |
b0a3721e SZ |
792 | GIC_FDT_IRQ_TYPE_SPI, irq, |
793 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
c8ef2bda PM |
794 | qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); |
795 | qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); | |
796 | qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); | |
3e6ebb64 | 797 | |
94f02c5e SZ |
798 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, |
799 | qdev_get_gpio_in(pl061_dev, 3)); | |
c8ef2bda PM |
800 | qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); |
801 | qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); | |
802 | qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); | |
803 | qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); | |
3e6ebb64 | 804 | |
c8ef2bda PM |
805 | qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); |
806 | qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", | |
3e6ebb64 | 807 | "label", "GPIO Key Poweroff"); |
c8ef2bda | 808 | qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", |
3e6ebb64 | 809 | KEY_POWER); |
c8ef2bda | 810 | qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", |
3e6ebb64 | 811 | "gpios", phandle, 3, 0); |
b0a3721e | 812 | |
4bedd849 SZ |
813 | /* connect powerdown request */ |
814 | qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); | |
815 | ||
b0a3721e SZ |
816 | g_free(nodename); |
817 | } | |
818 | ||
c8ef2bda | 819 | static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) |
f5fdcd6e PM |
820 | { |
821 | int i; | |
c8ef2bda | 822 | hwaddr size = vms->memmap[VIRT_MMIO].size; |
f5fdcd6e | 823 | |
587078f0 LE |
824 | /* We create the transports in forwards order. Since qbus_realize() |
825 | * prepends (not appends) new child buses, the incrementing loop below will | |
826 | * create a list of virtio-mmio buses with decreasing base addresses. | |
827 | * | |
828 | * When a -device option is processed from the command line, | |
829 | * qbus_find_recursive() picks the next free virtio-mmio bus in forwards | |
830 | * order. The upshot is that -device options in increasing command line | |
831 | * order are mapped to virtio-mmio buses with decreasing base addresses. | |
832 | * | |
833 | * When this code was originally written, that arrangement ensured that the | |
834 | * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to | |
835 | * the first -device on the command line. (The end-to-end order is a | |
836 | * function of this loop, qbus_realize(), qbus_find_recursive(), and the | |
837 | * guest kernel's name-to-address assignment strategy.) | |
838 | * | |
839 | * Meanwhile, the kernel's traversal seems to have been reversed; see eg. | |
840 | * the message, if not necessarily the code, of commit 70161ff336. | |
841 | * Therefore the loop now establishes the inverse of the original intent. | |
842 | * | |
843 | * Unfortunately, we can't counteract the kernel change by reversing the | |
844 | * loop; it would break existing command lines. | |
845 | * | |
846 | * In any case, the kernel makes no guarantee about the stability of | |
847 | * enumeration order of virtio devices (as demonstrated by it changing | |
848 | * between kernel versions). For reliable and stable identification | |
849 | * of disks users must use UUIDs or similar mechanisms. | |
f5fdcd6e PM |
850 | */ |
851 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
c8ef2bda PM |
852 | int irq = vms->irqmap[VIRT_MMIO] + i; |
853 | hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; | |
f5fdcd6e PM |
854 | |
855 | sysbus_create_simple("virtio-mmio", base, pic[irq]); | |
856 | } | |
857 | ||
587078f0 LE |
858 | /* We add dtb nodes in reverse order so that they appear in the finished |
859 | * device tree lowest address first. | |
860 | * | |
861 | * Note that this mapping is independent of the loop above. The previous | |
862 | * loop influences virtio device to virtio transport assignment, whereas | |
863 | * this loop controls how virtio transports are laid out in the dtb. | |
864 | */ | |
f5fdcd6e PM |
865 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
866 | char *nodename; | |
c8ef2bda PM |
867 | int irq = vms->irqmap[VIRT_MMIO] + i; |
868 | hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; | |
f5fdcd6e PM |
869 | |
870 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); | |
c8ef2bda PM |
871 | qemu_fdt_add_subnode(vms->fdt, nodename); |
872 | qemu_fdt_setprop_string(vms->fdt, nodename, | |
5a4348d1 | 873 | "compatible", "virtio,mmio"); |
c8ef2bda | 874 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
5a4348d1 | 875 | 2, base, 2, size); |
c8ef2bda | 876 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
5a4348d1 PC |
877 | GIC_FDT_IRQ_TYPE_SPI, irq, |
878 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
054bb7b2 | 879 | qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); |
f5fdcd6e PM |
880 | g_free(nodename); |
881 | } | |
882 | } | |
883 | ||
e0561e60 MA |
884 | #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) |
885 | ||
886 | static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, | |
887 | const char *name, | |
888 | const char *alias_prop_name) | |
acf82361 | 889 | { |
e0561e60 MA |
890 | /* |
891 | * Create a single flash device. We use the same parameters as | |
892 | * the flash devices on the Versatile Express board. | |
acf82361 | 893 | */ |
81c7db72 | 894 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); |
acf82361 | 895 | |
e0561e60 | 896 | qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); |
acf82361 PM |
897 | qdev_prop_set_uint8(dev, "width", 4); |
898 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 899 | qdev_prop_set_bit(dev, "big-endian", false); |
acf82361 PM |
900 | qdev_prop_set_uint16(dev, "id0", 0x89); |
901 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
902 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
903 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
904 | qdev_prop_set_string(dev, "name", name); | |
e0561e60 MA |
905 | object_property_add_child(OBJECT(vms), name, OBJECT(dev), |
906 | &error_abort); | |
907 | object_property_add_alias(OBJECT(vms), alias_prop_name, | |
908 | OBJECT(dev), "drive", &error_abort); | |
909 | return PFLASH_CFI01(dev); | |
910 | } | |
acf82361 | 911 | |
e0561e60 MA |
912 | static void virt_flash_create(VirtMachineState *vms) |
913 | { | |
914 | vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); | |
915 | vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); | |
916 | } | |
acf82361 | 917 | |
e0561e60 MA |
918 | static void virt_flash_map1(PFlashCFI01 *flash, |
919 | hwaddr base, hwaddr size, | |
920 | MemoryRegion *sysmem) | |
921 | { | |
922 | DeviceState *dev = DEVICE(flash); | |
acf82361 | 923 | |
e0561e60 MA |
924 | assert(size % VIRT_FLASH_SECTOR_SIZE == 0); |
925 | assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); | |
926 | qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); | |
927 | qdev_init_nofail(dev); | |
928 | ||
929 | memory_region_add_subregion(sysmem, base, | |
930 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), | |
931 | 0)); | |
16f4a8dc PM |
932 | } |
933 | ||
e0561e60 MA |
934 | static void virt_flash_map(VirtMachineState *vms, |
935 | MemoryRegion *sysmem, | |
936 | MemoryRegion *secure_sysmem) | |
16f4a8dc | 937 | { |
e0561e60 MA |
938 | /* |
939 | * Map two flash devices to fill the VIRT_FLASH space in the memmap. | |
738a5d9f PM |
940 | * sysmem is the system memory space. secure_sysmem is the secure view |
941 | * of the system, and the first flash device should be made visible only | |
942 | * there. The second flash device is visible to both secure and nonsecure. | |
943 | * If sysmem == secure_sysmem this means there is no separate Secure | |
944 | * address space and both flash devices are generally visible. | |
16f4a8dc | 945 | */ |
c8ef2bda PM |
946 | hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; |
947 | hwaddr flashbase = vms->memmap[VIRT_FLASH].base; | |
acf82361 | 948 | |
e0561e60 MA |
949 | virt_flash_map1(vms->flash[0], flashbase, flashsize, |
950 | secure_sysmem); | |
951 | virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, | |
952 | sysmem); | |
953 | } | |
954 | ||
955 | static void virt_flash_fdt(VirtMachineState *vms, | |
956 | MemoryRegion *sysmem, | |
957 | MemoryRegion *secure_sysmem) | |
958 | { | |
959 | hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; | |
960 | hwaddr flashbase = vms->memmap[VIRT_FLASH].base; | |
961 | char *nodename; | |
acf82361 | 962 | |
738a5d9f PM |
963 | if (sysmem == secure_sysmem) { |
964 | /* Report both flash devices as a single node in the DT */ | |
965 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
c8ef2bda PM |
966 | qemu_fdt_add_subnode(vms->fdt, nodename); |
967 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); | |
968 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
738a5d9f PM |
969 | 2, flashbase, 2, flashsize, |
970 | 2, flashbase + flashsize, 2, flashsize); | |
c8ef2bda | 971 | qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); |
738a5d9f PM |
972 | g_free(nodename); |
973 | } else { | |
e0561e60 MA |
974 | /* |
975 | * Report the devices as separate nodes so we can mark one as | |
738a5d9f PM |
976 | * only visible to the secure world. |
977 | */ | |
978 | nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); | |
c8ef2bda PM |
979 | qemu_fdt_add_subnode(vms->fdt, nodename); |
980 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); | |
981 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
738a5d9f | 982 | 2, flashbase, 2, flashsize); |
c8ef2bda PM |
983 | qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); |
984 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | |
985 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | |
738a5d9f PM |
986 | g_free(nodename); |
987 | ||
988 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
c8ef2bda PM |
989 | qemu_fdt_add_subnode(vms->fdt, nodename); |
990 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); | |
991 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
738a5d9f | 992 | 2, flashbase + flashsize, 2, flashsize); |
c8ef2bda | 993 | qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); |
738a5d9f PM |
994 | g_free(nodename); |
995 | } | |
acf82361 PM |
996 | } |
997 | ||
e0561e60 MA |
998 | static bool virt_firmware_init(VirtMachineState *vms, |
999 | MemoryRegion *sysmem, | |
1000 | MemoryRegion *secure_sysmem) | |
1001 | { | |
1002 | int i; | |
1003 | BlockBackend *pflash_blk0; | |
1004 | ||
1005 | /* Map legacy -drive if=pflash to machine properties */ | |
1006 | for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { | |
1007 | pflash_cfi01_legacy_drive(vms->flash[i], | |
1008 | drive_get(IF_PFLASH, 0, i)); | |
1009 | } | |
1010 | ||
1011 | virt_flash_map(vms, sysmem, secure_sysmem); | |
1012 | ||
1013 | pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); | |
1014 | ||
1015 | if (bios_name) { | |
1016 | char *fname; | |
1017 | MemoryRegion *mr; | |
1018 | int image_size; | |
1019 | ||
1020 | if (pflash_blk0) { | |
1021 | error_report("The contents of the first flash device may be " | |
1022 | "specified with -bios or with -drive if=pflash... " | |
1023 | "but you cannot use both options at once"); | |
1024 | exit(1); | |
1025 | } | |
1026 | ||
1027 | /* Fall back to -bios */ | |
1028 | ||
1029 | fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
1030 | if (!fname) { | |
1031 | error_report("Could not find ROM image '%s'", bios_name); | |
1032 | exit(1); | |
1033 | } | |
1034 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); | |
1035 | image_size = load_image_mr(fname, mr); | |
1036 | g_free(fname); | |
1037 | if (image_size < 0) { | |
1038 | error_report("Could not load ROM image '%s'", bios_name); | |
1039 | exit(1); | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | return pflash_blk0 || bios_name; | |
1044 | } | |
1045 | ||
af1f60a4 | 1046 | static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) |
578f3c7b | 1047 | { |
cc7d44c2 | 1048 | MachineState *ms = MACHINE(vms); |
c8ef2bda PM |
1049 | hwaddr base = vms->memmap[VIRT_FW_CFG].base; |
1050 | hwaddr size = vms->memmap[VIRT_FW_CFG].size; | |
5836d168 | 1051 | FWCfgState *fw_cfg; |
578f3c7b LE |
1052 | char *nodename; |
1053 | ||
5836d168 | 1054 | fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); |
cc7d44c2 | 1055 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); |
578f3c7b LE |
1056 | |
1057 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
c8ef2bda PM |
1058 | qemu_fdt_add_subnode(vms->fdt, nodename); |
1059 | qemu_fdt_setprop_string(vms->fdt, nodename, | |
578f3c7b | 1060 | "compatible", "qemu,fw-cfg-mmio"); |
c8ef2bda | 1061 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
578f3c7b | 1062 | 2, base, 2, size); |
14efdb5c | 1063 | qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); |
578f3c7b | 1064 | g_free(nodename); |
af1f60a4 | 1065 | return fw_cfg; |
578f3c7b LE |
1066 | } |
1067 | ||
c8ef2bda | 1068 | static void create_pcie_irq_map(const VirtMachineState *vms, |
9ac4ef77 | 1069 | uint32_t gic_phandle, |
4ab29b82 AG |
1070 | int first_irq, const char *nodename) |
1071 | { | |
1072 | int devfn, pin; | |
dfd90a87 | 1073 | uint32_t full_irq_map[4 * 4 * 10] = { 0 }; |
4ab29b82 AG |
1074 | uint32_t *irq_map = full_irq_map; |
1075 | ||
1076 | for (devfn = 0; devfn <= 0x18; devfn += 0x8) { | |
1077 | for (pin = 0; pin < 4; pin++) { | |
1078 | int irq_type = GIC_FDT_IRQ_TYPE_SPI; | |
1079 | int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); | |
1080 | int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
1081 | int i; | |
1082 | ||
1083 | uint32_t map[] = { | |
1084 | devfn << 8, 0, 0, /* devfn */ | |
1085 | pin + 1, /* PCI pin */ | |
dfd90a87 | 1086 | gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ |
4ab29b82 AG |
1087 | |
1088 | /* Convert map to big endian */ | |
dfd90a87 | 1089 | for (i = 0; i < 10; i++) { |
4ab29b82 AG |
1090 | irq_map[i] = cpu_to_be32(map[i]); |
1091 | } | |
dfd90a87 | 1092 | irq_map += 10; |
4ab29b82 AG |
1093 | } |
1094 | } | |
1095 | ||
c8ef2bda | 1096 | qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", |
4ab29b82 AG |
1097 | full_irq_map, sizeof(full_irq_map)); |
1098 | ||
c8ef2bda | 1099 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", |
4ab29b82 AG |
1100 | 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ |
1101 | 0x7 /* PCI irq */); | |
1102 | } | |
1103 | ||
584105ea PM |
1104 | static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, |
1105 | PCIBus *bus) | |
1106 | { | |
1107 | char *node; | |
1108 | const char compat[] = "arm,smmu-v3"; | |
1109 | int irq = vms->irqmap[VIRT_SMMU]; | |
1110 | int i; | |
1111 | hwaddr base = vms->memmap[VIRT_SMMU].base; | |
1112 | hwaddr size = vms->memmap[VIRT_SMMU].size; | |
1113 | const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; | |
1114 | DeviceState *dev; | |
1115 | ||
1116 | if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { | |
1117 | return; | |
1118 | } | |
1119 | ||
1120 | dev = qdev_create(NULL, "arm-smmuv3"); | |
1121 | ||
1122 | object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", | |
1123 | &error_abort); | |
1124 | qdev_init_nofail(dev); | |
1125 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | |
1126 | for (i = 0; i < NUM_SMMU_IRQS; i++) { | |
1127 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
1128 | } | |
1129 | ||
1130 | node = g_strdup_printf("/smmuv3@%" PRIx64, base); | |
1131 | qemu_fdt_add_subnode(vms->fdt, node); | |
1132 | qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); | |
1133 | qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); | |
1134 | ||
1135 | qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", | |
1136 | GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
1137 | GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
1138 | GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
1139 | GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
1140 | ||
1141 | qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, | |
1142 | sizeof(irq_names)); | |
1143 | ||
1144 | qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); | |
1145 | qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); | |
1146 | qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); | |
1147 | ||
1148 | qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); | |
1149 | ||
1150 | qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); | |
1151 | g_free(node); | |
1152 | } | |
1153 | ||
1154 | static void create_pcie(VirtMachineState *vms, qemu_irq *pic) | |
4ab29b82 | 1155 | { |
c8ef2bda PM |
1156 | hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; |
1157 | hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; | |
bf424a12 EA |
1158 | hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; |
1159 | hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; | |
c8ef2bda PM |
1160 | hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; |
1161 | hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; | |
601d626d | 1162 | hwaddr base_ecam, size_ecam; |
6a1f001b | 1163 | hwaddr base = base_mmio; |
601d626d | 1164 | int nr_pcie_buses; |
c8ef2bda | 1165 | int irq = vms->irqmap[VIRT_PCIE]; |
4ab29b82 AG |
1166 | MemoryRegion *mmio_alias; |
1167 | MemoryRegion *mmio_reg; | |
1168 | MemoryRegion *ecam_alias; | |
1169 | MemoryRegion *ecam_reg; | |
1170 | DeviceState *dev; | |
1171 | char *nodename; | |
601d626d | 1172 | int i, ecam_id; |
fea9b3ca | 1173 | PCIHostState *pci; |
4ab29b82 | 1174 | |
4ab29b82 AG |
1175 | dev = qdev_create(NULL, TYPE_GPEX_HOST); |
1176 | qdev_init_nofail(dev); | |
1177 | ||
601d626d EA |
1178 | ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); |
1179 | base_ecam = vms->memmap[ecam_id].base; | |
1180 | size_ecam = vms->memmap[ecam_id].size; | |
1181 | nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
4ab29b82 AG |
1182 | /* Map only the first size_ecam bytes of ECAM space */ |
1183 | ecam_alias = g_new0(MemoryRegion, 1); | |
1184 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
1185 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
1186 | ecam_reg, 0, size_ecam); | |
1187 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
1188 | ||
1189 | /* Map the MMIO window into system address space so as to expose | |
1190 | * the section of PCI MMIO space which starts at the same base address | |
1191 | * (ie 1:1 mapping for that part of PCI MMIO space visible through | |
1192 | * the window). | |
1193 | */ | |
1194 | mmio_alias = g_new0(MemoryRegion, 1); | |
1195 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
1196 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
1197 | mmio_reg, base_mmio, size_mmio); | |
1198 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
1199 | ||
0127937b | 1200 | if (vms->highmem) { |
5125f9cd PF |
1201 | /* Map high MMIO space */ |
1202 | MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); | |
1203 | ||
1204 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
1205 | mmio_reg, base_mmio_high, size_mmio_high); | |
1206 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
1207 | high_mmio_alias); | |
1208 | } | |
1209 | ||
4ab29b82 | 1210 | /* Map IO port space */ |
6a1f001b | 1211 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
4ab29b82 AG |
1212 | |
1213 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
1214 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
c9bb8e16 | 1215 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); |
4ab29b82 AG |
1216 | } |
1217 | ||
fea9b3ca AK |
1218 | pci = PCI_HOST_BRIDGE(dev); |
1219 | if (pci->bus) { | |
1220 | for (i = 0; i < nb_nics; i++) { | |
1221 | NICInfo *nd = &nd_table[i]; | |
1222 | ||
1223 | if (!nd->model) { | |
1224 | nd->model = g_strdup("virtio"); | |
1225 | } | |
1226 | ||
1227 | pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); | |
1228 | } | |
1229 | } | |
1230 | ||
4ab29b82 | 1231 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); |
c8ef2bda PM |
1232 | qemu_fdt_add_subnode(vms->fdt, nodename); |
1233 | qemu_fdt_setprop_string(vms->fdt, nodename, | |
4ab29b82 | 1234 | "compatible", "pci-host-ecam-generic"); |
c8ef2bda PM |
1235 | qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); |
1236 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); | |
1237 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); | |
6d9c1b8d | 1238 | qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); |
c8ef2bda | 1239 | qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, |
4ab29b82 | 1240 | nr_pcie_buses - 1); |
c8ef2bda | 1241 | qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); |
4ab29b82 | 1242 | |
c8ef2bda PM |
1243 | if (vms->msi_phandle) { |
1244 | qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", | |
1245 | vms->msi_phandle); | |
b92ad394 | 1246 | } |
bd204e63 | 1247 | |
c8ef2bda | 1248 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
4ab29b82 | 1249 | 2, base_ecam, 2, size_ecam); |
5125f9cd | 1250 | |
0127937b | 1251 | if (vms->highmem) { |
c8ef2bda | 1252 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", |
5125f9cd PF |
1253 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
1254 | 2, base_pio, 2, size_pio, | |
1255 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1256 | 2, base_mmio, 2, size_mmio, | |
1257 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
1258 | 2, base_mmio_high, | |
1259 | 2, base_mmio_high, 2, size_mmio_high); | |
1260 | } else { | |
c8ef2bda | 1261 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", |
5125f9cd PF |
1262 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
1263 | 2, base_pio, 2, size_pio, | |
1264 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1265 | 2, base_mmio, 2, size_mmio); | |
1266 | } | |
4ab29b82 | 1267 | |
c8ef2bda PM |
1268 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); |
1269 | create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); | |
4ab29b82 | 1270 | |
584105ea PM |
1271 | if (vms->iommu) { |
1272 | vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); | |
1273 | ||
1274 | create_smmu(vms, pic, pci->bus); | |
1275 | ||
1276 | qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", | |
1277 | 0x0, vms->iommu_phandle, 0x0, 0x10000); | |
1278 | } | |
1279 | ||
4ab29b82 AG |
1280 | g_free(nodename); |
1281 | } | |
1282 | ||
c8ef2bda | 1283 | static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) |
5f7a5a0e EA |
1284 | { |
1285 | DeviceState *dev; | |
1286 | SysBusDevice *s; | |
1287 | int i; | |
5f7a5a0e EA |
1288 | MemoryRegion *sysmem = get_system_memory(); |
1289 | ||
5f7a5a0e EA |
1290 | dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); |
1291 | dev->id = TYPE_PLATFORM_BUS_DEVICE; | |
3b77f6c3 IM |
1292 | qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); |
1293 | qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); | |
5f7a5a0e | 1294 | qdev_init_nofail(dev); |
a3fc8396 | 1295 | vms->platform_bus_dev = dev; |
5f7a5a0e | 1296 | |
3b77f6c3 IM |
1297 | s = SYS_BUS_DEVICE(dev); |
1298 | for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { | |
1299 | int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; | |
5f7a5a0e EA |
1300 | sysbus_connect_irq(s, i, pic[irqn]); |
1301 | } | |
1302 | ||
1303 | memory_region_add_subregion(sysmem, | |
3b77f6c3 | 1304 | vms->memmap[VIRT_PLATFORM_BUS].base, |
5f7a5a0e EA |
1305 | sysbus_mmio_get_region(s, 0)); |
1306 | } | |
1307 | ||
c8ef2bda | 1308 | static void create_secure_ram(VirtMachineState *vms, |
9ac4ef77 | 1309 | MemoryRegion *secure_sysmem) |
83ec1923 PM |
1310 | { |
1311 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
1312 | char *nodename; | |
c8ef2bda PM |
1313 | hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; |
1314 | hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; | |
83ec1923 | 1315 | |
98a99ce0 PM |
1316 | memory_region_init_ram(secram, NULL, "virt.secure-ram", size, |
1317 | &error_fatal); | |
83ec1923 PM |
1318 | memory_region_add_subregion(secure_sysmem, base, secram); |
1319 | ||
1320 | nodename = g_strdup_printf("/secram@%" PRIx64, base); | |
c8ef2bda PM |
1321 | qemu_fdt_add_subnode(vms->fdt, nodename); |
1322 | qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); | |
1323 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); | |
1324 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | |
1325 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | |
83ec1923 PM |
1326 | |
1327 | g_free(nodename); | |
1328 | } | |
1329 | ||
f5fdcd6e PM |
1330 | static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
1331 | { | |
9ac4ef77 PM |
1332 | const VirtMachineState *board = container_of(binfo, VirtMachineState, |
1333 | bootinfo); | |
f5fdcd6e PM |
1334 | |
1335 | *fdt_size = board->fdt_size; | |
1336 | return board->fdt; | |
1337 | } | |
1338 | ||
e9a8e474 | 1339 | static void virt_build_smbios(VirtMachineState *vms) |
c30e1565 | 1340 | { |
dfadc3bf WH |
1341 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
1342 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
c30e1565 WH |
1343 | uint8_t *smbios_tables, *smbios_anchor; |
1344 | size_t smbios_tables_len, smbios_anchor_len; | |
bab27ea2 | 1345 | const char *product = "QEMU Virtual Machine"; |
c30e1565 | 1346 | |
bab27ea2 AJ |
1347 | if (kvm_enabled()) { |
1348 | product = "KVM Virtual Machine"; | |
1349 | } | |
1350 | ||
1351 | smbios_set_defaults("QEMU", product, | |
dfadc3bf WH |
1352 | vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, |
1353 | true, SMBIOS_ENTRY_POINT_30); | |
c30e1565 | 1354 | |
a0628599 | 1355 | smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, |
c30e1565 WH |
1356 | &smbios_anchor, &smbios_anchor_len); |
1357 | ||
1358 | if (smbios_anchor) { | |
af1f60a4 | 1359 | fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", |
c30e1565 | 1360 | smbios_tables, smbios_tables_len); |
af1f60a4 | 1361 | fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", |
c30e1565 WH |
1362 | smbios_anchor, smbios_anchor_len); |
1363 | } | |
1364 | } | |
1365 | ||
d7c2e2db | 1366 | static |
054f4dc9 | 1367 | void virt_machine_done(Notifier *notifier, void *data) |
d7c2e2db | 1368 | { |
054f4dc9 AJ |
1369 | VirtMachineState *vms = container_of(notifier, VirtMachineState, |
1370 | machine_done); | |
3b77f6c3 IM |
1371 | ARMCPU *cpu = ARM_CPU(first_cpu); |
1372 | struct arm_boot_info *info = &vms->bootinfo; | |
1373 | AddressSpace *as = arm_boot_address_space(cpu, info); | |
1374 | ||
1375 | /* | |
1376 | * If the user provided a dtb, we assume the dynamic sysbus nodes | |
1377 | * already are integrated there. This corresponds to a use case where | |
1378 | * the dynamic sysbus nodes are complex and their generation is not yet | |
1379 | * supported. In that case the user can take charge of the guest dt | |
1380 | * while qemu takes charge of the qom stuff. | |
1381 | */ | |
1382 | if (info->dtb_filename == NULL) { | |
1383 | platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", | |
1384 | vms->memmap[VIRT_PLATFORM_BUS].base, | |
1385 | vms->memmap[VIRT_PLATFORM_BUS].size, | |
1386 | vms->irqmap[VIRT_PLATFORM_BUS]); | |
1387 | } | |
1388 | if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { | |
1389 | exit(1); | |
1390 | } | |
054f4dc9 | 1391 | |
e9a8e474 AJ |
1392 | virt_acpi_setup(vms); |
1393 | virt_build_smbios(vms); | |
d7c2e2db SZ |
1394 | } |
1395 | ||
46de5913 IM |
1396 | static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) |
1397 | { | |
1398 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; | |
1399 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
1400 | ||
1401 | if (!vmc->disallow_affinity_adjustment) { | |
1402 | /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the | |
1403 | * GIC's target-list limitations. 32-bit KVM hosts currently | |
1404 | * always create clusters of 4 CPUs, but that is expected to | |
1405 | * change when they gain support for gicv3. When KVM is enabled | |
1406 | * it will override the changes we make here, therefore our | |
1407 | * purposes are to make TCG consistent (with 64-bit KVM hosts) | |
1408 | * and to improve SGI efficiency. | |
1409 | */ | |
1410 | if (vms->gic_version == 3) { | |
1411 | clustersz = GICV3_TARGETLIST_BITS; | |
1412 | } else { | |
1413 | clustersz = GIC_TARGETLIST_BITS; | |
1414 | } | |
1415 | } | |
1416 | return arm_cpu_mp_affinity(idx, clustersz); | |
1417 | } | |
1418 | ||
350a9c9e EA |
1419 | static void virt_set_memmap(VirtMachineState *vms) |
1420 | { | |
957e32cf EA |
1421 | MachineState *ms = MACHINE(vms); |
1422 | hwaddr base, device_memory_base, device_memory_size; | |
350a9c9e EA |
1423 | int i; |
1424 | ||
1425 | vms->memmap = extended_memmap; | |
1426 | ||
1427 | for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { | |
1428 | vms->memmap[i] = base_memmap[i]; | |
1429 | } | |
1430 | ||
957e32cf EA |
1431 | if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1432 | error_report("unsupported number of memory slots: %"PRIu64, | |
1433 | ms->ram_slots); | |
1434 | exit(EXIT_FAILURE); | |
1435 | } | |
1436 | ||
1437 | /* | |
1438 | * We compute the base of the high IO region depending on the | |
1439 | * amount of initial and device memory. The device memory start/size | |
1440 | * is aligned on 1GiB. We never put the high IO region below 256GiB | |
1441 | * so that if maxram_size is < 255GiB we keep the legacy memory map. | |
1442 | * The device region size assumes 1GiB page max alignment per slot. | |
1443 | */ | |
1444 | device_memory_base = | |
1445 | ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); | |
1446 | device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; | |
1447 | ||
1448 | /* Base address of the high IO region */ | |
1449 | base = device_memory_base + ROUND_UP(device_memory_size, GiB); | |
1450 | if (base < device_memory_base) { | |
1451 | error_report("maxmem/slots too huge"); | |
1452 | exit(EXIT_FAILURE); | |
1453 | } | |
1454 | if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { | |
1455 | base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; | |
1456 | } | |
350a9c9e EA |
1457 | |
1458 | for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | |
1459 | hwaddr size = extended_memmap[i].size; | |
1460 | ||
1461 | base = ROUND_UP(base, size); | |
1462 | vms->memmap[i].base = base; | |
1463 | vms->memmap[i].size = size; | |
1464 | base += size; | |
1465 | } | |
957e32cf EA |
1466 | vms->highest_gpa = base - 1; |
1467 | if (device_memory_size > 0) { | |
1468 | ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); | |
1469 | ms->device_memory->base = device_memory_base; | |
1470 | memory_region_init(&ms->device_memory->mr, OBJECT(vms), | |
1471 | "device-memory", device_memory_size); | |
1472 | } | |
350a9c9e EA |
1473 | } |
1474 | ||
3ef96221 | 1475 | static void machvirt_init(MachineState *machine) |
f5fdcd6e | 1476 | { |
e5a5604f | 1477 | VirtMachineState *vms = VIRT_MACHINE(machine); |
95eb49c8 | 1478 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); |
17d3d0e2 IM |
1479 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1480 | const CPUArchIdList *possible_cpus; | |
f5fdcd6e PM |
1481 | qemu_irq pic[NUM_IRQS]; |
1482 | MemoryRegion *sysmem = get_system_memory(); | |
3df708eb | 1483 | MemoryRegion *secure_sysmem = NULL; |
7ea686f5 | 1484 | int n, virt_max_cpus; |
f5fdcd6e | 1485 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
e0561e60 | 1486 | bool firmware_loaded; |
17ec075a | 1487 | bool aarch64 = true; |
cc7d44c2 LX |
1488 | unsigned int smp_cpus = machine->smp.cpus; |
1489 | unsigned int max_cpus = machine->smp.max_cpus; | |
f5fdcd6e | 1490 | |
c9650222 EA |
1491 | /* |
1492 | * In accelerated mode, the memory map is computed earlier in kvm_type() | |
1493 | * to create a VM with the right number of IPA bits. | |
1494 | */ | |
1495 | if (!vms->memmap) { | |
1496 | virt_set_memmap(vms); | |
1497 | } | |
350a9c9e | 1498 | |
b92ad394 PF |
1499 | /* We can probe only here because during property set |
1500 | * KVM is not available yet | |
1501 | */ | |
dc16538a PM |
1502 | if (vms->gic_version <= 0) { |
1503 | /* "host" or "max" */ | |
0bf8039d | 1504 | if (!kvm_enabled()) { |
dc16538a PM |
1505 | if (vms->gic_version == 0) { |
1506 | error_report("gic-version=host requires KVM"); | |
1507 | exit(1); | |
1508 | } else { | |
1509 | /* "max": currently means 3 for TCG */ | |
1510 | vms->gic_version = 3; | |
1511 | } | |
1512 | } else { | |
1513 | vms->gic_version = kvm_arm_vgic_probe(); | |
1514 | if (!vms->gic_version) { | |
1515 | error_report( | |
1516 | "Unable to determine GIC version supported by host"); | |
1517 | exit(1); | |
1518 | } | |
b92ad394 PF |
1519 | } |
1520 | } | |
1521 | ||
ba1ba5cc IM |
1522 | if (!cpu_type_valid(machine->cpu_type)) { |
1523 | error_report("mach-virt: CPU type %s not supported", machine->cpu_type); | |
f5fdcd6e PM |
1524 | exit(1); |
1525 | } | |
1526 | ||
e0561e60 MA |
1527 | if (vms->secure) { |
1528 | if (kvm_enabled()) { | |
1529 | error_report("mach-virt: KVM does not support Security extensions"); | |
1530 | exit(1); | |
1531 | } | |
1532 | ||
1533 | /* | |
1534 | * The Secure view of the world is the same as the NonSecure, | |
1535 | * but with a few extra devices. Create it as a container region | |
1536 | * containing the system memory at low priority; any secure-only | |
1537 | * devices go in at higher priority and take precedence. | |
1538 | */ | |
1539 | secure_sysmem = g_new(MemoryRegion, 1); | |
1540 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", | |
1541 | UINT64_MAX); | |
1542 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
1543 | } | |
1544 | ||
1545 | firmware_loaded = virt_firmware_init(vms, sysmem, | |
1546 | secure_sysmem ?: sysmem); | |
1547 | ||
4824a61a PM |
1548 | /* If we have an EL3 boot ROM then the assumption is that it will |
1549 | * implement PSCI itself, so disable QEMU's internal implementation | |
1550 | * so it doesn't get in the way. Instead of starting secondary | |
1551 | * CPUs in PSCI powerdown state we will start them all running and | |
1552 | * let the boot ROM sort them out. | |
f29cacfb PM |
1553 | * The usual case is that we do use QEMU's PSCI implementation; |
1554 | * if the guest has EL2 then we will use SMC as the conduit, | |
1555 | * and otherwise we will use HVC (for backwards compatibility and | |
1556 | * because if we're using KVM then we must use HVC). | |
4824a61a | 1557 | */ |
2013c566 PM |
1558 | if (vms->secure && firmware_loaded) { |
1559 | vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | |
f29cacfb PM |
1560 | } else if (vms->virt) { |
1561 | vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; | |
2013c566 PM |
1562 | } else { |
1563 | vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; | |
1564 | } | |
4824a61a | 1565 | |
4b280b72 AJ |
1566 | /* The maximum number of CPUs depends on the GIC version, or on how |
1567 | * many redistributors we can fit into the memory map. | |
1568 | */ | |
055a7f2b | 1569 | if (vms->gic_version == 3) { |
bf424a12 EA |
1570 | virt_max_cpus = |
1571 | vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; | |
1572 | virt_max_cpus += | |
1573 | vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; | |
4b280b72 | 1574 | } else { |
7ea686f5 | 1575 | virt_max_cpus = GIC_NCPU; |
4b280b72 AJ |
1576 | } |
1577 | ||
7ea686f5 | 1578 | if (max_cpus > virt_max_cpus) { |
4b280b72 AJ |
1579 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " |
1580 | "supported by machine 'mach-virt' (%d)", | |
7ea686f5 | 1581 | max_cpus, virt_max_cpus); |
4b280b72 AJ |
1582 | exit(1); |
1583 | } | |
1584 | ||
c8ef2bda | 1585 | vms->smp_cpus = smp_cpus; |
f5fdcd6e | 1586 | |
f29cacfb PM |
1587 | if (vms->virt && kvm_enabled()) { |
1588 | error_report("mach-virt: KVM does not support providing " | |
1589 | "Virtualization extensions to the guest CPU"); | |
1590 | exit(1); | |
1591 | } | |
1592 | ||
c8ef2bda | 1593 | create_fdt(vms); |
f5fdcd6e | 1594 | |
17d3d0e2 IM |
1595 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
1596 | for (n = 0; n < possible_cpus->len; n++) { | |
1597 | Object *cpuobj; | |
d9c34f9c | 1598 | CPUState *cs; |
46de5913 | 1599 | |
17d3d0e2 IM |
1600 | if (n >= smp_cpus) { |
1601 | break; | |
1602 | } | |
1603 | ||
d342eb76 | 1604 | cpuobj = object_new(possible_cpus->cpus[n].type); |
17d3d0e2 | 1605 | object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, |
46de5913 | 1606 | "mp-affinity", NULL); |
f313369f | 1607 | |
d9c34f9c IM |
1608 | cs = CPU(cpuobj); |
1609 | cs->cpu_index = n; | |
1610 | ||
a0ceb640 IM |
1611 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), |
1612 | &error_fatal); | |
bd4c1bfe | 1613 | |
17ec075a EA |
1614 | aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); |
1615 | ||
e5a5604f GB |
1616 | if (!vms->secure) { |
1617 | object_property_set_bool(cpuobj, false, "has_el3", NULL); | |
1618 | } | |
1619 | ||
f29cacfb | 1620 | if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { |
c25bd18a PM |
1621 | object_property_set_bool(cpuobj, false, "has_el2", NULL); |
1622 | } | |
1623 | ||
2013c566 PM |
1624 | if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { |
1625 | object_property_set_int(cpuobj, vms->psci_conduit, | |
4824a61a | 1626 | "psci-conduit", NULL); |
211b0169 | 1627 | |
4824a61a PM |
1628 | /* Secondary CPUs start in PSCI powered-down state */ |
1629 | if (n > 0) { | |
1630 | object_property_set_bool(cpuobj, true, | |
1631 | "start-powered-off", NULL); | |
1632 | } | |
f5fdcd6e | 1633 | } |
ba750085 | 1634 | |
1141d1eb WH |
1635 | if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { |
1636 | object_property_set_bool(cpuobj, false, "pmu", NULL); | |
1637 | } | |
1638 | ||
ba750085 | 1639 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { |
c8ef2bda | 1640 | object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, |
ba750085 PM |
1641 | "reset-cbar", &error_abort); |
1642 | } | |
1643 | ||
1d939a68 PM |
1644 | object_property_set_link(cpuobj, OBJECT(sysmem), "memory", |
1645 | &error_abort); | |
3df708eb PM |
1646 | if (vms->secure) { |
1647 | object_property_set_link(cpuobj, OBJECT(secure_sysmem), | |
1648 | "secure-memory", &error_abort); | |
1649 | } | |
1d939a68 | 1650 | |
c88bc3e0 | 1651 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
dbb74759 | 1652 | object_unref(cpuobj); |
f5fdcd6e | 1653 | } |
055a7f2b | 1654 | fdt_add_timer_nodes(vms); |
c8ef2bda | 1655 | fdt_add_cpu_nodes(vms); |
f5fdcd6e | 1656 | |
2ba956cc EA |
1657 | if (!kvm_enabled()) { |
1658 | ARMCPU *cpu = ARM_CPU(first_cpu); | |
1659 | bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); | |
1660 | ||
1661 | if (aarch64 && vms->highmem) { | |
1662 | int requested_pa_size, pamax = arm_pamax(cpu); | |
1663 | ||
1664 | requested_pa_size = 64 - clz64(vms->highest_gpa); | |
1665 | if (pamax < requested_pa_size) { | |
1666 | error_report("VCPU supports less PA bits (%d) than requested " | |
1667 | "by the memory map (%d)", pamax, requested_pa_size); | |
1668 | exit(1); | |
1669 | } | |
1670 | } | |
1671 | } | |
1672 | ||
c8623c02 DM |
1673 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", |
1674 | machine->ram_size); | |
c8ef2bda | 1675 | memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); |
957e32cf EA |
1676 | if (machine->device_memory) { |
1677 | memory_region_add_subregion(sysmem, machine->device_memory->base, | |
1678 | &machine->device_memory->mr); | |
1679 | } | |
f5fdcd6e | 1680 | |
80734cbd | 1681 | virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); |
acf82361 | 1682 | |
055a7f2b | 1683 | create_gic(vms, pic); |
f5fdcd6e | 1684 | |
055a7f2b | 1685 | fdt_add_pmu_nodes(vms); |
01fe6b60 | 1686 | |
9bca0edb | 1687 | create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); |
3df708eb PM |
1688 | |
1689 | if (vms->secure) { | |
c8ef2bda | 1690 | create_secure_ram(vms, secure_sysmem); |
9bca0edb | 1691 | create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); |
3df708eb | 1692 | } |
f5fdcd6e | 1693 | |
17ec075a EA |
1694 | vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); |
1695 | ||
c8ef2bda | 1696 | create_rtc(vms, pic); |
6e411af9 | 1697 | |
0127937b | 1698 | create_pcie(vms, pic); |
4ab29b82 | 1699 | |
c8ef2bda | 1700 | create_gpio(vms, pic); |
b0a3721e | 1701 | |
f5fdcd6e PM |
1702 | /* Create mmio transports, so the user can create virtio backends |
1703 | * (which will be automatically plugged in to the transports). If | |
1704 | * no backend is created the transport will just sit harmlessly idle. | |
1705 | */ | |
c8ef2bda | 1706 | create_virtio_devices(vms, pic); |
f5fdcd6e | 1707 | |
af1f60a4 AJ |
1708 | vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); |
1709 | rom_set_fw(vms->fw_cfg); | |
d7c2e2db | 1710 | |
3b77f6c3 | 1711 | create_platform_bus(vms, pic); |
578f3c7b | 1712 | |
c8ef2bda PM |
1713 | vms->bootinfo.ram_size = machine->ram_size; |
1714 | vms->bootinfo.kernel_filename = machine->kernel_filename; | |
1715 | vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; | |
1716 | vms->bootinfo.initrd_filename = machine->initrd_filename; | |
1717 | vms->bootinfo.nb_cpus = smp_cpus; | |
1718 | vms->bootinfo.board_id = -1; | |
1719 | vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; | |
1720 | vms->bootinfo.get_dtb = machvirt_dtb; | |
3b77f6c3 | 1721 | vms->bootinfo.skip_dtb_autoload = true; |
c8ef2bda PM |
1722 | vms->bootinfo.firmware_loaded = firmware_loaded; |
1723 | arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); | |
5f7a5a0e | 1724 | |
3b77f6c3 IM |
1725 | vms->machine_done.notify = virt_machine_done; |
1726 | qemu_add_machine_init_done_notifier(&vms->machine_done); | |
f5fdcd6e PM |
1727 | } |
1728 | ||
083a5890 GB |
1729 | static bool virt_get_secure(Object *obj, Error **errp) |
1730 | { | |
1731 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1732 | ||
1733 | return vms->secure; | |
1734 | } | |
1735 | ||
1736 | static void virt_set_secure(Object *obj, bool value, Error **errp) | |
1737 | { | |
1738 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1739 | ||
1740 | vms->secure = value; | |
1741 | } | |
1742 | ||
f29cacfb PM |
1743 | static bool virt_get_virt(Object *obj, Error **errp) |
1744 | { | |
1745 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1746 | ||
1747 | return vms->virt; | |
1748 | } | |
1749 | ||
1750 | static void virt_set_virt(Object *obj, bool value, Error **errp) | |
1751 | { | |
1752 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1753 | ||
1754 | vms->virt = value; | |
1755 | } | |
1756 | ||
5125f9cd PF |
1757 | static bool virt_get_highmem(Object *obj, Error **errp) |
1758 | { | |
1759 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1760 | ||
1761 | return vms->highmem; | |
1762 | } | |
1763 | ||
1764 | static void virt_set_highmem(Object *obj, bool value, Error **errp) | |
1765 | { | |
1766 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1767 | ||
1768 | vms->highmem = value; | |
1769 | } | |
1770 | ||
ccc11b02 EA |
1771 | static bool virt_get_its(Object *obj, Error **errp) |
1772 | { | |
1773 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1774 | ||
1775 | return vms->its; | |
1776 | } | |
1777 | ||
1778 | static void virt_set_its(Object *obj, bool value, Error **errp) | |
1779 | { | |
1780 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1781 | ||
1782 | vms->its = value; | |
1783 | } | |
1784 | ||
b92ad394 PF |
1785 | static char *virt_get_gic_version(Object *obj, Error **errp) |
1786 | { | |
1787 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1788 | const char *val = vms->gic_version == 3 ? "3" : "2"; | |
1789 | ||
1790 | return g_strdup(val); | |
1791 | } | |
1792 | ||
1793 | static void virt_set_gic_version(Object *obj, const char *value, Error **errp) | |
1794 | { | |
1795 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1796 | ||
1797 | if (!strcmp(value, "3")) { | |
1798 | vms->gic_version = 3; | |
1799 | } else if (!strcmp(value, "2")) { | |
1800 | vms->gic_version = 2; | |
1801 | } else if (!strcmp(value, "host")) { | |
1802 | vms->gic_version = 0; /* Will probe later */ | |
dc16538a PM |
1803 | } else if (!strcmp(value, "max")) { |
1804 | vms->gic_version = -1; /* Will probe later */ | |
b92ad394 | 1805 | } else { |
7b55044f | 1806 | error_setg(errp, "Invalid gic-version value"); |
dc16538a | 1807 | error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); |
b92ad394 PF |
1808 | } |
1809 | } | |
1810 | ||
e24e3454 EA |
1811 | static char *virt_get_iommu(Object *obj, Error **errp) |
1812 | { | |
1813 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1814 | ||
1815 | switch (vms->iommu) { | |
1816 | case VIRT_IOMMU_NONE: | |
1817 | return g_strdup("none"); | |
1818 | case VIRT_IOMMU_SMMUV3: | |
1819 | return g_strdup("smmuv3"); | |
1820 | default: | |
1821 | g_assert_not_reached(); | |
1822 | } | |
1823 | } | |
1824 | ||
1825 | static void virt_set_iommu(Object *obj, const char *value, Error **errp) | |
1826 | { | |
1827 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1828 | ||
1829 | if (!strcmp(value, "smmuv3")) { | |
1830 | vms->iommu = VIRT_IOMMU_SMMUV3; | |
1831 | } else if (!strcmp(value, "none")) { | |
1832 | vms->iommu = VIRT_IOMMU_NONE; | |
1833 | } else { | |
1834 | error_setg(errp, "Invalid iommu value"); | |
1835 | error_append_hint(errp, "Valid values are none, smmuv3.\n"); | |
1836 | } | |
1837 | } | |
1838 | ||
ea089eeb IM |
1839 | static CpuInstanceProperties |
1840 | virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
1841 | { | |
1842 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
1843 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
1844 | ||
1845 | assert(cpu_index < possible_cpus->len); | |
1846 | return possible_cpus->cpus[cpu_index].props; | |
1847 | } | |
1848 | ||
79e07936 IM |
1849 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) |
1850 | { | |
1851 | return idx % nb_numa_nodes; | |
1852 | } | |
1853 | ||
17d3d0e2 IM |
1854 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
1855 | { | |
1856 | int n; | |
cc7d44c2 | 1857 | unsigned int max_cpus = ms->smp.max_cpus; |
17d3d0e2 IM |
1858 | VirtMachineState *vms = VIRT_MACHINE(ms); |
1859 | ||
1860 | if (ms->possible_cpus) { | |
1861 | assert(ms->possible_cpus->len == max_cpus); | |
1862 | return ms->possible_cpus; | |
1863 | } | |
1864 | ||
1865 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
1866 | sizeof(CPUArchId) * max_cpus); | |
1867 | ms->possible_cpus->len = max_cpus; | |
1868 | for (n = 0; n < ms->possible_cpus->len; n++) { | |
d342eb76 | 1869 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
17d3d0e2 IM |
1870 | ms->possible_cpus->cpus[n].arch_id = |
1871 | virt_cpu_mp_affinity(vms, n); | |
1872 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | |
1873 | ms->possible_cpus->cpus[n].props.thread_id = n; | |
17d3d0e2 IM |
1874 | } |
1875 | return ms->possible_cpus; | |
1876 | } | |
1877 | ||
a3fc8396 IM |
1878 | static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1879 | DeviceState *dev, Error **errp) | |
1880 | { | |
1881 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | |
1882 | ||
1883 | if (vms->platform_bus_dev) { | |
1884 | if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { | |
1885 | platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), | |
1886 | SYS_BUS_DEVICE(dev)); | |
1887 | } | |
1888 | } | |
1889 | } | |
1890 | ||
1891 | static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, | |
1892 | DeviceState *dev) | |
1893 | { | |
1894 | if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { | |
1895 | return HOTPLUG_HANDLER(machine); | |
1896 | } | |
1897 | ||
1898 | return NULL; | |
1899 | } | |
1900 | ||
c9650222 EA |
1901 | /* |
1902 | * for arm64 kvm_type [7-0] encodes the requested number of bits | |
1903 | * in the IPA address space | |
1904 | */ | |
1905 | static int virt_kvm_type(MachineState *ms, const char *type_str) | |
1906 | { | |
1907 | VirtMachineState *vms = VIRT_MACHINE(ms); | |
1908 | int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); | |
1909 | int requested_pa_size; | |
1910 | ||
1911 | /* we freeze the memory map to compute the highest gpa */ | |
1912 | virt_set_memmap(vms); | |
1913 | ||
1914 | requested_pa_size = 64 - clz64(vms->highest_gpa); | |
1915 | ||
1916 | if (requested_pa_size > max_vm_pa_size) { | |
1917 | error_report("-m and ,maxmem option values " | |
1918 | "require an IPA range (%d bits) larger than " | |
1919 | "the one supported by the host (%d bits)", | |
1920 | requested_pa_size, max_vm_pa_size); | |
1921 | exit(1); | |
1922 | } | |
1923 | /* | |
1924 | * By default we return 0 which corresponds to an implicit legacy | |
1925 | * 40b IPA setting. Otherwise we return the actual requested PA | |
1926 | * logsize | |
1927 | */ | |
1928 | return requested_pa_size > 40 ? requested_pa_size : 0; | |
1929 | } | |
1930 | ||
ed796373 WH |
1931 | static void virt_machine_class_init(ObjectClass *oc, void *data) |
1932 | { | |
9c94d8e6 | 1933 | MachineClass *mc = MACHINE_CLASS(oc); |
a3fc8396 | 1934 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
9c94d8e6 WH |
1935 | |
1936 | mc->init = machvirt_init; | |
b10fbd53 EA |
1937 | /* Start with max_cpus set to 512, which is the maximum supported by KVM. |
1938 | * The value may be reduced later when we have more information about the | |
9c94d8e6 WH |
1939 | * configuration of the particular instance. |
1940 | */ | |
b10fbd53 | 1941 | mc->max_cpus = 512; |
6f2062b9 EH |
1942 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); |
1943 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); | |
94692dcd | 1944 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); |
4ebc0b61 | 1945 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); |
9c94d8e6 WH |
1946 | mc->block_default_type = IF_VIRTIO; |
1947 | mc->no_cdrom = 1; | |
1948 | mc->pci_allow_0_address = true; | |
a2519ad1 PM |
1949 | /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ |
1950 | mc->minimum_page_bits = 12; | |
17d3d0e2 | 1951 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; |
ea089eeb | 1952 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; |
ba1ba5cc | 1953 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
79e07936 | 1954 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; |
c9650222 | 1955 | mc->kvm_type = virt_kvm_type; |
debbdc00 | 1956 | assert(!mc->get_hotplug_handler); |
a3fc8396 IM |
1957 | mc->get_hotplug_handler = virt_machine_get_hotplug_handler; |
1958 | hc->plug = virt_machine_device_plug_cb; | |
cd5ff833 | 1959 | mc->numa_mem_supported = true; |
ed796373 WH |
1960 | } |
1961 | ||
95159760 | 1962 | static void virt_instance_init(Object *obj) |
083a5890 GB |
1963 | { |
1964 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
ccc11b02 | 1965 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
083a5890 | 1966 | |
2d710006 PM |
1967 | /* EL3 is disabled by default on virt: this makes us consistent |
1968 | * between KVM and TCG for this board, and it also allows us to | |
1969 | * boot UEFI blobs which assume no TrustZone support. | |
1970 | */ | |
1971 | vms->secure = false; | |
083a5890 GB |
1972 | object_property_add_bool(obj, "secure", virt_get_secure, |
1973 | virt_set_secure, NULL); | |
1974 | object_property_set_description(obj, "secure", | |
1975 | "Set on/off to enable/disable the ARM " | |
1976 | "Security Extensions (TrustZone)", | |
1977 | NULL); | |
5125f9cd | 1978 | |
f29cacfb PM |
1979 | /* EL2 is also disabled by default, for similar reasons */ |
1980 | vms->virt = false; | |
1981 | object_property_add_bool(obj, "virtualization", virt_get_virt, | |
1982 | virt_set_virt, NULL); | |
1983 | object_property_set_description(obj, "virtualization", | |
1984 | "Set on/off to enable/disable emulating a " | |
1985 | "guest CPU which implements the ARM " | |
1986 | "Virtualization Extensions", | |
1987 | NULL); | |
1988 | ||
5125f9cd PF |
1989 | /* High memory is enabled by default */ |
1990 | vms->highmem = true; | |
1991 | object_property_add_bool(obj, "highmem", virt_get_highmem, | |
1992 | virt_set_highmem, NULL); | |
1993 | object_property_set_description(obj, "highmem", | |
1994 | "Set on/off to enable/disable using " | |
1995 | "physical address space above 32 bits", | |
1996 | NULL); | |
b92ad394 PF |
1997 | /* Default GIC type is v2 */ |
1998 | vms->gic_version = 2; | |
1999 | object_property_add_str(obj, "gic-version", virt_get_gic_version, | |
2000 | virt_set_gic_version, NULL); | |
2001 | object_property_set_description(obj, "gic-version", | |
2002 | "Set GIC version. " | |
2003 | "Valid values are 2, 3 and host", NULL); | |
9ac4ef77 | 2004 | |
17ec075a EA |
2005 | vms->highmem_ecam = !vmc->no_highmem_ecam; |
2006 | ||
ccc11b02 EA |
2007 | if (vmc->no_its) { |
2008 | vms->its = false; | |
2009 | } else { | |
2010 | /* Default allows ITS instantiation */ | |
2011 | vms->its = true; | |
2012 | object_property_add_bool(obj, "its", virt_get_its, | |
2013 | virt_set_its, NULL); | |
2014 | object_property_set_description(obj, "its", | |
2015 | "Set on/off to enable/disable " | |
2016 | "ITS instantiation", | |
2017 | NULL); | |
2018 | } | |
2019 | ||
e24e3454 EA |
2020 | /* Default disallows iommu instantiation */ |
2021 | vms->iommu = VIRT_IOMMU_NONE; | |
2022 | object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); | |
2023 | object_property_set_description(obj, "iommu", | |
2024 | "Set the IOMMU type. " | |
2025 | "Valid values are none and smmuv3", | |
2026 | NULL); | |
2027 | ||
9ac4ef77 | 2028 | vms->irqmap = a15irqmap; |
e0561e60 MA |
2029 | |
2030 | virt_flash_create(vms); | |
083a5890 GB |
2031 | } |
2032 | ||
95159760 EH |
2033 | static const TypeInfo virt_machine_info = { |
2034 | .name = TYPE_VIRT_MACHINE, | |
2035 | .parent = TYPE_MACHINE, | |
2036 | .abstract = true, | |
2037 | .instance_size = sizeof(VirtMachineState), | |
2038 | .class_size = sizeof(VirtMachineClass), | |
2039 | .class_init = virt_machine_class_init, | |
bbac02f1 | 2040 | .instance_init = virt_instance_init, |
95159760 EH |
2041 | .interfaces = (InterfaceInfo[]) { |
2042 | { TYPE_HOTPLUG_HANDLER }, | |
2043 | { } | |
2044 | }, | |
2045 | }; | |
2046 | ||
2047 | static void machvirt_machine_init(void) | |
2048 | { | |
2049 | type_register_static(&virt_machine_info); | |
2050 | } | |
2051 | type_init(machvirt_machine_init); | |
2052 | ||
9bf2650b CH |
2053 | static void virt_machine_4_1_options(MachineClass *mc) |
2054 | { | |
2055 | } | |
2056 | DEFINE_VIRT_MACHINE_AS_LATEST(4, 1) | |
2057 | ||
84e060bf AW |
2058 | static void virt_machine_4_0_options(MachineClass *mc) |
2059 | { | |
9bf2650b CH |
2060 | virt_machine_4_1_options(mc); |
2061 | compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); | |
84e060bf | 2062 | } |
9bf2650b | 2063 | DEFINE_VIRT_MACHINE(4, 0) |
84e060bf | 2064 | |
22907d2b AJ |
2065 | static void virt_machine_3_1_options(MachineClass *mc) |
2066 | { | |
84e060bf | 2067 | virt_machine_4_0_options(mc); |
abd93cc7 | 2068 | compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); |
22907d2b | 2069 | } |
84e060bf | 2070 | DEFINE_VIRT_MACHINE(3, 1) |
22907d2b | 2071 | |
8ae9a1ca EA |
2072 | static void virt_machine_3_0_options(MachineClass *mc) |
2073 | { | |
22907d2b | 2074 | virt_machine_3_1_options(mc); |
ddb3235d | 2075 | compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); |
8ae9a1ca | 2076 | } |
22907d2b AJ |
2077 | DEFINE_VIRT_MACHINE(3, 0) |
2078 | ||
a2a05159 PM |
2079 | static void virt_machine_2_12_options(MachineClass *mc) |
2080 | { | |
17ec075a EA |
2081 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
2082 | ||
8ae9a1ca | 2083 | virt_machine_3_0_options(mc); |
0d47310b | 2084 | compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); |
17ec075a | 2085 | vmc->no_highmem_ecam = true; |
b10fbd53 | 2086 | mc->max_cpus = 255; |
a2a05159 | 2087 | } |
8ae9a1ca | 2088 | DEFINE_VIRT_MACHINE(2, 12) |
a2a05159 | 2089 | |
79283dda EA |
2090 | static void virt_machine_2_11_options(MachineClass *mc) |
2091 | { | |
dfadc3bf WH |
2092 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
2093 | ||
a2a05159 | 2094 | virt_machine_2_12_options(mc); |
43df70a9 | 2095 | compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); |
dfadc3bf | 2096 | vmc->smbios_old_sys_ver = true; |
79283dda | 2097 | } |
a2a05159 | 2098 | DEFINE_VIRT_MACHINE(2, 11) |
79283dda | 2099 | |
f22ab6cb EA |
2100 | static void virt_machine_2_10_options(MachineClass *mc) |
2101 | { | |
79283dda | 2102 | virt_machine_2_11_options(mc); |
503224f4 | 2103 | compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); |
846690de PM |
2104 | /* before 2.11 we never faulted accesses to bad addresses */ |
2105 | mc->ignore_memory_transaction_failures = true; | |
f22ab6cb | 2106 | } |
79283dda | 2107 | DEFINE_VIRT_MACHINE(2, 10) |
f22ab6cb | 2108 | |
e353aac5 PM |
2109 | static void virt_machine_2_9_options(MachineClass *mc) |
2110 | { | |
f22ab6cb | 2111 | virt_machine_2_10_options(mc); |
3e803152 | 2112 | compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); |
e353aac5 | 2113 | } |
f22ab6cb | 2114 | DEFINE_VIRT_MACHINE(2, 9) |
e353aac5 | 2115 | |
96b0439b AJ |
2116 | static void virt_machine_2_8_options(MachineClass *mc) |
2117 | { | |
156bc9a5 PM |
2118 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
2119 | ||
e353aac5 | 2120 | virt_machine_2_9_options(mc); |
edc24ccd | 2121 | compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); |
156bc9a5 PM |
2122 | /* For 2.8 and earlier we falsely claimed in the DT that |
2123 | * our timers were edge-triggered, not level-triggered. | |
2124 | */ | |
2125 | vmc->claim_edge_triggered_timers = true; | |
96b0439b | 2126 | } |
e353aac5 | 2127 | DEFINE_VIRT_MACHINE(2, 8) |
96b0439b | 2128 | |
1287f2b3 AJ |
2129 | static void virt_machine_2_7_options(MachineClass *mc) |
2130 | { | |
2231f69b AJ |
2131 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
2132 | ||
96b0439b | 2133 | virt_machine_2_8_options(mc); |
5a995064 | 2134 | compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); |
2231f69b AJ |
2135 | /* ITS was introduced with 2.8 */ |
2136 | vmc->no_its = true; | |
a2519ad1 PM |
2137 | /* Stick with 1K pages for migration compatibility */ |
2138 | mc->minimum_page_bits = 0; | |
1287f2b3 | 2139 | } |
96b0439b | 2140 | DEFINE_VIRT_MACHINE(2, 7) |
1287f2b3 | 2141 | |
ab093c3c | 2142 | static void virt_machine_2_6_options(MachineClass *mc) |
c2919690 | 2143 | { |
95eb49c8 AJ |
2144 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
2145 | ||
1287f2b3 | 2146 | virt_machine_2_7_options(mc); |
ff8f261f | 2147 | compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); |
95eb49c8 | 2148 | vmc->disallow_affinity_adjustment = true; |
1141d1eb WH |
2149 | /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ |
2150 | vmc->no_pmu = true; | |
c2919690 | 2151 | } |
1287f2b3 | 2152 | DEFINE_VIRT_MACHINE(2, 6) |