[thirdparty/qemu.git] / hw / arm / xlnx-zynqmp.c

/*
 * Xilinx Zynq MPSoC emulation
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"

#define GIC_NUM_SPI_INTR 160

#define ARM_PHYS_TIMER_PPI  30
#define ARM_VIRT_TIMER_PPI  27

#define GIC_BASE_ADDR       0xf9000000
#define GIC_DIST_ADDR       0xf9010000
#define GIC_CPU_ADDR        0xf9020000

#define SATA_INTR           133
#define SATA_ADDR           0xFD0C0000
#define SATA_NUM_PORTS      2

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};

static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
    57, 59, 61, 63,
};

static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
    0xFF000000, 0xFF010000,
};

static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
    21, 22,
};

static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
    0xFF160000, 0xFF170000,
};

static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
    48, 49,
};

static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
    0xFF040000, 0xFF050000,
};

static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
    19, 20,
};

typedef struct XlnxZynqMPGICRegion {
    int region_index;
    uint32_t address;
} XlnxZynqMPGICRegion;

static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
    { .region_index = 0, .address = GIC_DIST_ADDR, },
    { .region_index = 1, .address = GIC_CPU_ADDR,  },
};

static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
    return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}

static void xlnx_zynqmp_init(Object *obj)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
    int i;

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                          "cortex-a53-" TYPE_ARM_CPU);
        object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
                                  &error_abort);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
                          "cortex-r5-" TYPE_ARM_CPU);
        object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
                                  &error_abort);
    }

    object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
                             (Object **)&s->ddr_ram,
                             qdev_prop_allow_set_link_before_realize,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);

    object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
                          TYPE_SYSBUS_SDHCI);
        qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                            sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        object_initialize(&s->spi[i], sizeof(s->spi[i]),
                          TYPE_XILINX_SPIPS);
        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
    }
}

static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
    MemoryRegion *system_memory = get_system_memory();
    uint8_t i;
    uint64_t ram_size;
    const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
    ram_addr_t ddr_low_size, ddr_high_size;
    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
    Error *err = NULL;

    ram_size = memory_region_size(s->ddr_ram);

    /* Create the DDR Memory Regions. User friendly checks should happen at
     * the board level
     */
    if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
        /* The RAM size is above the maximum available for the low DDR.
         * Create the high DDR memory region as well.
         */
        assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
        ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
        ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;

        memory_region_init_alias(&s->ddr_ram_high, NULL,
                                 "ddr-ram-high", s->ddr_ram,
                                  ddr_low_size, ddr_high_size);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_HIGH_RAM_START,
                                    &s->ddr_ram_high);
    } else {
        /* RAM must be non-zero */
        assert(ram_size);
        ddr_low_size = ram_size;
    }

    memory_region_init_alias(&s->ddr_ram_low, NULL,
                             "ddr-ram-low", s->ddr_ram,
                              0, ddr_low_size);
    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);

    /* Create the four OCM banks */
    for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
        char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);

        memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
                               XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
        vmstate_register_ram_global(&s->ocm_ram[i]);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
                                        i * XLNX_ZYNQMP_OCM_RAM_SIZE,
                                    &s->ocm_ram[i]);

        g_free(ocm_name);
    }

    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
    for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
        SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
        const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
        MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
        uint32_t addr = r->address;
        int j;

        sysbus_mmio_map(gic, r->region_index, addr);

        for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
            MemoryRegion *alias = &s->gic_mr[i][j];

            addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
            memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
                                     0, XLNX_ZYNQMP_GIC_REGION_SIZE);
            memory_region_add_subregion(system_memory, addr, alias);
        }
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        qemu_irq irq;
        char *name;

        object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->apu_cpu[i];
        }
        g_free(name);

        object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
                           qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
                                            ARM_CPU_IRQ));
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        char *name;

        name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->rpu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    if (!s->boot_cpu_ptr) {
        error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
        return;
    }

    for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        NICInfo *nd = &nd_table[i];

        if (nd->used) {
            qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
            qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
        }
        object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
                           gic_spi[gem_intr[i]]);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           gic_spi[uart_intr[i]]);
    }

    object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        char *bus_name;

        object_property_set_bool(OBJECT(&s->sdhci[i]), true,
                                 "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                        sdhci_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                           gic_spi[sdhci_intr[i]]);
        /* Alias controller SD bus to the SoC itself */
        bus_name = g_strdup_printf("sd-bus%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->sdhci[i]), "sd-bus",
                                  &error_abort);
        g_free(bus_name);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        gchar *bus_name;

        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           gic_spi[spi_intr[i]]);

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->spi[i]), "spi0",
                                  &error_abort);
	g_free(bus_name);
    }
}

static Property xlnx_zynqmp_props[] = {
    DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
    DEFINE_PROP_END_OF_LIST()
};

static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = xlnx_zynqmp_props;
    dc->realize = xlnx_zynqmp_realize;

    /*
     * Reason: creates an ARM CPU, thus use after free(), see
     * arm_cpu_class_init()
     */
    dc->cannot_destroy_with_object_finalize_yet = true;
}

static const TypeInfo xlnx_zynqmp_type_info = {
    .name = TYPE_XLNX_ZYNQMP,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPState),
    .instance_init = xlnx_zynqmp_init,
    .class_init = xlnx_zynqmp_class_init,
};

static void xlnx_zynqmp_register_types(void)
{
    type_register_static(&xlnx_zynqmp_type_info);
}

type_init(xlnx_zynqmp_register_types)
Commit	Line	Data
f0a902f7 PC	1	/*
	2	* Xilinx Zynq MPSoC emulation
	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
f0a902f7	20	#include "hw/arm/xlnx-zynqmp.h"
bf4cb109	21	#include "hw/intc/arm_gic_common.h"
7729e1f4 PC	22	#include "exec/address-spaces.h"
	23
	24	#define GIC_NUM_SPI_INTR 160
	25
bf4cb109 PC	26	#define ARM_PHYS_TIMER_PPI 30
	27	#define ARM_VIRT_TIMER_PPI 27
	28
7729e1f4 PC	29	#define GIC_BASE_ADDR 0xf9000000
	30	#define GIC_DIST_ADDR 0xf9010000
	31	#define GIC_CPU_ADDR 0xf9020000
	32
6fdf3282 AF	33	#define SATA_INTR 133
	34	#define SATA_ADDR 0xFD0C0000
	35	#define SATA_NUM_PORTS 2
	36
14ca2e46 PC	37	static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
	38	0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
	39	};
	40
	41	static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
	42	57, 59, 61, 63,
	43	};
	44
3bade2a9 PC	45	static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
	46	0xFF000000, 0xFF010000,
	47	};
	48
	49	static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
	50	21, 22,
	51	};
	52
33108e9f SPB	53	static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
	54	0xFF160000, 0xFF170000,
	55	};
	56
	57	static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
	58	48, 49,
	59	};
	60
02d07eb4 AF	61	static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
	62	0xFF040000, 0xFF050000,
	63	};
	64
	65	static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
	66	19, 20,
	67	};
	68
7729e1f4 PC	69	typedef struct XlnxZynqMPGICRegion {
	70	int region_index;
	71	uint32_t address;
	72	} XlnxZynqMPGICRegion;
	73
	74	static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
	75	{ .region_index = 0, .address = GIC_DIST_ADDR, },
	76	{ .region_index = 1, .address = GIC_CPU_ADDR, },
	77	};
f0a902f7	78
bf4cb109 PC	79	static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
	80	{
	81	return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
	82	}
	83
f0a902f7 PC	84	static void xlnx_zynqmp_init(Object *obj)
	85	{
	86	XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
	87	int i;
	88
2e5577bc PC	89	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
2e5577bc PC	90	object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
f0a902f7	91	"cortex-a53-" TYPE_ARM_CPU);
2e5577bc	92	object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
f0a902f7 PC	93	&error_abort);
f0a902f7 PC	94	}
7729e1f4	95
b58850e7 PC	96	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	97	object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
	98	"cortex-r5-" TYPE_ARM_CPU);
	99	object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
	100	&error_abort);
	101	}
	102
dc3b89ef AF	103	object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
	104	(Object **)&s->ddr_ram,
	105	qdev_prop_allow_set_link_before_realize,
	106	OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
	107
7729e1f4 PC	108	object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
7729e1f4 PC	109	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
14ca2e46 PC	110
	111	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	112	object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
	113	qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
	114	}
3bade2a9 PC	115
	116	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	117	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
	118	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	119	}
6fdf3282 AF	120
	121	object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
	122	qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
33108e9f SPB	123
	124	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	125	object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
	126	TYPE_SYSBUS_SDHCI);
	127	qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
	128	sysbus_get_default());
	129	}
02d07eb4 AF	130
	131	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	132	object_initialize(&s->spi[i], sizeof(s->spi[i]),
	133	TYPE_XILINX_SPIPS);
	134	qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
	135	}
f0a902f7 PC	136	}
	137
	138	static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
	139	{
	140	XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
7729e1f4	141	MemoryRegion *system_memory = get_system_memory();
f0a902f7	142	uint8_t i;
dc3b89ef	143	uint64_t ram_size;
6396a193	144	const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
dc3b89ef	145	ram_addr_t ddr_low_size, ddr_high_size;
14ca2e46	146	qemu_irq gic_spi[GIC_NUM_SPI_INTR];
f0a902f7 PC	147	Error *err = NULL;
f0a902f7 PC	148
dc3b89ef AF	149	ram_size = memory_region_size(s->ddr_ram);
	150
	151	/* Create the DDR Memory Regions. User friendly checks should happen at
	152	* the board level
	153	*/
	154	if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
	155	/* The RAM size is above the maximum available for the low DDR.
	156	* Create the high DDR memory region as well.
	157	*/
	158	assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
	159	ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	160	ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	161
	162	memory_region_init_alias(&s->ddr_ram_high, NULL,
	163	"ddr-ram-high", s->ddr_ram,
	164	ddr_low_size, ddr_high_size);
	165	memory_region_add_subregion(get_system_memory(),
	166	XLNX_ZYNQMP_HIGH_RAM_START,
	167	&s->ddr_ram_high);
	168	} else {
	169	/* RAM must be non-zero */
	170	assert(ram_size);
	171	ddr_low_size = ram_size;
	172	}
	173
	174	memory_region_init_alias(&s->ddr_ram_low, NULL,
	175	"ddr-ram-low", s->ddr_ram,
	176	0, ddr_low_size);
	177	memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
	178
6675d719 AF	179	/* Create the four OCM banks */
	180	for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
	181	char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
	182
	183	memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
f8ed85ac	184	XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
6675d719 AF	185	vmstate_register_ram_global(&s->ocm_ram[i]);
	186	memory_region_add_subregion(get_system_memory(),
	187	XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
	188	i * XLNX_ZYNQMP_OCM_RAM_SIZE,
	189	&s->ocm_ram[i]);
	190
	191	g_free(ocm_name);
	192	}
	193
7729e1f4 PC	194	qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
7729e1f4 PC	195	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
2e5577bc	196	qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
7729e1f4 PC	197	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
7729e1f4 PC	198	if (err) {
24cfc8dc	199	error_propagate(errp, err);
7729e1f4 PC	200	return;
	201	}
	202	assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
	203	for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
	204	SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
	205	const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
	206	MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
	207	uint32_t addr = r->address;
	208	int j;
	209
	210	sysbus_mmio_map(gic, r->region_index, addr);
	211
	212	for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
	213	MemoryRegion *alias = &s->gic_mr[i][j];
	214
	215	addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
	216	memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
	217	0, XLNX_ZYNQMP_GIC_REGION_SIZE);
	218	memory_region_add_subregion(system_memory, addr, alias);
	219	}
	220	}
	221
2e5577bc	222	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
bf4cb109	223	qemu_irq irq;
6396a193	224	char *name;
bf4cb109	225
2e5577bc	226	object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f0a902f7	227	"psci-conduit", &error_abort);
6396a193 PC	228
	229	name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
	230	if (strcmp(name, boot_cpu)) {
f0a902f7	231	/* Secondary CPUs start in PSCI powered-down state */
2e5577bc	232	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
f0a902f7	233	"start-powered-off", &error_abort);
6396a193 PC	234	} else {
6396a193 PC	235	s->boot_cpu_ptr = &s->apu_cpu[i];
f0a902f7	236	}
5348c62c	237	g_free(name);
f0a902f7	238
2e5577bc	239	object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
e1292517	240	"reset-cbar", &error_abort);
2e5577bc PC	241	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
2e5577bc PC	242	&err);
f0a902f7	243	if (err) {
24cfc8dc	244	error_propagate(errp, err);
f0a902f7 PC	245	return;
f0a902f7 PC	246	}
7729e1f4 PC	247
7729e1f4 PC	248	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
2e5577bc PC	249	qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
2e5577bc PC	250	ARM_CPU_IRQ));
bf4cb109 PC	251	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	252	arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
2e5577bc	253	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
bf4cb109 PC	254	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	255	arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
2e5577bc	256	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
f0a902f7	257	}
14ca2e46	258
b58850e7 PC	259	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	260	char *name;
	261
	262	name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
	263	if (strcmp(name, boot_cpu)) {
	264	/* Secondary CPUs start in PSCI powered-down state */
	265	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
	266	"start-powered-off", &error_abort);
	267	} else {
	268	s->boot_cpu_ptr = &s->rpu_cpu[i];
	269	}
5348c62c	270	g_free(name);
b58850e7 PC	271
b58850e7 PC	272	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
e1292517	273	&error_abort);
b58850e7 PC	274	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
	275	&err);
	276	if (err) {
24cfc8dc	277	error_propagate(errp, err);
b58850e7 PC	278	return;
	279	}
	280	}
	281
6396a193	282	if (!s->boot_cpu_ptr) {
9af9e0fe	283	error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
6396a193 PC	284	return;
	285	}
	286
14ca2e46 PC	287	for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
	288	gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
	289	}
	290
	291	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	292	NICInfo *nd = &nd_table[i];
	293
	294	if (nd->used) {
	295	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	296	qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
	297	}
	298	object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
	299	if (err) {
24cfc8dc	300	error_propagate(errp, err);
14ca2e46 PC	301	return;
	302	}
	303	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
	304	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
	305	gic_spi[gem_intr[i]]);
	306	}
3bade2a9 PC	307
	308	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	309	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	310	if (err) {
24cfc8dc	311	error_propagate(errp, err);
3bade2a9 PC	312	return;
	313	}
	314	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
	315	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	316	gic_spi[uart_intr[i]]);
	317	}
6fdf3282 AF	318
	319	object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
	320	&error_abort);
	321	object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
	322	if (err) {
	323	error_propagate(errp, err);
	324	return;
	325	}
	326
	327	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
	328	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
33108e9f SPB	329
33108e9f SPB	330	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
eb4f566b PM	331	char *bus_name;
eb4f566b PM	332
33108e9f SPB	333	object_property_set_bool(OBJECT(&s->sdhci[i]), true,
	334	"realized", &err);
	335	if (err) {
	336	error_propagate(errp, err);
	337	return;
	338	}
	339	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	340	sdhci_addr[i]);
	341	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	342	gic_spi[sdhci_intr[i]]);
eb4f566b PM	343	/* Alias controller SD bus to the SoC itself */
	344	bus_name = g_strdup_printf("sd-bus%d", i);
	345	object_property_add_alias(OBJECT(s), bus_name,
	346	OBJECT(&s->sdhci[i]), "sd-bus",
	347	&error_abort);
	348	g_free(bus_name);
33108e9f	349	}
02d07eb4 AF	350
	351	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	352	gchar *bus_name;
	353
	354	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
	355
	356	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
	357	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	358	gic_spi[spi_intr[i]]);
	359
	360	/* Alias controller SPI bus to the SoC itself */
	361	bus_name = g_strdup_printf("spi%d", i);
	362	object_property_add_alias(OBJECT(s), bus_name,
	363	OBJECT(&s->spi[i]), "spi0",
	364	&error_abort);
	365	g_free(bus_name);
	366	}
f0a902f7 PC	367	}
f0a902f7 PC	368
6396a193 PC	369	static Property xlnx_zynqmp_props[] = {
	370	DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
	371	DEFINE_PROP_END_OF_LIST()
	372	};
	373
f0a902f7 PC	374	static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
	375	{
	376	DeviceClass *dc = DEVICE_CLASS(oc);
	377
6396a193	378	dc->props = xlnx_zynqmp_props;
f0a902f7	379	dc->realize = xlnx_zynqmp_realize;
4c315c27 MA	380
	381	/*
	382	* Reason: creates an ARM CPU, thus use after free(), see
	383	* arm_cpu_class_init()
	384	*/
	385	dc->cannot_destroy_with_object_finalize_yet = true;
f0a902f7 PC	386	}
	387
	388	static const TypeInfo xlnx_zynqmp_type_info = {
	389	.name = TYPE_XLNX_ZYNQMP,
	390	.parent = TYPE_DEVICE,
	391	.instance_size = sizeof(XlnxZynqMPState),
	392	.instance_init = xlnx_zynqmp_init,
	393	.class_init = xlnx_zynqmp_class_init,
	394	};
	395
	396	static void xlnx_zynqmp_register_types(void)
	397	{
	398	type_register_static(&xlnx_zynqmp_type_info);
	399	}
	400
	401	type_init(xlnx_zynqmp_register_types)