[thirdparty/qemu.git] / hw / char / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sh4/sh.h"
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qemu/timer.h"

//#define DEBUG_SERIAL

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    MemoryRegion iomem;
    MemoryRegion iomem_p4;
    MemoryRegion iomem_a7;
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    int freq;
    int feat;
    int flags;
    int rtrg;

    CharBackend chr;
    QEMUTimer *fifo_timeout_timer;
    uint64_t etu; /* Elementary Time Unit (ns) */

    qemu_irq eri;
    qemu_irq rxi;
    qemu_irq txi;
    qemu_irq tei;
    qemu_irq bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state * s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_write(void *opaque, hwaddr offs,
                            uint64_t val, unsigned size)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

#ifdef DEBUG_SERIAL
    printf("sh_serial: write offs=0x%02x val=0x%02x\n",
           offs, val);
#endif
    switch(offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
        return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5)))
            s->flags |= SH_SERIAL_FLAG_TEND;
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
            qemu_set_irq(s->txi, val & (1 << 7));
        }
        if (!(val & (1 << 6))) {
            qemu_set_irq(s->rxi, 0);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (qemu_chr_fe_backend_connected(&s->chr)) {
            ch = val;
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
        }
        s->dr = val;
        s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6)))
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            if (!(val & (1 << 5)))
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            if (!(val & (1 << 4)))
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            if (!(val & (1 << 1)))
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            if (!(val & (1 << 0)))
                s->flags &= ~SH_SERIAL_FLAG_DR;

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi) {
                    qemu_set_irq(s->rxi, 0);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
#endif
        case 0x1c:
            s->sptr = val & 0x8f;
            return;
        }
    }

    fprintf(stderr, "sh_serial: unsupported write to 0x%02"
            HWADDR_PRIx "\n", offs);
    abort();
}

static uint64_t sh_serial_read(void *opaque, hwaddr offs,
                               unsigned size)
{
    sh_serial_state *s = opaque;
    uint32_t ret = ~0;

#if 0
    switch(offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
        break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND)
                ret |= (1 << 6);
            if (s->flags & SH_SERIAL_FLAG_TDE)
                ret |= (1 << 5);
            if (s->flags & SH_SERIAL_FLAG_BRK)
                ret |= (1 << 4);
            if (s->flags & SH_SERIAL_FLAG_RDF)
                ret |= (1 << 1);
            if (s->flags & SH_SERIAL_FLAG_DR)
                ret |= (1 << 0);

            if (s->scr & (1 << 5))
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH)
                    s->rx_tail = 0;
                if (s->rx_cnt < s->rtrg)
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            break;
        case 0x18:
            ret = s->fcr;
            break;
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
#endif
        case 0x1c:
            ret = s->sptr;
            break;
        }
    }
#ifdef DEBUG_SERIAL
    printf("sh_serial: read offs=0x%02x val=0x%x\n",
           offs, ret);
#endif

    if (ret & ~((1 << 16) - 1)) {
        fprintf(stderr, "sh_serial: unsupported read from 0x%02"
                HWADDR_PRIx "\n", offs);
        abort();
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF)
        s->sr |= (1 << 4);
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_timeout_int(void *opaque)
{
    sh_serial_state *s = opaque;

    s->flags |= SH_SERIAL_FLAG_RDF;
    if (s->scr & (1 << 6) && s->rxi) {
        qemu_set_irq(s->rxi, 1);
    }
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;

    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        int i;
        for (i = 0; i < size; i++) {
            if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
                s->rx_fifo[s->rx_head++] = buf[i];
                if (s->rx_head == SH_RX_FIFO_LENGTH) {
                    s->rx_head = 0;
                }
                s->rx_cnt++;
                if (s->rx_cnt >= s->rtrg) {
                    s->flags |= SH_SERIAL_FLAG_RDF;
                    if (s->scr & (1 << 6) && s->rxi) {
                        timer_del(s->fifo_timeout_timer);
                        qemu_set_irq(s->rxi, 1);
                    }
                } else {
                    timer_mod(s->fifo_timeout_timer,
                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
                }
            }
        }
    } else {
        s->rx_fifo[0] = buf[0];
    }
}

static void sh_serial_event(void *opaque, int event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK)
        sh_serial_receive_break(s);
}

static const MemoryRegionOps sh_serial_ops = {
    .read = sh_serial_read,
    .write = sh_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void sh_serial_init(MemoryRegion *sysmem,
                    hwaddr base, int feat,
                    uint32_t freq, Chardev *chr,
                    qemu_irq eri_source,
                    qemu_irq rxi_source,
                    qemu_irq txi_source,
                    qemu_irq tei_source,
                    qemu_irq bri_source)
{
    sh_serial_state *s;

    s = g_malloc0(sizeof(sh_serial_state));

    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    }
    else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
                          "serial", 0x100000000ULL);

    memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);

    memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);

    if (chr) {
        qemu_chr_fe_init(&s->chr, chr, &error_abort);
        qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
                                 sh_serial_receive1,
                                 sh_serial_event, NULL, s, NULL, true);
    }

    s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                         sh_serial_timeout_int, s);
    s->etu = NANOSECONDS_PER_SECOND / 9600;
    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
64552b6b	27
0430891c	28	#include "qemu/osdep.h"
64552b6b	29	#include "hw/irq.h"
0d09e41a	30	#include "hw/sh4/sh.h"
4d43a603	31	#include "chardev/char-fe.h"
32a6ebec	32	#include "qapi/error.h"
71bb4ce1	33	#include "qemu/timer.h"
2f062c72 TS	34
	35	//#define DEBUG_SERIAL
	36
	37	#define SH_SERIAL_FLAG_TEND (1 << 0)
	38	#define SH_SERIAL_FLAG_TDE (1 << 1)
	39	#define SH_SERIAL_FLAG_RDF (1 << 2)
	40	#define SH_SERIAL_FLAG_BRK (1 << 3)
	41	#define SH_SERIAL_FLAG_DR (1 << 4)
	42
63242a00 AJ	43	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	44
2f062c72	45	typedef struct {
9a9d0b81 BC	46	MemoryRegion iomem;
	47	MemoryRegion iomem_p4;
	48	MemoryRegion iomem_a7;
2f062c72 TS	49	uint8_t smr;
	50	uint8_t brr;
	51	uint8_t scr;
	52	uint8_t dr; /* ftdr / tdr */
	53	uint8_t sr; /* fsr / ssr */
	54	uint16_t fcr;
	55	uint8_t sptr;
	56
63242a00	57	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	58	uint8_t rx_cnt;
63242a00 AJ	59	uint8_t rx_tail;
63242a00 AJ	60	uint8_t rx_head;
2f062c72	61
2f062c72 TS	62	int freq;
	63	int feat;
	64	int flags;
63242a00	65	int rtrg;
2f062c72	66
32a6ebec	67	CharBackend chr;
71bb4ce1 GU	68	QEMUTimer *fifo_timeout_timer;
71bb4ce1 GU	69	uint64_t etu; /* Elementary Time Unit (ns) */
bf5b7423	70
4e7ed2d1 AJ	71	qemu_irq eri;
	72	qemu_irq rxi;
	73	qemu_irq txi;
	74	qemu_irq tei;
	75	qemu_irq bri;
2f062c72 TS	76	} sh_serial_state;
2f062c72 TS	77
63242a00 AJ	78	static void sh_serial_clear_fifo(sh_serial_state * s)
	79	{
	80	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	81	s->rx_cnt = 0;
	82	s->rx_head = 0;
	83	s->rx_tail = 0;
	84	}
	85
a8170e5e	86	static void sh_serial_write(void *opaque, hwaddr offs,
9a9d0b81	87	uint64_t val, unsigned size)
2f062c72 TS	88	{
	89	sh_serial_state *s = opaque;
	90	unsigned char ch;
	91
	92	#ifdef DEBUG_SERIAL
8da3ff18	93	printf("sh_serial: write offs=0x%02x val=0x%02x\n",
7d37435b	94	offs, val);
2f062c72 TS	95	#endif
	96	switch(offs) {
	97	case 0x00: /* SMR */
	98	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	99	return;
	100	case 0x04: /* BRR */
	101	s->brr = val;
7d37435b	102	return;
2f062c72	103	case 0x08: /* SCR */
63242a00	104	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	105	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
2f062c72 TS	106	if (!(val & (1 << 5)))
2f062c72 TS	107	s->flags \|= SH_SERIAL_FLAG_TEND;
bf5b7423	108	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
7d37435b	109	qemu_set_irq(s->txi, val & (1 << 7));
bf5b7423	110	}
4e7ed2d1	111	if (!(val & (1 << 6))) {
7d37435b	112	qemu_set_irq(s->rxi, 0);
63242a00	113	}
2f062c72 TS	114	return;
2f062c72 TS	115	case 0x0c: /* FTDR / TDR */
30650701	116	if (qemu_chr_fe_backend_connected(&s->chr)) {
2f062c72	117	ch = val;
6ab3fc32 DB	118	/* XXX this blocks entire thread. Rewrite to use
6ab3fc32 DB	119	* qemu_chr_fe_write and background I/O callbacks */
5345fdb4	120	qemu_chr_fe_write_all(&s->chr, &ch, 1);
7d37435b PB	121	}
	122	s->dr = val;
	123	s->flags &= ~SH_SERIAL_FLAG_TDE;
2f062c72 TS	124	return;
	125	#if 0
	126	case 0x14: /* FRDR / RDR */
	127	ret = 0;
	128	break;
	129	#endif
	130	}
	131	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	132	switch(offs) {
	133	case 0x10: /* FSR */
	134	if (!(val & (1 << 6)))
	135	s->flags &= ~SH_SERIAL_FLAG_TEND;
	136	if (!(val & (1 << 5)))
	137	s->flags &= ~SH_SERIAL_FLAG_TDE;
	138	if (!(val & (1 << 4)))
	139	s->flags &= ~SH_SERIAL_FLAG_BRK;
	140	if (!(val & (1 << 1)))
	141	s->flags &= ~SH_SERIAL_FLAG_RDF;
	142	if (!(val & (1 << 0)))
	143	s->flags &= ~SH_SERIAL_FLAG_DR;
63242a00 AJ	144
63242a00 AJ	145	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
4e7ed2d1 AJ	146	if (s->rxi) {
4e7ed2d1 AJ	147	qemu_set_irq(s->rxi, 0);
63242a00 AJ	148	}
63242a00 AJ	149	}
2f062c72 TS	150	return;
	151	case 0x18: /* FCR */
	152	s->fcr = val;
63242a00 AJ	153	switch ((val >> 6) & 3) {
	154	case 0:
	155	s->rtrg = 1;
	156	break;
	157	case 1:
	158	s->rtrg = 4;
	159	break;
	160	case 2:
	161	s->rtrg = 8;
	162	break;
	163	case 3:
	164	s->rtrg = 14;
	165	break;
	166	}
	167	if (val & (1 << 1)) {
	168	sh_serial_clear_fifo(s);
	169	s->sr &= ~(1 << 1);
	170	}
	171
2f062c72 TS	172	return;
2f062c72 TS	173	case 0x20: /* SPTR */
63242a00	174	s->sptr = val & 0xf3;
2f062c72 TS	175	return;
	176	case 0x24: /* LSR */
	177	return;
	178	}
	179	}
	180	else {
2f062c72	181	switch(offs) {
d1f193b0	182	#if 0
2f062c72 TS	183	case 0x0c:
	184	ret = s->dr;
	185	break;
	186	case 0x10:
	187	ret = 0;
	188	break;
d1f193b0	189	#endif
2f062c72	190	case 0x1c:
d1f193b0 AJ	191	s->sptr = val & 0x8f;
d1f193b0 AJ	192	return;
2f062c72	193	}
2f062c72 TS	194	}
2f062c72 TS	195
c1950a4e	196	fprintf(stderr, "sh_serial: unsupported write to 0x%02"
a8170e5e	197	HWADDR_PRIx "\n", offs);
43dc2a64	198	abort();
2f062c72 TS	199	}
2f062c72 TS	200
a8170e5e	201	static uint64_t sh_serial_read(void *opaque, hwaddr offs,
9a9d0b81	202	unsigned size)
2f062c72 TS	203	{
	204	sh_serial_state *s = opaque;
	205	uint32_t ret = ~0;
	206
	207	#if 0
	208	switch(offs) {
	209	case 0x00:
	210	ret = s->smr;
	211	break;
	212	case 0x04:
	213	ret = s->brr;
7d37435b	214	break;
2f062c72 TS	215	case 0x08:
	216	ret = s->scr;
	217	break;
	218	case 0x14:
	219	ret = 0;
	220	break;
	221	}
	222	#endif
	223	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	224	switch(offs) {
bf5b7423 AJ	225	case 0x00: /* SMR */
	226	ret = s->smr;
	227	break;
	228	case 0x08: /* SCR */
	229	ret = s->scr;
	230	break;
2f062c72 TS	231	case 0x10: /* FSR */
	232	ret = 0;
	233	if (s->flags & SH_SERIAL_FLAG_TEND)
	234	ret \|= (1 << 6);
	235	if (s->flags & SH_SERIAL_FLAG_TDE)
	236	ret \|= (1 << 5);
	237	if (s->flags & SH_SERIAL_FLAG_BRK)
	238	ret \|= (1 << 4);
	239	if (s->flags & SH_SERIAL_FLAG_RDF)
	240	ret \|= (1 << 1);
	241	if (s->flags & SH_SERIAL_FLAG_DR)
	242	ret \|= (1 << 0);
	243
63242a00	244	if (s->scr & (1 << 5))
2f062c72 TS	245	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
2f062c72 TS	246
63242a00 AJ	247	break;
	248	case 0x14:
	249	if (s->rx_cnt > 0) {
	250	ret = s->rx_fifo[s->rx_tail++];
	251	s->rx_cnt--;
	252	if (s->rx_tail == SH_RX_FIFO_LENGTH)
	253	s->rx_tail = 0;
	254	if (s->rx_cnt < s->rtrg)
	255	s->flags &= ~SH_SERIAL_FLAG_RDF;
	256	}
2f062c72	257	break;
2f062c72 TS	258	case 0x18:
	259	ret = s->fcr;
	260	break;
2f062c72 TS	261	case 0x1c:
	262	ret = s->rx_cnt;
	263	break;
	264	case 0x20:
	265	ret = s->sptr;
	266	break;
	267	case 0x24:
	268	ret = 0;
	269	break;
	270	}
	271	}
	272	else {
2f062c72	273	switch(offs) {
d1f193b0	274	#if 0
2f062c72 TS	275	case 0x0c:
	276	ret = s->dr;
	277	break;
	278	case 0x10:
	279	ret = 0;
	280	break;
63242a00 AJ	281	case 0x14:
	282	ret = s->rx_fifo[0];
	283	break;
d1f193b0	284	#endif
2f062c72 TS	285	case 0x1c:
	286	ret = s->sptr;
	287	break;
	288	}
2f062c72 TS	289	}
2f062c72 TS	290	#ifdef DEBUG_SERIAL
8da3ff18	291	printf("sh_serial: read offs=0x%02x val=0x%x\n",
7d37435b	292	offs, ret);
2f062c72 TS	293	#endif
	294
	295	if (ret & ~((1 << 16) - 1)) {
c1950a4e	296	fprintf(stderr, "sh_serial: unsupported read from 0x%02"
a8170e5e	297	HWADDR_PRIx "\n", offs);
43dc2a64	298	abort();
2f062c72 TS	299	}
	300
	301	return ret;
	302	}
	303
	304	static int sh_serial_can_receive(sh_serial_state *s)
	305	{
63242a00	306	return s->scr & (1 << 4);
2f062c72 TS	307	}
2f062c72 TS	308
2f062c72 TS	309	static void sh_serial_receive_break(sh_serial_state *s)
2f062c72 TS	310	{
63242a00 AJ	311	if (s->feat & SH_SERIAL_FEAT_SCIF)
63242a00 AJ	312	s->sr \|= (1 << 4);
2f062c72 TS	313	}
	314
	315	static int sh_serial_can_receive1(void *opaque)
	316	{
	317	sh_serial_state *s = opaque;
	318	return sh_serial_can_receive(s);
	319	}
	320
71bb4ce1 GU	321	static void sh_serial_timeout_int(void *opaque)
	322	{
	323	sh_serial_state *s = opaque;
	324
	325	s->flags \|= SH_SERIAL_FLAG_RDF;
	326	if (s->scr & (1 << 6) && s->rxi) {
	327	qemu_set_irq(s->rxi, 1);
	328	}
	329	}
	330
2f062c72 TS	331	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	332	{
	333	sh_serial_state *s = opaque;
b7d2b020 AJ	334
	335	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	336	int i;
	337	for (i = 0; i < size; i++) {
	338	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	339	s->rx_fifo[s->rx_head++] = buf[i];
	340	if (s->rx_head == SH_RX_FIFO_LENGTH) {
	341	s->rx_head = 0;
	342	}
	343	s->rx_cnt++;
	344	if (s->rx_cnt >= s->rtrg) {
	345	s->flags \|= SH_SERIAL_FLAG_RDF;
	346	if (s->scr & (1 << 6) && s->rxi) {
71bb4ce1	347	timer_del(s->fifo_timeout_timer);
b7d2b020 AJ	348	qemu_set_irq(s->rxi, 1);
b7d2b020 AJ	349	}
71bb4ce1 GU	350	} else {
	351	timer_mod(s->fifo_timeout_timer,
	352	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
b7d2b020 AJ	353	}
	354	}
	355	}
	356	} else {
	357	s->rx_fifo[0] = buf[0];
	358	}
2f062c72 TS	359	}
	360
	361	static void sh_serial_event(void *opaque, int event)
	362	{
	363	sh_serial_state *s = opaque;
	364	if (event == CHR_EVENT_BREAK)
	365	sh_serial_receive_break(s);
	366	}
	367
9a9d0b81 BC	368	static const MemoryRegionOps sh_serial_ops = {
	369	.read = sh_serial_read,
	370	.write = sh_serial_write,
	371	.endianness = DEVICE_NATIVE_ENDIAN,
2f062c72 TS	372	};
2f062c72 TS	373
9a9d0b81	374	void sh_serial_init(MemoryRegion *sysmem,
a8170e5e	375	hwaddr base, int feat,
0ec7b3e7	376	uint32_t freq, Chardev *chr,
9a9d0b81 BC	377	qemu_irq eri_source,
	378	qemu_irq rxi_source,
	379	qemu_irq txi_source,
	380	qemu_irq tei_source,
	381	qemu_irq bri_source)
2f062c72 TS	382	{
2f062c72 TS	383	sh_serial_state *s;
2f062c72	384
7267c094	385	s = g_malloc0(sizeof(sh_serial_state));
2f062c72	386
2f062c72 TS	387	s->feat = feat;
2f062c72 TS	388	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	389	s->rtrg = 1;
2f062c72 TS	390
	391	s->smr = 0;
	392	s->brr = 0xff;
b7d35e65	393	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	394	s->sptr = 0;
	395
	396	if (feat & SH_SERIAL_FEAT_SCIF) {
	397	s->fcr = 0;
	398	}
	399	else {
	400	s->dr = 0xff;
	401	}
	402
63242a00	403	sh_serial_clear_fifo(s);
2f062c72	404
2c9b15ca	405	memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
9a9d0b81 BC	406	"serial", 0x100000000ULL);
9a9d0b81 BC	407
2c9b15ca	408	memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
9a9d0b81 BC	409	0, 0x28);
	410	memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
	411
2c9b15ca	412	memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
9a9d0b81 BC	413	0, 0x28);
9a9d0b81 BC	414	memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
2f062c72	415
456d6069	416	if (chr) {
32a6ebec	417	qemu_chr_fe_init(&s->chr, chr, &error_abort);
5345fdb4 MAL	418	qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
5345fdb4 MAL	419	sh_serial_receive1,
81517ba3	420	sh_serial_event, NULL, s, NULL, true);
456d6069	421	}
bf5b7423	422
71bb4ce1 GU	423	s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
	424	sh_serial_timeout_int, s);
	425	s->etu = NANOSECONDS_PER_SECOND / 9600;
bf5b7423 AJ	426	s->eri = eri_source;
	427	s->rxi = rxi_source;
	428	s->txi = txi_source;
	429	s->tei = tei_source;
	430	s->bri = bri_source;
2f062c72	431	}